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ath9k: serialize ath9k_ps_{wakeup,restore} calls
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
f078f209
LR		 19
20#define ATH_PCI_VERSION "0.1"
21
f078f209
LR		 22static char *dev_info = "ath9k";
23
24MODULE_AUTHOR("Atheros Communications");
25MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27MODULE_LICENSE("Dual BSD/GPL");
28
b3bd89ce
JM		 29static int modparam_nohwcrypt;
30module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
31MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
32
5f8e077c
LR		 33/* We use the hw_value as an index into our private channel structure */
34
35#define CHAN2G(_freq, _idx) { \
36 .center_freq = (_freq), \
37 .hw_value = (_idx), \
eeddfd9d 38 .max_power = 20, \
5f8e077c
LR		 39}
40
41#define CHAN5G(_freq, _idx) { \
42 .band = IEEE80211_BAND_5GHZ, \
43 .center_freq = (_freq), \
44 .hw_value = (_idx), \
eeddfd9d 45 .max_power = 20, \
5f8e077c
LR		 46}
47
48/* Some 2 GHz radios are actually tunable on 2312-2732
49 * on 5 MHz steps, we support the channels which we know
50 * we have calibration data for all cards though to make
51 * this static */
52static struct ieee80211_channel ath9k_2ghz_chantable[] = {
53 CHAN2G(2412, 0), /* Channel 1 */
54 CHAN2G(2417, 1), /* Channel 2 */
55 CHAN2G(2422, 2), /* Channel 3 */
56 CHAN2G(2427, 3), /* Channel 4 */
57 CHAN2G(2432, 4), /* Channel 5 */
58 CHAN2G(2437, 5), /* Channel 6 */
59 CHAN2G(2442, 6), /* Channel 7 */
60 CHAN2G(2447, 7), /* Channel 8 */
61 CHAN2G(2452, 8), /* Channel 9 */
62 CHAN2G(2457, 9), /* Channel 10 */
63 CHAN2G(2462, 10), /* Channel 11 */
64 CHAN2G(2467, 11), /* Channel 12 */
65 CHAN2G(2472, 12), /* Channel 13 */
66 CHAN2G(2484, 13), /* Channel 14 */
67};
68
69/* Some 5 GHz radios are actually tunable on XXXX-YYYY
70 * on 5 MHz steps, we support the channels which we know
71 * we have calibration data for all cards though to make
72 * this static */
73static struct ieee80211_channel ath9k_5ghz_chantable[] = {
74 /* _We_ call this UNII 1 */
75 CHAN5G(5180, 14), /* Channel 36 */
76 CHAN5G(5200, 15), /* Channel 40 */
77 CHAN5G(5220, 16), /* Channel 44 */
78 CHAN5G(5240, 17), /* Channel 48 */
79 /* _We_ call this UNII 2 */
80 CHAN5G(5260, 18), /* Channel 52 */
81 CHAN5G(5280, 19), /* Channel 56 */
82 CHAN5G(5300, 20), /* Channel 60 */
83 CHAN5G(5320, 21), /* Channel 64 */
84 /* _We_ call this "Middle band" */
85 CHAN5G(5500, 22), /* Channel 100 */
86 CHAN5G(5520, 23), /* Channel 104 */
87 CHAN5G(5540, 24), /* Channel 108 */
88 CHAN5G(5560, 25), /* Channel 112 */
89 CHAN5G(5580, 26), /* Channel 116 */
90 CHAN5G(5600, 27), /* Channel 120 */
91 CHAN5G(5620, 28), /* Channel 124 */
92 CHAN5G(5640, 29), /* Channel 128 */
93 CHAN5G(5660, 30), /* Channel 132 */
94 CHAN5G(5680, 31), /* Channel 136 */
95 CHAN5G(5700, 32), /* Channel 140 */
96 /* _We_ call this UNII 3 */
97 CHAN5G(5745, 33), /* Channel 149 */
98 CHAN5G(5765, 34), /* Channel 153 */
99 CHAN5G(5785, 35), /* Channel 157 */
100 CHAN5G(5805, 36), /* Channel 161 */
101 CHAN5G(5825, 37), /* Channel 165 */
102};
103
ce111bad
LR		 104static void ath_cache_conf_rate(struct ath_softc *sc,
105 struct ieee80211_conf *conf)
ff37e337 106{
030bb495
LR		 107 switch (conf->channel->band) {
108 case IEEE80211_BAND_2GHZ:
109 if (conf_is_ht20(conf))
110 sc->cur_rate_table =
111 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
112 else if (conf_is_ht40_minus(conf))
113 sc->cur_rate_table =
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
115 else if (conf_is_ht40_plus(conf))
116 sc->cur_rate_table =
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 118 else
030bb495
LR		 119 sc->cur_rate_table =
120 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 121 break;
122 case IEEE80211_BAND_5GHZ:
123 if (conf_is_ht20(conf))
124 sc->cur_rate_table =
125 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
126 else if (conf_is_ht40_minus(conf))
127 sc->cur_rate_table =
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
129 else if (conf_is_ht40_plus(conf))
130 sc->cur_rate_table =
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
132 else
96742256
LR		 133 sc->cur_rate_table =
134 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 135 break;
136 default:
ce111bad 137 BUG_ON(1);
030bb495
LR		 138 break;
139 }
ff37e337
S		 140}
141
142static void ath_update_txpow(struct ath_softc *sc)
143{
cbe61d8a 144 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 145 u32 txpow;
146
17d7904d
S		 147 if (sc->curtxpow != sc->config.txpowlimit) {
148 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S		 149 /* read back in case value is clamped */
150 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 151 sc->curtxpow = txpow;
ff37e337
S		 152 }
153}
154
155static u8 parse_mpdudensity(u8 mpdudensity)
156{
157 /*
158 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
159 * 0 for no restriction
160 * 1 for 1/4 us
161 * 2 for 1/2 us
162 * 3 for 1 us
163 * 4 for 2 us
164 * 5 for 4 us
165 * 6 for 8 us
166 * 7 for 16 us
167 */
168 switch (mpdudensity) {
169 case 0:
170 return 0;
171 case 1:
172 case 2:
173 case 3:
174 /* Our lower layer calculations limit our precision to
175 1 microsecond */
176 return 1;
177 case 4:
178 return 2;
179 case 5:
180 return 4;
181 case 6:
182 return 8;
183 case 7:
184 return 16;
185 default:
186 return 0;
187 }
188}
189
190static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
191{
4f0fc7c3 192 const struct ath_rate_table *rate_table = NULL;
ff37e337
S		 193 struct ieee80211_supported_band *sband;
194 struct ieee80211_rate *rate;
195 int i, maxrates;
196
197 switch (band) {
198 case IEEE80211_BAND_2GHZ:
199 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
200 break;
201 case IEEE80211_BAND_5GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
203 break;
204 default:
205 break;
206 }
207
208 if (rate_table == NULL)
209 return;
210
211 sband = &sc->sbands[band];
212 rate = sc->rates[band];
213
214 if (rate_table->rate_cnt > ATH_RATE_MAX)
215 maxrates = ATH_RATE_MAX;
216 else
217 maxrates = rate_table->rate_cnt;
218
219 for (i = 0; i < maxrates; i++) {
220 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
221 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 222 if (rate_table->info[i].short_preamble) {
223 rate[i].hw_value_short = rate_table->info[i].ratecode |
224 rate_table->info[i].short_preamble;
225 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
226 }
ff37e337 227 sband->n_bitrates++;
f46730d1 228
04bd4638
S		 229 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
230 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 231 }
232}
233
82880a7c
VT		 234static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
235 struct ieee80211_hw *hw)
236{
237 struct ieee80211_channel *curchan = hw->conf.channel;
238 struct ath9k_channel *channel;
239 u8 chan_idx;
240
241 chan_idx = curchan->hw_value;
242 channel = &sc->sc_ah->channels[chan_idx];
243 ath9k_update_ichannel(sc, hw, channel);
244 return channel;
245}
246
ff37e337
S		 247/*
248 * Set/change channels. If the channel is really being changed, it's done
249 * by reseting the chip. To accomplish this we must first cleanup any pending
250 * DMA, then restart stuff.
251*/
0e2dedf9
JM		 252int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
253 struct ath9k_channel *hchan)
ff37e337 254{
cbe61d8a 255 struct ath_hw *ah = sc->sc_ah;
ff37e337 256 bool fastcc = true, stopped;
ae8d2858
LR		 257 struct ieee80211_channel *channel = hw->conf.channel;
258 int r;
ff37e337
S		 259
260 if (sc->sc_flags & SC_OP_INVALID)
261 return -EIO;
262
3cbb5dd7
VN		 263 ath9k_ps_wakeup(sc);
264
c0d7c7af
LR		 265 /*
266 * This is only performed if the channel settings have
267 * actually changed.
268 *
269 * To switch channels clear any pending DMA operations;
270 * wait long enough for the RX fifo to drain, reset the
271 * hardware at the new frequency, and then re-enable
272 * the relevant bits of the h/w.
273 */
274 ath9k_hw_set_interrupts(ah, 0);
043a0405 275 ath_drain_all_txq(sc, false);
c0d7c7af 276 stopped = ath_stoprecv(sc);
ff37e337 277
c0d7c7af
LR		 278 /* XXX: do not flush receive queue here. We don't want
279 * to flush data frames already in queue because of
280 * changing channel. */
ff37e337 281
c0d7c7af
LR		 282 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
283 fastcc = false;
284
285 DPRINTF(sc, ATH_DBG_CONFIG,
286 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
2660b81a 287 sc->sc_ah->curchan->channel,
c0d7c7af 288 channel->center_freq, sc->tx_chan_width);
ff37e337 289
c0d7c7af
LR		 290 spin_lock_bh(&sc->sc_resetlock);
291
292 r = ath9k_hw_reset(ah, hchan, fastcc);
293 if (r) {
294 DPRINTF(sc, ATH_DBG_FATAL,
295 "Unable to reset channel (%u Mhz) "
6b45784f 296 "reset status %d\n",
c0d7c7af
LR		 297 channel->center_freq, r);
298 spin_unlock_bh(&sc->sc_resetlock);
3989279c 299 goto ps_restore;
ff37e337 300 }
c0d7c7af
LR		 301 spin_unlock_bh(&sc->sc_resetlock);
302
c0d7c7af
LR		 303 sc->sc_flags &= ~SC_OP_FULL_RESET;
304
305 if (ath_startrecv(sc) != 0) {
306 DPRINTF(sc, ATH_DBG_FATAL,
307 "Unable to restart recv logic\n");
3989279c
GJ		 308 r = -EIO;
309 goto ps_restore;
c0d7c7af
LR		 310 }
311
312 ath_cache_conf_rate(sc, &hw->conf);
313 ath_update_txpow(sc);
17d7904d 314 ath9k_hw_set_interrupts(ah, sc->imask);
3989279c
GJ		 315
316 ps_restore:
3cbb5dd7 317 ath9k_ps_restore(sc);
3989279c 318 return r;
ff37e337
S		 319}
320
321/*
322 * This routine performs the periodic noise floor calibration function
323 * that is used to adjust and optimize the chip performance. This
324 * takes environmental changes (location, temperature) into account.
325 * When the task is complete, it reschedules itself depending on the
326 * appropriate interval that was calculated.
327 */
328static void ath_ani_calibrate(unsigned long data)
329{
20977d3e
S		 330 struct ath_softc *sc = (struct ath_softc *)data;
331 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 332 bool longcal = false;
333 bool shortcal = false;
334 bool aniflag = false;
335 unsigned int timestamp = jiffies_to_msecs(jiffies);
20977d3e 336 u32 cal_interval, short_cal_interval;
ff37e337 337
20977d3e
S		 338 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
339 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337
S		 340
341 /*
342 * don't calibrate when we're scanning.
343 * we are most likely not on our home channel.
344 */
e5f0921a 345 spin_lock(&sc->ani_lock);
0c98de65 346 if (sc->sc_flags & SC_OP_SCANNING)
20977d3e 347 goto set_timer;
ff37e337 348
1ffc1c61
JM		 349 /* Only calibrate if awake */
350 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
351 goto set_timer;
352
353 ath9k_ps_wakeup(sc);
354
ff37e337 355 /* Long calibration runs independently of short calibration. */
17d7904d 356 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 357 longcal = true;
04bd4638 358 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
17d7904d 359 sc->ani.longcal_timer = timestamp;
ff37e337
S		 360 }
361
17d7904d
S		 362 /* Short calibration applies only while caldone is false */
363 if (!sc->ani.caldone) {
20977d3e 364 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 365 shortcal = true;
04bd4638 366 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
17d7904d
S		 367 sc->ani.shortcal_timer = timestamp;
368 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 369 }
370 } else {
17d7904d 371 if ((timestamp - sc->ani.resetcal_timer) >=
ff37e337 372 ATH_RESTART_CALINTERVAL) {
17d7904d
S		 373 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
374 if (sc->ani.caldone)
375 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 376 }
377 }
378
379 /* Verify whether we must check ANI */
20977d3e 380 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
ff37e337 381 aniflag = true;
17d7904d 382 sc->ani.checkani_timer = timestamp;
ff37e337
S		 383 }
384
385 /* Skip all processing if there's nothing to do. */
386 if (longcal || shortcal || aniflag) {
387 /* Call ANI routine if necessary */
388 if (aniflag)
20977d3e 389 ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
ff37e337
S		 390
391 /* Perform calibration if necessary */
392 if (longcal || shortcal) {
379f0440
S		 393 sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
394 sc->rx_chainmask, longcal);
395
396 if (longcal)
397 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
398 ah->curchan);
399
400 DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
401 ah->curchan->channel, ah->curchan->channelFlags,
402 sc->ani.noise_floor);
ff37e337
S		 403 }
404 }
405
1ffc1c61
JM		 406 ath9k_ps_restore(sc);
407
20977d3e 408set_timer:
e5f0921a 409 spin_unlock(&sc->ani_lock);
ff37e337
S		 410 /*
411 * Set timer interval based on previous results.
412 * The interval must be the shortest necessary to satisfy ANI,
413 * short calibration and long calibration.
414 */
aac9207e 415 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 416 if (sc->sc_ah->config.enable_ani)
aac9207e 417 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
17d7904d 418 if (!sc->ani.caldone)
20977d3e 419 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 420
17d7904d 421 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S		 422}
423
415f738e
S		 424static void ath_start_ani(struct ath_softc *sc)
425{
426 unsigned long timestamp = jiffies_to_msecs(jiffies);
427
428 sc->ani.longcal_timer = timestamp;
429 sc->ani.shortcal_timer = timestamp;
430 sc->ani.checkani_timer = timestamp;
431
432 mod_timer(&sc->ani.timer,
433 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
434}
435
ff37e337
S		 436/*
437 * Update tx/rx chainmask. For legacy association,
438 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 439 * the chainmask configuration, for bt coexistence, use
440 * the chainmask configuration even in legacy mode.
ff37e337 441 */
0e2dedf9 442void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337 443{
c97c92d9 444 if (is_ht ||
2660b81a
S		 445 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
446 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
447 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
ff37e337 448 } else {
17d7904d
S		 449 sc->tx_chainmask = 1;
450 sc->rx_chainmask = 1;
ff37e337
S		 451 }
452
04bd4638 453 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
17d7904d 454 sc->tx_chainmask, sc->rx_chainmask);
ff37e337
S		 455}
456
457static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
458{
459 struct ath_node *an;
460
461 an = (struct ath_node *)sta->drv_priv;
462
87792efc 463 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 464 ath_tx_node_init(sc, an);
87792efc
S		 465 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
466 sta->ht_cap.ampdu_factor);
467 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
a59b5a5e 468 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
87792efc 469 }
ff37e337
S		 470}
471
472static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
473{
474 struct ath_node *an = (struct ath_node *)sta->drv_priv;
475
476 if (sc->sc_flags & SC_OP_TXAGGR)
477 ath_tx_node_cleanup(sc, an);
478}
479
480static void ath9k_tasklet(unsigned long data)
481{
482 struct ath_softc *sc = (struct ath_softc *)data;
17d7904d 483 u32 status = sc->intrstatus;
ff37e337 484
153e080d
VT		 485 ath9k_ps_wakeup(sc);
486
ff37e337 487 if (status & ATH9K_INT_FATAL) {
ff37e337 488 ath_reset(sc, false);
153e080d 489 ath9k_ps_restore(sc);
ff37e337 490 return;
063d8be3 491 }
ff37e337 492
063d8be3
S		 493 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
494 spin_lock_bh(&sc->rx.rxflushlock);
495 ath_rx_tasklet(sc, 0);
496 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 497 }
498
063d8be3
S		 499 if (status & ATH9K_INT_TX)
500 ath_tx_tasklet(sc);
501
54ce846e
JM		 502 if ((status & ATH9K_INT_TSFOOR) &&
503 (sc->hw->conf.flags & IEEE80211_CONF_PS)) {
504 /*
505 * TSF sync does not look correct; remain awake to sync with
506 * the next Beacon.
507 */
508 DPRINTF(sc, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
ccdfeab6 509 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
54ce846e
JM		 510 }
511
ff37e337 512 /* re-enable hardware interrupt */
17d7904d 513 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
153e080d 514 ath9k_ps_restore(sc);
ff37e337
S		 515}
516
6baff7f9 517irqreturn_t ath_isr(int irq, void *dev)
ff37e337 518{
063d8be3
S		 519#define SCHED_INTR ( \
520 ATH9K_INT_FATAL | \
521 ATH9K_INT_RXORN | \
522 ATH9K_INT_RXEOL | \
523 ATH9K_INT_RX | \
524 ATH9K_INT_TX | \
525 ATH9K_INT_BMISS | \
526 ATH9K_INT_CST | \
527 ATH9K_INT_TSFOOR)
528
ff37e337 529 struct ath_softc *sc = dev;
cbe61d8a 530 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 531 enum ath9k_int status;
532 bool sched = false;
533
063d8be3
S		 534 /*
535 * The hardware is not ready/present, don't
536 * touch anything. Note this can happen early
537 * on if the IRQ is shared.
538 */
539 if (sc->sc_flags & SC_OP_INVALID)
540 return IRQ_NONE;
ff37e337 541
063d8be3
S		 542
543 /* shared irq, not for us */
544
153e080d 545 if (!ath9k_hw_intrpend(ah))
063d8be3 546 return IRQ_NONE;
063d8be3
S		 547
548 /*
549 * Figure out the reason(s) for the interrupt. Note
550 * that the hal returns a pseudo-ISR that may include
551 * bits we haven't explicitly enabled so we mask the
552 * value to insure we only process bits we requested.
553 */
554 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
555 status &= sc->imask; /* discard unasked-for bits */
ff37e337 556
063d8be3
S		 557 /*
558 * If there are no status bits set, then this interrupt was not
559 * for me (should have been caught above).
560 */
153e080d 561 if (!status)
063d8be3 562 return IRQ_NONE;
ff37e337 563
063d8be3
S		 564 /* Cache the status */
565 sc->intrstatus = status;
566
567 if (status & SCHED_INTR)
568 sched = true;
569
570 /*
571 * If a FATAL or RXORN interrupt is received, we have to reset the
572 * chip immediately.
573 */
574 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
575 goto chip_reset;
576
577 if (status & ATH9K_INT_SWBA)
578 tasklet_schedule(&sc->bcon_tasklet);
579
580 if (status & ATH9K_INT_TXURN)
581 ath9k_hw_updatetxtriglevel(ah, true);
582
583 if (status & ATH9K_INT_MIB) {
ff37e337 584 /*
063d8be3
S		 585 * Disable interrupts until we service the MIB
586 * interrupt; otherwise it will continue to
587 * fire.
ff37e337 588 */
063d8be3
S		 589 ath9k_hw_set_interrupts(ah, 0);
590 /*
591 * Let the hal handle the event. We assume
592 * it will clear whatever condition caused
593 * the interrupt.
594 */
595 ath9k_hw_procmibevent(ah, &sc->nodestats);
596 ath9k_hw_set_interrupts(ah, sc->imask);
597 }
ff37e337 598
153e080d
VT		 599 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
600 if (status & ATH9K_INT_TIM_TIMER) {
063d8be3
S		 601 /* Clear RxAbort bit so that we can
602 * receive frames */
603 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
153e080d 604 ath9k_hw_setrxabort(sc->sc_ah, 0);
063d8be3 605 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337 606 }
063d8be3
S		 607
608chip_reset:
ff37e337 609
817e11de
S		 610 ath_debug_stat_interrupt(sc, status);
611
ff37e337
S		 612 if (sched) {
613 /* turn off every interrupt except SWBA */
17d7904d 614 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S		 615 tasklet_schedule(&sc->intr_tq);
616 }
617
618 return IRQ_HANDLED;
063d8be3
S		 619
620#undef SCHED_INTR
ff37e337
S		 621}
622
f078f209 623static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 624 struct ieee80211_channel *chan,
094d05dc 625 enum nl80211_channel_type channel_type)
f078f209
LR		 626{
627 u32 chanmode = 0;
f078f209
LR		 628
629 switch (chan->band) {
630 case IEEE80211_BAND_2GHZ:
094d05dc
S		 631 switch(channel_type) {
632 case NL80211_CHAN_NO_HT:
633 case NL80211_CHAN_HT20:
f078f209 634 chanmode = CHANNEL_G_HT20;
094d05dc
S		 635 break;
636 case NL80211_CHAN_HT40PLUS:
f078f209 637 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 638 break;
639 case NL80211_CHAN_HT40MINUS:
f078f209 640 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 641 break;
642 }
f078f209
LR		 643 break;
644 case IEEE80211_BAND_5GHZ:
094d05dc
S		 645 switch(channel_type) {
646 case NL80211_CHAN_NO_HT:
647 case NL80211_CHAN_HT20:
f078f209 648 chanmode = CHANNEL_A_HT20;
094d05dc
S		 649 break;
650 case NL80211_CHAN_HT40PLUS:
f078f209 651 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 652 break;
653 case NL80211_CHAN_HT40MINUS:
f078f209 654 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 655 break;
656 }
f078f209
LR		 657 break;
658 default:
659 break;
660 }
661
662 return chanmode;
663}
664
6ace2891 665static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
3f53dd64
JM		 666 struct ath9k_keyval *hk, const u8 *addr,
667 bool authenticator)
f078f209 668{
6ace2891
JM		 669 const u8 *key_rxmic;
670 const u8 *key_txmic;
f078f209 671
6ace2891
JM		 672 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
673 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 674
675 if (addr == NULL) {
d216aaa6
JM		 676 /*
677 * Group key installation - only two key cache entries are used
678 * regardless of splitmic capability since group key is only
679 * used either for TX or RX.
680 */
3f53dd64
JM		 681 if (authenticator) {
682 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
683 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
684 } else {
685 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
686 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
687 }
d216aaa6 688 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 689 }
17d7904d 690 if (!sc->splitmic) {
d216aaa6 691 /* TX and RX keys share the same key cache entry. */
f078f209
LR		 692 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
693 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
d216aaa6 694 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 695 }
d216aaa6
JM		 696
697 /* Separate key cache entries for TX and RX */
698
699 /* TX key goes at first index, RX key at +32. */
f078f209 700 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
d216aaa6
JM		 701 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
702 /* TX MIC entry failed. No need to proceed further */
d8baa939 703 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 704 "Setting TX MIC Key Failed\n");
f078f209
LR		 705 return 0;
706 }
707
708 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
709 /* XXX delete tx key on failure? */
d216aaa6 710 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
6ace2891
JM		 711}
712
713static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
714{
715 int i;
716
17d7904d
S		 717 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
718 if (test_bit(i, sc->keymap) ||
719 test_bit(i + 64, sc->keymap))
6ace2891 720 continue; /* At least one part of TKIP key allocated */
17d7904d
S		 721 if (sc->splitmic &&
722 (test_bit(i + 32, sc->keymap) ||
723 test_bit(i + 64 + 32, sc->keymap)))
6ace2891
JM		 724 continue; /* At least one part of TKIP key allocated */
725
726 /* Found a free slot for a TKIP key */
727 return i;
728 }
729 return -1;
730}
731
732static int ath_reserve_key_cache_slot(struct ath_softc *sc)
733{
734 int i;
735
736 /* First, try to find slots that would not be available for TKIP. */
17d7904d
S		 737 if (sc->splitmic) {
738 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
739 if (!test_bit(i, sc->keymap) &&
740 (test_bit(i + 32, sc->keymap) ||
741 test_bit(i + 64, sc->keymap) ||
742 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 743 return i;
17d7904d
S		 744 if (!test_bit(i + 32, sc->keymap) &&
745 (test_bit(i, sc->keymap) ||
746 test_bit(i + 64, sc->keymap) ||
747 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 748 return i + 32;
17d7904d
S		 749 if (!test_bit(i + 64, sc->keymap) &&
750 (test_bit(i , sc->keymap) ||
751 test_bit(i + 32, sc->keymap) ||
752 test_bit(i + 64 + 32, sc->keymap)))
ea612132 753 return i + 64;
17d7904d
S		 754 if (!test_bit(i + 64 + 32, sc->keymap) &&
755 (test_bit(i, sc->keymap) ||
756 test_bit(i + 32, sc->keymap) ||
757 test_bit(i + 64, sc->keymap)))
ea612132 758 return i + 64 + 32;
6ace2891
JM		 759 }
760 } else {
17d7904d
S		 761 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
762 if (!test_bit(i, sc->keymap) &&
763 test_bit(i + 64, sc->keymap))
6ace2891 764 return i;
17d7904d
S		 765 if (test_bit(i, sc->keymap) &&
766 !test_bit(i + 64, sc->keymap))
6ace2891
JM		 767 return i + 64;
768 }
769 }
770
771 /* No partially used TKIP slots, pick any available slot */
17d7904d 772 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
be2864cf
JM		 773 /* Do not allow slots that could be needed for TKIP group keys
774 * to be used. This limitation could be removed if we know that
775 * TKIP will not be used. */
776 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
777 continue;
17d7904d 778 if (sc->splitmic) {
be2864cf
JM		 779 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
780 continue;
781 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
782 continue;
783 }
784
17d7904d 785 if (!test_bit(i, sc->keymap))
6ace2891
JM		 786 return i; /* Found a free slot for a key */
787 }
788
789 /* No free slot found */
790 return -1;
f078f209
LR		 791}
792
793static int ath_key_config(struct ath_softc *sc,
3f53dd64 794 struct ieee80211_vif *vif,
dc822b5d 795 struct ieee80211_sta *sta,
f078f209
LR		 796 struct ieee80211_key_conf *key)
797{
f078f209
LR		 798 struct ath9k_keyval hk;
799 const u8 *mac = NULL;
800 int ret = 0;
6ace2891 801 int idx;
f078f209
LR		 802
803 memset(&hk, 0, sizeof(hk));
804
805 switch (key->alg) {
806 case ALG_WEP:
807 hk.kv_type = ATH9K_CIPHER_WEP;
808 break;
809 case ALG_TKIP:
810 hk.kv_type = ATH9K_CIPHER_TKIP;
811 break;
812 case ALG_CCMP:
813 hk.kv_type = ATH9K_CIPHER_AES_CCM;
814 break;
815 default:
ca470b29 816 return -EOPNOTSUPP;
f078f209
LR		 817 }
818
6ace2891 819 hk.kv_len = key->keylen;
f078f209
LR		 820 memcpy(hk.kv_val, key->key, key->keylen);
821
6ace2891
JM		 822 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
823 /* For now, use the default keys for broadcast keys. This may
824 * need to change with virtual interfaces. */
825 idx = key->keyidx;
826 } else if (key->keyidx) {
dc822b5d
JB		 827 if (WARN_ON(!sta))
828 return -EOPNOTSUPP;
829 mac = sta->addr;
830
6ace2891
JM		 831 if (vif->type != NL80211_IFTYPE_AP) {
832 /* Only keyidx 0 should be used with unicast key, but
833 * allow this for client mode for now. */
834 idx = key->keyidx;
835 } else
836 return -EIO;
f078f209 837 } else {
dc822b5d
JB		 838 if (WARN_ON(!sta))
839 return -EOPNOTSUPP;
840 mac = sta->addr;
841
6ace2891
JM		 842 if (key->alg == ALG_TKIP)
843 idx = ath_reserve_key_cache_slot_tkip(sc);
844 else
845 idx = ath_reserve_key_cache_slot(sc);
846 if (idx < 0)
ca470b29 847 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 848 }
849
850 if (key->alg == ALG_TKIP)
3f53dd64
JM		 851 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
852 vif->type == NL80211_IFTYPE_AP);
f078f209 853 else
d216aaa6 854 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
f078f209
LR		 855
856 if (!ret)
857 return -EIO;
858
17d7904d 859 set_bit(idx, sc->keymap);
6ace2891 860 if (key->alg == ALG_TKIP) {
17d7904d
S		 861 set_bit(idx + 64, sc->keymap);
862 if (sc->splitmic) {
863 set_bit(idx + 32, sc->keymap);
864 set_bit(idx + 64 + 32, sc->keymap);
6ace2891
JM		 865 }
866 }
867
868 return idx;
f078f209
LR		 869}
870
871static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
872{
6ace2891
JM		 873 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
874 if (key->hw_key_idx < IEEE80211_WEP_NKID)
875 return;
876
17d7904d 877 clear_bit(key->hw_key_idx, sc->keymap);
6ace2891
JM		 878 if (key->alg != ALG_TKIP)
879 return;
f078f209 880
17d7904d
S		 881 clear_bit(key->hw_key_idx + 64, sc->keymap);
882 if (sc->splitmic) {
883 clear_bit(key->hw_key_idx + 32, sc->keymap);
884 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
6ace2891 885 }
f078f209
LR		 886}
887
eb2599ca
S		 888static void setup_ht_cap(struct ath_softc *sc,
889 struct ieee80211_sta_ht_cap *ht_info)
f078f209 890{
60653678
S		 891#define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
892#define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
140add21 893 u8 tx_streams, rx_streams;
f078f209 894
d9fe60de
JB		 895 ht_info->ht_supported = true;
896 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
897 IEEE80211_HT_CAP_SM_PS |
898 IEEE80211_HT_CAP_SGI_40 |
899 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 900
60653678
S		 901 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
902 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
eb2599ca 903
d9fe60de
JB		 904 /* set up supported mcs set */
905 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
140add21
SB		 906 tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2;
907 rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;
908
909 if (tx_streams != rx_streams) {
910 DPRINTF(sc, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n",
911 tx_streams, rx_streams);
912 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
913 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
914 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
915 }
eb2599ca 916
140add21
SB		 917 ht_info->mcs.rx_mask[0] = 0xff;
918 if (rx_streams >= 2)
eb2599ca 919 ht_info->mcs.rx_mask[1] = 0xff;
eb2599ca 920
140add21 921 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 922}
923
8feceb67 924static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 925 struct ieee80211_vif *vif,
8feceb67 926 struct ieee80211_bss_conf *bss_conf)
f078f209 927{
f078f209 928
8feceb67 929 if (bss_conf->assoc) {
094d05dc 930 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
17d7904d 931 bss_conf->aid, sc->curbssid);
f078f209 932
8feceb67 933 /* New association, store aid */
2664f201
SB		 934 sc->curaid = bss_conf->aid;
935 ath9k_hw_write_associd(sc);
936
937 /*
938 * Request a re-configuration of Beacon related timers
939 * on the receipt of the first Beacon frame (i.e.,
940 * after time sync with the AP).
941 */
942 sc->sc_flags |= SC_OP_BEACON_SYNC;
f078f209 943
8feceb67 944 /* Configure the beacon */
2c3db3d5 945 ath_beacon_config(sc, vif);
f078f209 946
8feceb67 947 /* Reset rssi stats */
17d7904d
S		 948 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
949 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
950 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
951 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 952
415f738e 953 ath_start_ani(sc);
8feceb67 954 } else {
1ffb0610 955 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
17d7904d 956 sc->curaid = 0;
f38faa31
SB		 957 /* Stop ANI */
958 del_timer_sync(&sc->ani.timer);
f078f209 959 }
8feceb67 960}
f078f209 961
8feceb67
VT		 962/********************************/
963/* LED functions */
964/********************************/
f078f209 965
f2bffa7e
VT		 966static void ath_led_blink_work(struct work_struct *work)
967{
968 struct ath_softc *sc = container_of(work, struct ath_softc,
969 ath_led_blink_work.work);
970
971 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
972 return;
85067c06
VT		 973
974 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
975 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
976 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
977 else
978 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
979 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
f2bffa7e
VT		 980
981 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
982 (sc->sc_flags & SC_OP_LED_ON) ?
983 msecs_to_jiffies(sc->led_off_duration) :
984 msecs_to_jiffies(sc->led_on_duration));
985
85067c06
VT		 986 sc->led_on_duration = sc->led_on_cnt ?
987 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
988 ATH_LED_ON_DURATION_IDLE;
989 sc->led_off_duration = sc->led_off_cnt ?
990 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
991 ATH_LED_OFF_DURATION_IDLE;
f2bffa7e
VT		 992 sc->led_on_cnt = sc->led_off_cnt = 0;
993 if (sc->sc_flags & SC_OP_LED_ON)
994 sc->sc_flags &= ~SC_OP_LED_ON;
995 else
996 sc->sc_flags |= SC_OP_LED_ON;
997}
998
8feceb67
VT		 999static void ath_led_brightness(struct led_classdev *led_cdev,
1000 enum led_brightness brightness)
1001{
1002 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1003 struct ath_softc *sc = led->sc;
f078f209 1004
8feceb67
VT		 1005 switch (brightness) {
1006 case LED_OFF:
1007 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e
VT		 1008 led->led_type == ATH_LED_RADIO) {
1009 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
1010 (led->led_type == ATH_LED_RADIO));
8feceb67 1011 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 1012 if (led->led_type == ATH_LED_RADIO)
1013 sc->sc_flags &= ~SC_OP_LED_ON;
1014 } else {
1015 sc->led_off_cnt++;
1016 }
8feceb67
VT		 1017 break;
1018 case LED_FULL:
f2bffa7e 1019 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 1020 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 1021 queue_delayed_work(sc->hw->workqueue,
1022 &sc->ath_led_blink_work, 0);
1023 } else if (led->led_type == ATH_LED_RADIO) {
1024 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
1025 sc->sc_flags |= SC_OP_LED_ON;
1026 } else {
1027 sc->led_on_cnt++;
1028 }
8feceb67
VT		 1029 break;
1030 default:
1031 break;
f078f209 1032 }
8feceb67 1033}
f078f209 1034
8feceb67
VT		 1035static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1036 char *trigger)
1037{
1038 int ret;
f078f209 1039
8feceb67
VT		 1040 led->sc = sc;
1041 led->led_cdev.name = led->name;
1042 led->led_cdev.default_trigger = trigger;
1043 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 1044
8feceb67
VT		 1045 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1046 if (ret)
1047 DPRINTF(sc, ATH_DBG_FATAL,
1048 "Failed to register led:%s", led->name);
1049 else
1050 led->registered = 1;
1051 return ret;
1052}
f078f209 1053
8feceb67
VT		 1054static void ath_unregister_led(struct ath_led *led)
1055{
1056 if (led->registered) {
1057 led_classdev_unregister(&led->led_cdev);
1058 led->registered = 0;
f078f209 1059 }
f078f209
LR		 1060}
1061
8feceb67 1062static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1063{
f2bffa7e 1064 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67
VT		 1065 ath_unregister_led(&sc->assoc_led);
1066 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1067 ath_unregister_led(&sc->tx_led);
1068 ath_unregister_led(&sc->rx_led);
1069 ath_unregister_led(&sc->radio_led);
1070 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1071}
f078f209 1072
8feceb67
VT		 1073static void ath_init_leds(struct ath_softc *sc)
1074{
1075 char *trigger;
1076 int ret;
f078f209 1077
8feceb67
VT		 1078 /* Configure gpio 1 for output */
1079 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1080 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1081 /* LED off, active low */
1082 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 1083
f2bffa7e
VT		 1084 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1085
8feceb67
VT		 1086 trigger = ieee80211_get_radio_led_name(sc->hw);
1087 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
0818cb8a 1088 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1089 ret = ath_register_led(sc, &sc->radio_led, trigger);
1090 sc->radio_led.led_type = ATH_LED_RADIO;
1091 if (ret)
1092 goto fail;
7dcfdcd9 1093
8feceb67
VT		 1094 trigger = ieee80211_get_assoc_led_name(sc->hw);
1095 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
0818cb8a 1096 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1097 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1098 sc->assoc_led.led_type = ATH_LED_ASSOC;
1099 if (ret)
1100 goto fail;
f078f209 1101
8feceb67
VT		 1102 trigger = ieee80211_get_tx_led_name(sc->hw);
1103 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
0818cb8a 1104 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1105 ret = ath_register_led(sc, &sc->tx_led, trigger);
1106 sc->tx_led.led_type = ATH_LED_TX;
1107 if (ret)
1108 goto fail;
f078f209 1109
8feceb67
VT		 1110 trigger = ieee80211_get_rx_led_name(sc->hw);
1111 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
0818cb8a 1112 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1113 ret = ath_register_led(sc, &sc->rx_led, trigger);
1114 sc->rx_led.led_type = ATH_LED_RX;
1115 if (ret)
1116 goto fail;
f078f209 1117
8feceb67
VT		 1118 return;
1119
1120fail:
1121 ath_deinit_leds(sc);
f078f209
LR		 1122}
1123
7ec3e514 1124void ath_radio_enable(struct ath_softc *sc)
500c064d 1125{
cbe61d8a 1126 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1127 struct ieee80211_channel *channel = sc->hw->conf.channel;
1128 int r;
500c064d 1129
3cbb5dd7 1130 ath9k_ps_wakeup(sc);
d2f5b3a6 1131 ath9k_hw_configpcipowersave(ah, 0);
ae8d2858 1132
159cd468
VT		 1133 if (!ah->curchan)
1134 ah->curchan = ath_get_curchannel(sc, sc->hw);
1135
d2f5b3a6 1136 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1137 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1138 if (r) {
500c064d 1139 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1140 "Unable to reset channel %u (%uMhz) ",
6b45784f 1141 "reset status %d\n",
ae8d2858 1142 channel->center_freq, r);
500c064d
VT		 1143 }
1144 spin_unlock_bh(&sc->sc_resetlock);
1145
1146 ath_update_txpow(sc);
1147 if (ath_startrecv(sc) != 0) {
1148 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1149 "Unable to restart recv logic\n");
500c064d
VT		 1150 return;
1151 }
1152
1153 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1154 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT		 1155
1156 /* Re-Enable interrupts */
17d7904d 1157 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT		 1158
1159 /* Enable LED */
1160 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1161 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1162 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1163
1164 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1165 ath9k_ps_restore(sc);
500c064d
VT		 1166}
1167
7ec3e514 1168void ath_radio_disable(struct ath_softc *sc)
500c064d 1169{
cbe61d8a 1170 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1171 struct ieee80211_channel *channel = sc->hw->conf.channel;
1172 int r;
500c064d 1173
3cbb5dd7 1174 ath9k_ps_wakeup(sc);
500c064d
VT		 1175 ieee80211_stop_queues(sc->hw);
1176
1177 /* Disable LED */
1178 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1179 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1180
1181 /* Disable interrupts */
1182 ath9k_hw_set_interrupts(ah, 0);
1183
043a0405 1184 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1185 ath_stoprecv(sc); /* turn off frame recv */
1186 ath_flushrecv(sc); /* flush recv queue */
1187
159cd468
VT		 1188 if (!ah->curchan)
1189 ah->curchan = ath_get_curchannel(sc, sc->hw);
1190
500c064d 1191 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1192 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1193 if (r) {
500c064d 1194 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1195 "Unable to reset channel %u (%uMhz) "
6b45784f 1196 "reset status %d\n",
ae8d2858 1197 channel->center_freq, r);
500c064d
VT		 1198 }
1199 spin_unlock_bh(&sc->sc_resetlock);
1200
1201 ath9k_hw_phy_disable(ah);
d2f5b3a6 1202 ath9k_hw_configpcipowersave(ah, 1);
3cbb5dd7 1203 ath9k_ps_restore(sc);
38ab422e 1204 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
500c064d
VT		 1205}
1206
5077fd35
GJ		 1207/*******************/
1208/* Rfkill */
1209/*******************/
1210
500c064d
VT		 1211static bool ath_is_rfkill_set(struct ath_softc *sc)
1212{
cbe61d8a 1213 struct ath_hw *ah = sc->sc_ah;
500c064d 1214
2660b81a
S		 1215 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1216 ah->rfkill_polarity;
500c064d
VT		 1217}
1218
3b319aae 1219static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
500c064d 1220{
3b319aae
JB		 1221 struct ath_wiphy *aphy = hw->priv;
1222 struct ath_softc *sc = aphy->sc;
19d337df 1223 bool blocked = !!ath_is_rfkill_set(sc);
500c064d 1224
3b319aae
JB		 1225 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1226
1227 if (blocked)
19d337df
JB		 1228 ath_radio_disable(sc);
1229 else
1230 ath_radio_enable(sc);
500c064d
VT		 1231}
1232
3b319aae 1233static void ath_start_rfkill_poll(struct ath_softc *sc)
500c064d 1234{
3b319aae 1235 struct ath_hw *ah = sc->sc_ah;
9c84b797 1236
3b319aae
JB		 1237 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1238 wiphy_rfkill_start_polling(sc->hw->wiphy);
9c84b797 1239}
500c064d 1240
6baff7f9 1241void ath_cleanup(struct ath_softc *sc)
39c3c2f2
GJ		 1242{
1243 ath_detach(sc);
1244 free_irq(sc->irq, sc);
1245 ath_bus_cleanup(sc);
c52f33d0 1246 kfree(sc->sec_wiphy);
39c3c2f2
GJ		 1247 ieee80211_free_hw(sc->hw);
1248}
1249
6baff7f9 1250void ath_detach(struct ath_softc *sc)
f078f209 1251{
8feceb67 1252 struct ieee80211_hw *hw = sc->hw;
9c84b797 1253 int i = 0;
f078f209 1254
3cbb5dd7
VN		 1255 ath9k_ps_wakeup(sc);
1256
04bd4638 1257 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1258
3fcdfb4b 1259 ath_deinit_leds(sc);
0e2dedf9 1260 cancel_work_sync(&sc->chan_work);
f98c3bd2 1261 cancel_delayed_work_sync(&sc->wiphy_work);
164ace38 1262 cancel_delayed_work_sync(&sc->tx_complete_work);
3fcdfb4b 1263
c52f33d0
JM		 1264 for (i = 0; i < sc->num_sec_wiphy; i++) {
1265 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1266 if (aphy == NULL)
1267 continue;
1268 sc->sec_wiphy[i] = NULL;
1269 ieee80211_unregister_hw(aphy->hw);
1270 ieee80211_free_hw(aphy->hw);
1271 }
3fcdfb4b 1272 ieee80211_unregister_hw(hw);
8feceb67
VT		 1273 ath_rx_cleanup(sc);
1274 ath_tx_cleanup(sc);
f078f209 1275
9c84b797
S		 1276 tasklet_kill(&sc->intr_tq);
1277 tasklet_kill(&sc->bcon_tasklet);
f078f209 1278
9c84b797
S		 1279 if (!(sc->sc_flags & SC_OP_INVALID))
1280 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1281
9c84b797
S		 1282 /* cleanup tx queues */
1283 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1284 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1285 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797
S		 1286
1287 ath9k_hw_detach(sc->sc_ah);
826d2680 1288 ath9k_exit_debug(sc);
f078f209
LR		 1289}
1290
e3bb249b
BC		 1291static int ath9k_reg_notifier(struct wiphy *wiphy,
1292 struct regulatory_request *request)
1293{
1294 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1295 struct ath_wiphy *aphy = hw->priv;
1296 struct ath_softc *sc = aphy->sc;
1297 struct ath_regulatory *reg = &sc->sc_ah->regulatory;
1298
1299 return ath_reg_notifier_apply(wiphy, request, reg);
1300}
1301
ff37e337
S		 1302static int ath_init(u16 devid, struct ath_softc *sc)
1303{
cbe61d8a 1304 struct ath_hw *ah = NULL;
ff37e337
S		 1305 int status;
1306 int error = 0, i;
1307 int csz = 0;
1308
1309 /* XXX: hardware will not be ready until ath_open() being called */
1310 sc->sc_flags |= SC_OP_INVALID;
88b126af 1311
826d2680
S		 1312 if (ath9k_init_debug(sc) < 0)
1313 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337 1314
c52f33d0 1315 spin_lock_init(&sc->wiphy_lock);
ff37e337 1316 spin_lock_init(&sc->sc_resetlock);
6158425b 1317 spin_lock_init(&sc->sc_serial_rw);
e5f0921a 1318 spin_lock_init(&sc->ani_lock);
04717ccd 1319 spin_lock_init(&sc->sc_pm_lock);
aa33de09 1320 mutex_init(&sc->mutex);
ff37e337 1321 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
9fc9ab0a 1322 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
ff37e337
S		 1323 (unsigned long)sc);
1324
1325 /*
1326 * Cache line size is used to size and align various
1327 * structures used to communicate with the hardware.
1328 */
88d15707 1329 ath_read_cachesize(sc, &csz);
ff37e337 1330 /* XXX assert csz is non-zero */
17d7904d 1331 sc->cachelsz = csz << 2; /* convert to bytes */
ff37e337 1332
cbe61d8a 1333 ah = ath9k_hw_attach(devid, sc, &status);
ff37e337
S		 1334 if (ah == NULL) {
1335 DPRINTF(sc, ATH_DBG_FATAL,
295834fe 1336 "Unable to attach hardware; HAL status %d\n", status);
ff37e337
S		 1337 error = -ENXIO;
1338 goto bad;
1339 }
1340 sc->sc_ah = ah;
1341
1342 /* Get the hardware key cache size. */
2660b81a 1343 sc->keymax = ah->caps.keycache_size;
17d7904d 1344 if (sc->keymax > ATH_KEYMAX) {
d8baa939 1345 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 1346 "Warning, using only %u entries in %u key cache\n",
17d7904d
S		 1347 ATH_KEYMAX, sc->keymax);
1348 sc->keymax = ATH_KEYMAX;
ff37e337
S		 1349 }
1350
1351 /*
1352 * Reset the key cache since some parts do not
1353 * reset the contents on initial power up.
1354 */
17d7904d 1355 for (i = 0; i < sc->keymax; i++)
ff37e337 1356 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1357
85efc86e 1358 if (error)
ff37e337
S		 1359 goto bad;
1360
1361 /* default to MONITOR mode */
2660b81a 1362 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
d97809db 1363
ff37e337
S		 1364 /* Setup rate tables */
1365
1366 ath_rate_attach(sc);
1367 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1368 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1369
1370 /*
1371 * Allocate hardware transmit queues: one queue for
1372 * beacon frames and one data queue for each QoS
1373 * priority. Note that the hal handles reseting
1374 * these queues at the needed time.
1375 */
b77f483f
S		 1376 sc->beacon.beaconq = ath_beaconq_setup(ah);
1377 if (sc->beacon.beaconq == -1) {
ff37e337 1378 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1379 "Unable to setup a beacon xmit queue\n");
ff37e337
S		 1380 error = -EIO;
1381 goto bad2;
1382 }
b77f483f
S		 1383 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1384 if (sc->beacon.cabq == NULL) {
ff37e337 1385 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1386 "Unable to setup CAB xmit queue\n");
ff37e337
S		 1387 error = -EIO;
1388 goto bad2;
1389 }
1390
17d7904d 1391 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
ff37e337
S		 1392 ath_cabq_update(sc);
1393
b77f483f
S		 1394 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1395 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1396
1397 /* Setup data queues */
1398 /* NB: ensure BK queue is the lowest priority h/w queue */
1399 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1400 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1401 "Unable to setup xmit queue for BK traffic\n");
ff37e337
S		 1402 error = -EIO;
1403 goto bad2;
1404 }
1405
1406 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1407 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1408 "Unable to setup xmit queue for BE traffic\n");
ff37e337
S		 1409 error = -EIO;
1410 goto bad2;
1411 }
1412 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1413 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1414 "Unable to setup xmit queue for VI traffic\n");
ff37e337
S		 1415 error = -EIO;
1416 goto bad2;
1417 }
1418 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1419 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1420 "Unable to setup xmit queue for VO traffic\n");
ff37e337
S		 1421 error = -EIO;
1422 goto bad2;
1423 }
1424
1425 /* Initializes the noise floor to a reasonable default value.
1426 * Later on this will be updated during ANI processing. */
1427
17d7904d
S		 1428 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1429 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
ff37e337
S		 1430
1431 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1432 ATH9K_CIPHER_TKIP, NULL)) {
1433 /*
1434 * Whether we should enable h/w TKIP MIC.
1435 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1436 * report WMM capable, so it's always safe to turn on
1437 * TKIP MIC in this case.
1438 */
1439 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1440 0, 1, NULL);
1441 }
1442
1443 /*
1444 * Check whether the separate key cache entries
1445 * are required to handle both tx+rx MIC keys.
1446 * With split mic keys the number of stations is limited
1447 * to 27 otherwise 59.
1448 */
1449 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1450 ATH9K_CIPHER_TKIP, NULL)
1451 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1452 ATH9K_CIPHER_MIC, NULL)
1453 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1454 0, NULL))
17d7904d 1455 sc->splitmic = 1;
ff37e337
S		 1456
1457 /* turn on mcast key search if possible */
1458 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1459 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1460 1, NULL);
1461
17d7904d 1462 sc->config.txpowlimit = ATH_TXPOWER_MAX;
ff37e337
S		 1463
1464 /* 11n Capabilities */
2660b81a 1465 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337
S		 1466 sc->sc_flags |= SC_OP_TXAGGR;
1467 sc->sc_flags |= SC_OP_RXAGGR;
1468 }
1469
2660b81a
S		 1470 sc->tx_chainmask = ah->caps.tx_chainmask;
1471 sc->rx_chainmask = ah->caps.rx_chainmask;
ff37e337
S		 1472
1473 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1474 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337 1475
8ca21f01 1476 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
ba52da58 1477 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
ff37e337 1478
b77f483f 1479 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1480
1481 /* initialize beacon slots */
c52f33d0 1482 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2c3db3d5 1483 sc->beacon.bslot[i] = NULL;
c52f33d0
JM		 1484 sc->beacon.bslot_aphy[i] = NULL;
1485 }
ff37e337 1486
ff37e337
S		 1487 /* setup channels and rates */
1488
5f8e077c 1489 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1490 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1491 sc->rates[IEEE80211_BAND_2GHZ];
1492 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1493 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1494 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337 1495
2660b81a 1496 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
5f8e077c 1497 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1498 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1499 sc->rates[IEEE80211_BAND_5GHZ];
1500 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1501 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1502 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1503 }
1504
2660b81a 1505 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
c97c92d9
VT		 1506 ath9k_hw_btcoex_enable(sc->sc_ah);
1507
ff37e337
S		 1508 return 0;
1509bad2:
1510 /* cleanup tx queues */
1511 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1512 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1513 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337
S		 1514bad:
1515 if (ah)
1516 ath9k_hw_detach(ah);
40b130a9 1517 ath9k_exit_debug(sc);
ff37e337
S		 1518
1519 return error;
1520}
1521
c52f33d0 1522void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
f078f209 1523{
9c84b797
S		 1524 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1525 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1526 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1527 IEEE80211_HW_AMPDU_AGGREGATION |
1528 IEEE80211_HW_SUPPORTS_PS |
eeee1320
S		 1529 IEEE80211_HW_PS_NULLFUNC_STACK |
1530 IEEE80211_HW_SPECTRUM_MGMT;
f078f209 1531
b3bd89ce 1532 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
0ced0e17
JM		 1533 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1534
9c84b797
S		 1535 hw->wiphy->interface_modes =
1536 BIT(NL80211_IFTYPE_AP) |
1537 BIT(NL80211_IFTYPE_STATION) |
9cb5412b
PE		 1538 BIT(NL80211_IFTYPE_ADHOC) |
1539 BIT(NL80211_IFTYPE_MESH_POINT);
f078f209 1540
8feceb67 1541 hw->queues = 4;
e63835b0 1542 hw->max_rates = 4;
171387ef 1543 hw->channel_change_time = 5000;
465ca84d 1544 hw->max_listen_interval = 10;
dd190183
LR		 1545 /* Hardware supports 10 but we use 4 */
1546 hw->max_rate_tries = 4;
528f0c6b 1547 hw->sta_data_size = sizeof(struct ath_node);
17d7904d 1548 hw->vif_data_size = sizeof(struct ath_vif);
f078f209 1549
8feceb67 1550 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1551
c52f33d0
JM		 1552 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1553 &sc->sbands[IEEE80211_BAND_2GHZ];
1554 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1555 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1556 &sc->sbands[IEEE80211_BAND_5GHZ];
1557}
1558
1559int ath_attach(u16 devid, struct ath_softc *sc)
1560{
1561 struct ieee80211_hw *hw = sc->hw;
c52f33d0 1562 int error = 0, i;
3a702e49 1563 struct ath_regulatory *reg;
c52f33d0
JM		 1564
1565 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1566
1567 error = ath_init(devid, sc);
1568 if (error != 0)
1569 return error;
1570
1571 /* get mac address from hardware and set in mac80211 */
1572
1573 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1574
1575 ath_set_hw_capab(sc, hw);
1576
c26c2e57
LR		 1577 error = ath_regd_init(&sc->sc_ah->regulatory, sc->hw->wiphy,
1578 ath9k_reg_notifier);
1579 if (error)
1580 return error;
1581
1582 reg = &sc->sc_ah->regulatory;
1583
2660b81a 1584 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1585 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
2660b81a 1586 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
eb2599ca 1587 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1588 }
1589
db93e7b5
SB		 1590 /* initialize tx/rx engine */
1591 error = ath_tx_init(sc, ATH_TXBUF);
1592 if (error != 0)
40b130a9 1593 goto error_attach;
8feceb67 1594
db93e7b5
SB		 1595 error = ath_rx_init(sc, ATH_RXBUF);
1596 if (error != 0)
40b130a9 1597 goto error_attach;
8feceb67 1598
0e2dedf9 1599 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
f98c3bd2
JM		 1600 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1601 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
0e2dedf9 1602
db93e7b5 1603 error = ieee80211_register_hw(hw);
8feceb67 1604
3a702e49 1605 if (!ath_is_world_regd(reg)) {
c02cf373 1606 error = regulatory_hint(hw->wiphy, reg->alpha2);
fe33eb39
LR		 1607 if (error)
1608 goto error_attach;
1609 }
5f8e077c 1610
db93e7b5
SB		 1611 /* Initialize LED control */
1612 ath_init_leds(sc);
8feceb67 1613
3b319aae 1614 ath_start_rfkill_poll(sc);
5f8e077c 1615
8feceb67 1616 return 0;
40b130a9
VT		 1617
1618error_attach:
1619 /* cleanup tx queues */
1620 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1621 if (ATH_TXQ_SETUP(sc, i))
1622 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1623
1624 ath9k_hw_detach(sc->sc_ah);
1625 ath9k_exit_debug(sc);
1626
8feceb67 1627 return error;
f078f209
LR		 1628}
1629
ff37e337
S		 1630int ath_reset(struct ath_softc *sc, bool retry_tx)
1631{
cbe61d8a 1632 struct ath_hw *ah = sc->sc_ah;
030bb495 1633 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1634 int r;
ff37e337
S		 1635
1636 ath9k_hw_set_interrupts(ah, 0);
043a0405 1637 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1638 ath_stoprecv(sc);
1639 ath_flushrecv(sc);
1640
1641 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1642 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 1643 if (r)
ff37e337 1644 DPRINTF(sc, ATH_DBG_FATAL,
6b45784f 1645 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S		 1646 spin_unlock_bh(&sc->sc_resetlock);
1647
1648 if (ath_startrecv(sc) != 0)
04bd4638 1649 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1650
1651 /*
1652 * We may be doing a reset in response to a request
1653 * that changes the channel so update any state that
1654 * might change as a result.
1655 */
ce111bad 1656 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1657
1658 ath_update_txpow(sc);
1659
1660 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1661 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 1662
17d7904d 1663 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 1664
1665 if (retry_tx) {
1666 int i;
1667 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1668 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1669 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1670 ath_txq_schedule(sc, &sc->tx.txq[i]);
1671 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1672 }
1673 }
1674 }
1675
ae8d2858 1676 return r;
ff37e337
S		 1677}
1678
1679/*
1680 * This function will allocate both the DMA descriptor structure, and the
1681 * buffers it contains. These are used to contain the descriptors used
1682 * by the system.
1683*/
1684int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1685 struct list_head *head, const char *name,
1686 int nbuf, int ndesc)
1687{
1688#define DS2PHYS(_dd, _ds) \
1689 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1690#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1691#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1692
1693 struct ath_desc *ds;
1694 struct ath_buf *bf;
1695 int i, bsize, error;
1696
04bd4638
S		 1697 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1698 name, nbuf, ndesc);
ff37e337 1699
b03a9db9 1700 INIT_LIST_HEAD(head);
ff37e337
S		 1701 /* ath_desc must be a multiple of DWORDs */
1702 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1703 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1704 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1705 error = -ENOMEM;
1706 goto fail;
1707 }
1708
ff37e337
S		 1709 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1710
1711 /*
1712 * Need additional DMA memory because we can't use
1713 * descriptors that cross the 4K page boundary. Assume
1714 * one skipped descriptor per 4K page.
1715 */
2660b81a 1716 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
ff37e337
S		 1717 u32 ndesc_skipped =
1718 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1719 u32 dma_len;
1720
1721 while (ndesc_skipped) {
1722 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1723 dd->dd_desc_len += dma_len;
1724
1725 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1726 };
1727 }
1728
1729 /* allocate descriptors */
7da3c55c 1730 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
f0e6ce13 1731 &dd->dd_desc_paddr, GFP_KERNEL);
ff37e337
S		 1732 if (dd->dd_desc == NULL) {
1733 error = -ENOMEM;
1734 goto fail;
1735 }
1736 ds = dd->dd_desc;
04bd4638 1737 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
ae459af1 1738 name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1739 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1740
1741 /* allocate buffers */
1742 bsize = sizeof(struct ath_buf) * nbuf;
f0e6ce13 1743 bf = kzalloc(bsize, GFP_KERNEL);
ff37e337
S		 1744 if (bf == NULL) {
1745 error = -ENOMEM;
1746 goto fail2;
1747 }
ff37e337
S		 1748 dd->dd_bufptr = bf;
1749
ff37e337
S		 1750 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1751 bf->bf_desc = ds;
1752 bf->bf_daddr = DS2PHYS(dd, ds);
1753
2660b81a 1754 if (!(sc->sc_ah->caps.hw_caps &
ff37e337
S		 1755 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1756 /*
1757 * Skip descriptor addresses which can cause 4KB
1758 * boundary crossing (addr + length) with a 32 dword
1759 * descriptor fetch.
1760 */
1761 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1762 ASSERT((caddr_t) bf->bf_desc <
1763 ((caddr_t) dd->dd_desc +
1764 dd->dd_desc_len));
1765
1766 ds += ndesc;
1767 bf->bf_desc = ds;
1768 bf->bf_daddr = DS2PHYS(dd, ds);
1769 }
1770 }
1771 list_add_tail(&bf->list, head);
1772 }
1773 return 0;
1774fail2:
7da3c55c
GJ		 1775 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1776 dd->dd_desc_paddr);
ff37e337
S		 1777fail:
1778 memset(dd, 0, sizeof(*dd));
1779 return error;
1780#undef ATH_DESC_4KB_BOUND_CHECK
1781#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1782#undef DS2PHYS
1783}
1784
1785void ath_descdma_cleanup(struct ath_softc *sc,
1786 struct ath_descdma *dd,
1787 struct list_head *head)
1788{
7da3c55c
GJ		 1789 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1790 dd->dd_desc_paddr);
ff37e337
S		 1791
1792 INIT_LIST_HEAD(head);
1793 kfree(dd->dd_bufptr);
1794 memset(dd, 0, sizeof(*dd));
1795}
1796
1797int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1798{
1799 int qnum;
1800
1801 switch (queue) {
1802 case 0:
b77f483f 1803 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1804 break;
1805 case 1:
b77f483f 1806 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 1807 break;
1808 case 2:
b77f483f 1809 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1810 break;
1811 case 3:
b77f483f 1812 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 1813 break;
1814 default:
b77f483f 1815 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1816 break;
1817 }
1818
1819 return qnum;
1820}
1821
1822int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1823{
1824 int qnum;
1825
1826 switch (queue) {
1827 case ATH9K_WME_AC_VO:
1828 qnum = 0;
1829 break;
1830 case ATH9K_WME_AC_VI:
1831 qnum = 1;
1832 break;
1833 case ATH9K_WME_AC_BE:
1834 qnum = 2;
1835 break;
1836 case ATH9K_WME_AC_BK:
1837 qnum = 3;
1838 break;
1839 default:
1840 qnum = -1;
1841 break;
1842 }
1843
1844 return qnum;
1845}
1846
5f8e077c
LR		 1847/* XXX: Remove me once we don't depend on ath9k_channel for all
1848 * this redundant data */
0e2dedf9
JM		 1849void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1850 struct ath9k_channel *ichan)
5f8e077c 1851{
5f8e077c
LR		 1852 struct ieee80211_channel *chan = hw->conf.channel;
1853 struct ieee80211_conf *conf = &hw->conf;
1854
1855 ichan->channel = chan->center_freq;
1856 ichan->chan = chan;
1857
1858 if (chan->band == IEEE80211_BAND_2GHZ) {
1859 ichan->chanmode = CHANNEL_G;
1860 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1861 } else {
1862 ichan->chanmode = CHANNEL_A;
1863 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1864 }
1865
1866 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1867
1868 if (conf_is_ht(conf)) {
1869 if (conf_is_ht40(conf))
1870 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1871
1872 ichan->chanmode = ath_get_extchanmode(sc, chan,
1873 conf->channel_type);
1874 }
1875}
1876
ff37e337
S		 1877/**********************/
1878/* mac80211 callbacks */
1879/**********************/
1880
8feceb67 1881static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1882{
bce048d7
JM		 1883 struct ath_wiphy *aphy = hw->priv;
1884 struct ath_softc *sc = aphy->sc;
8feceb67 1885 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1886 struct ath9k_channel *init_channel;
82880a7c 1887 int r;
f078f209 1888
04bd4638
S		 1889 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1890 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1891
141b38b6
S		 1892 mutex_lock(&sc->mutex);
1893
9580a222
JM		 1894 if (ath9k_wiphy_started(sc)) {
1895 if (sc->chan_idx == curchan->hw_value) {
1896 /*
1897 * Already on the operational channel, the new wiphy
1898 * can be marked active.
1899 */
1900 aphy->state = ATH_WIPHY_ACTIVE;
1901 ieee80211_wake_queues(hw);
1902 } else {
1903 /*
1904 * Another wiphy is on another channel, start the new
1905 * wiphy in paused state.
1906 */
1907 aphy->state = ATH_WIPHY_PAUSED;
1908 ieee80211_stop_queues(hw);
1909 }
1910 mutex_unlock(&sc->mutex);
1911 return 0;
1912 }
1913 aphy->state = ATH_WIPHY_ACTIVE;
1914
8feceb67 1915 /* setup initial channel */
f078f209 1916
82880a7c 1917 sc->chan_idx = curchan->hw_value;
f078f209 1918
82880a7c 1919 init_channel = ath_get_curchannel(sc, hw);
ff37e337
S		 1920
1921 /* Reset SERDES registers */
1922 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1923
1924 /*
1925 * The basic interface to setting the hardware in a good
1926 * state is ``reset''. On return the hardware is known to
1927 * be powered up and with interrupts disabled. This must
1928 * be followed by initialization of the appropriate bits
1929 * and then setup of the interrupt mask.
1930 */
1931 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1932 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1933 if (r) {
ff37e337 1934 DPRINTF(sc, ATH_DBG_FATAL,
6b45784f 1935 "Unable to reset hardware; reset status %d "
ae8d2858
LR		 1936 "(freq %u MHz)\n", r,
1937 curchan->center_freq);
ff37e337 1938 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 1939 goto mutex_unlock;
ff37e337
S		 1940 }
1941 spin_unlock_bh(&sc->sc_resetlock);
1942
1943 /*
1944 * This is needed only to setup initial state
1945 * but it's best done after a reset.
1946 */
1947 ath_update_txpow(sc);
8feceb67 1948
ff37e337
S		 1949 /*
1950 * Setup the hardware after reset:
1951 * The receive engine is set going.
1952 * Frame transmit is handled entirely
1953 * in the frame output path; there's nothing to do
1954 * here except setup the interrupt mask.
1955 */
1956 if (ath_startrecv(sc) != 0) {
1ffb0610 1957 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
141b38b6
S		 1958 r = -EIO;
1959 goto mutex_unlock;
f078f209 1960 }
8feceb67 1961
ff37e337 1962 /* Setup our intr mask. */
17d7904d 1963 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S		 1964 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1965 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1966
2660b81a 1967 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 1968 sc->imask |= ATH9K_INT_GTT;
ff37e337 1969
2660b81a 1970 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 1971 sc->imask |= ATH9K_INT_CST;
ff37e337 1972
ce111bad 1973 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1974
1975 sc->sc_flags &= ~SC_OP_INVALID;
1976
1977 /* Disable BMISS interrupt when we're not associated */
17d7904d
S		 1978 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1979 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337 1980
bce048d7 1981 ieee80211_wake_queues(hw);
ff37e337 1982
164ace38
SB		 1983 queue_delayed_work(sc->hw->workqueue, &sc->tx_complete_work, 0);
1984
141b38b6
S		 1985mutex_unlock:
1986 mutex_unlock(&sc->mutex);
1987
ae8d2858 1988 return r;
f078f209
LR		 1989}
1990
8feceb67
VT		 1991static int ath9k_tx(struct ieee80211_hw *hw,
1992 struct sk_buff *skb)
f078f209 1993{
528f0c6b 1994 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM		 1995 struct ath_wiphy *aphy = hw->priv;
1996 struct ath_softc *sc = aphy->sc;
528f0c6b 1997 struct ath_tx_control txctl;
8feceb67 1998 int hdrlen, padsize;
528f0c6b 1999
8089cc47 2000 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
ee166a0e
JM		 2001 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2002 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2003 goto exit;
2004 }
2005
dc8c4585
JM		 2006 if (sc->hw->conf.flags & IEEE80211_CONF_PS) {
2007 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2008 /*
2009 * mac80211 does not set PM field for normal data frames, so we
2010 * need to update that based on the current PS mode.
2011 */
2012 if (ieee80211_is_data(hdr->frame_control) &&
2013 !ieee80211_is_nullfunc(hdr->frame_control) &&
2014 !ieee80211_has_pm(hdr->frame_control)) {
2015 DPRINTF(sc, ATH_DBG_PS, "Add PM=1 for a TX frame "
2016 "while in PS mode\n");
2017 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2018 }
2019 }
2020
9a23f9ca
JM		 2021 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2022 /*
2023 * We are using PS-Poll and mac80211 can request TX while in
2024 * power save mode. Need to wake up hardware for the TX to be
2025 * completed and if needed, also for RX of buffered frames.
2026 */
2027 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2028 ath9k_ps_wakeup(sc);
2029 ath9k_hw_setrxabort(sc->sc_ah, 0);
2030 if (ieee80211_is_pspoll(hdr->frame_control)) {
2031 DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a "
2032 "buffered frame\n");
2033 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2034 } else {
2035 DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n");
2036 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2037 }
2038 /*
2039 * The actual restore operation will happen only after
2040 * the sc_flags bit is cleared. We are just dropping
2041 * the ps_usecount here.
2042 */
2043 ath9k_ps_restore(sc);
2044 }
2045
528f0c6b 2046 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2047
8feceb67
VT		 2048 /*
2049 * As a temporary workaround, assign seq# here; this will likely need
2050 * to be cleaned up to work better with Beacon transmission and virtual
2051 * BSSes.
2052 */
2053 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2054 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2055 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2056 sc->tx.seq_no += 0x10;
8feceb67 2057 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2058 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2059 }
f078f209 2060
8feceb67
VT		 2061 /* Add the padding after the header if this is not already done */
2062 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2063 if (hdrlen & 3) {
2064 padsize = hdrlen % 4;
2065 if (skb_headroom(skb) < padsize)
2066 return -1;
2067 skb_push(skb, padsize);
2068 memmove(skb->data, skb->data + padsize, hdrlen);
2069 }
2070
528f0c6b
S		 2071 /* Check if a tx queue is available */
2072
2073 txctl.txq = ath_test_get_txq(sc, skb);
2074 if (!txctl.txq)
2075 goto exit;
2076
04bd4638 2077 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2078
c52f33d0 2079 if (ath_tx_start(hw, skb, &txctl) != 0) {
04bd4638 2080 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2081 goto exit;
8feceb67
VT		 2082 }
2083
528f0c6b
S		 2084 return 0;
2085exit:
2086 dev_kfree_skb_any(skb);
8feceb67 2087 return 0;
f078f209
LR		 2088}
2089
8feceb67 2090static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 2091{
bce048d7
JM		 2092 struct ath_wiphy *aphy = hw->priv;
2093 struct ath_softc *sc = aphy->sc;
f078f209 2094
9580a222
JM		 2095 aphy->state = ATH_WIPHY_INACTIVE;
2096
9c84b797 2097 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 2098 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
9c84b797
S		 2099 return;
2100 }
8feceb67 2101
141b38b6 2102 mutex_lock(&sc->mutex);
ff37e337 2103
bce048d7 2104 ieee80211_stop_queues(hw);
ff37e337 2105
9580a222
JM		 2106 if (ath9k_wiphy_started(sc)) {
2107 mutex_unlock(&sc->mutex);
2108 return; /* another wiphy still in use */
2109 }
2110
ff37e337
S		 2111 /* make sure h/w will not generate any interrupt
2112 * before setting the invalid flag. */
2113 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2114
2115 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2116 ath_drain_all_txq(sc, false);
ff37e337
S		 2117 ath_stoprecv(sc);
2118 ath9k_hw_phy_disable(sc->sc_ah);
2119 } else
b77f483f 2120 sc->rx.rxlink = NULL;
ff37e337 2121
3b319aae 2122 wiphy_rfkill_stop_polling(sc->hw->wiphy);
19d337df 2123
ff37e337
S		 2124 /* disable HAL and put h/w to sleep */
2125 ath9k_hw_disable(sc->sc_ah);
2126 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2127
2128 sc->sc_flags |= SC_OP_INVALID;
500c064d 2129
141b38b6
S		 2130 mutex_unlock(&sc->mutex);
2131
04bd4638 2132 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2133}
2134
8feceb67
VT		 2135static int ath9k_add_interface(struct ieee80211_hw *hw,
2136 struct ieee80211_if_init_conf *conf)
f078f209 2137{
bce048d7
JM		 2138 struct ath_wiphy *aphy = hw->priv;
2139 struct ath_softc *sc = aphy->sc;
17d7904d 2140 struct ath_vif *avp = (void *)conf->vif->drv_priv;
d97809db 2141 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 2142 int ret = 0;
8feceb67 2143
141b38b6
S		 2144 mutex_lock(&sc->mutex);
2145
8ca21f01
JM		 2146 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2147 sc->nvifs > 0) {
2148 ret = -ENOBUFS;
2149 goto out;
2150 }
2151
8feceb67 2152 switch (conf->type) {
05c914fe 2153 case NL80211_IFTYPE_STATION:
d97809db 2154 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2155 break;
05c914fe 2156 case NL80211_IFTYPE_ADHOC:
05c914fe 2157 case NL80211_IFTYPE_AP:
9cb5412b 2158 case NL80211_IFTYPE_MESH_POINT:
2c3db3d5
JM		 2159 if (sc->nbcnvifs >= ATH_BCBUF) {
2160 ret = -ENOBUFS;
2161 goto out;
2162 }
9cb5412b 2163 ic_opmode = conf->type;
f078f209
LR		 2164 break;
2165 default:
2166 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2167 "Interface type %d not yet supported\n", conf->type);
2c3db3d5
JM		 2168 ret = -EOPNOTSUPP;
2169 goto out;
f078f209
LR		 2170 }
2171
17d7904d 2172 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 2173
17d7904d 2174 /* Set the VIF opmode */
5640b08e
S		 2175 avp->av_opmode = ic_opmode;
2176 avp->av_bslot = -1;
2177
2c3db3d5 2178 sc->nvifs++;
8ca21f01
JM		 2179
2180 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2181 ath9k_set_bssid_mask(hw);
2182
2c3db3d5
JM		 2183 if (sc->nvifs > 1)
2184 goto out; /* skip global settings for secondary vif */
2185
b238e90e 2186 if (ic_opmode == NL80211_IFTYPE_AP) {
5640b08e 2187 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
b238e90e
S		 2188 sc->sc_flags |= SC_OP_TSF_RESET;
2189 }
5640b08e 2190
5640b08e 2191 /* Set the device opmode */
2660b81a 2192 sc->sc_ah->opmode = ic_opmode;
5640b08e 2193
4e30ffa2
VN		 2194 /*
2195 * Enable MIB interrupts when there are hardware phy counters.
2196 * Note we only do this (at the moment) for station mode.
2197 */
4af9cf4f 2198 if ((conf->type == NL80211_IFTYPE_STATION) ||
9cb5412b
PE		 2199 (conf->type == NL80211_IFTYPE_ADHOC) ||
2200 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
4af9cf4f
S		 2201 if (ath9k_hw_phycounters(sc->sc_ah))
2202 sc->imask |= ATH9K_INT_MIB;
2203 sc->imask |= ATH9K_INT_TSFOOR;
2204 }
2205
17d7904d 2206 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 2207
f38faa31
SB		 2208 if (conf->type == NL80211_IFTYPE_AP ||
2209 conf->type == NL80211_IFTYPE_ADHOC ||
2210 conf->type == NL80211_IFTYPE_MONITOR)
415f738e 2211 ath_start_ani(sc);
6f255425 2212
2c3db3d5 2213out:
141b38b6 2214 mutex_unlock(&sc->mutex);
2c3db3d5 2215 return ret;
f078f209
LR		 2216}
2217
8feceb67
VT		 2218static void ath9k_remove_interface(struct ieee80211_hw *hw,
2219 struct ieee80211_if_init_conf *conf)
f078f209 2220{
bce048d7
JM		 2221 struct ath_wiphy *aphy = hw->priv;
2222 struct ath_softc *sc = aphy->sc;
17d7904d 2223 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2c3db3d5 2224 int i;
f078f209 2225
04bd4638 2226 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2227
141b38b6
S		 2228 mutex_lock(&sc->mutex);
2229
6f255425 2230 /* Stop ANI */
17d7904d 2231 del_timer_sync(&sc->ani.timer);
580f0b8a 2232
8feceb67 2233 /* Reclaim beacon resources */
9cb5412b
PE		 2234 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2235 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2236 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
b77f483f 2237 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2238 ath_beacon_return(sc, avp);
580f0b8a 2239 }
f078f209 2240
8feceb67 2241 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2242
2c3db3d5
JM		 2243 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2244 if (sc->beacon.bslot[i] == conf->vif) {
2245 printk(KERN_DEBUG "%s: vif had allocated beacon "
2246 "slot\n", __func__);
2247 sc->beacon.bslot[i] = NULL;
c52f33d0 2248 sc->beacon.bslot_aphy[i] = NULL;
2c3db3d5
JM		 2249 }
2250 }
2251
17d7904d 2252 sc->nvifs--;
141b38b6
S		 2253
2254 mutex_unlock(&sc->mutex);
f078f209
LR		 2255}
2256
e8975581 2257static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2258{
bce048d7
JM		 2259 struct ath_wiphy *aphy = hw->priv;
2260 struct ath_softc *sc = aphy->sc;
e8975581 2261 struct ieee80211_conf *conf = &hw->conf;
8782b41d 2262 struct ath_hw *ah = sc->sc_ah;
f078f209 2263
aa33de09 2264 mutex_lock(&sc->mutex);
141b38b6 2265
3cbb5dd7
VN		 2266 if (changed & IEEE80211_CONF_CHANGE_PS) {
2267 if (conf->flags & IEEE80211_CONF_PS) {
8782b41d
VN		 2268 if (!(ah->caps.hw_caps &
2269 ATH9K_HW_CAP_AUTOSLEEP)) {
2270 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2271 sc->imask |= ATH9K_INT_TIM_TIMER;
2272 ath9k_hw_set_interrupts(sc->sc_ah,
2273 sc->imask);
2274 }
2275 ath9k_hw_setrxabort(sc->sc_ah, 1);
3cbb5dd7 2276 }
3cbb5dd7
VN		 2277 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2278 } else {
2279 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8782b41d
VN		 2280 if (!(ah->caps.hw_caps &
2281 ATH9K_HW_CAP_AUTOSLEEP)) {
2282 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca
JM		 2283 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2284 SC_OP_WAIT_FOR_CAB |
2285 SC_OP_WAIT_FOR_PSPOLL_DATA |
2286 SC_OP_WAIT_FOR_TX_ACK);
8782b41d
VN		 2287 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2288 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2289 ath9k_hw_set_interrupts(sc->sc_ah,
2290 sc->imask);
2291 }
3cbb5dd7
VN		 2292 }
2293 }
2294 }
2295
4797938c 2296 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2297 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2298 int pos = curchan->hw_value;
ae5eb026 2299
0e2dedf9
JM		 2300 aphy->chan_idx = pos;
2301 aphy->chan_is_ht = conf_is_ht(conf);
2302
8089cc47
JM		 2303 if (aphy->state == ATH_WIPHY_SCAN ||
2304 aphy->state == ATH_WIPHY_ACTIVE)
2305 ath9k_wiphy_pause_all_forced(sc, aphy);
2306 else {
2307 /*
2308 * Do not change operational channel based on a paused
2309 * wiphy changes.
2310 */
2311 goto skip_chan_change;
2312 }
0e2dedf9 2313
04bd4638
S		 2314 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2315 curchan->center_freq);
f078f209 2316
5f8e077c 2317 /* XXX: remove me eventualy */
0e2dedf9 2318 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 2319
ecf70441 2320 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2321
0e2dedf9 2322 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
04bd4638 2323 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2324 mutex_unlock(&sc->mutex);
e11602b7
S		 2325 return -EINVAL;
2326 }
094d05dc 2327 }
f078f209 2328
8089cc47 2329skip_chan_change:
5c020dc6 2330 if (changed & IEEE80211_CONF_CHANGE_POWER)
17d7904d 2331 sc->config.txpowlimit = 2 * conf->power_level;
f078f209 2332
aa33de09 2333 mutex_unlock(&sc->mutex);
141b38b6 2334
f078f209
LR		 2335 return 0;
2336}
2337
8feceb67
VT		 2338#define SUPPORTED_FILTERS \
2339 (FIF_PROMISC_IN_BSS | \
2340 FIF_ALLMULTI | \
2341 FIF_CONTROL | \
2342 FIF_OTHER_BSS | \
2343 FIF_BCN_PRBRESP_PROMISC | \
2344 FIF_FCSFAIL)
c83be688 2345
8feceb67
VT		 2346/* FIXME: sc->sc_full_reset ? */
2347static void ath9k_configure_filter(struct ieee80211_hw *hw,
2348 unsigned int changed_flags,
2349 unsigned int *total_flags,
2350 int mc_count,
2351 struct dev_mc_list *mclist)
2352{
bce048d7
JM		 2353 struct ath_wiphy *aphy = hw->priv;
2354 struct ath_softc *sc = aphy->sc;
8feceb67 2355 u32 rfilt;
f078f209 2356
8feceb67
VT		 2357 changed_flags &= SUPPORTED_FILTERS;
2358 *total_flags &= SUPPORTED_FILTERS;
f078f209 2359
b77f483f 2360 sc->rx.rxfilter = *total_flags;
aa68aeaa 2361 ath9k_ps_wakeup(sc);
8feceb67
VT		 2362 rfilt = ath_calcrxfilter(sc);
2363 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 2364 ath9k_ps_restore(sc);
f078f209 2365
b77f483f 2366 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
8feceb67 2367}
f078f209 2368
8feceb67
VT		 2369static void ath9k_sta_notify(struct ieee80211_hw *hw,
2370 struct ieee80211_vif *vif,
2371 enum sta_notify_cmd cmd,
17741cdc 2372 struct ieee80211_sta *sta)
8feceb67 2373{
bce048d7
JM		 2374 struct ath_wiphy *aphy = hw->priv;
2375 struct ath_softc *sc = aphy->sc;
f078f209 2376
8feceb67
VT		 2377 switch (cmd) {
2378 case STA_NOTIFY_ADD:
5640b08e 2379 ath_node_attach(sc, sta);
8feceb67
VT		 2380 break;
2381 case STA_NOTIFY_REMOVE:
b5aa9bf9 2382 ath_node_detach(sc, sta);
8feceb67
VT		 2383 break;
2384 default:
2385 break;
2386 }
f078f209
LR		 2387}
2388
141b38b6 2389static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 2390 const struct ieee80211_tx_queue_params *params)
f078f209 2391{
bce048d7
JM		 2392 struct ath_wiphy *aphy = hw->priv;
2393 struct ath_softc *sc = aphy->sc;
8feceb67
VT		 2394 struct ath9k_tx_queue_info qi;
2395 int ret = 0, qnum;
f078f209 2396
8feceb67
VT		 2397 if (queue >= WME_NUM_AC)
2398 return 0;
f078f209 2399
141b38b6
S		 2400 mutex_lock(&sc->mutex);
2401
1ffb0610
S		 2402 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2403
8feceb67
VT		 2404 qi.tqi_aifs = params->aifs;
2405 qi.tqi_cwmin = params->cw_min;
2406 qi.tqi_cwmax = params->cw_max;
2407 qi.tqi_burstTime = params->txop;
2408 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2409
8feceb67 2410 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2411 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2412 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2413 queue, qnum, params->aifs, params->cw_min,
2414 params->cw_max, params->txop);
f078f209 2415
8feceb67
VT		 2416 ret = ath_txq_update(sc, qnum, &qi);
2417 if (ret)
04bd4638 2418 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2419
141b38b6
S		 2420 mutex_unlock(&sc->mutex);
2421
8feceb67
VT		 2422 return ret;
2423}
f078f209 2424
8feceb67
VT		 2425static int ath9k_set_key(struct ieee80211_hw *hw,
2426 enum set_key_cmd cmd,
dc822b5d
JB		 2427 struct ieee80211_vif *vif,
2428 struct ieee80211_sta *sta,
8feceb67
VT		 2429 struct ieee80211_key_conf *key)
2430{
bce048d7
JM		 2431 struct ath_wiphy *aphy = hw->priv;
2432 struct ath_softc *sc = aphy->sc;
8feceb67 2433 int ret = 0;
f078f209 2434
b3bd89ce
JM		 2435 if (modparam_nohwcrypt)
2436 return -ENOSPC;
2437
141b38b6 2438 mutex_lock(&sc->mutex);
3cbb5dd7 2439 ath9k_ps_wakeup(sc);
d8baa939 2440 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 2441
8feceb67
VT		 2442 switch (cmd) {
2443 case SET_KEY:
3f53dd64 2444 ret = ath_key_config(sc, vif, sta, key);
6ace2891
JM		 2445 if (ret >= 0) {
2446 key->hw_key_idx = ret;
8feceb67
VT		 2447 /* push IV and Michael MIC generation to stack */
2448 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2449 if (key->alg == ALG_TKIP)
2450 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2451 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2452 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2453 ret = 0;
8feceb67
VT		 2454 }
2455 break;
2456 case DISABLE_KEY:
2457 ath_key_delete(sc, key);
8feceb67
VT		 2458 break;
2459 default:
2460 ret = -EINVAL;
2461 }
f078f209 2462
3cbb5dd7 2463 ath9k_ps_restore(sc);
141b38b6
S		 2464 mutex_unlock(&sc->mutex);
2465
8feceb67
VT		 2466 return ret;
2467}
f078f209 2468
8feceb67
VT		 2469static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2470 struct ieee80211_vif *vif,
2471 struct ieee80211_bss_conf *bss_conf,
2472 u32 changed)
2473{
bce048d7
JM		 2474 struct ath_wiphy *aphy = hw->priv;
2475 struct ath_softc *sc = aphy->sc;
2d0ddec5
JB		 2476 struct ath_hw *ah = sc->sc_ah;
2477 struct ath_vif *avp = (void *)vif->drv_priv;
2478 u32 rfilt = 0;
2479 int error, i;
f078f209 2480
141b38b6
S		 2481 mutex_lock(&sc->mutex);
2482
2d0ddec5
JB		 2483 /*
2484 * TODO: Need to decide which hw opmode to use for
2485 * multi-interface cases
2486 * XXX: This belongs into add_interface!
2487 */
2488 if (vif->type == NL80211_IFTYPE_AP &&
2489 ah->opmode != NL80211_IFTYPE_AP) {
2490 ah->opmode = NL80211_IFTYPE_STATION;
2491 ath9k_hw_setopmode(ah);
2492 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2493 sc->curaid = 0;
2494 ath9k_hw_write_associd(sc);
2495 /* Request full reset to get hw opmode changed properly */
2496 sc->sc_flags |= SC_OP_FULL_RESET;
2497 }
2498
2499 if ((changed & BSS_CHANGED_BSSID) &&
2500 !is_zero_ether_addr(bss_conf->bssid)) {
2501 switch (vif->type) {
2502 case NL80211_IFTYPE_STATION:
2503 case NL80211_IFTYPE_ADHOC:
2504 case NL80211_IFTYPE_MESH_POINT:
2505 /* Set BSSID */
2506 memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2507 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2508 sc->curaid = 0;
2509 ath9k_hw_write_associd(sc);
2510
2511 /* Set aggregation protection mode parameters */
2512 sc->config.ath_aggr_prot = 0;
2513
2514 DPRINTF(sc, ATH_DBG_CONFIG,
2515 "RX filter 0x%x bssid %pM aid 0x%x\n",
2516 rfilt, sc->curbssid, sc->curaid);
2517
2518 /* need to reconfigure the beacon */
2519 sc->sc_flags &= ~SC_OP_BEACONS ;
2520
2521 break;
2522 default:
2523 break;
2524 }
2525 }
2526
2527 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2528 (vif->type == NL80211_IFTYPE_AP) ||
2529 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2530 if ((changed & BSS_CHANGED_BEACON) ||
2531 (changed & BSS_CHANGED_BEACON_ENABLED &&
2532 bss_conf->enable_beacon)) {
2533 /*
2534 * Allocate and setup the beacon frame.
2535 *
2536 * Stop any previous beacon DMA. This may be
2537 * necessary, for example, when an ibss merge
2538 * causes reconfiguration; we may be called
2539 * with beacon transmission active.
2540 */
2541 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2542
2543 error = ath_beacon_alloc(aphy, vif);
2544 if (!error)
2545 ath_beacon_config(sc, vif);
2546 }
2547 }
2548
2549 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2550 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2551 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2552 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2553 ath9k_hw_keysetmac(sc->sc_ah,
2554 (u16)i,
2555 sc->curbssid);
2556 }
2557
2558 /* Only legacy IBSS for now */
2559 if (vif->type == NL80211_IFTYPE_ADHOC)
2560 ath_update_chainmask(sc, 0);
2561
8feceb67 2562 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2563 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2564 bss_conf->use_short_preamble);
2565 if (bss_conf->use_short_preamble)
2566 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2567 else
2568 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2569 }
f078f209 2570
8feceb67 2571 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2572 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2573 bss_conf->use_cts_prot);
2574 if (bss_conf->use_cts_prot &&
2575 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2576 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2577 else
2578 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2579 }
f078f209 2580
8feceb67 2581 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2582 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2583 bss_conf->assoc);
5640b08e 2584 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 2585 }
141b38b6 2586
57c4d7b4
JB		 2587 /*
2588 * The HW TSF has to be reset when the beacon interval changes.
2589 * We set the flag here, and ath_beacon_config_ap() would take this
2590 * into account when it gets called through the subsequent
2591 * config_interface() call - with IFCC_BEACON in the changed field.
2592 */
2593
2594 if (changed & BSS_CHANGED_BEACON_INT) {
2595 sc->sc_flags |= SC_OP_TSF_RESET;
2596 sc->beacon_interval = bss_conf->beacon_int;
2597 }
2598
141b38b6 2599 mutex_unlock(&sc->mutex);
8feceb67 2600}
f078f209 2601
8feceb67
VT		 2602static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2603{
2604 u64 tsf;
bce048d7
JM		 2605 struct ath_wiphy *aphy = hw->priv;
2606 struct ath_softc *sc = aphy->sc;
f078f209 2607
141b38b6
S		 2608 mutex_lock(&sc->mutex);
2609 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2610 mutex_unlock(&sc->mutex);
f078f209 2611
8feceb67
VT		 2612 return tsf;
2613}
f078f209 2614
3b5d665b
AF		 2615static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2616{
bce048d7
JM		 2617 struct ath_wiphy *aphy = hw->priv;
2618 struct ath_softc *sc = aphy->sc;
3b5d665b 2619
141b38b6
S		 2620 mutex_lock(&sc->mutex);
2621 ath9k_hw_settsf64(sc->sc_ah, tsf);
2622 mutex_unlock(&sc->mutex);
3b5d665b
AF		 2623}
2624
8feceb67
VT		 2625static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2626{
bce048d7
JM		 2627 struct ath_wiphy *aphy = hw->priv;
2628 struct ath_softc *sc = aphy->sc;
c83be688 2629
141b38b6
S		 2630 mutex_lock(&sc->mutex);
2631 ath9k_hw_reset_tsf(sc->sc_ah);
2632 mutex_unlock(&sc->mutex);
8feceb67 2633}
f078f209 2634
8feceb67 2635static int ath9k_ampdu_action(struct ieee80211_hw *hw,
141b38b6
S		 2636 enum ieee80211_ampdu_mlme_action action,
2637 struct ieee80211_sta *sta,
2638 u16 tid, u16 *ssn)
8feceb67 2639{
bce048d7
JM		 2640 struct ath_wiphy *aphy = hw->priv;
2641 struct ath_softc *sc = aphy->sc;
8feceb67 2642 int ret = 0;
f078f209 2643
8feceb67
VT		 2644 switch (action) {
2645 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2646 if (!(sc->sc_flags & SC_OP_RXAGGR))
2647 ret = -ENOTSUPP;
8feceb67
VT		 2648 break;
2649 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2650 break;
2651 case IEEE80211_AMPDU_TX_START:
b5aa9bf9 2652 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
8feceb67
VT		 2653 if (ret < 0)
2654 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2655 "Unable to start TX aggregation\n");
8feceb67 2656 else
17741cdc 2657 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2658 break;
2659 case IEEE80211_AMPDU_TX_STOP:
b5aa9bf9 2660 ret = ath_tx_aggr_stop(sc, sta, tid);
8feceb67
VT		 2661 if (ret < 0)
2662 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2663 "Unable to stop TX aggregation\n");
f078f209 2664
17741cdc 2665 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2666 break;
b1720231 2667 case IEEE80211_AMPDU_TX_OPERATIONAL:
8469cdef
S		 2668 ath_tx_aggr_resume(sc, sta, tid);
2669 break;
8feceb67 2670 default:
04bd4638 2671 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2672 }
2673
2674 return ret;
f078f209
LR		 2675}
2676
0c98de65
S		 2677static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2678{
bce048d7
JM		 2679 struct ath_wiphy *aphy = hw->priv;
2680 struct ath_softc *sc = aphy->sc;
0c98de65 2681
8089cc47
JM		 2682 if (ath9k_wiphy_scanning(sc)) {
2683 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2684 "same time\n");
2685 /*
2686 * Do not allow the concurrent scanning state for now. This
2687 * could be improved with scanning control moved into ath9k.
2688 */
2689 return;
2690 }
2691
2692 aphy->state = ATH_WIPHY_SCAN;
2693 ath9k_wiphy_pause_all_forced(sc, aphy);
2694
e5f0921a 2695 spin_lock_bh(&sc->ani_lock);
0c98de65 2696 sc->sc_flags |= SC_OP_SCANNING;
e5f0921a 2697 spin_unlock_bh(&sc->ani_lock);
0c98de65
S		 2698}
2699
2700static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2701{
bce048d7
JM		 2702 struct ath_wiphy *aphy = hw->priv;
2703 struct ath_softc *sc = aphy->sc;
0c98de65 2704
e5f0921a 2705 spin_lock_bh(&sc->ani_lock);
8089cc47 2706 aphy->state = ATH_WIPHY_ACTIVE;
0c98de65 2707 sc->sc_flags &= ~SC_OP_SCANNING;
9c07a777 2708 sc->sc_flags |= SC_OP_FULL_RESET;
e5f0921a 2709 spin_unlock_bh(&sc->ani_lock);
0c98de65
S		 2710}
2711
6baff7f9 2712struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2713 .tx = ath9k_tx,
2714 .start = ath9k_start,
2715 .stop = ath9k_stop,
2716 .add_interface = ath9k_add_interface,
2717 .remove_interface = ath9k_remove_interface,
2718 .config = ath9k_config,
8feceb67 2719 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2720 .sta_notify = ath9k_sta_notify,
2721 .conf_tx = ath9k_conf_tx,
8feceb67 2722 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2723 .set_key = ath9k_set_key,
8feceb67 2724 .get_tsf = ath9k_get_tsf,
3b5d665b 2725 .set_tsf = ath9k_set_tsf,
8feceb67 2726 .reset_tsf = ath9k_reset_tsf,
4233df6b 2727 .ampdu_action = ath9k_ampdu_action,
0c98de65
S		 2728 .sw_scan_start = ath9k_sw_scan_start,
2729 .sw_scan_complete = ath9k_sw_scan_complete,
3b319aae 2730 .rfkill_poll = ath9k_rfkill_poll_state,
8feceb67
VT		 2731};
2732
392dff83
BP		 2733static struct {
2734 u32 version;
2735 const char * name;
2736} ath_mac_bb_names[] = {
2737 { AR_SREV_VERSION_5416_PCI, "5416" },
2738 { AR_SREV_VERSION_5416_PCIE, "5418" },
2739 { AR_SREV_VERSION_9100, "9100" },
2740 { AR_SREV_VERSION_9160, "9160" },
2741 { AR_SREV_VERSION_9280, "9280" },
2742 { AR_SREV_VERSION_9285, "9285" }
2743};
2744
2745static struct {
2746 u16 version;
2747 const char * name;
2748} ath_rf_names[] = {
2749 { 0, "5133" },
2750 { AR_RAD5133_SREV_MAJOR, "5133" },
2751 { AR_RAD5122_SREV_MAJOR, "5122" },
2752 { AR_RAD2133_SREV_MAJOR, "2133" },
2753 { AR_RAD2122_SREV_MAJOR, "2122" }
2754};
2755
2756/*
2757 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2758 */
6baff7f9 2759const char *
392dff83
BP		 2760ath_mac_bb_name(u32 mac_bb_version)
2761{
2762 int i;
2763
2764 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2765 if (ath_mac_bb_names[i].version == mac_bb_version) {
2766 return ath_mac_bb_names[i].name;
2767 }
2768 }
2769
2770 return "????";
2771}
2772
2773/*
2774 * Return the RF name. "????" is returned if the RF is unknown.
2775 */
6baff7f9 2776const char *
392dff83
BP		 2777ath_rf_name(u16 rf_version)
2778{
2779 int i;
2780
2781 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2782 if (ath_rf_names[i].version == rf_version) {
2783 return ath_rf_names[i].name;
2784 }
2785 }
2786
2787 return "????";
2788}
2789
6baff7f9 2790static int __init ath9k_init(void)
f078f209 2791{
ca8a8560
VT		 2792 int error;
2793
ca8a8560
VT		 2794 /* Register rate control algorithm */
2795 error = ath_rate_control_register();
2796 if (error != 0) {
2797 printk(KERN_ERR
b51bb3cd
LR		 2798 "ath9k: Unable to register rate control "
2799 "algorithm: %d\n",
ca8a8560 2800 error);
6baff7f9 2801 goto err_out;
ca8a8560
VT		 2802 }
2803
19d8bc22
GJ		 2804 error = ath9k_debug_create_root();
2805 if (error) {
2806 printk(KERN_ERR
2807 "ath9k: Unable to create debugfs root: %d\n",
2808 error);
2809 goto err_rate_unregister;
2810 }
2811
6baff7f9
GJ		 2812 error = ath_pci_init();
2813 if (error < 0) {
f078f209 2814 printk(KERN_ERR
b51bb3cd 2815 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9 2816 error = -ENODEV;
19d8bc22 2817 goto err_remove_root;
f078f209
LR		 2818 }
2819
09329d37
GJ		 2820 error = ath_ahb_init();
2821 if (error < 0) {
2822 error = -ENODEV;
2823 goto err_pci_exit;
2824 }
2825
f078f209 2826 return 0;
6baff7f9 2827
09329d37
GJ		 2828 err_pci_exit:
2829 ath_pci_exit();
2830
19d8bc22
GJ		 2831 err_remove_root:
2832 ath9k_debug_remove_root();
6baff7f9
GJ		 2833 err_rate_unregister:
2834 ath_rate_control_unregister();
2835 err_out:
2836 return error;
f078f209 2837}
6baff7f9 2838module_init(ath9k_init);
f078f209 2839
6baff7f9 2840static void __exit ath9k_exit(void)
f078f209 2841{
09329d37 2842 ath_ahb_exit();
6baff7f9 2843 ath_pci_exit();
19d8bc22 2844 ath9k_debug_remove_root();
ca8a8560 2845 ath_rate_control_unregister();
04bd4638 2846 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 2847}
6baff7f9 2848module_exit(ath9k_exit);
Linux kernel - Deliverables
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