ath9k_hw: make ath9k_hw_set_interrupts use ah->imask by default
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
69081624 18#include <linux/delay.h>
394cf0a1 19#include "ath9k.h"
af03abec 20#include "btcoex.h"
f078f209 21
ff37e337
S
22static u8 parse_mpdudensity(u8 mpdudensity)
23{
24 /*
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
26 * 0 for no restriction
27 * 1 for 1/4 us
28 * 2 for 1/2 us
29 * 3 for 1 us
30 * 4 for 2 us
31 * 5 for 4 us
32 * 6 for 8 us
33 * 7 for 16 us
34 */
35 switch (mpdudensity) {
36 case 0:
37 return 0;
38 case 1:
39 case 2:
40 case 3:
41 /* Our lower layer calculations limit our precision to
42 1 microsecond */
43 return 1;
44 case 4:
45 return 2;
46 case 5:
47 return 4;
48 case 6:
49 return 8;
50 case 7:
51 return 16;
52 default:
53 return 0;
54 }
55}
56
69081624
VT
57static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
58{
59 bool pending = false;
60
61 spin_lock_bh(&txq->axq_lock);
62
63 if (txq->axq_depth || !list_empty(&txq->axq_acq))
64 pending = true;
69081624
VT
65
66 spin_unlock_bh(&txq->axq_lock);
67 return pending;
68}
69
6d79cb4c 70static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR
71{
72 unsigned long flags;
73 bool ret;
74
9ecdef4b
LR
75 spin_lock_irqsave(&sc->sc_pm_lock, flags);
76 ret = ath9k_hw_setpower(sc->sc_ah, mode);
77 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR
78
79 return ret;
80}
81
a91d75ae
LR
82void ath9k_ps_wakeup(struct ath_softc *sc)
83{
898c914a 84 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae 85 unsigned long flags;
fbb078fc 86 enum ath9k_power_mode power_mode;
a91d75ae
LR
87
88 spin_lock_irqsave(&sc->sc_pm_lock, flags);
89 if (++sc->ps_usecount != 1)
90 goto unlock;
91
fbb078fc 92 power_mode = sc->sc_ah->power_mode;
9ecdef4b 93 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae 94
898c914a
FF
95 /*
96 * While the hardware is asleep, the cycle counters contain no
97 * useful data. Better clear them now so that they don't mess up
98 * survey data results.
99 */
fbb078fc
FF
100 if (power_mode != ATH9K_PM_AWAKE) {
101 spin_lock(&common->cc_lock);
102 ath_hw_cycle_counters_update(common);
103 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
104 spin_unlock(&common->cc_lock);
105 }
898c914a 106
a91d75ae
LR
107 unlock:
108 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
109}
110
111void ath9k_ps_restore(struct ath_softc *sc)
112{
898c914a 113 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
c6c539f0 114 enum ath9k_power_mode mode;
a91d75ae
LR
115 unsigned long flags;
116
117 spin_lock_irqsave(&sc->sc_pm_lock, flags);
118 if (--sc->ps_usecount != 0)
119 goto unlock;
120
1dbfd9d4 121 if (sc->ps_idle)
c6c539f0 122 mode = ATH9K_PM_FULL_SLEEP;
1dbfd9d4
VN
123 else if (sc->ps_enabled &&
124 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
1b04b930
S
125 PS_WAIT_FOR_CAB |
126 PS_WAIT_FOR_PSPOLL_DATA |
127 PS_WAIT_FOR_TX_ACK)))
c6c539f0
FF
128 mode = ATH9K_PM_NETWORK_SLEEP;
129 else
130 goto unlock;
131
132 spin_lock(&common->cc_lock);
133 ath_hw_cycle_counters_update(common);
134 spin_unlock(&common->cc_lock);
135
1a8f0d39 136 ath9k_hw_setpower(sc->sc_ah, mode);
a91d75ae
LR
137
138 unlock:
139 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
140}
141
05c0be2f 142void ath_start_ani(struct ath_common *common)
5ee08656
FF
143{
144 struct ath_hw *ah = common->ah;
145 unsigned long timestamp = jiffies_to_msecs(jiffies);
146 struct ath_softc *sc = (struct ath_softc *) common->priv;
147
148 if (!(sc->sc_flags & SC_OP_ANI_RUN))
149 return;
150
151 if (sc->sc_flags & SC_OP_OFFCHANNEL)
152 return;
153
154 common->ani.longcal_timer = timestamp;
155 common->ani.shortcal_timer = timestamp;
156 common->ani.checkani_timer = timestamp;
157
158 mod_timer(&common->ani.timer,
159 jiffies +
160 msecs_to_jiffies((u32)ah->config.ani_poll_interval));
161}
162
3430098a
FF
163static void ath_update_survey_nf(struct ath_softc *sc, int channel)
164{
165 struct ath_hw *ah = sc->sc_ah;
166 struct ath9k_channel *chan = &ah->channels[channel];
167 struct survey_info *survey = &sc->survey[channel];
168
169 if (chan->noisefloor) {
170 survey->filled |= SURVEY_INFO_NOISE_DBM;
f749b946 171 survey->noise = ath9k_hw_getchan_noise(ah, chan);
3430098a
FF
172 }
173}
174
cb8d61de
FF
175/*
176 * Updates the survey statistics and returns the busy time since last
177 * update in %, if the measurement duration was long enough for the
178 * result to be useful, -1 otherwise.
179 */
180static int ath_update_survey_stats(struct ath_softc *sc)
3430098a
FF
181{
182 struct ath_hw *ah = sc->sc_ah;
183 struct ath_common *common = ath9k_hw_common(ah);
184 int pos = ah->curchan - &ah->channels[0];
185 struct survey_info *survey = &sc->survey[pos];
186 struct ath_cycle_counters *cc = &common->cc_survey;
187 unsigned int div = common->clockrate * 1000;
cb8d61de 188 int ret = 0;
3430098a 189
0845735e 190 if (!ah->curchan)
cb8d61de 191 return -1;
0845735e 192
898c914a
FF
193 if (ah->power_mode == ATH9K_PM_AWAKE)
194 ath_hw_cycle_counters_update(common);
3430098a
FF
195
196 if (cc->cycles > 0) {
197 survey->filled |= SURVEY_INFO_CHANNEL_TIME |
198 SURVEY_INFO_CHANNEL_TIME_BUSY |
199 SURVEY_INFO_CHANNEL_TIME_RX |
200 SURVEY_INFO_CHANNEL_TIME_TX;
201 survey->channel_time += cc->cycles / div;
202 survey->channel_time_busy += cc->rx_busy / div;
203 survey->channel_time_rx += cc->rx_frame / div;
204 survey->channel_time_tx += cc->tx_frame / div;
205 }
cb8d61de
FF
206
207 if (cc->cycles < div)
208 return -1;
209
210 if (cc->cycles > 0)
211 ret = cc->rx_busy * 100 / cc->cycles;
212
3430098a
FF
213 memset(cc, 0, sizeof(*cc));
214
215 ath_update_survey_nf(sc, pos);
cb8d61de
FF
216
217 return ret;
3430098a
FF
218}
219
9adcf440 220static void __ath_cancel_work(struct ath_softc *sc)
ff37e337 221{
5ee08656
FF
222 cancel_work_sync(&sc->paprd_work);
223 cancel_work_sync(&sc->hw_check_work);
224 cancel_delayed_work_sync(&sc->tx_complete_work);
181fb18d 225 cancel_delayed_work_sync(&sc->hw_pll_work);
9adcf440 226}
5ee08656 227
9adcf440
FF
228static void ath_cancel_work(struct ath_softc *sc)
229{
230 __ath_cancel_work(sc);
231 cancel_work_sync(&sc->hw_reset_work);
232}
3cbb5dd7 233
9adcf440
FF
234static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
235{
236 struct ath_hw *ah = sc->sc_ah;
237 struct ath_common *common = ath9k_hw_common(ah);
238 bool ret;
6a6733f2 239
9adcf440 240 ieee80211_stop_queues(sc->hw);
5e848f78 241
9adcf440
FF
242 sc->hw_busy_count = 0;
243 del_timer_sync(&common->ani.timer);
ff37e337 244
9adcf440
FF
245 ath9k_debug_samp_bb_mac(sc);
246 ath9k_hw_disable_interrupts(ah);
8b3f4616 247
9adcf440 248 ret = ath_drain_all_txq(sc, retry_tx);
ff37e337 249
9adcf440
FF
250 if (!ath_stoprecv(sc))
251 ret = false;
c0d7c7af 252
9adcf440
FF
253 if (!flush) {
254 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
3483288c
FF
255 ath_rx_tasklet(sc, 1, true);
256 ath_rx_tasklet(sc, 1, false);
9adcf440
FF
257 } else {
258 ath_flushrecv(sc);
259 }
20bd2a09 260
9adcf440
FF
261 return ret;
262}
ff37e337 263
9adcf440
FF
264static bool ath_complete_reset(struct ath_softc *sc, bool start)
265{
266 struct ath_hw *ah = sc->sc_ah;
267 struct ath_common *common = ath9k_hw_common(ah);
c0d7c7af 268
c0d7c7af 269 if (ath_startrecv(sc) != 0) {
3800276a 270 ath_err(common, "Unable to restart recv logic\n");
9adcf440 271 return false;
c0d7c7af
LR
272 }
273
5048e8c3
RM
274 ath9k_cmn_update_txpow(ah, sc->curtxpow,
275 sc->config.txpowlimit, &sc->curtxpow);
72d874c6 276 ath9k_hw_set_interrupts(ah);
b037b693 277 ath9k_hw_enable_interrupts(ah);
3989279c 278
9adcf440 279 if (!(sc->sc_flags & (SC_OP_OFFCHANNEL)) && start) {
1186488b 280 if (sc->sc_flags & SC_OP_BEACONS)
99e4d43a 281 ath_set_beacon(sc);
9adcf440 282
5ee08656 283 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
181fb18d 284 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
05c0be2f
MSS
285 if (!common->disable_ani)
286 ath_start_ani(common);
5ee08656
FF
287 }
288
43c35284
FF
289 if (ath9k_hw_ops(ah)->antdiv_comb_conf_get && sc->ant_rx != 3) {
290 struct ath_hw_antcomb_conf div_ant_conf;
291 u8 lna_conf;
292
293 ath9k_hw_antdiv_comb_conf_get(ah, &div_ant_conf);
294
295 if (sc->ant_rx == 1)
296 lna_conf = ATH_ANT_DIV_COMB_LNA1;
297 else
298 lna_conf = ATH_ANT_DIV_COMB_LNA2;
299 div_ant_conf.main_lna_conf = lna_conf;
300 div_ant_conf.alt_lna_conf = lna_conf;
301
302 ath9k_hw_antdiv_comb_conf_set(ah, &div_ant_conf);
303 }
304
9adcf440
FF
305 ieee80211_wake_queues(sc->hw);
306
307 return true;
308}
309
310static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
311 bool retry_tx)
312{
313 struct ath_hw *ah = sc->sc_ah;
314 struct ath_common *common = ath9k_hw_common(ah);
315 struct ath9k_hw_cal_data *caldata = NULL;
316 bool fastcc = true;
317 bool flush = false;
318 int r;
319
320 __ath_cancel_work(sc);
321
322 spin_lock_bh(&sc->sc_pcu_lock);
92460412 323
9adcf440
FF
324 if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) {
325 fastcc = false;
326 caldata = &sc->caldata;
327 }
328
329 if (!hchan) {
330 fastcc = false;
331 flush = true;
332 hchan = ah->curchan;
333 }
334
335 if (fastcc && !ath9k_hw_check_alive(ah))
336 fastcc = false;
337
338 if (!ath_prepare_reset(sc, retry_tx, flush))
339 fastcc = false;
340
341 ath_dbg(common, ATH_DBG_CONFIG,
342 "Reset to %u MHz, HT40: %d fastcc: %d\n",
343 hchan->channel, !!(hchan->channelFlags & (CHANNEL_HT40MINUS |
344 CHANNEL_HT40PLUS)),
345 fastcc);
346
347 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
348 if (r) {
349 ath_err(common,
350 "Unable to reset channel, reset status %d\n", r);
351 goto out;
352 }
353
354 if (!ath_complete_reset(sc, true))
355 r = -EIO;
356
357out:
6a6733f2 358 spin_unlock_bh(&sc->sc_pcu_lock);
9adcf440
FF
359 return r;
360}
361
362
363/*
364 * Set/change channels. If the channel is really being changed, it's done
365 * by reseting the chip. To accomplish this we must first cleanup any pending
366 * DMA, then restart stuff.
367*/
368static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
369 struct ath9k_channel *hchan)
370{
371 int r;
372
373 if (sc->sc_flags & SC_OP_INVALID)
374 return -EIO;
375
376 ath9k_ps_wakeup(sc);
377
378 r = ath_reset_internal(sc, hchan, false);
6a6733f2 379
3cbb5dd7 380 ath9k_ps_restore(sc);
9adcf440 381
3989279c 382 return r;
ff37e337
S
383}
384
9f42c2b6
FF
385static void ath_paprd_activate(struct ath_softc *sc)
386{
387 struct ath_hw *ah = sc->sc_ah;
20bd2a09 388 struct ath9k_hw_cal_data *caldata = ah->caldata;
9f42c2b6
FF
389 int chain;
390
20bd2a09 391 if (!caldata || !caldata->paprd_done)
9f42c2b6
FF
392 return;
393
394 ath9k_ps_wakeup(sc);
ddfef792 395 ar9003_paprd_enable(ah, false);
9f42c2b6 396 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
82b2d334 397 if (!(ah->txchainmask & BIT(chain)))
9f42c2b6
FF
398 continue;
399
20bd2a09 400 ar9003_paprd_populate_single_table(ah, caldata, chain);
9f42c2b6
FF
401 }
402
403 ar9003_paprd_enable(ah, true);
404 ath9k_ps_restore(sc);
405}
406
7607cbe2
FF
407static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
408{
409 struct ieee80211_hw *hw = sc->hw;
410 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
47960077
MSS
411 struct ath_hw *ah = sc->sc_ah;
412 struct ath_common *common = ath9k_hw_common(ah);
7607cbe2
FF
413 struct ath_tx_control txctl;
414 int time_left;
415
416 memset(&txctl, 0, sizeof(txctl));
417 txctl.txq = sc->tx.txq_map[WME_AC_BE];
418
419 memset(tx_info, 0, sizeof(*tx_info));
420 tx_info->band = hw->conf.channel->band;
421 tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
422 tx_info->control.rates[0].idx = 0;
423 tx_info->control.rates[0].count = 1;
424 tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
425 tx_info->control.rates[1].idx = -1;
426
427 init_completion(&sc->paprd_complete);
7607cbe2 428 txctl.paprd = BIT(chain);
47960077
MSS
429
430 if (ath_tx_start(hw, skb, &txctl) != 0) {
d4bb17c4 431 ath_dbg(common, ATH_DBG_CALIBRATE, "PAPRD TX failed\n");
47960077 432 dev_kfree_skb_any(skb);
7607cbe2 433 return false;
47960077 434 }
7607cbe2
FF
435
436 time_left = wait_for_completion_timeout(&sc->paprd_complete,
437 msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
7607cbe2
FF
438
439 if (!time_left)
d4bb17c4 440 ath_dbg(common, ATH_DBG_CALIBRATE,
7607cbe2
FF
441 "Timeout waiting for paprd training on TX chain %d\n",
442 chain);
443
444 return !!time_left;
445}
446
9f42c2b6
FF
447void ath_paprd_calibrate(struct work_struct *work)
448{
449 struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
450 struct ieee80211_hw *hw = sc->hw;
451 struct ath_hw *ah = sc->sc_ah;
452 struct ieee80211_hdr *hdr;
453 struct sk_buff *skb = NULL;
20bd2a09 454 struct ath9k_hw_cal_data *caldata = ah->caldata;
9094537c 455 struct ath_common *common = ath9k_hw_common(ah);
066dae93 456 int ftype;
9f42c2b6
FF
457 int chain_ok = 0;
458 int chain;
459 int len = 1800;
9f42c2b6 460
20bd2a09
FF
461 if (!caldata)
462 return;
463
b942471b
MSS
464 ath9k_ps_wakeup(sc);
465
1bf38661 466 if (ar9003_paprd_init_table(ah) < 0)
b942471b 467 goto fail_paprd;
1bf38661 468
9f42c2b6
FF
469 skb = alloc_skb(len, GFP_KERNEL);
470 if (!skb)
b942471b 471 goto fail_paprd;
9f42c2b6 472
9f42c2b6
FF
473 skb_put(skb, len);
474 memset(skb->data, 0, len);
475 hdr = (struct ieee80211_hdr *)skb->data;
476 ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
477 hdr->frame_control = cpu_to_le16(ftype);
a3d3da14 478 hdr->duration_id = cpu_to_le16(10);
9f42c2b6
FF
479 memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
480 memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
481 memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
482
9f42c2b6 483 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
82b2d334 484 if (!(ah->txchainmask & BIT(chain)))
9f42c2b6
FF
485 continue;
486
487 chain_ok = 0;
9f42c2b6 488
7607cbe2
FF
489 ath_dbg(common, ATH_DBG_CALIBRATE,
490 "Sending PAPRD frame for thermal measurement "
491 "on chain %d\n", chain);
492 if (!ath_paprd_send_frame(sc, skb, chain))
493 goto fail_paprd;
9f42c2b6 494
9f42c2b6 495 ar9003_paprd_setup_gain_table(ah, chain);
9f42c2b6 496
7607cbe2
FF
497 ath_dbg(common, ATH_DBG_CALIBRATE,
498 "Sending PAPRD training frame on chain %d\n", chain);
499 if (!ath_paprd_send_frame(sc, skb, chain))
ca369eb4 500 goto fail_paprd;
9f42c2b6 501
d4bb17c4
MSS
502 if (!ar9003_paprd_is_done(ah)) {
503 ath_dbg(common, ATH_DBG_CALIBRATE,
504 "PAPRD not yet done on chain %d\n", chain);
9f42c2b6 505 break;
d4bb17c4 506 }
9f42c2b6 507
d4bb17c4
MSS
508 if (ar9003_paprd_create_curve(ah, caldata, chain)) {
509 ath_dbg(common, ATH_DBG_CALIBRATE,
510 "PAPRD create curve failed on chain %d\n",
511 chain);
9f42c2b6 512 break;
d4bb17c4 513 }
9f42c2b6
FF
514
515 chain_ok = 1;
516 }
517 kfree_skb(skb);
518
519 if (chain_ok) {
20bd2a09 520 caldata->paprd_done = true;
9f42c2b6
FF
521 ath_paprd_activate(sc);
522 }
523
ca369eb4 524fail_paprd:
9f42c2b6
FF
525 ath9k_ps_restore(sc);
526}
527
ff37e337
S
528/*
529 * This routine performs the periodic noise floor calibration function
530 * that is used to adjust and optimize the chip performance. This
531 * takes environmental changes (location, temperature) into account.
532 * When the task is complete, it reschedules itself depending on the
533 * appropriate interval that was calculated.
534 */
55624204 535void ath_ani_calibrate(unsigned long data)
ff37e337 536{
20977d3e
S
537 struct ath_softc *sc = (struct ath_softc *)data;
538 struct ath_hw *ah = sc->sc_ah;
c46917bb 539 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
540 bool longcal = false;
541 bool shortcal = false;
542 bool aniflag = false;
543 unsigned int timestamp = jiffies_to_msecs(jiffies);
6044474e 544 u32 cal_interval, short_cal_interval, long_cal_interval;
b5bfc568 545 unsigned long flags;
6044474e
FF
546
547 if (ah->caldata && ah->caldata->nfcal_interference)
548 long_cal_interval = ATH_LONG_CALINTERVAL_INT;
549 else
550 long_cal_interval = ATH_LONG_CALINTERVAL;
ff37e337 551
20977d3e
S
552 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
553 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337 554
1ffc1c61
JM
555 /* Only calibrate if awake */
556 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
557 goto set_timer;
558
559 ath9k_ps_wakeup(sc);
560
ff37e337 561 /* Long calibration runs independently of short calibration. */
6044474e 562 if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
ff37e337 563 longcal = true;
226afe68 564 ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
3d536acf 565 common->ani.longcal_timer = timestamp;
ff37e337
S
566 }
567
17d7904d 568 /* Short calibration applies only while caldone is false */
3d536acf
LR
569 if (!common->ani.caldone) {
570 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 571 shortcal = true;
226afe68
JP
572 ath_dbg(common, ATH_DBG_ANI,
573 "shortcal @%lu\n", jiffies);
3d536acf
LR
574 common->ani.shortcal_timer = timestamp;
575 common->ani.resetcal_timer = timestamp;
ff37e337
S
576 }
577 } else {
3d536acf 578 if ((timestamp - common->ani.resetcal_timer) >=
ff37e337 579 ATH_RESTART_CALINTERVAL) {
3d536acf
LR
580 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
581 if (common->ani.caldone)
582 common->ani.resetcal_timer = timestamp;
ff37e337
S
583 }
584 }
585
586 /* Verify whether we must check ANI */
e36b27af
LR
587 if ((timestamp - common->ani.checkani_timer) >=
588 ah->config.ani_poll_interval) {
ff37e337 589 aniflag = true;
3d536acf 590 common->ani.checkani_timer = timestamp;
ff37e337
S
591 }
592
e62ddec9
MSS
593 /* Call ANI routine if necessary */
594 if (aniflag) {
595 spin_lock_irqsave(&common->cc_lock, flags);
596 ath9k_hw_ani_monitor(ah, ah->curchan);
597 ath_update_survey_stats(sc);
598 spin_unlock_irqrestore(&common->cc_lock, flags);
599 }
ff37e337 600
e62ddec9
MSS
601 /* Perform calibration if necessary */
602 if (longcal || shortcal) {
603 common->ani.caldone =
604 ath9k_hw_calibrate(ah, ah->curchan,
82b2d334 605 ah->rxchainmask, longcal);
ff37e337
S
606 }
607
1ffc1c61
JM
608 ath9k_ps_restore(sc);
609
20977d3e 610set_timer:
ff37e337
S
611 /*
612 * Set timer interval based on previous results.
613 * The interval must be the shortest necessary to satisfy ANI,
614 * short calibration and long calibration.
615 */
cf3af748 616 ath9k_debug_samp_bb_mac(sc);
aac9207e 617 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 618 if (sc->sc_ah->config.enable_ani)
e36b27af
LR
619 cal_interval = min(cal_interval,
620 (u32)ah->config.ani_poll_interval);
3d536acf 621 if (!common->ani.caldone)
20977d3e 622 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 623
3d536acf 624 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
20bd2a09
FF
625 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
626 if (!ah->caldata->paprd_done)
9f42c2b6 627 ieee80211_queue_work(sc->hw, &sc->paprd_work);
45ef6a0b 628 else if (!ah->paprd_table_write_done)
9f42c2b6
FF
629 ath_paprd_activate(sc);
630 }
ff37e337
S
631}
632
ff37e337
S
633static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
634{
635 struct ath_node *an;
ff37e337
S
636 an = (struct ath_node *)sta->drv_priv;
637
7f010c93
BG
638#ifdef CONFIG_ATH9K_DEBUGFS
639 spin_lock(&sc->nodes_lock);
640 list_add(&an->list, &sc->nodes);
641 spin_unlock(&sc->nodes_lock);
642 an->sta = sta;
643#endif
87792efc 644 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 645 ath_tx_node_init(sc, an);
9e98ac65 646 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S
647 sta->ht_cap.ampdu_factor);
648 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
649 }
ff37e337
S
650}
651
652static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
653{
654 struct ath_node *an = (struct ath_node *)sta->drv_priv;
655
7f010c93
BG
656#ifdef CONFIG_ATH9K_DEBUGFS
657 spin_lock(&sc->nodes_lock);
658 list_del(&an->list);
659 spin_unlock(&sc->nodes_lock);
660 an->sta = NULL;
661#endif
662
ff37e337
S
663 if (sc->sc_flags & SC_OP_TXAGGR)
664 ath_tx_node_cleanup(sc, an);
665}
666
9eab61c2 667
55624204 668void ath9k_tasklet(unsigned long data)
ff37e337
S
669{
670 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 671 struct ath_hw *ah = sc->sc_ah;
c46917bb 672 struct ath_common *common = ath9k_hw_common(ah);
af03abec 673
17d7904d 674 u32 status = sc->intrstatus;
b5c80475 675 u32 rxmask;
ff37e337 676
e3927007
FF
677 ath9k_ps_wakeup(sc);
678 spin_lock(&sc->sc_pcu_lock);
679
a4d86d95
RM
680 if ((status & ATH9K_INT_FATAL) ||
681 (status & ATH9K_INT_BB_WATCHDOG)) {
030d6294
FF
682#ifdef CONFIG_ATH9K_DEBUGFS
683 enum ath_reset_type type;
684
685 if (status & ATH9K_INT_FATAL)
686 type = RESET_TYPE_FATAL_INT;
687 else
688 type = RESET_TYPE_BB_WATCHDOG;
689
690 RESET_STAT_INC(sc, type);
691#endif
236de514 692 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
e3927007 693 goto out;
063d8be3 694 }
ff37e337 695
8b3f4616
FF
696 /*
697 * Only run the baseband hang check if beacons stop working in AP or
698 * IBSS mode, because it has a high false positive rate. For station
699 * mode it should not be necessary, since the upper layers will detect
700 * this through a beacon miss automatically and the following channel
701 * change will trigger a hardware reset anyway
702 */
703 if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 &&
704 !ath9k_hw_check_alive(ah))
347809fc
FF
705 ieee80211_queue_work(sc->hw, &sc->hw_check_work);
706
4105f807
RM
707 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
708 /*
709 * TSF sync does not look correct; remain awake to sync with
710 * the next Beacon.
711 */
712 ath_dbg(common, ATH_DBG_PS,
713 "TSFOOR - Sync with next Beacon\n");
e8fe7336 714 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
4105f807
RM
715 }
716
b5c80475
FF
717 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
718 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
719 ATH9K_INT_RXORN);
720 else
721 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
722
723 if (status & rxmask) {
b5c80475
FF
724 /* Check for high priority Rx first */
725 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
726 (status & ATH9K_INT_RXHP))
727 ath_rx_tasklet(sc, 0, true);
728
729 ath_rx_tasklet(sc, 0, false);
ff37e337
S
730 }
731
e5003249
VT
732 if (status & ATH9K_INT_TX) {
733 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
734 ath_tx_edma_tasklet(sc);
735 else
736 ath_tx_tasklet(sc);
737 }
063d8be3 738
766ec4a9 739 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
ebb8e1d7
VT
740 if (status & ATH9K_INT_GENTIMER)
741 ath_gen_timer_isr(sc->sc_ah);
742
e3927007 743out:
ff37e337 744 /* re-enable hardware interrupt */
4df3071e 745 ath9k_hw_enable_interrupts(ah);
6a6733f2 746
52671e43 747 spin_unlock(&sc->sc_pcu_lock);
153e080d 748 ath9k_ps_restore(sc);
ff37e337
S
749}
750
6baff7f9 751irqreturn_t ath_isr(int irq, void *dev)
ff37e337 752{
063d8be3
S
753#define SCHED_INTR ( \
754 ATH9K_INT_FATAL | \
a4d86d95 755 ATH9K_INT_BB_WATCHDOG | \
063d8be3
S
756 ATH9K_INT_RXORN | \
757 ATH9K_INT_RXEOL | \
758 ATH9K_INT_RX | \
b5c80475
FF
759 ATH9K_INT_RXLP | \
760 ATH9K_INT_RXHP | \
063d8be3
S
761 ATH9K_INT_TX | \
762 ATH9K_INT_BMISS | \
763 ATH9K_INT_CST | \
ebb8e1d7
VT
764 ATH9K_INT_TSFOOR | \
765 ATH9K_INT_GENTIMER)
063d8be3 766
ff37e337 767 struct ath_softc *sc = dev;
cbe61d8a 768 struct ath_hw *ah = sc->sc_ah;
b5bfc568 769 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
770 enum ath9k_int status;
771 bool sched = false;
772
063d8be3
S
773 /*
774 * The hardware is not ready/present, don't
775 * touch anything. Note this can happen early
776 * on if the IRQ is shared.
777 */
778 if (sc->sc_flags & SC_OP_INVALID)
779 return IRQ_NONE;
ff37e337 780
063d8be3
S
781
782 /* shared irq, not for us */
783
153e080d 784 if (!ath9k_hw_intrpend(ah))
063d8be3 785 return IRQ_NONE;
063d8be3
S
786
787 /*
788 * Figure out the reason(s) for the interrupt. Note
789 * that the hal returns a pseudo-ISR that may include
790 * bits we haven't explicitly enabled so we mask the
791 * value to insure we only process bits we requested.
792 */
793 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
3069168c 794 status &= ah->imask; /* discard unasked-for bits */
ff37e337 795
063d8be3
S
796 /*
797 * If there are no status bits set, then this interrupt was not
798 * for me (should have been caught above).
799 */
153e080d 800 if (!status)
063d8be3 801 return IRQ_NONE;
ff37e337 802
063d8be3
S
803 /* Cache the status */
804 sc->intrstatus = status;
805
806 if (status & SCHED_INTR)
807 sched = true;
808
809 /*
810 * If a FATAL or RXORN interrupt is received, we have to reset the
811 * chip immediately.
812 */
b5c80475
FF
813 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
814 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
063d8be3
S
815 goto chip_reset;
816
08578b8f
LR
817 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
818 (status & ATH9K_INT_BB_WATCHDOG)) {
b5bfc568
FF
819
820 spin_lock(&common->cc_lock);
821 ath_hw_cycle_counters_update(common);
08578b8f 822 ar9003_hw_bb_watchdog_dbg_info(ah);
b5bfc568
FF
823 spin_unlock(&common->cc_lock);
824
08578b8f
LR
825 goto chip_reset;
826 }
827
063d8be3
S
828 if (status & ATH9K_INT_SWBA)
829 tasklet_schedule(&sc->bcon_tasklet);
830
831 if (status & ATH9K_INT_TXURN)
832 ath9k_hw_updatetxtriglevel(ah, true);
833
0682c9b5
RM
834 if (status & ATH9K_INT_RXEOL) {
835 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
72d874c6 836 ath9k_hw_set_interrupts(ah);
b5c80475
FF
837 }
838
063d8be3 839 if (status & ATH9K_INT_MIB) {
ff37e337 840 /*
063d8be3
S
841 * Disable interrupts until we service the MIB
842 * interrupt; otherwise it will continue to
843 * fire.
ff37e337 844 */
4df3071e 845 ath9k_hw_disable_interrupts(ah);
063d8be3
S
846 /*
847 * Let the hal handle the event. We assume
848 * it will clear whatever condition caused
849 * the interrupt.
850 */
88eac2da 851 spin_lock(&common->cc_lock);
bfc472bb 852 ath9k_hw_proc_mib_event(ah);
88eac2da 853 spin_unlock(&common->cc_lock);
4df3071e 854 ath9k_hw_enable_interrupts(ah);
063d8be3 855 }
ff37e337 856
153e080d
VT
857 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
858 if (status & ATH9K_INT_TIM_TIMER) {
ff9f0b63
LR
859 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
860 goto chip_reset;
063d8be3
S
861 /* Clear RxAbort bit so that we can
862 * receive frames */
9ecdef4b 863 ath9k_setpower(sc, ATH9K_PM_AWAKE);
153e080d 864 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930 865 sc->ps_flags |= PS_WAIT_FOR_BEACON;
ff37e337 866 }
063d8be3
S
867
868chip_reset:
ff37e337 869
817e11de
S
870 ath_debug_stat_interrupt(sc, status);
871
ff37e337 872 if (sched) {
4df3071e
FF
873 /* turn off every interrupt */
874 ath9k_hw_disable_interrupts(ah);
ff37e337
S
875 tasklet_schedule(&sc->intr_tq);
876 }
877
878 return IRQ_HANDLED;
063d8be3
S
879
880#undef SCHED_INTR
ff37e337
S
881}
882
5595f119 883static void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 884{
cbe61d8a 885 struct ath_hw *ah = sc->sc_ah;
c46917bb 886 struct ath_common *common = ath9k_hw_common(ah);
68a89116 887 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 888 int r;
500c064d 889
3cbb5dd7 890 ath9k_ps_wakeup(sc);
6a6733f2 891 spin_lock_bh(&sc->sc_pcu_lock);
e8fe7336 892 atomic_set(&ah->intr_ref_cnt, -1);
6a6733f2 893
84c87dc8 894 ath9k_hw_configpcipowersave(ah, false);
ae8d2858 895
159cd468 896 if (!ah->curchan)
c344c9cb 897 ah->curchan = ath9k_cmn_get_curchannel(sc->hw, ah);
159cd468 898
20bd2a09 899 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ae8d2858 900 if (r) {
3800276a
JP
901 ath_err(common,
902 "Unable to reset channel (%u MHz), reset status %d\n",
903 channel->center_freq, r);
500c064d 904 }
500c064d 905
9adcf440 906 ath_complete_reset(sc, true);
500c064d
VT
907
908 /* Enable LED */
08fc5c1b 909 ath9k_hw_cfg_output(ah, ah->led_pin,
500c064d 910 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b 911 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
500c064d 912
6a6733f2
LR
913 spin_unlock_bh(&sc->sc_pcu_lock);
914
3cbb5dd7 915 ath9k_ps_restore(sc);
500c064d
VT
916}
917
68a89116 918void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 919{
cbe61d8a 920 struct ath_hw *ah = sc->sc_ah;
68a89116 921 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 922 int r;
500c064d 923
3cbb5dd7 924 ath9k_ps_wakeup(sc);
7e3514fd 925
9adcf440 926 ath_cancel_work(sc);
6a6733f2 927
9adcf440 928 spin_lock_bh(&sc->sc_pcu_lock);
500c064d 929
982723df
VN
930 /*
931 * Keep the LED on when the radio is disabled
932 * during idle unassociated state.
933 */
934 if (!sc->ps_idle) {
935 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
936 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
937 }
500c064d 938
9adcf440 939 ath_prepare_reset(sc, false, true);
500c064d 940
159cd468 941 if (!ah->curchan)
c344c9cb 942 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
159cd468 943
20bd2a09 944 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ae8d2858 945 if (r) {
3800276a
JP
946 ath_err(ath9k_hw_common(sc->sc_ah),
947 "Unable to reset channel (%u MHz), reset status %d\n",
948 channel->center_freq, r);
500c064d 949 }
500c064d
VT
950
951 ath9k_hw_phy_disable(ah);
5e848f78 952
84c87dc8 953 ath9k_hw_configpcipowersave(ah, true);
6a6733f2
LR
954
955 spin_unlock_bh(&sc->sc_pcu_lock);
3cbb5dd7 956 ath9k_ps_restore(sc);
500c064d
VT
957}
958
236de514 959static int ath_reset(struct ath_softc *sc, bool retry_tx)
ff37e337 960{
ae8d2858 961 int r;
ff37e337 962
783cd01e 963 ath9k_ps_wakeup(sc);
6a6733f2 964
9adcf440 965 r = ath_reset_internal(sc, NULL, retry_tx);
ff37e337
S
966
967 if (retry_tx) {
968 int i;
969 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
970 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S
971 spin_lock_bh(&sc->tx.txq[i].axq_lock);
972 ath_txq_schedule(sc, &sc->tx.txq[i]);
973 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S
974 }
975 }
976 }
977
783cd01e 978 ath9k_ps_restore(sc);
2ab81d4a 979
ae8d2858 980 return r;
ff37e337
S
981}
982
236de514
FF
983void ath_reset_work(struct work_struct *work)
984{
985 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
986
236de514 987 ath_reset(sc, true);
236de514
FF
988}
989
e8cfe9f8
FF
990void ath_hw_check(struct work_struct *work)
991{
992 struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
993 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
994 unsigned long flags;
995 int busy;
996
997 ath9k_ps_wakeup(sc);
998 if (ath9k_hw_check_alive(sc->sc_ah))
999 goto out;
1000
1001 spin_lock_irqsave(&common->cc_lock, flags);
1002 busy = ath_update_survey_stats(sc);
1003 spin_unlock_irqrestore(&common->cc_lock, flags);
1004
1005 ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, "
1006 "busy=%d (try %d)\n", busy, sc->hw_busy_count + 1);
1007 if (busy >= 99) {
030d6294
FF
1008 if (++sc->hw_busy_count >= 3) {
1009 RESET_STAT_INC(sc, RESET_TYPE_BB_HANG);
9adcf440 1010 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
030d6294 1011 }
e8cfe9f8
FF
1012
1013 } else if (busy >= 0)
1014 sc->hw_busy_count = 0;
1015
1016out:
1017 ath9k_ps_restore(sc);
1018}
1019
1020static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)
1021{
1022 static int count;
1023 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1024
1025 if (pll_sqsum >= 0x40000) {
1026 count++;
1027 if (count == 3) {
1028 /* Rx is hung for more than 500ms. Reset it */
1029 ath_dbg(common, ATH_DBG_RESET,
1030 "Possible RX hang, resetting");
030d6294 1031 RESET_STAT_INC(sc, RESET_TYPE_PLL_HANG);
9adcf440 1032 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
e8cfe9f8
FF
1033 count = 0;
1034 }
1035 } else
1036 count = 0;
1037}
1038
1039void ath_hw_pll_work(struct work_struct *work)
1040{
1041 struct ath_softc *sc = container_of(work, struct ath_softc,
1042 hw_pll_work.work);
1043 u32 pll_sqsum;
1044
1045 if (AR_SREV_9485(sc->sc_ah)) {
1046
1047 ath9k_ps_wakeup(sc);
1048 pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah);
1049 ath9k_ps_restore(sc);
1050
1051 ath_hw_pll_rx_hang_check(sc, pll_sqsum);
1052
1053 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5);
1054 }
1055}
1056
ff37e337
S
1057/**********************/
1058/* mac80211 callbacks */
1059/**********************/
1060
8feceb67 1061static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1062{
9ac58615 1063 struct ath_softc *sc = hw->priv;
af03abec 1064 struct ath_hw *ah = sc->sc_ah;
c46917bb 1065 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 1066 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1067 struct ath9k_channel *init_channel;
82880a7c 1068 int r;
f078f209 1069
226afe68
JP
1070 ath_dbg(common, ATH_DBG_CONFIG,
1071 "Starting driver with initial channel: %d MHz\n",
1072 curchan->center_freq);
f078f209 1073
f62d816f
FF
1074 ath9k_ps_wakeup(sc);
1075
141b38b6
S
1076 mutex_lock(&sc->mutex);
1077
8feceb67 1078 /* setup initial channel */
82880a7c 1079 sc->chan_idx = curchan->hw_value;
f078f209 1080
c344c9cb 1081 init_channel = ath9k_cmn_get_curchannel(hw, ah);
ff37e337
S
1082
1083 /* Reset SERDES registers */
84c87dc8 1084 ath9k_hw_configpcipowersave(ah, false);
ff37e337
S
1085
1086 /*
1087 * The basic interface to setting the hardware in a good
1088 * state is ``reset''. On return the hardware is known to
1089 * be powered up and with interrupts disabled. This must
1090 * be followed by initialization of the appropriate bits
1091 * and then setup of the interrupt mask.
1092 */
4bdd1e97 1093 spin_lock_bh(&sc->sc_pcu_lock);
20bd2a09 1094 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
ae8d2858 1095 if (r) {
3800276a
JP
1096 ath_err(common,
1097 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
1098 r, curchan->center_freq);
4bdd1e97 1099 spin_unlock_bh(&sc->sc_pcu_lock);
141b38b6 1100 goto mutex_unlock;
ff37e337 1101 }
ff37e337 1102
ff37e337 1103 /* Setup our intr mask. */
b5c80475
FF
1104 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
1105 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
1106 ATH9K_INT_GLOBAL;
1107
1108 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
08578b8f
LR
1109 ah->imask |= ATH9K_INT_RXHP |
1110 ATH9K_INT_RXLP |
1111 ATH9K_INT_BB_WATCHDOG;
b5c80475
FF
1112 else
1113 ah->imask |= ATH9K_INT_RX;
ff37e337 1114
364734fa 1115 ah->imask |= ATH9K_INT_GTT;
ff37e337 1116
af03abec 1117 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
3069168c 1118 ah->imask |= ATH9K_INT_CST;
ff37e337 1119
ff37e337 1120 sc->sc_flags &= ~SC_OP_INVALID;
5f841b41 1121 sc->sc_ah->is_monitoring = false;
ff37e337
S
1122
1123 /* Disable BMISS interrupt when we're not associated */
3069168c 1124 ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
ff37e337 1125
9adcf440
FF
1126 if (!ath_complete_reset(sc, false)) {
1127 r = -EIO;
1128 spin_unlock_bh(&sc->sc_pcu_lock);
1129 goto mutex_unlock;
1130 }
ff37e337 1131
9adcf440 1132 spin_unlock_bh(&sc->sc_pcu_lock);
164ace38 1133
766ec4a9
LR
1134 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
1135 !ah->btcoex_hw.enabled) {
5e197292
LR
1136 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1137 AR_STOMP_LOW_WLAN_WGHT);
af03abec 1138 ath9k_hw_btcoex_enable(ah);
f985ad12 1139
766ec4a9 1140 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1141 ath9k_btcoex_timer_resume(sc);
1773912b
VT
1142 }
1143
8060e169
VT
1144 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
1145 common->bus_ops->extn_synch_en(common);
1146
141b38b6
S
1147mutex_unlock:
1148 mutex_unlock(&sc->mutex);
1149
f62d816f
FF
1150 ath9k_ps_restore(sc);
1151
ae8d2858 1152 return r;
f078f209
LR
1153}
1154
7bb45683 1155static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
f078f209 1156{
9ac58615 1157 struct ath_softc *sc = hw->priv;
c46917bb 1158 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 1159 struct ath_tx_control txctl;
1bc14880 1160 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
528f0c6b 1161
96148326 1162 if (sc->ps_enabled) {
dc8c4585
JM
1163 /*
1164 * mac80211 does not set PM field for normal data frames, so we
1165 * need to update that based on the current PS mode.
1166 */
1167 if (ieee80211_is_data(hdr->frame_control) &&
1168 !ieee80211_is_nullfunc(hdr->frame_control) &&
1169 !ieee80211_has_pm(hdr->frame_control)) {
226afe68
JP
1170 ath_dbg(common, ATH_DBG_PS,
1171 "Add PM=1 for a TX frame while in PS mode\n");
dc8c4585
JM
1172 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1173 }
1174 }
1175
9a23f9ca
JM
1176 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
1177 /*
1178 * We are using PS-Poll and mac80211 can request TX while in
1179 * power save mode. Need to wake up hardware for the TX to be
1180 * completed and if needed, also for RX of buffered frames.
1181 */
9a23f9ca 1182 ath9k_ps_wakeup(sc);
fdf76622
VT
1183 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
1184 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca 1185 if (ieee80211_is_pspoll(hdr->frame_control)) {
226afe68
JP
1186 ath_dbg(common, ATH_DBG_PS,
1187 "Sending PS-Poll to pick a buffered frame\n");
1b04b930 1188 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
9a23f9ca 1189 } else {
226afe68
JP
1190 ath_dbg(common, ATH_DBG_PS,
1191 "Wake up to complete TX\n");
1b04b930 1192 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
9a23f9ca
JM
1193 }
1194 /*
1195 * The actual restore operation will happen only after
1196 * the sc_flags bit is cleared. We are just dropping
1197 * the ps_usecount here.
1198 */
1199 ath9k_ps_restore(sc);
1200 }
1201
528f0c6b 1202 memset(&txctl, 0, sizeof(struct ath_tx_control));
066dae93 1203 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
528f0c6b 1204
226afe68 1205 ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 1206
c52f33d0 1207 if (ath_tx_start(hw, skb, &txctl) != 0) {
226afe68 1208 ath_dbg(common, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 1209 goto exit;
8feceb67
VT
1210 }
1211
7bb45683 1212 return;
528f0c6b
S
1213exit:
1214 dev_kfree_skb_any(skb);
f078f209
LR
1215}
1216
8feceb67 1217static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 1218{
9ac58615 1219 struct ath_softc *sc = hw->priv;
af03abec 1220 struct ath_hw *ah = sc->sc_ah;
c46917bb 1221 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1222
4c483817
S
1223 mutex_lock(&sc->mutex);
1224
9adcf440 1225 ath_cancel_work(sc);
c94dbff7 1226
9c84b797 1227 if (sc->sc_flags & SC_OP_INVALID) {
226afe68 1228 ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
4c483817 1229 mutex_unlock(&sc->mutex);
9c84b797
S
1230 return;
1231 }
8feceb67 1232
3867cf6a
S
1233 /* Ensure HW is awake when we try to shut it down. */
1234 ath9k_ps_wakeup(sc);
1235
766ec4a9 1236 if (ah->btcoex_hw.enabled) {
af03abec 1237 ath9k_hw_btcoex_disable(ah);
766ec4a9 1238 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1239 ath9k_btcoex_timer_pause(sc);
1773912b
VT
1240 }
1241
6a6733f2
LR
1242 spin_lock_bh(&sc->sc_pcu_lock);
1243
203043f5
SG
1244 /* prevent tasklets to enable interrupts once we disable them */
1245 ah->imask &= ~ATH9K_INT_GLOBAL;
1246
ff37e337
S
1247 /* make sure h/w will not generate any interrupt
1248 * before setting the invalid flag. */
4df3071e 1249 ath9k_hw_disable_interrupts(ah);
ff37e337
S
1250
1251 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 1252 ath_drain_all_txq(sc, false);
ff37e337 1253 ath_stoprecv(sc);
af03abec 1254 ath9k_hw_phy_disable(ah);
6a6733f2 1255 } else
b77f483f 1256 sc->rx.rxlink = NULL;
ff37e337 1257
0d95521e
FF
1258 if (sc->rx.frag) {
1259 dev_kfree_skb_any(sc->rx.frag);
1260 sc->rx.frag = NULL;
1261 }
1262
ff37e337 1263 /* disable HAL and put h/w to sleep */
af03abec 1264 ath9k_hw_disable(ah);
6a6733f2
LR
1265
1266 spin_unlock_bh(&sc->sc_pcu_lock);
1267
203043f5
SG
1268 /* we can now sync irq and kill any running tasklets, since we already
1269 * disabled interrupts and not holding a spin lock */
1270 synchronize_irq(sc->irq);
1271 tasklet_kill(&sc->intr_tq);
1272 tasklet_kill(&sc->bcon_tasklet);
1273
3867cf6a
S
1274 ath9k_ps_restore(sc);
1275
a08e7ade
LR
1276 sc->ps_idle = true;
1277 ath_radio_disable(sc, hw);
ff37e337
S
1278
1279 sc->sc_flags |= SC_OP_INVALID;
500c064d 1280
141b38b6
S
1281 mutex_unlock(&sc->mutex);
1282
226afe68 1283 ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR
1284}
1285
4801416c
BG
1286bool ath9k_uses_beacons(int type)
1287{
1288 switch (type) {
1289 case NL80211_IFTYPE_AP:
1290 case NL80211_IFTYPE_ADHOC:
1291 case NL80211_IFTYPE_MESH_POINT:
1292 return true;
1293 default:
1294 return false;
1295 }
1296}
1297
1298static void ath9k_reclaim_beacon(struct ath_softc *sc,
1299 struct ieee80211_vif *vif)
f078f209 1300{
1ed32e4f 1301 struct ath_vif *avp = (void *)vif->drv_priv;
8feceb67 1302
014cf3bb 1303 ath9k_set_beaconing_status(sc, false);
4801416c 1304 ath_beacon_return(sc, avp);
014cf3bb 1305 ath9k_set_beaconing_status(sc, true);
4801416c 1306 sc->sc_flags &= ~SC_OP_BEACONS;
4801416c
BG
1307}
1308
1309static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1310{
1311 struct ath9k_vif_iter_data *iter_data = data;
1312 int i;
1313
1314 if (iter_data->hw_macaddr)
1315 for (i = 0; i < ETH_ALEN; i++)
1316 iter_data->mask[i] &=
1317 ~(iter_data->hw_macaddr[i] ^ mac[i]);
141b38b6 1318
1ed32e4f 1319 switch (vif->type) {
4801416c
BG
1320 case NL80211_IFTYPE_AP:
1321 iter_data->naps++;
f078f209 1322 break;
4801416c
BG
1323 case NL80211_IFTYPE_STATION:
1324 iter_data->nstations++;
e51f3eff 1325 break;
05c914fe 1326 case NL80211_IFTYPE_ADHOC:
4801416c
BG
1327 iter_data->nadhocs++;
1328 break;
9cb5412b 1329 case NL80211_IFTYPE_MESH_POINT:
4801416c
BG
1330 iter_data->nmeshes++;
1331 break;
1332 case NL80211_IFTYPE_WDS:
1333 iter_data->nwds++;
f078f209
LR
1334 break;
1335 default:
4801416c
BG
1336 iter_data->nothers++;
1337 break;
f078f209 1338 }
4801416c 1339}
f078f209 1340
4801416c
BG
1341/* Called with sc->mutex held. */
1342void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
1343 struct ieee80211_vif *vif,
1344 struct ath9k_vif_iter_data *iter_data)
1345{
9ac58615 1346 struct ath_softc *sc = hw->priv;
4801416c
BG
1347 struct ath_hw *ah = sc->sc_ah;
1348 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 1349
4801416c
BG
1350 /*
1351 * Use the hardware MAC address as reference, the hardware uses it
1352 * together with the BSSID mask when matching addresses.
1353 */
1354 memset(iter_data, 0, sizeof(*iter_data));
1355 iter_data->hw_macaddr = common->macaddr;
1356 memset(&iter_data->mask, 0xff, ETH_ALEN);
5640b08e 1357
4801416c
BG
1358 if (vif)
1359 ath9k_vif_iter(iter_data, vif->addr, vif);
1360
1361 /* Get list of all active MAC addresses */
4801416c
BG
1362 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
1363 iter_data);
4801416c 1364}
8ca21f01 1365
4801416c
BG
1366/* Called with sc->mutex held. */
1367static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
1368 struct ieee80211_vif *vif)
1369{
9ac58615 1370 struct ath_softc *sc = hw->priv;
4801416c
BG
1371 struct ath_hw *ah = sc->sc_ah;
1372 struct ath_common *common = ath9k_hw_common(ah);
1373 struct ath9k_vif_iter_data iter_data;
8ca21f01 1374
4801416c 1375 ath9k_calculate_iter_data(hw, vif, &iter_data);
2c3db3d5 1376
4801416c
BG
1377 /* Set BSSID mask. */
1378 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1379 ath_hw_setbssidmask(common);
1380
1381 /* Set op-mode & TSF */
1382 if (iter_data.naps > 0) {
3069168c 1383 ath9k_hw_set_tsfadjust(ah, 1);
b238e90e 1384 sc->sc_flags |= SC_OP_TSF_RESET;
4801416c
BG
1385 ah->opmode = NL80211_IFTYPE_AP;
1386 } else {
1387 ath9k_hw_set_tsfadjust(ah, 0);
1388 sc->sc_flags &= ~SC_OP_TSF_RESET;
5640b08e 1389
fd5999cf
JC
1390 if (iter_data.nmeshes)
1391 ah->opmode = NL80211_IFTYPE_MESH_POINT;
1392 else if (iter_data.nwds)
4801416c
BG
1393 ah->opmode = NL80211_IFTYPE_AP;
1394 else if (iter_data.nadhocs)
1395 ah->opmode = NL80211_IFTYPE_ADHOC;
1396 else
1397 ah->opmode = NL80211_IFTYPE_STATION;
1398 }
5640b08e 1399
4e30ffa2
VN
1400 /*
1401 * Enable MIB interrupts when there are hardware phy counters.
4e30ffa2 1402 */
4801416c 1403 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
3448f912
LR
1404 if (ah->config.enable_ani)
1405 ah->imask |= ATH9K_INT_MIB;
3069168c 1406 ah->imask |= ATH9K_INT_TSFOOR;
4801416c
BG
1407 } else {
1408 ah->imask &= ~ATH9K_INT_MIB;
1409 ah->imask &= ~ATH9K_INT_TSFOOR;
4af9cf4f
S
1410 }
1411
72d874c6 1412 ath9k_hw_set_interrupts(ah);
4e30ffa2 1413
4801416c 1414 /* Set up ANI */
2e5ef459 1415 if (iter_data.naps > 0) {
729da390 1416 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
05c0be2f
MSS
1417
1418 if (!common->disable_ani) {
1419 sc->sc_flags |= SC_OP_ANI_RUN;
1420 ath_start_ani(common);
1421 }
1422
f60c49b6
RM
1423 } else {
1424 sc->sc_flags &= ~SC_OP_ANI_RUN;
1425 del_timer_sync(&common->ani.timer);
6c3118e2 1426 }
4801416c 1427}
6f255425 1428
4801416c
BG
1429/* Called with sc->mutex held, vif counts set up properly. */
1430static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
1431 struct ieee80211_vif *vif)
1432{
9ac58615 1433 struct ath_softc *sc = hw->priv;
4801416c
BG
1434
1435 ath9k_calculate_summary_state(hw, vif);
1436
1437 if (ath9k_uses_beacons(vif->type)) {
1438 int error;
4801416c
BG
1439 /* This may fail because upper levels do not have beacons
1440 * properly configured yet. That's OK, we assume it
1441 * will be properly configured and then we will be notified
1442 * in the info_changed method and set up beacons properly
1443 * there.
1444 */
014cf3bb 1445 ath9k_set_beaconing_status(sc, false);
9ac58615 1446 error = ath_beacon_alloc(sc, vif);
391bd1c4 1447 if (!error)
4801416c 1448 ath_beacon_config(sc, vif);
014cf3bb 1449 ath9k_set_beaconing_status(sc, true);
4801416c 1450 }
f078f209
LR
1451}
1452
4801416c
BG
1453
1454static int ath9k_add_interface(struct ieee80211_hw *hw,
1455 struct ieee80211_vif *vif)
6b3b991d 1456{
9ac58615 1457 struct ath_softc *sc = hw->priv;
4801416c
BG
1458 struct ath_hw *ah = sc->sc_ah;
1459 struct ath_common *common = ath9k_hw_common(ah);
4801416c 1460 int ret = 0;
6b3b991d 1461
96f372c9 1462 ath9k_ps_wakeup(sc);
4801416c 1463 mutex_lock(&sc->mutex);
6b3b991d 1464
4801416c
BG
1465 switch (vif->type) {
1466 case NL80211_IFTYPE_STATION:
1467 case NL80211_IFTYPE_WDS:
1468 case NL80211_IFTYPE_ADHOC:
1469 case NL80211_IFTYPE_AP:
1470 case NL80211_IFTYPE_MESH_POINT:
1471 break;
1472 default:
1473 ath_err(common, "Interface type %d not yet supported\n",
1474 vif->type);
1475 ret = -EOPNOTSUPP;
1476 goto out;
1477 }
6b3b991d 1478
4801416c
BG
1479 if (ath9k_uses_beacons(vif->type)) {
1480 if (sc->nbcnvifs >= ATH_BCBUF) {
1481 ath_err(common, "Not enough beacon buffers when adding"
1482 " new interface of type: %i\n",
1483 vif->type);
1484 ret = -ENOBUFS;
1485 goto out;
1486 }
1487 }
1488
59575d1c
RM
1489 if ((ah->opmode == NL80211_IFTYPE_ADHOC) ||
1490 ((vif->type == NL80211_IFTYPE_ADHOC) &&
1491 sc->nvifs > 0)) {
4801416c
BG
1492 ath_err(common, "Cannot create ADHOC interface when other"
1493 " interfaces already exist.\n");
1494 ret = -EINVAL;
1495 goto out;
6b3b991d 1496 }
4801416c
BG
1497
1498 ath_dbg(common, ATH_DBG_CONFIG,
1499 "Attach a VIF of type: %d\n", vif->type);
1500
4801416c
BG
1501 sc->nvifs++;
1502
1503 ath9k_do_vif_add_setup(hw, vif);
1504out:
1505 mutex_unlock(&sc->mutex);
96f372c9 1506 ath9k_ps_restore(sc);
4801416c 1507 return ret;
6b3b991d
RM
1508}
1509
1510static int ath9k_change_interface(struct ieee80211_hw *hw,
1511 struct ieee80211_vif *vif,
1512 enum nl80211_iftype new_type,
1513 bool p2p)
1514{
9ac58615 1515 struct ath_softc *sc = hw->priv;
6b3b991d 1516 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
6dab55bf 1517 int ret = 0;
6b3b991d
RM
1518
1519 ath_dbg(common, ATH_DBG_CONFIG, "Change Interface\n");
1520 mutex_lock(&sc->mutex);
96f372c9 1521 ath9k_ps_wakeup(sc);
6b3b991d 1522
4801416c
BG
1523 /* See if new interface type is valid. */
1524 if ((new_type == NL80211_IFTYPE_ADHOC) &&
1525 (sc->nvifs > 1)) {
1526 ath_err(common, "When using ADHOC, it must be the only"
1527 " interface.\n");
1528 ret = -EINVAL;
1529 goto out;
1530 }
1531
1532 if (ath9k_uses_beacons(new_type) &&
1533 !ath9k_uses_beacons(vif->type)) {
6b3b991d
RM
1534 if (sc->nbcnvifs >= ATH_BCBUF) {
1535 ath_err(common, "No beacon slot available\n");
6dab55bf
DC
1536 ret = -ENOBUFS;
1537 goto out;
6b3b991d 1538 }
6b3b991d 1539 }
4801416c
BG
1540
1541 /* Clean up old vif stuff */
1542 if (ath9k_uses_beacons(vif->type))
1543 ath9k_reclaim_beacon(sc, vif);
1544
1545 /* Add new settings */
6b3b991d
RM
1546 vif->type = new_type;
1547 vif->p2p = p2p;
1548
4801416c 1549 ath9k_do_vif_add_setup(hw, vif);
6dab55bf 1550out:
96f372c9 1551 ath9k_ps_restore(sc);
6b3b991d 1552 mutex_unlock(&sc->mutex);
6dab55bf 1553 return ret;
6b3b991d
RM
1554}
1555
8feceb67 1556static void ath9k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1557 struct ieee80211_vif *vif)
f078f209 1558{
9ac58615 1559 struct ath_softc *sc = hw->priv;
c46917bb 1560 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
f078f209 1561
226afe68 1562 ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 1563
96f372c9 1564 ath9k_ps_wakeup(sc);
141b38b6
S
1565 mutex_lock(&sc->mutex);
1566
4801416c 1567 sc->nvifs--;
580f0b8a 1568
8feceb67 1569 /* Reclaim beacon resources */
4801416c 1570 if (ath9k_uses_beacons(vif->type))
6b3b991d 1571 ath9k_reclaim_beacon(sc, vif);
2c3db3d5 1572
4801416c 1573 ath9k_calculate_summary_state(hw, NULL);
141b38b6
S
1574
1575 mutex_unlock(&sc->mutex);
96f372c9 1576 ath9k_ps_restore(sc);
f078f209
LR
1577}
1578
fbab7390 1579static void ath9k_enable_ps(struct ath_softc *sc)
3f7c5c10 1580{
3069168c
PR
1581 struct ath_hw *ah = sc->sc_ah;
1582
3f7c5c10 1583 sc->ps_enabled = true;
3069168c
PR
1584 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1585 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1586 ah->imask |= ATH9K_INT_TIM_TIMER;
72d874c6 1587 ath9k_hw_set_interrupts(ah);
3f7c5c10 1588 }
fdf76622 1589 ath9k_hw_setrxabort(ah, 1);
3f7c5c10 1590 }
3f7c5c10
SB
1591}
1592
845d708e
SB
1593static void ath9k_disable_ps(struct ath_softc *sc)
1594{
1595 struct ath_hw *ah = sc->sc_ah;
1596
1597 sc->ps_enabled = false;
1598 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1599 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1600 ath9k_hw_setrxabort(ah, 0);
1601 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1602 PS_WAIT_FOR_CAB |
1603 PS_WAIT_FOR_PSPOLL_DATA |
1604 PS_WAIT_FOR_TX_ACK);
1605 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1606 ah->imask &= ~ATH9K_INT_TIM_TIMER;
72d874c6 1607 ath9k_hw_set_interrupts(ah);
845d708e
SB
1608 }
1609 }
1610
1611}
1612
e8975581 1613static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1614{
9ac58615 1615 struct ath_softc *sc = hw->priv;
3430098a
FF
1616 struct ath_hw *ah = sc->sc_ah;
1617 struct ath_common *common = ath9k_hw_common(ah);
e8975581 1618 struct ieee80211_conf *conf = &hw->conf;
7545daf4 1619 bool disable_radio = false;
f078f209 1620
aa33de09 1621 mutex_lock(&sc->mutex);
141b38b6 1622
194b7c13
LR
1623 /*
1624 * Leave this as the first check because we need to turn on the
1625 * radio if it was disabled before prior to processing the rest
1626 * of the changes. Likewise we must only disable the radio towards
1627 * the end.
1628 */
64839170 1629 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
7545daf4
FF
1630 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1631 if (!sc->ps_idle) {
68a89116 1632 ath_radio_enable(sc, hw);
226afe68
JP
1633 ath_dbg(common, ATH_DBG_CONFIG,
1634 "not-idle: enabling radio\n");
7545daf4
FF
1635 } else {
1636 disable_radio = true;
64839170
LR
1637 }
1638 }
1639
e7824a50
LR
1640 /*
1641 * We just prepare to enable PS. We have to wait until our AP has
1642 * ACK'd our null data frame to disable RX otherwise we'll ignore
1643 * those ACKs and end up retransmitting the same null data frames.
1644 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1645 */
3cbb5dd7 1646 if (changed & IEEE80211_CONF_CHANGE_PS) {
8ab2cd09
LR
1647 unsigned long flags;
1648 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fbab7390
SB
1649 if (conf->flags & IEEE80211_CONF_PS)
1650 ath9k_enable_ps(sc);
845d708e
SB
1651 else
1652 ath9k_disable_ps(sc);
8ab2cd09 1653 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3cbb5dd7
VN
1654 }
1655
199afd9d
S
1656 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1657 if (conf->flags & IEEE80211_CONF_MONITOR) {
226afe68
JP
1658 ath_dbg(common, ATH_DBG_CONFIG,
1659 "Monitor mode is enabled\n");
5f841b41
RM
1660 sc->sc_ah->is_monitoring = true;
1661 } else {
226afe68
JP
1662 ath_dbg(common, ATH_DBG_CONFIG,
1663 "Monitor mode is disabled\n");
5f841b41 1664 sc->sc_ah->is_monitoring = false;
199afd9d
S
1665 }
1666 }
1667
4797938c 1668 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 1669 struct ieee80211_channel *curchan = hw->conf.channel;
e338a85e 1670 struct ath9k_channel old_chan;
5f8e077c 1671 int pos = curchan->hw_value;
3430098a
FF
1672 int old_pos = -1;
1673 unsigned long flags;
1674
1675 if (ah->curchan)
1676 old_pos = ah->curchan - &ah->channels[0];
ae5eb026 1677
5ee08656
FF
1678 if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
1679 sc->sc_flags |= SC_OP_OFFCHANNEL;
1680 else
1681 sc->sc_flags &= ~SC_OP_OFFCHANNEL;
0e2dedf9 1682
8c79a610
BG
1683 ath_dbg(common, ATH_DBG_CONFIG,
1684 "Set channel: %d MHz type: %d\n",
1685 curchan->center_freq, conf->channel_type);
f078f209 1686
3430098a
FF
1687 /* update survey stats for the old channel before switching */
1688 spin_lock_irqsave(&common->cc_lock, flags);
1689 ath_update_survey_stats(sc);
1690 spin_unlock_irqrestore(&common->cc_lock, flags);
1691
e338a85e
RM
1692 /*
1693 * Preserve the current channel values, before updating
1694 * the same channel
1695 */
1696 if (old_pos == pos) {
1697 memcpy(&old_chan, &sc->sc_ah->channels[pos],
1698 sizeof(struct ath9k_channel));
1699 ah->curchan = &old_chan;
1700 }
1701
1702 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
1703 curchan, conf->channel_type);
1704
3430098a
FF
1705 /*
1706 * If the operating channel changes, change the survey in-use flags
1707 * along with it.
1708 * Reset the survey data for the new channel, unless we're switching
1709 * back to the operating channel from an off-channel operation.
1710 */
1711 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1712 sc->cur_survey != &sc->survey[pos]) {
1713
1714 if (sc->cur_survey)
1715 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1716
1717 sc->cur_survey = &sc->survey[pos];
1718
1719 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1720 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1721 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1722 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1723 }
1724
0e2dedf9 1725 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
3800276a 1726 ath_err(common, "Unable to set channel\n");
aa33de09 1727 mutex_unlock(&sc->mutex);
e11602b7
S
1728 return -EINVAL;
1729 }
3430098a
FF
1730
1731 /*
1732 * The most recent snapshot of channel->noisefloor for the old
1733 * channel is only available after the hardware reset. Copy it to
1734 * the survey stats now.
1735 */
1736 if (old_pos >= 0)
1737 ath_update_survey_nf(sc, old_pos);
094d05dc 1738 }
f078f209 1739
c9f6a656 1740 if (changed & IEEE80211_CONF_CHANGE_POWER) {
603b3eef
BG
1741 ath_dbg(common, ATH_DBG_CONFIG,
1742 "Set power: %d\n", conf->power_level);
17d7904d 1743 sc->config.txpowlimit = 2 * conf->power_level;
783cd01e 1744 ath9k_ps_wakeup(sc);
5048e8c3
RM
1745 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1746 sc->config.txpowlimit, &sc->curtxpow);
783cd01e 1747 ath9k_ps_restore(sc);
c9f6a656 1748 }
f078f209 1749
64839170 1750 if (disable_radio) {
226afe68 1751 ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
68a89116 1752 ath_radio_disable(sc, hw);
64839170
LR
1753 }
1754
aa33de09 1755 mutex_unlock(&sc->mutex);
141b38b6 1756
f078f209
LR
1757 return 0;
1758}
1759
8feceb67
VT
1760#define SUPPORTED_FILTERS \
1761 (FIF_PROMISC_IN_BSS | \
1762 FIF_ALLMULTI | \
1763 FIF_CONTROL | \
af6a3fc7 1764 FIF_PSPOLL | \
8feceb67
VT
1765 FIF_OTHER_BSS | \
1766 FIF_BCN_PRBRESP_PROMISC | \
9c1d8e4a 1767 FIF_PROBE_REQ | \
8feceb67 1768 FIF_FCSFAIL)
c83be688 1769
8feceb67
VT
1770/* FIXME: sc->sc_full_reset ? */
1771static void ath9k_configure_filter(struct ieee80211_hw *hw,
1772 unsigned int changed_flags,
1773 unsigned int *total_flags,
3ac64bee 1774 u64 multicast)
8feceb67 1775{
9ac58615 1776 struct ath_softc *sc = hw->priv;
8feceb67 1777 u32 rfilt;
f078f209 1778
8feceb67
VT
1779 changed_flags &= SUPPORTED_FILTERS;
1780 *total_flags &= SUPPORTED_FILTERS;
f078f209 1781
b77f483f 1782 sc->rx.rxfilter = *total_flags;
aa68aeaa 1783 ath9k_ps_wakeup(sc);
8feceb67
VT
1784 rfilt = ath_calcrxfilter(sc);
1785 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 1786 ath9k_ps_restore(sc);
f078f209 1787
226afe68
JP
1788 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
1789 "Set HW RX filter: 0x%x\n", rfilt);
8feceb67 1790}
f078f209 1791
4ca77860
JB
1792static int ath9k_sta_add(struct ieee80211_hw *hw,
1793 struct ieee80211_vif *vif,
1794 struct ieee80211_sta *sta)
8feceb67 1795{
9ac58615 1796 struct ath_softc *sc = hw->priv;
93ae2dd2
FF
1797 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1798 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1799 struct ieee80211_key_conf ps_key = { };
f078f209 1800
4ca77860 1801 ath_node_attach(sc, sta);
f59a59fe
FF
1802
1803 if (vif->type != NL80211_IFTYPE_AP &&
1804 vif->type != NL80211_IFTYPE_AP_VLAN)
1805 return 0;
1806
93ae2dd2 1807 an->ps_key = ath_key_config(common, vif, sta, &ps_key);
4ca77860
JB
1808
1809 return 0;
1810}
1811
93ae2dd2
FF
1812static void ath9k_del_ps_key(struct ath_softc *sc,
1813 struct ieee80211_vif *vif,
1814 struct ieee80211_sta *sta)
1815{
1816 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1817 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1818 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1819
1820 if (!an->ps_key)
1821 return;
1822
1823 ath_key_delete(common, &ps_key);
1824}
1825
4ca77860
JB
1826static int ath9k_sta_remove(struct ieee80211_hw *hw,
1827 struct ieee80211_vif *vif,
1828 struct ieee80211_sta *sta)
1829{
9ac58615 1830 struct ath_softc *sc = hw->priv;
4ca77860 1831
93ae2dd2 1832 ath9k_del_ps_key(sc, vif, sta);
4ca77860
JB
1833 ath_node_detach(sc, sta);
1834
1835 return 0;
f078f209
LR
1836}
1837
5519541d
FF
1838static void ath9k_sta_notify(struct ieee80211_hw *hw,
1839 struct ieee80211_vif *vif,
1840 enum sta_notify_cmd cmd,
1841 struct ieee80211_sta *sta)
1842{
1843 struct ath_softc *sc = hw->priv;
1844 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1845
1846 switch (cmd) {
1847 case STA_NOTIFY_SLEEP:
1848 an->sleeping = true;
042ec453 1849 ath_tx_aggr_sleep(sta, sc, an);
5519541d
FF
1850 break;
1851 case STA_NOTIFY_AWAKE:
1852 an->sleeping = false;
1853 ath_tx_aggr_wakeup(sc, an);
1854 break;
1855 }
1856}
1857
8a3a3c85
EP
1858static int ath9k_conf_tx(struct ieee80211_hw *hw,
1859 struct ieee80211_vif *vif, u16 queue,
8feceb67 1860 const struct ieee80211_tx_queue_params *params)
f078f209 1861{
9ac58615 1862 struct ath_softc *sc = hw->priv;
c46917bb 1863 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
066dae93 1864 struct ath_txq *txq;
8feceb67 1865 struct ath9k_tx_queue_info qi;
066dae93 1866 int ret = 0;
f078f209 1867
8feceb67
VT
1868 if (queue >= WME_NUM_AC)
1869 return 0;
f078f209 1870
066dae93
FF
1871 txq = sc->tx.txq_map[queue];
1872
96f372c9 1873 ath9k_ps_wakeup(sc);
141b38b6
S
1874 mutex_lock(&sc->mutex);
1875
1ffb0610
S
1876 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1877
8feceb67
VT
1878 qi.tqi_aifs = params->aifs;
1879 qi.tqi_cwmin = params->cw_min;
1880 qi.tqi_cwmax = params->cw_max;
1881 qi.tqi_burstTime = params->txop;
f078f209 1882
226afe68
JP
1883 ath_dbg(common, ATH_DBG_CONFIG,
1884 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1885 queue, txq->axq_qnum, params->aifs, params->cw_min,
1886 params->cw_max, params->txop);
f078f209 1887
066dae93 1888 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
8feceb67 1889 if (ret)
3800276a 1890 ath_err(common, "TXQ Update failed\n");
f078f209 1891
94db2936 1892 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
066dae93 1893 if (queue == WME_AC_BE && !ret)
94db2936
VN
1894 ath_beaconq_config(sc);
1895
141b38b6 1896 mutex_unlock(&sc->mutex);
96f372c9 1897 ath9k_ps_restore(sc);
141b38b6 1898
8feceb67
VT
1899 return ret;
1900}
f078f209 1901
8feceb67
VT
1902static int ath9k_set_key(struct ieee80211_hw *hw,
1903 enum set_key_cmd cmd,
dc822b5d
JB
1904 struct ieee80211_vif *vif,
1905 struct ieee80211_sta *sta,
8feceb67
VT
1906 struct ieee80211_key_conf *key)
1907{
9ac58615 1908 struct ath_softc *sc = hw->priv;
c46917bb 1909 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67 1910 int ret = 0;
f078f209 1911
3e6109c5 1912 if (ath9k_modparam_nohwcrypt)
b3bd89ce
JM
1913 return -ENOSPC;
1914
cfdc9a8b
JM
1915 if (vif->type == NL80211_IFTYPE_ADHOC &&
1916 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1917 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1918 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1919 /*
1920 * For now, disable hw crypto for the RSN IBSS group keys. This
1921 * could be optimized in the future to use a modified key cache
1922 * design to support per-STA RX GTK, but until that gets
1923 * implemented, use of software crypto for group addressed
1924 * frames is a acceptable to allow RSN IBSS to be used.
1925 */
1926 return -EOPNOTSUPP;
1927 }
1928
141b38b6 1929 mutex_lock(&sc->mutex);
3cbb5dd7 1930 ath9k_ps_wakeup(sc);
226afe68 1931 ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 1932
8feceb67
VT
1933 switch (cmd) {
1934 case SET_KEY:
93ae2dd2
FF
1935 if (sta)
1936 ath9k_del_ps_key(sc, vif, sta);
1937
040e539e 1938 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM
1939 if (ret >= 0) {
1940 key->hw_key_idx = ret;
8feceb67
VT
1941 /* push IV and Michael MIC generation to stack */
1942 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
97359d12 1943 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
8feceb67 1944 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
97359d12
JB
1945 if (sc->sc_ah->sw_mgmt_crypto &&
1946 key->cipher == WLAN_CIPHER_SUITE_CCMP)
0ced0e17 1947 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 1948 ret = 0;
8feceb67
VT
1949 }
1950 break;
1951 case DISABLE_KEY:
040e539e 1952 ath_key_delete(common, key);
8feceb67
VT
1953 break;
1954 default:
1955 ret = -EINVAL;
1956 }
f078f209 1957
3cbb5dd7 1958 ath9k_ps_restore(sc);
141b38b6
S
1959 mutex_unlock(&sc->mutex);
1960
8feceb67
VT
1961 return ret;
1962}
4f5ef75b
RM
1963static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1964{
1965 struct ath_softc *sc = data;
1966 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1967 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1968 struct ath_vif *avp = (void *)vif->drv_priv;
1969
2e5ef459
RM
1970 /*
1971 * Skip iteration if primary station vif's bss info
1972 * was not changed
1973 */
1974 if (sc->sc_flags & SC_OP_PRIM_STA_VIF)
1975 return;
1976
1977 if (bss_conf->assoc) {
1978 sc->sc_flags |= SC_OP_PRIM_STA_VIF;
1979 avp->primary_sta_vif = true;
4f5ef75b
RM
1980 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1981 common->curaid = bss_conf->aid;
1982 ath9k_hw_write_associd(sc->sc_ah);
2e5ef459 1983 ath_dbg(common, ATH_DBG_CONFIG,
99e4d43a
RM
1984 "Bss Info ASSOC %d, bssid: %pM\n",
1985 bss_conf->aid, common->curbssid);
2e5ef459
RM
1986 ath_beacon_config(sc, vif);
1987 /*
1988 * Request a re-configuration of Beacon related timers
1989 * on the receipt of the first Beacon frame (i.e.,
1990 * after time sync with the AP).
1991 */
1992 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1993 /* Reset rssi stats */
1994 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
1995 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
99e4d43a 1996
05c0be2f
MSS
1997 if (!common->disable_ani) {
1998 sc->sc_flags |= SC_OP_ANI_RUN;
1999 ath_start_ani(common);
2000 }
2001
4f5ef75b
RM
2002 }
2003}
2004
2005static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
2006{
2007 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2008 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
2009 struct ath_vif *avp = (void *)vif->drv_priv;
2010
2e5ef459
RM
2011 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
2012 return;
2013
4f5ef75b
RM
2014 /* Reconfigure bss info */
2015 if (avp->primary_sta_vif && !bss_conf->assoc) {
99e4d43a
RM
2016 ath_dbg(common, ATH_DBG_CONFIG,
2017 "Bss Info DISASSOC %d, bssid %pM\n",
2018 common->curaid, common->curbssid);
2019 sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS);
4f5ef75b
RM
2020 avp->primary_sta_vif = false;
2021 memset(common->curbssid, 0, ETH_ALEN);
2022 common->curaid = 0;
2023 }
2024
2025 ieee80211_iterate_active_interfaces_atomic(
2026 sc->hw, ath9k_bss_iter, sc);
2027
2028 /*
2029 * None of station vifs are associated.
2030 * Clear bssid & aid
2031 */
2e5ef459 2032 if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF)) {
4f5ef75b 2033 ath9k_hw_write_associd(sc->sc_ah);
99e4d43a
RM
2034 /* Stop ANI */
2035 sc->sc_flags &= ~SC_OP_ANI_RUN;
2036 del_timer_sync(&common->ani.timer);
d2c71c20 2037 memset(&sc->caldata, 0, sizeof(sc->caldata));
99e4d43a 2038 }
4f5ef75b 2039}
f078f209 2040
8feceb67
VT
2041static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2042 struct ieee80211_vif *vif,
2043 struct ieee80211_bss_conf *bss_conf,
2044 u32 changed)
2045{
9ac58615 2046 struct ath_softc *sc = hw->priv;
2d0ddec5 2047 struct ath_hw *ah = sc->sc_ah;
1510718d 2048 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 2049 struct ath_vif *avp = (void *)vif->drv_priv;
0005baf4 2050 int slottime;
c6089ccc 2051 int error;
f078f209 2052
96f372c9 2053 ath9k_ps_wakeup(sc);
141b38b6
S
2054 mutex_lock(&sc->mutex);
2055
c6089ccc 2056 if (changed & BSS_CHANGED_BSSID) {
4f5ef75b 2057 ath9k_config_bss(sc, vif);
2d0ddec5 2058
226afe68
JP
2059 ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n",
2060 common->curbssid, common->curaid);
c6089ccc 2061 }
2d0ddec5 2062
2e5ef459
RM
2063 if (changed & BSS_CHANGED_IBSS) {
2064 /* There can be only one vif available */
2065 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2066 common->curaid = bss_conf->aid;
2067 ath9k_hw_write_associd(sc->sc_ah);
2068
2069 if (bss_conf->ibss_joined) {
2070 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
05c0be2f
MSS
2071
2072 if (!common->disable_ani) {
2073 sc->sc_flags |= SC_OP_ANI_RUN;
2074 ath_start_ani(common);
2075 }
2076
2e5ef459
RM
2077 } else {
2078 sc->sc_flags &= ~SC_OP_ANI_RUN;
2079 del_timer_sync(&common->ani.timer);
2080 }
2081 }
2082
c6089ccc
S
2083 /* Enable transmission of beacons (AP, IBSS, MESH) */
2084 if ((changed & BSS_CHANGED_BEACON) ||
2085 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
014cf3bb 2086 ath9k_set_beaconing_status(sc, false);
9ac58615 2087 error = ath_beacon_alloc(sc, vif);
c6089ccc
S
2088 if (!error)
2089 ath_beacon_config(sc, vif);
014cf3bb 2090 ath9k_set_beaconing_status(sc, true);
0005baf4
FF
2091 }
2092
2093 if (changed & BSS_CHANGED_ERP_SLOT) {
2094 if (bss_conf->use_short_slot)
2095 slottime = 9;
2096 else
2097 slottime = 20;
2098 if (vif->type == NL80211_IFTYPE_AP) {
2099 /*
2100 * Defer update, so that connected stations can adjust
2101 * their settings at the same time.
2102 * See beacon.c for more details
2103 */
2104 sc->beacon.slottime = slottime;
2105 sc->beacon.updateslot = UPDATE;
2106 } else {
2107 ah->slottime = slottime;
2108 ath9k_hw_init_global_settings(ah);
2109 }
2d0ddec5
JB
2110 }
2111
c6089ccc 2112 /* Disable transmission of beacons */
014cf3bb
RM
2113 if ((changed & BSS_CHANGED_BEACON_ENABLED) &&
2114 !bss_conf->enable_beacon) {
2115 ath9k_set_beaconing_status(sc, false);
2116 avp->is_bslot_active = false;
2117 ath9k_set_beaconing_status(sc, true);
2118 }
2d0ddec5 2119
c6089ccc 2120 if (changed & BSS_CHANGED_BEACON_INT) {
c6089ccc
S
2121 /*
2122 * In case of AP mode, the HW TSF has to be reset
2123 * when the beacon interval changes.
2124 */
2125 if (vif->type == NL80211_IFTYPE_AP) {
2126 sc->sc_flags |= SC_OP_TSF_RESET;
014cf3bb 2127 ath9k_set_beaconing_status(sc, false);
9ac58615 2128 error = ath_beacon_alloc(sc, vif);
2d0ddec5
JB
2129 if (!error)
2130 ath_beacon_config(sc, vif);
014cf3bb 2131 ath9k_set_beaconing_status(sc, true);
99e4d43a 2132 } else
c6089ccc 2133 ath_beacon_config(sc, vif);
2d0ddec5
JB
2134 }
2135
8feceb67 2136 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
226afe68
JP
2137 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2138 bss_conf->use_short_preamble);
8feceb67
VT
2139 if (bss_conf->use_short_preamble)
2140 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2141 else
2142 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2143 }
f078f209 2144
8feceb67 2145 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
226afe68
JP
2146 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2147 bss_conf->use_cts_prot);
8feceb67
VT
2148 if (bss_conf->use_cts_prot &&
2149 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2150 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2151 else
2152 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2153 }
f078f209 2154
141b38b6 2155 mutex_unlock(&sc->mutex);
96f372c9 2156 ath9k_ps_restore(sc);
8feceb67 2157}
f078f209 2158
37a41b4a 2159static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
8feceb67 2160{
9ac58615 2161 struct ath_softc *sc = hw->priv;
8feceb67 2162 u64 tsf;
f078f209 2163
141b38b6 2164 mutex_lock(&sc->mutex);
9abbfb27 2165 ath9k_ps_wakeup(sc);
141b38b6 2166 tsf = ath9k_hw_gettsf64(sc->sc_ah);
9abbfb27 2167 ath9k_ps_restore(sc);
141b38b6 2168 mutex_unlock(&sc->mutex);
f078f209 2169
8feceb67
VT
2170 return tsf;
2171}
f078f209 2172
37a41b4a
EP
2173static void ath9k_set_tsf(struct ieee80211_hw *hw,
2174 struct ieee80211_vif *vif,
2175 u64 tsf)
3b5d665b 2176{
9ac58615 2177 struct ath_softc *sc = hw->priv;
3b5d665b 2178
141b38b6 2179 mutex_lock(&sc->mutex);
9abbfb27 2180 ath9k_ps_wakeup(sc);
141b38b6 2181 ath9k_hw_settsf64(sc->sc_ah, tsf);
9abbfb27 2182 ath9k_ps_restore(sc);
141b38b6 2183 mutex_unlock(&sc->mutex);
3b5d665b
AF
2184}
2185
37a41b4a 2186static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
8feceb67 2187{
9ac58615 2188 struct ath_softc *sc = hw->priv;
c83be688 2189
141b38b6 2190 mutex_lock(&sc->mutex);
21526d57
LR
2191
2192 ath9k_ps_wakeup(sc);
141b38b6 2193 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR
2194 ath9k_ps_restore(sc);
2195
141b38b6 2196 mutex_unlock(&sc->mutex);
8feceb67 2197}
f078f209 2198
8feceb67 2199static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 2200 struct ieee80211_vif *vif,
141b38b6
S
2201 enum ieee80211_ampdu_mlme_action action,
2202 struct ieee80211_sta *sta,
0b01f030 2203 u16 tid, u16 *ssn, u8 buf_size)
8feceb67 2204{
9ac58615 2205 struct ath_softc *sc = hw->priv;
8feceb67 2206 int ret = 0;
f078f209 2207
85ad181e
JB
2208 local_bh_disable();
2209
8feceb67
VT
2210 switch (action) {
2211 case IEEE80211_AMPDU_RX_START:
dca3edb8
S
2212 if (!(sc->sc_flags & SC_OP_RXAGGR))
2213 ret = -ENOTSUPP;
8feceb67
VT
2214 break;
2215 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT
2216 break;
2217 case IEEE80211_AMPDU_TX_START:
71a3bf3e
FF
2218 if (!(sc->sc_flags & SC_OP_TXAGGR))
2219 return -EOPNOTSUPP;
2220
8b685ba9 2221 ath9k_ps_wakeup(sc);
231c3a1f
FF
2222 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2223 if (!ret)
2224 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2225 ath9k_ps_restore(sc);
8feceb67
VT
2226 break;
2227 case IEEE80211_AMPDU_TX_STOP:
8b685ba9 2228 ath9k_ps_wakeup(sc);
f83da965 2229 ath_tx_aggr_stop(sc, sta, tid);
c951ad35 2230 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2231 ath9k_ps_restore(sc);
8feceb67 2232 break;
b1720231 2233 case IEEE80211_AMPDU_TX_OPERATIONAL:
8b685ba9 2234 ath9k_ps_wakeup(sc);
8469cdef 2235 ath_tx_aggr_resume(sc, sta, tid);
8b685ba9 2236 ath9k_ps_restore(sc);
8469cdef 2237 break;
8feceb67 2238 default:
3800276a 2239 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
8feceb67
VT
2240 }
2241
85ad181e
JB
2242 local_bh_enable();
2243
8feceb67 2244 return ret;
f078f209
LR
2245}
2246
62dad5b0
BP
2247static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2248 struct survey_info *survey)
2249{
9ac58615 2250 struct ath_softc *sc = hw->priv;
3430098a 2251 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39162dbe 2252 struct ieee80211_supported_band *sband;
3430098a
FF
2253 struct ieee80211_channel *chan;
2254 unsigned long flags;
2255 int pos;
2256
2257 spin_lock_irqsave(&common->cc_lock, flags);
2258 if (idx == 0)
2259 ath_update_survey_stats(sc);
39162dbe
FF
2260
2261 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2262 if (sband && idx >= sband->n_channels) {
2263 idx -= sband->n_channels;
2264 sband = NULL;
2265 }
62dad5b0 2266
39162dbe
FF
2267 if (!sband)
2268 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
62dad5b0 2269
3430098a
FF
2270 if (!sband || idx >= sband->n_channels) {
2271 spin_unlock_irqrestore(&common->cc_lock, flags);
2272 return -ENOENT;
4f1a5a4b 2273 }
62dad5b0 2274
3430098a
FF
2275 chan = &sband->channels[idx];
2276 pos = chan->hw_value;
2277 memcpy(survey, &sc->survey[pos], sizeof(*survey));
2278 survey->channel = chan;
2279 spin_unlock_irqrestore(&common->cc_lock, flags);
2280
62dad5b0
BP
2281 return 0;
2282}
2283
e239d859
FF
2284static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
2285{
9ac58615 2286 struct ath_softc *sc = hw->priv;
e239d859
FF
2287 struct ath_hw *ah = sc->sc_ah;
2288
2289 mutex_lock(&sc->mutex);
2290 ah->coverage_class = coverage_class;
8b2a3827
MSS
2291
2292 ath9k_ps_wakeup(sc);
e239d859 2293 ath9k_hw_init_global_settings(ah);
8b2a3827
MSS
2294 ath9k_ps_restore(sc);
2295
e239d859
FF
2296 mutex_unlock(&sc->mutex);
2297}
2298
69081624
VT
2299static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
2300{
69081624 2301 struct ath_softc *sc = hw->priv;
99aa55b6
MSS
2302 struct ath_hw *ah = sc->sc_ah;
2303 struct ath_common *common = ath9k_hw_common(ah);
86271e46
FF
2304 int timeout = 200; /* ms */
2305 int i, j;
2f6fc351 2306 bool drain_txq;
69081624
VT
2307
2308 mutex_lock(&sc->mutex);
69081624
VT
2309 cancel_delayed_work_sync(&sc->tx_complete_work);
2310
6a6b3f3e
MSS
2311 if (ah->ah_flags & AH_UNPLUGGED) {
2312 ath_dbg(common, ATH_DBG_ANY, "Device has been unplugged!\n");
2313 mutex_unlock(&sc->mutex);
2314 return;
2315 }
2316
99aa55b6
MSS
2317 if (sc->sc_flags & SC_OP_INVALID) {
2318 ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
2319 mutex_unlock(&sc->mutex);
2320 return;
2321 }
2322
86271e46
FF
2323 if (drop)
2324 timeout = 1;
69081624 2325
86271e46 2326 for (j = 0; j < timeout; j++) {
108697c4 2327 bool npend = false;
86271e46
FF
2328
2329 if (j)
2330 usleep_range(1000, 2000);
69081624 2331
86271e46
FF
2332 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2333 if (!ATH_TXQ_SETUP(sc, i))
2334 continue;
2335
108697c4
MSS
2336 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
2337
2338 if (npend)
2339 break;
69081624 2340 }
86271e46
FF
2341
2342 if (!npend)
2343 goto out;
69081624
VT
2344 }
2345
51513906 2346 ath9k_ps_wakeup(sc);
2f6fc351
RM
2347 spin_lock_bh(&sc->sc_pcu_lock);
2348 drain_txq = ath_drain_all_txq(sc, false);
9adcf440
FF
2349 spin_unlock_bh(&sc->sc_pcu_lock);
2350
2f6fc351 2351 if (!drain_txq)
69081624 2352 ath_reset(sc, false);
9adcf440 2353
51513906 2354 ath9k_ps_restore(sc);
d78f4b3e
SB
2355 ieee80211_wake_queues(hw);
2356
86271e46 2357out:
69081624
VT
2358 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
2359 mutex_unlock(&sc->mutex);
2360}
2361
15b91e83
VN
2362static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2363{
2364 struct ath_softc *sc = hw->priv;
2365 int i;
2366
2367 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2368 if (!ATH_TXQ_SETUP(sc, i))
2369 continue;
2370
2371 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
2372 return true;
2373 }
2374 return false;
2375}
2376
5595f119 2377static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
ba4903f9
FF
2378{
2379 struct ath_softc *sc = hw->priv;
2380 struct ath_hw *ah = sc->sc_ah;
2381 struct ieee80211_vif *vif;
2382 struct ath_vif *avp;
2383 struct ath_buf *bf;
2384 struct ath_tx_status ts;
2385 int status;
2386
2387 vif = sc->beacon.bslot[0];
2388 if (!vif)
2389 return 0;
2390
2391 avp = (void *)vif->drv_priv;
2392 if (!avp->is_bslot_active)
2393 return 0;
2394
2395 if (!sc->beacon.tx_processed) {
2396 tasklet_disable(&sc->bcon_tasklet);
2397
2398 bf = avp->av_bcbuf;
2399 if (!bf || !bf->bf_mpdu)
2400 goto skip;
2401
2402 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2403 if (status == -EINPROGRESS)
2404 goto skip;
2405
2406 sc->beacon.tx_processed = true;
2407 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2408
2409skip:
2410 tasklet_enable(&sc->bcon_tasklet);
2411 }
2412
2413 return sc->beacon.tx_last;
2414}
2415
52c94f41
MSS
2416static int ath9k_get_stats(struct ieee80211_hw *hw,
2417 struct ieee80211_low_level_stats *stats)
2418{
2419 struct ath_softc *sc = hw->priv;
2420 struct ath_hw *ah = sc->sc_ah;
2421 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2422
2423 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2424 stats->dot11RTSFailureCount = mib_stats->rts_bad;
2425 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2426 stats->dot11RTSSuccessCount = mib_stats->rts_good;
2427 return 0;
2428}
2429
43c35284
FF
2430static u32 fill_chainmask(u32 cap, u32 new)
2431{
2432 u32 filled = 0;
2433 int i;
2434
2435 for (i = 0; cap && new; i++, cap >>= 1) {
2436 if (!(cap & BIT(0)))
2437 continue;
2438
2439 if (new & BIT(0))
2440 filled |= BIT(i);
2441
2442 new >>= 1;
2443 }
2444
2445 return filled;
2446}
2447
2448static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2449{
2450 struct ath_softc *sc = hw->priv;
2451 struct ath_hw *ah = sc->sc_ah;
2452
2453 if (!rx_ant || !tx_ant)
2454 return -EINVAL;
2455
2456 sc->ant_rx = rx_ant;
2457 sc->ant_tx = tx_ant;
2458
2459 if (ah->caps.rx_chainmask == 1)
2460 return 0;
2461
2462 /* AR9100 runs into calibration issues if not all rx chains are enabled */
2463 if (AR_SREV_9100(ah))
2464 ah->rxchainmask = 0x7;
2465 else
2466 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2467
2468 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
2469 ath9k_reload_chainmask_settings(sc);
2470
2471 return 0;
2472}
2473
2474static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2475{
2476 struct ath_softc *sc = hw->priv;
2477
2478 *tx_ant = sc->ant_tx;
2479 *rx_ant = sc->ant_rx;
2480 return 0;
2481}
2482
6baff7f9 2483struct ieee80211_ops ath9k_ops = {
8feceb67
VT
2484 .tx = ath9k_tx,
2485 .start = ath9k_start,
2486 .stop = ath9k_stop,
2487 .add_interface = ath9k_add_interface,
6b3b991d 2488 .change_interface = ath9k_change_interface,
8feceb67
VT
2489 .remove_interface = ath9k_remove_interface,
2490 .config = ath9k_config,
8feceb67 2491 .configure_filter = ath9k_configure_filter,
4ca77860
JB
2492 .sta_add = ath9k_sta_add,
2493 .sta_remove = ath9k_sta_remove,
5519541d 2494 .sta_notify = ath9k_sta_notify,
8feceb67 2495 .conf_tx = ath9k_conf_tx,
8feceb67 2496 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2497 .set_key = ath9k_set_key,
8feceb67 2498 .get_tsf = ath9k_get_tsf,
3b5d665b 2499 .set_tsf = ath9k_set_tsf,
8feceb67 2500 .reset_tsf = ath9k_reset_tsf,
4233df6b 2501 .ampdu_action = ath9k_ampdu_action,
62dad5b0 2502 .get_survey = ath9k_get_survey,
3b319aae 2503 .rfkill_poll = ath9k_rfkill_poll_state,
e239d859 2504 .set_coverage_class = ath9k_set_coverage_class,
69081624 2505 .flush = ath9k_flush,
15b91e83 2506 .tx_frames_pending = ath9k_tx_frames_pending,
52c94f41
MSS
2507 .tx_last_beacon = ath9k_tx_last_beacon,
2508 .get_stats = ath9k_get_stats,
43c35284
FF
2509 .set_antenna = ath9k_set_antenna,
2510 .get_antenna = ath9k_get_antenna,
8feceb67 2511};
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