ath9k: make DFS detector pools SMP safe
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
69081624 18#include <linux/delay.h>
394cf0a1 19#include "ath9k.h"
af03abec 20#include "btcoex.h"
f078f209 21
ff37e337
S
22static u8 parse_mpdudensity(u8 mpdudensity)
23{
24 /*
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
26 * 0 for no restriction
27 * 1 for 1/4 us
28 * 2 for 1/2 us
29 * 3 for 1 us
30 * 4 for 2 us
31 * 5 for 4 us
32 * 6 for 8 us
33 * 7 for 16 us
34 */
35 switch (mpdudensity) {
36 case 0:
37 return 0;
38 case 1:
39 case 2:
40 case 3:
41 /* Our lower layer calculations limit our precision to
42 1 microsecond */
43 return 1;
44 case 4:
45 return 2;
46 case 5:
47 return 4;
48 case 6:
49 return 8;
50 case 7:
51 return 16;
52 default:
53 return 0;
54 }
55}
56
69081624
VT
57static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
58{
59 bool pending = false;
60
61 spin_lock_bh(&txq->axq_lock);
62
63 if (txq->axq_depth || !list_empty(&txq->axq_acq))
64 pending = true;
69081624
VT
65
66 spin_unlock_bh(&txq->axq_lock);
67 return pending;
68}
69
6d79cb4c 70static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR
71{
72 unsigned long flags;
73 bool ret;
74
9ecdef4b
LR
75 spin_lock_irqsave(&sc->sc_pm_lock, flags);
76 ret = ath9k_hw_setpower(sc->sc_ah, mode);
77 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR
78
79 return ret;
80}
81
a91d75ae
LR
82void ath9k_ps_wakeup(struct ath_softc *sc)
83{
898c914a 84 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae 85 unsigned long flags;
fbb078fc 86 enum ath9k_power_mode power_mode;
a91d75ae
LR
87
88 spin_lock_irqsave(&sc->sc_pm_lock, flags);
89 if (++sc->ps_usecount != 1)
90 goto unlock;
91
fbb078fc 92 power_mode = sc->sc_ah->power_mode;
9ecdef4b 93 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae 94
898c914a
FF
95 /*
96 * While the hardware is asleep, the cycle counters contain no
97 * useful data. Better clear them now so that they don't mess up
98 * survey data results.
99 */
fbb078fc
FF
100 if (power_mode != ATH9K_PM_AWAKE) {
101 spin_lock(&common->cc_lock);
102 ath_hw_cycle_counters_update(common);
103 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
104 spin_unlock(&common->cc_lock);
105 }
898c914a 106
a91d75ae
LR
107 unlock:
108 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
109}
110
111void ath9k_ps_restore(struct ath_softc *sc)
112{
898c914a 113 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
c6c539f0 114 enum ath9k_power_mode mode;
a91d75ae
LR
115 unsigned long flags;
116
117 spin_lock_irqsave(&sc->sc_pm_lock, flags);
118 if (--sc->ps_usecount != 0)
119 goto unlock;
120
011afa1e 121 if (sc->ps_idle && (sc->ps_flags & PS_WAIT_FOR_TX_ACK))
c6c539f0 122 mode = ATH9K_PM_FULL_SLEEP;
1dbfd9d4
VN
123 else if (sc->ps_enabled &&
124 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
1b04b930 125 PS_WAIT_FOR_CAB |
011afa1e
SM
126 PS_WAIT_FOR_PSPOLL_DATA |
127 PS_WAIT_FOR_TX_ACK)))
c6c539f0
FF
128 mode = ATH9K_PM_NETWORK_SLEEP;
129 else
130 goto unlock;
131
132 spin_lock(&common->cc_lock);
133 ath_hw_cycle_counters_update(common);
134 spin_unlock(&common->cc_lock);
135
1a8f0d39 136 ath9k_hw_setpower(sc->sc_ah, mode);
a91d75ae
LR
137
138 unlock:
139 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
140}
141
05c0be2f 142void ath_start_ani(struct ath_common *common)
5ee08656
FF
143{
144 struct ath_hw *ah = common->ah;
145 unsigned long timestamp = jiffies_to_msecs(jiffies);
146 struct ath_softc *sc = (struct ath_softc *) common->priv;
147
148 if (!(sc->sc_flags & SC_OP_ANI_RUN))
149 return;
150
151 if (sc->sc_flags & SC_OP_OFFCHANNEL)
152 return;
153
154 common->ani.longcal_timer = timestamp;
155 common->ani.shortcal_timer = timestamp;
156 common->ani.checkani_timer = timestamp;
157
158 mod_timer(&common->ani.timer,
159 jiffies +
160 msecs_to_jiffies((u32)ah->config.ani_poll_interval));
161}
162
3430098a
FF
163static void ath_update_survey_nf(struct ath_softc *sc, int channel)
164{
165 struct ath_hw *ah = sc->sc_ah;
166 struct ath9k_channel *chan = &ah->channels[channel];
167 struct survey_info *survey = &sc->survey[channel];
168
169 if (chan->noisefloor) {
170 survey->filled |= SURVEY_INFO_NOISE_DBM;
f749b946 171 survey->noise = ath9k_hw_getchan_noise(ah, chan);
3430098a
FF
172 }
173}
174
cb8d61de
FF
175/*
176 * Updates the survey statistics and returns the busy time since last
177 * update in %, if the measurement duration was long enough for the
178 * result to be useful, -1 otherwise.
179 */
180static int ath_update_survey_stats(struct ath_softc *sc)
3430098a
FF
181{
182 struct ath_hw *ah = sc->sc_ah;
183 struct ath_common *common = ath9k_hw_common(ah);
184 int pos = ah->curchan - &ah->channels[0];
185 struct survey_info *survey = &sc->survey[pos];
186 struct ath_cycle_counters *cc = &common->cc_survey;
187 unsigned int div = common->clockrate * 1000;
cb8d61de 188 int ret = 0;
3430098a 189
0845735e 190 if (!ah->curchan)
cb8d61de 191 return -1;
0845735e 192
898c914a
FF
193 if (ah->power_mode == ATH9K_PM_AWAKE)
194 ath_hw_cycle_counters_update(common);
3430098a
FF
195
196 if (cc->cycles > 0) {
197 survey->filled |= SURVEY_INFO_CHANNEL_TIME |
198 SURVEY_INFO_CHANNEL_TIME_BUSY |
199 SURVEY_INFO_CHANNEL_TIME_RX |
200 SURVEY_INFO_CHANNEL_TIME_TX;
201 survey->channel_time += cc->cycles / div;
202 survey->channel_time_busy += cc->rx_busy / div;
203 survey->channel_time_rx += cc->rx_frame / div;
204 survey->channel_time_tx += cc->tx_frame / div;
205 }
cb8d61de
FF
206
207 if (cc->cycles < div)
208 return -1;
209
210 if (cc->cycles > 0)
211 ret = cc->rx_busy * 100 / cc->cycles;
212
3430098a
FF
213 memset(cc, 0, sizeof(*cc));
214
215 ath_update_survey_nf(sc, pos);
cb8d61de
FF
216
217 return ret;
3430098a
FF
218}
219
9adcf440 220static void __ath_cancel_work(struct ath_softc *sc)
ff37e337 221{
5ee08656
FF
222 cancel_work_sync(&sc->paprd_work);
223 cancel_work_sync(&sc->hw_check_work);
224 cancel_delayed_work_sync(&sc->tx_complete_work);
181fb18d 225 cancel_delayed_work_sync(&sc->hw_pll_work);
9adcf440 226}
5ee08656 227
9adcf440
FF
228static void ath_cancel_work(struct ath_softc *sc)
229{
230 __ath_cancel_work(sc);
231 cancel_work_sync(&sc->hw_reset_work);
232}
3cbb5dd7 233
9adcf440
FF
234static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
235{
236 struct ath_hw *ah = sc->sc_ah;
237 struct ath_common *common = ath9k_hw_common(ah);
238 bool ret;
6a6733f2 239
9adcf440 240 ieee80211_stop_queues(sc->hw);
5e848f78 241
9adcf440
FF
242 sc->hw_busy_count = 0;
243 del_timer_sync(&common->ani.timer);
01e18918 244 del_timer_sync(&sc->rx_poll_timer);
ff37e337 245
9adcf440
FF
246 ath9k_debug_samp_bb_mac(sc);
247 ath9k_hw_disable_interrupts(ah);
8b3f4616 248
9adcf440 249 ret = ath_drain_all_txq(sc, retry_tx);
ff37e337 250
9adcf440
FF
251 if (!ath_stoprecv(sc))
252 ret = false;
c0d7c7af 253
9adcf440
FF
254 if (!flush) {
255 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
3483288c
FF
256 ath_rx_tasklet(sc, 1, true);
257 ath_rx_tasklet(sc, 1, false);
9adcf440
FF
258 } else {
259 ath_flushrecv(sc);
260 }
20bd2a09 261
9adcf440
FF
262 return ret;
263}
ff37e337 264
9adcf440
FF
265static bool ath_complete_reset(struct ath_softc *sc, bool start)
266{
267 struct ath_hw *ah = sc->sc_ah;
268 struct ath_common *common = ath9k_hw_common(ah);
c0d7c7af 269
c0d7c7af 270 if (ath_startrecv(sc) != 0) {
3800276a 271 ath_err(common, "Unable to restart recv logic\n");
9adcf440 272 return false;
c0d7c7af
LR
273 }
274
5048e8c3
RM
275 ath9k_cmn_update_txpow(ah, sc->curtxpow,
276 sc->config.txpowlimit, &sc->curtxpow);
72d874c6 277 ath9k_hw_set_interrupts(ah);
b037b693 278 ath9k_hw_enable_interrupts(ah);
3989279c 279
9adcf440 280 if (!(sc->sc_flags & (SC_OP_OFFCHANNEL)) && start) {
1186488b 281 if (sc->sc_flags & SC_OP_BEACONS)
99e4d43a 282 ath_set_beacon(sc);
9adcf440 283
5ee08656 284 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
181fb18d 285 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
01e18918 286 ath_start_rx_poll(sc, 3);
05c0be2f
MSS
287 if (!common->disable_ani)
288 ath_start_ani(common);
5ee08656
FF
289 }
290
162d12de 291 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3) {
43c35284
FF
292 struct ath_hw_antcomb_conf div_ant_conf;
293 u8 lna_conf;
294
295 ath9k_hw_antdiv_comb_conf_get(ah, &div_ant_conf);
296
297 if (sc->ant_rx == 1)
298 lna_conf = ATH_ANT_DIV_COMB_LNA1;
299 else
300 lna_conf = ATH_ANT_DIV_COMB_LNA2;
301 div_ant_conf.main_lna_conf = lna_conf;
302 div_ant_conf.alt_lna_conf = lna_conf;
303
304 ath9k_hw_antdiv_comb_conf_set(ah, &div_ant_conf);
305 }
306
9adcf440
FF
307 ieee80211_wake_queues(sc->hw);
308
309 return true;
310}
311
312static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
313 bool retry_tx)
314{
315 struct ath_hw *ah = sc->sc_ah;
316 struct ath_common *common = ath9k_hw_common(ah);
317 struct ath9k_hw_cal_data *caldata = NULL;
318 bool fastcc = true;
319 bool flush = false;
320 int r;
321
322 __ath_cancel_work(sc);
323
324 spin_lock_bh(&sc->sc_pcu_lock);
92460412 325
9adcf440
FF
326 if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) {
327 fastcc = false;
328 caldata = &sc->caldata;
329 }
330
331 if (!hchan) {
332 fastcc = false;
333 flush = true;
334 hchan = ah->curchan;
335 }
336
9adcf440
FF
337 if (!ath_prepare_reset(sc, retry_tx, flush))
338 fastcc = false;
339
d2182b69 340 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
feced201 341 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
9adcf440
FF
342
343 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
344 if (r) {
345 ath_err(common,
346 "Unable to reset channel, reset status %d\n", r);
347 goto out;
348 }
349
350 if (!ath_complete_reset(sc, true))
351 r = -EIO;
352
353out:
6a6733f2 354 spin_unlock_bh(&sc->sc_pcu_lock);
9adcf440
FF
355 return r;
356}
357
358
359/*
360 * Set/change channels. If the channel is really being changed, it's done
361 * by reseting the chip. To accomplish this we must first cleanup any pending
362 * DMA, then restart stuff.
363*/
364static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
365 struct ath9k_channel *hchan)
366{
367 int r;
368
369 if (sc->sc_flags & SC_OP_INVALID)
370 return -EIO;
371
9adcf440 372 r = ath_reset_internal(sc, hchan, false);
6a6733f2 373
3989279c 374 return r;
ff37e337
S
375}
376
9f42c2b6
FF
377static void ath_paprd_activate(struct ath_softc *sc)
378{
379 struct ath_hw *ah = sc->sc_ah;
20bd2a09 380 struct ath9k_hw_cal_data *caldata = ah->caldata;
9f42c2b6
FF
381 int chain;
382
20bd2a09 383 if (!caldata || !caldata->paprd_done)
9f42c2b6
FF
384 return;
385
386 ath9k_ps_wakeup(sc);
ddfef792 387 ar9003_paprd_enable(ah, false);
9f42c2b6 388 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
82b2d334 389 if (!(ah->txchainmask & BIT(chain)))
9f42c2b6
FF
390 continue;
391
20bd2a09 392 ar9003_paprd_populate_single_table(ah, caldata, chain);
9f42c2b6
FF
393 }
394
395 ar9003_paprd_enable(ah, true);
396 ath9k_ps_restore(sc);
397}
398
7607cbe2
FF
399static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
400{
401 struct ieee80211_hw *hw = sc->hw;
402 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
47960077
MSS
403 struct ath_hw *ah = sc->sc_ah;
404 struct ath_common *common = ath9k_hw_common(ah);
7607cbe2
FF
405 struct ath_tx_control txctl;
406 int time_left;
407
408 memset(&txctl, 0, sizeof(txctl));
409 txctl.txq = sc->tx.txq_map[WME_AC_BE];
410
411 memset(tx_info, 0, sizeof(*tx_info));
412 tx_info->band = hw->conf.channel->band;
413 tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
414 tx_info->control.rates[0].idx = 0;
415 tx_info->control.rates[0].count = 1;
416 tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
417 tx_info->control.rates[1].idx = -1;
418
419 init_completion(&sc->paprd_complete);
7607cbe2 420 txctl.paprd = BIT(chain);
47960077
MSS
421
422 if (ath_tx_start(hw, skb, &txctl) != 0) {
d2182b69 423 ath_dbg(common, CALIBRATE, "PAPRD TX failed\n");
47960077 424 dev_kfree_skb_any(skb);
7607cbe2 425 return false;
47960077 426 }
7607cbe2
FF
427
428 time_left = wait_for_completion_timeout(&sc->paprd_complete,
429 msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
7607cbe2
FF
430
431 if (!time_left)
d2182b69 432 ath_dbg(common, CALIBRATE,
7607cbe2
FF
433 "Timeout waiting for paprd training on TX chain %d\n",
434 chain);
435
436 return !!time_left;
437}
438
9f42c2b6
FF
439void ath_paprd_calibrate(struct work_struct *work)
440{
441 struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
442 struct ieee80211_hw *hw = sc->hw;
443 struct ath_hw *ah = sc->sc_ah;
444 struct ieee80211_hdr *hdr;
445 struct sk_buff *skb = NULL;
20bd2a09 446 struct ath9k_hw_cal_data *caldata = ah->caldata;
9094537c 447 struct ath_common *common = ath9k_hw_common(ah);
066dae93 448 int ftype;
9f42c2b6
FF
449 int chain_ok = 0;
450 int chain;
451 int len = 1800;
9f42c2b6 452
20bd2a09
FF
453 if (!caldata)
454 return;
455
b942471b
MSS
456 ath9k_ps_wakeup(sc);
457
1bf38661 458 if (ar9003_paprd_init_table(ah) < 0)
b942471b 459 goto fail_paprd;
1bf38661 460
9f42c2b6
FF
461 skb = alloc_skb(len, GFP_KERNEL);
462 if (!skb)
b942471b 463 goto fail_paprd;
9f42c2b6 464
9f42c2b6
FF
465 skb_put(skb, len);
466 memset(skb->data, 0, len);
467 hdr = (struct ieee80211_hdr *)skb->data;
468 ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
469 hdr->frame_control = cpu_to_le16(ftype);
a3d3da14 470 hdr->duration_id = cpu_to_le16(10);
9f42c2b6
FF
471 memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
472 memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
473 memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
474
9f42c2b6 475 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
82b2d334 476 if (!(ah->txchainmask & BIT(chain)))
9f42c2b6
FF
477 continue;
478
479 chain_ok = 0;
9f42c2b6 480
d2182b69
JP
481 ath_dbg(common, CALIBRATE,
482 "Sending PAPRD frame for thermal measurement on chain %d\n",
483 chain);
7607cbe2
FF
484 if (!ath_paprd_send_frame(sc, skb, chain))
485 goto fail_paprd;
9f42c2b6 486
9f42c2b6 487 ar9003_paprd_setup_gain_table(ah, chain);
9f42c2b6 488
d2182b69 489 ath_dbg(common, CALIBRATE,
7607cbe2
FF
490 "Sending PAPRD training frame on chain %d\n", chain);
491 if (!ath_paprd_send_frame(sc, skb, chain))
ca369eb4 492 goto fail_paprd;
9f42c2b6 493
d4bb17c4 494 if (!ar9003_paprd_is_done(ah)) {
d2182b69 495 ath_dbg(common, CALIBRATE,
d4bb17c4 496 "PAPRD not yet done on chain %d\n", chain);
9f42c2b6 497 break;
d4bb17c4 498 }
9f42c2b6 499
d4bb17c4 500 if (ar9003_paprd_create_curve(ah, caldata, chain)) {
d2182b69 501 ath_dbg(common, CALIBRATE,
d4bb17c4
MSS
502 "PAPRD create curve failed on chain %d\n",
503 chain);
9f42c2b6 504 break;
d4bb17c4 505 }
9f42c2b6
FF
506
507 chain_ok = 1;
508 }
509 kfree_skb(skb);
510
511 if (chain_ok) {
20bd2a09 512 caldata->paprd_done = true;
9f42c2b6
FF
513 ath_paprd_activate(sc);
514 }
515
ca369eb4 516fail_paprd:
9f42c2b6
FF
517 ath9k_ps_restore(sc);
518}
519
ff37e337
S
520/*
521 * This routine performs the periodic noise floor calibration function
522 * that is used to adjust and optimize the chip performance. This
523 * takes environmental changes (location, temperature) into account.
524 * When the task is complete, it reschedules itself depending on the
525 * appropriate interval that was calculated.
526 */
55624204 527void ath_ani_calibrate(unsigned long data)
ff37e337 528{
20977d3e
S
529 struct ath_softc *sc = (struct ath_softc *)data;
530 struct ath_hw *ah = sc->sc_ah;
c46917bb 531 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
532 bool longcal = false;
533 bool shortcal = false;
534 bool aniflag = false;
535 unsigned int timestamp = jiffies_to_msecs(jiffies);
6044474e 536 u32 cal_interval, short_cal_interval, long_cal_interval;
b5bfc568 537 unsigned long flags;
6044474e
FF
538
539 if (ah->caldata && ah->caldata->nfcal_interference)
540 long_cal_interval = ATH_LONG_CALINTERVAL_INT;
541 else
542 long_cal_interval = ATH_LONG_CALINTERVAL;
ff37e337 543
20977d3e
S
544 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
545 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337 546
1ffc1c61
JM
547 /* Only calibrate if awake */
548 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
549 goto set_timer;
550
551 ath9k_ps_wakeup(sc);
552
ff37e337 553 /* Long calibration runs independently of short calibration. */
6044474e 554 if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
ff37e337 555 longcal = true;
3d536acf 556 common->ani.longcal_timer = timestamp;
ff37e337
S
557 }
558
17d7904d 559 /* Short calibration applies only while caldone is false */
3d536acf
LR
560 if (!common->ani.caldone) {
561 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 562 shortcal = true;
3d536acf
LR
563 common->ani.shortcal_timer = timestamp;
564 common->ani.resetcal_timer = timestamp;
ff37e337
S
565 }
566 } else {
3d536acf 567 if ((timestamp - common->ani.resetcal_timer) >=
ff37e337 568 ATH_RESTART_CALINTERVAL) {
3d536acf
LR
569 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
570 if (common->ani.caldone)
571 common->ani.resetcal_timer = timestamp;
ff37e337
S
572 }
573 }
574
575 /* Verify whether we must check ANI */
4279425c
NM
576 if (sc->sc_ah->config.enable_ani
577 && (timestamp - common->ani.checkani_timer) >=
578 ah->config.ani_poll_interval) {
ff37e337 579 aniflag = true;
3d536acf 580 common->ani.checkani_timer = timestamp;
ff37e337
S
581 }
582
e62ddec9
MSS
583 /* Call ANI routine if necessary */
584 if (aniflag) {
585 spin_lock_irqsave(&common->cc_lock, flags);
586 ath9k_hw_ani_monitor(ah, ah->curchan);
587 ath_update_survey_stats(sc);
588 spin_unlock_irqrestore(&common->cc_lock, flags);
589 }
ff37e337 590
e62ddec9
MSS
591 /* Perform calibration if necessary */
592 if (longcal || shortcal) {
593 common->ani.caldone =
594 ath9k_hw_calibrate(ah, ah->curchan,
82b2d334 595 ah->rxchainmask, longcal);
ff37e337
S
596 }
597
d2182b69
JP
598 ath_dbg(common, ANI,
599 "Calibration @%lu finished: %s %s %s, caldone: %s\n",
600 jiffies,
86951359
NM
601 longcal ? "long" : "", shortcal ? "short" : "",
602 aniflag ? "ani" : "", common->ani.caldone ? "true" : "false");
603
1ffc1c61
JM
604 ath9k_ps_restore(sc);
605
20977d3e 606set_timer:
ff37e337
S
607 /*
608 * Set timer interval based on previous results.
609 * The interval must be the shortest necessary to satisfy ANI,
610 * short calibration and long calibration.
611 */
cf3af748 612 ath9k_debug_samp_bb_mac(sc);
aac9207e 613 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 614 if (sc->sc_ah->config.enable_ani)
e36b27af
LR
615 cal_interval = min(cal_interval,
616 (u32)ah->config.ani_poll_interval);
3d536acf 617 if (!common->ani.caldone)
20977d3e 618 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 619
3d536acf 620 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
20bd2a09
FF
621 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
622 if (!ah->caldata->paprd_done)
9f42c2b6 623 ieee80211_queue_work(sc->hw, &sc->paprd_work);
45ef6a0b 624 else if (!ah->paprd_table_write_done)
9f42c2b6
FF
625 ath_paprd_activate(sc);
626 }
ff37e337
S
627}
628
7e1e3864
BG
629static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
630 struct ieee80211_vif *vif)
ff37e337
S
631{
632 struct ath_node *an;
ff37e337
S
633 an = (struct ath_node *)sta->drv_priv;
634
7f010c93
BG
635#ifdef CONFIG_ATH9K_DEBUGFS
636 spin_lock(&sc->nodes_lock);
637 list_add(&an->list, &sc->nodes);
638 spin_unlock(&sc->nodes_lock);
156369fa 639#endif
7f010c93 640 an->sta = sta;
7e1e3864 641 an->vif = vif;
3d4e20f2 642
a4d6367f 643 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337 644 ath_tx_node_init(sc, an);
9e98ac65 645 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S
646 sta->ht_cap.ampdu_factor);
647 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
648 }
ff37e337
S
649}
650
651static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
652{
653 struct ath_node *an = (struct ath_node *)sta->drv_priv;
654
7f010c93
BG
655#ifdef CONFIG_ATH9K_DEBUGFS
656 spin_lock(&sc->nodes_lock);
657 list_del(&an->list);
658 spin_unlock(&sc->nodes_lock);
659 an->sta = NULL;
660#endif
661
a4d6367f 662 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
ff37e337
S
663 ath_tx_node_cleanup(sc, an);
664}
665
9eab61c2 666
55624204 667void ath9k_tasklet(unsigned long data)
ff37e337
S
668{
669 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 670 struct ath_hw *ah = sc->sc_ah;
c46917bb 671 struct ath_common *common = ath9k_hw_common(ah);
af03abec 672
17d7904d 673 u32 status = sc->intrstatus;
b5c80475 674 u32 rxmask;
ff37e337 675
e3927007
FF
676 ath9k_ps_wakeup(sc);
677 spin_lock(&sc->sc_pcu_lock);
678
a4d86d95
RM
679 if ((status & ATH9K_INT_FATAL) ||
680 (status & ATH9K_INT_BB_WATCHDOG)) {
030d6294
FF
681#ifdef CONFIG_ATH9K_DEBUGFS
682 enum ath_reset_type type;
683
684 if (status & ATH9K_INT_FATAL)
685 type = RESET_TYPE_FATAL_INT;
686 else
687 type = RESET_TYPE_BB_WATCHDOG;
688
689 RESET_STAT_INC(sc, type);
690#endif
236de514 691 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
e3927007 692 goto out;
063d8be3 693 }
ff37e337 694
4105f807
RM
695 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
696 /*
697 * TSF sync does not look correct; remain awake to sync with
698 * the next Beacon.
699 */
d2182b69 700 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
e8fe7336 701 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
4105f807
RM
702 }
703
b5c80475
FF
704 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
705 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
706 ATH9K_INT_RXORN);
707 else
708 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
709
710 if (status & rxmask) {
b5c80475
FF
711 /* Check for high priority Rx first */
712 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
713 (status & ATH9K_INT_RXHP))
714 ath_rx_tasklet(sc, 0, true);
715
716 ath_rx_tasklet(sc, 0, false);
ff37e337
S
717 }
718
e5003249
VT
719 if (status & ATH9K_INT_TX) {
720 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
721 ath_tx_edma_tasklet(sc);
722 else
723 ath_tx_tasklet(sc);
724 }
063d8be3 725
56ca0dba 726 ath9k_btcoex_handle_interrupt(sc, status);
19686ddf 727
e3927007 728out:
ff37e337 729 /* re-enable hardware interrupt */
4df3071e 730 ath9k_hw_enable_interrupts(ah);
6a6733f2 731
52671e43 732 spin_unlock(&sc->sc_pcu_lock);
153e080d 733 ath9k_ps_restore(sc);
ff37e337
S
734}
735
6baff7f9 736irqreturn_t ath_isr(int irq, void *dev)
ff37e337 737{
063d8be3
S
738#define SCHED_INTR ( \
739 ATH9K_INT_FATAL | \
a4d86d95 740 ATH9K_INT_BB_WATCHDOG | \
063d8be3
S
741 ATH9K_INT_RXORN | \
742 ATH9K_INT_RXEOL | \
743 ATH9K_INT_RX | \
b5c80475
FF
744 ATH9K_INT_RXLP | \
745 ATH9K_INT_RXHP | \
063d8be3
S
746 ATH9K_INT_TX | \
747 ATH9K_INT_BMISS | \
748 ATH9K_INT_CST | \
ebb8e1d7 749 ATH9K_INT_TSFOOR | \
40dc5392
MSS
750 ATH9K_INT_GENTIMER | \
751 ATH9K_INT_MCI)
063d8be3 752
ff37e337 753 struct ath_softc *sc = dev;
cbe61d8a 754 struct ath_hw *ah = sc->sc_ah;
b5bfc568 755 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
756 enum ath9k_int status;
757 bool sched = false;
758
063d8be3
S
759 /*
760 * The hardware is not ready/present, don't
761 * touch anything. Note this can happen early
762 * on if the IRQ is shared.
763 */
764 if (sc->sc_flags & SC_OP_INVALID)
765 return IRQ_NONE;
ff37e337 766
063d8be3
S
767
768 /* shared irq, not for us */
769
153e080d 770 if (!ath9k_hw_intrpend(ah))
063d8be3 771 return IRQ_NONE;
063d8be3
S
772
773 /*
774 * Figure out the reason(s) for the interrupt. Note
775 * that the hal returns a pseudo-ISR that may include
776 * bits we haven't explicitly enabled so we mask the
777 * value to insure we only process bits we requested.
778 */
779 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
3069168c 780 status &= ah->imask; /* discard unasked-for bits */
ff37e337 781
063d8be3
S
782 /*
783 * If there are no status bits set, then this interrupt was not
784 * for me (should have been caught above).
785 */
153e080d 786 if (!status)
063d8be3 787 return IRQ_NONE;
ff37e337 788
063d8be3
S
789 /* Cache the status */
790 sc->intrstatus = status;
791
792 if (status & SCHED_INTR)
793 sched = true;
794
795 /*
796 * If a FATAL or RXORN interrupt is received, we have to reset the
797 * chip immediately.
798 */
b5c80475
FF
799 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
800 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
063d8be3
S
801 goto chip_reset;
802
08578b8f
LR
803 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
804 (status & ATH9K_INT_BB_WATCHDOG)) {
b5bfc568
FF
805
806 spin_lock(&common->cc_lock);
807 ath_hw_cycle_counters_update(common);
08578b8f 808 ar9003_hw_bb_watchdog_dbg_info(ah);
b5bfc568
FF
809 spin_unlock(&common->cc_lock);
810
08578b8f
LR
811 goto chip_reset;
812 }
813
063d8be3
S
814 if (status & ATH9K_INT_SWBA)
815 tasklet_schedule(&sc->bcon_tasklet);
816
817 if (status & ATH9K_INT_TXURN)
818 ath9k_hw_updatetxtriglevel(ah, true);
819
0682c9b5
RM
820 if (status & ATH9K_INT_RXEOL) {
821 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
72d874c6 822 ath9k_hw_set_interrupts(ah);
b5c80475
FF
823 }
824
063d8be3 825 if (status & ATH9K_INT_MIB) {
ff37e337 826 /*
063d8be3
S
827 * Disable interrupts until we service the MIB
828 * interrupt; otherwise it will continue to
829 * fire.
ff37e337 830 */
4df3071e 831 ath9k_hw_disable_interrupts(ah);
063d8be3
S
832 /*
833 * Let the hal handle the event. We assume
834 * it will clear whatever condition caused
835 * the interrupt.
836 */
88eac2da 837 spin_lock(&common->cc_lock);
bfc472bb 838 ath9k_hw_proc_mib_event(ah);
88eac2da 839 spin_unlock(&common->cc_lock);
4df3071e 840 ath9k_hw_enable_interrupts(ah);
063d8be3 841 }
ff37e337 842
153e080d
VT
843 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
844 if (status & ATH9K_INT_TIM_TIMER) {
ff9f0b63
LR
845 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
846 goto chip_reset;
063d8be3
S
847 /* Clear RxAbort bit so that we can
848 * receive frames */
9ecdef4b 849 ath9k_setpower(sc, ATH9K_PM_AWAKE);
153e080d 850 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930 851 sc->ps_flags |= PS_WAIT_FOR_BEACON;
ff37e337 852 }
063d8be3
S
853
854chip_reset:
ff37e337 855
817e11de
S
856 ath_debug_stat_interrupt(sc, status);
857
ff37e337 858 if (sched) {
4df3071e
FF
859 /* turn off every interrupt */
860 ath9k_hw_disable_interrupts(ah);
ff37e337
S
861 tasklet_schedule(&sc->intr_tq);
862 }
863
864 return IRQ_HANDLED;
063d8be3
S
865
866#undef SCHED_INTR
ff37e337
S
867}
868
236de514 869static int ath_reset(struct ath_softc *sc, bool retry_tx)
ff37e337 870{
ae8d2858 871 int r;
ff37e337 872
783cd01e 873 ath9k_ps_wakeup(sc);
6a6733f2 874
9adcf440 875 r = ath_reset_internal(sc, NULL, retry_tx);
ff37e337
S
876
877 if (retry_tx) {
878 int i;
879 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
880 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S
881 spin_lock_bh(&sc->tx.txq[i].axq_lock);
882 ath_txq_schedule(sc, &sc->tx.txq[i]);
883 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S
884 }
885 }
886 }
887
783cd01e 888 ath9k_ps_restore(sc);
2ab81d4a 889
ae8d2858 890 return r;
ff37e337
S
891}
892
236de514
FF
893void ath_reset_work(struct work_struct *work)
894{
895 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
896
236de514 897 ath_reset(sc, true);
236de514
FF
898}
899
e8cfe9f8
FF
900void ath_hw_check(struct work_struct *work)
901{
902 struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
903 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
904 unsigned long flags;
905 int busy;
01e18918 906 u8 is_alive, nbeacon = 1;
e8cfe9f8
FF
907
908 ath9k_ps_wakeup(sc);
01e18918
RM
909 is_alive = ath9k_hw_check_alive(sc->sc_ah);
910
911 if (is_alive && !AR_SREV_9300(sc->sc_ah))
e8cfe9f8 912 goto out;
01e18918
RM
913 else if (!is_alive && AR_SREV_9300(sc->sc_ah)) {
914 ath_dbg(common, RESET,
915 "DCU stuck is detected. Schedule chip reset\n");
916 RESET_STAT_INC(sc, RESET_TYPE_MAC_HANG);
917 goto sched_reset;
918 }
e8cfe9f8
FF
919
920 spin_lock_irqsave(&common->cc_lock, flags);
921 busy = ath_update_survey_stats(sc);
922 spin_unlock_irqrestore(&common->cc_lock, flags);
923
d2182b69
JP
924 ath_dbg(common, RESET, "Possible baseband hang, busy=%d (try %d)\n",
925 busy, sc->hw_busy_count + 1);
e8cfe9f8 926 if (busy >= 99) {
030d6294
FF
927 if (++sc->hw_busy_count >= 3) {
928 RESET_STAT_INC(sc, RESET_TYPE_BB_HANG);
01e18918 929 goto sched_reset;
030d6294 930 }
01e18918 931 } else if (busy >= 0) {
e8cfe9f8 932 sc->hw_busy_count = 0;
01e18918
RM
933 nbeacon = 3;
934 }
e8cfe9f8 935
01e18918
RM
936 ath_start_rx_poll(sc, nbeacon);
937 goto out;
938
939sched_reset:
940 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
e8cfe9f8
FF
941out:
942 ath9k_ps_restore(sc);
943}
944
945static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)
946{
947 static int count;
948 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
949
950 if (pll_sqsum >= 0x40000) {
951 count++;
952 if (count == 3) {
953 /* Rx is hung for more than 500ms. Reset it */
d2182b69 954 ath_dbg(common, RESET, "Possible RX hang, resetting\n");
030d6294 955 RESET_STAT_INC(sc, RESET_TYPE_PLL_HANG);
9adcf440 956 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
e8cfe9f8
FF
957 count = 0;
958 }
959 } else
960 count = 0;
961}
962
963void ath_hw_pll_work(struct work_struct *work)
964{
965 struct ath_softc *sc = container_of(work, struct ath_softc,
966 hw_pll_work.work);
967 u32 pll_sqsum;
968
969 if (AR_SREV_9485(sc->sc_ah)) {
970
971 ath9k_ps_wakeup(sc);
972 pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah);
973 ath9k_ps_restore(sc);
974
975 ath_hw_pll_rx_hang_check(sc, pll_sqsum);
976
977 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5);
978 }
979}
980
ff37e337
S
981/**********************/
982/* mac80211 callbacks */
983/**********************/
984
8feceb67 985static int ath9k_start(struct ieee80211_hw *hw)
f078f209 986{
9ac58615 987 struct ath_softc *sc = hw->priv;
af03abec 988 struct ath_hw *ah = sc->sc_ah;
c46917bb 989 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 990 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 991 struct ath9k_channel *init_channel;
82880a7c 992 int r;
f078f209 993
d2182b69 994 ath_dbg(common, CONFIG,
226afe68
JP
995 "Starting driver with initial channel: %d MHz\n",
996 curchan->center_freq);
f078f209 997
f62d816f 998 ath9k_ps_wakeup(sc);
141b38b6
S
999 mutex_lock(&sc->mutex);
1000
c344c9cb 1001 init_channel = ath9k_cmn_get_curchannel(hw, ah);
ff37e337
S
1002
1003 /* Reset SERDES registers */
84c87dc8 1004 ath9k_hw_configpcipowersave(ah, false);
ff37e337
S
1005
1006 /*
1007 * The basic interface to setting the hardware in a good
1008 * state is ``reset''. On return the hardware is known to
1009 * be powered up and with interrupts disabled. This must
1010 * be followed by initialization of the appropriate bits
1011 * and then setup of the interrupt mask.
1012 */
4bdd1e97 1013 spin_lock_bh(&sc->sc_pcu_lock);
c0c11741
FF
1014
1015 atomic_set(&ah->intr_ref_cnt, -1);
1016
20bd2a09 1017 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
ae8d2858 1018 if (r) {
3800276a
JP
1019 ath_err(common,
1020 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
1021 r, curchan->center_freq);
4bdd1e97 1022 spin_unlock_bh(&sc->sc_pcu_lock);
141b38b6 1023 goto mutex_unlock;
ff37e337 1024 }
ff37e337 1025
ff37e337 1026 /* Setup our intr mask. */
b5c80475
FF
1027 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
1028 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
1029 ATH9K_INT_GLOBAL;
1030
1031 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
08578b8f
LR
1032 ah->imask |= ATH9K_INT_RXHP |
1033 ATH9K_INT_RXLP |
1034 ATH9K_INT_BB_WATCHDOG;
b5c80475
FF
1035 else
1036 ah->imask |= ATH9K_INT_RX;
ff37e337 1037
364734fa 1038 ah->imask |= ATH9K_INT_GTT;
ff37e337 1039
af03abec 1040 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
3069168c 1041 ah->imask |= ATH9K_INT_CST;
ff37e337 1042
40dc5392
MSS
1043 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
1044 ah->imask |= ATH9K_INT_MCI;
1045
ff37e337 1046 sc->sc_flags &= ~SC_OP_INVALID;
5f841b41 1047 sc->sc_ah->is_monitoring = false;
ff37e337 1048
9adcf440
FF
1049 if (!ath_complete_reset(sc, false)) {
1050 r = -EIO;
1051 spin_unlock_bh(&sc->sc_pcu_lock);
1052 goto mutex_unlock;
1053 }
ff37e337 1054
c0c11741
FF
1055 if (ah->led_pin >= 0) {
1056 ath9k_hw_cfg_output(ah, ah->led_pin,
1057 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1058 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
1059 }
1060
1061 /*
1062 * Reset key cache to sane defaults (all entries cleared) instead of
1063 * semi-random values after suspend/resume.
1064 */
1065 ath9k_cmn_init_crypto(sc->sc_ah);
1066
9adcf440 1067 spin_unlock_bh(&sc->sc_pcu_lock);
164ace38 1068
df198b17 1069 ath9k_start_btcoex(sc);
1773912b 1070
8060e169
VT
1071 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
1072 common->bus_ops->extn_synch_en(common);
1073
141b38b6
S
1074mutex_unlock:
1075 mutex_unlock(&sc->mutex);
1076
f62d816f
FF
1077 ath9k_ps_restore(sc);
1078
ae8d2858 1079 return r;
f078f209
LR
1080}
1081
7bb45683 1082static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
f078f209 1083{
9ac58615 1084 struct ath_softc *sc = hw->priv;
c46917bb 1085 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 1086 struct ath_tx_control txctl;
1bc14880 1087 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
528f0c6b 1088
96148326 1089 if (sc->ps_enabled) {
dc8c4585
JM
1090 /*
1091 * mac80211 does not set PM field for normal data frames, so we
1092 * need to update that based on the current PS mode.
1093 */
1094 if (ieee80211_is_data(hdr->frame_control) &&
1095 !ieee80211_is_nullfunc(hdr->frame_control) &&
1096 !ieee80211_has_pm(hdr->frame_control)) {
d2182b69 1097 ath_dbg(common, PS,
226afe68 1098 "Add PM=1 for a TX frame while in PS mode\n");
dc8c4585
JM
1099 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1100 }
1101 }
1102
c8e8868e
FF
1103 /*
1104 * Cannot tx while the hardware is in full sleep, it first needs a full
1105 * chip reset to recover from that
1106 */
1107 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP))
1108 goto exit;
1109
9a23f9ca
JM
1110 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
1111 /*
1112 * We are using PS-Poll and mac80211 can request TX while in
1113 * power save mode. Need to wake up hardware for the TX to be
1114 * completed and if needed, also for RX of buffered frames.
1115 */
9a23f9ca 1116 ath9k_ps_wakeup(sc);
fdf76622
VT
1117 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
1118 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca 1119 if (ieee80211_is_pspoll(hdr->frame_control)) {
d2182b69 1120 ath_dbg(common, PS,
226afe68 1121 "Sending PS-Poll to pick a buffered frame\n");
1b04b930 1122 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
9a23f9ca 1123 } else {
d2182b69 1124 ath_dbg(common, PS, "Wake up to complete TX\n");
1b04b930 1125 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
9a23f9ca
JM
1126 }
1127 /*
1128 * The actual restore operation will happen only after
1129 * the sc_flags bit is cleared. We are just dropping
1130 * the ps_usecount here.
1131 */
1132 ath9k_ps_restore(sc);
1133 }
1134
528f0c6b 1135 memset(&txctl, 0, sizeof(struct ath_tx_control));
066dae93 1136 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
528f0c6b 1137
d2182b69 1138 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 1139
c52f33d0 1140 if (ath_tx_start(hw, skb, &txctl) != 0) {
d2182b69 1141 ath_dbg(common, XMIT, "TX failed\n");
a5a0bca1 1142 TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
528f0c6b 1143 goto exit;
8feceb67
VT
1144 }
1145
7bb45683 1146 return;
528f0c6b
S
1147exit:
1148 dev_kfree_skb_any(skb);
f078f209
LR
1149}
1150
8feceb67 1151static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 1152{
9ac58615 1153 struct ath_softc *sc = hw->priv;
af03abec 1154 struct ath_hw *ah = sc->sc_ah;
c46917bb 1155 struct ath_common *common = ath9k_hw_common(ah);
c0c11741 1156 bool prev_idle;
f078f209 1157
4c483817
S
1158 mutex_lock(&sc->mutex);
1159
9adcf440 1160 ath_cancel_work(sc);
01e18918 1161 del_timer_sync(&sc->rx_poll_timer);
c94dbff7 1162
9c84b797 1163 if (sc->sc_flags & SC_OP_INVALID) {
d2182b69 1164 ath_dbg(common, ANY, "Device not present\n");
4c483817 1165 mutex_unlock(&sc->mutex);
9c84b797
S
1166 return;
1167 }
8feceb67 1168
3867cf6a
S
1169 /* Ensure HW is awake when we try to shut it down. */
1170 ath9k_ps_wakeup(sc);
1171
df198b17 1172 ath9k_stop_btcoex(sc);
1773912b 1173
6a6733f2
LR
1174 spin_lock_bh(&sc->sc_pcu_lock);
1175
203043f5
SG
1176 /* prevent tasklets to enable interrupts once we disable them */
1177 ah->imask &= ~ATH9K_INT_GLOBAL;
1178
ff37e337
S
1179 /* make sure h/w will not generate any interrupt
1180 * before setting the invalid flag. */
4df3071e 1181 ath9k_hw_disable_interrupts(ah);
ff37e337 1182
c0c11741
FF
1183 spin_unlock_bh(&sc->sc_pcu_lock);
1184
1185 /* we can now sync irq and kill any running tasklets, since we already
1186 * disabled interrupts and not holding a spin lock */
1187 synchronize_irq(sc->irq);
1188 tasklet_kill(&sc->intr_tq);
1189 tasklet_kill(&sc->bcon_tasklet);
1190
1191 prev_idle = sc->ps_idle;
1192 sc->ps_idle = true;
1193
1194 spin_lock_bh(&sc->sc_pcu_lock);
1195
1196 if (ah->led_pin >= 0) {
1197 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1198 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
1199 }
1200
1201 ath_prepare_reset(sc, false, true);
ff37e337 1202
0d95521e
FF
1203 if (sc->rx.frag) {
1204 dev_kfree_skb_any(sc->rx.frag);
1205 sc->rx.frag = NULL;
1206 }
1207
c0c11741
FF
1208 if (!ah->curchan)
1209 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
6a6733f2 1210
c0c11741
FF
1211 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
1212 ath9k_hw_phy_disable(ah);
6a6733f2 1213
c0c11741 1214 ath9k_hw_configpcipowersave(ah, true);
203043f5 1215
c0c11741 1216 spin_unlock_bh(&sc->sc_pcu_lock);
3867cf6a 1217
c0c11741 1218 ath9k_ps_restore(sc);
ff37e337
S
1219
1220 sc->sc_flags |= SC_OP_INVALID;
c0c11741 1221 sc->ps_idle = prev_idle;
500c064d 1222
141b38b6
S
1223 mutex_unlock(&sc->mutex);
1224
d2182b69 1225 ath_dbg(common, CONFIG, "Driver halt\n");
f078f209
LR
1226}
1227
4801416c
BG
1228bool ath9k_uses_beacons(int type)
1229{
1230 switch (type) {
1231 case NL80211_IFTYPE_AP:
1232 case NL80211_IFTYPE_ADHOC:
1233 case NL80211_IFTYPE_MESH_POINT:
1234 return true;
1235 default:
1236 return false;
1237 }
1238}
1239
1240static void ath9k_reclaim_beacon(struct ath_softc *sc,
1241 struct ieee80211_vif *vif)
f078f209 1242{
1ed32e4f 1243 struct ath_vif *avp = (void *)vif->drv_priv;
8feceb67 1244
014cf3bb 1245 ath9k_set_beaconing_status(sc, false);
4801416c 1246 ath_beacon_return(sc, avp);
014cf3bb 1247 ath9k_set_beaconing_status(sc, true);
4801416c 1248 sc->sc_flags &= ~SC_OP_BEACONS;
4801416c
BG
1249}
1250
1251static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1252{
1253 struct ath9k_vif_iter_data *iter_data = data;
1254 int i;
1255
1256 if (iter_data->hw_macaddr)
1257 for (i = 0; i < ETH_ALEN; i++)
1258 iter_data->mask[i] &=
1259 ~(iter_data->hw_macaddr[i] ^ mac[i]);
141b38b6 1260
1ed32e4f 1261 switch (vif->type) {
4801416c
BG
1262 case NL80211_IFTYPE_AP:
1263 iter_data->naps++;
f078f209 1264 break;
4801416c
BG
1265 case NL80211_IFTYPE_STATION:
1266 iter_data->nstations++;
e51f3eff 1267 break;
05c914fe 1268 case NL80211_IFTYPE_ADHOC:
4801416c
BG
1269 iter_data->nadhocs++;
1270 break;
9cb5412b 1271 case NL80211_IFTYPE_MESH_POINT:
4801416c
BG
1272 iter_data->nmeshes++;
1273 break;
1274 case NL80211_IFTYPE_WDS:
1275 iter_data->nwds++;
f078f209
LR
1276 break;
1277 default:
4801416c 1278 break;
f078f209 1279 }
4801416c 1280}
f078f209 1281
4801416c
BG
1282/* Called with sc->mutex held. */
1283void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
1284 struct ieee80211_vif *vif,
1285 struct ath9k_vif_iter_data *iter_data)
1286{
9ac58615 1287 struct ath_softc *sc = hw->priv;
4801416c
BG
1288 struct ath_hw *ah = sc->sc_ah;
1289 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 1290
4801416c
BG
1291 /*
1292 * Use the hardware MAC address as reference, the hardware uses it
1293 * together with the BSSID mask when matching addresses.
1294 */
1295 memset(iter_data, 0, sizeof(*iter_data));
1296 iter_data->hw_macaddr = common->macaddr;
1297 memset(&iter_data->mask, 0xff, ETH_ALEN);
5640b08e 1298
4801416c
BG
1299 if (vif)
1300 ath9k_vif_iter(iter_data, vif->addr, vif);
1301
1302 /* Get list of all active MAC addresses */
4801416c
BG
1303 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
1304 iter_data);
4801416c 1305}
8ca21f01 1306
4801416c
BG
1307/* Called with sc->mutex held. */
1308static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
1309 struct ieee80211_vif *vif)
1310{
9ac58615 1311 struct ath_softc *sc = hw->priv;
4801416c
BG
1312 struct ath_hw *ah = sc->sc_ah;
1313 struct ath_common *common = ath9k_hw_common(ah);
1314 struct ath9k_vif_iter_data iter_data;
8ca21f01 1315
4801416c 1316 ath9k_calculate_iter_data(hw, vif, &iter_data);
2c3db3d5 1317
4801416c
BG
1318 /* Set BSSID mask. */
1319 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1320 ath_hw_setbssidmask(common);
1321
1322 /* Set op-mode & TSF */
1323 if (iter_data.naps > 0) {
3069168c 1324 ath9k_hw_set_tsfadjust(ah, 1);
b238e90e 1325 sc->sc_flags |= SC_OP_TSF_RESET;
4801416c
BG
1326 ah->opmode = NL80211_IFTYPE_AP;
1327 } else {
1328 ath9k_hw_set_tsfadjust(ah, 0);
1329 sc->sc_flags &= ~SC_OP_TSF_RESET;
5640b08e 1330
fd5999cf
JC
1331 if (iter_data.nmeshes)
1332 ah->opmode = NL80211_IFTYPE_MESH_POINT;
1333 else if (iter_data.nwds)
4801416c
BG
1334 ah->opmode = NL80211_IFTYPE_AP;
1335 else if (iter_data.nadhocs)
1336 ah->opmode = NL80211_IFTYPE_ADHOC;
1337 else
1338 ah->opmode = NL80211_IFTYPE_STATION;
1339 }
5640b08e 1340
4e30ffa2
VN
1341 /*
1342 * Enable MIB interrupts when there are hardware phy counters.
4e30ffa2 1343 */
4801416c 1344 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
3448f912
LR
1345 if (ah->config.enable_ani)
1346 ah->imask |= ATH9K_INT_MIB;
3069168c 1347 ah->imask |= ATH9K_INT_TSFOOR;
4801416c
BG
1348 } else {
1349 ah->imask &= ~ATH9K_INT_MIB;
1350 ah->imask &= ~ATH9K_INT_TSFOOR;
4af9cf4f
S
1351 }
1352
72d874c6 1353 ath9k_hw_set_interrupts(ah);
4e30ffa2 1354
4801416c 1355 /* Set up ANI */
2e5ef459 1356 if (iter_data.naps > 0) {
729da390 1357 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
05c0be2f
MSS
1358
1359 if (!common->disable_ani) {
1360 sc->sc_flags |= SC_OP_ANI_RUN;
1361 ath_start_ani(common);
1362 }
1363
f60c49b6
RM
1364 } else {
1365 sc->sc_flags &= ~SC_OP_ANI_RUN;
1366 del_timer_sync(&common->ani.timer);
6c3118e2 1367 }
4801416c 1368}
6f255425 1369
4801416c
BG
1370/* Called with sc->mutex held, vif counts set up properly. */
1371static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
1372 struct ieee80211_vif *vif)
1373{
9ac58615 1374 struct ath_softc *sc = hw->priv;
4801416c
BG
1375
1376 ath9k_calculate_summary_state(hw, vif);
1377
1378 if (ath9k_uses_beacons(vif->type)) {
1379 int error;
4801416c
BG
1380 /* This may fail because upper levels do not have beacons
1381 * properly configured yet. That's OK, we assume it
1382 * will be properly configured and then we will be notified
1383 * in the info_changed method and set up beacons properly
1384 * there.
1385 */
014cf3bb 1386 ath9k_set_beaconing_status(sc, false);
9ac58615 1387 error = ath_beacon_alloc(sc, vif);
391bd1c4 1388 if (!error)
4801416c 1389 ath_beacon_config(sc, vif);
014cf3bb 1390 ath9k_set_beaconing_status(sc, true);
4801416c 1391 }
f078f209
LR
1392}
1393
01e18918
RM
1394void ath_start_rx_poll(struct ath_softc *sc, u8 nbeacon)
1395{
1396 if (!AR_SREV_9300(sc->sc_ah))
1397 return;
1398
1399 if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF))
1400 return;
1401
1402 mod_timer(&sc->rx_poll_timer, jiffies + msecs_to_jiffies
1403 (nbeacon * sc->cur_beacon_conf.beacon_interval));
1404}
1405
1406void ath_rx_poll(unsigned long data)
1407{
1408 struct ath_softc *sc = (struct ath_softc *)data;
1409
1410 ieee80211_queue_work(sc->hw, &sc->hw_check_work);
1411}
4801416c
BG
1412
1413static int ath9k_add_interface(struct ieee80211_hw *hw,
1414 struct ieee80211_vif *vif)
6b3b991d 1415{
9ac58615 1416 struct ath_softc *sc = hw->priv;
4801416c
BG
1417 struct ath_hw *ah = sc->sc_ah;
1418 struct ath_common *common = ath9k_hw_common(ah);
4801416c 1419 int ret = 0;
6b3b991d 1420
96f372c9 1421 ath9k_ps_wakeup(sc);
4801416c 1422 mutex_lock(&sc->mutex);
6b3b991d 1423
4801416c
BG
1424 switch (vif->type) {
1425 case NL80211_IFTYPE_STATION:
1426 case NL80211_IFTYPE_WDS:
1427 case NL80211_IFTYPE_ADHOC:
1428 case NL80211_IFTYPE_AP:
1429 case NL80211_IFTYPE_MESH_POINT:
1430 break;
1431 default:
1432 ath_err(common, "Interface type %d not yet supported\n",
1433 vif->type);
1434 ret = -EOPNOTSUPP;
1435 goto out;
1436 }
6b3b991d 1437
4801416c
BG
1438 if (ath9k_uses_beacons(vif->type)) {
1439 if (sc->nbcnvifs >= ATH_BCBUF) {
1440 ath_err(common, "Not enough beacon buffers when adding"
1441 " new interface of type: %i\n",
1442 vif->type);
1443 ret = -ENOBUFS;
1444 goto out;
1445 }
1446 }
1447
59575d1c
RM
1448 if ((ah->opmode == NL80211_IFTYPE_ADHOC) ||
1449 ((vif->type == NL80211_IFTYPE_ADHOC) &&
1450 sc->nvifs > 0)) {
4801416c
BG
1451 ath_err(common, "Cannot create ADHOC interface when other"
1452 " interfaces already exist.\n");
1453 ret = -EINVAL;
1454 goto out;
6b3b991d 1455 }
4801416c 1456
d2182b69 1457 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
4801416c 1458
4801416c
BG
1459 sc->nvifs++;
1460
1461 ath9k_do_vif_add_setup(hw, vif);
1462out:
1463 mutex_unlock(&sc->mutex);
96f372c9 1464 ath9k_ps_restore(sc);
4801416c 1465 return ret;
6b3b991d
RM
1466}
1467
1468static int ath9k_change_interface(struct ieee80211_hw *hw,
1469 struct ieee80211_vif *vif,
1470 enum nl80211_iftype new_type,
1471 bool p2p)
1472{
9ac58615 1473 struct ath_softc *sc = hw->priv;
6b3b991d 1474 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
6dab55bf 1475 int ret = 0;
6b3b991d 1476
d2182b69 1477 ath_dbg(common, CONFIG, "Change Interface\n");
6b3b991d 1478 mutex_lock(&sc->mutex);
96f372c9 1479 ath9k_ps_wakeup(sc);
6b3b991d 1480
4801416c
BG
1481 /* See if new interface type is valid. */
1482 if ((new_type == NL80211_IFTYPE_ADHOC) &&
1483 (sc->nvifs > 1)) {
1484 ath_err(common, "When using ADHOC, it must be the only"
1485 " interface.\n");
1486 ret = -EINVAL;
1487 goto out;
1488 }
1489
1490 if (ath9k_uses_beacons(new_type) &&
1491 !ath9k_uses_beacons(vif->type)) {
6b3b991d
RM
1492 if (sc->nbcnvifs >= ATH_BCBUF) {
1493 ath_err(common, "No beacon slot available\n");
6dab55bf
DC
1494 ret = -ENOBUFS;
1495 goto out;
6b3b991d 1496 }
6b3b991d 1497 }
4801416c
BG
1498
1499 /* Clean up old vif stuff */
1500 if (ath9k_uses_beacons(vif->type))
1501 ath9k_reclaim_beacon(sc, vif);
1502
1503 /* Add new settings */
6b3b991d
RM
1504 vif->type = new_type;
1505 vif->p2p = p2p;
1506
4801416c 1507 ath9k_do_vif_add_setup(hw, vif);
6dab55bf 1508out:
96f372c9 1509 ath9k_ps_restore(sc);
6b3b991d 1510 mutex_unlock(&sc->mutex);
6dab55bf 1511 return ret;
6b3b991d
RM
1512}
1513
8feceb67 1514static void ath9k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1515 struct ieee80211_vif *vif)
f078f209 1516{
9ac58615 1517 struct ath_softc *sc = hw->priv;
c46917bb 1518 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
f078f209 1519
d2182b69 1520 ath_dbg(common, CONFIG, "Detach Interface\n");
f078f209 1521
96f372c9 1522 ath9k_ps_wakeup(sc);
141b38b6
S
1523 mutex_lock(&sc->mutex);
1524
4801416c 1525 sc->nvifs--;
580f0b8a 1526
8feceb67 1527 /* Reclaim beacon resources */
4801416c 1528 if (ath9k_uses_beacons(vif->type))
6b3b991d 1529 ath9k_reclaim_beacon(sc, vif);
2c3db3d5 1530
4801416c 1531 ath9k_calculate_summary_state(hw, NULL);
141b38b6
S
1532
1533 mutex_unlock(&sc->mutex);
96f372c9 1534 ath9k_ps_restore(sc);
f078f209
LR
1535}
1536
fbab7390 1537static void ath9k_enable_ps(struct ath_softc *sc)
3f7c5c10 1538{
3069168c
PR
1539 struct ath_hw *ah = sc->sc_ah;
1540
3f7c5c10 1541 sc->ps_enabled = true;
3069168c
PR
1542 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1543 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1544 ah->imask |= ATH9K_INT_TIM_TIMER;
72d874c6 1545 ath9k_hw_set_interrupts(ah);
3f7c5c10 1546 }
fdf76622 1547 ath9k_hw_setrxabort(ah, 1);
3f7c5c10 1548 }
3f7c5c10
SB
1549}
1550
845d708e
SB
1551static void ath9k_disable_ps(struct ath_softc *sc)
1552{
1553 struct ath_hw *ah = sc->sc_ah;
1554
1555 sc->ps_enabled = false;
1556 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1557 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1558 ath9k_hw_setrxabort(ah, 0);
1559 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1560 PS_WAIT_FOR_CAB |
1561 PS_WAIT_FOR_PSPOLL_DATA |
1562 PS_WAIT_FOR_TX_ACK);
1563 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1564 ah->imask &= ~ATH9K_INT_TIM_TIMER;
72d874c6 1565 ath9k_hw_set_interrupts(ah);
845d708e
SB
1566 }
1567 }
1568
1569}
1570
e8975581 1571static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1572{
9ac58615 1573 struct ath_softc *sc = hw->priv;
3430098a
FF
1574 struct ath_hw *ah = sc->sc_ah;
1575 struct ath_common *common = ath9k_hw_common(ah);
e8975581 1576 struct ieee80211_conf *conf = &hw->conf;
f078f209 1577
c0c11741 1578 ath9k_ps_wakeup(sc);
aa33de09 1579 mutex_lock(&sc->mutex);
141b38b6 1580
daa1b6ee 1581 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
7545daf4 1582 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
daa1b6ee
FF
1583 if (sc->ps_idle)
1584 ath_cancel_work(sc);
1585 }
64839170 1586
e7824a50
LR
1587 /*
1588 * We just prepare to enable PS. We have to wait until our AP has
1589 * ACK'd our null data frame to disable RX otherwise we'll ignore
1590 * those ACKs and end up retransmitting the same null data frames.
1591 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1592 */
3cbb5dd7 1593 if (changed & IEEE80211_CONF_CHANGE_PS) {
8ab2cd09
LR
1594 unsigned long flags;
1595 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fbab7390
SB
1596 if (conf->flags & IEEE80211_CONF_PS)
1597 ath9k_enable_ps(sc);
845d708e
SB
1598 else
1599 ath9k_disable_ps(sc);
8ab2cd09 1600 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3cbb5dd7
VN
1601 }
1602
199afd9d
S
1603 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1604 if (conf->flags & IEEE80211_CONF_MONITOR) {
d2182b69 1605 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
5f841b41
RM
1606 sc->sc_ah->is_monitoring = true;
1607 } else {
d2182b69 1608 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
5f841b41 1609 sc->sc_ah->is_monitoring = false;
199afd9d
S
1610 }
1611 }
1612
4797938c 1613 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 1614 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 1615 int pos = curchan->hw_value;
3430098a
FF
1616 int old_pos = -1;
1617 unsigned long flags;
1618
1619 if (ah->curchan)
1620 old_pos = ah->curchan - &ah->channels[0];
ae5eb026 1621
5ee08656
FF
1622 if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
1623 sc->sc_flags |= SC_OP_OFFCHANNEL;
1624 else
1625 sc->sc_flags &= ~SC_OP_OFFCHANNEL;
0e2dedf9 1626
d2182b69 1627 ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
8c79a610 1628 curchan->center_freq, conf->channel_type);
f078f209 1629
3430098a
FF
1630 /* update survey stats for the old channel before switching */
1631 spin_lock_irqsave(&common->cc_lock, flags);
1632 ath_update_survey_stats(sc);
1633 spin_unlock_irqrestore(&common->cc_lock, flags);
1634
e338a85e
RM
1635 /*
1636 * Preserve the current channel values, before updating
1637 * the same channel
1638 */
1a19f77f
RM
1639 if (ah->curchan && (old_pos == pos))
1640 ath9k_hw_getnf(ah, ah->curchan);
e338a85e
RM
1641
1642 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
1643 curchan, conf->channel_type);
1644
3430098a
FF
1645 /*
1646 * If the operating channel changes, change the survey in-use flags
1647 * along with it.
1648 * Reset the survey data for the new channel, unless we're switching
1649 * back to the operating channel from an off-channel operation.
1650 */
1651 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1652 sc->cur_survey != &sc->survey[pos]) {
1653
1654 if (sc->cur_survey)
1655 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1656
1657 sc->cur_survey = &sc->survey[pos];
1658
1659 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1660 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1661 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1662 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1663 }
1664
0e2dedf9 1665 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
3800276a 1666 ath_err(common, "Unable to set channel\n");
aa33de09 1667 mutex_unlock(&sc->mutex);
e11602b7
S
1668 return -EINVAL;
1669 }
3430098a
FF
1670
1671 /*
1672 * The most recent snapshot of channel->noisefloor for the old
1673 * channel is only available after the hardware reset. Copy it to
1674 * the survey stats now.
1675 */
1676 if (old_pos >= 0)
1677 ath_update_survey_nf(sc, old_pos);
094d05dc 1678 }
f078f209 1679
c9f6a656 1680 if (changed & IEEE80211_CONF_CHANGE_POWER) {
d2182b69 1681 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
17d7904d 1682 sc->config.txpowlimit = 2 * conf->power_level;
5048e8c3
RM
1683 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1684 sc->config.txpowlimit, &sc->curtxpow);
64839170
LR
1685 }
1686
aa33de09 1687 mutex_unlock(&sc->mutex);
c0c11741 1688 ath9k_ps_restore(sc);
141b38b6 1689
f078f209
LR
1690 return 0;
1691}
1692
8feceb67
VT
1693#define SUPPORTED_FILTERS \
1694 (FIF_PROMISC_IN_BSS | \
1695 FIF_ALLMULTI | \
1696 FIF_CONTROL | \
af6a3fc7 1697 FIF_PSPOLL | \
8feceb67
VT
1698 FIF_OTHER_BSS | \
1699 FIF_BCN_PRBRESP_PROMISC | \
9c1d8e4a 1700 FIF_PROBE_REQ | \
8feceb67 1701 FIF_FCSFAIL)
c83be688 1702
8feceb67
VT
1703/* FIXME: sc->sc_full_reset ? */
1704static void ath9k_configure_filter(struct ieee80211_hw *hw,
1705 unsigned int changed_flags,
1706 unsigned int *total_flags,
3ac64bee 1707 u64 multicast)
8feceb67 1708{
9ac58615 1709 struct ath_softc *sc = hw->priv;
8feceb67 1710 u32 rfilt;
f078f209 1711
8feceb67
VT
1712 changed_flags &= SUPPORTED_FILTERS;
1713 *total_flags &= SUPPORTED_FILTERS;
f078f209 1714
b77f483f 1715 sc->rx.rxfilter = *total_flags;
aa68aeaa 1716 ath9k_ps_wakeup(sc);
8feceb67
VT
1717 rfilt = ath_calcrxfilter(sc);
1718 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 1719 ath9k_ps_restore(sc);
f078f209 1720
d2182b69
JP
1721 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1722 rfilt);
8feceb67 1723}
f078f209 1724
4ca77860
JB
1725static int ath9k_sta_add(struct ieee80211_hw *hw,
1726 struct ieee80211_vif *vif,
1727 struct ieee80211_sta *sta)
8feceb67 1728{
9ac58615 1729 struct ath_softc *sc = hw->priv;
93ae2dd2
FF
1730 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1731 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1732 struct ieee80211_key_conf ps_key = { };
f078f209 1733
7e1e3864 1734 ath_node_attach(sc, sta, vif);
f59a59fe
FF
1735
1736 if (vif->type != NL80211_IFTYPE_AP &&
1737 vif->type != NL80211_IFTYPE_AP_VLAN)
1738 return 0;
1739
93ae2dd2 1740 an->ps_key = ath_key_config(common, vif, sta, &ps_key);
4ca77860
JB
1741
1742 return 0;
1743}
1744
93ae2dd2
FF
1745static void ath9k_del_ps_key(struct ath_softc *sc,
1746 struct ieee80211_vif *vif,
1747 struct ieee80211_sta *sta)
1748{
1749 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1750 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1751 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1752
1753 if (!an->ps_key)
1754 return;
1755
1756 ath_key_delete(common, &ps_key);
1757}
1758
4ca77860
JB
1759static int ath9k_sta_remove(struct ieee80211_hw *hw,
1760 struct ieee80211_vif *vif,
1761 struct ieee80211_sta *sta)
1762{
9ac58615 1763 struct ath_softc *sc = hw->priv;
4ca77860 1764
93ae2dd2 1765 ath9k_del_ps_key(sc, vif, sta);
4ca77860
JB
1766 ath_node_detach(sc, sta);
1767
1768 return 0;
f078f209
LR
1769}
1770
5519541d
FF
1771static void ath9k_sta_notify(struct ieee80211_hw *hw,
1772 struct ieee80211_vif *vif,
1773 enum sta_notify_cmd cmd,
1774 struct ieee80211_sta *sta)
1775{
1776 struct ath_softc *sc = hw->priv;
1777 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1778
3d4e20f2 1779 if (!sta->ht_cap.ht_supported)
b25bfda3
MSS
1780 return;
1781
5519541d
FF
1782 switch (cmd) {
1783 case STA_NOTIFY_SLEEP:
1784 an->sleeping = true;
042ec453 1785 ath_tx_aggr_sleep(sta, sc, an);
5519541d
FF
1786 break;
1787 case STA_NOTIFY_AWAKE:
1788 an->sleeping = false;
1789 ath_tx_aggr_wakeup(sc, an);
1790 break;
1791 }
1792}
1793
8a3a3c85
EP
1794static int ath9k_conf_tx(struct ieee80211_hw *hw,
1795 struct ieee80211_vif *vif, u16 queue,
8feceb67 1796 const struct ieee80211_tx_queue_params *params)
f078f209 1797{
9ac58615 1798 struct ath_softc *sc = hw->priv;
c46917bb 1799 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
066dae93 1800 struct ath_txq *txq;
8feceb67 1801 struct ath9k_tx_queue_info qi;
066dae93 1802 int ret = 0;
f078f209 1803
8feceb67
VT
1804 if (queue >= WME_NUM_AC)
1805 return 0;
f078f209 1806
066dae93
FF
1807 txq = sc->tx.txq_map[queue];
1808
96f372c9 1809 ath9k_ps_wakeup(sc);
141b38b6
S
1810 mutex_lock(&sc->mutex);
1811
1ffb0610
S
1812 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1813
8feceb67
VT
1814 qi.tqi_aifs = params->aifs;
1815 qi.tqi_cwmin = params->cw_min;
1816 qi.tqi_cwmax = params->cw_max;
1817 qi.tqi_burstTime = params->txop;
f078f209 1818
d2182b69 1819 ath_dbg(common, CONFIG,
226afe68
JP
1820 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1821 queue, txq->axq_qnum, params->aifs, params->cw_min,
1822 params->cw_max, params->txop);
f078f209 1823
066dae93 1824 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
8feceb67 1825 if (ret)
3800276a 1826 ath_err(common, "TXQ Update failed\n");
f078f209 1827
94db2936 1828 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
066dae93 1829 if (queue == WME_AC_BE && !ret)
94db2936
VN
1830 ath_beaconq_config(sc);
1831
141b38b6 1832 mutex_unlock(&sc->mutex);
96f372c9 1833 ath9k_ps_restore(sc);
141b38b6 1834
8feceb67
VT
1835 return ret;
1836}
f078f209 1837
8feceb67
VT
1838static int ath9k_set_key(struct ieee80211_hw *hw,
1839 enum set_key_cmd cmd,
dc822b5d
JB
1840 struct ieee80211_vif *vif,
1841 struct ieee80211_sta *sta,
8feceb67
VT
1842 struct ieee80211_key_conf *key)
1843{
9ac58615 1844 struct ath_softc *sc = hw->priv;
c46917bb 1845 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67 1846 int ret = 0;
f078f209 1847
3e6109c5 1848 if (ath9k_modparam_nohwcrypt)
b3bd89ce
JM
1849 return -ENOSPC;
1850
5bd5e9a6
CYY
1851 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1852 vif->type == NL80211_IFTYPE_MESH_POINT) &&
cfdc9a8b
JM
1853 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1854 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1855 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1856 /*
1857 * For now, disable hw crypto for the RSN IBSS group keys. This
1858 * could be optimized in the future to use a modified key cache
1859 * design to support per-STA RX GTK, but until that gets
1860 * implemented, use of software crypto for group addressed
1861 * frames is a acceptable to allow RSN IBSS to be used.
1862 */
1863 return -EOPNOTSUPP;
1864 }
1865
141b38b6 1866 mutex_lock(&sc->mutex);
3cbb5dd7 1867 ath9k_ps_wakeup(sc);
d2182b69 1868 ath_dbg(common, CONFIG, "Set HW Key\n");
f078f209 1869
8feceb67
VT
1870 switch (cmd) {
1871 case SET_KEY:
93ae2dd2
FF
1872 if (sta)
1873 ath9k_del_ps_key(sc, vif, sta);
1874
040e539e 1875 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM
1876 if (ret >= 0) {
1877 key->hw_key_idx = ret;
8feceb67
VT
1878 /* push IV and Michael MIC generation to stack */
1879 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
97359d12 1880 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
8feceb67 1881 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
97359d12
JB
1882 if (sc->sc_ah->sw_mgmt_crypto &&
1883 key->cipher == WLAN_CIPHER_SUITE_CCMP)
0ced0e17 1884 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 1885 ret = 0;
8feceb67
VT
1886 }
1887 break;
1888 case DISABLE_KEY:
040e539e 1889 ath_key_delete(common, key);
8feceb67
VT
1890 break;
1891 default:
1892 ret = -EINVAL;
1893 }
f078f209 1894
3cbb5dd7 1895 ath9k_ps_restore(sc);
141b38b6
S
1896 mutex_unlock(&sc->mutex);
1897
8feceb67
VT
1898 return ret;
1899}
4f5ef75b
RM
1900static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1901{
1902 struct ath_softc *sc = data;
1903 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1904 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1905 struct ath_vif *avp = (void *)vif->drv_priv;
1906
2e5ef459
RM
1907 /*
1908 * Skip iteration if primary station vif's bss info
1909 * was not changed
1910 */
1911 if (sc->sc_flags & SC_OP_PRIM_STA_VIF)
1912 return;
1913
1914 if (bss_conf->assoc) {
1915 sc->sc_flags |= SC_OP_PRIM_STA_VIF;
1916 avp->primary_sta_vif = true;
4f5ef75b
RM
1917 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1918 common->curaid = bss_conf->aid;
1919 ath9k_hw_write_associd(sc->sc_ah);
d2182b69
JP
1920 ath_dbg(common, CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
1921 bss_conf->aid, common->curbssid);
2e5ef459
RM
1922 ath_beacon_config(sc, vif);
1923 /*
1924 * Request a re-configuration of Beacon related timers
1925 * on the receipt of the first Beacon frame (i.e.,
1926 * after time sync with the AP).
1927 */
1928 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1929 /* Reset rssi stats */
1930 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
1931 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
99e4d43a 1932
01e18918
RM
1933 ath_start_rx_poll(sc, 3);
1934
05c0be2f
MSS
1935 if (!common->disable_ani) {
1936 sc->sc_flags |= SC_OP_ANI_RUN;
1937 ath_start_ani(common);
1938 }
1939
4f5ef75b
RM
1940 }
1941}
1942
1943static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
1944{
1945 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1946 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1947 struct ath_vif *avp = (void *)vif->drv_priv;
1948
2e5ef459
RM
1949 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
1950 return;
1951
4f5ef75b
RM
1952 /* Reconfigure bss info */
1953 if (avp->primary_sta_vif && !bss_conf->assoc) {
d2182b69 1954 ath_dbg(common, CONFIG, "Bss Info DISASSOC %d, bssid %pM\n",
99e4d43a
RM
1955 common->curaid, common->curbssid);
1956 sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS);
4f5ef75b
RM
1957 avp->primary_sta_vif = false;
1958 memset(common->curbssid, 0, ETH_ALEN);
1959 common->curaid = 0;
1960 }
1961
1962 ieee80211_iterate_active_interfaces_atomic(
1963 sc->hw, ath9k_bss_iter, sc);
1964
1965 /*
1966 * None of station vifs are associated.
1967 * Clear bssid & aid
1968 */
2e5ef459 1969 if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF)) {
4f5ef75b 1970 ath9k_hw_write_associd(sc->sc_ah);
99e4d43a
RM
1971 /* Stop ANI */
1972 sc->sc_flags &= ~SC_OP_ANI_RUN;
1973 del_timer_sync(&common->ani.timer);
01e18918 1974 del_timer_sync(&sc->rx_poll_timer);
d2c71c20 1975 memset(&sc->caldata, 0, sizeof(sc->caldata));
99e4d43a 1976 }
4f5ef75b 1977}
f078f209 1978
8feceb67
VT
1979static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1980 struct ieee80211_vif *vif,
1981 struct ieee80211_bss_conf *bss_conf,
1982 u32 changed)
1983{
9ac58615 1984 struct ath_softc *sc = hw->priv;
2d0ddec5 1985 struct ath_hw *ah = sc->sc_ah;
1510718d 1986 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 1987 struct ath_vif *avp = (void *)vif->drv_priv;
0005baf4 1988 int slottime;
c6089ccc 1989 int error;
f078f209 1990
96f372c9 1991 ath9k_ps_wakeup(sc);
141b38b6
S
1992 mutex_lock(&sc->mutex);
1993
9f61903c 1994 if (changed & BSS_CHANGED_ASSOC) {
4f5ef75b 1995 ath9k_config_bss(sc, vif);
2d0ddec5 1996
d2182b69 1997 ath_dbg(common, CONFIG, "BSSID: %pM aid: 0x%x\n",
226afe68 1998 common->curbssid, common->curaid);
c6089ccc 1999 }
2d0ddec5 2000
2e5ef459
RM
2001 if (changed & BSS_CHANGED_IBSS) {
2002 /* There can be only one vif available */
2003 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2004 common->curaid = bss_conf->aid;
2005 ath9k_hw_write_associd(sc->sc_ah);
2006
2007 if (bss_conf->ibss_joined) {
2008 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
05c0be2f
MSS
2009
2010 if (!common->disable_ani) {
2011 sc->sc_flags |= SC_OP_ANI_RUN;
2012 ath_start_ani(common);
2013 }
2014
2e5ef459
RM
2015 } else {
2016 sc->sc_flags &= ~SC_OP_ANI_RUN;
2017 del_timer_sync(&common->ani.timer);
01e18918 2018 del_timer_sync(&sc->rx_poll_timer);
2e5ef459
RM
2019 }
2020 }
2021
c6089ccc
S
2022 /* Enable transmission of beacons (AP, IBSS, MESH) */
2023 if ((changed & BSS_CHANGED_BEACON) ||
2024 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
014cf3bb 2025 ath9k_set_beaconing_status(sc, false);
9ac58615 2026 error = ath_beacon_alloc(sc, vif);
c6089ccc
S
2027 if (!error)
2028 ath_beacon_config(sc, vif);
014cf3bb 2029 ath9k_set_beaconing_status(sc, true);
0005baf4
FF
2030 }
2031
2032 if (changed & BSS_CHANGED_ERP_SLOT) {
2033 if (bss_conf->use_short_slot)
2034 slottime = 9;
2035 else
2036 slottime = 20;
2037 if (vif->type == NL80211_IFTYPE_AP) {
2038 /*
2039 * Defer update, so that connected stations can adjust
2040 * their settings at the same time.
2041 * See beacon.c for more details
2042 */
2043 sc->beacon.slottime = slottime;
2044 sc->beacon.updateslot = UPDATE;
2045 } else {
2046 ah->slottime = slottime;
2047 ath9k_hw_init_global_settings(ah);
2048 }
2d0ddec5
JB
2049 }
2050
c6089ccc 2051 /* Disable transmission of beacons */
014cf3bb
RM
2052 if ((changed & BSS_CHANGED_BEACON_ENABLED) &&
2053 !bss_conf->enable_beacon) {
2054 ath9k_set_beaconing_status(sc, false);
2055 avp->is_bslot_active = false;
2056 ath9k_set_beaconing_status(sc, true);
2057 }
2d0ddec5 2058
c6089ccc 2059 if (changed & BSS_CHANGED_BEACON_INT) {
c6089ccc
S
2060 /*
2061 * In case of AP mode, the HW TSF has to be reset
2062 * when the beacon interval changes.
2063 */
2064 if (vif->type == NL80211_IFTYPE_AP) {
2065 sc->sc_flags |= SC_OP_TSF_RESET;
014cf3bb 2066 ath9k_set_beaconing_status(sc, false);
9ac58615 2067 error = ath_beacon_alloc(sc, vif);
2d0ddec5
JB
2068 if (!error)
2069 ath_beacon_config(sc, vif);
014cf3bb 2070 ath9k_set_beaconing_status(sc, true);
99e4d43a 2071 } else
c6089ccc 2072 ath_beacon_config(sc, vif);
2d0ddec5
JB
2073 }
2074
141b38b6 2075 mutex_unlock(&sc->mutex);
96f372c9 2076 ath9k_ps_restore(sc);
8feceb67 2077}
f078f209 2078
37a41b4a 2079static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
8feceb67 2080{
9ac58615 2081 struct ath_softc *sc = hw->priv;
8feceb67 2082 u64 tsf;
f078f209 2083
141b38b6 2084 mutex_lock(&sc->mutex);
9abbfb27 2085 ath9k_ps_wakeup(sc);
141b38b6 2086 tsf = ath9k_hw_gettsf64(sc->sc_ah);
9abbfb27 2087 ath9k_ps_restore(sc);
141b38b6 2088 mutex_unlock(&sc->mutex);
f078f209 2089
8feceb67
VT
2090 return tsf;
2091}
f078f209 2092
37a41b4a
EP
2093static void ath9k_set_tsf(struct ieee80211_hw *hw,
2094 struct ieee80211_vif *vif,
2095 u64 tsf)
3b5d665b 2096{
9ac58615 2097 struct ath_softc *sc = hw->priv;
3b5d665b 2098
141b38b6 2099 mutex_lock(&sc->mutex);
9abbfb27 2100 ath9k_ps_wakeup(sc);
141b38b6 2101 ath9k_hw_settsf64(sc->sc_ah, tsf);
9abbfb27 2102 ath9k_ps_restore(sc);
141b38b6 2103 mutex_unlock(&sc->mutex);
3b5d665b
AF
2104}
2105
37a41b4a 2106static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
8feceb67 2107{
9ac58615 2108 struct ath_softc *sc = hw->priv;
c83be688 2109
141b38b6 2110 mutex_lock(&sc->mutex);
21526d57
LR
2111
2112 ath9k_ps_wakeup(sc);
141b38b6 2113 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR
2114 ath9k_ps_restore(sc);
2115
141b38b6 2116 mutex_unlock(&sc->mutex);
8feceb67 2117}
f078f209 2118
8feceb67 2119static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 2120 struct ieee80211_vif *vif,
141b38b6
S
2121 enum ieee80211_ampdu_mlme_action action,
2122 struct ieee80211_sta *sta,
0b01f030 2123 u16 tid, u16 *ssn, u8 buf_size)
8feceb67 2124{
9ac58615 2125 struct ath_softc *sc = hw->priv;
8feceb67 2126 int ret = 0;
f078f209 2127
85ad181e
JB
2128 local_bh_disable();
2129
8feceb67
VT
2130 switch (action) {
2131 case IEEE80211_AMPDU_RX_START:
8feceb67
VT
2132 break;
2133 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT
2134 break;
2135 case IEEE80211_AMPDU_TX_START:
8b685ba9 2136 ath9k_ps_wakeup(sc);
231c3a1f
FF
2137 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2138 if (!ret)
2139 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2140 ath9k_ps_restore(sc);
8feceb67
VT
2141 break;
2142 case IEEE80211_AMPDU_TX_STOP:
8b685ba9 2143 ath9k_ps_wakeup(sc);
f83da965 2144 ath_tx_aggr_stop(sc, sta, tid);
c951ad35 2145 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2146 ath9k_ps_restore(sc);
8feceb67 2147 break;
b1720231 2148 case IEEE80211_AMPDU_TX_OPERATIONAL:
8b685ba9 2149 ath9k_ps_wakeup(sc);
8469cdef 2150 ath_tx_aggr_resume(sc, sta, tid);
8b685ba9 2151 ath9k_ps_restore(sc);
8469cdef 2152 break;
8feceb67 2153 default:
3800276a 2154 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
8feceb67
VT
2155 }
2156
85ad181e
JB
2157 local_bh_enable();
2158
8feceb67 2159 return ret;
f078f209
LR
2160}
2161
62dad5b0
BP
2162static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2163 struct survey_info *survey)
2164{
9ac58615 2165 struct ath_softc *sc = hw->priv;
3430098a 2166 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39162dbe 2167 struct ieee80211_supported_band *sband;
3430098a
FF
2168 struct ieee80211_channel *chan;
2169 unsigned long flags;
2170 int pos;
2171
2172 spin_lock_irqsave(&common->cc_lock, flags);
2173 if (idx == 0)
2174 ath_update_survey_stats(sc);
39162dbe
FF
2175
2176 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2177 if (sband && idx >= sband->n_channels) {
2178 idx -= sband->n_channels;
2179 sband = NULL;
2180 }
62dad5b0 2181
39162dbe
FF
2182 if (!sband)
2183 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
62dad5b0 2184
3430098a
FF
2185 if (!sband || idx >= sband->n_channels) {
2186 spin_unlock_irqrestore(&common->cc_lock, flags);
2187 return -ENOENT;
4f1a5a4b 2188 }
62dad5b0 2189
3430098a
FF
2190 chan = &sband->channels[idx];
2191 pos = chan->hw_value;
2192 memcpy(survey, &sc->survey[pos], sizeof(*survey));
2193 survey->channel = chan;
2194 spin_unlock_irqrestore(&common->cc_lock, flags);
2195
62dad5b0
BP
2196 return 0;
2197}
2198
e239d859
FF
2199static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
2200{
9ac58615 2201 struct ath_softc *sc = hw->priv;
e239d859
FF
2202 struct ath_hw *ah = sc->sc_ah;
2203
2204 mutex_lock(&sc->mutex);
2205 ah->coverage_class = coverage_class;
8b2a3827
MSS
2206
2207 ath9k_ps_wakeup(sc);
e239d859 2208 ath9k_hw_init_global_settings(ah);
8b2a3827
MSS
2209 ath9k_ps_restore(sc);
2210
e239d859
FF
2211 mutex_unlock(&sc->mutex);
2212}
2213
69081624
VT
2214static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
2215{
69081624 2216 struct ath_softc *sc = hw->priv;
99aa55b6
MSS
2217 struct ath_hw *ah = sc->sc_ah;
2218 struct ath_common *common = ath9k_hw_common(ah);
86271e46
FF
2219 int timeout = 200; /* ms */
2220 int i, j;
2f6fc351 2221 bool drain_txq;
69081624
VT
2222
2223 mutex_lock(&sc->mutex);
69081624
VT
2224 cancel_delayed_work_sync(&sc->tx_complete_work);
2225
6a6b3f3e 2226 if (ah->ah_flags & AH_UNPLUGGED) {
d2182b69 2227 ath_dbg(common, ANY, "Device has been unplugged!\n");
6a6b3f3e
MSS
2228 mutex_unlock(&sc->mutex);
2229 return;
2230 }
2231
99aa55b6 2232 if (sc->sc_flags & SC_OP_INVALID) {
d2182b69 2233 ath_dbg(common, ANY, "Device not present\n");
99aa55b6
MSS
2234 mutex_unlock(&sc->mutex);
2235 return;
2236 }
2237
86271e46 2238 for (j = 0; j < timeout; j++) {
108697c4 2239 bool npend = false;
86271e46
FF
2240
2241 if (j)
2242 usleep_range(1000, 2000);
69081624 2243
86271e46
FF
2244 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2245 if (!ATH_TXQ_SETUP(sc, i))
2246 continue;
2247
108697c4
MSS
2248 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
2249
2250 if (npend)
2251 break;
69081624 2252 }
86271e46
FF
2253
2254 if (!npend)
9df0d6a2 2255 break;
69081624
VT
2256 }
2257
9df0d6a2
FF
2258 if (drop) {
2259 ath9k_ps_wakeup(sc);
2260 spin_lock_bh(&sc->sc_pcu_lock);
2261 drain_txq = ath_drain_all_txq(sc, false);
2262 spin_unlock_bh(&sc->sc_pcu_lock);
9adcf440 2263
9df0d6a2
FF
2264 if (!drain_txq)
2265 ath_reset(sc, false);
9adcf440 2266
9df0d6a2
FF
2267 ath9k_ps_restore(sc);
2268 ieee80211_wake_queues(hw);
2269 }
d78f4b3e 2270
69081624
VT
2271 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
2272 mutex_unlock(&sc->mutex);
2273}
2274
15b91e83
VN
2275static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2276{
2277 struct ath_softc *sc = hw->priv;
2278 int i;
2279
2280 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2281 if (!ATH_TXQ_SETUP(sc, i))
2282 continue;
2283
2284 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
2285 return true;
2286 }
2287 return false;
2288}
2289
5595f119 2290static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
ba4903f9
FF
2291{
2292 struct ath_softc *sc = hw->priv;
2293 struct ath_hw *ah = sc->sc_ah;
2294 struct ieee80211_vif *vif;
2295 struct ath_vif *avp;
2296 struct ath_buf *bf;
2297 struct ath_tx_status ts;
4286df60 2298 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
ba4903f9
FF
2299 int status;
2300
2301 vif = sc->beacon.bslot[0];
2302 if (!vif)
2303 return 0;
2304
2305 avp = (void *)vif->drv_priv;
2306 if (!avp->is_bslot_active)
2307 return 0;
2308
4286df60 2309 if (!sc->beacon.tx_processed && !edma) {
ba4903f9
FF
2310 tasklet_disable(&sc->bcon_tasklet);
2311
2312 bf = avp->av_bcbuf;
2313 if (!bf || !bf->bf_mpdu)
2314 goto skip;
2315
2316 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2317 if (status == -EINPROGRESS)
2318 goto skip;
2319
2320 sc->beacon.tx_processed = true;
2321 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2322
2323skip:
2324 tasklet_enable(&sc->bcon_tasklet);
2325 }
2326
2327 return sc->beacon.tx_last;
2328}
2329
52c94f41
MSS
2330static int ath9k_get_stats(struct ieee80211_hw *hw,
2331 struct ieee80211_low_level_stats *stats)
2332{
2333 struct ath_softc *sc = hw->priv;
2334 struct ath_hw *ah = sc->sc_ah;
2335 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2336
2337 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2338 stats->dot11RTSFailureCount = mib_stats->rts_bad;
2339 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2340 stats->dot11RTSSuccessCount = mib_stats->rts_good;
2341 return 0;
2342}
2343
43c35284
FF
2344static u32 fill_chainmask(u32 cap, u32 new)
2345{
2346 u32 filled = 0;
2347 int i;
2348
2349 for (i = 0; cap && new; i++, cap >>= 1) {
2350 if (!(cap & BIT(0)))
2351 continue;
2352
2353 if (new & BIT(0))
2354 filled |= BIT(i);
2355
2356 new >>= 1;
2357 }
2358
2359 return filled;
2360}
2361
2362static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2363{
2364 struct ath_softc *sc = hw->priv;
2365 struct ath_hw *ah = sc->sc_ah;
2366
2367 if (!rx_ant || !tx_ant)
2368 return -EINVAL;
2369
2370 sc->ant_rx = rx_ant;
2371 sc->ant_tx = tx_ant;
2372
2373 if (ah->caps.rx_chainmask == 1)
2374 return 0;
2375
2376 /* AR9100 runs into calibration issues if not all rx chains are enabled */
2377 if (AR_SREV_9100(ah))
2378 ah->rxchainmask = 0x7;
2379 else
2380 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2381
2382 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
2383 ath9k_reload_chainmask_settings(sc);
2384
2385 return 0;
2386}
2387
2388static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2389{
2390 struct ath_softc *sc = hw->priv;
2391
2392 *tx_ant = sc->ant_tx;
2393 *rx_ant = sc->ant_rx;
2394 return 0;
2395}
2396
6baff7f9 2397struct ieee80211_ops ath9k_ops = {
8feceb67
VT
2398 .tx = ath9k_tx,
2399 .start = ath9k_start,
2400 .stop = ath9k_stop,
2401 .add_interface = ath9k_add_interface,
6b3b991d 2402 .change_interface = ath9k_change_interface,
8feceb67
VT
2403 .remove_interface = ath9k_remove_interface,
2404 .config = ath9k_config,
8feceb67 2405 .configure_filter = ath9k_configure_filter,
4ca77860
JB
2406 .sta_add = ath9k_sta_add,
2407 .sta_remove = ath9k_sta_remove,
5519541d 2408 .sta_notify = ath9k_sta_notify,
8feceb67 2409 .conf_tx = ath9k_conf_tx,
8feceb67 2410 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2411 .set_key = ath9k_set_key,
8feceb67 2412 .get_tsf = ath9k_get_tsf,
3b5d665b 2413 .set_tsf = ath9k_set_tsf,
8feceb67 2414 .reset_tsf = ath9k_reset_tsf,
4233df6b 2415 .ampdu_action = ath9k_ampdu_action,
62dad5b0 2416 .get_survey = ath9k_get_survey,
3b319aae 2417 .rfkill_poll = ath9k_rfkill_poll_state,
e239d859 2418 .set_coverage_class = ath9k_set_coverage_class,
69081624 2419 .flush = ath9k_flush,
15b91e83 2420 .tx_frames_pending = ath9k_tx_frames_pending,
52c94f41
MSS
2421 .tx_last_beacon = ath9k_tx_last_beacon,
2422 .get_stats = ath9k_get_stats,
43c35284
FF
2423 .set_antenna = ath9k_set_antenna,
2424 .get_antenna = ath9k_get_antenna,
8feceb67 2425};
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