Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 | 17 | #include <linux/nl80211.h> |
69081624 | 18 | #include <linux/delay.h> |
394cf0a1 | 19 | #include "ath9k.h" |
af03abec | 20 | #include "btcoex.h" |
f078f209 | 21 | |
ff37e337 S |
22 | static u8 parse_mpdudensity(u8 mpdudensity) |
23 | { | |
24 | /* | |
25 | * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": | |
26 | * 0 for no restriction | |
27 | * 1 for 1/4 us | |
28 | * 2 for 1/2 us | |
29 | * 3 for 1 us | |
30 | * 4 for 2 us | |
31 | * 5 for 4 us | |
32 | * 6 for 8 us | |
33 | * 7 for 16 us | |
34 | */ | |
35 | switch (mpdudensity) { | |
36 | case 0: | |
37 | return 0; | |
38 | case 1: | |
39 | case 2: | |
40 | case 3: | |
41 | /* Our lower layer calculations limit our precision to | |
42 | 1 microsecond */ | |
43 | return 1; | |
44 | case 4: | |
45 | return 2; | |
46 | case 5: | |
47 | return 4; | |
48 | case 6: | |
49 | return 8; | |
50 | case 7: | |
51 | return 16; | |
52 | default: | |
53 | return 0; | |
54 | } | |
55 | } | |
56 | ||
69081624 VT |
57 | static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq) |
58 | { | |
59 | bool pending = false; | |
60 | ||
61 | spin_lock_bh(&txq->axq_lock); | |
62 | ||
63 | if (txq->axq_depth || !list_empty(&txq->axq_acq)) | |
64 | pending = true; | |
65 | else if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
66 | pending = !list_empty(&txq->txq_fifo_pending); | |
67 | ||
68 | spin_unlock_bh(&txq->axq_lock); | |
69 | return pending; | |
70 | } | |
71 | ||
55624204 | 72 | bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) |
8c77a569 LR |
73 | { |
74 | unsigned long flags; | |
75 | bool ret; | |
76 | ||
9ecdef4b LR |
77 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
78 | ret = ath9k_hw_setpower(sc->sc_ah, mode); | |
79 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
8c77a569 LR |
80 | |
81 | return ret; | |
82 | } | |
83 | ||
a91d75ae LR |
84 | void ath9k_ps_wakeup(struct ath_softc *sc) |
85 | { | |
898c914a | 86 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
a91d75ae | 87 | unsigned long flags; |
fbb078fc | 88 | enum ath9k_power_mode power_mode; |
a91d75ae LR |
89 | |
90 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
91 | if (++sc->ps_usecount != 1) | |
92 | goto unlock; | |
93 | ||
fbb078fc | 94 | power_mode = sc->sc_ah->power_mode; |
9ecdef4b | 95 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); |
a91d75ae | 96 | |
898c914a FF |
97 | /* |
98 | * While the hardware is asleep, the cycle counters contain no | |
99 | * useful data. Better clear them now so that they don't mess up | |
100 | * survey data results. | |
101 | */ | |
fbb078fc FF |
102 | if (power_mode != ATH9K_PM_AWAKE) { |
103 | spin_lock(&common->cc_lock); | |
104 | ath_hw_cycle_counters_update(common); | |
105 | memset(&common->cc_survey, 0, sizeof(common->cc_survey)); | |
106 | spin_unlock(&common->cc_lock); | |
107 | } | |
898c914a | 108 | |
a91d75ae LR |
109 | unlock: |
110 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
111 | } | |
112 | ||
113 | void ath9k_ps_restore(struct ath_softc *sc) | |
114 | { | |
898c914a | 115 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
a91d75ae LR |
116 | unsigned long flags; |
117 | ||
118 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
119 | if (--sc->ps_usecount != 0) | |
120 | goto unlock; | |
121 | ||
898c914a FF |
122 | spin_lock(&common->cc_lock); |
123 | ath_hw_cycle_counters_update(common); | |
124 | spin_unlock(&common->cc_lock); | |
125 | ||
1dbfd9d4 VN |
126 | if (sc->ps_idle) |
127 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); | |
128 | else if (sc->ps_enabled && | |
129 | !(sc->ps_flags & (PS_WAIT_FOR_BEACON | | |
1b04b930 S |
130 | PS_WAIT_FOR_CAB | |
131 | PS_WAIT_FOR_PSPOLL_DATA | | |
132 | PS_WAIT_FOR_TX_ACK))) | |
9ecdef4b | 133 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP); |
a91d75ae LR |
134 | |
135 | unlock: | |
136 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
137 | } | |
138 | ||
5ee08656 FF |
139 | static void ath_start_ani(struct ath_common *common) |
140 | { | |
141 | struct ath_hw *ah = common->ah; | |
142 | unsigned long timestamp = jiffies_to_msecs(jiffies); | |
143 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
144 | ||
145 | if (!(sc->sc_flags & SC_OP_ANI_RUN)) | |
146 | return; | |
147 | ||
148 | if (sc->sc_flags & SC_OP_OFFCHANNEL) | |
149 | return; | |
150 | ||
151 | common->ani.longcal_timer = timestamp; | |
152 | common->ani.shortcal_timer = timestamp; | |
153 | common->ani.checkani_timer = timestamp; | |
154 | ||
155 | mod_timer(&common->ani.timer, | |
156 | jiffies + | |
157 | msecs_to_jiffies((u32)ah->config.ani_poll_interval)); | |
158 | } | |
159 | ||
3430098a FF |
160 | static void ath_update_survey_nf(struct ath_softc *sc, int channel) |
161 | { | |
162 | struct ath_hw *ah = sc->sc_ah; | |
163 | struct ath9k_channel *chan = &ah->channels[channel]; | |
164 | struct survey_info *survey = &sc->survey[channel]; | |
165 | ||
166 | if (chan->noisefloor) { | |
167 | survey->filled |= SURVEY_INFO_NOISE_DBM; | |
168 | survey->noise = chan->noisefloor; | |
169 | } | |
170 | } | |
171 | ||
cb8d61de FF |
172 | /* |
173 | * Updates the survey statistics and returns the busy time since last | |
174 | * update in %, if the measurement duration was long enough for the | |
175 | * result to be useful, -1 otherwise. | |
176 | */ | |
177 | static int ath_update_survey_stats(struct ath_softc *sc) | |
3430098a FF |
178 | { |
179 | struct ath_hw *ah = sc->sc_ah; | |
180 | struct ath_common *common = ath9k_hw_common(ah); | |
181 | int pos = ah->curchan - &ah->channels[0]; | |
182 | struct survey_info *survey = &sc->survey[pos]; | |
183 | struct ath_cycle_counters *cc = &common->cc_survey; | |
184 | unsigned int div = common->clockrate * 1000; | |
cb8d61de | 185 | int ret = 0; |
3430098a | 186 | |
0845735e | 187 | if (!ah->curchan) |
cb8d61de | 188 | return -1; |
0845735e | 189 | |
898c914a FF |
190 | if (ah->power_mode == ATH9K_PM_AWAKE) |
191 | ath_hw_cycle_counters_update(common); | |
3430098a FF |
192 | |
193 | if (cc->cycles > 0) { | |
194 | survey->filled |= SURVEY_INFO_CHANNEL_TIME | | |
195 | SURVEY_INFO_CHANNEL_TIME_BUSY | | |
196 | SURVEY_INFO_CHANNEL_TIME_RX | | |
197 | SURVEY_INFO_CHANNEL_TIME_TX; | |
198 | survey->channel_time += cc->cycles / div; | |
199 | survey->channel_time_busy += cc->rx_busy / div; | |
200 | survey->channel_time_rx += cc->rx_frame / div; | |
201 | survey->channel_time_tx += cc->tx_frame / div; | |
202 | } | |
cb8d61de FF |
203 | |
204 | if (cc->cycles < div) | |
205 | return -1; | |
206 | ||
207 | if (cc->cycles > 0) | |
208 | ret = cc->rx_busy * 100 / cc->cycles; | |
209 | ||
3430098a FF |
210 | memset(cc, 0, sizeof(*cc)); |
211 | ||
212 | ath_update_survey_nf(sc, pos); | |
cb8d61de FF |
213 | |
214 | return ret; | |
3430098a FF |
215 | } |
216 | ||
ff37e337 S |
217 | /* |
218 | * Set/change channels. If the channel is really being changed, it's done | |
219 | * by reseting the chip. To accomplish this we must first cleanup any pending | |
220 | * DMA, then restart stuff. | |
221 | */ | |
0e2dedf9 JM |
222 | int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, |
223 | struct ath9k_channel *hchan) | |
ff37e337 | 224 | { |
cbe61d8a | 225 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 226 | struct ath_common *common = ath9k_hw_common(ah); |
25c56eec | 227 | struct ieee80211_conf *conf = &common->hw->conf; |
ff37e337 | 228 | bool fastcc = true, stopped; |
ae8d2858 | 229 | struct ieee80211_channel *channel = hw->conf.channel; |
20bd2a09 | 230 | struct ath9k_hw_cal_data *caldata = NULL; |
ae8d2858 | 231 | int r; |
ff37e337 S |
232 | |
233 | if (sc->sc_flags & SC_OP_INVALID) | |
234 | return -EIO; | |
235 | ||
cb8d61de FF |
236 | sc->hw_busy_count = 0; |
237 | ||
5ee08656 FF |
238 | del_timer_sync(&common->ani.timer); |
239 | cancel_work_sync(&sc->paprd_work); | |
240 | cancel_work_sync(&sc->hw_check_work); | |
241 | cancel_delayed_work_sync(&sc->tx_complete_work); | |
181fb18d | 242 | cancel_delayed_work_sync(&sc->hw_pll_work); |
5ee08656 | 243 | |
3cbb5dd7 VN |
244 | ath9k_ps_wakeup(sc); |
245 | ||
6a6733f2 LR |
246 | spin_lock_bh(&sc->sc_pcu_lock); |
247 | ||
c0d7c7af LR |
248 | /* |
249 | * This is only performed if the channel settings have | |
250 | * actually changed. | |
251 | * | |
252 | * To switch channels clear any pending DMA operations; | |
253 | * wait long enough for the RX fifo to drain, reset the | |
254 | * hardware at the new frequency, and then re-enable | |
255 | * the relevant bits of the h/w. | |
256 | */ | |
4df3071e | 257 | ath9k_hw_disable_interrupts(ah); |
080e1a25 | 258 | stopped = ath_drain_all_txq(sc, false); |
5e848f78 | 259 | |
080e1a25 FF |
260 | if (!ath_stoprecv(sc)) |
261 | stopped = false; | |
ff37e337 | 262 | |
8b3f4616 FF |
263 | if (!ath9k_hw_check_alive(ah)) |
264 | stopped = false; | |
265 | ||
c0d7c7af LR |
266 | /* XXX: do not flush receive queue here. We don't want |
267 | * to flush data frames already in queue because of | |
268 | * changing channel. */ | |
ff37e337 | 269 | |
5ee08656 | 270 | if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL)) |
c0d7c7af LR |
271 | fastcc = false; |
272 | ||
20bd2a09 | 273 | if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) |
9ac58615 | 274 | caldata = &sc->caldata; |
20bd2a09 | 275 | |
226afe68 JP |
276 | ath_dbg(common, ATH_DBG_CONFIG, |
277 | "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n", | |
278 | sc->sc_ah->curchan->channel, | |
279 | channel->center_freq, conf_is_ht40(conf), | |
280 | fastcc); | |
ff37e337 | 281 | |
20bd2a09 | 282 | r = ath9k_hw_reset(ah, hchan, caldata, fastcc); |
c0d7c7af | 283 | if (r) { |
3800276a JP |
284 | ath_err(common, |
285 | "Unable to reset channel (%u MHz), reset status %d\n", | |
286 | channel->center_freq, r); | |
3989279c | 287 | goto ps_restore; |
ff37e337 | 288 | } |
c0d7c7af | 289 | |
c0d7c7af | 290 | if (ath_startrecv(sc) != 0) { |
3800276a | 291 | ath_err(common, "Unable to restart recv logic\n"); |
3989279c GJ |
292 | r = -EIO; |
293 | goto ps_restore; | |
c0d7c7af LR |
294 | } |
295 | ||
5048e8c3 RM |
296 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
297 | sc->config.txpowlimit, &sc->curtxpow); | |
3069168c | 298 | ath9k_hw_set_interrupts(ah, ah->imask); |
3989279c | 299 | |
48a6a468 | 300 | if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) { |
1186488b | 301 | if (sc->sc_flags & SC_OP_BEACONS) |
99e4d43a | 302 | ath_set_beacon(sc); |
5ee08656 | 303 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
181fb18d | 304 | ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2); |
48a6a468 | 305 | ath_start_ani(common); |
5ee08656 FF |
306 | } |
307 | ||
3989279c | 308 | ps_restore: |
92460412 FF |
309 | ieee80211_wake_queues(hw); |
310 | ||
6a6733f2 LR |
311 | spin_unlock_bh(&sc->sc_pcu_lock); |
312 | ||
3cbb5dd7 | 313 | ath9k_ps_restore(sc); |
3989279c | 314 | return r; |
ff37e337 S |
315 | } |
316 | ||
9f42c2b6 FF |
317 | static void ath_paprd_activate(struct ath_softc *sc) |
318 | { | |
319 | struct ath_hw *ah = sc->sc_ah; | |
20bd2a09 | 320 | struct ath9k_hw_cal_data *caldata = ah->caldata; |
9094537c | 321 | struct ath_common *common = ath9k_hw_common(ah); |
9f42c2b6 FF |
322 | int chain; |
323 | ||
20bd2a09 | 324 | if (!caldata || !caldata->paprd_done) |
9f42c2b6 FF |
325 | return; |
326 | ||
327 | ath9k_ps_wakeup(sc); | |
ddfef792 | 328 | ar9003_paprd_enable(ah, false); |
9f42c2b6 | 329 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { |
9094537c | 330 | if (!(common->tx_chainmask & BIT(chain))) |
9f42c2b6 FF |
331 | continue; |
332 | ||
20bd2a09 | 333 | ar9003_paprd_populate_single_table(ah, caldata, chain); |
9f42c2b6 FF |
334 | } |
335 | ||
336 | ar9003_paprd_enable(ah, true); | |
337 | ath9k_ps_restore(sc); | |
338 | } | |
339 | ||
7607cbe2 FF |
340 | static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain) |
341 | { | |
342 | struct ieee80211_hw *hw = sc->hw; | |
343 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
47960077 MSS |
344 | struct ath_hw *ah = sc->sc_ah; |
345 | struct ath_common *common = ath9k_hw_common(ah); | |
7607cbe2 FF |
346 | struct ath_tx_control txctl; |
347 | int time_left; | |
348 | ||
349 | memset(&txctl, 0, sizeof(txctl)); | |
350 | txctl.txq = sc->tx.txq_map[WME_AC_BE]; | |
351 | ||
352 | memset(tx_info, 0, sizeof(*tx_info)); | |
353 | tx_info->band = hw->conf.channel->band; | |
354 | tx_info->flags |= IEEE80211_TX_CTL_NO_ACK; | |
355 | tx_info->control.rates[0].idx = 0; | |
356 | tx_info->control.rates[0].count = 1; | |
357 | tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS; | |
358 | tx_info->control.rates[1].idx = -1; | |
359 | ||
360 | init_completion(&sc->paprd_complete); | |
7607cbe2 | 361 | txctl.paprd = BIT(chain); |
47960077 MSS |
362 | |
363 | if (ath_tx_start(hw, skb, &txctl) != 0) { | |
364 | ath_dbg(common, ATH_DBG_XMIT, "PAPRD TX failed\n"); | |
365 | dev_kfree_skb_any(skb); | |
7607cbe2 | 366 | return false; |
47960077 | 367 | } |
7607cbe2 FF |
368 | |
369 | time_left = wait_for_completion_timeout(&sc->paprd_complete, | |
370 | msecs_to_jiffies(ATH_PAPRD_TIMEOUT)); | |
7607cbe2 FF |
371 | |
372 | if (!time_left) | |
373 | ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CALIBRATE, | |
374 | "Timeout waiting for paprd training on TX chain %d\n", | |
375 | chain); | |
376 | ||
377 | return !!time_left; | |
378 | } | |
379 | ||
9f42c2b6 FF |
380 | void ath_paprd_calibrate(struct work_struct *work) |
381 | { | |
382 | struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work); | |
383 | struct ieee80211_hw *hw = sc->hw; | |
384 | struct ath_hw *ah = sc->sc_ah; | |
385 | struct ieee80211_hdr *hdr; | |
386 | struct sk_buff *skb = NULL; | |
20bd2a09 | 387 | struct ath9k_hw_cal_data *caldata = ah->caldata; |
9094537c | 388 | struct ath_common *common = ath9k_hw_common(ah); |
066dae93 | 389 | int ftype; |
9f42c2b6 FF |
390 | int chain_ok = 0; |
391 | int chain; | |
392 | int len = 1800; | |
9f42c2b6 | 393 | |
20bd2a09 FF |
394 | if (!caldata) |
395 | return; | |
396 | ||
1bf38661 FF |
397 | if (ar9003_paprd_init_table(ah) < 0) |
398 | return; | |
399 | ||
9f42c2b6 FF |
400 | skb = alloc_skb(len, GFP_KERNEL); |
401 | if (!skb) | |
402 | return; | |
403 | ||
9f42c2b6 FF |
404 | skb_put(skb, len); |
405 | memset(skb->data, 0, len); | |
406 | hdr = (struct ieee80211_hdr *)skb->data; | |
407 | ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC; | |
408 | hdr->frame_control = cpu_to_le16(ftype); | |
a3d3da14 | 409 | hdr->duration_id = cpu_to_le16(10); |
9f42c2b6 FF |
410 | memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN); |
411 | memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN); | |
412 | memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN); | |
413 | ||
47399f1a | 414 | ath9k_ps_wakeup(sc); |
9f42c2b6 | 415 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { |
9094537c | 416 | if (!(common->tx_chainmask & BIT(chain))) |
9f42c2b6 FF |
417 | continue; |
418 | ||
419 | chain_ok = 0; | |
9f42c2b6 | 420 | |
7607cbe2 FF |
421 | ath_dbg(common, ATH_DBG_CALIBRATE, |
422 | "Sending PAPRD frame for thermal measurement " | |
423 | "on chain %d\n", chain); | |
424 | if (!ath_paprd_send_frame(sc, skb, chain)) | |
425 | goto fail_paprd; | |
9f42c2b6 | 426 | |
9f42c2b6 | 427 | ar9003_paprd_setup_gain_table(ah, chain); |
9f42c2b6 | 428 | |
7607cbe2 FF |
429 | ath_dbg(common, ATH_DBG_CALIBRATE, |
430 | "Sending PAPRD training frame on chain %d\n", chain); | |
431 | if (!ath_paprd_send_frame(sc, skb, chain)) | |
ca369eb4 | 432 | goto fail_paprd; |
9f42c2b6 FF |
433 | |
434 | if (!ar9003_paprd_is_done(ah)) | |
435 | break; | |
436 | ||
20bd2a09 | 437 | if (ar9003_paprd_create_curve(ah, caldata, chain) != 0) |
9f42c2b6 FF |
438 | break; |
439 | ||
440 | chain_ok = 1; | |
441 | } | |
442 | kfree_skb(skb); | |
443 | ||
444 | if (chain_ok) { | |
20bd2a09 | 445 | caldata->paprd_done = true; |
9f42c2b6 FF |
446 | ath_paprd_activate(sc); |
447 | } | |
448 | ||
ca369eb4 | 449 | fail_paprd: |
9f42c2b6 FF |
450 | ath9k_ps_restore(sc); |
451 | } | |
452 | ||
ff37e337 S |
453 | /* |
454 | * This routine performs the periodic noise floor calibration function | |
455 | * that is used to adjust and optimize the chip performance. This | |
456 | * takes environmental changes (location, temperature) into account. | |
457 | * When the task is complete, it reschedules itself depending on the | |
458 | * appropriate interval that was calculated. | |
459 | */ | |
55624204 | 460 | void ath_ani_calibrate(unsigned long data) |
ff37e337 | 461 | { |
20977d3e S |
462 | struct ath_softc *sc = (struct ath_softc *)data; |
463 | struct ath_hw *ah = sc->sc_ah; | |
c46917bb | 464 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
465 | bool longcal = false; |
466 | bool shortcal = false; | |
467 | bool aniflag = false; | |
468 | unsigned int timestamp = jiffies_to_msecs(jiffies); | |
6044474e | 469 | u32 cal_interval, short_cal_interval, long_cal_interval; |
b5bfc568 | 470 | unsigned long flags; |
6044474e FF |
471 | |
472 | if (ah->caldata && ah->caldata->nfcal_interference) | |
473 | long_cal_interval = ATH_LONG_CALINTERVAL_INT; | |
474 | else | |
475 | long_cal_interval = ATH_LONG_CALINTERVAL; | |
ff37e337 | 476 | |
20977d3e S |
477 | short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ? |
478 | ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL; | |
ff37e337 | 479 | |
1ffc1c61 JM |
480 | /* Only calibrate if awake */ |
481 | if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) | |
482 | goto set_timer; | |
483 | ||
484 | ath9k_ps_wakeup(sc); | |
485 | ||
ff37e337 | 486 | /* Long calibration runs independently of short calibration. */ |
6044474e | 487 | if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) { |
ff37e337 | 488 | longcal = true; |
226afe68 | 489 | ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies); |
3d536acf | 490 | common->ani.longcal_timer = timestamp; |
ff37e337 S |
491 | } |
492 | ||
17d7904d | 493 | /* Short calibration applies only while caldone is false */ |
3d536acf LR |
494 | if (!common->ani.caldone) { |
495 | if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) { | |
ff37e337 | 496 | shortcal = true; |
226afe68 JP |
497 | ath_dbg(common, ATH_DBG_ANI, |
498 | "shortcal @%lu\n", jiffies); | |
3d536acf LR |
499 | common->ani.shortcal_timer = timestamp; |
500 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
501 | } |
502 | } else { | |
3d536acf | 503 | if ((timestamp - common->ani.resetcal_timer) >= |
ff37e337 | 504 | ATH_RESTART_CALINTERVAL) { |
3d536acf LR |
505 | common->ani.caldone = ath9k_hw_reset_calvalid(ah); |
506 | if (common->ani.caldone) | |
507 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
508 | } |
509 | } | |
510 | ||
511 | /* Verify whether we must check ANI */ | |
e36b27af LR |
512 | if ((timestamp - common->ani.checkani_timer) >= |
513 | ah->config.ani_poll_interval) { | |
ff37e337 | 514 | aniflag = true; |
3d536acf | 515 | common->ani.checkani_timer = timestamp; |
ff37e337 S |
516 | } |
517 | ||
518 | /* Skip all processing if there's nothing to do. */ | |
519 | if (longcal || shortcal || aniflag) { | |
520 | /* Call ANI routine if necessary */ | |
b5bfc568 FF |
521 | if (aniflag) { |
522 | spin_lock_irqsave(&common->cc_lock, flags); | |
22e66a4c | 523 | ath9k_hw_ani_monitor(ah, ah->curchan); |
3430098a | 524 | ath_update_survey_stats(sc); |
b5bfc568 FF |
525 | spin_unlock_irqrestore(&common->cc_lock, flags); |
526 | } | |
ff37e337 S |
527 | |
528 | /* Perform calibration if necessary */ | |
529 | if (longcal || shortcal) { | |
3d536acf | 530 | common->ani.caldone = |
43c27613 LR |
531 | ath9k_hw_calibrate(ah, |
532 | ah->curchan, | |
533 | common->rx_chainmask, | |
534 | longcal); | |
ff37e337 S |
535 | } |
536 | } | |
537 | ||
1ffc1c61 JM |
538 | ath9k_ps_restore(sc); |
539 | ||
20977d3e | 540 | set_timer: |
ff37e337 S |
541 | /* |
542 | * Set timer interval based on previous results. | |
543 | * The interval must be the shortest necessary to satisfy ANI, | |
544 | * short calibration and long calibration. | |
545 | */ | |
aac9207e | 546 | cal_interval = ATH_LONG_CALINTERVAL; |
2660b81a | 547 | if (sc->sc_ah->config.enable_ani) |
e36b27af LR |
548 | cal_interval = min(cal_interval, |
549 | (u32)ah->config.ani_poll_interval); | |
3d536acf | 550 | if (!common->ani.caldone) |
20977d3e | 551 | cal_interval = min(cal_interval, (u32)short_cal_interval); |
ff37e337 | 552 | |
3d536acf | 553 | mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval)); |
20bd2a09 FF |
554 | if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) { |
555 | if (!ah->caldata->paprd_done) | |
9f42c2b6 | 556 | ieee80211_queue_work(sc->hw, &sc->paprd_work); |
45ef6a0b | 557 | else if (!ah->paprd_table_write_done) |
9f42c2b6 FF |
558 | ath_paprd_activate(sc); |
559 | } | |
ff37e337 S |
560 | } |
561 | ||
ff37e337 S |
562 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) |
563 | { | |
564 | struct ath_node *an; | |
ea066d5a | 565 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 S |
566 | an = (struct ath_node *)sta->drv_priv; |
567 | ||
7f010c93 BG |
568 | #ifdef CONFIG_ATH9K_DEBUGFS |
569 | spin_lock(&sc->nodes_lock); | |
570 | list_add(&an->list, &sc->nodes); | |
571 | spin_unlock(&sc->nodes_lock); | |
572 | an->sta = sta; | |
573 | #endif | |
ea066d5a MSS |
574 | if ((ah->caps.hw_caps) & ATH9K_HW_CAP_APM) |
575 | sc->sc_flags |= SC_OP_ENABLE_APM; | |
576 | ||
87792efc | 577 | if (sc->sc_flags & SC_OP_TXAGGR) { |
ff37e337 | 578 | ath_tx_node_init(sc, an); |
9e98ac65 | 579 | an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + |
87792efc S |
580 | sta->ht_cap.ampdu_factor); |
581 | an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density); | |
582 | } | |
ff37e337 S |
583 | } |
584 | ||
585 | static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
586 | { | |
587 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
588 | ||
7f010c93 BG |
589 | #ifdef CONFIG_ATH9K_DEBUGFS |
590 | spin_lock(&sc->nodes_lock); | |
591 | list_del(&an->list); | |
592 | spin_unlock(&sc->nodes_lock); | |
593 | an->sta = NULL; | |
594 | #endif | |
595 | ||
ff37e337 S |
596 | if (sc->sc_flags & SC_OP_TXAGGR) |
597 | ath_tx_node_cleanup(sc, an); | |
598 | } | |
599 | ||
347809fc FF |
600 | void ath_hw_check(struct work_struct *work) |
601 | { | |
602 | struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work); | |
cb8d61de FF |
603 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
604 | unsigned long flags; | |
605 | int busy; | |
347809fc FF |
606 | |
607 | ath9k_ps_wakeup(sc); | |
cb8d61de FF |
608 | if (ath9k_hw_check_alive(sc->sc_ah)) |
609 | goto out; | |
347809fc | 610 | |
cb8d61de FF |
611 | spin_lock_irqsave(&common->cc_lock, flags); |
612 | busy = ath_update_survey_stats(sc); | |
613 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
347809fc | 614 | |
cb8d61de FF |
615 | ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, " |
616 | "busy=%d (try %d)\n", busy, sc->hw_busy_count + 1); | |
617 | if (busy >= 99) { | |
618 | if (++sc->hw_busy_count >= 3) | |
619 | ath_reset(sc, true); | |
620 | } else if (busy >= 0) | |
621 | sc->hw_busy_count = 0; | |
347809fc FF |
622 | |
623 | out: | |
624 | ath9k_ps_restore(sc); | |
625 | } | |
626 | ||
b84628eb SB |
627 | static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum) |
628 | { | |
629 | static int count; | |
630 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
631 | ||
632 | if (pll_sqsum >= 0x40000) { | |
633 | count++; | |
634 | if (count == 3) { | |
635 | /* Rx is hung for more than 500ms. Reset it */ | |
636 | ath_dbg(common, ATH_DBG_RESET, | |
637 | "Possible RX hang, resetting"); | |
638 | ath_reset(sc, true); | |
639 | count = 0; | |
640 | } | |
641 | } else | |
642 | count = 0; | |
643 | } | |
644 | ||
9eab61c2 SB |
645 | void ath_hw_pll_work(struct work_struct *work) |
646 | { | |
647 | struct ath_softc *sc = container_of(work, struct ath_softc, | |
648 | hw_pll_work.work); | |
b84628eb | 649 | u32 pll_sqsum; |
9eab61c2 SB |
650 | |
651 | if (AR_SREV_9485(sc->sc_ah)) { | |
b84628eb SB |
652 | |
653 | ath9k_ps_wakeup(sc); | |
654 | pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah); | |
655 | ath9k_ps_restore(sc); | |
656 | ||
657 | ath_hw_pll_rx_hang_check(sc, pll_sqsum); | |
9eab61c2 SB |
658 | |
659 | ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5); | |
660 | } | |
661 | } | |
662 | ||
663 | ||
55624204 | 664 | void ath9k_tasklet(unsigned long data) |
ff37e337 S |
665 | { |
666 | struct ath_softc *sc = (struct ath_softc *)data; | |
af03abec | 667 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 668 | struct ath_common *common = ath9k_hw_common(ah); |
af03abec | 669 | |
17d7904d | 670 | u32 status = sc->intrstatus; |
b5c80475 | 671 | u32 rxmask; |
ff37e337 | 672 | |
a4d86d95 RM |
673 | if ((status & ATH9K_INT_FATAL) || |
674 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
fac6b6a0 | 675 | ath_reset(sc, true); |
ff37e337 | 676 | return; |
063d8be3 | 677 | } |
ff37e337 | 678 | |
783cd01e | 679 | ath9k_ps_wakeup(sc); |
52671e43 | 680 | spin_lock(&sc->sc_pcu_lock); |
6a6733f2 | 681 | |
8b3f4616 FF |
682 | /* |
683 | * Only run the baseband hang check if beacons stop working in AP or | |
684 | * IBSS mode, because it has a high false positive rate. For station | |
685 | * mode it should not be necessary, since the upper layers will detect | |
686 | * this through a beacon miss automatically and the following channel | |
687 | * change will trigger a hardware reset anyway | |
688 | */ | |
689 | if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 && | |
690 | !ath9k_hw_check_alive(ah)) | |
347809fc FF |
691 | ieee80211_queue_work(sc->hw, &sc->hw_check_work); |
692 | ||
4105f807 RM |
693 | if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { |
694 | /* | |
695 | * TSF sync does not look correct; remain awake to sync with | |
696 | * the next Beacon. | |
697 | */ | |
698 | ath_dbg(common, ATH_DBG_PS, | |
699 | "TSFOOR - Sync with next Beacon\n"); | |
700 | sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC | | |
701 | PS_TSFOOR_SYNC; | |
702 | } | |
703 | ||
b5c80475 FF |
704 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
705 | rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | | |
706 | ATH9K_INT_RXORN); | |
707 | else | |
708 | rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
709 | ||
710 | if (status & rxmask) { | |
b5c80475 FF |
711 | /* Check for high priority Rx first */ |
712 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && | |
713 | (status & ATH9K_INT_RXHP)) | |
714 | ath_rx_tasklet(sc, 0, true); | |
715 | ||
716 | ath_rx_tasklet(sc, 0, false); | |
ff37e337 S |
717 | } |
718 | ||
e5003249 VT |
719 | if (status & ATH9K_INT_TX) { |
720 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
721 | ath_tx_edma_tasklet(sc); | |
722 | else | |
723 | ath_tx_tasklet(sc); | |
724 | } | |
063d8be3 | 725 | |
766ec4a9 | 726 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
ebb8e1d7 VT |
727 | if (status & ATH9K_INT_GENTIMER) |
728 | ath_gen_timer_isr(sc->sc_ah); | |
729 | ||
ff37e337 | 730 | /* re-enable hardware interrupt */ |
4df3071e | 731 | ath9k_hw_enable_interrupts(ah); |
6a6733f2 | 732 | |
52671e43 | 733 | spin_unlock(&sc->sc_pcu_lock); |
153e080d | 734 | ath9k_ps_restore(sc); |
ff37e337 S |
735 | } |
736 | ||
6baff7f9 | 737 | irqreturn_t ath_isr(int irq, void *dev) |
ff37e337 | 738 | { |
063d8be3 S |
739 | #define SCHED_INTR ( \ |
740 | ATH9K_INT_FATAL | \ | |
a4d86d95 | 741 | ATH9K_INT_BB_WATCHDOG | \ |
063d8be3 S |
742 | ATH9K_INT_RXORN | \ |
743 | ATH9K_INT_RXEOL | \ | |
744 | ATH9K_INT_RX | \ | |
b5c80475 FF |
745 | ATH9K_INT_RXLP | \ |
746 | ATH9K_INT_RXHP | \ | |
063d8be3 S |
747 | ATH9K_INT_TX | \ |
748 | ATH9K_INT_BMISS | \ | |
749 | ATH9K_INT_CST | \ | |
ebb8e1d7 VT |
750 | ATH9K_INT_TSFOOR | \ |
751 | ATH9K_INT_GENTIMER) | |
063d8be3 | 752 | |
ff37e337 | 753 | struct ath_softc *sc = dev; |
cbe61d8a | 754 | struct ath_hw *ah = sc->sc_ah; |
b5bfc568 | 755 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
756 | enum ath9k_int status; |
757 | bool sched = false; | |
758 | ||
063d8be3 S |
759 | /* |
760 | * The hardware is not ready/present, don't | |
761 | * touch anything. Note this can happen early | |
762 | * on if the IRQ is shared. | |
763 | */ | |
764 | if (sc->sc_flags & SC_OP_INVALID) | |
765 | return IRQ_NONE; | |
ff37e337 | 766 | |
063d8be3 S |
767 | |
768 | /* shared irq, not for us */ | |
769 | ||
153e080d | 770 | if (!ath9k_hw_intrpend(ah)) |
063d8be3 | 771 | return IRQ_NONE; |
063d8be3 S |
772 | |
773 | /* | |
774 | * Figure out the reason(s) for the interrupt. Note | |
775 | * that the hal returns a pseudo-ISR that may include | |
776 | * bits we haven't explicitly enabled so we mask the | |
777 | * value to insure we only process bits we requested. | |
778 | */ | |
779 | ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ | |
3069168c | 780 | status &= ah->imask; /* discard unasked-for bits */ |
ff37e337 | 781 | |
063d8be3 S |
782 | /* |
783 | * If there are no status bits set, then this interrupt was not | |
784 | * for me (should have been caught above). | |
785 | */ | |
153e080d | 786 | if (!status) |
063d8be3 | 787 | return IRQ_NONE; |
ff37e337 | 788 | |
063d8be3 S |
789 | /* Cache the status */ |
790 | sc->intrstatus = status; | |
791 | ||
792 | if (status & SCHED_INTR) | |
793 | sched = true; | |
794 | ||
795 | /* | |
796 | * If a FATAL or RXORN interrupt is received, we have to reset the | |
797 | * chip immediately. | |
798 | */ | |
b5c80475 FF |
799 | if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && |
800 | !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) | |
063d8be3 S |
801 | goto chip_reset; |
802 | ||
08578b8f LR |
803 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && |
804 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
b5bfc568 FF |
805 | |
806 | spin_lock(&common->cc_lock); | |
807 | ath_hw_cycle_counters_update(common); | |
08578b8f | 808 | ar9003_hw_bb_watchdog_dbg_info(ah); |
b5bfc568 FF |
809 | spin_unlock(&common->cc_lock); |
810 | ||
08578b8f LR |
811 | goto chip_reset; |
812 | } | |
813 | ||
063d8be3 S |
814 | if (status & ATH9K_INT_SWBA) |
815 | tasklet_schedule(&sc->bcon_tasklet); | |
816 | ||
817 | if (status & ATH9K_INT_TXURN) | |
818 | ath9k_hw_updatetxtriglevel(ah, true); | |
819 | ||
b5c80475 FF |
820 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
821 | if (status & ATH9K_INT_RXEOL) { | |
822 | ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
823 | ath9k_hw_set_interrupts(ah, ah->imask); | |
824 | } | |
825 | } | |
826 | ||
063d8be3 | 827 | if (status & ATH9K_INT_MIB) { |
ff37e337 | 828 | /* |
063d8be3 S |
829 | * Disable interrupts until we service the MIB |
830 | * interrupt; otherwise it will continue to | |
831 | * fire. | |
ff37e337 | 832 | */ |
4df3071e | 833 | ath9k_hw_disable_interrupts(ah); |
063d8be3 S |
834 | /* |
835 | * Let the hal handle the event. We assume | |
836 | * it will clear whatever condition caused | |
837 | * the interrupt. | |
838 | */ | |
88eac2da | 839 | spin_lock(&common->cc_lock); |
bfc472bb | 840 | ath9k_hw_proc_mib_event(ah); |
88eac2da | 841 | spin_unlock(&common->cc_lock); |
4df3071e | 842 | ath9k_hw_enable_interrupts(ah); |
063d8be3 | 843 | } |
ff37e337 | 844 | |
153e080d VT |
845 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
846 | if (status & ATH9K_INT_TIM_TIMER) { | |
ff9f0b63 LR |
847 | if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) |
848 | goto chip_reset; | |
063d8be3 S |
849 | /* Clear RxAbort bit so that we can |
850 | * receive frames */ | |
9ecdef4b | 851 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
153e080d | 852 | ath9k_hw_setrxabort(sc->sc_ah, 0); |
1b04b930 | 853 | sc->ps_flags |= PS_WAIT_FOR_BEACON; |
ff37e337 | 854 | } |
063d8be3 S |
855 | |
856 | chip_reset: | |
ff37e337 | 857 | |
817e11de S |
858 | ath_debug_stat_interrupt(sc, status); |
859 | ||
ff37e337 | 860 | if (sched) { |
4df3071e FF |
861 | /* turn off every interrupt */ |
862 | ath9k_hw_disable_interrupts(ah); | |
ff37e337 S |
863 | tasklet_schedule(&sc->intr_tq); |
864 | } | |
865 | ||
866 | return IRQ_HANDLED; | |
063d8be3 S |
867 | |
868 | #undef SCHED_INTR | |
ff37e337 S |
869 | } |
870 | ||
68a89116 | 871 | void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 872 | { |
cbe61d8a | 873 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 874 | struct ath_common *common = ath9k_hw_common(ah); |
68a89116 | 875 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 876 | int r; |
500c064d | 877 | |
3cbb5dd7 | 878 | ath9k_ps_wakeup(sc); |
6a6733f2 LR |
879 | spin_lock_bh(&sc->sc_pcu_lock); |
880 | ||
93b1b37f | 881 | ath9k_hw_configpcipowersave(ah, 0, 0); |
ae8d2858 | 882 | |
159cd468 | 883 | if (!ah->curchan) |
c344c9cb | 884 | ah->curchan = ath9k_cmn_get_curchannel(sc->hw, ah); |
159cd468 | 885 | |
20bd2a09 | 886 | r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); |
ae8d2858 | 887 | if (r) { |
3800276a JP |
888 | ath_err(common, |
889 | "Unable to reset channel (%u MHz), reset status %d\n", | |
890 | channel->center_freq, r); | |
500c064d | 891 | } |
500c064d | 892 | |
5048e8c3 RM |
893 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
894 | sc->config.txpowlimit, &sc->curtxpow); | |
500c064d | 895 | if (ath_startrecv(sc) != 0) { |
3800276a | 896 | ath_err(common, "Unable to restart recv logic\n"); |
c2731b81 | 897 | goto out; |
500c064d | 898 | } |
500c064d | 899 | if (sc->sc_flags & SC_OP_BEACONS) |
99e4d43a | 900 | ath_set_beacon(sc); /* restart beacons */ |
500c064d VT |
901 | |
902 | /* Re-Enable interrupts */ | |
3069168c | 903 | ath9k_hw_set_interrupts(ah, ah->imask); |
500c064d VT |
904 | |
905 | /* Enable LED */ | |
08fc5c1b | 906 | ath9k_hw_cfg_output(ah, ah->led_pin, |
500c064d | 907 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); |
08fc5c1b | 908 | ath9k_hw_set_gpio(ah, ah->led_pin, 0); |
500c064d | 909 | |
68a89116 | 910 | ieee80211_wake_queues(hw); |
7e3514fd VN |
911 | ieee80211_queue_delayed_work(hw, &sc->hw_pll_work, HZ/2); |
912 | ||
c2731b81 | 913 | out: |
6a6733f2 LR |
914 | spin_unlock_bh(&sc->sc_pcu_lock); |
915 | ||
3cbb5dd7 | 916 | ath9k_ps_restore(sc); |
500c064d VT |
917 | } |
918 | ||
68a89116 | 919 | void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 920 | { |
cbe61d8a | 921 | struct ath_hw *ah = sc->sc_ah; |
68a89116 | 922 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 923 | int r; |
500c064d | 924 | |
3cbb5dd7 | 925 | ath9k_ps_wakeup(sc); |
7e3514fd VN |
926 | cancel_delayed_work_sync(&sc->hw_pll_work); |
927 | ||
6a6733f2 LR |
928 | spin_lock_bh(&sc->sc_pcu_lock); |
929 | ||
68a89116 | 930 | ieee80211_stop_queues(hw); |
500c064d | 931 | |
982723df VN |
932 | /* |
933 | * Keep the LED on when the radio is disabled | |
934 | * during idle unassociated state. | |
935 | */ | |
936 | if (!sc->ps_idle) { | |
937 | ath9k_hw_set_gpio(ah, ah->led_pin, 1); | |
938 | ath9k_hw_cfg_gpio_input(ah, ah->led_pin); | |
939 | } | |
500c064d VT |
940 | |
941 | /* Disable interrupts */ | |
4df3071e | 942 | ath9k_hw_disable_interrupts(ah); |
500c064d | 943 | |
043a0405 | 944 | ath_drain_all_txq(sc, false); /* clear pending tx frames */ |
5e848f78 | 945 | |
500c064d VT |
946 | ath_stoprecv(sc); /* turn off frame recv */ |
947 | ath_flushrecv(sc); /* flush recv queue */ | |
948 | ||
159cd468 | 949 | if (!ah->curchan) |
c344c9cb | 950 | ah->curchan = ath9k_cmn_get_curchannel(hw, ah); |
159cd468 | 951 | |
20bd2a09 | 952 | r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); |
ae8d2858 | 953 | if (r) { |
3800276a JP |
954 | ath_err(ath9k_hw_common(sc->sc_ah), |
955 | "Unable to reset channel (%u MHz), reset status %d\n", | |
956 | channel->center_freq, r); | |
500c064d | 957 | } |
500c064d VT |
958 | |
959 | ath9k_hw_phy_disable(ah); | |
5e848f78 | 960 | |
93b1b37f | 961 | ath9k_hw_configpcipowersave(ah, 1, 1); |
6a6733f2 LR |
962 | |
963 | spin_unlock_bh(&sc->sc_pcu_lock); | |
3cbb5dd7 | 964 | ath9k_ps_restore(sc); |
500c064d VT |
965 | } |
966 | ||
ff37e337 S |
967 | int ath_reset(struct ath_softc *sc, bool retry_tx) |
968 | { | |
cbe61d8a | 969 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 970 | struct ath_common *common = ath9k_hw_common(ah); |
030bb495 | 971 | struct ieee80211_hw *hw = sc->hw; |
ae8d2858 | 972 | int r; |
ff37e337 | 973 | |
cb8d61de FF |
974 | sc->hw_busy_count = 0; |
975 | ||
2ab81d4a S |
976 | /* Stop ANI */ |
977 | del_timer_sync(&common->ani.timer); | |
978 | ||
783cd01e | 979 | ath9k_ps_wakeup(sc); |
6a6733f2 LR |
980 | spin_lock_bh(&sc->sc_pcu_lock); |
981 | ||
cc9c378a S |
982 | ieee80211_stop_queues(hw); |
983 | ||
4df3071e | 984 | ath9k_hw_disable_interrupts(ah); |
043a0405 | 985 | ath_drain_all_txq(sc, retry_tx); |
5e848f78 | 986 | |
ff37e337 S |
987 | ath_stoprecv(sc); |
988 | ath_flushrecv(sc); | |
989 | ||
20bd2a09 | 990 | r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false); |
ae8d2858 | 991 | if (r) |
3800276a JP |
992 | ath_err(common, |
993 | "Unable to reset hardware; reset status %d\n", r); | |
ff37e337 S |
994 | |
995 | if (ath_startrecv(sc) != 0) | |
3800276a | 996 | ath_err(common, "Unable to start recv logic\n"); |
ff37e337 S |
997 | |
998 | /* | |
999 | * We may be doing a reset in response to a request | |
1000 | * that changes the channel so update any state that | |
1001 | * might change as a result. | |
1002 | */ | |
5048e8c3 RM |
1003 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
1004 | sc->config.txpowlimit, &sc->curtxpow); | |
ff37e337 | 1005 | |
52b8ac92 | 1006 | if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL))) |
99e4d43a | 1007 | ath_set_beacon(sc); /* restart beacons */ |
ff37e337 | 1008 | |
3069168c | 1009 | ath9k_hw_set_interrupts(ah, ah->imask); |
ff37e337 S |
1010 | |
1011 | if (retry_tx) { | |
1012 | int i; | |
1013 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1014 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f S |
1015 | spin_lock_bh(&sc->tx.txq[i].axq_lock); |
1016 | ath_txq_schedule(sc, &sc->tx.txq[i]); | |
1017 | spin_unlock_bh(&sc->tx.txq[i].axq_lock); | |
ff37e337 S |
1018 | } |
1019 | } | |
1020 | } | |
1021 | ||
cc9c378a | 1022 | ieee80211_wake_queues(hw); |
6a6733f2 | 1023 | spin_unlock_bh(&sc->sc_pcu_lock); |
cc9c378a | 1024 | |
2ab81d4a S |
1025 | /* Start ANI */ |
1026 | ath_start_ani(common); | |
783cd01e | 1027 | ath9k_ps_restore(sc); |
2ab81d4a | 1028 | |
ae8d2858 | 1029 | return r; |
ff37e337 S |
1030 | } |
1031 | ||
ff37e337 S |
1032 | /**********************/ |
1033 | /* mac80211 callbacks */ | |
1034 | /**********************/ | |
1035 | ||
8feceb67 | 1036 | static int ath9k_start(struct ieee80211_hw *hw) |
f078f209 | 1037 | { |
9ac58615 | 1038 | struct ath_softc *sc = hw->priv; |
af03abec | 1039 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1040 | struct ath_common *common = ath9k_hw_common(ah); |
8feceb67 | 1041 | struct ieee80211_channel *curchan = hw->conf.channel; |
ff37e337 | 1042 | struct ath9k_channel *init_channel; |
82880a7c | 1043 | int r; |
f078f209 | 1044 | |
226afe68 JP |
1045 | ath_dbg(common, ATH_DBG_CONFIG, |
1046 | "Starting driver with initial channel: %d MHz\n", | |
1047 | curchan->center_freq); | |
f078f209 | 1048 | |
f62d816f FF |
1049 | ath9k_ps_wakeup(sc); |
1050 | ||
141b38b6 S |
1051 | mutex_lock(&sc->mutex); |
1052 | ||
8feceb67 | 1053 | /* setup initial channel */ |
82880a7c | 1054 | sc->chan_idx = curchan->hw_value; |
f078f209 | 1055 | |
c344c9cb | 1056 | init_channel = ath9k_cmn_get_curchannel(hw, ah); |
ff37e337 S |
1057 | |
1058 | /* Reset SERDES registers */ | |
af03abec | 1059 | ath9k_hw_configpcipowersave(ah, 0, 0); |
ff37e337 S |
1060 | |
1061 | /* | |
1062 | * The basic interface to setting the hardware in a good | |
1063 | * state is ``reset''. On return the hardware is known to | |
1064 | * be powered up and with interrupts disabled. This must | |
1065 | * be followed by initialization of the appropriate bits | |
1066 | * and then setup of the interrupt mask. | |
1067 | */ | |
4bdd1e97 | 1068 | spin_lock_bh(&sc->sc_pcu_lock); |
20bd2a09 | 1069 | r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); |
ae8d2858 | 1070 | if (r) { |
3800276a JP |
1071 | ath_err(common, |
1072 | "Unable to reset hardware; reset status %d (freq %u MHz)\n", | |
1073 | r, curchan->center_freq); | |
4bdd1e97 | 1074 | spin_unlock_bh(&sc->sc_pcu_lock); |
141b38b6 | 1075 | goto mutex_unlock; |
ff37e337 | 1076 | } |
ff37e337 S |
1077 | |
1078 | /* | |
1079 | * This is needed only to setup initial state | |
1080 | * but it's best done after a reset. | |
1081 | */ | |
5048e8c3 RM |
1082 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
1083 | sc->config.txpowlimit, &sc->curtxpow); | |
8feceb67 | 1084 | |
ff37e337 S |
1085 | /* |
1086 | * Setup the hardware after reset: | |
1087 | * The receive engine is set going. | |
1088 | * Frame transmit is handled entirely | |
1089 | * in the frame output path; there's nothing to do | |
1090 | * here except setup the interrupt mask. | |
1091 | */ | |
1092 | if (ath_startrecv(sc) != 0) { | |
3800276a | 1093 | ath_err(common, "Unable to start recv logic\n"); |
141b38b6 | 1094 | r = -EIO; |
4bdd1e97 | 1095 | spin_unlock_bh(&sc->sc_pcu_lock); |
141b38b6 | 1096 | goto mutex_unlock; |
f078f209 | 1097 | } |
4bdd1e97 | 1098 | spin_unlock_bh(&sc->sc_pcu_lock); |
8feceb67 | 1099 | |
ff37e337 | 1100 | /* Setup our intr mask. */ |
b5c80475 FF |
1101 | ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | |
1102 | ATH9K_INT_RXORN | ATH9K_INT_FATAL | | |
1103 | ATH9K_INT_GLOBAL; | |
1104 | ||
1105 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
08578b8f LR |
1106 | ah->imask |= ATH9K_INT_RXHP | |
1107 | ATH9K_INT_RXLP | | |
1108 | ATH9K_INT_BB_WATCHDOG; | |
b5c80475 FF |
1109 | else |
1110 | ah->imask |= ATH9K_INT_RX; | |
ff37e337 | 1111 | |
364734fa | 1112 | ah->imask |= ATH9K_INT_GTT; |
ff37e337 | 1113 | |
af03abec | 1114 | if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
3069168c | 1115 | ah->imask |= ATH9K_INT_CST; |
ff37e337 | 1116 | |
ff37e337 | 1117 | sc->sc_flags &= ~SC_OP_INVALID; |
5f841b41 | 1118 | sc->sc_ah->is_monitoring = false; |
ff37e337 S |
1119 | |
1120 | /* Disable BMISS interrupt when we're not associated */ | |
3069168c PR |
1121 | ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); |
1122 | ath9k_hw_set_interrupts(ah, ah->imask); | |
ff37e337 | 1123 | |
bce048d7 | 1124 | ieee80211_wake_queues(hw); |
ff37e337 | 1125 | |
42935eca | 1126 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
164ace38 | 1127 | |
766ec4a9 LR |
1128 | if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) && |
1129 | !ah->btcoex_hw.enabled) { | |
5e197292 LR |
1130 | ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT, |
1131 | AR_STOMP_LOW_WLAN_WGHT); | |
af03abec | 1132 | ath9k_hw_btcoex_enable(ah); |
f985ad12 | 1133 | |
5bb12791 LR |
1134 | if (common->bus_ops->bt_coex_prep) |
1135 | common->bus_ops->bt_coex_prep(common); | |
766ec4a9 | 1136 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1137 | ath9k_btcoex_timer_resume(sc); |
1773912b VT |
1138 | } |
1139 | ||
8060e169 VT |
1140 | if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en) |
1141 | common->bus_ops->extn_synch_en(common); | |
1142 | ||
141b38b6 S |
1143 | mutex_unlock: |
1144 | mutex_unlock(&sc->mutex); | |
1145 | ||
f62d816f FF |
1146 | ath9k_ps_restore(sc); |
1147 | ||
ae8d2858 | 1148 | return r; |
f078f209 LR |
1149 | } |
1150 | ||
7bb45683 | 1151 | static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
f078f209 | 1152 | { |
9ac58615 | 1153 | struct ath_softc *sc = hw->priv; |
c46917bb | 1154 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
528f0c6b | 1155 | struct ath_tx_control txctl; |
1bc14880 | 1156 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; |
528f0c6b | 1157 | |
96148326 | 1158 | if (sc->ps_enabled) { |
dc8c4585 JM |
1159 | /* |
1160 | * mac80211 does not set PM field for normal data frames, so we | |
1161 | * need to update that based on the current PS mode. | |
1162 | */ | |
1163 | if (ieee80211_is_data(hdr->frame_control) && | |
1164 | !ieee80211_is_nullfunc(hdr->frame_control) && | |
1165 | !ieee80211_has_pm(hdr->frame_control)) { | |
226afe68 JP |
1166 | ath_dbg(common, ATH_DBG_PS, |
1167 | "Add PM=1 for a TX frame while in PS mode\n"); | |
dc8c4585 JM |
1168 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); |
1169 | } | |
1170 | } | |
1171 | ||
9a23f9ca JM |
1172 | if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) { |
1173 | /* | |
1174 | * We are using PS-Poll and mac80211 can request TX while in | |
1175 | * power save mode. Need to wake up hardware for the TX to be | |
1176 | * completed and if needed, also for RX of buffered frames. | |
1177 | */ | |
9a23f9ca | 1178 | ath9k_ps_wakeup(sc); |
fdf76622 VT |
1179 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
1180 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
9a23f9ca | 1181 | if (ieee80211_is_pspoll(hdr->frame_control)) { |
226afe68 JP |
1182 | ath_dbg(common, ATH_DBG_PS, |
1183 | "Sending PS-Poll to pick a buffered frame\n"); | |
1b04b930 | 1184 | sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; |
9a23f9ca | 1185 | } else { |
226afe68 JP |
1186 | ath_dbg(common, ATH_DBG_PS, |
1187 | "Wake up to complete TX\n"); | |
1b04b930 | 1188 | sc->ps_flags |= PS_WAIT_FOR_TX_ACK; |
9a23f9ca JM |
1189 | } |
1190 | /* | |
1191 | * The actual restore operation will happen only after | |
1192 | * the sc_flags bit is cleared. We are just dropping | |
1193 | * the ps_usecount here. | |
1194 | */ | |
1195 | ath9k_ps_restore(sc); | |
1196 | } | |
1197 | ||
528f0c6b | 1198 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
066dae93 | 1199 | txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; |
528f0c6b | 1200 | |
226afe68 | 1201 | ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); |
8feceb67 | 1202 | |
c52f33d0 | 1203 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
226afe68 | 1204 | ath_dbg(common, ATH_DBG_XMIT, "TX failed\n"); |
528f0c6b | 1205 | goto exit; |
8feceb67 VT |
1206 | } |
1207 | ||
7bb45683 | 1208 | return; |
528f0c6b S |
1209 | exit: |
1210 | dev_kfree_skb_any(skb); | |
f078f209 LR |
1211 | } |
1212 | ||
8feceb67 | 1213 | static void ath9k_stop(struct ieee80211_hw *hw) |
f078f209 | 1214 | { |
9ac58615 | 1215 | struct ath_softc *sc = hw->priv; |
af03abec | 1216 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1217 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 1218 | |
4c483817 S |
1219 | mutex_lock(&sc->mutex); |
1220 | ||
c94dbff7 | 1221 | cancel_delayed_work_sync(&sc->tx_complete_work); |
181fb18d | 1222 | cancel_delayed_work_sync(&sc->hw_pll_work); |
9f42c2b6 | 1223 | cancel_work_sync(&sc->paprd_work); |
347809fc | 1224 | cancel_work_sync(&sc->hw_check_work); |
c94dbff7 | 1225 | |
9c84b797 | 1226 | if (sc->sc_flags & SC_OP_INVALID) { |
226afe68 | 1227 | ath_dbg(common, ATH_DBG_ANY, "Device not present\n"); |
4c483817 | 1228 | mutex_unlock(&sc->mutex); |
9c84b797 S |
1229 | return; |
1230 | } | |
8feceb67 | 1231 | |
3867cf6a S |
1232 | /* Ensure HW is awake when we try to shut it down. */ |
1233 | ath9k_ps_wakeup(sc); | |
1234 | ||
766ec4a9 | 1235 | if (ah->btcoex_hw.enabled) { |
af03abec | 1236 | ath9k_hw_btcoex_disable(ah); |
766ec4a9 | 1237 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1238 | ath9k_btcoex_timer_pause(sc); |
1773912b VT |
1239 | } |
1240 | ||
6a6733f2 LR |
1241 | spin_lock_bh(&sc->sc_pcu_lock); |
1242 | ||
203043f5 SG |
1243 | /* prevent tasklets to enable interrupts once we disable them */ |
1244 | ah->imask &= ~ATH9K_INT_GLOBAL; | |
1245 | ||
ff37e337 S |
1246 | /* make sure h/w will not generate any interrupt |
1247 | * before setting the invalid flag. */ | |
4df3071e | 1248 | ath9k_hw_disable_interrupts(ah); |
ff37e337 S |
1249 | |
1250 | if (!(sc->sc_flags & SC_OP_INVALID)) { | |
043a0405 | 1251 | ath_drain_all_txq(sc, false); |
ff37e337 | 1252 | ath_stoprecv(sc); |
af03abec | 1253 | ath9k_hw_phy_disable(ah); |
6a6733f2 | 1254 | } else |
b77f483f | 1255 | sc->rx.rxlink = NULL; |
ff37e337 | 1256 | |
0d95521e FF |
1257 | if (sc->rx.frag) { |
1258 | dev_kfree_skb_any(sc->rx.frag); | |
1259 | sc->rx.frag = NULL; | |
1260 | } | |
1261 | ||
ff37e337 | 1262 | /* disable HAL and put h/w to sleep */ |
af03abec LR |
1263 | ath9k_hw_disable(ah); |
1264 | ath9k_hw_configpcipowersave(ah, 1, 1); | |
6a6733f2 LR |
1265 | |
1266 | spin_unlock_bh(&sc->sc_pcu_lock); | |
1267 | ||
203043f5 SG |
1268 | /* we can now sync irq and kill any running tasklets, since we already |
1269 | * disabled interrupts and not holding a spin lock */ | |
1270 | synchronize_irq(sc->irq); | |
1271 | tasklet_kill(&sc->intr_tq); | |
1272 | tasklet_kill(&sc->bcon_tasklet); | |
1273 | ||
3867cf6a S |
1274 | ath9k_ps_restore(sc); |
1275 | ||
a08e7ade LR |
1276 | sc->ps_idle = true; |
1277 | ath_radio_disable(sc, hw); | |
ff37e337 S |
1278 | |
1279 | sc->sc_flags |= SC_OP_INVALID; | |
500c064d | 1280 | |
141b38b6 S |
1281 | mutex_unlock(&sc->mutex); |
1282 | ||
226afe68 | 1283 | ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n"); |
f078f209 LR |
1284 | } |
1285 | ||
4801416c BG |
1286 | bool ath9k_uses_beacons(int type) |
1287 | { | |
1288 | switch (type) { | |
1289 | case NL80211_IFTYPE_AP: | |
1290 | case NL80211_IFTYPE_ADHOC: | |
1291 | case NL80211_IFTYPE_MESH_POINT: | |
1292 | return true; | |
1293 | default: | |
1294 | return false; | |
1295 | } | |
1296 | } | |
1297 | ||
1298 | static void ath9k_reclaim_beacon(struct ath_softc *sc, | |
1299 | struct ieee80211_vif *vif) | |
f078f209 | 1300 | { |
1ed32e4f | 1301 | struct ath_vif *avp = (void *)vif->drv_priv; |
8feceb67 | 1302 | |
014cf3bb | 1303 | ath9k_set_beaconing_status(sc, false); |
4801416c | 1304 | ath_beacon_return(sc, avp); |
014cf3bb | 1305 | ath9k_set_beaconing_status(sc, true); |
4801416c | 1306 | sc->sc_flags &= ~SC_OP_BEACONS; |
4801416c BG |
1307 | } |
1308 | ||
1309 | static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) | |
1310 | { | |
1311 | struct ath9k_vif_iter_data *iter_data = data; | |
1312 | int i; | |
1313 | ||
1314 | if (iter_data->hw_macaddr) | |
1315 | for (i = 0; i < ETH_ALEN; i++) | |
1316 | iter_data->mask[i] &= | |
1317 | ~(iter_data->hw_macaddr[i] ^ mac[i]); | |
141b38b6 | 1318 | |
1ed32e4f | 1319 | switch (vif->type) { |
4801416c BG |
1320 | case NL80211_IFTYPE_AP: |
1321 | iter_data->naps++; | |
f078f209 | 1322 | break; |
4801416c BG |
1323 | case NL80211_IFTYPE_STATION: |
1324 | iter_data->nstations++; | |
e51f3eff | 1325 | break; |
05c914fe | 1326 | case NL80211_IFTYPE_ADHOC: |
4801416c BG |
1327 | iter_data->nadhocs++; |
1328 | break; | |
9cb5412b | 1329 | case NL80211_IFTYPE_MESH_POINT: |
4801416c BG |
1330 | iter_data->nmeshes++; |
1331 | break; | |
1332 | case NL80211_IFTYPE_WDS: | |
1333 | iter_data->nwds++; | |
f078f209 LR |
1334 | break; |
1335 | default: | |
4801416c BG |
1336 | iter_data->nothers++; |
1337 | break; | |
f078f209 | 1338 | } |
4801416c | 1339 | } |
f078f209 | 1340 | |
4801416c BG |
1341 | /* Called with sc->mutex held. */ |
1342 | void ath9k_calculate_iter_data(struct ieee80211_hw *hw, | |
1343 | struct ieee80211_vif *vif, | |
1344 | struct ath9k_vif_iter_data *iter_data) | |
1345 | { | |
9ac58615 | 1346 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1347 | struct ath_hw *ah = sc->sc_ah; |
1348 | struct ath_common *common = ath9k_hw_common(ah); | |
8feceb67 | 1349 | |
4801416c BG |
1350 | /* |
1351 | * Use the hardware MAC address as reference, the hardware uses it | |
1352 | * together with the BSSID mask when matching addresses. | |
1353 | */ | |
1354 | memset(iter_data, 0, sizeof(*iter_data)); | |
1355 | iter_data->hw_macaddr = common->macaddr; | |
1356 | memset(&iter_data->mask, 0xff, ETH_ALEN); | |
5640b08e | 1357 | |
4801416c BG |
1358 | if (vif) |
1359 | ath9k_vif_iter(iter_data, vif->addr, vif); | |
1360 | ||
1361 | /* Get list of all active MAC addresses */ | |
4801416c BG |
1362 | ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter, |
1363 | iter_data); | |
4801416c | 1364 | } |
8ca21f01 | 1365 | |
4801416c BG |
1366 | /* Called with sc->mutex held. */ |
1367 | static void ath9k_calculate_summary_state(struct ieee80211_hw *hw, | |
1368 | struct ieee80211_vif *vif) | |
1369 | { | |
9ac58615 | 1370 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1371 | struct ath_hw *ah = sc->sc_ah; |
1372 | struct ath_common *common = ath9k_hw_common(ah); | |
1373 | struct ath9k_vif_iter_data iter_data; | |
8ca21f01 | 1374 | |
4801416c | 1375 | ath9k_calculate_iter_data(hw, vif, &iter_data); |
2c3db3d5 | 1376 | |
4801416c BG |
1377 | /* Set BSSID mask. */ |
1378 | memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); | |
1379 | ath_hw_setbssidmask(common); | |
1380 | ||
1381 | /* Set op-mode & TSF */ | |
1382 | if (iter_data.naps > 0) { | |
3069168c | 1383 | ath9k_hw_set_tsfadjust(ah, 1); |
b238e90e | 1384 | sc->sc_flags |= SC_OP_TSF_RESET; |
4801416c BG |
1385 | ah->opmode = NL80211_IFTYPE_AP; |
1386 | } else { | |
1387 | ath9k_hw_set_tsfadjust(ah, 0); | |
1388 | sc->sc_flags &= ~SC_OP_TSF_RESET; | |
5640b08e | 1389 | |
fd5999cf JC |
1390 | if (iter_data.nmeshes) |
1391 | ah->opmode = NL80211_IFTYPE_MESH_POINT; | |
1392 | else if (iter_data.nwds) | |
4801416c BG |
1393 | ah->opmode = NL80211_IFTYPE_AP; |
1394 | else if (iter_data.nadhocs) | |
1395 | ah->opmode = NL80211_IFTYPE_ADHOC; | |
1396 | else | |
1397 | ah->opmode = NL80211_IFTYPE_STATION; | |
1398 | } | |
5640b08e | 1399 | |
4e30ffa2 VN |
1400 | /* |
1401 | * Enable MIB interrupts when there are hardware phy counters. | |
4e30ffa2 | 1402 | */ |
4801416c | 1403 | if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) { |
3448f912 LR |
1404 | if (ah->config.enable_ani) |
1405 | ah->imask |= ATH9K_INT_MIB; | |
3069168c | 1406 | ah->imask |= ATH9K_INT_TSFOOR; |
4801416c BG |
1407 | } else { |
1408 | ah->imask &= ~ATH9K_INT_MIB; | |
1409 | ah->imask &= ~ATH9K_INT_TSFOOR; | |
4af9cf4f S |
1410 | } |
1411 | ||
3069168c | 1412 | ath9k_hw_set_interrupts(ah, ah->imask); |
4e30ffa2 | 1413 | |
4801416c BG |
1414 | /* Set up ANI */ |
1415 | if ((iter_data.naps + iter_data.nadhocs) > 0) { | |
729da390 | 1416 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; |
6c3118e2 | 1417 | sc->sc_flags |= SC_OP_ANI_RUN; |
3d536acf | 1418 | ath_start_ani(common); |
f60c49b6 RM |
1419 | } else { |
1420 | sc->sc_flags &= ~SC_OP_ANI_RUN; | |
1421 | del_timer_sync(&common->ani.timer); | |
6c3118e2 | 1422 | } |
4801416c | 1423 | } |
6f255425 | 1424 | |
4801416c BG |
1425 | /* Called with sc->mutex held, vif counts set up properly. */ |
1426 | static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw, | |
1427 | struct ieee80211_vif *vif) | |
1428 | { | |
9ac58615 | 1429 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1430 | |
1431 | ath9k_calculate_summary_state(hw, vif); | |
1432 | ||
1433 | if (ath9k_uses_beacons(vif->type)) { | |
1434 | int error; | |
4801416c BG |
1435 | /* This may fail because upper levels do not have beacons |
1436 | * properly configured yet. That's OK, we assume it | |
1437 | * will be properly configured and then we will be notified | |
1438 | * in the info_changed method and set up beacons properly | |
1439 | * there. | |
1440 | */ | |
014cf3bb | 1441 | ath9k_set_beaconing_status(sc, false); |
9ac58615 | 1442 | error = ath_beacon_alloc(sc, vif); |
391bd1c4 | 1443 | if (!error) |
4801416c | 1444 | ath_beacon_config(sc, vif); |
014cf3bb | 1445 | ath9k_set_beaconing_status(sc, true); |
4801416c | 1446 | } |
f078f209 LR |
1447 | } |
1448 | ||
4801416c BG |
1449 | |
1450 | static int ath9k_add_interface(struct ieee80211_hw *hw, | |
1451 | struct ieee80211_vif *vif) | |
6b3b991d | 1452 | { |
9ac58615 | 1453 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1454 | struct ath_hw *ah = sc->sc_ah; |
1455 | struct ath_common *common = ath9k_hw_common(ah); | |
4801416c | 1456 | int ret = 0; |
6b3b991d | 1457 | |
96f372c9 | 1458 | ath9k_ps_wakeup(sc); |
4801416c | 1459 | mutex_lock(&sc->mutex); |
6b3b991d | 1460 | |
4801416c BG |
1461 | switch (vif->type) { |
1462 | case NL80211_IFTYPE_STATION: | |
1463 | case NL80211_IFTYPE_WDS: | |
1464 | case NL80211_IFTYPE_ADHOC: | |
1465 | case NL80211_IFTYPE_AP: | |
1466 | case NL80211_IFTYPE_MESH_POINT: | |
1467 | break; | |
1468 | default: | |
1469 | ath_err(common, "Interface type %d not yet supported\n", | |
1470 | vif->type); | |
1471 | ret = -EOPNOTSUPP; | |
1472 | goto out; | |
1473 | } | |
6b3b991d | 1474 | |
4801416c BG |
1475 | if (ath9k_uses_beacons(vif->type)) { |
1476 | if (sc->nbcnvifs >= ATH_BCBUF) { | |
1477 | ath_err(common, "Not enough beacon buffers when adding" | |
1478 | " new interface of type: %i\n", | |
1479 | vif->type); | |
1480 | ret = -ENOBUFS; | |
1481 | goto out; | |
1482 | } | |
1483 | } | |
1484 | ||
59575d1c RM |
1485 | if ((ah->opmode == NL80211_IFTYPE_ADHOC) || |
1486 | ((vif->type == NL80211_IFTYPE_ADHOC) && | |
1487 | sc->nvifs > 0)) { | |
4801416c BG |
1488 | ath_err(common, "Cannot create ADHOC interface when other" |
1489 | " interfaces already exist.\n"); | |
1490 | ret = -EINVAL; | |
1491 | goto out; | |
6b3b991d | 1492 | } |
4801416c BG |
1493 | |
1494 | ath_dbg(common, ATH_DBG_CONFIG, | |
1495 | "Attach a VIF of type: %d\n", vif->type); | |
1496 | ||
4801416c BG |
1497 | sc->nvifs++; |
1498 | ||
1499 | ath9k_do_vif_add_setup(hw, vif); | |
1500 | out: | |
1501 | mutex_unlock(&sc->mutex); | |
96f372c9 | 1502 | ath9k_ps_restore(sc); |
4801416c | 1503 | return ret; |
6b3b991d RM |
1504 | } |
1505 | ||
1506 | static int ath9k_change_interface(struct ieee80211_hw *hw, | |
1507 | struct ieee80211_vif *vif, | |
1508 | enum nl80211_iftype new_type, | |
1509 | bool p2p) | |
1510 | { | |
9ac58615 | 1511 | struct ath_softc *sc = hw->priv; |
6b3b991d | 1512 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
6dab55bf | 1513 | int ret = 0; |
6b3b991d RM |
1514 | |
1515 | ath_dbg(common, ATH_DBG_CONFIG, "Change Interface\n"); | |
1516 | mutex_lock(&sc->mutex); | |
96f372c9 | 1517 | ath9k_ps_wakeup(sc); |
6b3b991d | 1518 | |
4801416c BG |
1519 | /* See if new interface type is valid. */ |
1520 | if ((new_type == NL80211_IFTYPE_ADHOC) && | |
1521 | (sc->nvifs > 1)) { | |
1522 | ath_err(common, "When using ADHOC, it must be the only" | |
1523 | " interface.\n"); | |
1524 | ret = -EINVAL; | |
1525 | goto out; | |
1526 | } | |
1527 | ||
1528 | if (ath9k_uses_beacons(new_type) && | |
1529 | !ath9k_uses_beacons(vif->type)) { | |
6b3b991d RM |
1530 | if (sc->nbcnvifs >= ATH_BCBUF) { |
1531 | ath_err(common, "No beacon slot available\n"); | |
6dab55bf DC |
1532 | ret = -ENOBUFS; |
1533 | goto out; | |
6b3b991d | 1534 | } |
6b3b991d | 1535 | } |
4801416c BG |
1536 | |
1537 | /* Clean up old vif stuff */ | |
1538 | if (ath9k_uses_beacons(vif->type)) | |
1539 | ath9k_reclaim_beacon(sc, vif); | |
1540 | ||
1541 | /* Add new settings */ | |
6b3b991d RM |
1542 | vif->type = new_type; |
1543 | vif->p2p = p2p; | |
1544 | ||
4801416c | 1545 | ath9k_do_vif_add_setup(hw, vif); |
6dab55bf | 1546 | out: |
96f372c9 | 1547 | ath9k_ps_restore(sc); |
6b3b991d | 1548 | mutex_unlock(&sc->mutex); |
6dab55bf | 1549 | return ret; |
6b3b991d RM |
1550 | } |
1551 | ||
8feceb67 | 1552 | static void ath9k_remove_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1553 | struct ieee80211_vif *vif) |
f078f209 | 1554 | { |
9ac58615 | 1555 | struct ath_softc *sc = hw->priv; |
c46917bb | 1556 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
f078f209 | 1557 | |
226afe68 | 1558 | ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n"); |
f078f209 | 1559 | |
96f372c9 | 1560 | ath9k_ps_wakeup(sc); |
141b38b6 S |
1561 | mutex_lock(&sc->mutex); |
1562 | ||
4801416c | 1563 | sc->nvifs--; |
580f0b8a | 1564 | |
8feceb67 | 1565 | /* Reclaim beacon resources */ |
4801416c | 1566 | if (ath9k_uses_beacons(vif->type)) |
6b3b991d | 1567 | ath9k_reclaim_beacon(sc, vif); |
2c3db3d5 | 1568 | |
4801416c | 1569 | ath9k_calculate_summary_state(hw, NULL); |
141b38b6 S |
1570 | |
1571 | mutex_unlock(&sc->mutex); | |
96f372c9 | 1572 | ath9k_ps_restore(sc); |
f078f209 LR |
1573 | } |
1574 | ||
fbab7390 | 1575 | static void ath9k_enable_ps(struct ath_softc *sc) |
3f7c5c10 | 1576 | { |
3069168c PR |
1577 | struct ath_hw *ah = sc->sc_ah; |
1578 | ||
3f7c5c10 | 1579 | sc->ps_enabled = true; |
3069168c PR |
1580 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
1581 | if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { | |
1582 | ah->imask |= ATH9K_INT_TIM_TIMER; | |
1583 | ath9k_hw_set_interrupts(ah, ah->imask); | |
3f7c5c10 | 1584 | } |
fdf76622 | 1585 | ath9k_hw_setrxabort(ah, 1); |
3f7c5c10 | 1586 | } |
3f7c5c10 SB |
1587 | } |
1588 | ||
845d708e SB |
1589 | static void ath9k_disable_ps(struct ath_softc *sc) |
1590 | { | |
1591 | struct ath_hw *ah = sc->sc_ah; | |
1592 | ||
1593 | sc->ps_enabled = false; | |
1594 | ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); | |
1595 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { | |
1596 | ath9k_hw_setrxabort(ah, 0); | |
1597 | sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | | |
1598 | PS_WAIT_FOR_CAB | | |
1599 | PS_WAIT_FOR_PSPOLL_DATA | | |
1600 | PS_WAIT_FOR_TX_ACK); | |
1601 | if (ah->imask & ATH9K_INT_TIM_TIMER) { | |
1602 | ah->imask &= ~ATH9K_INT_TIM_TIMER; | |
1603 | ath9k_hw_set_interrupts(ah, ah->imask); | |
1604 | } | |
1605 | } | |
1606 | ||
1607 | } | |
1608 | ||
e8975581 | 1609 | static int ath9k_config(struct ieee80211_hw *hw, u32 changed) |
f078f209 | 1610 | { |
9ac58615 | 1611 | struct ath_softc *sc = hw->priv; |
3430098a FF |
1612 | struct ath_hw *ah = sc->sc_ah; |
1613 | struct ath_common *common = ath9k_hw_common(ah); | |
e8975581 | 1614 | struct ieee80211_conf *conf = &hw->conf; |
7545daf4 | 1615 | bool disable_radio = false; |
f078f209 | 1616 | |
aa33de09 | 1617 | mutex_lock(&sc->mutex); |
141b38b6 | 1618 | |
194b7c13 LR |
1619 | /* |
1620 | * Leave this as the first check because we need to turn on the | |
1621 | * radio if it was disabled before prior to processing the rest | |
1622 | * of the changes. Likewise we must only disable the radio towards | |
1623 | * the end. | |
1624 | */ | |
64839170 | 1625 | if (changed & IEEE80211_CONF_CHANGE_IDLE) { |
7545daf4 FF |
1626 | sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); |
1627 | if (!sc->ps_idle) { | |
68a89116 | 1628 | ath_radio_enable(sc, hw); |
226afe68 JP |
1629 | ath_dbg(common, ATH_DBG_CONFIG, |
1630 | "not-idle: enabling radio\n"); | |
7545daf4 FF |
1631 | } else { |
1632 | disable_radio = true; | |
64839170 LR |
1633 | } |
1634 | } | |
1635 | ||
e7824a50 LR |
1636 | /* |
1637 | * We just prepare to enable PS. We have to wait until our AP has | |
1638 | * ACK'd our null data frame to disable RX otherwise we'll ignore | |
1639 | * those ACKs and end up retransmitting the same null data frames. | |
1640 | * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. | |
1641 | */ | |
3cbb5dd7 | 1642 | if (changed & IEEE80211_CONF_CHANGE_PS) { |
8ab2cd09 LR |
1643 | unsigned long flags; |
1644 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
fbab7390 SB |
1645 | if (conf->flags & IEEE80211_CONF_PS) |
1646 | ath9k_enable_ps(sc); | |
845d708e SB |
1647 | else |
1648 | ath9k_disable_ps(sc); | |
8ab2cd09 | 1649 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
3cbb5dd7 VN |
1650 | } |
1651 | ||
199afd9d S |
1652 | if (changed & IEEE80211_CONF_CHANGE_MONITOR) { |
1653 | if (conf->flags & IEEE80211_CONF_MONITOR) { | |
226afe68 JP |
1654 | ath_dbg(common, ATH_DBG_CONFIG, |
1655 | "Monitor mode is enabled\n"); | |
5f841b41 RM |
1656 | sc->sc_ah->is_monitoring = true; |
1657 | } else { | |
226afe68 JP |
1658 | ath_dbg(common, ATH_DBG_CONFIG, |
1659 | "Monitor mode is disabled\n"); | |
5f841b41 | 1660 | sc->sc_ah->is_monitoring = false; |
199afd9d S |
1661 | } |
1662 | } | |
1663 | ||
4797938c | 1664 | if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { |
99405f93 | 1665 | struct ieee80211_channel *curchan = hw->conf.channel; |
5f8e077c | 1666 | int pos = curchan->hw_value; |
3430098a FF |
1667 | int old_pos = -1; |
1668 | unsigned long flags; | |
1669 | ||
1670 | if (ah->curchan) | |
1671 | old_pos = ah->curchan - &ah->channels[0]; | |
ae5eb026 | 1672 | |
5ee08656 FF |
1673 | if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) |
1674 | sc->sc_flags |= SC_OP_OFFCHANNEL; | |
1675 | else | |
1676 | sc->sc_flags &= ~SC_OP_OFFCHANNEL; | |
0e2dedf9 | 1677 | |
8c79a610 BG |
1678 | ath_dbg(common, ATH_DBG_CONFIG, |
1679 | "Set channel: %d MHz type: %d\n", | |
1680 | curchan->center_freq, conf->channel_type); | |
f078f209 | 1681 | |
de87f736 RM |
1682 | ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos], |
1683 | curchan, conf->channel_type); | |
e11602b7 | 1684 | |
3430098a FF |
1685 | /* update survey stats for the old channel before switching */ |
1686 | spin_lock_irqsave(&common->cc_lock, flags); | |
1687 | ath_update_survey_stats(sc); | |
1688 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
1689 | ||
1690 | /* | |
1691 | * If the operating channel changes, change the survey in-use flags | |
1692 | * along with it. | |
1693 | * Reset the survey data for the new channel, unless we're switching | |
1694 | * back to the operating channel from an off-channel operation. | |
1695 | */ | |
1696 | if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && | |
1697 | sc->cur_survey != &sc->survey[pos]) { | |
1698 | ||
1699 | if (sc->cur_survey) | |
1700 | sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE; | |
1701 | ||
1702 | sc->cur_survey = &sc->survey[pos]; | |
1703 | ||
1704 | memset(sc->cur_survey, 0, sizeof(struct survey_info)); | |
1705 | sc->cur_survey->filled |= SURVEY_INFO_IN_USE; | |
1706 | } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) { | |
1707 | memset(&sc->survey[pos], 0, sizeof(struct survey_info)); | |
1708 | } | |
1709 | ||
0e2dedf9 | 1710 | if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { |
3800276a | 1711 | ath_err(common, "Unable to set channel\n"); |
aa33de09 | 1712 | mutex_unlock(&sc->mutex); |
e11602b7 S |
1713 | return -EINVAL; |
1714 | } | |
3430098a FF |
1715 | |
1716 | /* | |
1717 | * The most recent snapshot of channel->noisefloor for the old | |
1718 | * channel is only available after the hardware reset. Copy it to | |
1719 | * the survey stats now. | |
1720 | */ | |
1721 | if (old_pos >= 0) | |
1722 | ath_update_survey_nf(sc, old_pos); | |
094d05dc | 1723 | } |
f078f209 | 1724 | |
c9f6a656 | 1725 | if (changed & IEEE80211_CONF_CHANGE_POWER) { |
603b3eef BG |
1726 | ath_dbg(common, ATH_DBG_CONFIG, |
1727 | "Set power: %d\n", conf->power_level); | |
17d7904d | 1728 | sc->config.txpowlimit = 2 * conf->power_level; |
783cd01e | 1729 | ath9k_ps_wakeup(sc); |
5048e8c3 RM |
1730 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
1731 | sc->config.txpowlimit, &sc->curtxpow); | |
783cd01e | 1732 | ath9k_ps_restore(sc); |
c9f6a656 | 1733 | } |
f078f209 | 1734 | |
64839170 | 1735 | if (disable_radio) { |
226afe68 | 1736 | ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n"); |
68a89116 | 1737 | ath_radio_disable(sc, hw); |
64839170 LR |
1738 | } |
1739 | ||
aa33de09 | 1740 | mutex_unlock(&sc->mutex); |
141b38b6 | 1741 | |
f078f209 LR |
1742 | return 0; |
1743 | } | |
1744 | ||
8feceb67 VT |
1745 | #define SUPPORTED_FILTERS \ |
1746 | (FIF_PROMISC_IN_BSS | \ | |
1747 | FIF_ALLMULTI | \ | |
1748 | FIF_CONTROL | \ | |
af6a3fc7 | 1749 | FIF_PSPOLL | \ |
8feceb67 VT |
1750 | FIF_OTHER_BSS | \ |
1751 | FIF_BCN_PRBRESP_PROMISC | \ | |
9c1d8e4a | 1752 | FIF_PROBE_REQ | \ |
8feceb67 | 1753 | FIF_FCSFAIL) |
c83be688 | 1754 | |
8feceb67 VT |
1755 | /* FIXME: sc->sc_full_reset ? */ |
1756 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | |
1757 | unsigned int changed_flags, | |
1758 | unsigned int *total_flags, | |
3ac64bee | 1759 | u64 multicast) |
8feceb67 | 1760 | { |
9ac58615 | 1761 | struct ath_softc *sc = hw->priv; |
8feceb67 | 1762 | u32 rfilt; |
f078f209 | 1763 | |
8feceb67 VT |
1764 | changed_flags &= SUPPORTED_FILTERS; |
1765 | *total_flags &= SUPPORTED_FILTERS; | |
f078f209 | 1766 | |
b77f483f | 1767 | sc->rx.rxfilter = *total_flags; |
aa68aeaa | 1768 | ath9k_ps_wakeup(sc); |
8feceb67 VT |
1769 | rfilt = ath_calcrxfilter(sc); |
1770 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | |
aa68aeaa | 1771 | ath9k_ps_restore(sc); |
f078f209 | 1772 | |
226afe68 JP |
1773 | ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG, |
1774 | "Set HW RX filter: 0x%x\n", rfilt); | |
8feceb67 | 1775 | } |
f078f209 | 1776 | |
4ca77860 JB |
1777 | static int ath9k_sta_add(struct ieee80211_hw *hw, |
1778 | struct ieee80211_vif *vif, | |
1779 | struct ieee80211_sta *sta) | |
8feceb67 | 1780 | { |
9ac58615 | 1781 | struct ath_softc *sc = hw->priv; |
93ae2dd2 FF |
1782 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
1783 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1784 | struct ieee80211_key_conf ps_key = { }; | |
f078f209 | 1785 | |
4ca77860 | 1786 | ath_node_attach(sc, sta); |
f59a59fe FF |
1787 | |
1788 | if (vif->type != NL80211_IFTYPE_AP && | |
1789 | vif->type != NL80211_IFTYPE_AP_VLAN) | |
1790 | return 0; | |
1791 | ||
93ae2dd2 | 1792 | an->ps_key = ath_key_config(common, vif, sta, &ps_key); |
4ca77860 JB |
1793 | |
1794 | return 0; | |
1795 | } | |
1796 | ||
93ae2dd2 FF |
1797 | static void ath9k_del_ps_key(struct ath_softc *sc, |
1798 | struct ieee80211_vif *vif, | |
1799 | struct ieee80211_sta *sta) | |
1800 | { | |
1801 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
1802 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1803 | struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key }; | |
1804 | ||
1805 | if (!an->ps_key) | |
1806 | return; | |
1807 | ||
1808 | ath_key_delete(common, &ps_key); | |
1809 | } | |
1810 | ||
4ca77860 JB |
1811 | static int ath9k_sta_remove(struct ieee80211_hw *hw, |
1812 | struct ieee80211_vif *vif, | |
1813 | struct ieee80211_sta *sta) | |
1814 | { | |
9ac58615 | 1815 | struct ath_softc *sc = hw->priv; |
4ca77860 | 1816 | |
93ae2dd2 | 1817 | ath9k_del_ps_key(sc, vif, sta); |
4ca77860 JB |
1818 | ath_node_detach(sc, sta); |
1819 | ||
1820 | return 0; | |
f078f209 LR |
1821 | } |
1822 | ||
5519541d FF |
1823 | static void ath9k_sta_notify(struct ieee80211_hw *hw, |
1824 | struct ieee80211_vif *vif, | |
1825 | enum sta_notify_cmd cmd, | |
1826 | struct ieee80211_sta *sta) | |
1827 | { | |
1828 | struct ath_softc *sc = hw->priv; | |
1829 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1830 | ||
1831 | switch (cmd) { | |
1832 | case STA_NOTIFY_SLEEP: | |
1833 | an->sleeping = true; | |
1834 | if (ath_tx_aggr_sleep(sc, an)) | |
1835 | ieee80211_sta_set_tim(sta); | |
1836 | break; | |
1837 | case STA_NOTIFY_AWAKE: | |
1838 | an->sleeping = false; | |
1839 | ath_tx_aggr_wakeup(sc, an); | |
1840 | break; | |
1841 | } | |
1842 | } | |
1843 | ||
141b38b6 | 1844 | static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue, |
8feceb67 | 1845 | const struct ieee80211_tx_queue_params *params) |
f078f209 | 1846 | { |
9ac58615 | 1847 | struct ath_softc *sc = hw->priv; |
c46917bb | 1848 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
066dae93 | 1849 | struct ath_txq *txq; |
8feceb67 | 1850 | struct ath9k_tx_queue_info qi; |
066dae93 | 1851 | int ret = 0; |
f078f209 | 1852 | |
8feceb67 VT |
1853 | if (queue >= WME_NUM_AC) |
1854 | return 0; | |
f078f209 | 1855 | |
066dae93 FF |
1856 | txq = sc->tx.txq_map[queue]; |
1857 | ||
96f372c9 | 1858 | ath9k_ps_wakeup(sc); |
141b38b6 S |
1859 | mutex_lock(&sc->mutex); |
1860 | ||
1ffb0610 S |
1861 | memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); |
1862 | ||
8feceb67 VT |
1863 | qi.tqi_aifs = params->aifs; |
1864 | qi.tqi_cwmin = params->cw_min; | |
1865 | qi.tqi_cwmax = params->cw_max; | |
1866 | qi.tqi_burstTime = params->txop; | |
f078f209 | 1867 | |
226afe68 JP |
1868 | ath_dbg(common, ATH_DBG_CONFIG, |
1869 | "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", | |
1870 | queue, txq->axq_qnum, params->aifs, params->cw_min, | |
1871 | params->cw_max, params->txop); | |
f078f209 | 1872 | |
066dae93 | 1873 | ret = ath_txq_update(sc, txq->axq_qnum, &qi); |
8feceb67 | 1874 | if (ret) |
3800276a | 1875 | ath_err(common, "TXQ Update failed\n"); |
f078f209 | 1876 | |
94db2936 | 1877 | if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) |
066dae93 | 1878 | if (queue == WME_AC_BE && !ret) |
94db2936 VN |
1879 | ath_beaconq_config(sc); |
1880 | ||
141b38b6 | 1881 | mutex_unlock(&sc->mutex); |
96f372c9 | 1882 | ath9k_ps_restore(sc); |
141b38b6 | 1883 | |
8feceb67 VT |
1884 | return ret; |
1885 | } | |
f078f209 | 1886 | |
8feceb67 VT |
1887 | static int ath9k_set_key(struct ieee80211_hw *hw, |
1888 | enum set_key_cmd cmd, | |
dc822b5d JB |
1889 | struct ieee80211_vif *vif, |
1890 | struct ieee80211_sta *sta, | |
8feceb67 VT |
1891 | struct ieee80211_key_conf *key) |
1892 | { | |
9ac58615 | 1893 | struct ath_softc *sc = hw->priv; |
c46917bb | 1894 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 | 1895 | int ret = 0; |
f078f209 | 1896 | |
3e6109c5 | 1897 | if (ath9k_modparam_nohwcrypt) |
b3bd89ce JM |
1898 | return -ENOSPC; |
1899 | ||
cfdc9a8b JM |
1900 | if (vif->type == NL80211_IFTYPE_ADHOC && |
1901 | (key->cipher == WLAN_CIPHER_SUITE_TKIP || | |
1902 | key->cipher == WLAN_CIPHER_SUITE_CCMP) && | |
1903 | !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { | |
1904 | /* | |
1905 | * For now, disable hw crypto for the RSN IBSS group keys. This | |
1906 | * could be optimized in the future to use a modified key cache | |
1907 | * design to support per-STA RX GTK, but until that gets | |
1908 | * implemented, use of software crypto for group addressed | |
1909 | * frames is a acceptable to allow RSN IBSS to be used. | |
1910 | */ | |
1911 | return -EOPNOTSUPP; | |
1912 | } | |
1913 | ||
141b38b6 | 1914 | mutex_lock(&sc->mutex); |
3cbb5dd7 | 1915 | ath9k_ps_wakeup(sc); |
226afe68 | 1916 | ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n"); |
f078f209 | 1917 | |
8feceb67 VT |
1918 | switch (cmd) { |
1919 | case SET_KEY: | |
93ae2dd2 FF |
1920 | if (sta) |
1921 | ath9k_del_ps_key(sc, vif, sta); | |
1922 | ||
040e539e | 1923 | ret = ath_key_config(common, vif, sta, key); |
6ace2891 JM |
1924 | if (ret >= 0) { |
1925 | key->hw_key_idx = ret; | |
8feceb67 VT |
1926 | /* push IV and Michael MIC generation to stack */ |
1927 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
97359d12 | 1928 | if (key->cipher == WLAN_CIPHER_SUITE_TKIP) |
8feceb67 | 1929 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; |
97359d12 JB |
1930 | if (sc->sc_ah->sw_mgmt_crypto && |
1931 | key->cipher == WLAN_CIPHER_SUITE_CCMP) | |
0ced0e17 | 1932 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT; |
6ace2891 | 1933 | ret = 0; |
8feceb67 VT |
1934 | } |
1935 | break; | |
1936 | case DISABLE_KEY: | |
040e539e | 1937 | ath_key_delete(common, key); |
8feceb67 VT |
1938 | break; |
1939 | default: | |
1940 | ret = -EINVAL; | |
1941 | } | |
f078f209 | 1942 | |
3cbb5dd7 | 1943 | ath9k_ps_restore(sc); |
141b38b6 S |
1944 | mutex_unlock(&sc->mutex); |
1945 | ||
8feceb67 VT |
1946 | return ret; |
1947 | } | |
4f5ef75b RM |
1948 | static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif) |
1949 | { | |
1950 | struct ath_softc *sc = data; | |
1951 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
1952 | struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; | |
1953 | struct ath_vif *avp = (void *)vif->drv_priv; | |
1954 | ||
1955 | switch (sc->sc_ah->opmode) { | |
1956 | case NL80211_IFTYPE_ADHOC: | |
1957 | /* There can be only one vif available */ | |
1958 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); | |
1959 | common->curaid = bss_conf->aid; | |
1960 | ath9k_hw_write_associd(sc->sc_ah); | |
99e4d43a RM |
1961 | /* configure beacon */ |
1962 | if (bss_conf->enable_beacon) | |
1963 | ath_beacon_config(sc, vif); | |
4f5ef75b RM |
1964 | break; |
1965 | case NL80211_IFTYPE_STATION: | |
1966 | /* | |
1967 | * Skip iteration if primary station vif's bss info | |
1968 | * was not changed | |
1969 | */ | |
1970 | if (sc->sc_flags & SC_OP_PRIM_STA_VIF) | |
1971 | break; | |
1972 | ||
1973 | if (bss_conf->assoc) { | |
1974 | sc->sc_flags |= SC_OP_PRIM_STA_VIF; | |
1975 | avp->primary_sta_vif = true; | |
1976 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); | |
1977 | common->curaid = bss_conf->aid; | |
1978 | ath9k_hw_write_associd(sc->sc_ah); | |
99e4d43a RM |
1979 | ath_dbg(common, ATH_DBG_CONFIG, |
1980 | "Bss Info ASSOC %d, bssid: %pM\n", | |
1981 | bss_conf->aid, common->curbssid); | |
1982 | ath_beacon_config(sc, vif); | |
92c6f76c RM |
1983 | /* |
1984 | * Request a re-configuration of Beacon related timers | |
1985 | * on the receipt of the first Beacon frame (i.e., | |
1986 | * after time sync with the AP). | |
1987 | */ | |
1988 | sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; | |
99e4d43a RM |
1989 | /* Reset rssi stats */ |
1990 | sc->last_rssi = ATH_RSSI_DUMMY_MARKER; | |
1991 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; | |
1992 | ||
1993 | sc->sc_flags |= SC_OP_ANI_RUN; | |
1994 | ath_start_ani(common); | |
4f5ef75b RM |
1995 | } |
1996 | break; | |
1997 | default: | |
1998 | break; | |
1999 | } | |
2000 | } | |
2001 | ||
2002 | static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif) | |
2003 | { | |
2004 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
2005 | struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; | |
2006 | struct ath_vif *avp = (void *)vif->drv_priv; | |
2007 | ||
2008 | /* Reconfigure bss info */ | |
2009 | if (avp->primary_sta_vif && !bss_conf->assoc) { | |
99e4d43a RM |
2010 | ath_dbg(common, ATH_DBG_CONFIG, |
2011 | "Bss Info DISASSOC %d, bssid %pM\n", | |
2012 | common->curaid, common->curbssid); | |
2013 | sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS); | |
4f5ef75b RM |
2014 | avp->primary_sta_vif = false; |
2015 | memset(common->curbssid, 0, ETH_ALEN); | |
2016 | common->curaid = 0; | |
2017 | } | |
2018 | ||
2019 | ieee80211_iterate_active_interfaces_atomic( | |
2020 | sc->hw, ath9k_bss_iter, sc); | |
2021 | ||
2022 | /* | |
2023 | * None of station vifs are associated. | |
2024 | * Clear bssid & aid | |
2025 | */ | |
2026 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) && | |
99e4d43a | 2027 | !(sc->sc_flags & SC_OP_PRIM_STA_VIF)) { |
4f5ef75b | 2028 | ath9k_hw_write_associd(sc->sc_ah); |
99e4d43a RM |
2029 | /* Stop ANI */ |
2030 | sc->sc_flags &= ~SC_OP_ANI_RUN; | |
2031 | del_timer_sync(&common->ani.timer); | |
2032 | } | |
4f5ef75b | 2033 | } |
f078f209 | 2034 | |
8feceb67 VT |
2035 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, |
2036 | struct ieee80211_vif *vif, | |
2037 | struct ieee80211_bss_conf *bss_conf, | |
2038 | u32 changed) | |
2039 | { | |
9ac58615 | 2040 | struct ath_softc *sc = hw->priv; |
2d0ddec5 | 2041 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 2042 | struct ath_common *common = ath9k_hw_common(ah); |
2d0ddec5 | 2043 | struct ath_vif *avp = (void *)vif->drv_priv; |
0005baf4 | 2044 | int slottime; |
c6089ccc | 2045 | int error; |
f078f209 | 2046 | |
96f372c9 | 2047 | ath9k_ps_wakeup(sc); |
141b38b6 S |
2048 | mutex_lock(&sc->mutex); |
2049 | ||
c6089ccc | 2050 | if (changed & BSS_CHANGED_BSSID) { |
4f5ef75b | 2051 | ath9k_config_bss(sc, vif); |
2d0ddec5 | 2052 | |
226afe68 JP |
2053 | ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n", |
2054 | common->curbssid, common->curaid); | |
c6089ccc | 2055 | } |
2d0ddec5 | 2056 | |
c6089ccc S |
2057 | /* Enable transmission of beacons (AP, IBSS, MESH) */ |
2058 | if ((changed & BSS_CHANGED_BEACON) || | |
2059 | ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) { | |
014cf3bb | 2060 | ath9k_set_beaconing_status(sc, false); |
9ac58615 | 2061 | error = ath_beacon_alloc(sc, vif); |
c6089ccc S |
2062 | if (!error) |
2063 | ath_beacon_config(sc, vif); | |
014cf3bb | 2064 | ath9k_set_beaconing_status(sc, true); |
0005baf4 FF |
2065 | } |
2066 | ||
2067 | if (changed & BSS_CHANGED_ERP_SLOT) { | |
2068 | if (bss_conf->use_short_slot) | |
2069 | slottime = 9; | |
2070 | else | |
2071 | slottime = 20; | |
2072 | if (vif->type == NL80211_IFTYPE_AP) { | |
2073 | /* | |
2074 | * Defer update, so that connected stations can adjust | |
2075 | * their settings at the same time. | |
2076 | * See beacon.c for more details | |
2077 | */ | |
2078 | sc->beacon.slottime = slottime; | |
2079 | sc->beacon.updateslot = UPDATE; | |
2080 | } else { | |
2081 | ah->slottime = slottime; | |
2082 | ath9k_hw_init_global_settings(ah); | |
2083 | } | |
2d0ddec5 JB |
2084 | } |
2085 | ||
c6089ccc | 2086 | /* Disable transmission of beacons */ |
014cf3bb RM |
2087 | if ((changed & BSS_CHANGED_BEACON_ENABLED) && |
2088 | !bss_conf->enable_beacon) { | |
2089 | ath9k_set_beaconing_status(sc, false); | |
2090 | avp->is_bslot_active = false; | |
2091 | ath9k_set_beaconing_status(sc, true); | |
2092 | } | |
2d0ddec5 | 2093 | |
c6089ccc | 2094 | if (changed & BSS_CHANGED_BEACON_INT) { |
c6089ccc S |
2095 | /* |
2096 | * In case of AP mode, the HW TSF has to be reset | |
2097 | * when the beacon interval changes. | |
2098 | */ | |
2099 | if (vif->type == NL80211_IFTYPE_AP) { | |
2100 | sc->sc_flags |= SC_OP_TSF_RESET; | |
014cf3bb | 2101 | ath9k_set_beaconing_status(sc, false); |
9ac58615 | 2102 | error = ath_beacon_alloc(sc, vif); |
2d0ddec5 JB |
2103 | if (!error) |
2104 | ath_beacon_config(sc, vif); | |
014cf3bb | 2105 | ath9k_set_beaconing_status(sc, true); |
99e4d43a | 2106 | } else |
c6089ccc | 2107 | ath_beacon_config(sc, vif); |
2d0ddec5 JB |
2108 | } |
2109 | ||
8feceb67 | 2110 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
226afe68 JP |
2111 | ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", |
2112 | bss_conf->use_short_preamble); | |
8feceb67 VT |
2113 | if (bss_conf->use_short_preamble) |
2114 | sc->sc_flags |= SC_OP_PREAMBLE_SHORT; | |
2115 | else | |
2116 | sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT; | |
2117 | } | |
f078f209 | 2118 | |
8feceb67 | 2119 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { |
226afe68 JP |
2120 | ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", |
2121 | bss_conf->use_cts_prot); | |
8feceb67 VT |
2122 | if (bss_conf->use_cts_prot && |
2123 | hw->conf.channel->band != IEEE80211_BAND_5GHZ) | |
2124 | sc->sc_flags |= SC_OP_PROTECT_ENABLE; | |
2125 | else | |
2126 | sc->sc_flags &= ~SC_OP_PROTECT_ENABLE; | |
2127 | } | |
f078f209 | 2128 | |
141b38b6 | 2129 | mutex_unlock(&sc->mutex); |
96f372c9 | 2130 | ath9k_ps_restore(sc); |
8feceb67 | 2131 | } |
f078f209 | 2132 | |
8feceb67 VT |
2133 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw) |
2134 | { | |
9ac58615 | 2135 | struct ath_softc *sc = hw->priv; |
8feceb67 | 2136 | u64 tsf; |
f078f209 | 2137 | |
141b38b6 | 2138 | mutex_lock(&sc->mutex); |
9abbfb27 | 2139 | ath9k_ps_wakeup(sc); |
141b38b6 | 2140 | tsf = ath9k_hw_gettsf64(sc->sc_ah); |
9abbfb27 | 2141 | ath9k_ps_restore(sc); |
141b38b6 | 2142 | mutex_unlock(&sc->mutex); |
f078f209 | 2143 | |
8feceb67 VT |
2144 | return tsf; |
2145 | } | |
f078f209 | 2146 | |
3b5d665b AF |
2147 | static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf) |
2148 | { | |
9ac58615 | 2149 | struct ath_softc *sc = hw->priv; |
3b5d665b | 2150 | |
141b38b6 | 2151 | mutex_lock(&sc->mutex); |
9abbfb27 | 2152 | ath9k_ps_wakeup(sc); |
141b38b6 | 2153 | ath9k_hw_settsf64(sc->sc_ah, tsf); |
9abbfb27 | 2154 | ath9k_ps_restore(sc); |
141b38b6 | 2155 | mutex_unlock(&sc->mutex); |
3b5d665b AF |
2156 | } |
2157 | ||
8feceb67 VT |
2158 | static void ath9k_reset_tsf(struct ieee80211_hw *hw) |
2159 | { | |
9ac58615 | 2160 | struct ath_softc *sc = hw->priv; |
c83be688 | 2161 | |
141b38b6 | 2162 | mutex_lock(&sc->mutex); |
21526d57 LR |
2163 | |
2164 | ath9k_ps_wakeup(sc); | |
141b38b6 | 2165 | ath9k_hw_reset_tsf(sc->sc_ah); |
21526d57 LR |
2166 | ath9k_ps_restore(sc); |
2167 | ||
141b38b6 | 2168 | mutex_unlock(&sc->mutex); |
8feceb67 | 2169 | } |
f078f209 | 2170 | |
8feceb67 | 2171 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, |
c951ad35 | 2172 | struct ieee80211_vif *vif, |
141b38b6 S |
2173 | enum ieee80211_ampdu_mlme_action action, |
2174 | struct ieee80211_sta *sta, | |
0b01f030 | 2175 | u16 tid, u16 *ssn, u8 buf_size) |
8feceb67 | 2176 | { |
9ac58615 | 2177 | struct ath_softc *sc = hw->priv; |
8feceb67 | 2178 | int ret = 0; |
f078f209 | 2179 | |
85ad181e JB |
2180 | local_bh_disable(); |
2181 | ||
8feceb67 VT |
2182 | switch (action) { |
2183 | case IEEE80211_AMPDU_RX_START: | |
dca3edb8 S |
2184 | if (!(sc->sc_flags & SC_OP_RXAGGR)) |
2185 | ret = -ENOTSUPP; | |
8feceb67 VT |
2186 | break; |
2187 | case IEEE80211_AMPDU_RX_STOP: | |
8feceb67 VT |
2188 | break; |
2189 | case IEEE80211_AMPDU_TX_START: | |
71a3bf3e FF |
2190 | if (!(sc->sc_flags & SC_OP_TXAGGR)) |
2191 | return -EOPNOTSUPP; | |
2192 | ||
8b685ba9 | 2193 | ath9k_ps_wakeup(sc); |
231c3a1f FF |
2194 | ret = ath_tx_aggr_start(sc, sta, tid, ssn); |
2195 | if (!ret) | |
2196 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); | |
8b685ba9 | 2197 | ath9k_ps_restore(sc); |
8feceb67 VT |
2198 | break; |
2199 | case IEEE80211_AMPDU_TX_STOP: | |
8b685ba9 | 2200 | ath9k_ps_wakeup(sc); |
f83da965 | 2201 | ath_tx_aggr_stop(sc, sta, tid); |
c951ad35 | 2202 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 2203 | ath9k_ps_restore(sc); |
8feceb67 | 2204 | break; |
b1720231 | 2205 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
8b685ba9 | 2206 | ath9k_ps_wakeup(sc); |
8469cdef | 2207 | ath_tx_aggr_resume(sc, sta, tid); |
8b685ba9 | 2208 | ath9k_ps_restore(sc); |
8469cdef | 2209 | break; |
8feceb67 | 2210 | default: |
3800276a | 2211 | ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); |
8feceb67 VT |
2212 | } |
2213 | ||
85ad181e JB |
2214 | local_bh_enable(); |
2215 | ||
8feceb67 | 2216 | return ret; |
f078f209 LR |
2217 | } |
2218 | ||
62dad5b0 BP |
2219 | static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, |
2220 | struct survey_info *survey) | |
2221 | { | |
9ac58615 | 2222 | struct ath_softc *sc = hw->priv; |
3430098a | 2223 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39162dbe | 2224 | struct ieee80211_supported_band *sband; |
3430098a FF |
2225 | struct ieee80211_channel *chan; |
2226 | unsigned long flags; | |
2227 | int pos; | |
2228 | ||
2229 | spin_lock_irqsave(&common->cc_lock, flags); | |
2230 | if (idx == 0) | |
2231 | ath_update_survey_stats(sc); | |
39162dbe FF |
2232 | |
2233 | sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; | |
2234 | if (sband && idx >= sband->n_channels) { | |
2235 | idx -= sband->n_channels; | |
2236 | sband = NULL; | |
2237 | } | |
62dad5b0 | 2238 | |
39162dbe FF |
2239 | if (!sband) |
2240 | sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; | |
62dad5b0 | 2241 | |
3430098a FF |
2242 | if (!sband || idx >= sband->n_channels) { |
2243 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
2244 | return -ENOENT; | |
4f1a5a4b | 2245 | } |
62dad5b0 | 2246 | |
3430098a FF |
2247 | chan = &sband->channels[idx]; |
2248 | pos = chan->hw_value; | |
2249 | memcpy(survey, &sc->survey[pos], sizeof(*survey)); | |
2250 | survey->channel = chan; | |
2251 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
2252 | ||
62dad5b0 BP |
2253 | return 0; |
2254 | } | |
2255 | ||
e239d859 FF |
2256 | static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) |
2257 | { | |
9ac58615 | 2258 | struct ath_softc *sc = hw->priv; |
e239d859 FF |
2259 | struct ath_hw *ah = sc->sc_ah; |
2260 | ||
2261 | mutex_lock(&sc->mutex); | |
2262 | ah->coverage_class = coverage_class; | |
2263 | ath9k_hw_init_global_settings(ah); | |
2264 | mutex_unlock(&sc->mutex); | |
2265 | } | |
2266 | ||
69081624 VT |
2267 | static void ath9k_flush(struct ieee80211_hw *hw, bool drop) |
2268 | { | |
69081624 | 2269 | struct ath_softc *sc = hw->priv; |
99aa55b6 MSS |
2270 | struct ath_hw *ah = sc->sc_ah; |
2271 | struct ath_common *common = ath9k_hw_common(ah); | |
86271e46 FF |
2272 | int timeout = 200; /* ms */ |
2273 | int i, j; | |
2f6fc351 | 2274 | bool drain_txq; |
69081624 VT |
2275 | |
2276 | mutex_lock(&sc->mutex); | |
69081624 VT |
2277 | cancel_delayed_work_sync(&sc->tx_complete_work); |
2278 | ||
99aa55b6 MSS |
2279 | if (sc->sc_flags & SC_OP_INVALID) { |
2280 | ath_dbg(common, ATH_DBG_ANY, "Device not present\n"); | |
2281 | mutex_unlock(&sc->mutex); | |
2282 | return; | |
2283 | } | |
2284 | ||
86271e46 FF |
2285 | if (drop) |
2286 | timeout = 1; | |
69081624 | 2287 | |
86271e46 | 2288 | for (j = 0; j < timeout; j++) { |
108697c4 | 2289 | bool npend = false; |
86271e46 FF |
2290 | |
2291 | if (j) | |
2292 | usleep_range(1000, 2000); | |
69081624 | 2293 | |
86271e46 FF |
2294 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
2295 | if (!ATH_TXQ_SETUP(sc, i)) | |
2296 | continue; | |
2297 | ||
108697c4 MSS |
2298 | npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]); |
2299 | ||
2300 | if (npend) | |
2301 | break; | |
69081624 | 2302 | } |
86271e46 FF |
2303 | |
2304 | if (!npend) | |
2305 | goto out; | |
69081624 VT |
2306 | } |
2307 | ||
51513906 | 2308 | ath9k_ps_wakeup(sc); |
2f6fc351 RM |
2309 | spin_lock_bh(&sc->sc_pcu_lock); |
2310 | drain_txq = ath_drain_all_txq(sc, false); | |
2311 | spin_unlock_bh(&sc->sc_pcu_lock); | |
2312 | if (!drain_txq) | |
69081624 | 2313 | ath_reset(sc, false); |
51513906 | 2314 | ath9k_ps_restore(sc); |
d78f4b3e SB |
2315 | ieee80211_wake_queues(hw); |
2316 | ||
86271e46 | 2317 | out: |
69081624 VT |
2318 | ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0); |
2319 | mutex_unlock(&sc->mutex); | |
2320 | } | |
2321 | ||
15b91e83 VN |
2322 | static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) |
2323 | { | |
2324 | struct ath_softc *sc = hw->priv; | |
2325 | int i; | |
2326 | ||
2327 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
2328 | if (!ATH_TXQ_SETUP(sc, i)) | |
2329 | continue; | |
2330 | ||
2331 | if (ath9k_has_pending_frames(sc, &sc->tx.txq[i])) | |
2332 | return true; | |
2333 | } | |
2334 | return false; | |
2335 | } | |
2336 | ||
ba4903f9 FF |
2337 | int ath9k_tx_last_beacon(struct ieee80211_hw *hw) |
2338 | { | |
2339 | struct ath_softc *sc = hw->priv; | |
2340 | struct ath_hw *ah = sc->sc_ah; | |
2341 | struct ieee80211_vif *vif; | |
2342 | struct ath_vif *avp; | |
2343 | struct ath_buf *bf; | |
2344 | struct ath_tx_status ts; | |
2345 | int status; | |
2346 | ||
2347 | vif = sc->beacon.bslot[0]; | |
2348 | if (!vif) | |
2349 | return 0; | |
2350 | ||
2351 | avp = (void *)vif->drv_priv; | |
2352 | if (!avp->is_bslot_active) | |
2353 | return 0; | |
2354 | ||
2355 | if (!sc->beacon.tx_processed) { | |
2356 | tasklet_disable(&sc->bcon_tasklet); | |
2357 | ||
2358 | bf = avp->av_bcbuf; | |
2359 | if (!bf || !bf->bf_mpdu) | |
2360 | goto skip; | |
2361 | ||
2362 | status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts); | |
2363 | if (status == -EINPROGRESS) | |
2364 | goto skip; | |
2365 | ||
2366 | sc->beacon.tx_processed = true; | |
2367 | sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); | |
2368 | ||
2369 | skip: | |
2370 | tasklet_enable(&sc->bcon_tasklet); | |
2371 | } | |
2372 | ||
2373 | return sc->beacon.tx_last; | |
2374 | } | |
2375 | ||
6baff7f9 | 2376 | struct ieee80211_ops ath9k_ops = { |
8feceb67 VT |
2377 | .tx = ath9k_tx, |
2378 | .start = ath9k_start, | |
2379 | .stop = ath9k_stop, | |
2380 | .add_interface = ath9k_add_interface, | |
6b3b991d | 2381 | .change_interface = ath9k_change_interface, |
8feceb67 VT |
2382 | .remove_interface = ath9k_remove_interface, |
2383 | .config = ath9k_config, | |
8feceb67 | 2384 | .configure_filter = ath9k_configure_filter, |
4ca77860 JB |
2385 | .sta_add = ath9k_sta_add, |
2386 | .sta_remove = ath9k_sta_remove, | |
5519541d | 2387 | .sta_notify = ath9k_sta_notify, |
8feceb67 | 2388 | .conf_tx = ath9k_conf_tx, |
8feceb67 | 2389 | .bss_info_changed = ath9k_bss_info_changed, |
8feceb67 | 2390 | .set_key = ath9k_set_key, |
8feceb67 | 2391 | .get_tsf = ath9k_get_tsf, |
3b5d665b | 2392 | .set_tsf = ath9k_set_tsf, |
8feceb67 | 2393 | .reset_tsf = ath9k_reset_tsf, |
4233df6b | 2394 | .ampdu_action = ath9k_ampdu_action, |
62dad5b0 | 2395 | .get_survey = ath9k_get_survey, |
3b319aae | 2396 | .rfkill_poll = ath9k_rfkill_poll_state, |
e239d859 | 2397 | .set_coverage_class = ath9k_set_coverage_class, |
69081624 | 2398 | .flush = ath9k_flush, |
15b91e83 | 2399 | .tx_frames_pending = ath9k_tx_frames_pending, |
ba4903f9 | 2400 | .tx_last_beacon = ath9k_tx_last_beacon, |
8feceb67 | 2401 | }; |