mac80211: add probe request filter flag
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
af03abec 19#include "btcoex.h"
f078f209 20
ce111bad
LR
21static void ath_cache_conf_rate(struct ath_softc *sc,
22 struct ieee80211_conf *conf)
ff37e337 23{
030bb495
LR
24 switch (conf->channel->band) {
25 case IEEE80211_BAND_2GHZ:
26 if (conf_is_ht20(conf))
545750d3 27 sc->cur_rate_mode = ATH9K_MODE_11NG_HT20;
030bb495 28 else if (conf_is_ht40_minus(conf))
545750d3 29 sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS;
030bb495 30 else if (conf_is_ht40_plus(conf))
545750d3 31 sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS;
96742256 32 else
545750d3 33 sc->cur_rate_mode = ATH9K_MODE_11G;
030bb495
LR
34 break;
35 case IEEE80211_BAND_5GHZ:
36 if (conf_is_ht20(conf))
545750d3 37 sc->cur_rate_mode = ATH9K_MODE_11NA_HT20;
030bb495 38 else if (conf_is_ht40_minus(conf))
545750d3 39 sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS;
030bb495 40 else if (conf_is_ht40_plus(conf))
545750d3 41 sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS;
030bb495 42 else
545750d3 43 sc->cur_rate_mode = ATH9K_MODE_11A;
030bb495
LR
44 break;
45 default:
ce111bad 46 BUG_ON(1);
030bb495
LR
47 break;
48 }
ff37e337
S
49}
50
51static void ath_update_txpow(struct ath_softc *sc)
52{
cbe61d8a 53 struct ath_hw *ah = sc->sc_ah;
ff37e337 54
17d7904d
S
55 if (sc->curtxpow != sc->config.txpowlimit) {
56 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337 57 /* read back in case value is clamped */
9cc3271f 58 sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
ff37e337
S
59 }
60}
61
62static u8 parse_mpdudensity(u8 mpdudensity)
63{
64 /*
65 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
66 * 0 for no restriction
67 * 1 for 1/4 us
68 * 2 for 1/2 us
69 * 3 for 1 us
70 * 4 for 2 us
71 * 5 for 4 us
72 * 6 for 8 us
73 * 7 for 16 us
74 */
75 switch (mpdudensity) {
76 case 0:
77 return 0;
78 case 1:
79 case 2:
80 case 3:
81 /* Our lower layer calculations limit our precision to
82 1 microsecond */
83 return 1;
84 case 4:
85 return 2;
86 case 5:
87 return 4;
88 case 6:
89 return 8;
90 case 7:
91 return 16;
92 default:
93 return 0;
94 }
95}
96
82880a7c
VT
97static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
98 struct ieee80211_hw *hw)
99{
100 struct ieee80211_channel *curchan = hw->conf.channel;
101 struct ath9k_channel *channel;
102 u8 chan_idx;
103
104 chan_idx = curchan->hw_value;
105 channel = &sc->sc_ah->channels[chan_idx];
106 ath9k_update_ichannel(sc, hw, channel);
107 return channel;
108}
109
55624204 110bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR
111{
112 unsigned long flags;
113 bool ret;
114
9ecdef4b
LR
115 spin_lock_irqsave(&sc->sc_pm_lock, flags);
116 ret = ath9k_hw_setpower(sc->sc_ah, mode);
117 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR
118
119 return ret;
120}
121
a91d75ae
LR
122void ath9k_ps_wakeup(struct ath_softc *sc)
123{
124 unsigned long flags;
125
126 spin_lock_irqsave(&sc->sc_pm_lock, flags);
127 if (++sc->ps_usecount != 1)
128 goto unlock;
129
9ecdef4b 130 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae
LR
131
132 unlock:
133 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
134}
135
136void ath9k_ps_restore(struct ath_softc *sc)
137{
138 unsigned long flags;
139
140 spin_lock_irqsave(&sc->sc_pm_lock, flags);
141 if (--sc->ps_usecount != 0)
142 goto unlock;
143
1dbfd9d4
VN
144 if (sc->ps_idle)
145 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
146 else if (sc->ps_enabled &&
147 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
1b04b930
S
148 PS_WAIT_FOR_CAB |
149 PS_WAIT_FOR_PSPOLL_DATA |
150 PS_WAIT_FOR_TX_ACK)))
9ecdef4b 151 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
a91d75ae
LR
152
153 unlock:
154 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
155}
156
5ee08656
FF
157static void ath_start_ani(struct ath_common *common)
158{
159 struct ath_hw *ah = common->ah;
160 unsigned long timestamp = jiffies_to_msecs(jiffies);
161 struct ath_softc *sc = (struct ath_softc *) common->priv;
162
163 if (!(sc->sc_flags & SC_OP_ANI_RUN))
164 return;
165
166 if (sc->sc_flags & SC_OP_OFFCHANNEL)
167 return;
168
169 common->ani.longcal_timer = timestamp;
170 common->ani.shortcal_timer = timestamp;
171 common->ani.checkani_timer = timestamp;
172
173 mod_timer(&common->ani.timer,
174 jiffies +
175 msecs_to_jiffies((u32)ah->config.ani_poll_interval));
176}
177
3430098a
FF
178static void ath_update_survey_nf(struct ath_softc *sc, int channel)
179{
180 struct ath_hw *ah = sc->sc_ah;
181 struct ath9k_channel *chan = &ah->channels[channel];
182 struct survey_info *survey = &sc->survey[channel];
183
184 if (chan->noisefloor) {
185 survey->filled |= SURVEY_INFO_NOISE_DBM;
186 survey->noise = chan->noisefloor;
187 }
188}
189
190static void ath_update_survey_stats(struct ath_softc *sc)
191{
192 struct ath_hw *ah = sc->sc_ah;
193 struct ath_common *common = ath9k_hw_common(ah);
194 int pos = ah->curchan - &ah->channels[0];
195 struct survey_info *survey = &sc->survey[pos];
196 struct ath_cycle_counters *cc = &common->cc_survey;
197 unsigned int div = common->clockrate * 1000;
198
199 ath_hw_cycle_counters_update(common);
200
201 if (cc->cycles > 0) {
202 survey->filled |= SURVEY_INFO_CHANNEL_TIME |
203 SURVEY_INFO_CHANNEL_TIME_BUSY |
204 SURVEY_INFO_CHANNEL_TIME_RX |
205 SURVEY_INFO_CHANNEL_TIME_TX;
206 survey->channel_time += cc->cycles / div;
207 survey->channel_time_busy += cc->rx_busy / div;
208 survey->channel_time_rx += cc->rx_frame / div;
209 survey->channel_time_tx += cc->tx_frame / div;
210 }
211 memset(cc, 0, sizeof(*cc));
212
213 ath_update_survey_nf(sc, pos);
214}
215
ff37e337
S
216/*
217 * Set/change channels. If the channel is really being changed, it's done
218 * by reseting the chip. To accomplish this we must first cleanup any pending
219 * DMA, then restart stuff.
220*/
0e2dedf9
JM
221int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
222 struct ath9k_channel *hchan)
ff37e337 223{
20bd2a09 224 struct ath_wiphy *aphy = hw->priv;
cbe61d8a 225 struct ath_hw *ah = sc->sc_ah;
c46917bb 226 struct ath_common *common = ath9k_hw_common(ah);
25c56eec 227 struct ieee80211_conf *conf = &common->hw->conf;
ff37e337 228 bool fastcc = true, stopped;
ae8d2858 229 struct ieee80211_channel *channel = hw->conf.channel;
20bd2a09 230 struct ath9k_hw_cal_data *caldata = NULL;
ae8d2858 231 int r;
ff37e337
S
232
233 if (sc->sc_flags & SC_OP_INVALID)
234 return -EIO;
235
5ee08656
FF
236 del_timer_sync(&common->ani.timer);
237 cancel_work_sync(&sc->paprd_work);
238 cancel_work_sync(&sc->hw_check_work);
239 cancel_delayed_work_sync(&sc->tx_complete_work);
240
3cbb5dd7
VN
241 ath9k_ps_wakeup(sc);
242
c0d7c7af
LR
243 /*
244 * This is only performed if the channel settings have
245 * actually changed.
246 *
247 * To switch channels clear any pending DMA operations;
248 * wait long enough for the RX fifo to drain, reset the
249 * hardware at the new frequency, and then re-enable
250 * the relevant bits of the h/w.
251 */
252 ath9k_hw_set_interrupts(ah, 0);
043a0405 253 ath_drain_all_txq(sc, false);
c0d7c7af 254 stopped = ath_stoprecv(sc);
ff37e337 255
c0d7c7af
LR
256 /* XXX: do not flush receive queue here. We don't want
257 * to flush data frames already in queue because of
258 * changing channel. */
ff37e337 259
5ee08656 260 if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL))
c0d7c7af
LR
261 fastcc = false;
262
20bd2a09
FF
263 if (!(sc->sc_flags & SC_OP_OFFCHANNEL))
264 caldata = &aphy->caldata;
265
c46917bb 266 ath_print(common, ATH_DBG_CONFIG,
1e51b2ff 267 "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n",
c46917bb 268 sc->sc_ah->curchan->channel,
1e51b2ff
LR
269 channel->center_freq, conf_is_ht40(conf),
270 fastcc);
ff37e337 271
c0d7c7af
LR
272 spin_lock_bh(&sc->sc_resetlock);
273
20bd2a09 274 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
c0d7c7af 275 if (r) {
c46917bb 276 ath_print(common, ATH_DBG_FATAL,
f643e51d 277 "Unable to reset channel (%u MHz), "
c46917bb
LR
278 "reset status %d\n",
279 channel->center_freq, r);
c0d7c7af 280 spin_unlock_bh(&sc->sc_resetlock);
3989279c 281 goto ps_restore;
ff37e337 282 }
c0d7c7af
LR
283 spin_unlock_bh(&sc->sc_resetlock);
284
c0d7c7af 285 if (ath_startrecv(sc) != 0) {
c46917bb
LR
286 ath_print(common, ATH_DBG_FATAL,
287 "Unable to restart recv logic\n");
3989279c
GJ
288 r = -EIO;
289 goto ps_restore;
c0d7c7af
LR
290 }
291
292 ath_cache_conf_rate(sc, &hw->conf);
293 ath_update_txpow(sc);
3069168c 294 ath9k_hw_set_interrupts(ah, ah->imask);
3989279c 295
48a6a468
LR
296 if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) {
297 ath_beacon_config(sc, NULL);
5ee08656 298 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
48a6a468 299 ath_start_ani(common);
5ee08656
FF
300 }
301
3989279c 302 ps_restore:
3cbb5dd7 303 ath9k_ps_restore(sc);
3989279c 304 return r;
ff37e337
S
305}
306
9f42c2b6
FF
307static void ath_paprd_activate(struct ath_softc *sc)
308{
309 struct ath_hw *ah = sc->sc_ah;
20bd2a09 310 struct ath9k_hw_cal_data *caldata = ah->caldata;
9094537c 311 struct ath_common *common = ath9k_hw_common(ah);
9f42c2b6
FF
312 int chain;
313
20bd2a09 314 if (!caldata || !caldata->paprd_done)
9f42c2b6
FF
315 return;
316
317 ath9k_ps_wakeup(sc);
ddfef792 318 ar9003_paprd_enable(ah, false);
9f42c2b6 319 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
9094537c 320 if (!(common->tx_chainmask & BIT(chain)))
9f42c2b6
FF
321 continue;
322
20bd2a09 323 ar9003_paprd_populate_single_table(ah, caldata, chain);
9f42c2b6
FF
324 }
325
326 ar9003_paprd_enable(ah, true);
327 ath9k_ps_restore(sc);
328}
329
330void ath_paprd_calibrate(struct work_struct *work)
331{
332 struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
333 struct ieee80211_hw *hw = sc->hw;
334 struct ath_hw *ah = sc->sc_ah;
335 struct ieee80211_hdr *hdr;
336 struct sk_buff *skb = NULL;
337 struct ieee80211_tx_info *tx_info;
338 int band = hw->conf.channel->band;
339 struct ieee80211_supported_band *sband = &sc->sbands[band];
340 struct ath_tx_control txctl;
20bd2a09 341 struct ath9k_hw_cal_data *caldata = ah->caldata;
9094537c 342 struct ath_common *common = ath9k_hw_common(ah);
9f42c2b6
FF
343 int qnum, ftype;
344 int chain_ok = 0;
345 int chain;
346 int len = 1800;
347 int time_left;
348 int i;
349
20bd2a09
FF
350 if (!caldata)
351 return;
352
9f42c2b6
FF
353 skb = alloc_skb(len, GFP_KERNEL);
354 if (!skb)
355 return;
356
357 tx_info = IEEE80211_SKB_CB(skb);
358
359 skb_put(skb, len);
360 memset(skb->data, 0, len);
361 hdr = (struct ieee80211_hdr *)skb->data;
362 ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
363 hdr->frame_control = cpu_to_le16(ftype);
a3d3da14 364 hdr->duration_id = cpu_to_le16(10);
9f42c2b6
FF
365 memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
366 memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
367 memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
368
369 memset(&txctl, 0, sizeof(txctl));
370 qnum = sc->tx.hwq_map[WME_AC_BE];
371 txctl.txq = &sc->tx.txq[qnum];
372
47399f1a 373 ath9k_ps_wakeup(sc);
9f42c2b6
FF
374 ar9003_paprd_init_table(ah);
375 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
9094537c 376 if (!(common->tx_chainmask & BIT(chain)))
9f42c2b6
FF
377 continue;
378
379 chain_ok = 0;
380 memset(tx_info, 0, sizeof(*tx_info));
381 tx_info->band = band;
382
383 for (i = 0; i < 4; i++) {
384 tx_info->control.rates[i].idx = sband->n_bitrates - 1;
385 tx_info->control.rates[i].count = 6;
386 }
387
388 init_completion(&sc->paprd_complete);
389 ar9003_paprd_setup_gain_table(ah, chain);
390 txctl.paprd = BIT(chain);
391 if (ath_tx_start(hw, skb, &txctl) != 0)
392 break;
393
394 time_left = wait_for_completion_timeout(&sc->paprd_complete,
ca369eb4 395 msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
9f42c2b6
FF
396 if (!time_left) {
397 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
398 "Timeout waiting for paprd training on "
399 "TX chain %d\n",
400 chain);
ca369eb4 401 goto fail_paprd;
9f42c2b6
FF
402 }
403
404 if (!ar9003_paprd_is_done(ah))
405 break;
406
20bd2a09 407 if (ar9003_paprd_create_curve(ah, caldata, chain) != 0)
9f42c2b6
FF
408 break;
409
410 chain_ok = 1;
411 }
412 kfree_skb(skb);
413
414 if (chain_ok) {
20bd2a09 415 caldata->paprd_done = true;
9f42c2b6
FF
416 ath_paprd_activate(sc);
417 }
418
ca369eb4 419fail_paprd:
9f42c2b6
FF
420 ath9k_ps_restore(sc);
421}
422
ff37e337
S
423/*
424 * This routine performs the periodic noise floor calibration function
425 * that is used to adjust and optimize the chip performance. This
426 * takes environmental changes (location, temperature) into account.
427 * When the task is complete, it reschedules itself depending on the
428 * appropriate interval that was calculated.
429 */
55624204 430void ath_ani_calibrate(unsigned long data)
ff37e337 431{
20977d3e
S
432 struct ath_softc *sc = (struct ath_softc *)data;
433 struct ath_hw *ah = sc->sc_ah;
c46917bb 434 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
435 bool longcal = false;
436 bool shortcal = false;
437 bool aniflag = false;
438 unsigned int timestamp = jiffies_to_msecs(jiffies);
6044474e 439 u32 cal_interval, short_cal_interval, long_cal_interval;
b5bfc568 440 unsigned long flags;
6044474e
FF
441
442 if (ah->caldata && ah->caldata->nfcal_interference)
443 long_cal_interval = ATH_LONG_CALINTERVAL_INT;
444 else
445 long_cal_interval = ATH_LONG_CALINTERVAL;
ff37e337 446
20977d3e
S
447 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
448 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337 449
1ffc1c61
JM
450 /* Only calibrate if awake */
451 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
452 goto set_timer;
453
454 ath9k_ps_wakeup(sc);
455
ff37e337 456 /* Long calibration runs independently of short calibration. */
6044474e 457 if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
ff37e337 458 longcal = true;
c46917bb 459 ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
3d536acf 460 common->ani.longcal_timer = timestamp;
ff37e337
S
461 }
462
17d7904d 463 /* Short calibration applies only while caldone is false */
3d536acf
LR
464 if (!common->ani.caldone) {
465 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 466 shortcal = true;
c46917bb
LR
467 ath_print(common, ATH_DBG_ANI,
468 "shortcal @%lu\n", jiffies);
3d536acf
LR
469 common->ani.shortcal_timer = timestamp;
470 common->ani.resetcal_timer = timestamp;
ff37e337
S
471 }
472 } else {
3d536acf 473 if ((timestamp - common->ani.resetcal_timer) >=
ff37e337 474 ATH_RESTART_CALINTERVAL) {
3d536acf
LR
475 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
476 if (common->ani.caldone)
477 common->ani.resetcal_timer = timestamp;
ff37e337
S
478 }
479 }
480
481 /* Verify whether we must check ANI */
e36b27af
LR
482 if ((timestamp - common->ani.checkani_timer) >=
483 ah->config.ani_poll_interval) {
ff37e337 484 aniflag = true;
3d536acf 485 common->ani.checkani_timer = timestamp;
ff37e337
S
486 }
487
488 /* Skip all processing if there's nothing to do. */
489 if (longcal || shortcal || aniflag) {
490 /* Call ANI routine if necessary */
b5bfc568
FF
491 if (aniflag) {
492 spin_lock_irqsave(&common->cc_lock, flags);
22e66a4c 493 ath9k_hw_ani_monitor(ah, ah->curchan);
3430098a 494 ath_update_survey_stats(sc);
b5bfc568
FF
495 spin_unlock_irqrestore(&common->cc_lock, flags);
496 }
ff37e337
S
497
498 /* Perform calibration if necessary */
499 if (longcal || shortcal) {
3d536acf 500 common->ani.caldone =
43c27613
LR
501 ath9k_hw_calibrate(ah,
502 ah->curchan,
503 common->rx_chainmask,
504 longcal);
ff37e337
S
505 }
506 }
507
1ffc1c61
JM
508 ath9k_ps_restore(sc);
509
20977d3e 510set_timer:
ff37e337
S
511 /*
512 * Set timer interval based on previous results.
513 * The interval must be the shortest necessary to satisfy ANI,
514 * short calibration and long calibration.
515 */
aac9207e 516 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 517 if (sc->sc_ah->config.enable_ani)
e36b27af
LR
518 cal_interval = min(cal_interval,
519 (u32)ah->config.ani_poll_interval);
3d536acf 520 if (!common->ani.caldone)
20977d3e 521 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 522
3d536acf 523 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
20bd2a09
FF
524 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
525 if (!ah->caldata->paprd_done)
9f42c2b6
FF
526 ieee80211_queue_work(sc->hw, &sc->paprd_work);
527 else
528 ath_paprd_activate(sc);
529 }
ff37e337
S
530}
531
532/*
533 * Update tx/rx chainmask. For legacy association,
534 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT
535 * the chainmask configuration, for bt coexistence, use
536 * the chainmask configuration even in legacy mode.
ff37e337 537 */
0e2dedf9 538void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337 539{
af03abec 540 struct ath_hw *ah = sc->sc_ah;
43c27613 541 struct ath_common *common = ath9k_hw_common(ah);
af03abec 542
5ee08656 543 if ((sc->sc_flags & SC_OP_OFFCHANNEL) || is_ht ||
766ec4a9 544 (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
43c27613
LR
545 common->tx_chainmask = ah->caps.tx_chainmask;
546 common->rx_chainmask = ah->caps.rx_chainmask;
ff37e337 547 } else {
43c27613
LR
548 common->tx_chainmask = 1;
549 common->rx_chainmask = 1;
ff37e337
S
550 }
551
43c27613 552 ath_print(common, ATH_DBG_CONFIG,
c46917bb 553 "tx chmask: %d, rx chmask: %d\n",
43c27613
LR
554 common->tx_chainmask,
555 common->rx_chainmask);
ff37e337
S
556}
557
558static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
559{
560 struct ath_node *an;
561
562 an = (struct ath_node *)sta->drv_priv;
563
87792efc 564 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 565 ath_tx_node_init(sc, an);
9e98ac65 566 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S
567 sta->ht_cap.ampdu_factor);
568 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
a59b5a5e 569 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
87792efc 570 }
ff37e337
S
571}
572
573static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
574{
575 struct ath_node *an = (struct ath_node *)sta->drv_priv;
576
577 if (sc->sc_flags & SC_OP_TXAGGR)
578 ath_tx_node_cleanup(sc, an);
579}
580
347809fc
FF
581void ath_hw_check(struct work_struct *work)
582{
583 struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
584 int i;
585
586 ath9k_ps_wakeup(sc);
587
588 for (i = 0; i < 3; i++) {
589 if (ath9k_hw_check_alive(sc->sc_ah))
590 goto out;
591
592 msleep(1);
593 }
594 ath_reset(sc, false);
595
596out:
597 ath9k_ps_restore(sc);
598}
599
55624204 600void ath9k_tasklet(unsigned long data)
ff37e337
S
601{
602 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 603 struct ath_hw *ah = sc->sc_ah;
c46917bb 604 struct ath_common *common = ath9k_hw_common(ah);
af03abec 605
17d7904d 606 u32 status = sc->intrstatus;
b5c80475 607 u32 rxmask;
ff37e337 608
153e080d
VT
609 ath9k_ps_wakeup(sc);
610
347809fc 611 if (status & ATH9K_INT_FATAL) {
ff37e337 612 ath_reset(sc, false);
153e080d 613 ath9k_ps_restore(sc);
ff37e337 614 return;
063d8be3 615 }
ff37e337 616
347809fc
FF
617 if (!ath9k_hw_check_alive(ah))
618 ieee80211_queue_work(sc->hw, &sc->hw_check_work);
619
b5c80475
FF
620 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
621 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
622 ATH9K_INT_RXORN);
623 else
624 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
625
626 if (status & rxmask) {
063d8be3 627 spin_lock_bh(&sc->rx.rxflushlock);
b5c80475
FF
628
629 /* Check for high priority Rx first */
630 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
631 (status & ATH9K_INT_RXHP))
632 ath_rx_tasklet(sc, 0, true);
633
634 ath_rx_tasklet(sc, 0, false);
063d8be3 635 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S
636 }
637
e5003249
VT
638 if (status & ATH9K_INT_TX) {
639 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
640 ath_tx_edma_tasklet(sc);
641 else
642 ath_tx_tasklet(sc);
643 }
063d8be3 644
96148326 645 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
54ce846e
JM
646 /*
647 * TSF sync does not look correct; remain awake to sync with
648 * the next Beacon.
649 */
c46917bb
LR
650 ath_print(common, ATH_DBG_PS,
651 "TSFOOR - Sync with next Beacon\n");
1b04b930 652 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
54ce846e
JM
653 }
654
766ec4a9 655 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
ebb8e1d7
VT
656 if (status & ATH9K_INT_GENTIMER)
657 ath_gen_timer_isr(sc->sc_ah);
658
ff37e337 659 /* re-enable hardware interrupt */
3069168c 660 ath9k_hw_set_interrupts(ah, ah->imask);
153e080d 661 ath9k_ps_restore(sc);
ff37e337
S
662}
663
6baff7f9 664irqreturn_t ath_isr(int irq, void *dev)
ff37e337 665{
063d8be3
S
666#define SCHED_INTR ( \
667 ATH9K_INT_FATAL | \
668 ATH9K_INT_RXORN | \
669 ATH9K_INT_RXEOL | \
670 ATH9K_INT_RX | \
b5c80475
FF
671 ATH9K_INT_RXLP | \
672 ATH9K_INT_RXHP | \
063d8be3
S
673 ATH9K_INT_TX | \
674 ATH9K_INT_BMISS | \
675 ATH9K_INT_CST | \
ebb8e1d7
VT
676 ATH9K_INT_TSFOOR | \
677 ATH9K_INT_GENTIMER)
063d8be3 678
ff37e337 679 struct ath_softc *sc = dev;
cbe61d8a 680 struct ath_hw *ah = sc->sc_ah;
b5bfc568 681 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
682 enum ath9k_int status;
683 bool sched = false;
684
063d8be3
S
685 /*
686 * The hardware is not ready/present, don't
687 * touch anything. Note this can happen early
688 * on if the IRQ is shared.
689 */
690 if (sc->sc_flags & SC_OP_INVALID)
691 return IRQ_NONE;
ff37e337 692
063d8be3
S
693
694 /* shared irq, not for us */
695
153e080d 696 if (!ath9k_hw_intrpend(ah))
063d8be3 697 return IRQ_NONE;
063d8be3
S
698
699 /*
700 * Figure out the reason(s) for the interrupt. Note
701 * that the hal returns a pseudo-ISR that may include
702 * bits we haven't explicitly enabled so we mask the
703 * value to insure we only process bits we requested.
704 */
705 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
3069168c 706 status &= ah->imask; /* discard unasked-for bits */
ff37e337 707
063d8be3
S
708 /*
709 * If there are no status bits set, then this interrupt was not
710 * for me (should have been caught above).
711 */
153e080d 712 if (!status)
063d8be3 713 return IRQ_NONE;
ff37e337 714
063d8be3
S
715 /* Cache the status */
716 sc->intrstatus = status;
717
718 if (status & SCHED_INTR)
719 sched = true;
720
721 /*
722 * If a FATAL or RXORN interrupt is received, we have to reset the
723 * chip immediately.
724 */
b5c80475
FF
725 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
726 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
063d8be3
S
727 goto chip_reset;
728
08578b8f
LR
729 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
730 (status & ATH9K_INT_BB_WATCHDOG)) {
b5bfc568
FF
731
732 spin_lock(&common->cc_lock);
733 ath_hw_cycle_counters_update(common);
08578b8f 734 ar9003_hw_bb_watchdog_dbg_info(ah);
b5bfc568
FF
735 spin_unlock(&common->cc_lock);
736
08578b8f
LR
737 goto chip_reset;
738 }
739
063d8be3
S
740 if (status & ATH9K_INT_SWBA)
741 tasklet_schedule(&sc->bcon_tasklet);
742
743 if (status & ATH9K_INT_TXURN)
744 ath9k_hw_updatetxtriglevel(ah, true);
745
b5c80475
FF
746 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
747 if (status & ATH9K_INT_RXEOL) {
748 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
749 ath9k_hw_set_interrupts(ah, ah->imask);
750 }
751 }
752
063d8be3 753 if (status & ATH9K_INT_MIB) {
ff37e337 754 /*
063d8be3
S
755 * Disable interrupts until we service the MIB
756 * interrupt; otherwise it will continue to
757 * fire.
ff37e337 758 */
063d8be3
S
759 ath9k_hw_set_interrupts(ah, 0);
760 /*
761 * Let the hal handle the event. We assume
762 * it will clear whatever condition caused
763 * the interrupt.
764 */
bfc472bb 765 ath9k_hw_proc_mib_event(ah);
3069168c 766 ath9k_hw_set_interrupts(ah, ah->imask);
063d8be3 767 }
ff37e337 768
153e080d
VT
769 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
770 if (status & ATH9K_INT_TIM_TIMER) {
063d8be3
S
771 /* Clear RxAbort bit so that we can
772 * receive frames */
9ecdef4b 773 ath9k_setpower(sc, ATH9K_PM_AWAKE);
153e080d 774 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930 775 sc->ps_flags |= PS_WAIT_FOR_BEACON;
ff37e337 776 }
063d8be3
S
777
778chip_reset:
ff37e337 779
817e11de
S
780 ath_debug_stat_interrupt(sc, status);
781
ff37e337
S
782 if (sched) {
783 /* turn off every interrupt except SWBA */
3069168c 784 ath9k_hw_set_interrupts(ah, (ah->imask & ATH9K_INT_SWBA));
ff37e337
S
785 tasklet_schedule(&sc->intr_tq);
786 }
787
788 return IRQ_HANDLED;
063d8be3
S
789
790#undef SCHED_INTR
ff37e337
S
791}
792
f078f209 793static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 794 struct ieee80211_channel *chan,
094d05dc 795 enum nl80211_channel_type channel_type)
f078f209
LR
796{
797 u32 chanmode = 0;
f078f209
LR
798
799 switch (chan->band) {
800 case IEEE80211_BAND_2GHZ:
094d05dc
S
801 switch(channel_type) {
802 case NL80211_CHAN_NO_HT:
803 case NL80211_CHAN_HT20:
f078f209 804 chanmode = CHANNEL_G_HT20;
094d05dc
S
805 break;
806 case NL80211_CHAN_HT40PLUS:
f078f209 807 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S
808 break;
809 case NL80211_CHAN_HT40MINUS:
f078f209 810 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S
811 break;
812 }
f078f209
LR
813 break;
814 case IEEE80211_BAND_5GHZ:
094d05dc
S
815 switch(channel_type) {
816 case NL80211_CHAN_NO_HT:
817 case NL80211_CHAN_HT20:
f078f209 818 chanmode = CHANNEL_A_HT20;
094d05dc
S
819 break;
820 case NL80211_CHAN_HT40PLUS:
f078f209 821 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S
822 break;
823 case NL80211_CHAN_HT40MINUS:
f078f209 824 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S
825 break;
826 }
f078f209
LR
827 break;
828 default:
829 break;
830 }
831
832 return chanmode;
833}
834
8feceb67 835static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 836 struct ieee80211_vif *vif,
8feceb67 837 struct ieee80211_bss_conf *bss_conf)
f078f209 838{
f2b2143e 839 struct ath_hw *ah = sc->sc_ah;
1510718d 840 struct ath_common *common = ath9k_hw_common(ah);
f078f209 841
8feceb67 842 if (bss_conf->assoc) {
c46917bb
LR
843 ath_print(common, ATH_DBG_CONFIG,
844 "Bss Info ASSOC %d, bssid: %pM\n",
845 bss_conf->aid, common->curbssid);
f078f209 846
8feceb67 847 /* New association, store aid */
1510718d 848 common->curaid = bss_conf->aid;
f2b2143e 849 ath9k_hw_write_associd(ah);
2664f201
SB
850
851 /*
852 * Request a re-configuration of Beacon related timers
853 * on the receipt of the first Beacon frame (i.e.,
854 * after time sync with the AP).
855 */
1b04b930 856 sc->ps_flags |= PS_BEACON_SYNC;
f078f209 857
8feceb67 858 /* Configure the beacon */
2c3db3d5 859 ath_beacon_config(sc, vif);
f078f209 860
8feceb67 861 /* Reset rssi stats */
22e66a4c 862 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
f078f209 863
6c3118e2 864 sc->sc_flags |= SC_OP_ANI_RUN;
3d536acf 865 ath_start_ani(common);
8feceb67 866 } else {
c46917bb 867 ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
1510718d 868 common->curaid = 0;
f38faa31 869 /* Stop ANI */
6c3118e2 870 sc->sc_flags &= ~SC_OP_ANI_RUN;
3d536acf 871 del_timer_sync(&common->ani.timer);
f078f209 872 }
8feceb67 873}
f078f209 874
68a89116 875void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 876{
cbe61d8a 877 struct ath_hw *ah = sc->sc_ah;
c46917bb 878 struct ath_common *common = ath9k_hw_common(ah);
68a89116 879 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 880 int r;
500c064d 881
3cbb5dd7 882 ath9k_ps_wakeup(sc);
93b1b37f 883 ath9k_hw_configpcipowersave(ah, 0, 0);
ae8d2858 884
159cd468
VT
885 if (!ah->curchan)
886 ah->curchan = ath_get_curchannel(sc, sc->hw);
887
d2f5b3a6 888 spin_lock_bh(&sc->sc_resetlock);
20bd2a09 889 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ae8d2858 890 if (r) {
c46917bb 891 ath_print(common, ATH_DBG_FATAL,
f643e51d 892 "Unable to reset channel (%u MHz), "
c46917bb
LR
893 "reset status %d\n",
894 channel->center_freq, r);
500c064d
VT
895 }
896 spin_unlock_bh(&sc->sc_resetlock);
897
898 ath_update_txpow(sc);
899 if (ath_startrecv(sc) != 0) {
c46917bb
LR
900 ath_print(common, ATH_DBG_FATAL,
901 "Unable to restart recv logic\n");
500c064d
VT
902 return;
903 }
904
905 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 906 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT
907
908 /* Re-Enable interrupts */
3069168c 909 ath9k_hw_set_interrupts(ah, ah->imask);
500c064d
VT
910
911 /* Enable LED */
08fc5c1b 912 ath9k_hw_cfg_output(ah, ah->led_pin,
500c064d 913 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b 914 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
500c064d 915
68a89116 916 ieee80211_wake_queues(hw);
3cbb5dd7 917 ath9k_ps_restore(sc);
500c064d
VT
918}
919
68a89116 920void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 921{
cbe61d8a 922 struct ath_hw *ah = sc->sc_ah;
68a89116 923 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 924 int r;
500c064d 925
3cbb5dd7 926 ath9k_ps_wakeup(sc);
68a89116 927 ieee80211_stop_queues(hw);
500c064d 928
982723df
VN
929 /*
930 * Keep the LED on when the radio is disabled
931 * during idle unassociated state.
932 */
933 if (!sc->ps_idle) {
934 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
935 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
936 }
500c064d
VT
937
938 /* Disable interrupts */
939 ath9k_hw_set_interrupts(ah, 0);
940
043a0405 941 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT
942 ath_stoprecv(sc); /* turn off frame recv */
943 ath_flushrecv(sc); /* flush recv queue */
944
159cd468 945 if (!ah->curchan)
68a89116 946 ah->curchan = ath_get_curchannel(sc, hw);
159cd468 947
500c064d 948 spin_lock_bh(&sc->sc_resetlock);
20bd2a09 949 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ae8d2858 950 if (r) {
c46917bb 951 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
f643e51d 952 "Unable to reset channel (%u MHz), "
c46917bb
LR
953 "reset status %d\n",
954 channel->center_freq, r);
500c064d
VT
955 }
956 spin_unlock_bh(&sc->sc_resetlock);
957
958 ath9k_hw_phy_disable(ah);
93b1b37f 959 ath9k_hw_configpcipowersave(ah, 1, 1);
3cbb5dd7 960 ath9k_ps_restore(sc);
9ecdef4b 961 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
500c064d
VT
962}
963
ff37e337
S
964int ath_reset(struct ath_softc *sc, bool retry_tx)
965{
cbe61d8a 966 struct ath_hw *ah = sc->sc_ah;
c46917bb 967 struct ath_common *common = ath9k_hw_common(ah);
030bb495 968 struct ieee80211_hw *hw = sc->hw;
ae8d2858 969 int r;
ff37e337 970
2ab81d4a
S
971 /* Stop ANI */
972 del_timer_sync(&common->ani.timer);
973
cc9c378a
S
974 ieee80211_stop_queues(hw);
975
ff37e337 976 ath9k_hw_set_interrupts(ah, 0);
043a0405 977 ath_drain_all_txq(sc, retry_tx);
ff37e337
S
978 ath_stoprecv(sc);
979 ath_flushrecv(sc);
980
981 spin_lock_bh(&sc->sc_resetlock);
20bd2a09 982 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
ae8d2858 983 if (r)
c46917bb
LR
984 ath_print(common, ATH_DBG_FATAL,
985 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S
986 spin_unlock_bh(&sc->sc_resetlock);
987
988 if (ath_startrecv(sc) != 0)
c46917bb
LR
989 ath_print(common, ATH_DBG_FATAL,
990 "Unable to start recv logic\n");
ff37e337
S
991
992 /*
993 * We may be doing a reset in response to a request
994 * that changes the channel so update any state that
995 * might change as a result.
996 */
ce111bad 997 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S
998
999 ath_update_txpow(sc);
1000
52b8ac92 1001 if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL)))
2c3db3d5 1002 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 1003
3069168c 1004 ath9k_hw_set_interrupts(ah, ah->imask);
ff37e337
S
1005
1006 if (retry_tx) {
1007 int i;
1008 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1009 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S
1010 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1011 ath_txq_schedule(sc, &sc->tx.txq[i]);
1012 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S
1013 }
1014 }
1015 }
1016
cc9c378a
S
1017 ieee80211_wake_queues(hw);
1018
2ab81d4a
S
1019 /* Start ANI */
1020 ath_start_ani(common);
1021
ae8d2858 1022 return r;
ff37e337
S
1023}
1024
ebe297c3 1025static int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
ff37e337
S
1026{
1027 int qnum;
1028
1029 switch (queue) {
1030 case 0:
1d2231e2 1031 qnum = sc->tx.hwq_map[WME_AC_VO];
ff37e337
S
1032 break;
1033 case 1:
1d2231e2 1034 qnum = sc->tx.hwq_map[WME_AC_VI];
ff37e337
S
1035 break;
1036 case 2:
1d2231e2 1037 qnum = sc->tx.hwq_map[WME_AC_BE];
ff37e337
S
1038 break;
1039 case 3:
1d2231e2 1040 qnum = sc->tx.hwq_map[WME_AC_BK];
ff37e337
S
1041 break;
1042 default:
1d2231e2 1043 qnum = sc->tx.hwq_map[WME_AC_BE];
ff37e337
S
1044 break;
1045 }
1046
1047 return qnum;
1048}
1049
1050int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1051{
1052 int qnum;
1053
1054 switch (queue) {
1d2231e2 1055 case WME_AC_VO:
ff37e337
S
1056 qnum = 0;
1057 break;
1d2231e2 1058 case WME_AC_VI:
ff37e337
S
1059 qnum = 1;
1060 break;
1d2231e2 1061 case WME_AC_BE:
ff37e337
S
1062 qnum = 2;
1063 break;
1d2231e2 1064 case WME_AC_BK:
ff37e337
S
1065 qnum = 3;
1066 break;
1067 default:
1068 qnum = -1;
1069 break;
1070 }
1071
1072 return qnum;
1073}
1074
5f8e077c
LR
1075/* XXX: Remove me once we don't depend on ath9k_channel for all
1076 * this redundant data */
0e2dedf9
JM
1077void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1078 struct ath9k_channel *ichan)
5f8e077c 1079{
5f8e077c
LR
1080 struct ieee80211_channel *chan = hw->conf.channel;
1081 struct ieee80211_conf *conf = &hw->conf;
1082
1083 ichan->channel = chan->center_freq;
1084 ichan->chan = chan;
1085
1086 if (chan->band == IEEE80211_BAND_2GHZ) {
1087 ichan->chanmode = CHANNEL_G;
8813262e 1088 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
5f8e077c
LR
1089 } else {
1090 ichan->chanmode = CHANNEL_A;
1091 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1092 }
1093
25c56eec 1094 if (conf_is_ht(conf))
5f8e077c
LR
1095 ichan->chanmode = ath_get_extchanmode(sc, chan,
1096 conf->channel_type);
5f8e077c
LR
1097}
1098
ff37e337
S
1099/**********************/
1100/* mac80211 callbacks */
1101/**********************/
1102
8feceb67 1103static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1104{
bce048d7
JM
1105 struct ath_wiphy *aphy = hw->priv;
1106 struct ath_softc *sc = aphy->sc;
af03abec 1107 struct ath_hw *ah = sc->sc_ah;
c46917bb 1108 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 1109 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1110 struct ath9k_channel *init_channel;
82880a7c 1111 int r;
f078f209 1112
c46917bb
LR
1113 ath_print(common, ATH_DBG_CONFIG,
1114 "Starting driver with initial channel: %d MHz\n",
1115 curchan->center_freq);
f078f209 1116
141b38b6
S
1117 mutex_lock(&sc->mutex);
1118
9580a222
JM
1119 if (ath9k_wiphy_started(sc)) {
1120 if (sc->chan_idx == curchan->hw_value) {
1121 /*
1122 * Already on the operational channel, the new wiphy
1123 * can be marked active.
1124 */
1125 aphy->state = ATH_WIPHY_ACTIVE;
1126 ieee80211_wake_queues(hw);
1127 } else {
1128 /*
1129 * Another wiphy is on another channel, start the new
1130 * wiphy in paused state.
1131 */
1132 aphy->state = ATH_WIPHY_PAUSED;
1133 ieee80211_stop_queues(hw);
1134 }
1135 mutex_unlock(&sc->mutex);
1136 return 0;
1137 }
1138 aphy->state = ATH_WIPHY_ACTIVE;
1139
8feceb67 1140 /* setup initial channel */
f078f209 1141
82880a7c 1142 sc->chan_idx = curchan->hw_value;
f078f209 1143
82880a7c 1144 init_channel = ath_get_curchannel(sc, hw);
ff37e337
S
1145
1146 /* Reset SERDES registers */
af03abec 1147 ath9k_hw_configpcipowersave(ah, 0, 0);
ff37e337
S
1148
1149 /*
1150 * The basic interface to setting the hardware in a good
1151 * state is ``reset''. On return the hardware is known to
1152 * be powered up and with interrupts disabled. This must
1153 * be followed by initialization of the appropriate bits
1154 * and then setup of the interrupt mask.
1155 */
1156 spin_lock_bh(&sc->sc_resetlock);
20bd2a09 1157 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
ae8d2858 1158 if (r) {
c46917bb
LR
1159 ath_print(common, ATH_DBG_FATAL,
1160 "Unable to reset hardware; reset status %d "
1161 "(freq %u MHz)\n", r,
1162 curchan->center_freq);
ff37e337 1163 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 1164 goto mutex_unlock;
ff37e337
S
1165 }
1166 spin_unlock_bh(&sc->sc_resetlock);
1167
1168 /*
1169 * This is needed only to setup initial state
1170 * but it's best done after a reset.
1171 */
1172 ath_update_txpow(sc);
8feceb67 1173
ff37e337
S
1174 /*
1175 * Setup the hardware after reset:
1176 * The receive engine is set going.
1177 * Frame transmit is handled entirely
1178 * in the frame output path; there's nothing to do
1179 * here except setup the interrupt mask.
1180 */
1181 if (ath_startrecv(sc) != 0) {
c46917bb
LR
1182 ath_print(common, ATH_DBG_FATAL,
1183 "Unable to start recv logic\n");
141b38b6
S
1184 r = -EIO;
1185 goto mutex_unlock;
f078f209 1186 }
8feceb67 1187
ff37e337 1188 /* Setup our intr mask. */
b5c80475
FF
1189 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
1190 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
1191 ATH9K_INT_GLOBAL;
1192
1193 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
08578b8f
LR
1194 ah->imask |= ATH9K_INT_RXHP |
1195 ATH9K_INT_RXLP |
1196 ATH9K_INT_BB_WATCHDOG;
b5c80475
FF
1197 else
1198 ah->imask |= ATH9K_INT_RX;
ff37e337 1199
364734fa 1200 ah->imask |= ATH9K_INT_GTT;
ff37e337 1201
af03abec 1202 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
3069168c 1203 ah->imask |= ATH9K_INT_CST;
ff37e337 1204
ce111bad 1205 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S
1206
1207 sc->sc_flags &= ~SC_OP_INVALID;
1208
1209 /* Disable BMISS interrupt when we're not associated */
3069168c
PR
1210 ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1211 ath9k_hw_set_interrupts(ah, ah->imask);
ff37e337 1212
bce048d7 1213 ieee80211_wake_queues(hw);
ff37e337 1214
42935eca 1215 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
164ace38 1216
766ec4a9
LR
1217 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
1218 !ah->btcoex_hw.enabled) {
5e197292
LR
1219 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1220 AR_STOMP_LOW_WLAN_WGHT);
af03abec 1221 ath9k_hw_btcoex_enable(ah);
f985ad12 1222
5bb12791
LR
1223 if (common->bus_ops->bt_coex_prep)
1224 common->bus_ops->bt_coex_prep(common);
766ec4a9 1225 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1226 ath9k_btcoex_timer_resume(sc);
1773912b
VT
1227 }
1228
141b38b6
S
1229mutex_unlock:
1230 mutex_unlock(&sc->mutex);
1231
ae8d2858 1232 return r;
f078f209
LR
1233}
1234
8feceb67
VT
1235static int ath9k_tx(struct ieee80211_hw *hw,
1236 struct sk_buff *skb)
f078f209 1237{
528f0c6b 1238 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM
1239 struct ath_wiphy *aphy = hw->priv;
1240 struct ath_softc *sc = aphy->sc;
c46917bb 1241 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 1242 struct ath_tx_control txctl;
1bc14880
BP
1243 int padpos, padsize;
1244 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
84642d6b 1245 int qnum;
528f0c6b 1246
8089cc47 1247 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
c46917bb
LR
1248 ath_print(common, ATH_DBG_XMIT,
1249 "ath9k: %s: TX in unexpected wiphy state "
1250 "%d\n", wiphy_name(hw->wiphy), aphy->state);
ee166a0e
JM
1251 goto exit;
1252 }
1253
96148326 1254 if (sc->ps_enabled) {
dc8c4585
JM
1255 /*
1256 * mac80211 does not set PM field for normal data frames, so we
1257 * need to update that based on the current PS mode.
1258 */
1259 if (ieee80211_is_data(hdr->frame_control) &&
1260 !ieee80211_is_nullfunc(hdr->frame_control) &&
1261 !ieee80211_has_pm(hdr->frame_control)) {
c46917bb
LR
1262 ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
1263 "while in PS mode\n");
dc8c4585
JM
1264 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1265 }
1266 }
1267
9a23f9ca
JM
1268 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
1269 /*
1270 * We are using PS-Poll and mac80211 can request TX while in
1271 * power save mode. Need to wake up hardware for the TX to be
1272 * completed and if needed, also for RX of buffered frames.
1273 */
9a23f9ca 1274 ath9k_ps_wakeup(sc);
fdf76622
VT
1275 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
1276 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca 1277 if (ieee80211_is_pspoll(hdr->frame_control)) {
c46917bb
LR
1278 ath_print(common, ATH_DBG_PS,
1279 "Sending PS-Poll to pick a buffered frame\n");
1b04b930 1280 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
9a23f9ca 1281 } else {
c46917bb
LR
1282 ath_print(common, ATH_DBG_PS,
1283 "Wake up to complete TX\n");
1b04b930 1284 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
9a23f9ca
JM
1285 }
1286 /*
1287 * The actual restore operation will happen only after
1288 * the sc_flags bit is cleared. We are just dropping
1289 * the ps_usecount here.
1290 */
1291 ath9k_ps_restore(sc);
1292 }
1293
528f0c6b 1294 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 1295
8feceb67
VT
1296 /*
1297 * As a temporary workaround, assign seq# here; this will likely need
1298 * to be cleaned up to work better with Beacon transmission and virtual
1299 * BSSes.
1300 */
1301 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
8feceb67 1302 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 1303 sc->tx.seq_no += 0x10;
8feceb67 1304 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 1305 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 1306 }
f078f209 1307
8feceb67 1308 /* Add the padding after the header if this is not already done */
1bc14880
BP
1309 padpos = ath9k_cmn_padpos(hdr->frame_control);
1310 padsize = padpos & 3;
1311 if (padsize && skb->len>padpos) {
8feceb67
VT
1312 if (skb_headroom(skb) < padsize)
1313 return -1;
1314 skb_push(skb, padsize);
1bc14880 1315 memmove(skb->data, skb->data + padsize, padpos);
8feceb67
VT
1316 }
1317
84642d6b
FF
1318 qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
1319 txctl.txq = &sc->tx.txq[qnum];
528f0c6b 1320
c46917bb 1321 ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 1322
c52f33d0 1323 if (ath_tx_start(hw, skb, &txctl) != 0) {
c46917bb 1324 ath_print(common, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 1325 goto exit;
8feceb67
VT
1326 }
1327
528f0c6b
S
1328 return 0;
1329exit:
1330 dev_kfree_skb_any(skb);
8feceb67 1331 return 0;
f078f209
LR
1332}
1333
8feceb67 1334static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 1335{
bce048d7
JM
1336 struct ath_wiphy *aphy = hw->priv;
1337 struct ath_softc *sc = aphy->sc;
af03abec 1338 struct ath_hw *ah = sc->sc_ah;
c46917bb 1339 struct ath_common *common = ath9k_hw_common(ah);
447a42c2 1340 int i;
f078f209 1341
4c483817
S
1342 mutex_lock(&sc->mutex);
1343
9580a222
JM
1344 aphy->state = ATH_WIPHY_INACTIVE;
1345
9a75c2ff
VN
1346 if (led_blink)
1347 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1348
c94dbff7 1349 cancel_delayed_work_sync(&sc->tx_complete_work);
9f42c2b6 1350 cancel_work_sync(&sc->paprd_work);
347809fc 1351 cancel_work_sync(&sc->hw_check_work);
c94dbff7 1352
447a42c2
RM
1353 for (i = 0; i < sc->num_sec_wiphy; i++) {
1354 if (sc->sec_wiphy[i])
1355 break;
1356 }
1357
1358 if (i == sc->num_sec_wiphy) {
c94dbff7
LR
1359 cancel_delayed_work_sync(&sc->wiphy_work);
1360 cancel_work_sync(&sc->chan_work);
1361 }
1362
9c84b797 1363 if (sc->sc_flags & SC_OP_INVALID) {
c46917bb 1364 ath_print(common, ATH_DBG_ANY, "Device not present\n");
4c483817 1365 mutex_unlock(&sc->mutex);
9c84b797
S
1366 return;
1367 }
8feceb67 1368
9580a222
JM
1369 if (ath9k_wiphy_started(sc)) {
1370 mutex_unlock(&sc->mutex);
1371 return; /* another wiphy still in use */
1372 }
1373
3867cf6a
S
1374 /* Ensure HW is awake when we try to shut it down. */
1375 ath9k_ps_wakeup(sc);
1376
766ec4a9 1377 if (ah->btcoex_hw.enabled) {
af03abec 1378 ath9k_hw_btcoex_disable(ah);
766ec4a9 1379 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1380 ath9k_btcoex_timer_pause(sc);
1773912b
VT
1381 }
1382
ff37e337
S
1383 /* make sure h/w will not generate any interrupt
1384 * before setting the invalid flag. */
af03abec 1385 ath9k_hw_set_interrupts(ah, 0);
ff37e337
S
1386
1387 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 1388 ath_drain_all_txq(sc, false);
ff37e337 1389 ath_stoprecv(sc);
af03abec 1390 ath9k_hw_phy_disable(ah);
ff37e337 1391 } else
b77f483f 1392 sc->rx.rxlink = NULL;
ff37e337 1393
ff37e337 1394 /* disable HAL and put h/w to sleep */
af03abec
LR
1395 ath9k_hw_disable(ah);
1396 ath9k_hw_configpcipowersave(ah, 1, 1);
3867cf6a
S
1397 ath9k_ps_restore(sc);
1398
1399 /* Finally, put the chip in FULL SLEEP mode */
9ecdef4b 1400 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
ff37e337
S
1401
1402 sc->sc_flags |= SC_OP_INVALID;
500c064d 1403
141b38b6
S
1404 mutex_unlock(&sc->mutex);
1405
c46917bb 1406 ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR
1407}
1408
8feceb67 1409static int ath9k_add_interface(struct ieee80211_hw *hw,
1ed32e4f 1410 struct ieee80211_vif *vif)
f078f209 1411{
bce048d7
JM
1412 struct ath_wiphy *aphy = hw->priv;
1413 struct ath_softc *sc = aphy->sc;
3069168c
PR
1414 struct ath_hw *ah = sc->sc_ah;
1415 struct ath_common *common = ath9k_hw_common(ah);
1ed32e4f 1416 struct ath_vif *avp = (void *)vif->drv_priv;
d97809db 1417 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 1418 int ret = 0;
8feceb67 1419
141b38b6
S
1420 mutex_lock(&sc->mutex);
1421
1ed32e4f 1422 switch (vif->type) {
05c914fe 1423 case NL80211_IFTYPE_STATION:
d97809db 1424 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 1425 break;
e51f3eff
BJ
1426 case NL80211_IFTYPE_WDS:
1427 ic_opmode = NL80211_IFTYPE_WDS;
1428 break;
05c914fe 1429 case NL80211_IFTYPE_ADHOC:
05c914fe 1430 case NL80211_IFTYPE_AP:
9cb5412b 1431 case NL80211_IFTYPE_MESH_POINT:
2c3db3d5
JM
1432 if (sc->nbcnvifs >= ATH_BCBUF) {
1433 ret = -ENOBUFS;
1434 goto out;
1435 }
1ed32e4f 1436 ic_opmode = vif->type;
f078f209
LR
1437 break;
1438 default:
c46917bb 1439 ath_print(common, ATH_DBG_FATAL,
1ed32e4f 1440 "Interface type %d not yet supported\n", vif->type);
2c3db3d5
JM
1441 ret = -EOPNOTSUPP;
1442 goto out;
f078f209
LR
1443 }
1444
c46917bb
LR
1445 ath_print(common, ATH_DBG_CONFIG,
1446 "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 1447
17d7904d 1448 /* Set the VIF opmode */
5640b08e
S
1449 avp->av_opmode = ic_opmode;
1450 avp->av_bslot = -1;
1451
2c3db3d5 1452 sc->nvifs++;
8ca21f01 1453
364734fa 1454 ath9k_set_bssid_mask(hw, vif);
8ca21f01 1455
2c3db3d5
JM
1456 if (sc->nvifs > 1)
1457 goto out; /* skip global settings for secondary vif */
1458
b238e90e 1459 if (ic_opmode == NL80211_IFTYPE_AP) {
3069168c 1460 ath9k_hw_set_tsfadjust(ah, 1);
b238e90e
S
1461 sc->sc_flags |= SC_OP_TSF_RESET;
1462 }
5640b08e 1463
5640b08e 1464 /* Set the device opmode */
3069168c 1465 ah->opmode = ic_opmode;
5640b08e 1466
4e30ffa2
VN
1467 /*
1468 * Enable MIB interrupts when there are hardware phy counters.
1469 * Note we only do this (at the moment) for station mode.
1470 */
1ed32e4f
JB
1471 if ((vif->type == NL80211_IFTYPE_STATION) ||
1472 (vif->type == NL80211_IFTYPE_ADHOC) ||
1473 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
3448f912
LR
1474 if (ah->config.enable_ani)
1475 ah->imask |= ATH9K_INT_MIB;
3069168c 1476 ah->imask |= ATH9K_INT_TSFOOR;
4af9cf4f
S
1477 }
1478
3069168c 1479 ath9k_hw_set_interrupts(ah, ah->imask);
4e30ffa2 1480
1ed32e4f
JB
1481 if (vif->type == NL80211_IFTYPE_AP ||
1482 vif->type == NL80211_IFTYPE_ADHOC ||
6c3118e2
VT
1483 vif->type == NL80211_IFTYPE_MONITOR) {
1484 sc->sc_flags |= SC_OP_ANI_RUN;
3d536acf 1485 ath_start_ani(common);
6c3118e2 1486 }
6f255425 1487
2c3db3d5 1488out:
141b38b6 1489 mutex_unlock(&sc->mutex);
2c3db3d5 1490 return ret;
f078f209
LR
1491}
1492
8feceb67 1493static void ath9k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1494 struct ieee80211_vif *vif)
f078f209 1495{
bce048d7
JM
1496 struct ath_wiphy *aphy = hw->priv;
1497 struct ath_softc *sc = aphy->sc;
c46917bb 1498 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1ed32e4f 1499 struct ath_vif *avp = (void *)vif->drv_priv;
2c3db3d5 1500 int i;
f078f209 1501
c46917bb 1502 ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 1503
141b38b6
S
1504 mutex_lock(&sc->mutex);
1505
6f255425 1506 /* Stop ANI */
6c3118e2 1507 sc->sc_flags &= ~SC_OP_ANI_RUN;
3d536acf 1508 del_timer_sync(&common->ani.timer);
580f0b8a 1509
8feceb67 1510 /* Reclaim beacon resources */
9cb5412b
PE
1511 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
1512 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
1513 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
5f70a88f 1514 ath9k_ps_wakeup(sc);
b77f483f 1515 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
5f70a88f 1516 ath9k_ps_restore(sc);
580f0b8a 1517 }
f078f209 1518
74401773 1519 ath_beacon_return(sc, avp);
8feceb67 1520 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 1521
2c3db3d5 1522 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1ed32e4f 1523 if (sc->beacon.bslot[i] == vif) {
2c3db3d5
JM
1524 printk(KERN_DEBUG "%s: vif had allocated beacon "
1525 "slot\n", __func__);
1526 sc->beacon.bslot[i] = NULL;
c52f33d0 1527 sc->beacon.bslot_aphy[i] = NULL;
2c3db3d5
JM
1528 }
1529 }
1530
17d7904d 1531 sc->nvifs--;
141b38b6
S
1532
1533 mutex_unlock(&sc->mutex);
f078f209
LR
1534}
1535
fbab7390 1536static void ath9k_enable_ps(struct ath_softc *sc)
3f7c5c10 1537{
3069168c
PR
1538 struct ath_hw *ah = sc->sc_ah;
1539
3f7c5c10 1540 sc->ps_enabled = true;
3069168c
PR
1541 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1542 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1543 ah->imask |= ATH9K_INT_TIM_TIMER;
1544 ath9k_hw_set_interrupts(ah, ah->imask);
3f7c5c10 1545 }
fdf76622 1546 ath9k_hw_setrxabort(ah, 1);
3f7c5c10 1547 }
3f7c5c10
SB
1548}
1549
845d708e
SB
1550static void ath9k_disable_ps(struct ath_softc *sc)
1551{
1552 struct ath_hw *ah = sc->sc_ah;
1553
1554 sc->ps_enabled = false;
1555 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1556 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1557 ath9k_hw_setrxabort(ah, 0);
1558 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1559 PS_WAIT_FOR_CAB |
1560 PS_WAIT_FOR_PSPOLL_DATA |
1561 PS_WAIT_FOR_TX_ACK);
1562 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1563 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1564 ath9k_hw_set_interrupts(ah, ah->imask);
1565 }
1566 }
1567
1568}
1569
e8975581 1570static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1571{
bce048d7
JM
1572 struct ath_wiphy *aphy = hw->priv;
1573 struct ath_softc *sc = aphy->sc;
3430098a
FF
1574 struct ath_hw *ah = sc->sc_ah;
1575 struct ath_common *common = ath9k_hw_common(ah);
e8975581 1576 struct ieee80211_conf *conf = &hw->conf;
194b7c13 1577 bool disable_radio;
f078f209 1578
aa33de09 1579 mutex_lock(&sc->mutex);
141b38b6 1580
194b7c13
LR
1581 /*
1582 * Leave this as the first check because we need to turn on the
1583 * radio if it was disabled before prior to processing the rest
1584 * of the changes. Likewise we must only disable the radio towards
1585 * the end.
1586 */
64839170 1587 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
194b7c13
LR
1588 bool enable_radio;
1589 bool all_wiphys_idle;
1590 bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
64839170
LR
1591
1592 spin_lock_bh(&sc->wiphy_lock);
1593 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
194b7c13
LR
1594 ath9k_set_wiphy_idle(aphy, idle);
1595
11446011 1596 enable_radio = (!idle && all_wiphys_idle);
194b7c13
LR
1597
1598 /*
1599 * After we unlock here its possible another wiphy
1600 * can be re-renabled so to account for that we will
1601 * only disable the radio toward the end of this routine
1602 * if by then all wiphys are still idle.
1603 */
64839170
LR
1604 spin_unlock_bh(&sc->wiphy_lock);
1605
194b7c13 1606 if (enable_radio) {
1dbfd9d4 1607 sc->ps_idle = false;
68a89116 1608 ath_radio_enable(sc, hw);
c46917bb
LR
1609 ath_print(common, ATH_DBG_CONFIG,
1610 "not-idle: enabling radio\n");
64839170
LR
1611 }
1612 }
1613
e7824a50
LR
1614 /*
1615 * We just prepare to enable PS. We have to wait until our AP has
1616 * ACK'd our null data frame to disable RX otherwise we'll ignore
1617 * those ACKs and end up retransmitting the same null data frames.
1618 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1619 */
3cbb5dd7 1620 if (changed & IEEE80211_CONF_CHANGE_PS) {
8ab2cd09
LR
1621 unsigned long flags;
1622 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fbab7390
SB
1623 if (conf->flags & IEEE80211_CONF_PS)
1624 ath9k_enable_ps(sc);
845d708e
SB
1625 else
1626 ath9k_disable_ps(sc);
8ab2cd09 1627 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3cbb5dd7
VN
1628 }
1629
199afd9d
S
1630 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1631 if (conf->flags & IEEE80211_CONF_MONITOR) {
1632 ath_print(common, ATH_DBG_CONFIG,
1633 "HW opmode set to Monitor mode\n");
1634 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1635 }
1636 }
1637
4797938c 1638 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 1639 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 1640 int pos = curchan->hw_value;
3430098a
FF
1641 int old_pos = -1;
1642 unsigned long flags;
1643
1644 if (ah->curchan)
1645 old_pos = ah->curchan - &ah->channels[0];
ae5eb026 1646
0e2dedf9
JM
1647 aphy->chan_idx = pos;
1648 aphy->chan_is_ht = conf_is_ht(conf);
5ee08656
FF
1649 if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
1650 sc->sc_flags |= SC_OP_OFFCHANNEL;
1651 else
1652 sc->sc_flags &= ~SC_OP_OFFCHANNEL;
0e2dedf9 1653
8089cc47
JM
1654 if (aphy->state == ATH_WIPHY_SCAN ||
1655 aphy->state == ATH_WIPHY_ACTIVE)
1656 ath9k_wiphy_pause_all_forced(sc, aphy);
1657 else {
1658 /*
1659 * Do not change operational channel based on a paused
1660 * wiphy changes.
1661 */
1662 goto skip_chan_change;
1663 }
0e2dedf9 1664
c46917bb
LR
1665 ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
1666 curchan->center_freq);
f078f209 1667
5f8e077c 1668 /* XXX: remove me eventualy */
0e2dedf9 1669 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 1670
ecf70441 1671 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 1672
3430098a
FF
1673 /* update survey stats for the old channel before switching */
1674 spin_lock_irqsave(&common->cc_lock, flags);
1675 ath_update_survey_stats(sc);
1676 spin_unlock_irqrestore(&common->cc_lock, flags);
1677
1678 /*
1679 * If the operating channel changes, change the survey in-use flags
1680 * along with it.
1681 * Reset the survey data for the new channel, unless we're switching
1682 * back to the operating channel from an off-channel operation.
1683 */
1684 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1685 sc->cur_survey != &sc->survey[pos]) {
1686
1687 if (sc->cur_survey)
1688 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1689
1690 sc->cur_survey = &sc->survey[pos];
1691
1692 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1693 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1694 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1695 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1696 }
1697
0e2dedf9 1698 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
c46917bb
LR
1699 ath_print(common, ATH_DBG_FATAL,
1700 "Unable to set channel\n");
aa33de09 1701 mutex_unlock(&sc->mutex);
e11602b7
S
1702 return -EINVAL;
1703 }
3430098a
FF
1704
1705 /*
1706 * The most recent snapshot of channel->noisefloor for the old
1707 * channel is only available after the hardware reset. Copy it to
1708 * the survey stats now.
1709 */
1710 if (old_pos >= 0)
1711 ath_update_survey_nf(sc, old_pos);
094d05dc 1712 }
f078f209 1713
8089cc47 1714skip_chan_change:
c9f6a656 1715 if (changed & IEEE80211_CONF_CHANGE_POWER) {
17d7904d 1716 sc->config.txpowlimit = 2 * conf->power_level;
c9f6a656
LR
1717 ath_update_txpow(sc);
1718 }
f078f209 1719
194b7c13
LR
1720 spin_lock_bh(&sc->wiphy_lock);
1721 disable_radio = ath9k_all_wiphys_idle(sc);
1722 spin_unlock_bh(&sc->wiphy_lock);
1723
64839170 1724 if (disable_radio) {
c46917bb 1725 ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
1dbfd9d4 1726 sc->ps_idle = true;
68a89116 1727 ath_radio_disable(sc, hw);
64839170
LR
1728 }
1729
aa33de09 1730 mutex_unlock(&sc->mutex);
141b38b6 1731
f078f209
LR
1732 return 0;
1733}
1734
8feceb67
VT
1735#define SUPPORTED_FILTERS \
1736 (FIF_PROMISC_IN_BSS | \
1737 FIF_ALLMULTI | \
1738 FIF_CONTROL | \
af6a3fc7 1739 FIF_PSPOLL | \
8feceb67
VT
1740 FIF_OTHER_BSS | \
1741 FIF_BCN_PRBRESP_PROMISC | \
1742 FIF_FCSFAIL)
c83be688 1743
8feceb67
VT
1744/* FIXME: sc->sc_full_reset ? */
1745static void ath9k_configure_filter(struct ieee80211_hw *hw,
1746 unsigned int changed_flags,
1747 unsigned int *total_flags,
3ac64bee 1748 u64 multicast)
8feceb67 1749{
bce048d7
JM
1750 struct ath_wiphy *aphy = hw->priv;
1751 struct ath_softc *sc = aphy->sc;
8feceb67 1752 u32 rfilt;
f078f209 1753
8feceb67
VT
1754 changed_flags &= SUPPORTED_FILTERS;
1755 *total_flags &= SUPPORTED_FILTERS;
f078f209 1756
b77f483f 1757 sc->rx.rxfilter = *total_flags;
aa68aeaa 1758 ath9k_ps_wakeup(sc);
8feceb67
VT
1759 rfilt = ath_calcrxfilter(sc);
1760 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 1761 ath9k_ps_restore(sc);
f078f209 1762
c46917bb
LR
1763 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
1764 "Set HW RX filter: 0x%x\n", rfilt);
8feceb67 1765}
f078f209 1766
4ca77860
JB
1767static int ath9k_sta_add(struct ieee80211_hw *hw,
1768 struct ieee80211_vif *vif,
1769 struct ieee80211_sta *sta)
8feceb67 1770{
bce048d7
JM
1771 struct ath_wiphy *aphy = hw->priv;
1772 struct ath_softc *sc = aphy->sc;
f078f209 1773
4ca77860
JB
1774 ath_node_attach(sc, sta);
1775
1776 return 0;
1777}
1778
1779static int ath9k_sta_remove(struct ieee80211_hw *hw,
1780 struct ieee80211_vif *vif,
1781 struct ieee80211_sta *sta)
1782{
1783 struct ath_wiphy *aphy = hw->priv;
1784 struct ath_softc *sc = aphy->sc;
1785
1786 ath_node_detach(sc, sta);
1787
1788 return 0;
f078f209
LR
1789}
1790
141b38b6 1791static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 1792 const struct ieee80211_tx_queue_params *params)
f078f209 1793{
bce048d7
JM
1794 struct ath_wiphy *aphy = hw->priv;
1795 struct ath_softc *sc = aphy->sc;
c46917bb 1796 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67
VT
1797 struct ath9k_tx_queue_info qi;
1798 int ret = 0, qnum;
f078f209 1799
8feceb67
VT
1800 if (queue >= WME_NUM_AC)
1801 return 0;
f078f209 1802
141b38b6
S
1803 mutex_lock(&sc->mutex);
1804
1ffb0610
S
1805 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1806
8feceb67
VT
1807 qi.tqi_aifs = params->aifs;
1808 qi.tqi_cwmin = params->cw_min;
1809 qi.tqi_cwmax = params->cw_max;
1810 qi.tqi_burstTime = params->txop;
1811 qnum = ath_get_hal_qnum(queue, sc);
f078f209 1812
c46917bb
LR
1813 ath_print(common, ATH_DBG_CONFIG,
1814 "Configure tx [queue/halq] [%d/%d], "
1815 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1816 queue, qnum, params->aifs, params->cw_min,
1817 params->cw_max, params->txop);
f078f209 1818
8feceb67
VT
1819 ret = ath_txq_update(sc, qnum, &qi);
1820 if (ret)
c46917bb 1821 ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 1822
94db2936 1823 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
1d2231e2 1824 if ((qnum == sc->tx.hwq_map[WME_AC_BE]) && !ret)
94db2936
VN
1825 ath_beaconq_config(sc);
1826
141b38b6
S
1827 mutex_unlock(&sc->mutex);
1828
8feceb67
VT
1829 return ret;
1830}
f078f209 1831
8feceb67
VT
1832static int ath9k_set_key(struct ieee80211_hw *hw,
1833 enum set_key_cmd cmd,
dc822b5d
JB
1834 struct ieee80211_vif *vif,
1835 struct ieee80211_sta *sta,
8feceb67
VT
1836 struct ieee80211_key_conf *key)
1837{
bce048d7
JM
1838 struct ath_wiphy *aphy = hw->priv;
1839 struct ath_softc *sc = aphy->sc;
c46917bb 1840 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67 1841 int ret = 0;
f078f209 1842
b3bd89ce
JM
1843 if (modparam_nohwcrypt)
1844 return -ENOSPC;
1845
141b38b6 1846 mutex_lock(&sc->mutex);
3cbb5dd7 1847 ath9k_ps_wakeup(sc);
c46917bb 1848 ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 1849
8feceb67
VT
1850 switch (cmd) {
1851 case SET_KEY:
040e539e 1852 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM
1853 if (ret >= 0) {
1854 key->hw_key_idx = ret;
8feceb67
VT
1855 /* push IV and Michael MIC generation to stack */
1856 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
97359d12 1857 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
8feceb67 1858 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
97359d12
JB
1859 if (sc->sc_ah->sw_mgmt_crypto &&
1860 key->cipher == WLAN_CIPHER_SUITE_CCMP)
0ced0e17 1861 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 1862 ret = 0;
8feceb67
VT
1863 }
1864 break;
1865 case DISABLE_KEY:
040e539e 1866 ath_key_delete(common, key);
8feceb67
VT
1867 break;
1868 default:
1869 ret = -EINVAL;
1870 }
f078f209 1871
3cbb5dd7 1872 ath9k_ps_restore(sc);
141b38b6
S
1873 mutex_unlock(&sc->mutex);
1874
8feceb67
VT
1875 return ret;
1876}
f078f209 1877
8feceb67
VT
1878static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1879 struct ieee80211_vif *vif,
1880 struct ieee80211_bss_conf *bss_conf,
1881 u32 changed)
1882{
bce048d7
JM
1883 struct ath_wiphy *aphy = hw->priv;
1884 struct ath_softc *sc = aphy->sc;
2d0ddec5 1885 struct ath_hw *ah = sc->sc_ah;
1510718d 1886 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 1887 struct ath_vif *avp = (void *)vif->drv_priv;
0005baf4 1888 int slottime;
c6089ccc 1889 int error;
f078f209 1890
141b38b6
S
1891 mutex_lock(&sc->mutex);
1892
c6089ccc
S
1893 if (changed & BSS_CHANGED_BSSID) {
1894 /* Set BSSID */
1895 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1896 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1510718d 1897 common->curaid = 0;
f2b2143e 1898 ath9k_hw_write_associd(ah);
2d0ddec5 1899
c6089ccc
S
1900 /* Set aggregation protection mode parameters */
1901 sc->config.ath_aggr_prot = 0;
2d0ddec5 1902
c6089ccc
S
1903 /* Only legacy IBSS for now */
1904 if (vif->type == NL80211_IFTYPE_ADHOC)
1905 ath_update_chainmask(sc, 0);
2d0ddec5 1906
c6089ccc
S
1907 ath_print(common, ATH_DBG_CONFIG,
1908 "BSSID: %pM aid: 0x%x\n",
1909 common->curbssid, common->curaid);
2d0ddec5 1910
c6089ccc
S
1911 /* need to reconfigure the beacon */
1912 sc->sc_flags &= ~SC_OP_BEACONS ;
1913 }
2d0ddec5 1914
c6089ccc
S
1915 /* Enable transmission of beacons (AP, IBSS, MESH) */
1916 if ((changed & BSS_CHANGED_BEACON) ||
1917 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
1918 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1919 error = ath_beacon_alloc(aphy, vif);
1920 if (!error)
1921 ath_beacon_config(sc, vif);
0005baf4
FF
1922 }
1923
1924 if (changed & BSS_CHANGED_ERP_SLOT) {
1925 if (bss_conf->use_short_slot)
1926 slottime = 9;
1927 else
1928 slottime = 20;
1929 if (vif->type == NL80211_IFTYPE_AP) {
1930 /*
1931 * Defer update, so that connected stations can adjust
1932 * their settings at the same time.
1933 * See beacon.c for more details
1934 */
1935 sc->beacon.slottime = slottime;
1936 sc->beacon.updateslot = UPDATE;
1937 } else {
1938 ah->slottime = slottime;
1939 ath9k_hw_init_global_settings(ah);
1940 }
2d0ddec5
JB
1941 }
1942
c6089ccc
S
1943 /* Disable transmission of beacons */
1944 if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
1945 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2d0ddec5 1946
c6089ccc
S
1947 if (changed & BSS_CHANGED_BEACON_INT) {
1948 sc->beacon_interval = bss_conf->beacon_int;
1949 /*
1950 * In case of AP mode, the HW TSF has to be reset
1951 * when the beacon interval changes.
1952 */
1953 if (vif->type == NL80211_IFTYPE_AP) {
1954 sc->sc_flags |= SC_OP_TSF_RESET;
1955 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2d0ddec5
JB
1956 error = ath_beacon_alloc(aphy, vif);
1957 if (!error)
1958 ath_beacon_config(sc, vif);
c6089ccc
S
1959 } else {
1960 ath_beacon_config(sc, vif);
2d0ddec5
JB
1961 }
1962 }
1963
8feceb67 1964 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
c46917bb
LR
1965 ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
1966 bss_conf->use_short_preamble);
8feceb67
VT
1967 if (bss_conf->use_short_preamble)
1968 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
1969 else
1970 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
1971 }
f078f209 1972
8feceb67 1973 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
c46917bb
LR
1974 ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
1975 bss_conf->use_cts_prot);
8feceb67
VT
1976 if (bss_conf->use_cts_prot &&
1977 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
1978 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
1979 else
1980 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
1981 }
f078f209 1982
8feceb67 1983 if (changed & BSS_CHANGED_ASSOC) {
c46917bb 1984 ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 1985 bss_conf->assoc);
5640b08e 1986 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 1987 }
141b38b6
S
1988
1989 mutex_unlock(&sc->mutex);
8feceb67 1990}
f078f209 1991
8feceb67
VT
1992static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
1993{
1994 u64 tsf;
bce048d7
JM
1995 struct ath_wiphy *aphy = hw->priv;
1996 struct ath_softc *sc = aphy->sc;
f078f209 1997
141b38b6
S
1998 mutex_lock(&sc->mutex);
1999 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2000 mutex_unlock(&sc->mutex);
f078f209 2001
8feceb67
VT
2002 return tsf;
2003}
f078f209 2004
3b5d665b
AF
2005static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2006{
bce048d7
JM
2007 struct ath_wiphy *aphy = hw->priv;
2008 struct ath_softc *sc = aphy->sc;
3b5d665b 2009
141b38b6
S
2010 mutex_lock(&sc->mutex);
2011 ath9k_hw_settsf64(sc->sc_ah, tsf);
2012 mutex_unlock(&sc->mutex);
3b5d665b
AF
2013}
2014
8feceb67
VT
2015static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2016{
bce048d7
JM
2017 struct ath_wiphy *aphy = hw->priv;
2018 struct ath_softc *sc = aphy->sc;
c83be688 2019
141b38b6 2020 mutex_lock(&sc->mutex);
21526d57
LR
2021
2022 ath9k_ps_wakeup(sc);
141b38b6 2023 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR
2024 ath9k_ps_restore(sc);
2025
141b38b6 2026 mutex_unlock(&sc->mutex);
8feceb67 2027}
f078f209 2028
8feceb67 2029static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 2030 struct ieee80211_vif *vif,
141b38b6
S
2031 enum ieee80211_ampdu_mlme_action action,
2032 struct ieee80211_sta *sta,
2033 u16 tid, u16 *ssn)
8feceb67 2034{
bce048d7
JM
2035 struct ath_wiphy *aphy = hw->priv;
2036 struct ath_softc *sc = aphy->sc;
8feceb67 2037 int ret = 0;
f078f209 2038
85ad181e
JB
2039 local_bh_disable();
2040
8feceb67
VT
2041 switch (action) {
2042 case IEEE80211_AMPDU_RX_START:
dca3edb8
S
2043 if (!(sc->sc_flags & SC_OP_RXAGGR))
2044 ret = -ENOTSUPP;
8feceb67
VT
2045 break;
2046 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT
2047 break;
2048 case IEEE80211_AMPDU_TX_START:
8b685ba9 2049 ath9k_ps_wakeup(sc);
231c3a1f
FF
2050 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2051 if (!ret)
2052 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2053 ath9k_ps_restore(sc);
8feceb67
VT
2054 break;
2055 case IEEE80211_AMPDU_TX_STOP:
8b685ba9 2056 ath9k_ps_wakeup(sc);
f83da965 2057 ath_tx_aggr_stop(sc, sta, tid);
c951ad35 2058 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2059 ath9k_ps_restore(sc);
8feceb67 2060 break;
b1720231 2061 case IEEE80211_AMPDU_TX_OPERATIONAL:
8b685ba9 2062 ath9k_ps_wakeup(sc);
8469cdef 2063 ath_tx_aggr_resume(sc, sta, tid);
8b685ba9 2064 ath9k_ps_restore(sc);
8469cdef 2065 break;
8feceb67 2066 default:
c46917bb
LR
2067 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
2068 "Unknown AMPDU action\n");
8feceb67
VT
2069 }
2070
85ad181e
JB
2071 local_bh_enable();
2072
8feceb67 2073 return ret;
f078f209
LR
2074}
2075
62dad5b0
BP
2076static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2077 struct survey_info *survey)
2078{
2079 struct ath_wiphy *aphy = hw->priv;
2080 struct ath_softc *sc = aphy->sc;
3430098a 2081 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39162dbe 2082 struct ieee80211_supported_band *sband;
3430098a
FF
2083 struct ieee80211_channel *chan;
2084 unsigned long flags;
2085 int pos;
2086
2087 spin_lock_irqsave(&common->cc_lock, flags);
2088 if (idx == 0)
2089 ath_update_survey_stats(sc);
39162dbe
FF
2090
2091 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2092 if (sband && idx >= sband->n_channels) {
2093 idx -= sband->n_channels;
2094 sband = NULL;
2095 }
62dad5b0 2096
39162dbe
FF
2097 if (!sband)
2098 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
62dad5b0 2099
3430098a
FF
2100 if (!sband || idx >= sband->n_channels) {
2101 spin_unlock_irqrestore(&common->cc_lock, flags);
2102 return -ENOENT;
4f1a5a4b 2103 }
62dad5b0 2104
3430098a
FF
2105 chan = &sband->channels[idx];
2106 pos = chan->hw_value;
2107 memcpy(survey, &sc->survey[pos], sizeof(*survey));
2108 survey->channel = chan;
2109 spin_unlock_irqrestore(&common->cc_lock, flags);
2110
62dad5b0
BP
2111 return 0;
2112}
2113
0c98de65
S
2114static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2115{
bce048d7
JM
2116 struct ath_wiphy *aphy = hw->priv;
2117 struct ath_softc *sc = aphy->sc;
0c98de65 2118
3d832611 2119 mutex_lock(&sc->mutex);
8089cc47 2120 if (ath9k_wiphy_scanning(sc)) {
8089cc47 2121 /*
30888338
LR
2122 * There is a race here in mac80211 but fixing it requires
2123 * we revisit how we handle the scan complete callback.
2124 * After mac80211 fixes we will not have configured hardware
2125 * to the home channel nor would we have configured the RX
2126 * filter yet.
8089cc47 2127 */
3d832611 2128 mutex_unlock(&sc->mutex);
8089cc47
JM
2129 return;
2130 }
2131
2132 aphy->state = ATH_WIPHY_SCAN;
2133 ath9k_wiphy_pause_all_forced(sc, aphy);
3d832611 2134 mutex_unlock(&sc->mutex);
0c98de65
S
2135}
2136
30888338
LR
2137/*
2138 * XXX: this requires a revisit after the driver
2139 * scan_complete gets moved to another place/removed in mac80211.
2140 */
0c98de65
S
2141static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2142{
bce048d7
JM
2143 struct ath_wiphy *aphy = hw->priv;
2144 struct ath_softc *sc = aphy->sc;
0c98de65 2145
3d832611 2146 mutex_lock(&sc->mutex);
8089cc47 2147 aphy->state = ATH_WIPHY_ACTIVE;
3d832611 2148 mutex_unlock(&sc->mutex);
0c98de65
S
2149}
2150
e239d859
FF
2151static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
2152{
2153 struct ath_wiphy *aphy = hw->priv;
2154 struct ath_softc *sc = aphy->sc;
2155 struct ath_hw *ah = sc->sc_ah;
2156
2157 mutex_lock(&sc->mutex);
2158 ah->coverage_class = coverage_class;
2159 ath9k_hw_init_global_settings(ah);
2160 mutex_unlock(&sc->mutex);
2161}
2162
6baff7f9 2163struct ieee80211_ops ath9k_ops = {
8feceb67
VT
2164 .tx = ath9k_tx,
2165 .start = ath9k_start,
2166 .stop = ath9k_stop,
2167 .add_interface = ath9k_add_interface,
2168 .remove_interface = ath9k_remove_interface,
2169 .config = ath9k_config,
8feceb67 2170 .configure_filter = ath9k_configure_filter,
4ca77860
JB
2171 .sta_add = ath9k_sta_add,
2172 .sta_remove = ath9k_sta_remove,
8feceb67 2173 .conf_tx = ath9k_conf_tx,
8feceb67 2174 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2175 .set_key = ath9k_set_key,
8feceb67 2176 .get_tsf = ath9k_get_tsf,
3b5d665b 2177 .set_tsf = ath9k_set_tsf,
8feceb67 2178 .reset_tsf = ath9k_reset_tsf,
4233df6b 2179 .ampdu_action = ath9k_ampdu_action,
62dad5b0 2180 .get_survey = ath9k_get_survey,
0c98de65
S
2181 .sw_scan_start = ath9k_sw_scan_start,
2182 .sw_scan_complete = ath9k_sw_scan_complete,
3b319aae 2183 .rfkill_poll = ath9k_rfkill_poll_state,
e239d859 2184 .set_coverage_class = ath9k_set_coverage_class,
8feceb67 2185};
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