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ath9k: Further fix for mesh beaconing
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
69081624 18#include <linux/delay.h>
394cf0a1 19#include "ath9k.h"
af03abec 20#include "btcoex.h"
f078f209 21
ff37e337
S		 22static u8 parse_mpdudensity(u8 mpdudensity)
23{
24 /*
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
26 * 0 for no restriction
27 * 1 for 1/4 us
28 * 2 for 1/2 us
29 * 3 for 1 us
30 * 4 for 2 us
31 * 5 for 4 us
32 * 6 for 8 us
33 * 7 for 16 us
34 */
35 switch (mpdudensity) {
36 case 0:
37 return 0;
38 case 1:
39 case 2:
40 case 3:
41 /* Our lower layer calculations limit our precision to
42 1 microsecond */
43 return 1;
44 case 4:
45 return 2;
46 case 5:
47 return 4;
48 case 6:
49 return 8;
50 case 7:
51 return 16;
52 default:
53 return 0;
54 }
55}
56
69081624
VT		 57static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
58{
59 bool pending = false;
60
61 spin_lock_bh(&txq->axq_lock);
62
63 if (txq->axq_depth || !list_empty(&txq->axq_acq))
64 pending = true;
69081624
VT		 65
66 spin_unlock_bh(&txq->axq_lock);
67 return pending;
68}
69
6d79cb4c 70static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR		 71{
72 unsigned long flags;
73 bool ret;
74
9ecdef4b
LR		 75 spin_lock_irqsave(&sc->sc_pm_lock, flags);
76 ret = ath9k_hw_setpower(sc->sc_ah, mode);
77 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR		 78
79 return ret;
80}
81
a91d75ae
LR		 82void ath9k_ps_wakeup(struct ath_softc *sc)
83{
898c914a 84 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae 85 unsigned long flags;
fbb078fc 86 enum ath9k_power_mode power_mode;
a91d75ae
LR		 87
88 spin_lock_irqsave(&sc->sc_pm_lock, flags);
89 if (++sc->ps_usecount != 1)
90 goto unlock;
91
fbb078fc 92 power_mode = sc->sc_ah->power_mode;
9ecdef4b 93 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae 94
898c914a
FF		 95 /*
96 * While the hardware is asleep, the cycle counters contain no
97 * useful data. Better clear them now so that they don't mess up
98 * survey data results.
99 */
fbb078fc
FF		 100 if (power_mode != ATH9K_PM_AWAKE) {
101 spin_lock(&common->cc_lock);
102 ath_hw_cycle_counters_update(common);
103 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
104 spin_unlock(&common->cc_lock);
105 }
898c914a 106
a91d75ae
LR		 107 unlock:
108 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
109}
110
111void ath9k_ps_restore(struct ath_softc *sc)
112{
898c914a 113 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae
LR		 114 unsigned long flags;
115
116 spin_lock_irqsave(&sc->sc_pm_lock, flags);
117 if (--sc->ps_usecount != 0)
118 goto unlock;
119
898c914a
FF		 120 spin_lock(&common->cc_lock);
121 ath_hw_cycle_counters_update(common);
122 spin_unlock(&common->cc_lock);
123
1dbfd9d4
VN		 124 if (sc->ps_idle)
125 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
126 else if (sc->ps_enabled &&
127 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
1b04b930
S		 128 PS_WAIT_FOR_CAB |
129 PS_WAIT_FOR_PSPOLL_DATA |
130 PS_WAIT_FOR_TX_ACK)))
9ecdef4b 131 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
a91d75ae
LR		 132
133 unlock:
134 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
135}
136
5ee08656
FF		 137static void ath_start_ani(struct ath_common *common)
138{
139 struct ath_hw *ah = common->ah;
140 unsigned long timestamp = jiffies_to_msecs(jiffies);
141 struct ath_softc *sc = (struct ath_softc *) common->priv;
142
143 if (!(sc->sc_flags & SC_OP_ANI_RUN))
144 return;
145
146 if (sc->sc_flags & SC_OP_OFFCHANNEL)
147 return;
148
149 common->ani.longcal_timer = timestamp;
150 common->ani.shortcal_timer = timestamp;
151 common->ani.checkani_timer = timestamp;
152
153 mod_timer(&common->ani.timer,
154 jiffies +
155 msecs_to_jiffies((u32)ah->config.ani_poll_interval));
156}
157
3430098a
FF		 158static void ath_update_survey_nf(struct ath_softc *sc, int channel)
159{
160 struct ath_hw *ah = sc->sc_ah;
161 struct ath9k_channel *chan = &ah->channels[channel];
162 struct survey_info *survey = &sc->survey[channel];
163
164 if (chan->noisefloor) {
165 survey->filled |= SURVEY_INFO_NOISE_DBM;
166 survey->noise = chan->noisefloor;
167 }
168}
169
cb8d61de
FF		 170/*
171 * Updates the survey statistics and returns the busy time since last
172 * update in %, if the measurement duration was long enough for the
173 * result to be useful, -1 otherwise.
174 */
175static int ath_update_survey_stats(struct ath_softc *sc)
3430098a
FF		 176{
177 struct ath_hw *ah = sc->sc_ah;
178 struct ath_common *common = ath9k_hw_common(ah);
179 int pos = ah->curchan - &ah->channels[0];
180 struct survey_info *survey = &sc->survey[pos];
181 struct ath_cycle_counters *cc = &common->cc_survey;
182 unsigned int div = common->clockrate * 1000;
cb8d61de 183 int ret = 0;
3430098a 184
0845735e 185 if (!ah->curchan)
cb8d61de 186 return -1;
0845735e 187
898c914a
FF		 188 if (ah->power_mode == ATH9K_PM_AWAKE)
189 ath_hw_cycle_counters_update(common);
3430098a
FF		 190
191 if (cc->cycles > 0) {
192 survey->filled |= SURVEY_INFO_CHANNEL_TIME |
193 SURVEY_INFO_CHANNEL_TIME_BUSY |
194 SURVEY_INFO_CHANNEL_TIME_RX |
195 SURVEY_INFO_CHANNEL_TIME_TX;
196 survey->channel_time += cc->cycles / div;
197 survey->channel_time_busy += cc->rx_busy / div;
198 survey->channel_time_rx += cc->rx_frame / div;
199 survey->channel_time_tx += cc->tx_frame / div;
200 }
cb8d61de
FF		 201
202 if (cc->cycles < div)
203 return -1;
204
205 if (cc->cycles > 0)
206 ret = cc->rx_busy * 100 / cc->cycles;
207
3430098a
FF		 208 memset(cc, 0, sizeof(*cc));
209
210 ath_update_survey_nf(sc, pos);
cb8d61de
FF		 211
212 return ret;
3430098a
FF		 213}
214
ff37e337
S		 215/*
216 * Set/change channels. If the channel is really being changed, it's done
217 * by reseting the chip. To accomplish this we must first cleanup any pending
218 * DMA, then restart stuff.
219*/
5595f119 220static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
0e2dedf9 221 struct ath9k_channel *hchan)
ff37e337 222{
cbe61d8a 223 struct ath_hw *ah = sc->sc_ah;
c46917bb 224 struct ath_common *common = ath9k_hw_common(ah);
25c56eec 225 struct ieee80211_conf *conf = &common->hw->conf;
ff37e337 226 bool fastcc = true, stopped;
ae8d2858 227 struct ieee80211_channel *channel = hw->conf.channel;
20bd2a09 228 struct ath9k_hw_cal_data *caldata = NULL;
ae8d2858 229 int r;
ff37e337
S		 230
231 if (sc->sc_flags & SC_OP_INVALID)
232 return -EIO;
233
cb8d61de
FF		 234 sc->hw_busy_count = 0;
235
5ee08656
FF		 236 del_timer_sync(&common->ani.timer);
237 cancel_work_sync(&sc->paprd_work);
238 cancel_work_sync(&sc->hw_check_work);
239 cancel_delayed_work_sync(&sc->tx_complete_work);
181fb18d 240 cancel_delayed_work_sync(&sc->hw_pll_work);
5ee08656 241
3cbb5dd7
VN		 242 ath9k_ps_wakeup(sc);
243
6a6733f2
LR		 244 spin_lock_bh(&sc->sc_pcu_lock);
245
c0d7c7af
LR		 246 /*
247 * This is only performed if the channel settings have
248 * actually changed.
249 *
250 * To switch channels clear any pending DMA operations;
251 * wait long enough for the RX fifo to drain, reset the
252 * hardware at the new frequency, and then re-enable
253 * the relevant bits of the h/w.
254 */
4df3071e 255 ath9k_hw_disable_interrupts(ah);
080e1a25 256 stopped = ath_drain_all_txq(sc, false);
5e848f78 257
080e1a25
FF		 258 if (!ath_stoprecv(sc))
259 stopped = false;
ff37e337 260
8b3f4616
FF		 261 if (!ath9k_hw_check_alive(ah))
262 stopped = false;
263
c0d7c7af
LR		 264 /* XXX: do not flush receive queue here. We don't want
265 * to flush data frames already in queue because of
266 * changing channel. */
ff37e337 267
5ee08656 268 if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL))
c0d7c7af
LR		 269 fastcc = false;
270
20bd2a09 271 if (!(sc->sc_flags & SC_OP_OFFCHANNEL))
9ac58615 272 caldata = &sc->caldata;
20bd2a09 273
226afe68
JP		 274 ath_dbg(common, ATH_DBG_CONFIG,
275 "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n",
276 sc->sc_ah->curchan->channel,
277 channel->center_freq, conf_is_ht40(conf),
278 fastcc);
ff37e337 279
20bd2a09 280 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
c0d7c7af 281 if (r) {
3800276a
JP		 282 ath_err(common,
283 "Unable to reset channel (%u MHz), reset status %d\n",
284 channel->center_freq, r);
3989279c 285 goto ps_restore;
ff37e337 286 }
c0d7c7af 287
c0d7c7af 288 if (ath_startrecv(sc) != 0) {
3800276a 289 ath_err(common, "Unable to restart recv logic\n");
3989279c
GJ		 290 r = -EIO;
291 goto ps_restore;
c0d7c7af
LR		 292 }
293
5048e8c3
RM		 294 ath9k_cmn_update_txpow(ah, sc->curtxpow,
295 sc->config.txpowlimit, &sc->curtxpow);
3069168c 296 ath9k_hw_set_interrupts(ah, ah->imask);
3989279c 297
48a6a468 298 if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) {
1186488b 299 if (sc->sc_flags & SC_OP_BEACONS)
99e4d43a 300 ath_set_beacon(sc);
5ee08656 301 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
181fb18d 302 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
48a6a468 303 ath_start_ani(common);
5ee08656
FF		 304 }
305
3989279c 306 ps_restore:
92460412
FF		 307 ieee80211_wake_queues(hw);
308
6a6733f2
LR		 309 spin_unlock_bh(&sc->sc_pcu_lock);
310
3cbb5dd7 311 ath9k_ps_restore(sc);
3989279c 312 return r;
ff37e337
S		 313}
314
9f42c2b6
FF		 315static void ath_paprd_activate(struct ath_softc *sc)
316{
317 struct ath_hw *ah = sc->sc_ah;
20bd2a09 318 struct ath9k_hw_cal_data *caldata = ah->caldata;
9094537c 319 struct ath_common *common = ath9k_hw_common(ah);
9f42c2b6
FF		 320 int chain;
321
20bd2a09 322 if (!caldata || !caldata->paprd_done)
9f42c2b6
FF		 323 return;
324
325 ath9k_ps_wakeup(sc);
ddfef792 326 ar9003_paprd_enable(ah, false);
9f42c2b6 327 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
9094537c 328 if (!(common->tx_chainmask & BIT(chain)))
9f42c2b6
FF		 329 continue;
330
20bd2a09 331 ar9003_paprd_populate_single_table(ah, caldata, chain);
9f42c2b6
FF		 332 }
333
334 ar9003_paprd_enable(ah, true);
335 ath9k_ps_restore(sc);
336}
337
7607cbe2
FF		 338static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
339{
340 struct ieee80211_hw *hw = sc->hw;
341 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
47960077
MSS		 342 struct ath_hw *ah = sc->sc_ah;
343 struct ath_common *common = ath9k_hw_common(ah);
7607cbe2
FF		 344 struct ath_tx_control txctl;
345 int time_left;
346
347 memset(&txctl, 0, sizeof(txctl));
348 txctl.txq = sc->tx.txq_map[WME_AC_BE];
349
350 memset(tx_info, 0, sizeof(*tx_info));
351 tx_info->band = hw->conf.channel->band;
352 tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
353 tx_info->control.rates[0].idx = 0;
354 tx_info->control.rates[0].count = 1;
355 tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
356 tx_info->control.rates[1].idx = -1;
357
358 init_completion(&sc->paprd_complete);
7607cbe2 359 txctl.paprd = BIT(chain);
47960077
MSS		 360
361 if (ath_tx_start(hw, skb, &txctl) != 0) {
362 ath_dbg(common, ATH_DBG_XMIT, "PAPRD TX failed\n");
363 dev_kfree_skb_any(skb);
7607cbe2 364 return false;
47960077 365 }
7607cbe2
FF		 366
367 time_left = wait_for_completion_timeout(&sc->paprd_complete,
368 msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
7607cbe2
FF		 369
370 if (!time_left)
371 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CALIBRATE,
372 "Timeout waiting for paprd training on TX chain %d\n",
373 chain);
374
375 return !!time_left;
376}
377
9f42c2b6
FF		 378void ath_paprd_calibrate(struct work_struct *work)
379{
380 struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
381 struct ieee80211_hw *hw = sc->hw;
382 struct ath_hw *ah = sc->sc_ah;
383 struct ieee80211_hdr *hdr;
384 struct sk_buff *skb = NULL;
20bd2a09 385 struct ath9k_hw_cal_data *caldata = ah->caldata;
9094537c 386 struct ath_common *common = ath9k_hw_common(ah);
066dae93 387 int ftype;
9f42c2b6
FF		 388 int chain_ok = 0;
389 int chain;
390 int len = 1800;
9f42c2b6 391
20bd2a09
FF		 392 if (!caldata)
393 return;
394
b942471b
MSS		 395 ath9k_ps_wakeup(sc);
396
1bf38661 397 if (ar9003_paprd_init_table(ah) < 0)
b942471b 398 goto fail_paprd;
1bf38661 399
9f42c2b6
FF		 400 skb = alloc_skb(len, GFP_KERNEL);
401 if (!skb)
b942471b 402 goto fail_paprd;
9f42c2b6 403
9f42c2b6
FF		 404 skb_put(skb, len);
405 memset(skb->data, 0, len);
406 hdr = (struct ieee80211_hdr *)skb->data;
407 ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
408 hdr->frame_control = cpu_to_le16(ftype);
a3d3da14 409 hdr->duration_id = cpu_to_le16(10);
9f42c2b6
FF		 410 memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
411 memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
412 memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
413
9f42c2b6 414 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
9094537c 415 if (!(common->tx_chainmask & BIT(chain)))
9f42c2b6
FF		 416 continue;
417
418 chain_ok = 0;
9f42c2b6 419
7607cbe2
FF		 420 ath_dbg(common, ATH_DBG_CALIBRATE,
421 "Sending PAPRD frame for thermal measurement "
422 "on chain %d\n", chain);
423 if (!ath_paprd_send_frame(sc, skb, chain))
424 goto fail_paprd;
9f42c2b6 425
9f42c2b6 426 ar9003_paprd_setup_gain_table(ah, chain);
9f42c2b6 427
7607cbe2
FF		 428 ath_dbg(common, ATH_DBG_CALIBRATE,
429 "Sending PAPRD training frame on chain %d\n", chain);
430 if (!ath_paprd_send_frame(sc, skb, chain))
ca369eb4 431 goto fail_paprd;
9f42c2b6
FF		 432
433 if (!ar9003_paprd_is_done(ah))
434 break;
435
20bd2a09 436 if (ar9003_paprd_create_curve(ah, caldata, chain) != 0)
9f42c2b6
FF		 437 break;
438
439 chain_ok = 1;
440 }
441 kfree_skb(skb);
442
443 if (chain_ok) {
20bd2a09 444 caldata->paprd_done = true;
9f42c2b6
FF		 445 ath_paprd_activate(sc);
446 }
447
ca369eb4 448fail_paprd:
9f42c2b6
FF		 449 ath9k_ps_restore(sc);
450}
451
ff37e337
S		 452/*
453 * This routine performs the periodic noise floor calibration function
454 * that is used to adjust and optimize the chip performance. This
455 * takes environmental changes (location, temperature) into account.
456 * When the task is complete, it reschedules itself depending on the
457 * appropriate interval that was calculated.
458 */
55624204 459void ath_ani_calibrate(unsigned long data)
ff37e337 460{
20977d3e
S		 461 struct ath_softc *sc = (struct ath_softc *)data;
462 struct ath_hw *ah = sc->sc_ah;
c46917bb 463 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S		 464 bool longcal = false;
465 bool shortcal = false;
466 bool aniflag = false;
467 unsigned int timestamp = jiffies_to_msecs(jiffies);
6044474e 468 u32 cal_interval, short_cal_interval, long_cal_interval;
b5bfc568 469 unsigned long flags;
6044474e
FF		 470
471 if (ah->caldata && ah->caldata->nfcal_interference)
472 long_cal_interval = ATH_LONG_CALINTERVAL_INT;
473 else
474 long_cal_interval = ATH_LONG_CALINTERVAL;
ff37e337 475
20977d3e
S		 476 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
477 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337 478
1ffc1c61
JM		 479 /* Only calibrate if awake */
480 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
481 goto set_timer;
482
483 ath9k_ps_wakeup(sc);
484
ff37e337 485 /* Long calibration runs independently of short calibration. */
6044474e 486 if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
ff37e337 487 longcal = true;
226afe68 488 ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
3d536acf 489 common->ani.longcal_timer = timestamp;
ff37e337
S		 490 }
491
17d7904d 492 /* Short calibration applies only while caldone is false */
3d536acf
LR		 493 if (!common->ani.caldone) {
494 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 495 shortcal = true;
226afe68
JP		 496 ath_dbg(common, ATH_DBG_ANI,
497 "shortcal @%lu\n", jiffies);
3d536acf
LR		 498 common->ani.shortcal_timer = timestamp;
499 common->ani.resetcal_timer = timestamp;
ff37e337
S		 500 }
501 } else {
3d536acf 502 if ((timestamp - common->ani.resetcal_timer) >=
ff37e337 503 ATH_RESTART_CALINTERVAL) {
3d536acf
LR		 504 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
505 if (common->ani.caldone)
506 common->ani.resetcal_timer = timestamp;
ff37e337
S		 507 }
508 }
509
510 /* Verify whether we must check ANI */
e36b27af
LR		 511 if ((timestamp - common->ani.checkani_timer) >=
512 ah->config.ani_poll_interval) {
ff37e337 513 aniflag = true;
3d536acf 514 common->ani.checkani_timer = timestamp;
ff37e337
S		 515 }
516
e62ddec9
MSS		 517 /* Call ANI routine if necessary */
518 if (aniflag) {
519 spin_lock_irqsave(&common->cc_lock, flags);
520 ath9k_hw_ani_monitor(ah, ah->curchan);
521 ath_update_survey_stats(sc);
522 spin_unlock_irqrestore(&common->cc_lock, flags);
523 }
ff37e337 524
e62ddec9
MSS		 525 /* Perform calibration if necessary */
526 if (longcal || shortcal) {
527 common->ani.caldone =
528 ath9k_hw_calibrate(ah, ah->curchan,
529 common->rx_chainmask, longcal);
ff37e337
S		 530 }
531
1ffc1c61
JM		 532 ath9k_ps_restore(sc);
533
20977d3e 534set_timer:
ff37e337
S		 535 /*
536 * Set timer interval based on previous results.
537 * The interval must be the shortest necessary to satisfy ANI,
538 * short calibration and long calibration.
539 */
aac9207e 540 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 541 if (sc->sc_ah->config.enable_ani)
e36b27af
LR		 542 cal_interval = min(cal_interval,
543 (u32)ah->config.ani_poll_interval);
3d536acf 544 if (!common->ani.caldone)
20977d3e 545 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 546
3d536acf 547 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
20bd2a09
FF		 548 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
549 if (!ah->caldata->paprd_done)
9f42c2b6 550 ieee80211_queue_work(sc->hw, &sc->paprd_work);
45ef6a0b 551 else if (!ah->paprd_table_write_done)
9f42c2b6
FF		 552 ath_paprd_activate(sc);
553 }
ff37e337
S		 554}
555
ff37e337
S		 556static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
557{
558 struct ath_node *an;
ea066d5a 559 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 560 an = (struct ath_node *)sta->drv_priv;
561
7f010c93
BG		 562#ifdef CONFIG_ATH9K_DEBUGFS
563 spin_lock(&sc->nodes_lock);
564 list_add(&an->list, &sc->nodes);
565 spin_unlock(&sc->nodes_lock);
566 an->sta = sta;
567#endif
ea066d5a
MSS		 568 if ((ah->caps.hw_caps) & ATH9K_HW_CAP_APM)
569 sc->sc_flags |= SC_OP_ENABLE_APM;
570
87792efc 571 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 572 ath_tx_node_init(sc, an);
9e98ac65 573 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S		 574 sta->ht_cap.ampdu_factor);
575 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
576 }
ff37e337
S		 577}
578
579static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
580{
581 struct ath_node *an = (struct ath_node *)sta->drv_priv;
582
7f010c93
BG		 583#ifdef CONFIG_ATH9K_DEBUGFS
584 spin_lock(&sc->nodes_lock);
585 list_del(&an->list);
586 spin_unlock(&sc->nodes_lock);
587 an->sta = NULL;
588#endif
589
ff37e337
S		 590 if (sc->sc_flags & SC_OP_TXAGGR)
591 ath_tx_node_cleanup(sc, an);
592}
593
347809fc
FF		 594void ath_hw_check(struct work_struct *work)
595{
596 struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
cb8d61de
FF		 597 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
598 unsigned long flags;
599 int busy;
347809fc
FF		 600
601 ath9k_ps_wakeup(sc);
cb8d61de
FF		 602 if (ath9k_hw_check_alive(sc->sc_ah))
603 goto out;
347809fc 604
cb8d61de
FF		 605 spin_lock_irqsave(&common->cc_lock, flags);
606 busy = ath_update_survey_stats(sc);
607 spin_unlock_irqrestore(&common->cc_lock, flags);
347809fc 608
cb8d61de
FF		 609 ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, "
610 "busy=%d (try %d)\n", busy, sc->hw_busy_count + 1);
611 if (busy >= 99) {
612 if (++sc->hw_busy_count >= 3)
613 ath_reset(sc, true);
614 } else if (busy >= 0)
615 sc->hw_busy_count = 0;
347809fc
FF		 616
617out:
618 ath9k_ps_restore(sc);
619}
620
b84628eb
SB		 621static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)
622{
623 static int count;
624 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
625
626 if (pll_sqsum >= 0x40000) {
627 count++;
628 if (count == 3) {
629 /* Rx is hung for more than 500ms. Reset it */
630 ath_dbg(common, ATH_DBG_RESET,
631 "Possible RX hang, resetting");
632 ath_reset(sc, true);
633 count = 0;
634 }
635 } else
636 count = 0;
637}
638
9eab61c2
SB		 639void ath_hw_pll_work(struct work_struct *work)
640{
641 struct ath_softc *sc = container_of(work, struct ath_softc,
642 hw_pll_work.work);
b84628eb 643 u32 pll_sqsum;
9eab61c2
SB		 644
645 if (AR_SREV_9485(sc->sc_ah)) {
b84628eb
SB		 646
647 ath9k_ps_wakeup(sc);
648 pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah);
649 ath9k_ps_restore(sc);
650
651 ath_hw_pll_rx_hang_check(sc, pll_sqsum);
9eab61c2
SB		 652
653 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5);
654 }
655}
656
657
55624204 658void ath9k_tasklet(unsigned long data)
ff37e337
S		 659{
660 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 661 struct ath_hw *ah = sc->sc_ah;
c46917bb 662 struct ath_common *common = ath9k_hw_common(ah);
af03abec 663
17d7904d 664 u32 status = sc->intrstatus;
b5c80475 665 u32 rxmask;
ff37e337 666
a4d86d95
RM		 667 if ((status & ATH9K_INT_FATAL) ||
668 (status & ATH9K_INT_BB_WATCHDOG)) {
fac6b6a0 669 ath_reset(sc, true);
ff37e337 670 return;
063d8be3 671 }
ff37e337 672
783cd01e 673 ath9k_ps_wakeup(sc);
52671e43 674 spin_lock(&sc->sc_pcu_lock);
6a6733f2 675
8b3f4616
FF		 676 /*
677 * Only run the baseband hang check if beacons stop working in AP or
678 * IBSS mode, because it has a high false positive rate. For station
679 * mode it should not be necessary, since the upper layers will detect
680 * this through a beacon miss automatically and the following channel
681 * change will trigger a hardware reset anyway
682 */
683 if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 &&
684 !ath9k_hw_check_alive(ah))
347809fc
FF		 685 ieee80211_queue_work(sc->hw, &sc->hw_check_work);
686
4105f807
RM		 687 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
688 /*
689 * TSF sync does not look correct; remain awake to sync with
690 * the next Beacon.
691 */
692 ath_dbg(common, ATH_DBG_PS,
693 "TSFOOR - Sync with next Beacon\n");
694 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC |
695 PS_TSFOOR_SYNC;
696 }
697
b5c80475
FF		 698 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
699 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
700 ATH9K_INT_RXORN);
701 else
702 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
703
704 if (status & rxmask) {
b5c80475
FF		 705 /* Check for high priority Rx first */
706 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
707 (status & ATH9K_INT_RXHP))
708 ath_rx_tasklet(sc, 0, true);
709
710 ath_rx_tasklet(sc, 0, false);
ff37e337
S		 711 }
712
e5003249
VT		 713 if (status & ATH9K_INT_TX) {
714 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
715 ath_tx_edma_tasklet(sc);
716 else
717 ath_tx_tasklet(sc);
718 }
063d8be3 719
766ec4a9 720 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
ebb8e1d7
VT		 721 if (status & ATH9K_INT_GENTIMER)
722 ath_gen_timer_isr(sc->sc_ah);
723
ff37e337 724 /* re-enable hardware interrupt */
4df3071e 725 ath9k_hw_enable_interrupts(ah);
6a6733f2 726
52671e43 727 spin_unlock(&sc->sc_pcu_lock);
153e080d 728 ath9k_ps_restore(sc);
ff37e337
S		 729}
730
6baff7f9 731irqreturn_t ath_isr(int irq, void *dev)
ff37e337 732{
063d8be3
S		 733#define SCHED_INTR ( \
734 ATH9K_INT_FATAL | \
a4d86d95 735 ATH9K_INT_BB_WATCHDOG | \
063d8be3
S		 736 ATH9K_INT_RXORN | \
737 ATH9K_INT_RXEOL | \
738 ATH9K_INT_RX | \
b5c80475
FF		 739 ATH9K_INT_RXLP | \
740 ATH9K_INT_RXHP | \
063d8be3
S		 741 ATH9K_INT_TX | \
742 ATH9K_INT_BMISS | \
743 ATH9K_INT_CST | \
ebb8e1d7
VT		 744 ATH9K_INT_TSFOOR | \
745 ATH9K_INT_GENTIMER)
063d8be3 746
ff37e337 747 struct ath_softc *sc = dev;
cbe61d8a 748 struct ath_hw *ah = sc->sc_ah;
b5bfc568 749 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S		 750 enum ath9k_int status;
751 bool sched = false;
752
063d8be3
S		 753 /*
754 * The hardware is not ready/present, don't
755 * touch anything. Note this can happen early
756 * on if the IRQ is shared.
757 */
758 if (sc->sc_flags & SC_OP_INVALID)
759 return IRQ_NONE;
ff37e337 760
063d8be3
S		 761
762 /* shared irq, not for us */
763
153e080d 764 if (!ath9k_hw_intrpend(ah))
063d8be3 765 return IRQ_NONE;
063d8be3
S		 766
767 /*
768 * Figure out the reason(s) for the interrupt. Note
769 * that the hal returns a pseudo-ISR that may include
770 * bits we haven't explicitly enabled so we mask the
771 * value to insure we only process bits we requested.
772 */
773 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
3069168c 774 status &= ah->imask; /* discard unasked-for bits */
ff37e337 775
063d8be3
S		 776 /*
777 * If there are no status bits set, then this interrupt was not
778 * for me (should have been caught above).
779 */
153e080d 780 if (!status)
063d8be3 781 return IRQ_NONE;
ff37e337 782
063d8be3
S		 783 /* Cache the status */
784 sc->intrstatus = status;
785
786 if (status & SCHED_INTR)
787 sched = true;
788
789 /*
790 * If a FATAL or RXORN interrupt is received, we have to reset the
791 * chip immediately.
792 */
b5c80475
FF		 793 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
794 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
063d8be3
S		 795 goto chip_reset;
796
08578b8f
LR		 797 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
798 (status & ATH9K_INT_BB_WATCHDOG)) {
b5bfc568
FF		 799
800 spin_lock(&common->cc_lock);
801 ath_hw_cycle_counters_update(common);
08578b8f 802 ar9003_hw_bb_watchdog_dbg_info(ah);
b5bfc568
FF		 803 spin_unlock(&common->cc_lock);
804
08578b8f
LR		 805 goto chip_reset;
806 }
807
063d8be3
S		 808 if (status & ATH9K_INT_SWBA)
809 tasklet_schedule(&sc->bcon_tasklet);
810
811 if (status & ATH9K_INT_TXURN)
812 ath9k_hw_updatetxtriglevel(ah, true);
813
b5c80475
FF		 814 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
815 if (status & ATH9K_INT_RXEOL) {
816 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
817 ath9k_hw_set_interrupts(ah, ah->imask);
818 }
819 }
820
063d8be3 821 if (status & ATH9K_INT_MIB) {
ff37e337 822 /*
063d8be3
S		 823 * Disable interrupts until we service the MIB
824 * interrupt; otherwise it will continue to
825 * fire.
ff37e337 826 */
4df3071e 827 ath9k_hw_disable_interrupts(ah);
063d8be3
S		 828 /*
829 * Let the hal handle the event. We assume
830 * it will clear whatever condition caused
831 * the interrupt.
832 */
88eac2da 833 spin_lock(&common->cc_lock);
bfc472bb 834 ath9k_hw_proc_mib_event(ah);
88eac2da 835 spin_unlock(&common->cc_lock);
4df3071e 836 ath9k_hw_enable_interrupts(ah);
063d8be3 837 }
ff37e337 838
153e080d
VT		 839 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
840 if (status & ATH9K_INT_TIM_TIMER) {
ff9f0b63
LR		 841 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
842 goto chip_reset;
063d8be3
S		 843 /* Clear RxAbort bit so that we can
844 * receive frames */
9ecdef4b 845 ath9k_setpower(sc, ATH9K_PM_AWAKE);
153e080d 846 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930 847 sc->ps_flags |= PS_WAIT_FOR_BEACON;
ff37e337 848 }
063d8be3
S		 849
850chip_reset:
ff37e337 851
817e11de
S		 852 ath_debug_stat_interrupt(sc, status);
853
ff37e337 854 if (sched) {
4df3071e
FF		 855 /* turn off every interrupt */
856 ath9k_hw_disable_interrupts(ah);
ff37e337
S		 857 tasklet_schedule(&sc->intr_tq);
858 }
859
860 return IRQ_HANDLED;
063d8be3
S		 861
862#undef SCHED_INTR
ff37e337
S		 863}
864
5595f119 865static void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 866{
cbe61d8a 867 struct ath_hw *ah = sc->sc_ah;
c46917bb 868 struct ath_common *common = ath9k_hw_common(ah);
68a89116 869 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 870 int r;
500c064d 871
3cbb5dd7 872 ath9k_ps_wakeup(sc);
6a6733f2
LR		 873 spin_lock_bh(&sc->sc_pcu_lock);
874
93b1b37f 875 ath9k_hw_configpcipowersave(ah, 0, 0);
ae8d2858 876
159cd468 877 if (!ah->curchan)
c344c9cb 878 ah->curchan = ath9k_cmn_get_curchannel(sc->hw, ah);
159cd468 879
20bd2a09 880 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ae8d2858 881 if (r) {
3800276a
JP		 882 ath_err(common,
883 "Unable to reset channel (%u MHz), reset status %d\n",
884 channel->center_freq, r);
500c064d 885 }
500c064d 886
5048e8c3
RM		 887 ath9k_cmn_update_txpow(ah, sc->curtxpow,
888 sc->config.txpowlimit, &sc->curtxpow);
500c064d 889 if (ath_startrecv(sc) != 0) {
3800276a 890 ath_err(common, "Unable to restart recv logic\n");
c2731b81 891 goto out;
500c064d 892 }
500c064d 893 if (sc->sc_flags & SC_OP_BEACONS)
99e4d43a 894 ath_set_beacon(sc); /* restart beacons */
500c064d
VT		 895
896 /* Re-Enable interrupts */
3069168c 897 ath9k_hw_set_interrupts(ah, ah->imask);
500c064d
VT		 898
899 /* Enable LED */
08fc5c1b 900 ath9k_hw_cfg_output(ah, ah->led_pin,
500c064d 901 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b 902 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
500c064d 903
68a89116 904 ieee80211_wake_queues(hw);
7e3514fd
VN		 905 ieee80211_queue_delayed_work(hw, &sc->hw_pll_work, HZ/2);
906
c2731b81 907out:
6a6733f2
LR		 908 spin_unlock_bh(&sc->sc_pcu_lock);
909
3cbb5dd7 910 ath9k_ps_restore(sc);
500c064d
VT		 911}
912
68a89116 913void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 914{
cbe61d8a 915 struct ath_hw *ah = sc->sc_ah;
68a89116 916 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 917 int r;
500c064d 918
3cbb5dd7 919 ath9k_ps_wakeup(sc);
7e3514fd
VN		 920 cancel_delayed_work_sync(&sc->hw_pll_work);
921
6a6733f2
LR		 922 spin_lock_bh(&sc->sc_pcu_lock);
923
68a89116 924 ieee80211_stop_queues(hw);
500c064d 925
982723df
VN		 926 /*
927 * Keep the LED on when the radio is disabled
928 * during idle unassociated state.
929 */
930 if (!sc->ps_idle) {
931 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
932 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
933 }
500c064d
VT		 934
935 /* Disable interrupts */
4df3071e 936 ath9k_hw_disable_interrupts(ah);
500c064d 937
043a0405 938 ath_drain_all_txq(sc, false); /* clear pending tx frames */
5e848f78 939
500c064d
VT		 940 ath_stoprecv(sc); /* turn off frame recv */
941 ath_flushrecv(sc); /* flush recv queue */
942
159cd468 943 if (!ah->curchan)
c344c9cb 944 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
159cd468 945
20bd2a09 946 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ae8d2858 947 if (r) {
3800276a
JP		 948 ath_err(ath9k_hw_common(sc->sc_ah),
949 "Unable to reset channel (%u MHz), reset status %d\n",
950 channel->center_freq, r);
500c064d 951 }
500c064d
VT		 952
953 ath9k_hw_phy_disable(ah);
5e848f78 954
93b1b37f 955 ath9k_hw_configpcipowersave(ah, 1, 1);
6a6733f2
LR		 956
957 spin_unlock_bh(&sc->sc_pcu_lock);
3cbb5dd7 958 ath9k_ps_restore(sc);
500c064d
VT		 959}
960
ff37e337
S		 961int ath_reset(struct ath_softc *sc, bool retry_tx)
962{
cbe61d8a 963 struct ath_hw *ah = sc->sc_ah;
c46917bb 964 struct ath_common *common = ath9k_hw_common(ah);
030bb495 965 struct ieee80211_hw *hw = sc->hw;
ae8d2858 966 int r;
ff37e337 967
cb8d61de
FF		 968 sc->hw_busy_count = 0;
969
2ab81d4a
S		 970 /* Stop ANI */
971 del_timer_sync(&common->ani.timer);
972
783cd01e 973 ath9k_ps_wakeup(sc);
6a6733f2
LR		 974 spin_lock_bh(&sc->sc_pcu_lock);
975
cc9c378a
S		 976 ieee80211_stop_queues(hw);
977
4df3071e 978 ath9k_hw_disable_interrupts(ah);
043a0405 979 ath_drain_all_txq(sc, retry_tx);
5e848f78 980
ff37e337
S		 981 ath_stoprecv(sc);
982 ath_flushrecv(sc);
983
20bd2a09 984 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
ae8d2858 985 if (r)
3800276a
JP		 986 ath_err(common,
987 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S		 988
989 if (ath_startrecv(sc) != 0)
3800276a 990 ath_err(common, "Unable to start recv logic\n");
ff37e337
S		 991
992 /*
993 * We may be doing a reset in response to a request
994 * that changes the channel so update any state that
995 * might change as a result.
996 */
5048e8c3
RM		 997 ath9k_cmn_update_txpow(ah, sc->curtxpow,
998 sc->config.txpowlimit, &sc->curtxpow);
ff37e337 999
52b8ac92 1000 if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL)))
99e4d43a 1001 ath_set_beacon(sc); /* restart beacons */
ff37e337 1002
3069168c 1003 ath9k_hw_set_interrupts(ah, ah->imask);
ff37e337
S		 1004
1005 if (retry_tx) {
1006 int i;
1007 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1008 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1009 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1010 ath_txq_schedule(sc, &sc->tx.txq[i]);
1011 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1012 }
1013 }
1014 }
1015
cc9c378a 1016 ieee80211_wake_queues(hw);
6a6733f2 1017 spin_unlock_bh(&sc->sc_pcu_lock);
cc9c378a 1018
2ab81d4a
S		 1019 /* Start ANI */
1020 ath_start_ani(common);
783cd01e 1021 ath9k_ps_restore(sc);
2ab81d4a 1022
ae8d2858 1023 return r;
ff37e337
S		 1024}
1025
ff37e337
S		 1026/**********************/
1027/* mac80211 callbacks */
1028/**********************/
1029
8feceb67 1030static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1031{
9ac58615 1032 struct ath_softc *sc = hw->priv;
af03abec 1033 struct ath_hw *ah = sc->sc_ah;
c46917bb 1034 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 1035 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1036 struct ath9k_channel *init_channel;
82880a7c 1037 int r;
f078f209 1038
226afe68
JP		 1039 ath_dbg(common, ATH_DBG_CONFIG,
1040 "Starting driver with initial channel: %d MHz\n",
1041 curchan->center_freq);
f078f209 1042
f62d816f
FF		 1043 ath9k_ps_wakeup(sc);
1044
141b38b6
S		 1045 mutex_lock(&sc->mutex);
1046
8feceb67 1047 /* setup initial channel */
82880a7c 1048 sc->chan_idx = curchan->hw_value;
f078f209 1049
c344c9cb 1050 init_channel = ath9k_cmn_get_curchannel(hw, ah);
ff37e337
S		 1051
1052 /* Reset SERDES registers */
af03abec 1053 ath9k_hw_configpcipowersave(ah, 0, 0);
ff37e337
S		 1054
1055 /*
1056 * The basic interface to setting the hardware in a good
1057 * state is ``reset''. On return the hardware is known to
1058 * be powered up and with interrupts disabled. This must
1059 * be followed by initialization of the appropriate bits
1060 * and then setup of the interrupt mask.
1061 */
4bdd1e97 1062 spin_lock_bh(&sc->sc_pcu_lock);
20bd2a09 1063 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
ae8d2858 1064 if (r) {
3800276a
JP		 1065 ath_err(common,
1066 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
1067 r, curchan->center_freq);
4bdd1e97 1068 spin_unlock_bh(&sc->sc_pcu_lock);
141b38b6 1069 goto mutex_unlock;
ff37e337 1070 }
ff37e337
S		 1071
1072 /*
1073 * This is needed only to setup initial state
1074 * but it's best done after a reset.
1075 */
5048e8c3
RM		 1076 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1077 sc->config.txpowlimit, &sc->curtxpow);
8feceb67 1078
ff37e337
S		 1079 /*
1080 * Setup the hardware after reset:
1081 * The receive engine is set going.
1082 * Frame transmit is handled entirely
1083 * in the frame output path; there's nothing to do
1084 * here except setup the interrupt mask.
1085 */
1086 if (ath_startrecv(sc) != 0) {
3800276a 1087 ath_err(common, "Unable to start recv logic\n");
141b38b6 1088 r = -EIO;
4bdd1e97 1089 spin_unlock_bh(&sc->sc_pcu_lock);
141b38b6 1090 goto mutex_unlock;
f078f209 1091 }
4bdd1e97 1092 spin_unlock_bh(&sc->sc_pcu_lock);
8feceb67 1093
ff37e337 1094 /* Setup our intr mask. */
b5c80475
FF		 1095 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
1096 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
1097 ATH9K_INT_GLOBAL;
1098
1099 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
08578b8f
LR		 1100 ah->imask |= ATH9K_INT_RXHP |
1101 ATH9K_INT_RXLP |
1102 ATH9K_INT_BB_WATCHDOG;
b5c80475
FF		 1103 else
1104 ah->imask |= ATH9K_INT_RX;
ff37e337 1105
364734fa 1106 ah->imask |= ATH9K_INT_GTT;
ff37e337 1107
af03abec 1108 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
3069168c 1109 ah->imask |= ATH9K_INT_CST;
ff37e337 1110
ff37e337 1111 sc->sc_flags &= ~SC_OP_INVALID;
5f841b41 1112 sc->sc_ah->is_monitoring = false;
ff37e337
S		 1113
1114 /* Disable BMISS interrupt when we're not associated */
3069168c
PR		 1115 ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1116 ath9k_hw_set_interrupts(ah, ah->imask);
ff37e337 1117
bce048d7 1118 ieee80211_wake_queues(hw);
ff37e337 1119
42935eca 1120 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
164ace38 1121
766ec4a9
LR		 1122 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
1123 !ah->btcoex_hw.enabled) {
5e197292
LR		 1124 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1125 AR_STOMP_LOW_WLAN_WGHT);
af03abec 1126 ath9k_hw_btcoex_enable(ah);
f985ad12 1127
5bb12791
LR		 1128 if (common->bus_ops->bt_coex_prep)
1129 common->bus_ops->bt_coex_prep(common);
766ec4a9 1130 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1131 ath9k_btcoex_timer_resume(sc);
1773912b
VT		 1132 }
1133
8060e169
VT		 1134 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
1135 common->bus_ops->extn_synch_en(common);
1136
141b38b6
S		 1137mutex_unlock:
1138 mutex_unlock(&sc->mutex);
1139
f62d816f
FF		 1140 ath9k_ps_restore(sc);
1141
ae8d2858 1142 return r;
f078f209
LR		 1143}
1144
7bb45683 1145static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
f078f209 1146{
9ac58615 1147 struct ath_softc *sc = hw->priv;
c46917bb 1148 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 1149 struct ath_tx_control txctl;
1bc14880 1150 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
528f0c6b 1151
96148326 1152 if (sc->ps_enabled) {
dc8c4585
JM		 1153 /*
1154 * mac80211 does not set PM field for normal data frames, so we
1155 * need to update that based on the current PS mode.
1156 */
1157 if (ieee80211_is_data(hdr->frame_control) &&
1158 !ieee80211_is_nullfunc(hdr->frame_control) &&
1159 !ieee80211_has_pm(hdr->frame_control)) {
226afe68
JP		 1160 ath_dbg(common, ATH_DBG_PS,
1161 "Add PM=1 for a TX frame while in PS mode\n");
dc8c4585
JM		 1162 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1163 }
1164 }
1165
9a23f9ca
JM		 1166 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
1167 /*
1168 * We are using PS-Poll and mac80211 can request TX while in
1169 * power save mode. Need to wake up hardware for the TX to be
1170 * completed and if needed, also for RX of buffered frames.
1171 */
9a23f9ca 1172 ath9k_ps_wakeup(sc);
fdf76622
VT		 1173 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
1174 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca 1175 if (ieee80211_is_pspoll(hdr->frame_control)) {
226afe68
JP		 1176 ath_dbg(common, ATH_DBG_PS,
1177 "Sending PS-Poll to pick a buffered frame\n");
1b04b930 1178 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
9a23f9ca 1179 } else {
226afe68
JP		 1180 ath_dbg(common, ATH_DBG_PS,
1181 "Wake up to complete TX\n");
1b04b930 1182 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
9a23f9ca
JM		 1183 }
1184 /*
1185 * The actual restore operation will happen only after
1186 * the sc_flags bit is cleared. We are just dropping
1187 * the ps_usecount here.
1188 */
1189 ath9k_ps_restore(sc);
1190 }
1191
528f0c6b 1192 memset(&txctl, 0, sizeof(struct ath_tx_control));
066dae93 1193 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
528f0c6b 1194
226afe68 1195 ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 1196
c52f33d0 1197 if (ath_tx_start(hw, skb, &txctl) != 0) {
226afe68 1198 ath_dbg(common, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 1199 goto exit;
8feceb67
VT		 1200 }
1201
7bb45683 1202 return;
528f0c6b
S		 1203exit:
1204 dev_kfree_skb_any(skb);
f078f209
LR		 1205}
1206
8feceb67 1207static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 1208{
9ac58615 1209 struct ath_softc *sc = hw->priv;
af03abec 1210 struct ath_hw *ah = sc->sc_ah;
c46917bb 1211 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1212
4c483817
S		 1213 mutex_lock(&sc->mutex);
1214
c94dbff7 1215 cancel_delayed_work_sync(&sc->tx_complete_work);
181fb18d 1216 cancel_delayed_work_sync(&sc->hw_pll_work);
9f42c2b6 1217 cancel_work_sync(&sc->paprd_work);
347809fc 1218 cancel_work_sync(&sc->hw_check_work);
c94dbff7 1219
9c84b797 1220 if (sc->sc_flags & SC_OP_INVALID) {
226afe68 1221 ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
4c483817 1222 mutex_unlock(&sc->mutex);
9c84b797
S		 1223 return;
1224 }
8feceb67 1225
3867cf6a
S		 1226 /* Ensure HW is awake when we try to shut it down. */
1227 ath9k_ps_wakeup(sc);
1228
766ec4a9 1229 if (ah->btcoex_hw.enabled) {
af03abec 1230 ath9k_hw_btcoex_disable(ah);
766ec4a9 1231 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1232 ath9k_btcoex_timer_pause(sc);
1773912b
VT		 1233 }
1234
6a6733f2
LR		 1235 spin_lock_bh(&sc->sc_pcu_lock);
1236
203043f5
SG		 1237 /* prevent tasklets to enable interrupts once we disable them */
1238 ah->imask &= ~ATH9K_INT_GLOBAL;
1239
ff37e337
S		 1240 /* make sure h/w will not generate any interrupt
1241 * before setting the invalid flag. */
4df3071e 1242 ath9k_hw_disable_interrupts(ah);
ff37e337
S		 1243
1244 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 1245 ath_drain_all_txq(sc, false);
ff37e337 1246 ath_stoprecv(sc);
af03abec 1247 ath9k_hw_phy_disable(ah);
6a6733f2 1248 } else
b77f483f 1249 sc->rx.rxlink = NULL;
ff37e337 1250
0d95521e
FF		 1251 if (sc->rx.frag) {
1252 dev_kfree_skb_any(sc->rx.frag);
1253 sc->rx.frag = NULL;
1254 }
1255
ff37e337 1256 /* disable HAL and put h/w to sleep */
af03abec
LR		 1257 ath9k_hw_disable(ah);
1258 ath9k_hw_configpcipowersave(ah, 1, 1);
6a6733f2
LR		 1259
1260 spin_unlock_bh(&sc->sc_pcu_lock);
1261
203043f5
SG		 1262 /* we can now sync irq and kill any running tasklets, since we already
1263 * disabled interrupts and not holding a spin lock */
1264 synchronize_irq(sc->irq);
1265 tasklet_kill(&sc->intr_tq);
1266 tasklet_kill(&sc->bcon_tasklet);
1267
3867cf6a
S		 1268 ath9k_ps_restore(sc);
1269
a08e7ade
LR		 1270 sc->ps_idle = true;
1271 ath_radio_disable(sc, hw);
ff37e337
S		 1272
1273 sc->sc_flags |= SC_OP_INVALID;
500c064d 1274
141b38b6
S		 1275 mutex_unlock(&sc->mutex);
1276
226afe68 1277 ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 1278}
1279
4801416c
BG		 1280bool ath9k_uses_beacons(int type)
1281{
1282 switch (type) {
1283 case NL80211_IFTYPE_AP:
1284 case NL80211_IFTYPE_ADHOC:
1285 case NL80211_IFTYPE_MESH_POINT:
1286 return true;
1287 default:
1288 return false;
1289 }
1290}
1291
1292static void ath9k_reclaim_beacon(struct ath_softc *sc,
1293 struct ieee80211_vif *vif)
f078f209 1294{
1ed32e4f 1295 struct ath_vif *avp = (void *)vif->drv_priv;
8feceb67 1296
014cf3bb 1297 ath9k_set_beaconing_status(sc, false);
4801416c 1298 ath_beacon_return(sc, avp);
014cf3bb 1299 ath9k_set_beaconing_status(sc, true);
4801416c 1300 sc->sc_flags &= ~SC_OP_BEACONS;
4801416c
BG		 1301}
1302
1303static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1304{
1305 struct ath9k_vif_iter_data *iter_data = data;
1306 int i;
1307
1308 if (iter_data->hw_macaddr)
1309 for (i = 0; i < ETH_ALEN; i++)
1310 iter_data->mask[i] &=
1311 ~(iter_data->hw_macaddr[i] ^ mac[i]);
141b38b6 1312
1ed32e4f 1313 switch (vif->type) {
4801416c
BG		 1314 case NL80211_IFTYPE_AP:
1315 iter_data->naps++;
f078f209 1316 break;
4801416c
BG		 1317 case NL80211_IFTYPE_STATION:
1318 iter_data->nstations++;
e51f3eff 1319 break;
05c914fe 1320 case NL80211_IFTYPE_ADHOC:
4801416c
BG		 1321 iter_data->nadhocs++;
1322 break;
9cb5412b 1323 case NL80211_IFTYPE_MESH_POINT:
4801416c
BG		 1324 iter_data->nmeshes++;
1325 break;
1326 case NL80211_IFTYPE_WDS:
1327 iter_data->nwds++;
f078f209
LR		 1328 break;
1329 default:
4801416c
BG		 1330 iter_data->nothers++;
1331 break;
f078f209 1332 }
4801416c 1333}
f078f209 1334
4801416c
BG		 1335/* Called with sc->mutex held. */
1336void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
1337 struct ieee80211_vif *vif,
1338 struct ath9k_vif_iter_data *iter_data)
1339{
9ac58615 1340 struct ath_softc *sc = hw->priv;
4801416c
BG		 1341 struct ath_hw *ah = sc->sc_ah;
1342 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 1343
4801416c
BG		 1344 /*
1345 * Use the hardware MAC address as reference, the hardware uses it
1346 * together with the BSSID mask when matching addresses.
1347 */
1348 memset(iter_data, 0, sizeof(*iter_data));
1349 iter_data->hw_macaddr = common->macaddr;
1350 memset(&iter_data->mask, 0xff, ETH_ALEN);
5640b08e 1351
4801416c
BG		 1352 if (vif)
1353 ath9k_vif_iter(iter_data, vif->addr, vif);
1354
1355 /* Get list of all active MAC addresses */
4801416c
BG		 1356 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
1357 iter_data);
4801416c 1358}
8ca21f01 1359
4801416c
BG		 1360/* Called with sc->mutex held. */
1361static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
1362 struct ieee80211_vif *vif)
1363{
9ac58615 1364 struct ath_softc *sc = hw->priv;
4801416c
BG		 1365 struct ath_hw *ah = sc->sc_ah;
1366 struct ath_common *common = ath9k_hw_common(ah);
1367 struct ath9k_vif_iter_data iter_data;
8ca21f01 1368
4801416c 1369 ath9k_calculate_iter_data(hw, vif, &iter_data);
2c3db3d5 1370
4801416c
BG		 1371 /* Set BSSID mask. */
1372 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1373 ath_hw_setbssidmask(common);
1374
1375 /* Set op-mode & TSF */
1376 if (iter_data.naps > 0) {
3069168c 1377 ath9k_hw_set_tsfadjust(ah, 1);
b238e90e 1378 sc->sc_flags |= SC_OP_TSF_RESET;
4801416c
BG		 1379 ah->opmode = NL80211_IFTYPE_AP;
1380 } else {
1381 ath9k_hw_set_tsfadjust(ah, 0);
1382 sc->sc_flags &= ~SC_OP_TSF_RESET;
5640b08e 1383
fd5999cf
JC		 1384 if (iter_data.nmeshes)
1385 ah->opmode = NL80211_IFTYPE_MESH_POINT;
1386 else if (iter_data.nwds)
4801416c
BG		 1387 ah->opmode = NL80211_IFTYPE_AP;
1388 else if (iter_data.nadhocs)
1389 ah->opmode = NL80211_IFTYPE_ADHOC;
1390 else
1391 ah->opmode = NL80211_IFTYPE_STATION;
1392 }
5640b08e 1393
4e30ffa2
VN		 1394 /*
1395 * Enable MIB interrupts when there are hardware phy counters.
4e30ffa2 1396 */
4801416c 1397 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
3448f912
LR		 1398 if (ah->config.enable_ani)
1399 ah->imask |= ATH9K_INT_MIB;
3069168c 1400 ah->imask |= ATH9K_INT_TSFOOR;
4801416c
BG		 1401 } else {
1402 ah->imask &= ~ATH9K_INT_MIB;
1403 ah->imask &= ~ATH9K_INT_TSFOOR;
4af9cf4f
S		 1404 }
1405
3069168c 1406 ath9k_hw_set_interrupts(ah, ah->imask);
4e30ffa2 1407
4801416c 1408 /* Set up ANI */
2e5ef459 1409 if (iter_data.naps > 0) {
729da390 1410 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
6c3118e2 1411 sc->sc_flags |= SC_OP_ANI_RUN;
3d536acf 1412 ath_start_ani(common);
f60c49b6
RM		 1413 } else {
1414 sc->sc_flags &= ~SC_OP_ANI_RUN;
1415 del_timer_sync(&common->ani.timer);
6c3118e2 1416 }
4801416c 1417}
6f255425 1418
4801416c
BG		 1419/* Called with sc->mutex held, vif counts set up properly. */
1420static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
1421 struct ieee80211_vif *vif)
1422{
9ac58615 1423 struct ath_softc *sc = hw->priv;
4801416c
BG		 1424
1425 ath9k_calculate_summary_state(hw, vif);
1426
1427 if (ath9k_uses_beacons(vif->type)) {
1428 int error;
4801416c
BG		 1429 /* This may fail because upper levels do not have beacons
1430 * properly configured yet. That's OK, we assume it
1431 * will be properly configured and then we will be notified
1432 * in the info_changed method and set up beacons properly
1433 * there.
1434 */
014cf3bb 1435 ath9k_set_beaconing_status(sc, false);
9ac58615 1436 error = ath_beacon_alloc(sc, vif);
391bd1c4 1437 if (!error)
4801416c 1438 ath_beacon_config(sc, vif);
014cf3bb 1439 ath9k_set_beaconing_status(sc, true);
4801416c 1440 }
f078f209
LR		 1441}
1442
4801416c
BG		 1443
1444static int ath9k_add_interface(struct ieee80211_hw *hw,
1445 struct ieee80211_vif *vif)
6b3b991d 1446{
9ac58615 1447 struct ath_softc *sc = hw->priv;
4801416c
BG		 1448 struct ath_hw *ah = sc->sc_ah;
1449 struct ath_common *common = ath9k_hw_common(ah);
4801416c 1450 int ret = 0;
6b3b991d 1451
96f372c9 1452 ath9k_ps_wakeup(sc);
4801416c 1453 mutex_lock(&sc->mutex);
6b3b991d 1454
4801416c
BG		 1455 switch (vif->type) {
1456 case NL80211_IFTYPE_STATION:
1457 case NL80211_IFTYPE_WDS:
1458 case NL80211_IFTYPE_ADHOC:
1459 case NL80211_IFTYPE_AP:
1460 case NL80211_IFTYPE_MESH_POINT:
1461 break;
1462 default:
1463 ath_err(common, "Interface type %d not yet supported\n",
1464 vif->type);
1465 ret = -EOPNOTSUPP;
1466 goto out;
1467 }
6b3b991d 1468
4801416c
BG		 1469 if (ath9k_uses_beacons(vif->type)) {
1470 if (sc->nbcnvifs >= ATH_BCBUF) {
1471 ath_err(common, "Not enough beacon buffers when adding"
1472 " new interface of type: %i\n",
1473 vif->type);
1474 ret = -ENOBUFS;
1475 goto out;
1476 }
1477 }
1478
59575d1c
RM		 1479 if ((ah->opmode == NL80211_IFTYPE_ADHOC) ||
1480 ((vif->type == NL80211_IFTYPE_ADHOC) &&
1481 sc->nvifs > 0)) {
4801416c
BG		 1482 ath_err(common, "Cannot create ADHOC interface when other"
1483 " interfaces already exist.\n");
1484 ret = -EINVAL;
1485 goto out;
6b3b991d 1486 }
4801416c
BG		 1487
1488 ath_dbg(common, ATH_DBG_CONFIG,
1489 "Attach a VIF of type: %d\n", vif->type);
1490
4801416c
BG		 1491 sc->nvifs++;
1492
1493 ath9k_do_vif_add_setup(hw, vif);
1494out:
1495 mutex_unlock(&sc->mutex);
96f372c9 1496 ath9k_ps_restore(sc);
4801416c 1497 return ret;
6b3b991d
RM		 1498}
1499
1500static int ath9k_change_interface(struct ieee80211_hw *hw,
1501 struct ieee80211_vif *vif,
1502 enum nl80211_iftype new_type,
1503 bool p2p)
1504{
9ac58615 1505 struct ath_softc *sc = hw->priv;
6b3b991d 1506 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
6dab55bf 1507 int ret = 0;
6b3b991d
RM		 1508
1509 ath_dbg(common, ATH_DBG_CONFIG, "Change Interface\n");
1510 mutex_lock(&sc->mutex);
96f372c9 1511 ath9k_ps_wakeup(sc);
6b3b991d 1512
4801416c
BG		 1513 /* See if new interface type is valid. */
1514 if ((new_type == NL80211_IFTYPE_ADHOC) &&
1515 (sc->nvifs > 1)) {
1516 ath_err(common, "When using ADHOC, it must be the only"
1517 " interface.\n");
1518 ret = -EINVAL;
1519 goto out;
1520 }
1521
1522 if (ath9k_uses_beacons(new_type) &&
1523 !ath9k_uses_beacons(vif->type)) {
6b3b991d
RM		 1524 if (sc->nbcnvifs >= ATH_BCBUF) {
1525 ath_err(common, "No beacon slot available\n");
6dab55bf
DC		 1526 ret = -ENOBUFS;
1527 goto out;
6b3b991d 1528 }
6b3b991d 1529 }
4801416c
BG		 1530
1531 /* Clean up old vif stuff */
1532 if (ath9k_uses_beacons(vif->type))
1533 ath9k_reclaim_beacon(sc, vif);
1534
1535 /* Add new settings */
6b3b991d
RM		 1536 vif->type = new_type;
1537 vif->p2p = p2p;
1538
4801416c 1539 ath9k_do_vif_add_setup(hw, vif);
6dab55bf 1540out:
96f372c9 1541 ath9k_ps_restore(sc);
6b3b991d 1542 mutex_unlock(&sc->mutex);
6dab55bf 1543 return ret;
6b3b991d
RM		 1544}
1545
8feceb67 1546static void ath9k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1547 struct ieee80211_vif *vif)
f078f209 1548{
9ac58615 1549 struct ath_softc *sc = hw->priv;
c46917bb 1550 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
f078f209 1551
226afe68 1552 ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 1553
96f372c9 1554 ath9k_ps_wakeup(sc);
141b38b6
S		 1555 mutex_lock(&sc->mutex);
1556
4801416c 1557 sc->nvifs--;
580f0b8a 1558
8feceb67 1559 /* Reclaim beacon resources */
4801416c 1560 if (ath9k_uses_beacons(vif->type))
6b3b991d 1561 ath9k_reclaim_beacon(sc, vif);
2c3db3d5 1562
4801416c 1563 ath9k_calculate_summary_state(hw, NULL);
141b38b6
S		 1564
1565 mutex_unlock(&sc->mutex);
96f372c9 1566 ath9k_ps_restore(sc);
f078f209
LR		 1567}
1568
fbab7390 1569static void ath9k_enable_ps(struct ath_softc *sc)
3f7c5c10 1570{
3069168c
PR		 1571 struct ath_hw *ah = sc->sc_ah;
1572
3f7c5c10 1573 sc->ps_enabled = true;
3069168c
PR		 1574 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1575 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1576 ah->imask |= ATH9K_INT_TIM_TIMER;
1577 ath9k_hw_set_interrupts(ah, ah->imask);
3f7c5c10 1578 }
fdf76622 1579 ath9k_hw_setrxabort(ah, 1);
3f7c5c10 1580 }
3f7c5c10
SB		 1581}
1582
845d708e
SB		 1583static void ath9k_disable_ps(struct ath_softc *sc)
1584{
1585 struct ath_hw *ah = sc->sc_ah;
1586
1587 sc->ps_enabled = false;
1588 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1589 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1590 ath9k_hw_setrxabort(ah, 0);
1591 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1592 PS_WAIT_FOR_CAB |
1593 PS_WAIT_FOR_PSPOLL_DATA |
1594 PS_WAIT_FOR_TX_ACK);
1595 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1596 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1597 ath9k_hw_set_interrupts(ah, ah->imask);
1598 }
1599 }
1600
1601}
1602
e8975581 1603static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1604{
9ac58615 1605 struct ath_softc *sc = hw->priv;
3430098a
FF		 1606 struct ath_hw *ah = sc->sc_ah;
1607 struct ath_common *common = ath9k_hw_common(ah);
e8975581 1608 struct ieee80211_conf *conf = &hw->conf;
7545daf4 1609 bool disable_radio = false;
f078f209 1610
aa33de09 1611 mutex_lock(&sc->mutex);
141b38b6 1612
194b7c13
LR		 1613 /*
1614 * Leave this as the first check because we need to turn on the
1615 * radio if it was disabled before prior to processing the rest
1616 * of the changes. Likewise we must only disable the radio towards
1617 * the end.
1618 */
64839170 1619 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
7545daf4
FF		 1620 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1621 if (!sc->ps_idle) {
68a89116 1622 ath_radio_enable(sc, hw);
226afe68
JP		 1623 ath_dbg(common, ATH_DBG_CONFIG,
1624 "not-idle: enabling radio\n");
7545daf4
FF		 1625 } else {
1626 disable_radio = true;
64839170
LR		 1627 }
1628 }
1629
e7824a50
LR		 1630 /*
1631 * We just prepare to enable PS. We have to wait until our AP has
1632 * ACK'd our null data frame to disable RX otherwise we'll ignore
1633 * those ACKs and end up retransmitting the same null data frames.
1634 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1635 */
3cbb5dd7 1636 if (changed & IEEE80211_CONF_CHANGE_PS) {
8ab2cd09
LR		 1637 unsigned long flags;
1638 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fbab7390
SB		 1639 if (conf->flags & IEEE80211_CONF_PS)
1640 ath9k_enable_ps(sc);
845d708e
SB		 1641 else
1642 ath9k_disable_ps(sc);
8ab2cd09 1643 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3cbb5dd7
VN		 1644 }
1645
199afd9d
S		 1646 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1647 if (conf->flags & IEEE80211_CONF_MONITOR) {
226afe68
JP		 1648 ath_dbg(common, ATH_DBG_CONFIG,
1649 "Monitor mode is enabled\n");
5f841b41
RM		 1650 sc->sc_ah->is_monitoring = true;
1651 } else {
226afe68
JP		 1652 ath_dbg(common, ATH_DBG_CONFIG,
1653 "Monitor mode is disabled\n");
5f841b41 1654 sc->sc_ah->is_monitoring = false;
199afd9d
S		 1655 }
1656 }
1657
4797938c 1658 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 1659 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 1660 int pos = curchan->hw_value;
3430098a
FF		 1661 int old_pos = -1;
1662 unsigned long flags;
1663
1664 if (ah->curchan)
1665 old_pos = ah->curchan - &ah->channels[0];
ae5eb026 1666
5ee08656
FF		 1667 if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
1668 sc->sc_flags |= SC_OP_OFFCHANNEL;
1669 else
1670 sc->sc_flags &= ~SC_OP_OFFCHANNEL;
0e2dedf9 1671
8c79a610
BG		 1672 ath_dbg(common, ATH_DBG_CONFIG,
1673 "Set channel: %d MHz type: %d\n",
1674 curchan->center_freq, conf->channel_type);
f078f209 1675
de87f736
RM		 1676 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
1677 curchan, conf->channel_type);
e11602b7 1678
3430098a
FF		 1679 /* update survey stats for the old channel before switching */
1680 spin_lock_irqsave(&common->cc_lock, flags);
1681 ath_update_survey_stats(sc);
1682 spin_unlock_irqrestore(&common->cc_lock, flags);
1683
1684 /*
1685 * If the operating channel changes, change the survey in-use flags
1686 * along with it.
1687 * Reset the survey data for the new channel, unless we're switching
1688 * back to the operating channel from an off-channel operation.
1689 */
1690 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1691 sc->cur_survey != &sc->survey[pos]) {
1692
1693 if (sc->cur_survey)
1694 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1695
1696 sc->cur_survey = &sc->survey[pos];
1697
1698 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1699 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1700 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1701 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1702 }
1703
0e2dedf9 1704 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
3800276a 1705 ath_err(common, "Unable to set channel\n");
aa33de09 1706 mutex_unlock(&sc->mutex);
e11602b7
S		 1707 return -EINVAL;
1708 }
3430098a
FF		 1709
1710 /*
1711 * The most recent snapshot of channel->noisefloor for the old
1712 * channel is only available after the hardware reset. Copy it to
1713 * the survey stats now.
1714 */
1715 if (old_pos >= 0)
1716 ath_update_survey_nf(sc, old_pos);
094d05dc 1717 }
f078f209 1718
c9f6a656 1719 if (changed & IEEE80211_CONF_CHANGE_POWER) {
603b3eef
BG		 1720 ath_dbg(common, ATH_DBG_CONFIG,
1721 "Set power: %d\n", conf->power_level);
17d7904d 1722 sc->config.txpowlimit = 2 * conf->power_level;
783cd01e 1723 ath9k_ps_wakeup(sc);
5048e8c3
RM		 1724 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1725 sc->config.txpowlimit, &sc->curtxpow);
783cd01e 1726 ath9k_ps_restore(sc);
c9f6a656 1727 }
f078f209 1728
64839170 1729 if (disable_radio) {
226afe68 1730 ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
68a89116 1731 ath_radio_disable(sc, hw);
64839170
LR		 1732 }
1733
aa33de09 1734 mutex_unlock(&sc->mutex);
141b38b6 1735
f078f209
LR		 1736 return 0;
1737}
1738
8feceb67
VT		 1739#define SUPPORTED_FILTERS \
1740 (FIF_PROMISC_IN_BSS | \
1741 FIF_ALLMULTI | \
1742 FIF_CONTROL | \
af6a3fc7 1743 FIF_PSPOLL | \
8feceb67
VT		 1744 FIF_OTHER_BSS | \
1745 FIF_BCN_PRBRESP_PROMISC | \
9c1d8e4a 1746 FIF_PROBE_REQ | \
8feceb67 1747 FIF_FCSFAIL)
c83be688 1748
8feceb67
VT		 1749/* FIXME: sc->sc_full_reset ? */
1750static void ath9k_configure_filter(struct ieee80211_hw *hw,
1751 unsigned int changed_flags,
1752 unsigned int *total_flags,
3ac64bee 1753 u64 multicast)
8feceb67 1754{
9ac58615 1755 struct ath_softc *sc = hw->priv;
8feceb67 1756 u32 rfilt;
f078f209 1757
8feceb67
VT		 1758 changed_flags &= SUPPORTED_FILTERS;
1759 *total_flags &= SUPPORTED_FILTERS;
f078f209 1760
b77f483f 1761 sc->rx.rxfilter = *total_flags;
aa68aeaa 1762 ath9k_ps_wakeup(sc);
8feceb67
VT		 1763 rfilt = ath_calcrxfilter(sc);
1764 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 1765 ath9k_ps_restore(sc);
f078f209 1766
226afe68
JP		 1767 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
1768 "Set HW RX filter: 0x%x\n", rfilt);
8feceb67 1769}
f078f209 1770
4ca77860
JB		 1771static int ath9k_sta_add(struct ieee80211_hw *hw,
1772 struct ieee80211_vif *vif,
1773 struct ieee80211_sta *sta)
8feceb67 1774{
9ac58615 1775 struct ath_softc *sc = hw->priv;
93ae2dd2
FF		 1776 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1777 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1778 struct ieee80211_key_conf ps_key = { };
f078f209 1779
4ca77860 1780 ath_node_attach(sc, sta);
f59a59fe
FF		 1781
1782 if (vif->type != NL80211_IFTYPE_AP &&
1783 vif->type != NL80211_IFTYPE_AP_VLAN)
1784 return 0;
1785
93ae2dd2 1786 an->ps_key = ath_key_config(common, vif, sta, &ps_key);
4ca77860
JB		 1787
1788 return 0;
1789}
1790
93ae2dd2
FF		 1791static void ath9k_del_ps_key(struct ath_softc *sc,
1792 struct ieee80211_vif *vif,
1793 struct ieee80211_sta *sta)
1794{
1795 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1796 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1797 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1798
1799 if (!an->ps_key)
1800 return;
1801
1802 ath_key_delete(common, &ps_key);
1803}
1804
4ca77860
JB		 1805static int ath9k_sta_remove(struct ieee80211_hw *hw,
1806 struct ieee80211_vif *vif,
1807 struct ieee80211_sta *sta)
1808{
9ac58615 1809 struct ath_softc *sc = hw->priv;
4ca77860 1810
93ae2dd2 1811 ath9k_del_ps_key(sc, vif, sta);
4ca77860
JB		 1812 ath_node_detach(sc, sta);
1813
1814 return 0;
f078f209
LR		 1815}
1816
5519541d
FF		 1817static void ath9k_sta_notify(struct ieee80211_hw *hw,
1818 struct ieee80211_vif *vif,
1819 enum sta_notify_cmd cmd,
1820 struct ieee80211_sta *sta)
1821{
1822 struct ath_softc *sc = hw->priv;
1823 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1824
1825 switch (cmd) {
1826 case STA_NOTIFY_SLEEP:
1827 an->sleeping = true;
1828 if (ath_tx_aggr_sleep(sc, an))
1829 ieee80211_sta_set_tim(sta);
1830 break;
1831 case STA_NOTIFY_AWAKE:
1832 an->sleeping = false;
1833 ath_tx_aggr_wakeup(sc, an);
1834 break;
1835 }
1836}
1837
141b38b6 1838static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 1839 const struct ieee80211_tx_queue_params *params)
f078f209 1840{
9ac58615 1841 struct ath_softc *sc = hw->priv;
c46917bb 1842 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
066dae93 1843 struct ath_txq *txq;
8feceb67 1844 struct ath9k_tx_queue_info qi;
066dae93 1845 int ret = 0;
f078f209 1846
8feceb67
VT		 1847 if (queue >= WME_NUM_AC)
1848 return 0;
f078f209 1849
066dae93
FF		 1850 txq = sc->tx.txq_map[queue];
1851
96f372c9 1852 ath9k_ps_wakeup(sc);
141b38b6
S		 1853 mutex_lock(&sc->mutex);
1854
1ffb0610
S		 1855 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1856
8feceb67
VT		 1857 qi.tqi_aifs = params->aifs;
1858 qi.tqi_cwmin = params->cw_min;
1859 qi.tqi_cwmax = params->cw_max;
1860 qi.tqi_burstTime = params->txop;
f078f209 1861
226afe68
JP		 1862 ath_dbg(common, ATH_DBG_CONFIG,
1863 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1864 queue, txq->axq_qnum, params->aifs, params->cw_min,
1865 params->cw_max, params->txop);
f078f209 1866
066dae93 1867 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
8feceb67 1868 if (ret)
3800276a 1869 ath_err(common, "TXQ Update failed\n");
f078f209 1870
94db2936 1871 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
066dae93 1872 if (queue == WME_AC_BE && !ret)
94db2936
VN		 1873 ath_beaconq_config(sc);
1874
141b38b6 1875 mutex_unlock(&sc->mutex);
96f372c9 1876 ath9k_ps_restore(sc);
141b38b6 1877
8feceb67
VT		 1878 return ret;
1879}
f078f209 1880
8feceb67
VT		 1881static int ath9k_set_key(struct ieee80211_hw *hw,
1882 enum set_key_cmd cmd,
dc822b5d
JB		 1883 struct ieee80211_vif *vif,
1884 struct ieee80211_sta *sta,
8feceb67
VT		 1885 struct ieee80211_key_conf *key)
1886{
9ac58615 1887 struct ath_softc *sc = hw->priv;
c46917bb 1888 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67 1889 int ret = 0;
f078f209 1890
3e6109c5 1891 if (ath9k_modparam_nohwcrypt)
b3bd89ce
JM		 1892 return -ENOSPC;
1893
cfdc9a8b
JM		 1894 if (vif->type == NL80211_IFTYPE_ADHOC &&
1895 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1896 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1897 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1898 /*
1899 * For now, disable hw crypto for the RSN IBSS group keys. This
1900 * could be optimized in the future to use a modified key cache
1901 * design to support per-STA RX GTK, but until that gets
1902 * implemented, use of software crypto for group addressed
1903 * frames is a acceptable to allow RSN IBSS to be used.
1904 */
1905 return -EOPNOTSUPP;
1906 }
1907
141b38b6 1908 mutex_lock(&sc->mutex);
3cbb5dd7 1909 ath9k_ps_wakeup(sc);
226afe68 1910 ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 1911
8feceb67
VT		 1912 switch (cmd) {
1913 case SET_KEY:
93ae2dd2
FF		 1914 if (sta)
1915 ath9k_del_ps_key(sc, vif, sta);
1916
040e539e 1917 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM		 1918 if (ret >= 0) {
1919 key->hw_key_idx = ret;
8feceb67
VT		 1920 /* push IV and Michael MIC generation to stack */
1921 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
97359d12 1922 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
8feceb67 1923 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
97359d12
JB		 1924 if (sc->sc_ah->sw_mgmt_crypto &&
1925 key->cipher == WLAN_CIPHER_SUITE_CCMP)
0ced0e17 1926 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 1927 ret = 0;
8feceb67
VT		 1928 }
1929 break;
1930 case DISABLE_KEY:
040e539e 1931 ath_key_delete(common, key);
8feceb67
VT		 1932 break;
1933 default:
1934 ret = -EINVAL;
1935 }
f078f209 1936
3cbb5dd7 1937 ath9k_ps_restore(sc);
141b38b6
S		 1938 mutex_unlock(&sc->mutex);
1939
8feceb67
VT		 1940 return ret;
1941}
4f5ef75b
RM		 1942static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1943{
1944 struct ath_softc *sc = data;
1945 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1946 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1947 struct ath_vif *avp = (void *)vif->drv_priv;
1948
2e5ef459
RM		 1949 /*
1950 * Skip iteration if primary station vif's bss info
1951 * was not changed
1952 */
1953 if (sc->sc_flags & SC_OP_PRIM_STA_VIF)
1954 return;
1955
1956 if (bss_conf->assoc) {
1957 sc->sc_flags |= SC_OP_PRIM_STA_VIF;
1958 avp->primary_sta_vif = true;
4f5ef75b
RM		 1959 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1960 common->curaid = bss_conf->aid;
1961 ath9k_hw_write_associd(sc->sc_ah);
2e5ef459 1962 ath_dbg(common, ATH_DBG_CONFIG,
99e4d43a
RM		 1963 "Bss Info ASSOC %d, bssid: %pM\n",
1964 bss_conf->aid, common->curbssid);
2e5ef459
RM		 1965 ath_beacon_config(sc, vif);
1966 /*
1967 * Request a re-configuration of Beacon related timers
1968 * on the receipt of the first Beacon frame (i.e.,
1969 * after time sync with the AP).
1970 */
1971 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1972 /* Reset rssi stats */
1973 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
1974 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
99e4d43a 1975
2e5ef459
RM		 1976 sc->sc_flags |= SC_OP_ANI_RUN;
1977 ath_start_ani(common);
4f5ef75b
RM		 1978 }
1979}
1980
1981static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
1982{
1983 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1984 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1985 struct ath_vif *avp = (void *)vif->drv_priv;
1986
2e5ef459
RM		 1987 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
1988 return;
1989
4f5ef75b
RM		 1990 /* Reconfigure bss info */
1991 if (avp->primary_sta_vif && !bss_conf->assoc) {
99e4d43a
RM		 1992 ath_dbg(common, ATH_DBG_CONFIG,
1993 "Bss Info DISASSOC %d, bssid %pM\n",
1994 common->curaid, common->curbssid);
1995 sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS);
4f5ef75b
RM		 1996 avp->primary_sta_vif = false;
1997 memset(common->curbssid, 0, ETH_ALEN);
1998 common->curaid = 0;
1999 }
2000
2001 ieee80211_iterate_active_interfaces_atomic(
2002 sc->hw, ath9k_bss_iter, sc);
2003
2004 /*
2005 * None of station vifs are associated.
2006 * Clear bssid & aid
2007 */
2e5ef459 2008 if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF)) {
4f5ef75b 2009 ath9k_hw_write_associd(sc->sc_ah);
99e4d43a
RM		 2010 /* Stop ANI */
2011 sc->sc_flags &= ~SC_OP_ANI_RUN;
2012 del_timer_sync(&common->ani.timer);
2013 }
4f5ef75b 2014}
f078f209 2015
8feceb67
VT		 2016static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2017 struct ieee80211_vif *vif,
2018 struct ieee80211_bss_conf *bss_conf,
2019 u32 changed)
2020{
9ac58615 2021 struct ath_softc *sc = hw->priv;
2d0ddec5 2022 struct ath_hw *ah = sc->sc_ah;
1510718d 2023 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 2024 struct ath_vif *avp = (void *)vif->drv_priv;
0005baf4 2025 int slottime;
c6089ccc 2026 int error;
f078f209 2027
96f372c9 2028 ath9k_ps_wakeup(sc);
141b38b6
S		 2029 mutex_lock(&sc->mutex);
2030
c6089ccc 2031 if (changed & BSS_CHANGED_BSSID) {
4f5ef75b 2032 ath9k_config_bss(sc, vif);
2d0ddec5 2033
226afe68
JP		 2034 ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n",
2035 common->curbssid, common->curaid);
c6089ccc 2036 }
2d0ddec5 2037
2e5ef459
RM		 2038 if (changed & BSS_CHANGED_IBSS) {
2039 /* There can be only one vif available */
2040 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2041 common->curaid = bss_conf->aid;
2042 ath9k_hw_write_associd(sc->sc_ah);
2043
2044 if (bss_conf->ibss_joined) {
2045 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
2046 sc->sc_flags |= SC_OP_ANI_RUN;
2047 ath_start_ani(common);
2048 } else {
2049 sc->sc_flags &= ~SC_OP_ANI_RUN;
2050 del_timer_sync(&common->ani.timer);
2051 }
2052 }
2053
c6089ccc
S		 2054 /* Enable transmission of beacons (AP, IBSS, MESH) */
2055 if ((changed & BSS_CHANGED_BEACON) ||
2056 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
014cf3bb 2057 ath9k_set_beaconing_status(sc, false);
9ac58615 2058 error = ath_beacon_alloc(sc, vif);
c6089ccc
S		 2059 if (!error)
2060 ath_beacon_config(sc, vif);
014cf3bb 2061 ath9k_set_beaconing_status(sc, true);
0005baf4
FF		 2062 }
2063
2064 if (changed & BSS_CHANGED_ERP_SLOT) {
2065 if (bss_conf->use_short_slot)
2066 slottime = 9;
2067 else
2068 slottime = 20;
2069 if (vif->type == NL80211_IFTYPE_AP) {
2070 /*
2071 * Defer update, so that connected stations can adjust
2072 * their settings at the same time.
2073 * See beacon.c for more details
2074 */
2075 sc->beacon.slottime = slottime;
2076 sc->beacon.updateslot = UPDATE;
2077 } else {
2078 ah->slottime = slottime;
2079 ath9k_hw_init_global_settings(ah);
2080 }
2d0ddec5
JB		 2081 }
2082
c6089ccc 2083 /* Disable transmission of beacons */
014cf3bb
RM		 2084 if ((changed & BSS_CHANGED_BEACON_ENABLED) &&
2085 !bss_conf->enable_beacon) {
2086 ath9k_set_beaconing_status(sc, false);
2087 avp->is_bslot_active = false;
2088 ath9k_set_beaconing_status(sc, true);
2089 }
2d0ddec5 2090
c6089ccc 2091 if (changed & BSS_CHANGED_BEACON_INT) {
c6089ccc
S		 2092 /*
2093 * In case of AP mode, the HW TSF has to be reset
2094 * when the beacon interval changes.
2095 */
2096 if (vif->type == NL80211_IFTYPE_AP) {
2097 sc->sc_flags |= SC_OP_TSF_RESET;
014cf3bb 2098 ath9k_set_beaconing_status(sc, false);
9ac58615 2099 error = ath_beacon_alloc(sc, vif);
2d0ddec5
JB		 2100 if (!error)
2101 ath_beacon_config(sc, vif);
014cf3bb 2102 ath9k_set_beaconing_status(sc, true);
99e4d43a 2103 } else
c6089ccc 2104 ath_beacon_config(sc, vif);
2d0ddec5
JB		 2105 }
2106
8feceb67 2107 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
226afe68
JP		 2108 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2109 bss_conf->use_short_preamble);
8feceb67
VT		 2110 if (bss_conf->use_short_preamble)
2111 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2112 else
2113 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2114 }
f078f209 2115
8feceb67 2116 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
226afe68
JP		 2117 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2118 bss_conf->use_cts_prot);
8feceb67
VT		 2119 if (bss_conf->use_cts_prot &&
2120 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2121 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2122 else
2123 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2124 }
f078f209 2125
141b38b6 2126 mutex_unlock(&sc->mutex);
96f372c9 2127 ath9k_ps_restore(sc);
8feceb67 2128}
f078f209 2129
8feceb67
VT		 2130static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2131{
9ac58615 2132 struct ath_softc *sc = hw->priv;
8feceb67 2133 u64 tsf;
f078f209 2134
141b38b6 2135 mutex_lock(&sc->mutex);
9abbfb27 2136 ath9k_ps_wakeup(sc);
141b38b6 2137 tsf = ath9k_hw_gettsf64(sc->sc_ah);
9abbfb27 2138 ath9k_ps_restore(sc);
141b38b6 2139 mutex_unlock(&sc->mutex);
f078f209 2140
8feceb67
VT		 2141 return tsf;
2142}
f078f209 2143
3b5d665b
AF		 2144static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2145{
9ac58615 2146 struct ath_softc *sc = hw->priv;
3b5d665b 2147
141b38b6 2148 mutex_lock(&sc->mutex);
9abbfb27 2149 ath9k_ps_wakeup(sc);
141b38b6 2150 ath9k_hw_settsf64(sc->sc_ah, tsf);
9abbfb27 2151 ath9k_ps_restore(sc);
141b38b6 2152 mutex_unlock(&sc->mutex);
3b5d665b
AF		 2153}
2154
8feceb67
VT		 2155static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2156{
9ac58615 2157 struct ath_softc *sc = hw->priv;
c83be688 2158
141b38b6 2159 mutex_lock(&sc->mutex);
21526d57
LR		 2160
2161 ath9k_ps_wakeup(sc);
141b38b6 2162 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR		 2163 ath9k_ps_restore(sc);
2164
141b38b6 2165 mutex_unlock(&sc->mutex);
8feceb67 2166}
f078f209 2167
8feceb67 2168static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 2169 struct ieee80211_vif *vif,
141b38b6
S		 2170 enum ieee80211_ampdu_mlme_action action,
2171 struct ieee80211_sta *sta,
0b01f030 2172 u16 tid, u16 *ssn, u8 buf_size)
8feceb67 2173{
9ac58615 2174 struct ath_softc *sc = hw->priv;
8feceb67 2175 int ret = 0;
f078f209 2176
85ad181e
JB		 2177 local_bh_disable();
2178
8feceb67
VT		 2179 switch (action) {
2180 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2181 if (!(sc->sc_flags & SC_OP_RXAGGR))
2182 ret = -ENOTSUPP;
8feceb67
VT		 2183 break;
2184 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2185 break;
2186 case IEEE80211_AMPDU_TX_START:
71a3bf3e
FF		 2187 if (!(sc->sc_flags & SC_OP_TXAGGR))
2188 return -EOPNOTSUPP;
2189
8b685ba9 2190 ath9k_ps_wakeup(sc);
231c3a1f
FF		 2191 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2192 if (!ret)
2193 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2194 ath9k_ps_restore(sc);
8feceb67
VT		 2195 break;
2196 case IEEE80211_AMPDU_TX_STOP:
8b685ba9 2197 ath9k_ps_wakeup(sc);
f83da965 2198 ath_tx_aggr_stop(sc, sta, tid);
c951ad35 2199 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2200 ath9k_ps_restore(sc);
8feceb67 2201 break;
b1720231 2202 case IEEE80211_AMPDU_TX_OPERATIONAL:
8b685ba9 2203 ath9k_ps_wakeup(sc);
8469cdef 2204 ath_tx_aggr_resume(sc, sta, tid);
8b685ba9 2205 ath9k_ps_restore(sc);
8469cdef 2206 break;
8feceb67 2207 default:
3800276a 2208 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
8feceb67
VT		 2209 }
2210
85ad181e
JB		 2211 local_bh_enable();
2212
8feceb67 2213 return ret;
f078f209
LR		 2214}
2215
62dad5b0
BP		 2216static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2217 struct survey_info *survey)
2218{
9ac58615 2219 struct ath_softc *sc = hw->priv;
3430098a 2220 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39162dbe 2221 struct ieee80211_supported_band *sband;
3430098a
FF		 2222 struct ieee80211_channel *chan;
2223 unsigned long flags;
2224 int pos;
2225
2226 spin_lock_irqsave(&common->cc_lock, flags);
2227 if (idx == 0)
2228 ath_update_survey_stats(sc);
39162dbe
FF		 2229
2230 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2231 if (sband && idx >= sband->n_channels) {
2232 idx -= sband->n_channels;
2233 sband = NULL;
2234 }
62dad5b0 2235
39162dbe
FF		 2236 if (!sband)
2237 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
62dad5b0 2238
3430098a
FF		 2239 if (!sband || idx >= sband->n_channels) {
2240 spin_unlock_irqrestore(&common->cc_lock, flags);
2241 return -ENOENT;
4f1a5a4b 2242 }
62dad5b0 2243
3430098a
FF		 2244 chan = &sband->channels[idx];
2245 pos = chan->hw_value;
2246 memcpy(survey, &sc->survey[pos], sizeof(*survey));
2247 survey->channel = chan;
2248 spin_unlock_irqrestore(&common->cc_lock, flags);
2249
62dad5b0
BP		 2250 return 0;
2251}
2252
e239d859
FF		 2253static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
2254{
9ac58615 2255 struct ath_softc *sc = hw->priv;
e239d859
FF		 2256 struct ath_hw *ah = sc->sc_ah;
2257
2258 mutex_lock(&sc->mutex);
2259 ah->coverage_class = coverage_class;
2260 ath9k_hw_init_global_settings(ah);
2261 mutex_unlock(&sc->mutex);
2262}
2263
69081624
VT		 2264static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
2265{
69081624 2266 struct ath_softc *sc = hw->priv;
99aa55b6
MSS		 2267 struct ath_hw *ah = sc->sc_ah;
2268 struct ath_common *common = ath9k_hw_common(ah);
86271e46
FF		 2269 int timeout = 200; /* ms */
2270 int i, j;
2f6fc351 2271 bool drain_txq;
69081624
VT		 2272
2273 mutex_lock(&sc->mutex);
69081624
VT		 2274 cancel_delayed_work_sync(&sc->tx_complete_work);
2275
99aa55b6
MSS		 2276 if (sc->sc_flags & SC_OP_INVALID) {
2277 ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
2278 mutex_unlock(&sc->mutex);
2279 return;
2280 }
2281
86271e46
FF		 2282 if (drop)
2283 timeout = 1;
69081624 2284
86271e46 2285 for (j = 0; j < timeout; j++) {
108697c4 2286 bool npend = false;
86271e46
FF		 2287
2288 if (j)
2289 usleep_range(1000, 2000);
69081624 2290
86271e46
FF		 2291 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2292 if (!ATH_TXQ_SETUP(sc, i))
2293 continue;
2294
108697c4
MSS		 2295 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
2296
2297 if (npend)
2298 break;
69081624 2299 }
86271e46
FF		 2300
2301 if (!npend)
2302 goto out;
69081624
VT		 2303 }
2304
51513906 2305 ath9k_ps_wakeup(sc);
2f6fc351
RM		 2306 spin_lock_bh(&sc->sc_pcu_lock);
2307 drain_txq = ath_drain_all_txq(sc, false);
2308 spin_unlock_bh(&sc->sc_pcu_lock);
2309 if (!drain_txq)
69081624 2310 ath_reset(sc, false);
51513906 2311 ath9k_ps_restore(sc);
d78f4b3e
SB		 2312 ieee80211_wake_queues(hw);
2313
86271e46 2314out:
69081624
VT		 2315 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
2316 mutex_unlock(&sc->mutex);
2317}
2318
15b91e83
VN		 2319static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2320{
2321 struct ath_softc *sc = hw->priv;
2322 int i;
2323
2324 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2325 if (!ATH_TXQ_SETUP(sc, i))
2326 continue;
2327
2328 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
2329 return true;
2330 }
2331 return false;
2332}
2333
5595f119 2334static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
ba4903f9
FF		 2335{
2336 struct ath_softc *sc = hw->priv;
2337 struct ath_hw *ah = sc->sc_ah;
2338 struct ieee80211_vif *vif;
2339 struct ath_vif *avp;
2340 struct ath_buf *bf;
2341 struct ath_tx_status ts;
2342 int status;
2343
2344 vif = sc->beacon.bslot[0];
2345 if (!vif)
2346 return 0;
2347
2348 avp = (void *)vif->drv_priv;
2349 if (!avp->is_bslot_active)
2350 return 0;
2351
2352 if (!sc->beacon.tx_processed) {
2353 tasklet_disable(&sc->bcon_tasklet);
2354
2355 bf = avp->av_bcbuf;
2356 if (!bf || !bf->bf_mpdu)
2357 goto skip;
2358
2359 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2360 if (status == -EINPROGRESS)
2361 goto skip;
2362
2363 sc->beacon.tx_processed = true;
2364 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2365
2366skip:
2367 tasklet_enable(&sc->bcon_tasklet);
2368 }
2369
2370 return sc->beacon.tx_last;
2371}
2372
6baff7f9 2373struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2374 .tx = ath9k_tx,
2375 .start = ath9k_start,
2376 .stop = ath9k_stop,
2377 .add_interface = ath9k_add_interface,
6b3b991d 2378 .change_interface = ath9k_change_interface,
8feceb67
VT		 2379 .remove_interface = ath9k_remove_interface,
2380 .config = ath9k_config,
8feceb67 2381 .configure_filter = ath9k_configure_filter,
4ca77860
JB		 2382 .sta_add = ath9k_sta_add,
2383 .sta_remove = ath9k_sta_remove,
5519541d 2384 .sta_notify = ath9k_sta_notify,
8feceb67 2385 .conf_tx = ath9k_conf_tx,
8feceb67 2386 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2387 .set_key = ath9k_set_key,
8feceb67 2388 .get_tsf = ath9k_get_tsf,
3b5d665b 2389 .set_tsf = ath9k_set_tsf,
8feceb67 2390 .reset_tsf = ath9k_reset_tsf,
4233df6b 2391 .ampdu_action = ath9k_ampdu_action,
62dad5b0 2392 .get_survey = ath9k_get_survey,
3b319aae 2393 .rfkill_poll = ath9k_rfkill_poll_state,
e239d859 2394 .set_coverage_class = ath9k_set_coverage_class,
69081624 2395 .flush = ath9k_flush,
15b91e83 2396 .tx_frames_pending = ath9k_tx_frames_pending,
ba4903f9 2397 .tx_last_beacon = ath9k_tx_last_beacon,
8feceb67 2398};
Linux kernel - Deliverables
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