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ath9k: get rid of tx_info_priv
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
af03abec 19#include "btcoex.h"
f078f209 20
f078f209
LR		 21static char *dev_info = "ath9k";
22
23MODULE_AUTHOR("Atheros Communications");
24MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
25MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
26MODULE_LICENSE("Dual BSD/GPL");
27
b3bd89ce
JM		 28static int modparam_nohwcrypt;
29module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
30MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
31
faa27fae
LR		 32static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
33module_param_named(debug, ath9k_debug, uint, 0);
af1fc67c 34MODULE_PARM_DESC(debug, "Debugging mask");
faa27fae 35
5f8e077c
LR		 36/* We use the hw_value as an index into our private channel structure */
37
38#define CHAN2G(_freq, _idx) { \
39 .center_freq = (_freq), \
40 .hw_value = (_idx), \
eeddfd9d 41 .max_power = 20, \
5f8e077c
LR		 42}
43
44#define CHAN5G(_freq, _idx) { \
45 .band = IEEE80211_BAND_5GHZ, \
46 .center_freq = (_freq), \
47 .hw_value = (_idx), \
eeddfd9d 48 .max_power = 20, \
5f8e077c
LR		 49}
50
51/* Some 2 GHz radios are actually tunable on 2312-2732
52 * on 5 MHz steps, we support the channels which we know
53 * we have calibration data for all cards though to make
54 * this static */
55static struct ieee80211_channel ath9k_2ghz_chantable[] = {
56 CHAN2G(2412, 0), /* Channel 1 */
57 CHAN2G(2417, 1), /* Channel 2 */
58 CHAN2G(2422, 2), /* Channel 3 */
59 CHAN2G(2427, 3), /* Channel 4 */
60 CHAN2G(2432, 4), /* Channel 5 */
61 CHAN2G(2437, 5), /* Channel 6 */
62 CHAN2G(2442, 6), /* Channel 7 */
63 CHAN2G(2447, 7), /* Channel 8 */
64 CHAN2G(2452, 8), /* Channel 9 */
65 CHAN2G(2457, 9), /* Channel 10 */
66 CHAN2G(2462, 10), /* Channel 11 */
67 CHAN2G(2467, 11), /* Channel 12 */
68 CHAN2G(2472, 12), /* Channel 13 */
69 CHAN2G(2484, 13), /* Channel 14 */
70};
71
72/* Some 5 GHz radios are actually tunable on XXXX-YYYY
73 * on 5 MHz steps, we support the channels which we know
74 * we have calibration data for all cards though to make
75 * this static */
76static struct ieee80211_channel ath9k_5ghz_chantable[] = {
77 /* _We_ call this UNII 1 */
78 CHAN5G(5180, 14), /* Channel 36 */
79 CHAN5G(5200, 15), /* Channel 40 */
80 CHAN5G(5220, 16), /* Channel 44 */
81 CHAN5G(5240, 17), /* Channel 48 */
82 /* _We_ call this UNII 2 */
83 CHAN5G(5260, 18), /* Channel 52 */
84 CHAN5G(5280, 19), /* Channel 56 */
85 CHAN5G(5300, 20), /* Channel 60 */
86 CHAN5G(5320, 21), /* Channel 64 */
87 /* _We_ call this "Middle band" */
88 CHAN5G(5500, 22), /* Channel 100 */
89 CHAN5G(5520, 23), /* Channel 104 */
90 CHAN5G(5540, 24), /* Channel 108 */
91 CHAN5G(5560, 25), /* Channel 112 */
92 CHAN5G(5580, 26), /* Channel 116 */
93 CHAN5G(5600, 27), /* Channel 120 */
94 CHAN5G(5620, 28), /* Channel 124 */
95 CHAN5G(5640, 29), /* Channel 128 */
96 CHAN5G(5660, 30), /* Channel 132 */
97 CHAN5G(5680, 31), /* Channel 136 */
98 CHAN5G(5700, 32), /* Channel 140 */
99 /* _We_ call this UNII 3 */
100 CHAN5G(5745, 33), /* Channel 149 */
101 CHAN5G(5765, 34), /* Channel 153 */
102 CHAN5G(5785, 35), /* Channel 157 */
103 CHAN5G(5805, 36), /* Channel 161 */
104 CHAN5G(5825, 37), /* Channel 165 */
105};
106
ce111bad
LR		 107static void ath_cache_conf_rate(struct ath_softc *sc,
108 struct ieee80211_conf *conf)
ff37e337 109{
030bb495
LR		 110 switch (conf->channel->band) {
111 case IEEE80211_BAND_2GHZ:
112 if (conf_is_ht20(conf))
113 sc->cur_rate_table =
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
115 else if (conf_is_ht40_minus(conf))
116 sc->cur_rate_table =
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
118 else if (conf_is_ht40_plus(conf))
119 sc->cur_rate_table =
120 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 121 else
030bb495
LR		 122 sc->cur_rate_table =
123 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 124 break;
125 case IEEE80211_BAND_5GHZ:
126 if (conf_is_ht20(conf))
127 sc->cur_rate_table =
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
129 else if (conf_is_ht40_minus(conf))
130 sc->cur_rate_table =
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
132 else if (conf_is_ht40_plus(conf))
133 sc->cur_rate_table =
134 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
135 else
96742256
LR		 136 sc->cur_rate_table =
137 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 138 break;
139 default:
ce111bad 140 BUG_ON(1);
030bb495
LR		 141 break;
142 }
ff37e337
S		 143}
144
145static void ath_update_txpow(struct ath_softc *sc)
146{
cbe61d8a 147 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 148 u32 txpow;
149
17d7904d
S		 150 if (sc->curtxpow != sc->config.txpowlimit) {
151 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S		 152 /* read back in case value is clamped */
153 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 154 sc->curtxpow = txpow;
ff37e337
S		 155 }
156}
157
158static u8 parse_mpdudensity(u8 mpdudensity)
159{
160 /*
161 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
162 * 0 for no restriction
163 * 1 for 1/4 us
164 * 2 for 1/2 us
165 * 3 for 1 us
166 * 4 for 2 us
167 * 5 for 4 us
168 * 6 for 8 us
169 * 7 for 16 us
170 */
171 switch (mpdudensity) {
172 case 0:
173 return 0;
174 case 1:
175 case 2:
176 case 3:
177 /* Our lower layer calculations limit our precision to
178 1 microsecond */
179 return 1;
180 case 4:
181 return 2;
182 case 5:
183 return 4;
184 case 6:
185 return 8;
186 case 7:
187 return 16;
188 default:
189 return 0;
190 }
191}
192
193static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
194{
4f0fc7c3 195 const struct ath_rate_table *rate_table = NULL;
ff37e337
S		 196 struct ieee80211_supported_band *sband;
197 struct ieee80211_rate *rate;
198 int i, maxrates;
199
200 switch (band) {
201 case IEEE80211_BAND_2GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
203 break;
204 case IEEE80211_BAND_5GHZ:
205 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
206 break;
207 default:
208 break;
209 }
210
211 if (rate_table == NULL)
212 return;
213
214 sband = &sc->sbands[band];
215 rate = sc->rates[band];
216
217 if (rate_table->rate_cnt > ATH_RATE_MAX)
218 maxrates = ATH_RATE_MAX;
219 else
220 maxrates = rate_table->rate_cnt;
221
222 for (i = 0; i < maxrates; i++) {
223 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
224 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 225 if (rate_table->info[i].short_preamble) {
226 rate[i].hw_value_short = rate_table->info[i].ratecode |
227 rate_table->info[i].short_preamble;
228 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
229 }
ff37e337 230 sband->n_bitrates++;
f46730d1 231
c46917bb
LR		 232 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
233 "Rate: %2dMbps, ratecode: %2d\n",
234 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 235 }
236}
237
82880a7c
VT		 238static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
239 struct ieee80211_hw *hw)
240{
241 struct ieee80211_channel *curchan = hw->conf.channel;
242 struct ath9k_channel *channel;
243 u8 chan_idx;
244
245 chan_idx = curchan->hw_value;
246 channel = &sc->sc_ah->channels[chan_idx];
247 ath9k_update_ichannel(sc, hw, channel);
248 return channel;
249}
250
9ecdef4b 251static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR		 252{
253 unsigned long flags;
254 bool ret;
255
9ecdef4b
LR		 256 spin_lock_irqsave(&sc->sc_pm_lock, flags);
257 ret = ath9k_hw_setpower(sc->sc_ah, mode);
258 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR		 259
260 return ret;
261}
262
a91d75ae
LR		 263void ath9k_ps_wakeup(struct ath_softc *sc)
264{
265 unsigned long flags;
266
267 spin_lock_irqsave(&sc->sc_pm_lock, flags);
268 if (++sc->ps_usecount != 1)
269 goto unlock;
270
9ecdef4b 271 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae
LR		 272
273 unlock:
274 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
275}
276
277void ath9k_ps_restore(struct ath_softc *sc)
278{
279 unsigned long flags;
280
281 spin_lock_irqsave(&sc->sc_pm_lock, flags);
282 if (--sc->ps_usecount != 0)
283 goto unlock;
284
285 if (sc->ps_enabled &&
286 !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
287 SC_OP_WAIT_FOR_CAB |
288 SC_OP_WAIT_FOR_PSPOLL_DATA |
289 SC_OP_WAIT_FOR_TX_ACK)))
9ecdef4b 290 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
a91d75ae
LR		 291
292 unlock:
293 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
294}
295
ff37e337
S		 296/*
297 * Set/change channels. If the channel is really being changed, it's done
298 * by reseting the chip. To accomplish this we must first cleanup any pending
299 * DMA, then restart stuff.
300*/
0e2dedf9
JM		 301int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
302 struct ath9k_channel *hchan)
ff37e337 303{
cbe61d8a 304 struct ath_hw *ah = sc->sc_ah;
c46917bb 305 struct ath_common *common = ath9k_hw_common(ah);
25c56eec 306 struct ieee80211_conf *conf = &common->hw->conf;
ff37e337 307 bool fastcc = true, stopped;
ae8d2858
LR		 308 struct ieee80211_channel *channel = hw->conf.channel;
309 int r;
ff37e337
S		 310
311 if (sc->sc_flags & SC_OP_INVALID)
312 return -EIO;
313
3cbb5dd7
VN		 314 ath9k_ps_wakeup(sc);
315
c0d7c7af
LR		 316 /*
317 * This is only performed if the channel settings have
318 * actually changed.
319 *
320 * To switch channels clear any pending DMA operations;
321 * wait long enough for the RX fifo to drain, reset the
322 * hardware at the new frequency, and then re-enable
323 * the relevant bits of the h/w.
324 */
325 ath9k_hw_set_interrupts(ah, 0);
043a0405 326 ath_drain_all_txq(sc, false);
c0d7c7af 327 stopped = ath_stoprecv(sc);
ff37e337 328
c0d7c7af
LR		 329 /* XXX: do not flush receive queue here. We don't want
330 * to flush data frames already in queue because of
331 * changing channel. */
ff37e337 332
c0d7c7af
LR		 333 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
334 fastcc = false;
335
c46917bb 336 ath_print(common, ATH_DBG_CONFIG,
25c56eec 337 "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n",
c46917bb 338 sc->sc_ah->curchan->channel,
25c56eec 339 channel->center_freq, conf_is_ht40(conf));
ff37e337 340
c0d7c7af
LR		 341 spin_lock_bh(&sc->sc_resetlock);
342
343 r = ath9k_hw_reset(ah, hchan, fastcc);
344 if (r) {
c46917bb
LR		 345 ath_print(common, ATH_DBG_FATAL,
346 "Unable to reset channel (%u Mhz) "
347 "reset status %d\n",
348 channel->center_freq, r);
c0d7c7af 349 spin_unlock_bh(&sc->sc_resetlock);
3989279c 350 goto ps_restore;
ff37e337 351 }
c0d7c7af
LR		 352 spin_unlock_bh(&sc->sc_resetlock);
353
c0d7c7af
LR		 354 sc->sc_flags &= ~SC_OP_FULL_RESET;
355
356 if (ath_startrecv(sc) != 0) {
c46917bb
LR		 357 ath_print(common, ATH_DBG_FATAL,
358 "Unable to restart recv logic\n");
3989279c
GJ		 359 r = -EIO;
360 goto ps_restore;
c0d7c7af
LR		 361 }
362
363 ath_cache_conf_rate(sc, &hw->conf);
364 ath_update_txpow(sc);
17d7904d 365 ath9k_hw_set_interrupts(ah, sc->imask);
3989279c
GJ		 366
367 ps_restore:
3cbb5dd7 368 ath9k_ps_restore(sc);
3989279c 369 return r;
ff37e337
S		 370}
371
372/*
373 * This routine performs the periodic noise floor calibration function
374 * that is used to adjust and optimize the chip performance. This
375 * takes environmental changes (location, temperature) into account.
376 * When the task is complete, it reschedules itself depending on the
377 * appropriate interval that was calculated.
378 */
379static void ath_ani_calibrate(unsigned long data)
380{
20977d3e
S		 381 struct ath_softc *sc = (struct ath_softc *)data;
382 struct ath_hw *ah = sc->sc_ah;
c46917bb 383 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S		 384 bool longcal = false;
385 bool shortcal = false;
386 bool aniflag = false;
387 unsigned int timestamp = jiffies_to_msecs(jiffies);
20977d3e 388 u32 cal_interval, short_cal_interval;
ff37e337 389
20977d3e
S		 390 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
391 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337
S		 392
393 /*
394 * don't calibrate when we're scanning.
395 * we are most likely not on our home channel.
396 */
e5f0921a 397 spin_lock(&sc->ani_lock);
0c98de65 398 if (sc->sc_flags & SC_OP_SCANNING)
20977d3e 399 goto set_timer;
ff37e337 400
1ffc1c61
JM		 401 /* Only calibrate if awake */
402 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
403 goto set_timer;
404
405 ath9k_ps_wakeup(sc);
406
ff37e337 407 /* Long calibration runs independently of short calibration. */
3d536acf 408 if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 409 longcal = true;
c46917bb 410 ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
3d536acf 411 common->ani.longcal_timer = timestamp;
ff37e337
S		 412 }
413
17d7904d 414 /* Short calibration applies only while caldone is false */
3d536acf
LR		 415 if (!common->ani.caldone) {
416 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 417 shortcal = true;
c46917bb
LR		 418 ath_print(common, ATH_DBG_ANI,
419 "shortcal @%lu\n", jiffies);
3d536acf
LR		 420 common->ani.shortcal_timer = timestamp;
421 common->ani.resetcal_timer = timestamp;
ff37e337
S		 422 }
423 } else {
3d536acf 424 if ((timestamp - common->ani.resetcal_timer) >=
ff37e337 425 ATH_RESTART_CALINTERVAL) {
3d536acf
LR		 426 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
427 if (common->ani.caldone)
428 common->ani.resetcal_timer = timestamp;
ff37e337
S		 429 }
430 }
431
432 /* Verify whether we must check ANI */
3d536acf 433 if ((timestamp - common->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
ff37e337 434 aniflag = true;
3d536acf 435 common->ani.checkani_timer = timestamp;
ff37e337
S		 436 }
437
438 /* Skip all processing if there's nothing to do. */
439 if (longcal || shortcal || aniflag) {
440 /* Call ANI routine if necessary */
441 if (aniflag)
22e66a4c 442 ath9k_hw_ani_monitor(ah, ah->curchan);
ff37e337
S		 443
444 /* Perform calibration if necessary */
445 if (longcal || shortcal) {
3d536acf 446 common->ani.caldone =
43c27613
LR		 447 ath9k_hw_calibrate(ah,
448 ah->curchan,
449 common->rx_chainmask,
450 longcal);
379f0440
S		 451
452 if (longcal)
3d536acf 453 common->ani.noise_floor = ath9k_hw_getchan_noise(ah,
379f0440
S		 454 ah->curchan);
455
c46917bb
LR		 456 ath_print(common, ATH_DBG_ANI,
457 " calibrate chan %u/%x nf: %d\n",
458 ah->curchan->channel,
459 ah->curchan->channelFlags,
3d536acf 460 common->ani.noise_floor);
ff37e337
S		 461 }
462 }
463
1ffc1c61
JM		 464 ath9k_ps_restore(sc);
465
20977d3e 466set_timer:
e5f0921a 467 spin_unlock(&sc->ani_lock);
ff37e337
S		 468 /*
469 * Set timer interval based on previous results.
470 * The interval must be the shortest necessary to satisfy ANI,
471 * short calibration and long calibration.
472 */
aac9207e 473 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 474 if (sc->sc_ah->config.enable_ani)
aac9207e 475 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
3d536acf 476 if (!common->ani.caldone)
20977d3e 477 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 478
3d536acf 479 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S		 480}
481
3d536acf 482static void ath_start_ani(struct ath_common *common)
415f738e
S		 483{
484 unsigned long timestamp = jiffies_to_msecs(jiffies);
485
3d536acf
LR		 486 common->ani.longcal_timer = timestamp;
487 common->ani.shortcal_timer = timestamp;
488 common->ani.checkani_timer = timestamp;
415f738e 489
3d536acf 490 mod_timer(&common->ani.timer,
415f738e
S		 491 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
492}
493
ff37e337
S		 494/*
495 * Update tx/rx chainmask. For legacy association,
496 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 497 * the chainmask configuration, for bt coexistence, use
498 * the chainmask configuration even in legacy mode.
ff37e337 499 */
0e2dedf9 500void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337 501{
af03abec 502 struct ath_hw *ah = sc->sc_ah;
43c27613 503 struct ath_common *common = ath9k_hw_common(ah);
af03abec 504
3d832611 505 if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
766ec4a9 506 (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
43c27613
LR		 507 common->tx_chainmask = ah->caps.tx_chainmask;
508 common->rx_chainmask = ah->caps.rx_chainmask;
ff37e337 509 } else {
43c27613
LR		 510 common->tx_chainmask = 1;
511 common->rx_chainmask = 1;
ff37e337
S		 512 }
513
43c27613 514 ath_print(common, ATH_DBG_CONFIG,
c46917bb 515 "tx chmask: %d, rx chmask: %d\n",
43c27613
LR		 516 common->tx_chainmask,
517 common->rx_chainmask);
ff37e337
S		 518}
519
520static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
521{
522 struct ath_node *an;
523
524 an = (struct ath_node *)sta->drv_priv;
525
87792efc 526 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 527 ath_tx_node_init(sc, an);
9e98ac65 528 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S		 529 sta->ht_cap.ampdu_factor);
530 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
a59b5a5e 531 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
87792efc 532 }
ff37e337
S		 533}
534
535static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
536{
537 struct ath_node *an = (struct ath_node *)sta->drv_priv;
538
539 if (sc->sc_flags & SC_OP_TXAGGR)
540 ath_tx_node_cleanup(sc, an);
541}
542
543static void ath9k_tasklet(unsigned long data)
544{
545 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 546 struct ath_hw *ah = sc->sc_ah;
c46917bb 547 struct ath_common *common = ath9k_hw_common(ah);
af03abec 548
17d7904d 549 u32 status = sc->intrstatus;
ff37e337 550
153e080d
VT		 551 ath9k_ps_wakeup(sc);
552
ff37e337 553 if (status & ATH9K_INT_FATAL) {
ff37e337 554 ath_reset(sc, false);
153e080d 555 ath9k_ps_restore(sc);
ff37e337 556 return;
063d8be3 557 }
ff37e337 558
063d8be3
S		 559 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
560 spin_lock_bh(&sc->rx.rxflushlock);
561 ath_rx_tasklet(sc, 0);
562 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 563 }
564
063d8be3
S		 565 if (status & ATH9K_INT_TX)
566 ath_tx_tasklet(sc);
567
96148326 568 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
54ce846e
JM		 569 /*
570 * TSF sync does not look correct; remain awake to sync with
571 * the next Beacon.
572 */
c46917bb
LR		 573 ath_print(common, ATH_DBG_PS,
574 "TSFOOR - Sync with next Beacon\n");
ccdfeab6 575 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
54ce846e
JM		 576 }
577
766ec4a9 578 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
ebb8e1d7
VT		 579 if (status & ATH9K_INT_GENTIMER)
580 ath_gen_timer_isr(sc->sc_ah);
581
ff37e337 582 /* re-enable hardware interrupt */
af03abec 583 ath9k_hw_set_interrupts(ah, sc->imask);
153e080d 584 ath9k_ps_restore(sc);
ff37e337
S		 585}
586
6baff7f9 587irqreturn_t ath_isr(int irq, void *dev)
ff37e337 588{
063d8be3
S		 589#define SCHED_INTR ( \
590 ATH9K_INT_FATAL | \
591 ATH9K_INT_RXORN | \
592 ATH9K_INT_RXEOL | \
593 ATH9K_INT_RX | \
594 ATH9K_INT_TX | \
595 ATH9K_INT_BMISS | \
596 ATH9K_INT_CST | \
ebb8e1d7
VT		 597 ATH9K_INT_TSFOOR | \
598 ATH9K_INT_GENTIMER)
063d8be3 599
ff37e337 600 struct ath_softc *sc = dev;
cbe61d8a 601 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 602 enum ath9k_int status;
603 bool sched = false;
604
063d8be3
S		 605 /*
606 * The hardware is not ready/present, don't
607 * touch anything. Note this can happen early
608 * on if the IRQ is shared.
609 */
610 if (sc->sc_flags & SC_OP_INVALID)
611 return IRQ_NONE;
ff37e337 612
063d8be3
S		 613
614 /* shared irq, not for us */
615
153e080d 616 if (!ath9k_hw_intrpend(ah))
063d8be3 617 return IRQ_NONE;
063d8be3
S		 618
619 /*
620 * Figure out the reason(s) for the interrupt. Note
621 * that the hal returns a pseudo-ISR that may include
622 * bits we haven't explicitly enabled so we mask the
623 * value to insure we only process bits we requested.
624 */
625 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
626 status &= sc->imask; /* discard unasked-for bits */
ff37e337 627
063d8be3
S		 628 /*
629 * If there are no status bits set, then this interrupt was not
630 * for me (should have been caught above).
631 */
153e080d 632 if (!status)
063d8be3 633 return IRQ_NONE;
ff37e337 634
063d8be3
S		 635 /* Cache the status */
636 sc->intrstatus = status;
637
638 if (status & SCHED_INTR)
639 sched = true;
640
641 /*
642 * If a FATAL or RXORN interrupt is received, we have to reset the
643 * chip immediately.
644 */
645 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
646 goto chip_reset;
647
648 if (status & ATH9K_INT_SWBA)
649 tasklet_schedule(&sc->bcon_tasklet);
650
651 if (status & ATH9K_INT_TXURN)
652 ath9k_hw_updatetxtriglevel(ah, true);
653
654 if (status & ATH9K_INT_MIB) {
ff37e337 655 /*
063d8be3
S		 656 * Disable interrupts until we service the MIB
657 * interrupt; otherwise it will continue to
658 * fire.
ff37e337 659 */
063d8be3
S		 660 ath9k_hw_set_interrupts(ah, 0);
661 /*
662 * Let the hal handle the event. We assume
663 * it will clear whatever condition caused
664 * the interrupt.
665 */
22e66a4c 666 ath9k_hw_procmibevent(ah);
063d8be3
S		 667 ath9k_hw_set_interrupts(ah, sc->imask);
668 }
ff37e337 669
153e080d
VT		 670 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
671 if (status & ATH9K_INT_TIM_TIMER) {
063d8be3
S		 672 /* Clear RxAbort bit so that we can
673 * receive frames */
9ecdef4b 674 ath9k_setpower(sc, ATH9K_PM_AWAKE);
153e080d 675 ath9k_hw_setrxabort(sc->sc_ah, 0);
063d8be3 676 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337 677 }
063d8be3
S		 678
679chip_reset:
ff37e337 680
817e11de
S		 681 ath_debug_stat_interrupt(sc, status);
682
ff37e337
S		 683 if (sched) {
684 /* turn off every interrupt except SWBA */
17d7904d 685 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S		 686 tasklet_schedule(&sc->intr_tq);
687 }
688
689 return IRQ_HANDLED;
063d8be3
S		 690
691#undef SCHED_INTR
ff37e337
S		 692}
693
f078f209 694static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 695 struct ieee80211_channel *chan,
094d05dc 696 enum nl80211_channel_type channel_type)
f078f209
LR		 697{
698 u32 chanmode = 0;
f078f209
LR		 699
700 switch (chan->band) {
701 case IEEE80211_BAND_2GHZ:
094d05dc
S		 702 switch(channel_type) {
703 case NL80211_CHAN_NO_HT:
704 case NL80211_CHAN_HT20:
f078f209 705 chanmode = CHANNEL_G_HT20;
094d05dc
S		 706 break;
707 case NL80211_CHAN_HT40PLUS:
f078f209 708 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 709 break;
710 case NL80211_CHAN_HT40MINUS:
f078f209 711 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 712 break;
713 }
f078f209
LR		 714 break;
715 case IEEE80211_BAND_5GHZ:
094d05dc
S		 716 switch(channel_type) {
717 case NL80211_CHAN_NO_HT:
718 case NL80211_CHAN_HT20:
f078f209 719 chanmode = CHANNEL_A_HT20;
094d05dc
S		 720 break;
721 case NL80211_CHAN_HT40PLUS:
f078f209 722 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 723 break;
724 case NL80211_CHAN_HT40MINUS:
f078f209 725 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 726 break;
727 }
f078f209
LR		 728 break;
729 default:
730 break;
731 }
732
733 return chanmode;
734}
735
7e86c104 736static int ath_setkey_tkip(struct ath_common *common, u16 keyix, const u8 *key,
3f53dd64
JM		 737 struct ath9k_keyval *hk, const u8 *addr,
738 bool authenticator)
f078f209 739{
7e86c104 740 struct ath_hw *ah = common->ah;
6ace2891
JM		 741 const u8 *key_rxmic;
742 const u8 *key_txmic;
f078f209 743
6ace2891
JM		 744 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
745 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 746
747 if (addr == NULL) {
d216aaa6
JM		 748 /*
749 * Group key installation - only two key cache entries are used
750 * regardless of splitmic capability since group key is only
751 * used either for TX or RX.
752 */
3f53dd64
JM		 753 if (authenticator) {
754 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
755 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
756 } else {
757 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
758 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
759 }
7e86c104 760 return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
f078f209 761 }
7e86c104 762 if (!common->splitmic) {
d216aaa6 763 /* TX and RX keys share the same key cache entry. */
f078f209
LR		 764 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
765 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
7e86c104 766 return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
f078f209 767 }
d216aaa6
JM		 768
769 /* Separate key cache entries for TX and RX */
770
771 /* TX key goes at first index, RX key at +32. */
f078f209 772 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
7e86c104 773 if (!ath9k_hw_set_keycache_entry(ah, keyix, hk, NULL)) {
d216aaa6 774 /* TX MIC entry failed. No need to proceed further */
7e86c104 775 ath_print(common, ATH_DBG_FATAL,
c46917bb 776 "Setting TX MIC Key Failed\n");
f078f209
LR		 777 return 0;
778 }
779
780 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
781 /* XXX delete tx key on failure? */
7e86c104 782 return ath9k_hw_set_keycache_entry(ah, keyix + 32, hk, addr);
6ace2891
JM		 783}
784
7e86c104 785static int ath_reserve_key_cache_slot_tkip(struct ath_common *common)
6ace2891
JM		 786{
787 int i;
788
7e86c104
LR		 789 for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
790 if (test_bit(i, common->keymap) ||
791 test_bit(i + 64, common->keymap))
6ace2891 792 continue; /* At least one part of TKIP key allocated */
7e86c104
LR		 793 if (common->splitmic &&
794 (test_bit(i + 32, common->keymap) ||
795 test_bit(i + 64 + 32, common->keymap)))
6ace2891
JM		 796 continue; /* At least one part of TKIP key allocated */
797
798 /* Found a free slot for a TKIP key */
799 return i;
800 }
801 return -1;
802}
803
7e86c104 804static int ath_reserve_key_cache_slot(struct ath_common *common)
6ace2891
JM		 805{
806 int i;
807
808 /* First, try to find slots that would not be available for TKIP. */
7e86c104
LR		 809 if (common->splitmic) {
810 for (i = IEEE80211_WEP_NKID; i < common->keymax / 4; i++) {
811 if (!test_bit(i, common->keymap) &&
812 (test_bit(i + 32, common->keymap) ||
813 test_bit(i + 64, common->keymap) ||
814 test_bit(i + 64 + 32, common->keymap)))
6ace2891 815 return i;
7e86c104
LR		 816 if (!test_bit(i + 32, common->keymap) &&
817 (test_bit(i, common->keymap) ||
818 test_bit(i + 64, common->keymap) ||
819 test_bit(i + 64 + 32, common->keymap)))
6ace2891 820 return i + 32;
7e86c104
LR		 821 if (!test_bit(i + 64, common->keymap) &&
822 (test_bit(i , common->keymap) ||
823 test_bit(i + 32, common->keymap) ||
824 test_bit(i + 64 + 32, common->keymap)))
ea612132 825 return i + 64;
7e86c104
LR		 826 if (!test_bit(i + 64 + 32, common->keymap) &&
827 (test_bit(i, common->keymap) ||
828 test_bit(i + 32, common->keymap) ||
829 test_bit(i + 64, common->keymap)))
ea612132 830 return i + 64 + 32;
6ace2891
JM		 831 }
832 } else {
7e86c104
LR		 833 for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
834 if (!test_bit(i, common->keymap) &&
835 test_bit(i + 64, common->keymap))
6ace2891 836 return i;
7e86c104
LR		 837 if (test_bit(i, common->keymap) &&
838 !test_bit(i + 64, common->keymap))
6ace2891
JM		 839 return i + 64;
840 }
841 }
842
843 /* No partially used TKIP slots, pick any available slot */
7e86c104 844 for (i = IEEE80211_WEP_NKID; i < common->keymax; i++) {
be2864cf
JM		 845 /* Do not allow slots that could be needed for TKIP group keys
846 * to be used. This limitation could be removed if we know that
847 * TKIP will not be used. */
848 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
849 continue;
7e86c104 850 if (common->splitmic) {
be2864cf
JM		 851 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
852 continue;
853 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
854 continue;
855 }
856
7e86c104 857 if (!test_bit(i, common->keymap))
6ace2891
JM		 858 return i; /* Found a free slot for a key */
859 }
860
861 /* No free slot found */
862 return -1;
f078f209
LR		 863}
864
7e86c104 865static int ath_key_config(struct ath_common *common,
3f53dd64 866 struct ieee80211_vif *vif,
dc822b5d 867 struct ieee80211_sta *sta,
f078f209
LR		 868 struct ieee80211_key_conf *key)
869{
7e86c104 870 struct ath_hw *ah = common->ah;
f078f209
LR		 871 struct ath9k_keyval hk;
872 const u8 *mac = NULL;
873 int ret = 0;
6ace2891 874 int idx;
f078f209
LR		 875
876 memset(&hk, 0, sizeof(hk));
877
878 switch (key->alg) {
879 case ALG_WEP:
880 hk.kv_type = ATH9K_CIPHER_WEP;
881 break;
882 case ALG_TKIP:
883 hk.kv_type = ATH9K_CIPHER_TKIP;
884 break;
885 case ALG_CCMP:
886 hk.kv_type = ATH9K_CIPHER_AES_CCM;
887 break;
888 default:
ca470b29 889 return -EOPNOTSUPP;
f078f209
LR		 890 }
891
6ace2891 892 hk.kv_len = key->keylen;
f078f209
LR		 893 memcpy(hk.kv_val, key->key, key->keylen);
894
6ace2891
JM		 895 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
896 /* For now, use the default keys for broadcast keys. This may
897 * need to change with virtual interfaces. */
898 idx = key->keyidx;
899 } else if (key->keyidx) {
dc822b5d
JB		 900 if (WARN_ON(!sta))
901 return -EOPNOTSUPP;
902 mac = sta->addr;
903
6ace2891
JM		 904 if (vif->type != NL80211_IFTYPE_AP) {
905 /* Only keyidx 0 should be used with unicast key, but
906 * allow this for client mode for now. */
907 idx = key->keyidx;
908 } else
909 return -EIO;
f078f209 910 } else {
dc822b5d
JB		 911 if (WARN_ON(!sta))
912 return -EOPNOTSUPP;
913 mac = sta->addr;
914
6ace2891 915 if (key->alg == ALG_TKIP)
7e86c104 916 idx = ath_reserve_key_cache_slot_tkip(common);
6ace2891 917 else
7e86c104 918 idx = ath_reserve_key_cache_slot(common);
6ace2891 919 if (idx < 0)
ca470b29 920 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 921 }
922
923 if (key->alg == ALG_TKIP)
7e86c104 924 ret = ath_setkey_tkip(common, idx, key->key, &hk, mac,
3f53dd64 925 vif->type == NL80211_IFTYPE_AP);
f078f209 926 else
7e86c104 927 ret = ath9k_hw_set_keycache_entry(ah, idx, &hk, mac);
f078f209
LR		 928
929 if (!ret)
930 return -EIO;
931
7e86c104 932 set_bit(idx, common->keymap);
6ace2891 933 if (key->alg == ALG_TKIP) {
7e86c104
LR		 934 set_bit(idx + 64, common->keymap);
935 if (common->splitmic) {
936 set_bit(idx + 32, common->keymap);
937 set_bit(idx + 64 + 32, common->keymap);
6ace2891
JM		 938 }
939 }
940
941 return idx;
f078f209
LR		 942}
943
7e86c104 944static void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key)
f078f209 945{
7e86c104
LR		 946 struct ath_hw *ah = common->ah;
947
948 ath9k_hw_keyreset(ah, key->hw_key_idx);
6ace2891
JM		 949 if (key->hw_key_idx < IEEE80211_WEP_NKID)
950 return;
951
7e86c104 952 clear_bit(key->hw_key_idx, common->keymap);
6ace2891
JM		 953 if (key->alg != ALG_TKIP)
954 return;
f078f209 955
7e86c104
LR		 956 clear_bit(key->hw_key_idx + 64, common->keymap);
957 if (common->splitmic) {
958 clear_bit(key->hw_key_idx + 32, common->keymap);
959 clear_bit(key->hw_key_idx + 64 + 32, common->keymap);
6ace2891 960 }
f078f209
LR		 961}
962
eb2599ca
S		 963static void setup_ht_cap(struct ath_softc *sc,
964 struct ieee80211_sta_ht_cap *ht_info)
f078f209 965{
43c27613 966 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
140add21 967 u8 tx_streams, rx_streams;
f078f209 968
d9fe60de
JB		 969 ht_info->ht_supported = true;
970 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
971 IEEE80211_HT_CAP_SM_PS |
972 IEEE80211_HT_CAP_SGI_40 |
973 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 974
9e98ac65
S		 975 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
976 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
eb2599ca 977
d9fe60de
JB		 978 /* set up supported mcs set */
979 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
43c27613
LR		 980 tx_streams = !(common->tx_chainmask & (common->tx_chainmask - 1)) ?
981 1 : 2;
982 rx_streams = !(common->rx_chainmask & (common->rx_chainmask - 1)) ?
983 1 : 2;
140add21
SB		 984
985 if (tx_streams != rx_streams) {
43c27613 986 ath_print(common, ATH_DBG_CONFIG,
c46917bb
LR		 987 "TX streams %d, RX streams: %d\n",
988 tx_streams, rx_streams);
140add21
SB		 989 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
990 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
991 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
992 }
eb2599ca 993
140add21
SB		 994 ht_info->mcs.rx_mask[0] = 0xff;
995 if (rx_streams >= 2)
eb2599ca 996 ht_info->mcs.rx_mask[1] = 0xff;
eb2599ca 997
140add21 998 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 999}
1000
8feceb67 1001static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 1002 struct ieee80211_vif *vif,
8feceb67 1003 struct ieee80211_bss_conf *bss_conf)
f078f209 1004{
f2b2143e 1005 struct ath_hw *ah = sc->sc_ah;
1510718d 1006 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1007
8feceb67 1008 if (bss_conf->assoc) {
c46917bb
LR		 1009 ath_print(common, ATH_DBG_CONFIG,
1010 "Bss Info ASSOC %d, bssid: %pM\n",
1011 bss_conf->aid, common->curbssid);
f078f209 1012
8feceb67 1013 /* New association, store aid */
1510718d 1014 common->curaid = bss_conf->aid;
f2b2143e 1015 ath9k_hw_write_associd(ah);
2664f201
SB		 1016
1017 /*
1018 * Request a re-configuration of Beacon related timers
1019 * on the receipt of the first Beacon frame (i.e.,
1020 * after time sync with the AP).
1021 */
1022 sc->sc_flags |= SC_OP_BEACON_SYNC;
f078f209 1023
8feceb67 1024 /* Configure the beacon */
2c3db3d5 1025 ath_beacon_config(sc, vif);
f078f209 1026
8feceb67 1027 /* Reset rssi stats */
22e66a4c 1028 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
f078f209 1029
3d536acf 1030 ath_start_ani(common);
8feceb67 1031 } else {
c46917bb 1032 ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
1510718d 1033 common->curaid = 0;
f38faa31 1034 /* Stop ANI */
3d536acf 1035 del_timer_sync(&common->ani.timer);
f078f209 1036 }
8feceb67 1037}
f078f209 1038
8feceb67
VT		 1039/********************************/
1040/* LED functions */
1041/********************************/
f078f209 1042
f2bffa7e
VT		 1043static void ath_led_blink_work(struct work_struct *work)
1044{
1045 struct ath_softc *sc = container_of(work, struct ath_softc,
1046 ath_led_blink_work.work);
1047
1048 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
1049 return;
85067c06
VT		 1050
1051 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
1052 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
08fc5c1b 1053 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
85067c06 1054 else
08fc5c1b 1055 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
85067c06 1056 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
f2bffa7e 1057
42935eca
LR		 1058 ieee80211_queue_delayed_work(sc->hw,
1059 &sc->ath_led_blink_work,
1060 (sc->sc_flags & SC_OP_LED_ON) ?
1061 msecs_to_jiffies(sc->led_off_duration) :
1062 msecs_to_jiffies(sc->led_on_duration));
f2bffa7e 1063
85067c06
VT		 1064 sc->led_on_duration = sc->led_on_cnt ?
1065 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
1066 ATH_LED_ON_DURATION_IDLE;
1067 sc->led_off_duration = sc->led_off_cnt ?
1068 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
1069 ATH_LED_OFF_DURATION_IDLE;
f2bffa7e
VT		 1070 sc->led_on_cnt = sc->led_off_cnt = 0;
1071 if (sc->sc_flags & SC_OP_LED_ON)
1072 sc->sc_flags &= ~SC_OP_LED_ON;
1073 else
1074 sc->sc_flags |= SC_OP_LED_ON;
1075}
1076
8feceb67
VT		 1077static void ath_led_brightness(struct led_classdev *led_cdev,
1078 enum led_brightness brightness)
1079{
1080 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1081 struct ath_softc *sc = led->sc;
f078f209 1082
8feceb67
VT		 1083 switch (brightness) {
1084 case LED_OFF:
1085 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e 1086 led->led_type == ATH_LED_RADIO) {
08fc5c1b 1087 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
f2bffa7e 1088 (led->led_type == ATH_LED_RADIO));
8feceb67 1089 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 1090 if (led->led_type == ATH_LED_RADIO)
1091 sc->sc_flags &= ~SC_OP_LED_ON;
1092 } else {
1093 sc->led_off_cnt++;
1094 }
8feceb67
VT		 1095 break;
1096 case LED_FULL:
f2bffa7e 1097 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 1098 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
42935eca
LR		 1099 ieee80211_queue_delayed_work(sc->hw,
1100 &sc->ath_led_blink_work, 0);
f2bffa7e 1101 } else if (led->led_type == ATH_LED_RADIO) {
08fc5c1b 1102 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
f2bffa7e
VT		 1103 sc->sc_flags |= SC_OP_LED_ON;
1104 } else {
1105 sc->led_on_cnt++;
1106 }
8feceb67
VT		 1107 break;
1108 default:
1109 break;
f078f209 1110 }
8feceb67 1111}
f078f209 1112
8feceb67
VT		 1113static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1114 char *trigger)
1115{
1116 int ret;
f078f209 1117
8feceb67
VT		 1118 led->sc = sc;
1119 led->led_cdev.name = led->name;
1120 led->led_cdev.default_trigger = trigger;
1121 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 1122
8feceb67
VT		 1123 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1124 if (ret)
c46917bb
LR		 1125 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1126 "Failed to register led:%s", led->name);
8feceb67
VT		 1127 else
1128 led->registered = 1;
1129 return ret;
1130}
f078f209 1131
8feceb67
VT		 1132static void ath_unregister_led(struct ath_led *led)
1133{
1134 if (led->registered) {
1135 led_classdev_unregister(&led->led_cdev);
1136 led->registered = 0;
f078f209 1137 }
f078f209
LR		 1138}
1139
8feceb67 1140static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1141{
8feceb67
VT		 1142 ath_unregister_led(&sc->assoc_led);
1143 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1144 ath_unregister_led(&sc->tx_led);
1145 ath_unregister_led(&sc->rx_led);
1146 ath_unregister_led(&sc->radio_led);
08fc5c1b 1147 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
8feceb67 1148}
f078f209 1149
8feceb67
VT		 1150static void ath_init_leds(struct ath_softc *sc)
1151{
1152 char *trigger;
1153 int ret;
f078f209 1154
08fc5c1b
VN		 1155 if (AR_SREV_9287(sc->sc_ah))
1156 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
1157 else
1158 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
1159
8feceb67 1160 /* Configure gpio 1 for output */
08fc5c1b 1161 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
8feceb67
VT		 1162 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1163 /* LED off, active low */
08fc5c1b 1164 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
7dcfdcd9 1165
f2bffa7e
VT		 1166 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1167
8feceb67
VT		 1168 trigger = ieee80211_get_radio_led_name(sc->hw);
1169 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
0818cb8a 1170 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1171 ret = ath_register_led(sc, &sc->radio_led, trigger);
1172 sc->radio_led.led_type = ATH_LED_RADIO;
1173 if (ret)
1174 goto fail;
7dcfdcd9 1175
8feceb67
VT		 1176 trigger = ieee80211_get_assoc_led_name(sc->hw);
1177 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
0818cb8a 1178 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1179 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1180 sc->assoc_led.led_type = ATH_LED_ASSOC;
1181 if (ret)
1182 goto fail;
f078f209 1183
8feceb67
VT		 1184 trigger = ieee80211_get_tx_led_name(sc->hw);
1185 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
0818cb8a 1186 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1187 ret = ath_register_led(sc, &sc->tx_led, trigger);
1188 sc->tx_led.led_type = ATH_LED_TX;
1189 if (ret)
1190 goto fail;
f078f209 1191
8feceb67
VT		 1192 trigger = ieee80211_get_rx_led_name(sc->hw);
1193 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
0818cb8a 1194 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1195 ret = ath_register_led(sc, &sc->rx_led, trigger);
1196 sc->rx_led.led_type = ATH_LED_RX;
1197 if (ret)
1198 goto fail;
f078f209 1199
8feceb67
VT		 1200 return;
1201
1202fail:
35c95ab9 1203 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67 1204 ath_deinit_leds(sc);
f078f209
LR		 1205}
1206
68a89116 1207void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 1208{
cbe61d8a 1209 struct ath_hw *ah = sc->sc_ah;
c46917bb 1210 struct ath_common *common = ath9k_hw_common(ah);
68a89116 1211 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 1212 int r;
500c064d 1213
3cbb5dd7 1214 ath9k_ps_wakeup(sc);
93b1b37f 1215 ath9k_hw_configpcipowersave(ah, 0, 0);
ae8d2858 1216
159cd468
VT		 1217 if (!ah->curchan)
1218 ah->curchan = ath_get_curchannel(sc, sc->hw);
1219
d2f5b3a6 1220 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1221 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1222 if (r) {
c46917bb
LR		 1223 ath_print(common, ATH_DBG_FATAL,
1224 "Unable to reset channel %u (%uMhz) ",
1225 "reset status %d\n",
1226 channel->center_freq, r);
500c064d
VT		 1227 }
1228 spin_unlock_bh(&sc->sc_resetlock);
1229
1230 ath_update_txpow(sc);
1231 if (ath_startrecv(sc) != 0) {
c46917bb
LR		 1232 ath_print(common, ATH_DBG_FATAL,
1233 "Unable to restart recv logic\n");
500c064d
VT		 1234 return;
1235 }
1236
1237 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1238 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT		 1239
1240 /* Re-Enable interrupts */
17d7904d 1241 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT		 1242
1243 /* Enable LED */
08fc5c1b 1244 ath9k_hw_cfg_output(ah, ah->led_pin,
500c064d 1245 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b 1246 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
500c064d 1247
68a89116 1248 ieee80211_wake_queues(hw);
3cbb5dd7 1249 ath9k_ps_restore(sc);
500c064d
VT		 1250}
1251
68a89116 1252void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 1253{
cbe61d8a 1254 struct ath_hw *ah = sc->sc_ah;
68a89116 1255 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 1256 int r;
500c064d 1257
3cbb5dd7 1258 ath9k_ps_wakeup(sc);
68a89116 1259 ieee80211_stop_queues(hw);
500c064d
VT		 1260
1261 /* Disable LED */
08fc5c1b
VN		 1262 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1263 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
500c064d
VT		 1264
1265 /* Disable interrupts */
1266 ath9k_hw_set_interrupts(ah, 0);
1267
043a0405 1268 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1269 ath_stoprecv(sc); /* turn off frame recv */
1270 ath_flushrecv(sc); /* flush recv queue */
1271
159cd468 1272 if (!ah->curchan)
68a89116 1273 ah->curchan = ath_get_curchannel(sc, hw);
159cd468 1274
500c064d 1275 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1276 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1277 if (r) {
c46917bb
LR		 1278 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1279 "Unable to reset channel %u (%uMhz) "
1280 "reset status %d\n",
1281 channel->center_freq, r);
500c064d
VT		 1282 }
1283 spin_unlock_bh(&sc->sc_resetlock);
1284
1285 ath9k_hw_phy_disable(ah);
93b1b37f 1286 ath9k_hw_configpcipowersave(ah, 1, 1);
3cbb5dd7 1287 ath9k_ps_restore(sc);
9ecdef4b 1288 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
500c064d
VT		 1289}
1290
5077fd35
GJ		 1291/*******************/
1292/* Rfkill */
1293/*******************/
1294
500c064d
VT		 1295static bool ath_is_rfkill_set(struct ath_softc *sc)
1296{
cbe61d8a 1297 struct ath_hw *ah = sc->sc_ah;
500c064d 1298
2660b81a
S		 1299 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1300 ah->rfkill_polarity;
500c064d
VT		 1301}
1302
3b319aae 1303static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
500c064d 1304{
3b319aae
JB		 1305 struct ath_wiphy *aphy = hw->priv;
1306 struct ath_softc *sc = aphy->sc;
19d337df 1307 bool blocked = !!ath_is_rfkill_set(sc);
500c064d 1308
3b319aae 1309 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
500c064d
VT		 1310}
1311
3b319aae 1312static void ath_start_rfkill_poll(struct ath_softc *sc)
500c064d 1313{
3b319aae 1314 struct ath_hw *ah = sc->sc_ah;
9c84b797 1315
3b319aae
JB		 1316 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1317 wiphy_rfkill_start_polling(sc->hw->wiphy);
9c84b797 1318}
500c064d 1319
7fda1666
LR		 1320static void ath9k_uninit_hw(struct ath_softc *sc)
1321{
1322 struct ath_hw *ah = sc->sc_ah;
1323
1324 BUG_ON(!ah);
1325
1326 ath9k_exit_debug(ah);
1327 ath9k_hw_detach(ah);
1328 sc->sc_ah = NULL;
1329}
1330
2568835c 1331static void ath_clean_core(struct ath_softc *sc)
f078f209 1332{
8feceb67 1333 struct ieee80211_hw *hw = sc->hw;
4d6b228d 1334 struct ath_hw *ah = sc->sc_ah;
9c84b797 1335 int i = 0;
f078f209 1336
3cbb5dd7
VN		 1337 ath9k_ps_wakeup(sc);
1338
4d6b228d 1339 dev_dbg(sc->dev, "Detach ATH hw\n");
f078f209 1340
35c95ab9 1341 ath_deinit_leds(sc);
e31f7b96 1342 wiphy_rfkill_stop_polling(sc->hw->wiphy);
35c95ab9 1343
c52f33d0
JM		 1344 for (i = 0; i < sc->num_sec_wiphy; i++) {
1345 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1346 if (aphy == NULL)
1347 continue;
1348 sc->sec_wiphy[i] = NULL;
1349 ieee80211_unregister_hw(aphy->hw);
1350 ieee80211_free_hw(aphy->hw);
1351 }
3fcdfb4b 1352 ieee80211_unregister_hw(hw);
8feceb67
VT		 1353 ath_rx_cleanup(sc);
1354 ath_tx_cleanup(sc);
f078f209 1355
9c84b797
S		 1356 tasklet_kill(&sc->intr_tq);
1357 tasklet_kill(&sc->bcon_tasklet);
f078f209 1358
9c84b797 1359 if (!(sc->sc_flags & SC_OP_INVALID))
9ecdef4b 1360 ath9k_setpower(sc, ATH9K_PM_AWAKE);
8feceb67 1361
9c84b797
S		 1362 /* cleanup tx queues */
1363 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1364 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1365 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797 1366
75d7839f 1367 if ((sc->btcoex.no_stomp_timer) &&
766ec4a9 1368 ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1369 ath_gen_timer_free(ah, sc->btcoex.no_stomp_timer);
2568835c 1370}
1773912b 1371
2568835c
LR		 1372void ath_detach(struct ath_softc *sc)
1373{
1374 ath_clean_core(sc);
7fda1666 1375 ath9k_uninit_hw(sc);
f078f209
LR		 1376}
1377
bd96d390
LR		 1378void ath_cleanup(struct ath_softc *sc)
1379{
1380 struct ath_hw *ah = sc->sc_ah;
1381 struct ath_common *common = ath9k_hw_common(ah);
1382
1383 ath_clean_core(sc);
1384 free_irq(sc->irq, sc);
1385 ath_bus_cleanup(common);
1386 kfree(sc->sec_wiphy);
1387 ieee80211_free_hw(sc->hw);
1388
1389 ath9k_uninit_hw(sc);
1390}
1391
e3bb249b
BC		 1392static int ath9k_reg_notifier(struct wiphy *wiphy,
1393 struct regulatory_request *request)
1394{
1395 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1396 struct ath_wiphy *aphy = hw->priv;
1397 struct ath_softc *sc = aphy->sc;
27c51f1a 1398 struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
e3bb249b
BC		 1399
1400 return ath_reg_notifier_apply(wiphy, request, reg);
1401}
1402
75d7839f
LR		 1403/*
1404 * Detects if there is any priority bt traffic
1405 */
1406static void ath_detect_bt_priority(struct ath_softc *sc)
1407{
1408 struct ath_btcoex *btcoex = &sc->btcoex;
1409 struct ath_hw *ah = sc->sc_ah;
1410
766ec4a9 1411 if (ath9k_hw_gpio_get(sc->sc_ah, ah->btcoex_hw.btpriority_gpio))
75d7839f
LR		 1412 btcoex->bt_priority_cnt++;
1413
1414 if (time_after(jiffies, btcoex->bt_priority_time +
1415 msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
1416 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
c46917bb
LR		 1417 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
1418 "BT priority traffic detected");
75d7839f
LR		 1419 sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
1420 } else {
1421 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
1422 }
1423
1424 btcoex->bt_priority_cnt = 0;
1425 btcoex->bt_priority_time = jiffies;
1426 }
1427}
1428
75d7839f
LR		 1429/*
1430 * Configures appropriate weight based on stomp type.
1431 */
269ad812
LR		 1432static void ath9k_btcoex_bt_stomp(struct ath_softc *sc,
1433 enum ath_stomp_type stomp_type)
75d7839f 1434{
269ad812 1435 struct ath_hw *ah = sc->sc_ah;
75d7839f
LR		 1436
1437 switch (stomp_type) {
1438 case ATH_BTCOEX_STOMP_ALL:
269ad812
LR		 1439 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1440 AR_STOMP_ALL_WLAN_WGHT);
75d7839f
LR		 1441 break;
1442 case ATH_BTCOEX_STOMP_LOW:
269ad812
LR		 1443 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1444 AR_STOMP_LOW_WLAN_WGHT);
75d7839f
LR		 1445 break;
1446 case ATH_BTCOEX_STOMP_NONE:
269ad812
LR		 1447 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1448 AR_STOMP_NONE_WLAN_WGHT);
75d7839f
LR		 1449 break;
1450 default:
c46917bb
LR		 1451 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1452 "Invalid Stomptype\n");
75d7839f
LR		 1453 break;
1454 }
1455
269ad812 1456 ath9k_hw_btcoex_enable(ah);
75d7839f
LR		 1457}
1458
cd9bf689
LR		 1459static void ath9k_gen_timer_start(struct ath_hw *ah,
1460 struct ath_gen_timer *timer,
1461 u32 timer_next,
1462 u32 timer_period)
1463{
bc974f4a
LR		 1464 struct ath_common *common = ath9k_hw_common(ah);
1465 struct ath_softc *sc = (struct ath_softc *) common->priv;
1466
cd9bf689
LR		 1467 ath9k_hw_gen_timer_start(ah, timer, timer_next, timer_period);
1468
bc974f4a 1469 if ((sc->imask & ATH9K_INT_GENTIMER) == 0) {
cd9bf689 1470 ath9k_hw_set_interrupts(ah, 0);
bc974f4a
LR		 1471 sc->imask |= ATH9K_INT_GENTIMER;
1472 ath9k_hw_set_interrupts(ah, sc->imask);
cd9bf689
LR		 1473 }
1474}
1475
1476static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
1477{
bc974f4a
LR		 1478 struct ath_common *common = ath9k_hw_common(ah);
1479 struct ath_softc *sc = (struct ath_softc *) common->priv;
cd9bf689
LR		 1480 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
1481
1482 ath9k_hw_gen_timer_stop(ah, timer);
1483
1484 /* if no timer is enabled, turn off interrupt mask */
1485 if (timer_table->timer_mask.val == 0) {
1486 ath9k_hw_set_interrupts(ah, 0);
bc974f4a
LR		 1487 sc->imask &= ~ATH9K_INT_GENTIMER;
1488 ath9k_hw_set_interrupts(ah, sc->imask);
cd9bf689
LR		 1489 }
1490}
1491
75d7839f
LR		 1492/*
1493 * This is the master bt coex timer which runs for every
1494 * 45ms, bt traffic will be given priority during 55% of this
1495 * period while wlan gets remaining 45%
1496 */
1497static void ath_btcoex_period_timer(unsigned long data)
1498{
1499 struct ath_softc *sc = (struct ath_softc *) data;
1500 struct ath_hw *ah = sc->sc_ah;
1501 struct ath_btcoex *btcoex = &sc->btcoex;
75d7839f
LR		 1502
1503 ath_detect_bt_priority(sc);
1504
1505 spin_lock_bh(&btcoex->btcoex_lock);
1506
269ad812 1507 ath9k_btcoex_bt_stomp(sc, btcoex->bt_stomp_type);
75d7839f
LR		 1508
1509 spin_unlock_bh(&btcoex->btcoex_lock);
1510
1511 if (btcoex->btcoex_period != btcoex->btcoex_no_stomp) {
1512 if (btcoex->hw_timer_enabled)
cd9bf689 1513 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
75d7839f 1514
cd9bf689
LR		 1515 ath9k_gen_timer_start(ah,
1516 btcoex->no_stomp_timer,
1517 (ath9k_hw_gettsf32(ah) +
1518 btcoex->btcoex_no_stomp),
1519 btcoex->btcoex_no_stomp * 10);
75d7839f
LR		 1520 btcoex->hw_timer_enabled = true;
1521 }
1522
1523 mod_timer(&btcoex->period_timer, jiffies +
1524 msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD));
1525}
1526
1527/*
1528 * Generic tsf based hw timer which configures weight
1529 * registers to time slice between wlan and bt traffic
1530 */
1531static void ath_btcoex_no_stomp_timer(void *arg)
1532{
1533 struct ath_softc *sc = (struct ath_softc *)arg;
1534 struct ath_hw *ah = sc->sc_ah;
1535 struct ath_btcoex *btcoex = &sc->btcoex;
75d7839f 1536
c46917bb
LR		 1537 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1538 "no stomp timer running \n");
75d7839f
LR		 1539
1540 spin_lock_bh(&btcoex->btcoex_lock);
1541
e08a6ace 1542 if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW)
269ad812 1543 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_NONE);
e08a6ace 1544 else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
269ad812 1545 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_LOW);
75d7839f
LR		 1546
1547 spin_unlock_bh(&btcoex->btcoex_lock);
1548}
1549
1550static int ath_init_btcoex_timer(struct ath_softc *sc)
1551{
1552 struct ath_btcoex *btcoex = &sc->btcoex;
1553
1554 btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD * 1000;
1555 btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
1556 btcoex->btcoex_period / 100;
1557
1558 setup_timer(&btcoex->period_timer, ath_btcoex_period_timer,
1559 (unsigned long) sc);
1560
1561 spin_lock_init(&btcoex->btcoex_lock);
1562
1563 btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah,
1564 ath_btcoex_no_stomp_timer,
1565 ath_btcoex_no_stomp_timer,
1566 (void *) sc, AR_FIRST_NDP_TIMER);
1567
1568 if (!btcoex->no_stomp_timer)
1569 return -ENOMEM;
1570
1571 return 0;
1572}
1573
9e4bffd2
LR		 1574/*
1575 * Read and write, they both share the same lock. We do this to serialize
1576 * reads and writes on Atheros 802.11n PCI devices only. This is required
1577 * as the FIFO on these devices can only accept sanely 2 requests. After
1578 * that the device goes bananas. Serializing the reads/writes prevents this
1579 * from happening.
1580 */
1581
1582static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
1583{
1584 struct ath_hw *ah = (struct ath_hw *) hw_priv;
bc974f4a
LR		 1585 struct ath_common *common = ath9k_hw_common(ah);
1586 struct ath_softc *sc = (struct ath_softc *) common->priv;
9e4bffd2
LR		 1587
1588 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1589 unsigned long flags;
bc974f4a
LR		 1590 spin_lock_irqsave(&sc->sc_serial_rw, flags);
1591 iowrite32(val, sc->mem + reg_offset);
1592 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
9e4bffd2 1593 } else
bc974f4a 1594 iowrite32(val, sc->mem + reg_offset);
9e4bffd2
LR		 1595}
1596
1597static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
1598{
1599 struct ath_hw *ah = (struct ath_hw *) hw_priv;
bc974f4a
LR		 1600 struct ath_common *common = ath9k_hw_common(ah);
1601 struct ath_softc *sc = (struct ath_softc *) common->priv;
9e4bffd2
LR		 1602 u32 val;
1603
1604 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1605 unsigned long flags;
bc974f4a
LR		 1606 spin_lock_irqsave(&sc->sc_serial_rw, flags);
1607 val = ioread32(sc->mem + reg_offset);
1608 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
9e4bffd2 1609 } else
bc974f4a 1610 val = ioread32(sc->mem + reg_offset);
9e4bffd2
LR		 1611 return val;
1612}
1613
2ddb5c8b 1614static const struct ath_ops ath9k_common_ops = {
9e4bffd2
LR		 1615 .read = ath9k_ioread32,
1616 .write = ath9k_iowrite32,
1617};
1618
1e40bcfa
LR		 1619/*
1620 * Initialize and fill ath_softc, ath_sofct is the
1621 * "Software Carrier" struct. Historically it has existed
1622 * to allow the separation between hardware specific
1623 * variables (now in ath_hw) and driver specific variables.
1624 */
5bb12791
LR		 1625static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
1626 const struct ath_bus_ops *bus_ops)
ff37e337 1627{
cbe61d8a 1628 struct ath_hw *ah = NULL;
1510718d 1629 struct ath_common *common;
4f3acf81 1630 int r = 0, i;
ff37e337 1631 int csz = 0;
75d7839f 1632 int qnum;
ff37e337
S		 1633
1634 /* XXX: hardware will not be ready until ath_open() being called */
1635 sc->sc_flags |= SC_OP_INVALID;
88b126af 1636
c52f33d0 1637 spin_lock_init(&sc->wiphy_lock);
ff37e337 1638 spin_lock_init(&sc->sc_resetlock);
6158425b 1639 spin_lock_init(&sc->sc_serial_rw);
e5f0921a 1640 spin_lock_init(&sc->ani_lock);
04717ccd 1641 spin_lock_init(&sc->sc_pm_lock);
aa33de09 1642 mutex_init(&sc->mutex);
ff37e337 1643 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
9fc9ab0a 1644 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
ff37e337
S		 1645 (unsigned long)sc);
1646
4f3acf81 1647 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
211f5859
LR		 1648 if (!ah)
1649 return -ENOMEM;
4f3acf81 1650
8df5d1b7 1651 ah->hw_version.devid = devid;
aeac355d 1652 ah->hw_version.subsysid = subsysid;
e1e2f93f 1653 sc->sc_ah = ah;
4f3acf81 1654
27c51f1a 1655 common = ath9k_hw_common(ah);
9e4bffd2 1656 common->ops = &ath9k_common_ops;
5bb12791 1657 common->bus_ops = bus_ops;
13b81559 1658 common->ah = ah;
b002a4a9 1659 common->hw = sc->hw;
bc974f4a 1660 common->priv = sc;
faa27fae 1661 common->debug_mask = ath9k_debug;
27c51f1a
LR		 1662
1663 /*
1664 * Cache line size is used to size and align various
1665 * structures used to communicate with the hardware.
1666 */
5bb12791 1667 ath_read_cachesize(common, &csz);
27c51f1a
LR		 1668 /* XXX assert csz is non-zero */
1669 common->cachelsz = csz << 2; /* convert to bytes */
1670
f637cfd6 1671 r = ath9k_hw_init(ah);
4f3acf81 1672 if (r) {
c46917bb
LR		 1673 ath_print(common, ATH_DBG_FATAL,
1674 "Unable to initialize hardware; "
1675 "initialization status: %d\n", r);
211f5859
LR		 1676 goto bad_free_hw;
1677 }
1678
1679 if (ath9k_init_debug(ah) < 0) {
1680 ath_print(common, ATH_DBG_FATAL,
1681 "Unable to create debugfs files\n");
1682 goto bad_free_hw;
ff37e337 1683 }
ff37e337
S		 1684
1685 /* Get the hardware key cache size. */
7e86c104
LR		 1686 common->keymax = ah->caps.keycache_size;
1687 if (common->keymax > ATH_KEYMAX) {
c46917bb
LR		 1688 ath_print(common, ATH_DBG_ANY,
1689 "Warning, using only %u entries in %u key cache\n",
7e86c104
LR		 1690 ATH_KEYMAX, common->keymax);
1691 common->keymax = ATH_KEYMAX;
ff37e337
S		 1692 }
1693
1694 /*
1695 * Reset the key cache since some parts do not
1696 * reset the contents on initial power up.
1697 */
7e86c104 1698 for (i = 0; i < common->keymax; i++)
ff37e337 1699 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1700
ff37e337 1701 /* default to MONITOR mode */
2660b81a 1702 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
d97809db 1703
ff37e337
S		 1704 /* Setup rate tables */
1705
1706 ath_rate_attach(sc);
1707 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1708 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1709
1710 /*
1711 * Allocate hardware transmit queues: one queue for
1712 * beacon frames and one data queue for each QoS
1713 * priority. Note that the hal handles reseting
1714 * these queues at the needed time.
1715 */
536b3a7a 1716 sc->beacon.beaconq = ath9k_hw_beaconq_setup(ah);
b77f483f 1717 if (sc->beacon.beaconq == -1) {
c46917bb
LR		 1718 ath_print(common, ATH_DBG_FATAL,
1719 "Unable to setup a beacon xmit queue\n");
4f3acf81 1720 r = -EIO;
ff37e337
S		 1721 goto bad2;
1722 }
b77f483f
S		 1723 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1724 if (sc->beacon.cabq == NULL) {
c46917bb
LR		 1725 ath_print(common, ATH_DBG_FATAL,
1726 "Unable to setup CAB xmit queue\n");
4f3acf81 1727 r = -EIO;
ff37e337
S		 1728 goto bad2;
1729 }
1730
17d7904d 1731 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
ff37e337
S		 1732 ath_cabq_update(sc);
1733
b77f483f
S		 1734 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1735 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1736
1737 /* Setup data queues */
1738 /* NB: ensure BK queue is the lowest priority h/w queue */
1739 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
c46917bb
LR		 1740 ath_print(common, ATH_DBG_FATAL,
1741 "Unable to setup xmit queue for BK traffic\n");
4f3acf81 1742 r = -EIO;
ff37e337
S		 1743 goto bad2;
1744 }
1745
1746 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
c46917bb
LR		 1747 ath_print(common, ATH_DBG_FATAL,
1748 "Unable to setup xmit queue for BE traffic\n");
4f3acf81 1749 r = -EIO;
ff37e337
S		 1750 goto bad2;
1751 }
1752 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
c46917bb
LR		 1753 ath_print(common, ATH_DBG_FATAL,
1754 "Unable to setup xmit queue for VI traffic\n");
4f3acf81 1755 r = -EIO;
ff37e337
S		 1756 goto bad2;
1757 }
1758 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
c46917bb
LR		 1759 ath_print(common, ATH_DBG_FATAL,
1760 "Unable to setup xmit queue for VO traffic\n");
4f3acf81 1761 r = -EIO;
ff37e337
S		 1762 goto bad2;
1763 }
1764
1765 /* Initializes the noise floor to a reasonable default value.
1766 * Later on this will be updated during ANI processing. */
1767
3d536acf
LR		 1768 common->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1769 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
ff37e337
S		 1770
1771 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1772 ATH9K_CIPHER_TKIP, NULL)) {
1773 /*
1774 * Whether we should enable h/w TKIP MIC.
1775 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1776 * report WMM capable, so it's always safe to turn on
1777 * TKIP MIC in this case.
1778 */
1779 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1780 0, 1, NULL);
1781 }
1782
1783 /*
1784 * Check whether the separate key cache entries
1785 * are required to handle both tx+rx MIC keys.
1786 * With split mic keys the number of stations is limited
1787 * to 27 otherwise 59.
1788 */
1789 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1790 ATH9K_CIPHER_TKIP, NULL)
1791 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1792 ATH9K_CIPHER_MIC, NULL)
1793 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1794 0, NULL))
7e86c104 1795 common->splitmic = 1;
ff37e337
S		 1796
1797 /* turn on mcast key search if possible */
1798 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1799 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1800 1, NULL);
1801
17d7904d 1802 sc->config.txpowlimit = ATH_TXPOWER_MAX;
ff37e337
S		 1803
1804 /* 11n Capabilities */
2660b81a 1805 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337
S		 1806 sc->sc_flags |= SC_OP_TXAGGR;
1807 sc->sc_flags |= SC_OP_RXAGGR;
1808 }
1809
43c27613
LR		 1810 common->tx_chainmask = ah->caps.tx_chainmask;
1811 common->rx_chainmask = ah->caps.rx_chainmask;
ff37e337
S		 1812
1813 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1814 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337 1815
8ca21f01 1816 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1510718d 1817 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
ff37e337 1818
b77f483f 1819 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1820
1821 /* initialize beacon slots */
c52f33d0 1822 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2c3db3d5 1823 sc->beacon.bslot[i] = NULL;
c52f33d0
JM		 1824 sc->beacon.bslot_aphy[i] = NULL;
1825 }
ff37e337 1826
ff37e337
S		 1827 /* setup channels and rates */
1828
5f8e077c 1829 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1830 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1831 sc->rates[IEEE80211_BAND_2GHZ];
1832 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1833 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1834 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337 1835
2660b81a 1836 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
5f8e077c 1837 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1838 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1839 sc->rates[IEEE80211_BAND_5GHZ];
1840 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1841 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1842 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1843 }
1844
766ec4a9 1845 switch (ah->btcoex_hw.scheme) {
75d7839f
LR		 1846 case ATH_BTCOEX_CFG_NONE:
1847 break;
1848 case ATH_BTCOEX_CFG_2WIRE:
1849 ath9k_hw_btcoex_init_2wire(ah);
1850 break;
1851 case ATH_BTCOEX_CFG_3WIRE:
1852 ath9k_hw_btcoex_init_3wire(ah);
1853 r = ath_init_btcoex_timer(sc);
1773912b
VT		 1854 if (r)
1855 goto bad2;
75d7839f 1856 qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
766ec4a9 1857 ath9k_hw_init_btcoex_hw(ah, qnum);
e08a6ace 1858 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
75d7839f
LR		 1859 break;
1860 default:
1861 WARN_ON(1);
1862 break;
1773912b 1863 }
c97c92d9 1864
ff37e337
S		 1865 return 0;
1866bad2:
1867 /* cleanup tx queues */
1868 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1869 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1870 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
211f5859 1871
211f5859 1872bad_free_hw:
7fda1666 1873 ath9k_uninit_hw(sc);
4f3acf81 1874 return r;
ff37e337
S		 1875}
1876
c52f33d0 1877void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
f078f209 1878{
9c84b797
S		 1879 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1880 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1881 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1882 IEEE80211_HW_AMPDU_AGGREGATION |
1883 IEEE80211_HW_SUPPORTS_PS |
eeee1320
S		 1884 IEEE80211_HW_PS_NULLFUNC_STACK |
1885 IEEE80211_HW_SPECTRUM_MGMT;
f078f209 1886
b3bd89ce 1887 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
0ced0e17
JM		 1888 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1889
9c84b797
S		 1890 hw->wiphy->interface_modes =
1891 BIT(NL80211_IFTYPE_AP) |
1892 BIT(NL80211_IFTYPE_STATION) |
9cb5412b
PE		 1893 BIT(NL80211_IFTYPE_ADHOC) |
1894 BIT(NL80211_IFTYPE_MESH_POINT);
f078f209 1895
8feceb67 1896 hw->queues = 4;
e63835b0 1897 hw->max_rates = 4;
171387ef 1898 hw->channel_change_time = 5000;
465ca84d 1899 hw->max_listen_interval = 10;
dd190183
LR		 1900 /* Hardware supports 10 but we use 4 */
1901 hw->max_rate_tries = 4;
528f0c6b 1902 hw->sta_data_size = sizeof(struct ath_node);
17d7904d 1903 hw->vif_data_size = sizeof(struct ath_vif);
f078f209 1904
8feceb67 1905 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1906
c52f33d0
JM		 1907 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1908 &sc->sbands[IEEE80211_BAND_2GHZ];
1909 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1910 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1911 &sc->sbands[IEEE80211_BAND_5GHZ];
1912}
1913
1e40bcfa 1914/* Device driver core initialization */
5bb12791
LR		 1915int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
1916 const struct ath_bus_ops *bus_ops)
c52f33d0
JM		 1917{
1918 struct ieee80211_hw *hw = sc->hw;
1510718d 1919 struct ath_common *common;
4d6b228d 1920 struct ath_hw *ah;
c52f33d0 1921 int error = 0, i;
3a702e49 1922 struct ath_regulatory *reg;
c52f33d0 1923
4d6b228d 1924 dev_dbg(sc->dev, "Attach ATH hw\n");
c52f33d0 1925
5bb12791 1926 error = ath_init_softc(devid, sc, subsysid, bus_ops);
c52f33d0
JM		 1927 if (error != 0)
1928 return error;
1929
4d6b228d 1930 ah = sc->sc_ah;
1510718d 1931 common = ath9k_hw_common(ah);
4d6b228d 1932
c52f33d0
JM		 1933 /* get mac address from hardware and set in mac80211 */
1934
1510718d 1935 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
c52f33d0
JM		 1936
1937 ath_set_hw_capab(sc, hw);
1938
1510718d 1939 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
c26c2e57
LR		 1940 ath9k_reg_notifier);
1941 if (error)
1942 return error;
1943
1510718d 1944 reg = &common->regulatory;
c26c2e57 1945
4d6b228d 1946 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1947 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
4d6b228d 1948 if (test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes))
eb2599ca 1949 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1950 }
1951
db93e7b5
SB		 1952 /* initialize tx/rx engine */
1953 error = ath_tx_init(sc, ATH_TXBUF);
1954 if (error != 0)
40b130a9 1955 goto error_attach;
8feceb67 1956
db93e7b5
SB		 1957 error = ath_rx_init(sc, ATH_RXBUF);
1958 if (error != 0)
40b130a9 1959 goto error_attach;
8feceb67 1960
0e2dedf9 1961 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
f98c3bd2
JM		 1962 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1963 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
0e2dedf9 1964
db93e7b5 1965 error = ieee80211_register_hw(hw);
8feceb67 1966
3a702e49 1967 if (!ath_is_world_regd(reg)) {
c02cf373 1968 error = regulatory_hint(hw->wiphy, reg->alpha2);
fe33eb39
LR		 1969 if (error)
1970 goto error_attach;
1971 }
5f8e077c 1972
db93e7b5
SB		 1973 /* Initialize LED control */
1974 ath_init_leds(sc);
8feceb67 1975
3b319aae 1976 ath_start_rfkill_poll(sc);
5f8e077c 1977
8feceb67 1978 return 0;
40b130a9
VT		 1979
1980error_attach:
1981 /* cleanup tx queues */
1982 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1983 if (ATH_TXQ_SETUP(sc, i))
1984 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1985
7fda1666 1986 ath9k_uninit_hw(sc);
40b130a9 1987
8feceb67 1988 return error;
f078f209
LR		 1989}
1990
ff37e337
S		 1991int ath_reset(struct ath_softc *sc, bool retry_tx)
1992{
cbe61d8a 1993 struct ath_hw *ah = sc->sc_ah;
c46917bb 1994 struct ath_common *common = ath9k_hw_common(ah);
030bb495 1995 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1996 int r;
ff37e337
S		 1997
1998 ath9k_hw_set_interrupts(ah, 0);
043a0405 1999 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 2000 ath_stoprecv(sc);
2001 ath_flushrecv(sc);
2002
2003 spin_lock_bh(&sc->sc_resetlock);
2660b81a 2004 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 2005 if (r)
c46917bb
LR		 2006 ath_print(common, ATH_DBG_FATAL,
2007 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S		 2008 spin_unlock_bh(&sc->sc_resetlock);
2009
2010 if (ath_startrecv(sc) != 0)
c46917bb
LR		 2011 ath_print(common, ATH_DBG_FATAL,
2012 "Unable to start recv logic\n");
ff37e337
S		 2013
2014 /*
2015 * We may be doing a reset in response to a request
2016 * that changes the channel so update any state that
2017 * might change as a result.
2018 */
ce111bad 2019 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 2020
2021 ath_update_txpow(sc);
2022
2023 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 2024 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 2025
17d7904d 2026 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 2027
2028 if (retry_tx) {
2029 int i;
2030 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2031 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 2032 spin_lock_bh(&sc->tx.txq[i].axq_lock);
2033 ath_txq_schedule(sc, &sc->tx.txq[i]);
2034 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 2035 }
2036 }
2037 }
2038
ae8d2858 2039 return r;
ff37e337
S		 2040}
2041
2042/*
2043 * This function will allocate both the DMA descriptor structure, and the
2044 * buffers it contains. These are used to contain the descriptors used
2045 * by the system.
2046*/
2047int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
2048 struct list_head *head, const char *name,
2049 int nbuf, int ndesc)
2050{
2051#define DS2PHYS(_dd, _ds) \
2052 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
2053#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
2054#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
c46917bb 2055 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
ff37e337
S		 2056 struct ath_desc *ds;
2057 struct ath_buf *bf;
2058 int i, bsize, error;
2059
c46917bb
LR		 2060 ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
2061 name, nbuf, ndesc);
ff37e337 2062
b03a9db9 2063 INIT_LIST_HEAD(head);
ff37e337
S		 2064 /* ath_desc must be a multiple of DWORDs */
2065 if ((sizeof(struct ath_desc) % 4) != 0) {
c46917bb
LR		 2066 ath_print(common, ATH_DBG_FATAL,
2067 "ath_desc not DWORD aligned\n");
9680e8a3 2068 BUG_ON((sizeof(struct ath_desc) % 4) != 0);
ff37e337
S		 2069 error = -ENOMEM;
2070 goto fail;
2071 }
2072
ff37e337
S		 2073 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
2074
2075 /*
2076 * Need additional DMA memory because we can't use
2077 * descriptors that cross the 4K page boundary. Assume
2078 * one skipped descriptor per 4K page.
2079 */
2660b81a 2080 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
ff37e337
S		 2081 u32 ndesc_skipped =
2082 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
2083 u32 dma_len;
2084
2085 while (ndesc_skipped) {
2086 dma_len = ndesc_skipped * sizeof(struct ath_desc);
2087 dd->dd_desc_len += dma_len;
2088
2089 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
2090 };
2091 }
2092
2093 /* allocate descriptors */
7da3c55c 2094 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
f0e6ce13 2095 &dd->dd_desc_paddr, GFP_KERNEL);
ff37e337
S		 2096 if (dd->dd_desc == NULL) {
2097 error = -ENOMEM;
2098 goto fail;
2099 }
2100 ds = dd->dd_desc;
c46917bb
LR		 2101 ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
2102 name, ds, (u32) dd->dd_desc_len,
2103 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
ff37e337
S		 2104
2105 /* allocate buffers */
2106 bsize = sizeof(struct ath_buf) * nbuf;
f0e6ce13 2107 bf = kzalloc(bsize, GFP_KERNEL);
ff37e337
S		 2108 if (bf == NULL) {
2109 error = -ENOMEM;
2110 goto fail2;
2111 }
ff37e337
S		 2112 dd->dd_bufptr = bf;
2113
ff37e337
S		 2114 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
2115 bf->bf_desc = ds;
2116 bf->bf_daddr = DS2PHYS(dd, ds);
2117
2660b81a 2118 if (!(sc->sc_ah->caps.hw_caps &
ff37e337
S		 2119 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
2120 /*
2121 * Skip descriptor addresses which can cause 4KB
2122 * boundary crossing (addr + length) with a 32 dword
2123 * descriptor fetch.
2124 */
2125 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
9680e8a3 2126 BUG_ON((caddr_t) bf->bf_desc >=
ff37e337
S		 2127 ((caddr_t) dd->dd_desc +
2128 dd->dd_desc_len));
2129
2130 ds += ndesc;
2131 bf->bf_desc = ds;
2132 bf->bf_daddr = DS2PHYS(dd, ds);
2133 }
2134 }
2135 list_add_tail(&bf->list, head);
2136 }
2137 return 0;
2138fail2:
7da3c55c
GJ		 2139 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2140 dd->dd_desc_paddr);
ff37e337
S		 2141fail:
2142 memset(dd, 0, sizeof(*dd));
2143 return error;
2144#undef ATH_DESC_4KB_BOUND_CHECK
2145#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
2146#undef DS2PHYS
2147}
2148
2149void ath_descdma_cleanup(struct ath_softc *sc,
2150 struct ath_descdma *dd,
2151 struct list_head *head)
2152{
7da3c55c
GJ		 2153 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2154 dd->dd_desc_paddr);
ff37e337
S		 2155
2156 INIT_LIST_HEAD(head);
2157 kfree(dd->dd_bufptr);
2158 memset(dd, 0, sizeof(*dd));
2159}
2160
2161int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
2162{
2163 int qnum;
2164
2165 switch (queue) {
2166 case 0:
b77f483f 2167 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 2168 break;
2169 case 1:
b77f483f 2170 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 2171 break;
2172 case 2:
b77f483f 2173 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 2174 break;
2175 case 3:
b77f483f 2176 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 2177 break;
2178 default:
b77f483f 2179 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 2180 break;
2181 }
2182
2183 return qnum;
2184}
2185
2186int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
2187{
2188 int qnum;
2189
2190 switch (queue) {
2191 case ATH9K_WME_AC_VO:
2192 qnum = 0;
2193 break;
2194 case ATH9K_WME_AC_VI:
2195 qnum = 1;
2196 break;
2197 case ATH9K_WME_AC_BE:
2198 qnum = 2;
2199 break;
2200 case ATH9K_WME_AC_BK:
2201 qnum = 3;
2202 break;
2203 default:
2204 qnum = -1;
2205 break;
2206 }
2207
2208 return qnum;
2209}
2210
5f8e077c
LR		 2211/* XXX: Remove me once we don't depend on ath9k_channel for all
2212 * this redundant data */
0e2dedf9
JM		 2213void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
2214 struct ath9k_channel *ichan)
5f8e077c 2215{
5f8e077c
LR		 2216 struct ieee80211_channel *chan = hw->conf.channel;
2217 struct ieee80211_conf *conf = &hw->conf;
2218
2219 ichan->channel = chan->center_freq;
2220 ichan->chan = chan;
2221
2222 if (chan->band == IEEE80211_BAND_2GHZ) {
2223 ichan->chanmode = CHANNEL_G;
8813262e 2224 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
5f8e077c
LR		 2225 } else {
2226 ichan->chanmode = CHANNEL_A;
2227 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
2228 }
2229
25c56eec 2230 if (conf_is_ht(conf))
5f8e077c
LR		 2231 ichan->chanmode = ath_get_extchanmode(sc, chan,
2232 conf->channel_type);
5f8e077c
LR		 2233}
2234
ff37e337
S		 2235/**********************/
2236/* mac80211 callbacks */
2237/**********************/
2238
75d7839f
LR		 2239/*
2240 * (Re)start btcoex timers
2241 */
2242static void ath9k_btcoex_timer_resume(struct ath_softc *sc)
2243{
2244 struct ath_btcoex *btcoex = &sc->btcoex;
2245 struct ath_hw *ah = sc->sc_ah;
2246
c46917bb
LR		 2247 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
2248 "Starting btcoex timers");
75d7839f
LR		 2249
2250 /* make sure duty cycle timer is also stopped when resuming */
2251 if (btcoex->hw_timer_enabled)
cd9bf689 2252 ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
75d7839f
LR		 2253
2254 btcoex->bt_priority_cnt = 0;
2255 btcoex->bt_priority_time = jiffies;
2256 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
2257
2258 mod_timer(&btcoex->period_timer, jiffies);
2259}
2260
8feceb67 2261static int ath9k_start(struct ieee80211_hw *hw)
f078f209 2262{
bce048d7
JM		 2263 struct ath_wiphy *aphy = hw->priv;
2264 struct ath_softc *sc = aphy->sc;
af03abec 2265 struct ath_hw *ah = sc->sc_ah;
c46917bb 2266 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 2267 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 2268 struct ath9k_channel *init_channel;
82880a7c 2269 int r;
f078f209 2270
c46917bb
LR		 2271 ath_print(common, ATH_DBG_CONFIG,
2272 "Starting driver with initial channel: %d MHz\n",
2273 curchan->center_freq);
f078f209 2274
141b38b6
S		 2275 mutex_lock(&sc->mutex);
2276
9580a222
JM		 2277 if (ath9k_wiphy_started(sc)) {
2278 if (sc->chan_idx == curchan->hw_value) {
2279 /*
2280 * Already on the operational channel, the new wiphy
2281 * can be marked active.
2282 */
2283 aphy->state = ATH_WIPHY_ACTIVE;
2284 ieee80211_wake_queues(hw);
2285 } else {
2286 /*
2287 * Another wiphy is on another channel, start the new
2288 * wiphy in paused state.
2289 */
2290 aphy->state = ATH_WIPHY_PAUSED;
2291 ieee80211_stop_queues(hw);
2292 }
2293 mutex_unlock(&sc->mutex);
2294 return 0;
2295 }
2296 aphy->state = ATH_WIPHY_ACTIVE;
2297
8feceb67 2298 /* setup initial channel */
f078f209 2299
82880a7c 2300 sc->chan_idx = curchan->hw_value;
f078f209 2301
82880a7c 2302 init_channel = ath_get_curchannel(sc, hw);
ff37e337
S		 2303
2304 /* Reset SERDES registers */
af03abec 2305 ath9k_hw_configpcipowersave(ah, 0, 0);
ff37e337
S		 2306
2307 /*
2308 * The basic interface to setting the hardware in a good
2309 * state is ``reset''. On return the hardware is known to
2310 * be powered up and with interrupts disabled. This must
2311 * be followed by initialization of the appropriate bits
2312 * and then setup of the interrupt mask.
2313 */
2314 spin_lock_bh(&sc->sc_resetlock);
af03abec 2315 r = ath9k_hw_reset(ah, init_channel, false);
ae8d2858 2316 if (r) {
c46917bb
LR		 2317 ath_print(common, ATH_DBG_FATAL,
2318 "Unable to reset hardware; reset status %d "
2319 "(freq %u MHz)\n", r,
2320 curchan->center_freq);
ff37e337 2321 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 2322 goto mutex_unlock;
ff37e337
S		 2323 }
2324 spin_unlock_bh(&sc->sc_resetlock);
2325
2326 /*
2327 * This is needed only to setup initial state
2328 * but it's best done after a reset.
2329 */
2330 ath_update_txpow(sc);
8feceb67 2331
ff37e337
S		 2332 /*
2333 * Setup the hardware after reset:
2334 * The receive engine is set going.
2335 * Frame transmit is handled entirely
2336 * in the frame output path; there's nothing to do
2337 * here except setup the interrupt mask.
2338 */
2339 if (ath_startrecv(sc) != 0) {
c46917bb
LR		 2340 ath_print(common, ATH_DBG_FATAL,
2341 "Unable to start recv logic\n");
141b38b6
S		 2342 r = -EIO;
2343 goto mutex_unlock;
f078f209 2344 }
8feceb67 2345
ff37e337 2346 /* Setup our intr mask. */
17d7904d 2347 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S		 2348 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2349 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2350
af03abec 2351 if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 2352 sc->imask |= ATH9K_INT_GTT;
ff37e337 2353
af03abec 2354 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 2355 sc->imask |= ATH9K_INT_CST;
ff37e337 2356
ce111bad 2357 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 2358
2359 sc->sc_flags &= ~SC_OP_INVALID;
2360
2361 /* Disable BMISS interrupt when we're not associated */
17d7904d 2362 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
af03abec 2363 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337 2364
bce048d7 2365 ieee80211_wake_queues(hw);
ff37e337 2366
42935eca 2367 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
164ace38 2368
766ec4a9
LR		 2369 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
2370 !ah->btcoex_hw.enabled) {
5e197292
LR		 2371 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
2372 AR_STOMP_LOW_WLAN_WGHT);
af03abec 2373 ath9k_hw_btcoex_enable(ah);
f985ad12 2374
5bb12791
LR		 2375 if (common->bus_ops->bt_coex_prep)
2376 common->bus_ops->bt_coex_prep(common);
766ec4a9 2377 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 2378 ath9k_btcoex_timer_resume(sc);
1773912b
VT		 2379 }
2380
141b38b6
S		 2381mutex_unlock:
2382 mutex_unlock(&sc->mutex);
2383
ae8d2858 2384 return r;
f078f209
LR		 2385}
2386
8feceb67
VT		 2387static int ath9k_tx(struct ieee80211_hw *hw,
2388 struct sk_buff *skb)
f078f209 2389{
528f0c6b 2390 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM		 2391 struct ath_wiphy *aphy = hw->priv;
2392 struct ath_softc *sc = aphy->sc;
c46917bb 2393 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 2394 struct ath_tx_control txctl;
8feceb67 2395 int hdrlen, padsize;
528f0c6b 2396
8089cc47 2397 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
c46917bb
LR		 2398 ath_print(common, ATH_DBG_XMIT,
2399 "ath9k: %s: TX in unexpected wiphy state "
2400 "%d\n", wiphy_name(hw->wiphy), aphy->state);
ee166a0e
JM		 2401 goto exit;
2402 }
2403
96148326 2404 if (sc->ps_enabled) {
dc8c4585
JM		 2405 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2406 /*
2407 * mac80211 does not set PM field for normal data frames, so we
2408 * need to update that based on the current PS mode.
2409 */
2410 if (ieee80211_is_data(hdr->frame_control) &&
2411 !ieee80211_is_nullfunc(hdr->frame_control) &&
2412 !ieee80211_has_pm(hdr->frame_control)) {
c46917bb
LR		 2413 ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
2414 "while in PS mode\n");
dc8c4585
JM		 2415 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2416 }
2417 }
2418
9a23f9ca
JM		 2419 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2420 /*
2421 * We are using PS-Poll and mac80211 can request TX while in
2422 * power save mode. Need to wake up hardware for the TX to be
2423 * completed and if needed, also for RX of buffered frames.
2424 */
2425 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2426 ath9k_ps_wakeup(sc);
2427 ath9k_hw_setrxabort(sc->sc_ah, 0);
2428 if (ieee80211_is_pspoll(hdr->frame_control)) {
c46917bb
LR		 2429 ath_print(common, ATH_DBG_PS,
2430 "Sending PS-Poll to pick a buffered frame\n");
9a23f9ca
JM		 2431 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2432 } else {
c46917bb
LR		 2433 ath_print(common, ATH_DBG_PS,
2434 "Wake up to complete TX\n");
9a23f9ca
JM		 2435 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2436 }
2437 /*
2438 * The actual restore operation will happen only after
2439 * the sc_flags bit is cleared. We are just dropping
2440 * the ps_usecount here.
2441 */
2442 ath9k_ps_restore(sc);
2443 }
2444
528f0c6b 2445 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2446
8feceb67
VT		 2447 /*
2448 * As a temporary workaround, assign seq# here; this will likely need
2449 * to be cleaned up to work better with Beacon transmission and virtual
2450 * BSSes.
2451 */
2452 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2453 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2454 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2455 sc->tx.seq_no += 0x10;
8feceb67 2456 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2457 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2458 }
f078f209 2459
8feceb67
VT		 2460 /* Add the padding after the header if this is not already done */
2461 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2462 if (hdrlen & 3) {
2463 padsize = hdrlen % 4;
2464 if (skb_headroom(skb) < padsize)
2465 return -1;
2466 skb_push(skb, padsize);
2467 memmove(skb->data, skb->data + padsize, hdrlen);
2468 }
2469
528f0c6b
S		 2470 /* Check if a tx queue is available */
2471
2472 txctl.txq = ath_test_get_txq(sc, skb);
2473 if (!txctl.txq)
2474 goto exit;
2475
c46917bb 2476 ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2477
c52f33d0 2478 if (ath_tx_start(hw, skb, &txctl) != 0) {
c46917bb 2479 ath_print(common, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2480 goto exit;
8feceb67
VT		 2481 }
2482
528f0c6b
S		 2483 return 0;
2484exit:
2485 dev_kfree_skb_any(skb);
8feceb67 2486 return 0;
f078f209
LR		 2487}
2488
75d7839f
LR		 2489/*
2490 * Pause btcoex timer and bt duty cycle timer
2491 */
2492static void ath9k_btcoex_timer_pause(struct ath_softc *sc)
2493{
2494 struct ath_btcoex *btcoex = &sc->btcoex;
2495 struct ath_hw *ah = sc->sc_ah;
2496
2497 del_timer_sync(&btcoex->period_timer);
2498
2499 if (btcoex->hw_timer_enabled)
cd9bf689 2500 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
75d7839f
LR		 2501
2502 btcoex->hw_timer_enabled = false;
2503}
2504
8feceb67 2505static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 2506{
bce048d7
JM		 2507 struct ath_wiphy *aphy = hw->priv;
2508 struct ath_softc *sc = aphy->sc;
af03abec 2509 struct ath_hw *ah = sc->sc_ah;
c46917bb 2510 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2511
4c483817
S		 2512 mutex_lock(&sc->mutex);
2513
9580a222
JM		 2514 aphy->state = ATH_WIPHY_INACTIVE;
2515
c94dbff7
LR		 2516 cancel_delayed_work_sync(&sc->ath_led_blink_work);
2517 cancel_delayed_work_sync(&sc->tx_complete_work);
2518
2519 if (!sc->num_sec_wiphy) {
2520 cancel_delayed_work_sync(&sc->wiphy_work);
2521 cancel_work_sync(&sc->chan_work);
2522 }
2523
9c84b797 2524 if (sc->sc_flags & SC_OP_INVALID) {
c46917bb 2525 ath_print(common, ATH_DBG_ANY, "Device not present\n");
4c483817 2526 mutex_unlock(&sc->mutex);
9c84b797
S		 2527 return;
2528 }
8feceb67 2529
9580a222
JM		 2530 if (ath9k_wiphy_started(sc)) {
2531 mutex_unlock(&sc->mutex);
2532 return; /* another wiphy still in use */
2533 }
2534
766ec4a9 2535 if (ah->btcoex_hw.enabled) {
af03abec 2536 ath9k_hw_btcoex_disable(ah);
766ec4a9 2537 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 2538 ath9k_btcoex_timer_pause(sc);
1773912b
VT		 2539 }
2540
ff37e337
S		 2541 /* make sure h/w will not generate any interrupt
2542 * before setting the invalid flag. */
af03abec 2543 ath9k_hw_set_interrupts(ah, 0);
ff37e337
S		 2544
2545 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2546 ath_drain_all_txq(sc, false);
ff37e337 2547 ath_stoprecv(sc);
af03abec 2548 ath9k_hw_phy_disable(ah);
ff37e337 2549 } else
b77f483f 2550 sc->rx.rxlink = NULL;
ff37e337 2551
ff37e337 2552 /* disable HAL and put h/w to sleep */
af03abec
LR		 2553 ath9k_hw_disable(ah);
2554 ath9k_hw_configpcipowersave(ah, 1, 1);
9ecdef4b 2555 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
ff37e337
S		 2556
2557 sc->sc_flags |= SC_OP_INVALID;
500c064d 2558
141b38b6
S		 2559 mutex_unlock(&sc->mutex);
2560
c46917bb 2561 ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2562}
2563
8feceb67
VT		 2564static int ath9k_add_interface(struct ieee80211_hw *hw,
2565 struct ieee80211_if_init_conf *conf)
f078f209 2566{
bce048d7
JM		 2567 struct ath_wiphy *aphy = hw->priv;
2568 struct ath_softc *sc = aphy->sc;
c46917bb 2569 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
17d7904d 2570 struct ath_vif *avp = (void *)conf->vif->drv_priv;
d97809db 2571 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 2572 int ret = 0;
8feceb67 2573
141b38b6
S		 2574 mutex_lock(&sc->mutex);
2575
8ca21f01
JM		 2576 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2577 sc->nvifs > 0) {
2578 ret = -ENOBUFS;
2579 goto out;
2580 }
2581
8feceb67 2582 switch (conf->type) {
05c914fe 2583 case NL80211_IFTYPE_STATION:
d97809db 2584 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2585 break;
05c914fe 2586 case NL80211_IFTYPE_ADHOC:
05c914fe 2587 case NL80211_IFTYPE_AP:
9cb5412b 2588 case NL80211_IFTYPE_MESH_POINT:
2c3db3d5
JM		 2589 if (sc->nbcnvifs >= ATH_BCBUF) {
2590 ret = -ENOBUFS;
2591 goto out;
2592 }
9cb5412b 2593 ic_opmode = conf->type;
f078f209
LR		 2594 break;
2595 default:
c46917bb 2596 ath_print(common, ATH_DBG_FATAL,
04bd4638 2597 "Interface type %d not yet supported\n", conf->type);
2c3db3d5
JM		 2598 ret = -EOPNOTSUPP;
2599 goto out;
f078f209
LR		 2600 }
2601
c46917bb
LR		 2602 ath_print(common, ATH_DBG_CONFIG,
2603 "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 2604
17d7904d 2605 /* Set the VIF opmode */
5640b08e
S		 2606 avp->av_opmode = ic_opmode;
2607 avp->av_bslot = -1;
2608
2c3db3d5 2609 sc->nvifs++;
8ca21f01
JM		 2610
2611 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2612 ath9k_set_bssid_mask(hw);
2613
2c3db3d5
JM		 2614 if (sc->nvifs > 1)
2615 goto out; /* skip global settings for secondary vif */
2616
b238e90e 2617 if (ic_opmode == NL80211_IFTYPE_AP) {
5640b08e 2618 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
b238e90e
S		 2619 sc->sc_flags |= SC_OP_TSF_RESET;
2620 }
5640b08e 2621
5640b08e 2622 /* Set the device opmode */
2660b81a 2623 sc->sc_ah->opmode = ic_opmode;
5640b08e 2624
4e30ffa2
VN		 2625 /*
2626 * Enable MIB interrupts when there are hardware phy counters.
2627 * Note we only do this (at the moment) for station mode.
2628 */
4af9cf4f 2629 if ((conf->type == NL80211_IFTYPE_STATION) ||
9cb5412b
PE		 2630 (conf->type == NL80211_IFTYPE_ADHOC) ||
2631 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
1aa8e847 2632 sc->imask |= ATH9K_INT_MIB;
4af9cf4f
S		 2633 sc->imask |= ATH9K_INT_TSFOOR;
2634 }
2635
17d7904d 2636 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 2637
f38faa31
SB		 2638 if (conf->type == NL80211_IFTYPE_AP ||
2639 conf->type == NL80211_IFTYPE_ADHOC ||
2640 conf->type == NL80211_IFTYPE_MONITOR)
3d536acf 2641 ath_start_ani(common);
6f255425 2642
2c3db3d5 2643out:
141b38b6 2644 mutex_unlock(&sc->mutex);
2c3db3d5 2645 return ret;
f078f209
LR		 2646}
2647
8feceb67
VT		 2648static void ath9k_remove_interface(struct ieee80211_hw *hw,
2649 struct ieee80211_if_init_conf *conf)
f078f209 2650{
bce048d7
JM		 2651 struct ath_wiphy *aphy = hw->priv;
2652 struct ath_softc *sc = aphy->sc;
c46917bb 2653 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
17d7904d 2654 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2c3db3d5 2655 int i;
f078f209 2656
c46917bb 2657 ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2658
141b38b6
S		 2659 mutex_lock(&sc->mutex);
2660
6f255425 2661 /* Stop ANI */
3d536acf 2662 del_timer_sync(&common->ani.timer);
580f0b8a 2663
8feceb67 2664 /* Reclaim beacon resources */
9cb5412b
PE		 2665 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2666 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2667 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
b77f483f 2668 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2669 ath_beacon_return(sc, avp);
580f0b8a 2670 }
f078f209 2671
8feceb67 2672 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2673
2c3db3d5
JM		 2674 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2675 if (sc->beacon.bslot[i] == conf->vif) {
2676 printk(KERN_DEBUG "%s: vif had allocated beacon "
2677 "slot\n", __func__);
2678 sc->beacon.bslot[i] = NULL;
c52f33d0 2679 sc->beacon.bslot_aphy[i] = NULL;
2c3db3d5
JM		 2680 }
2681 }
2682
17d7904d 2683 sc->nvifs--;
141b38b6
S		 2684
2685 mutex_unlock(&sc->mutex);
f078f209
LR		 2686}
2687
e8975581 2688static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2689{
bce048d7
JM		 2690 struct ath_wiphy *aphy = hw->priv;
2691 struct ath_softc *sc = aphy->sc;
c46917bb 2692 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
e8975581 2693 struct ieee80211_conf *conf = &hw->conf;
8782b41d 2694 struct ath_hw *ah = sc->sc_ah;
194b7c13 2695 bool disable_radio;
f078f209 2696
aa33de09 2697 mutex_lock(&sc->mutex);
141b38b6 2698
194b7c13
LR		 2699 /*
2700 * Leave this as the first check because we need to turn on the
2701 * radio if it was disabled before prior to processing the rest
2702 * of the changes. Likewise we must only disable the radio towards
2703 * the end.
2704 */
64839170 2705 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
194b7c13
LR		 2706 bool enable_radio;
2707 bool all_wiphys_idle;
2708 bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
64839170
LR		 2709
2710 spin_lock_bh(&sc->wiphy_lock);
2711 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
194b7c13
LR		 2712 ath9k_set_wiphy_idle(aphy, idle);
2713
2714 if (!idle && all_wiphys_idle)
2715 enable_radio = true;
2716
2717 /*
2718 * After we unlock here its possible another wiphy
2719 * can be re-renabled so to account for that we will
2720 * only disable the radio toward the end of this routine
2721 * if by then all wiphys are still idle.
2722 */
64839170
LR		 2723 spin_unlock_bh(&sc->wiphy_lock);
2724
194b7c13 2725 if (enable_radio) {
68a89116 2726 ath_radio_enable(sc, hw);
c46917bb
LR		 2727 ath_print(common, ATH_DBG_CONFIG,
2728 "not-idle: enabling radio\n");
64839170
LR		 2729 }
2730 }
2731
3cbb5dd7
VN		 2732 if (changed & IEEE80211_CONF_CHANGE_PS) {
2733 if (conf->flags & IEEE80211_CONF_PS) {
8782b41d
VN		 2734 if (!(ah->caps.hw_caps &
2735 ATH9K_HW_CAP_AUTOSLEEP)) {
2736 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2737 sc->imask |= ATH9K_INT_TIM_TIMER;
2738 ath9k_hw_set_interrupts(sc->sc_ah,
2739 sc->imask);
2740 }
2741 ath9k_hw_setrxabort(sc->sc_ah, 1);
3cbb5dd7 2742 }
96148326 2743 sc->ps_enabled = true;
3cbb5dd7 2744 } else {
96148326 2745 sc->ps_enabled = false;
9ecdef4b 2746 ath9k_setpower(sc, ATH9K_PM_AWAKE);
8782b41d
VN		 2747 if (!(ah->caps.hw_caps &
2748 ATH9K_HW_CAP_AUTOSLEEP)) {
2749 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca
JM		 2750 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2751 SC_OP_WAIT_FOR_CAB |
2752 SC_OP_WAIT_FOR_PSPOLL_DATA |
2753 SC_OP_WAIT_FOR_TX_ACK);
8782b41d
VN		 2754 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2755 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2756 ath9k_hw_set_interrupts(sc->sc_ah,
2757 sc->imask);
2758 }
3cbb5dd7
VN		 2759 }
2760 }
2761 }
2762
4797938c 2763 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2764 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2765 int pos = curchan->hw_value;
ae5eb026 2766
0e2dedf9
JM		 2767 aphy->chan_idx = pos;
2768 aphy->chan_is_ht = conf_is_ht(conf);
2769
8089cc47
JM		 2770 if (aphy->state == ATH_WIPHY_SCAN ||
2771 aphy->state == ATH_WIPHY_ACTIVE)
2772 ath9k_wiphy_pause_all_forced(sc, aphy);
2773 else {
2774 /*
2775 * Do not change operational channel based on a paused
2776 * wiphy changes.
2777 */
2778 goto skip_chan_change;
2779 }
0e2dedf9 2780
c46917bb
LR		 2781 ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2782 curchan->center_freq);
f078f209 2783
5f8e077c 2784 /* XXX: remove me eventualy */
0e2dedf9 2785 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 2786
ecf70441 2787 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2788
0e2dedf9 2789 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
c46917bb
LR		 2790 ath_print(common, ATH_DBG_FATAL,
2791 "Unable to set channel\n");
aa33de09 2792 mutex_unlock(&sc->mutex);
e11602b7
S		 2793 return -EINVAL;
2794 }
094d05dc 2795 }
f078f209 2796
8089cc47 2797skip_chan_change:
5c020dc6 2798 if (changed & IEEE80211_CONF_CHANGE_POWER)
17d7904d 2799 sc->config.txpowlimit = 2 * conf->power_level;
f078f209 2800
194b7c13
LR		 2801 spin_lock_bh(&sc->wiphy_lock);
2802 disable_radio = ath9k_all_wiphys_idle(sc);
2803 spin_unlock_bh(&sc->wiphy_lock);
2804
64839170 2805 if (disable_radio) {
c46917bb 2806 ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
68a89116 2807 ath_radio_disable(sc, hw);
64839170
LR		 2808 }
2809
aa33de09 2810 mutex_unlock(&sc->mutex);
141b38b6 2811
f078f209
LR		 2812 return 0;
2813}
2814
8feceb67
VT		 2815#define SUPPORTED_FILTERS \
2816 (FIF_PROMISC_IN_BSS | \
2817 FIF_ALLMULTI | \
2818 FIF_CONTROL | \
af6a3fc7 2819 FIF_PSPOLL | \
8feceb67
VT		 2820 FIF_OTHER_BSS | \
2821 FIF_BCN_PRBRESP_PROMISC | \
2822 FIF_FCSFAIL)
c83be688 2823
8feceb67
VT		 2824/* FIXME: sc->sc_full_reset ? */
2825static void ath9k_configure_filter(struct ieee80211_hw *hw,
2826 unsigned int changed_flags,
2827 unsigned int *total_flags,
3ac64bee 2828 u64 multicast)
8feceb67 2829{
bce048d7
JM		 2830 struct ath_wiphy *aphy = hw->priv;
2831 struct ath_softc *sc = aphy->sc;
8feceb67 2832 u32 rfilt;
f078f209 2833
8feceb67
VT		 2834 changed_flags &= SUPPORTED_FILTERS;
2835 *total_flags &= SUPPORTED_FILTERS;
f078f209 2836
b77f483f 2837 sc->rx.rxfilter = *total_flags;
aa68aeaa 2838 ath9k_ps_wakeup(sc);
8feceb67
VT		 2839 rfilt = ath_calcrxfilter(sc);
2840 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 2841 ath9k_ps_restore(sc);
f078f209 2842
c46917bb
LR		 2843 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
2844 "Set HW RX filter: 0x%x\n", rfilt);
8feceb67 2845}
f078f209 2846
8feceb67
VT		 2847static void ath9k_sta_notify(struct ieee80211_hw *hw,
2848 struct ieee80211_vif *vif,
2849 enum sta_notify_cmd cmd,
17741cdc 2850 struct ieee80211_sta *sta)
8feceb67 2851{
bce048d7
JM		 2852 struct ath_wiphy *aphy = hw->priv;
2853 struct ath_softc *sc = aphy->sc;
f078f209 2854
8feceb67
VT		 2855 switch (cmd) {
2856 case STA_NOTIFY_ADD:
5640b08e 2857 ath_node_attach(sc, sta);
8feceb67
VT		 2858 break;
2859 case STA_NOTIFY_REMOVE:
b5aa9bf9 2860 ath_node_detach(sc, sta);
8feceb67
VT		 2861 break;
2862 default:
2863 break;
2864 }
f078f209
LR		 2865}
2866
141b38b6 2867static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 2868 const struct ieee80211_tx_queue_params *params)
f078f209 2869{
bce048d7
JM		 2870 struct ath_wiphy *aphy = hw->priv;
2871 struct ath_softc *sc = aphy->sc;
c46917bb 2872 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67
VT		 2873 struct ath9k_tx_queue_info qi;
2874 int ret = 0, qnum;
f078f209 2875
8feceb67
VT		 2876 if (queue >= WME_NUM_AC)
2877 return 0;
f078f209 2878
141b38b6
S		 2879 mutex_lock(&sc->mutex);
2880
1ffb0610
S		 2881 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2882
8feceb67
VT		 2883 qi.tqi_aifs = params->aifs;
2884 qi.tqi_cwmin = params->cw_min;
2885 qi.tqi_cwmax = params->cw_max;
2886 qi.tqi_burstTime = params->txop;
2887 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2888
c46917bb
LR		 2889 ath_print(common, ATH_DBG_CONFIG,
2890 "Configure tx [queue/halq] [%d/%d], "
2891 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2892 queue, qnum, params->aifs, params->cw_min,
2893 params->cw_max, params->txop);
f078f209 2894
8feceb67
VT		 2895 ret = ath_txq_update(sc, qnum, &qi);
2896 if (ret)
c46917bb 2897 ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2898
141b38b6
S		 2899 mutex_unlock(&sc->mutex);
2900
8feceb67
VT		 2901 return ret;
2902}
f078f209 2903
8feceb67
VT		 2904static int ath9k_set_key(struct ieee80211_hw *hw,
2905 enum set_key_cmd cmd,
dc822b5d
JB		 2906 struct ieee80211_vif *vif,
2907 struct ieee80211_sta *sta,
8feceb67
VT		 2908 struct ieee80211_key_conf *key)
2909{
bce048d7
JM		 2910 struct ath_wiphy *aphy = hw->priv;
2911 struct ath_softc *sc = aphy->sc;
c46917bb 2912 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67 2913 int ret = 0;
f078f209 2914
b3bd89ce
JM		 2915 if (modparam_nohwcrypt)
2916 return -ENOSPC;
2917
141b38b6 2918 mutex_lock(&sc->mutex);
3cbb5dd7 2919 ath9k_ps_wakeup(sc);
c46917bb 2920 ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 2921
8feceb67
VT		 2922 switch (cmd) {
2923 case SET_KEY:
7e86c104 2924 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM		 2925 if (ret >= 0) {
2926 key->hw_key_idx = ret;
8feceb67
VT		 2927 /* push IV and Michael MIC generation to stack */
2928 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2929 if (key->alg == ALG_TKIP)
2930 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2931 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2932 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2933 ret = 0;
8feceb67
VT		 2934 }
2935 break;
2936 case DISABLE_KEY:
7e86c104 2937 ath_key_delete(common, key);
8feceb67
VT		 2938 break;
2939 default:
2940 ret = -EINVAL;
2941 }
f078f209 2942
3cbb5dd7 2943 ath9k_ps_restore(sc);
141b38b6
S		 2944 mutex_unlock(&sc->mutex);
2945
8feceb67
VT		 2946 return ret;
2947}
f078f209 2948
8feceb67
VT		 2949static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2950 struct ieee80211_vif *vif,
2951 struct ieee80211_bss_conf *bss_conf,
2952 u32 changed)
2953{
bce048d7
JM		 2954 struct ath_wiphy *aphy = hw->priv;
2955 struct ath_softc *sc = aphy->sc;
2d0ddec5 2956 struct ath_hw *ah = sc->sc_ah;
1510718d 2957 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5
JB		 2958 struct ath_vif *avp = (void *)vif->drv_priv;
2959 u32 rfilt = 0;
2960 int error, i;
f078f209 2961
141b38b6
S		 2962 mutex_lock(&sc->mutex);
2963
2d0ddec5
JB		 2964 /*
2965 * TODO: Need to decide which hw opmode to use for
2966 * multi-interface cases
2967 * XXX: This belongs into add_interface!
2968 */
2969 if (vif->type == NL80211_IFTYPE_AP &&
2970 ah->opmode != NL80211_IFTYPE_AP) {
2971 ah->opmode = NL80211_IFTYPE_STATION;
2972 ath9k_hw_setopmode(ah);
1510718d
LR		 2973 memcpy(common->curbssid, common->macaddr, ETH_ALEN);
2974 common->curaid = 0;
f2b2143e 2975 ath9k_hw_write_associd(ah);
2d0ddec5
JB		 2976 /* Request full reset to get hw opmode changed properly */
2977 sc->sc_flags |= SC_OP_FULL_RESET;
2978 }
2979
2980 if ((changed & BSS_CHANGED_BSSID) &&
2981 !is_zero_ether_addr(bss_conf->bssid)) {
2982 switch (vif->type) {
2983 case NL80211_IFTYPE_STATION:
2984 case NL80211_IFTYPE_ADHOC:
2985 case NL80211_IFTYPE_MESH_POINT:
2986 /* Set BSSID */
1510718d 2987 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2d0ddec5 2988 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1510718d 2989 common->curaid = 0;
f2b2143e 2990 ath9k_hw_write_associd(ah);
2d0ddec5
JB		 2991
2992 /* Set aggregation protection mode parameters */
2993 sc->config.ath_aggr_prot = 0;
2994
c46917bb
LR		 2995 ath_print(common, ATH_DBG_CONFIG,
2996 "RX filter 0x%x bssid %pM aid 0x%x\n",
2997 rfilt, common->curbssid, common->curaid);
2d0ddec5
JB		 2998
2999 /* need to reconfigure the beacon */
3000 sc->sc_flags &= ~SC_OP_BEACONS ;
3001
3002 break;
3003 default:
3004 break;
3005 }
3006 }
3007
3008 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
3009 (vif->type == NL80211_IFTYPE_AP) ||
3010 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
3011 if ((changed & BSS_CHANGED_BEACON) ||
3012 (changed & BSS_CHANGED_BEACON_ENABLED &&
3013 bss_conf->enable_beacon)) {
3014 /*
3015 * Allocate and setup the beacon frame.
3016 *
3017 * Stop any previous beacon DMA. This may be
3018 * necessary, for example, when an ibss merge
3019 * causes reconfiguration; we may be called
3020 * with beacon transmission active.
3021 */
3022 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
3023
3024 error = ath_beacon_alloc(aphy, vif);
3025 if (!error)
3026 ath_beacon_config(sc, vif);
3027 }
3028 }
3029
3030 /* Check for WLAN_CAPABILITY_PRIVACY ? */
3031 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
3032 for (i = 0; i < IEEE80211_WEP_NKID; i++)
3033 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
3034 ath9k_hw_keysetmac(sc->sc_ah,
3035 (u16)i,
1510718d 3036 common->curbssid);
2d0ddec5
JB		 3037 }
3038
3039 /* Only legacy IBSS for now */
3040 if (vif->type == NL80211_IFTYPE_ADHOC)
3041 ath_update_chainmask(sc, 0);
3042
8feceb67 3043 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
c46917bb
LR		 3044 ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
3045 bss_conf->use_short_preamble);
8feceb67
VT		 3046 if (bss_conf->use_short_preamble)
3047 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
3048 else
3049 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
3050 }
f078f209 3051
8feceb67 3052 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
c46917bb
LR		 3053 ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
3054 bss_conf->use_cts_prot);
8feceb67
VT		 3055 if (bss_conf->use_cts_prot &&
3056 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
3057 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
3058 else
3059 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
3060 }
f078f209 3061
8feceb67 3062 if (changed & BSS_CHANGED_ASSOC) {
c46917bb 3063 ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 3064 bss_conf->assoc);
5640b08e 3065 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 3066 }
141b38b6 3067
57c4d7b4
JB		 3068 /*
3069 * The HW TSF has to be reset when the beacon interval changes.
3070 * We set the flag here, and ath_beacon_config_ap() would take this
3071 * into account when it gets called through the subsequent
3072 * config_interface() call - with IFCC_BEACON in the changed field.
3073 */
3074
3075 if (changed & BSS_CHANGED_BEACON_INT) {
3076 sc->sc_flags |= SC_OP_TSF_RESET;
3077 sc->beacon_interval = bss_conf->beacon_int;
3078 }
3079
141b38b6 3080 mutex_unlock(&sc->mutex);
8feceb67 3081}
f078f209 3082
8feceb67
VT		 3083static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
3084{
3085 u64 tsf;
bce048d7
JM		 3086 struct ath_wiphy *aphy = hw->priv;
3087 struct ath_softc *sc = aphy->sc;
f078f209 3088
141b38b6
S		 3089 mutex_lock(&sc->mutex);
3090 tsf = ath9k_hw_gettsf64(sc->sc_ah);
3091 mutex_unlock(&sc->mutex);
f078f209 3092
8feceb67
VT		 3093 return tsf;
3094}
f078f209 3095
3b5d665b
AF		 3096static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3097{
bce048d7
JM		 3098 struct ath_wiphy *aphy = hw->priv;
3099 struct ath_softc *sc = aphy->sc;
3b5d665b 3100
141b38b6
S		 3101 mutex_lock(&sc->mutex);
3102 ath9k_hw_settsf64(sc->sc_ah, tsf);
3103 mutex_unlock(&sc->mutex);
3b5d665b
AF		 3104}
3105
8feceb67
VT		 3106static void ath9k_reset_tsf(struct ieee80211_hw *hw)
3107{
bce048d7
JM		 3108 struct ath_wiphy *aphy = hw->priv;
3109 struct ath_softc *sc = aphy->sc;
c83be688 3110
141b38b6 3111 mutex_lock(&sc->mutex);
21526d57
LR		 3112
3113 ath9k_ps_wakeup(sc);
141b38b6 3114 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR		 3115 ath9k_ps_restore(sc);
3116
141b38b6 3117 mutex_unlock(&sc->mutex);
8feceb67 3118}
f078f209 3119
8feceb67 3120static int ath9k_ampdu_action(struct ieee80211_hw *hw,
141b38b6
S		 3121 enum ieee80211_ampdu_mlme_action action,
3122 struct ieee80211_sta *sta,
3123 u16 tid, u16 *ssn)
8feceb67 3124{
bce048d7
JM		 3125 struct ath_wiphy *aphy = hw->priv;
3126 struct ath_softc *sc = aphy->sc;
8feceb67 3127 int ret = 0;
f078f209 3128
8feceb67
VT		 3129 switch (action) {
3130 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 3131 if (!(sc->sc_flags & SC_OP_RXAGGR))
3132 ret = -ENOTSUPP;
8feceb67
VT		 3133 break;
3134 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 3135 break;
3136 case IEEE80211_AMPDU_TX_START:
f83da965
S		 3137 ath_tx_aggr_start(sc, sta, tid, ssn);
3138 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 3139 break;
3140 case IEEE80211_AMPDU_TX_STOP:
f83da965 3141 ath_tx_aggr_stop(sc, sta, tid);
17741cdc 3142 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 3143 break;
b1720231 3144 case IEEE80211_AMPDU_TX_OPERATIONAL:
8469cdef
S		 3145 ath_tx_aggr_resume(sc, sta, tid);
3146 break;
8feceb67 3147 default:
c46917bb
LR		 3148 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
3149 "Unknown AMPDU action\n");
8feceb67
VT		 3150 }
3151
3152 return ret;
f078f209
LR		 3153}
3154
0c98de65
S		 3155static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
3156{
bce048d7
JM		 3157 struct ath_wiphy *aphy = hw->priv;
3158 struct ath_softc *sc = aphy->sc;
0c98de65 3159
3d832611 3160 mutex_lock(&sc->mutex);
8089cc47
JM		 3161 if (ath9k_wiphy_scanning(sc)) {
3162 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
3163 "same time\n");
3164 /*
3165 * Do not allow the concurrent scanning state for now. This
3166 * could be improved with scanning control moved into ath9k.
3167 */
3d832611 3168 mutex_unlock(&sc->mutex);
8089cc47
JM		 3169 return;
3170 }
3171
3172 aphy->state = ATH_WIPHY_SCAN;
3173 ath9k_wiphy_pause_all_forced(sc, aphy);
3174
e5f0921a 3175 spin_lock_bh(&sc->ani_lock);
0c98de65 3176 sc->sc_flags |= SC_OP_SCANNING;
e5f0921a 3177 spin_unlock_bh(&sc->ani_lock);
3d832611 3178 mutex_unlock(&sc->mutex);
0c98de65
S		 3179}
3180
3181static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
3182{
bce048d7
JM		 3183 struct ath_wiphy *aphy = hw->priv;
3184 struct ath_softc *sc = aphy->sc;
0c98de65 3185
3d832611 3186 mutex_lock(&sc->mutex);
e5f0921a 3187 spin_lock_bh(&sc->ani_lock);
8089cc47 3188 aphy->state = ATH_WIPHY_ACTIVE;
0c98de65 3189 sc->sc_flags &= ~SC_OP_SCANNING;
9c07a777 3190 sc->sc_flags |= SC_OP_FULL_RESET;
e5f0921a 3191 spin_unlock_bh(&sc->ani_lock);
d0bec342 3192 ath_beacon_config(sc, NULL);
3d832611 3193 mutex_unlock(&sc->mutex);
0c98de65
S		 3194}
3195
6baff7f9 3196struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 3197 .tx = ath9k_tx,
3198 .start = ath9k_start,
3199 .stop = ath9k_stop,
3200 .add_interface = ath9k_add_interface,
3201 .remove_interface = ath9k_remove_interface,
3202 .config = ath9k_config,
8feceb67 3203 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 3204 .sta_notify = ath9k_sta_notify,
3205 .conf_tx = ath9k_conf_tx,
8feceb67 3206 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 3207 .set_key = ath9k_set_key,
8feceb67 3208 .get_tsf = ath9k_get_tsf,
3b5d665b 3209 .set_tsf = ath9k_set_tsf,
8feceb67 3210 .reset_tsf = ath9k_reset_tsf,
4233df6b 3211 .ampdu_action = ath9k_ampdu_action,
0c98de65
S		 3212 .sw_scan_start = ath9k_sw_scan_start,
3213 .sw_scan_complete = ath9k_sw_scan_complete,
3b319aae 3214 .rfkill_poll = ath9k_rfkill_poll_state,
8feceb67
VT		 3215};
3216
6baff7f9 3217static int __init ath9k_init(void)
f078f209 3218{
ca8a8560
VT		 3219 int error;
3220
ca8a8560
VT		 3221 /* Register rate control algorithm */
3222 error = ath_rate_control_register();
3223 if (error != 0) {
3224 printk(KERN_ERR
b51bb3cd
LR		 3225 "ath9k: Unable to register rate control "
3226 "algorithm: %d\n",
ca8a8560 3227 error);
6baff7f9 3228 goto err_out;
ca8a8560
VT		 3229 }
3230
19d8bc22
GJ		 3231 error = ath9k_debug_create_root();
3232 if (error) {
3233 printk(KERN_ERR
3234 "ath9k: Unable to create debugfs root: %d\n",
3235 error);
3236 goto err_rate_unregister;
3237 }
3238
6baff7f9
GJ		 3239 error = ath_pci_init();
3240 if (error < 0) {
f078f209 3241 printk(KERN_ERR
b51bb3cd 3242 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9 3243 error = -ENODEV;
19d8bc22 3244 goto err_remove_root;
f078f209
LR		 3245 }
3246
09329d37
GJ		 3247 error = ath_ahb_init();
3248 if (error < 0) {
3249 error = -ENODEV;
3250 goto err_pci_exit;
3251 }
3252
f078f209 3253 return 0;
6baff7f9 3254
09329d37
GJ		 3255 err_pci_exit:
3256 ath_pci_exit();
3257
19d8bc22
GJ		 3258 err_remove_root:
3259 ath9k_debug_remove_root();
6baff7f9
GJ		 3260 err_rate_unregister:
3261 ath_rate_control_unregister();
3262 err_out:
3263 return error;
f078f209 3264}
6baff7f9 3265module_init(ath9k_init);
f078f209 3266
6baff7f9 3267static void __exit ath9k_exit(void)
f078f209 3268{
09329d37 3269 ath_ahb_exit();
6baff7f9 3270 ath_pci_exit();
19d8bc22 3271 ath9k_debug_remove_root();
ca8a8560 3272 ath_rate_control_unregister();
04bd4638 3273 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 3274}
6baff7f9 3275module_exit(ath9k_exit);
Linux kernel - Deliverables
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