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rfkill: relicense header file
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
f078f209 19
f078f209
LR		 20static char *dev_info = "ath9k";
21
22MODULE_AUTHOR("Atheros Communications");
23MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
24MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
25MODULE_LICENSE("Dual BSD/GPL");
26
b3bd89ce
JM		 27static int modparam_nohwcrypt;
28module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
29MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
30
5f8e077c
LR		 31/* We use the hw_value as an index into our private channel structure */
32
33#define CHAN2G(_freq, _idx) { \
34 .center_freq = (_freq), \
35 .hw_value = (_idx), \
eeddfd9d 36 .max_power = 20, \
5f8e077c
LR		 37}
38
39#define CHAN5G(_freq, _idx) { \
40 .band = IEEE80211_BAND_5GHZ, \
41 .center_freq = (_freq), \
42 .hw_value = (_idx), \
eeddfd9d 43 .max_power = 20, \
5f8e077c
LR		 44}
45
46/* Some 2 GHz radios are actually tunable on 2312-2732
47 * on 5 MHz steps, we support the channels which we know
48 * we have calibration data for all cards though to make
49 * this static */
50static struct ieee80211_channel ath9k_2ghz_chantable[] = {
51 CHAN2G(2412, 0), /* Channel 1 */
52 CHAN2G(2417, 1), /* Channel 2 */
53 CHAN2G(2422, 2), /* Channel 3 */
54 CHAN2G(2427, 3), /* Channel 4 */
55 CHAN2G(2432, 4), /* Channel 5 */
56 CHAN2G(2437, 5), /* Channel 6 */
57 CHAN2G(2442, 6), /* Channel 7 */
58 CHAN2G(2447, 7), /* Channel 8 */
59 CHAN2G(2452, 8), /* Channel 9 */
60 CHAN2G(2457, 9), /* Channel 10 */
61 CHAN2G(2462, 10), /* Channel 11 */
62 CHAN2G(2467, 11), /* Channel 12 */
63 CHAN2G(2472, 12), /* Channel 13 */
64 CHAN2G(2484, 13), /* Channel 14 */
65};
66
67/* Some 5 GHz radios are actually tunable on XXXX-YYYY
68 * on 5 MHz steps, we support the channels which we know
69 * we have calibration data for all cards though to make
70 * this static */
71static struct ieee80211_channel ath9k_5ghz_chantable[] = {
72 /* _We_ call this UNII 1 */
73 CHAN5G(5180, 14), /* Channel 36 */
74 CHAN5G(5200, 15), /* Channel 40 */
75 CHAN5G(5220, 16), /* Channel 44 */
76 CHAN5G(5240, 17), /* Channel 48 */
77 /* _We_ call this UNII 2 */
78 CHAN5G(5260, 18), /* Channel 52 */
79 CHAN5G(5280, 19), /* Channel 56 */
80 CHAN5G(5300, 20), /* Channel 60 */
81 CHAN5G(5320, 21), /* Channel 64 */
82 /* _We_ call this "Middle band" */
83 CHAN5G(5500, 22), /* Channel 100 */
84 CHAN5G(5520, 23), /* Channel 104 */
85 CHAN5G(5540, 24), /* Channel 108 */
86 CHAN5G(5560, 25), /* Channel 112 */
87 CHAN5G(5580, 26), /* Channel 116 */
88 CHAN5G(5600, 27), /* Channel 120 */
89 CHAN5G(5620, 28), /* Channel 124 */
90 CHAN5G(5640, 29), /* Channel 128 */
91 CHAN5G(5660, 30), /* Channel 132 */
92 CHAN5G(5680, 31), /* Channel 136 */
93 CHAN5G(5700, 32), /* Channel 140 */
94 /* _We_ call this UNII 3 */
95 CHAN5G(5745, 33), /* Channel 149 */
96 CHAN5G(5765, 34), /* Channel 153 */
97 CHAN5G(5785, 35), /* Channel 157 */
98 CHAN5G(5805, 36), /* Channel 161 */
99 CHAN5G(5825, 37), /* Channel 165 */
100};
101
ce111bad
LR		 102static void ath_cache_conf_rate(struct ath_softc *sc,
103 struct ieee80211_conf *conf)
ff37e337 104{
030bb495
LR		 105 switch (conf->channel->band) {
106 case IEEE80211_BAND_2GHZ:
107 if (conf_is_ht20(conf))
108 sc->cur_rate_table =
109 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
110 else if (conf_is_ht40_minus(conf))
111 sc->cur_rate_table =
112 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
113 else if (conf_is_ht40_plus(conf))
114 sc->cur_rate_table =
115 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 116 else
030bb495
LR		 117 sc->cur_rate_table =
118 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 119 break;
120 case IEEE80211_BAND_5GHZ:
121 if (conf_is_ht20(conf))
122 sc->cur_rate_table =
123 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
124 else if (conf_is_ht40_minus(conf))
125 sc->cur_rate_table =
126 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
127 else if (conf_is_ht40_plus(conf))
128 sc->cur_rate_table =
129 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
130 else
96742256
LR		 131 sc->cur_rate_table =
132 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 133 break;
134 default:
ce111bad 135 BUG_ON(1);
030bb495
LR		 136 break;
137 }
ff37e337
S		 138}
139
140static void ath_update_txpow(struct ath_softc *sc)
141{
cbe61d8a 142 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 143 u32 txpow;
144
17d7904d
S		 145 if (sc->curtxpow != sc->config.txpowlimit) {
146 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S		 147 /* read back in case value is clamped */
148 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 149 sc->curtxpow = txpow;
ff37e337
S		 150 }
151}
152
153static u8 parse_mpdudensity(u8 mpdudensity)
154{
155 /*
156 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
157 * 0 for no restriction
158 * 1 for 1/4 us
159 * 2 for 1/2 us
160 * 3 for 1 us
161 * 4 for 2 us
162 * 5 for 4 us
163 * 6 for 8 us
164 * 7 for 16 us
165 */
166 switch (mpdudensity) {
167 case 0:
168 return 0;
169 case 1:
170 case 2:
171 case 3:
172 /* Our lower layer calculations limit our precision to
173 1 microsecond */
174 return 1;
175 case 4:
176 return 2;
177 case 5:
178 return 4;
179 case 6:
180 return 8;
181 case 7:
182 return 16;
183 default:
184 return 0;
185 }
186}
187
188static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
189{
4f0fc7c3 190 const struct ath_rate_table *rate_table = NULL;
ff37e337
S		 191 struct ieee80211_supported_band *sband;
192 struct ieee80211_rate *rate;
193 int i, maxrates;
194
195 switch (band) {
196 case IEEE80211_BAND_2GHZ:
197 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
198 break;
199 case IEEE80211_BAND_5GHZ:
200 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
201 break;
202 default:
203 break;
204 }
205
206 if (rate_table == NULL)
207 return;
208
209 sband = &sc->sbands[band];
210 rate = sc->rates[band];
211
212 if (rate_table->rate_cnt > ATH_RATE_MAX)
213 maxrates = ATH_RATE_MAX;
214 else
215 maxrates = rate_table->rate_cnt;
216
217 for (i = 0; i < maxrates; i++) {
218 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
219 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 220 if (rate_table->info[i].short_preamble) {
221 rate[i].hw_value_short = rate_table->info[i].ratecode |
222 rate_table->info[i].short_preamble;
223 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
224 }
ff37e337 225 sband->n_bitrates++;
f46730d1 226
04bd4638
S		 227 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
228 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 229 }
230}
231
82880a7c
VT		 232static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
233 struct ieee80211_hw *hw)
234{
235 struct ieee80211_channel *curchan = hw->conf.channel;
236 struct ath9k_channel *channel;
237 u8 chan_idx;
238
239 chan_idx = curchan->hw_value;
240 channel = &sc->sc_ah->channels[chan_idx];
241 ath9k_update_ichannel(sc, hw, channel);
242 return channel;
243}
244
ff37e337
S		 245/*
246 * Set/change channels. If the channel is really being changed, it's done
247 * by reseting the chip. To accomplish this we must first cleanup any pending
248 * DMA, then restart stuff.
249*/
0e2dedf9
JM		 250int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
251 struct ath9k_channel *hchan)
ff37e337 252{
cbe61d8a 253 struct ath_hw *ah = sc->sc_ah;
ff37e337 254 bool fastcc = true, stopped;
ae8d2858
LR		 255 struct ieee80211_channel *channel = hw->conf.channel;
256 int r;
ff37e337
S		 257
258 if (sc->sc_flags & SC_OP_INVALID)
259 return -EIO;
260
3cbb5dd7
VN		 261 ath9k_ps_wakeup(sc);
262
c0d7c7af
LR		 263 /*
264 * This is only performed if the channel settings have
265 * actually changed.
266 *
267 * To switch channels clear any pending DMA operations;
268 * wait long enough for the RX fifo to drain, reset the
269 * hardware at the new frequency, and then re-enable
270 * the relevant bits of the h/w.
271 */
272 ath9k_hw_set_interrupts(ah, 0);
043a0405 273 ath_drain_all_txq(sc, false);
c0d7c7af 274 stopped = ath_stoprecv(sc);
ff37e337 275
c0d7c7af
LR		 276 /* XXX: do not flush receive queue here. We don't want
277 * to flush data frames already in queue because of
278 * changing channel. */
ff37e337 279
c0d7c7af
LR		 280 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
281 fastcc = false;
282
283 DPRINTF(sc, ATH_DBG_CONFIG,
284 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
2660b81a 285 sc->sc_ah->curchan->channel,
c0d7c7af 286 channel->center_freq, sc->tx_chan_width);
ff37e337 287
c0d7c7af
LR		 288 spin_lock_bh(&sc->sc_resetlock);
289
290 r = ath9k_hw_reset(ah, hchan, fastcc);
291 if (r) {
292 DPRINTF(sc, ATH_DBG_FATAL,
293 "Unable to reset channel (%u Mhz) "
6b45784f 294 "reset status %d\n",
c0d7c7af
LR		 295 channel->center_freq, r);
296 spin_unlock_bh(&sc->sc_resetlock);
3989279c 297 goto ps_restore;
ff37e337 298 }
c0d7c7af
LR		 299 spin_unlock_bh(&sc->sc_resetlock);
300
c0d7c7af
LR		 301 sc->sc_flags &= ~SC_OP_FULL_RESET;
302
303 if (ath_startrecv(sc) != 0) {
304 DPRINTF(sc, ATH_DBG_FATAL,
305 "Unable to restart recv logic\n");
3989279c
GJ		 306 r = -EIO;
307 goto ps_restore;
c0d7c7af
LR		 308 }
309
310 ath_cache_conf_rate(sc, &hw->conf);
311 ath_update_txpow(sc);
17d7904d 312 ath9k_hw_set_interrupts(ah, sc->imask);
3989279c
GJ		 313
314 ps_restore:
3cbb5dd7 315 ath9k_ps_restore(sc);
3989279c 316 return r;
ff37e337
S		 317}
318
319/*
320 * This routine performs the periodic noise floor calibration function
321 * that is used to adjust and optimize the chip performance. This
322 * takes environmental changes (location, temperature) into account.
323 * When the task is complete, it reschedules itself depending on the
324 * appropriate interval that was calculated.
325 */
326static void ath_ani_calibrate(unsigned long data)
327{
20977d3e
S		 328 struct ath_softc *sc = (struct ath_softc *)data;
329 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 330 bool longcal = false;
331 bool shortcal = false;
332 bool aniflag = false;
333 unsigned int timestamp = jiffies_to_msecs(jiffies);
20977d3e 334 u32 cal_interval, short_cal_interval;
ff37e337 335
20977d3e
S		 336 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
337 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337
S		 338
339 /*
340 * don't calibrate when we're scanning.
341 * we are most likely not on our home channel.
342 */
e5f0921a 343 spin_lock(&sc->ani_lock);
0c98de65 344 if (sc->sc_flags & SC_OP_SCANNING)
20977d3e 345 goto set_timer;
ff37e337 346
1ffc1c61
JM		 347 /* Only calibrate if awake */
348 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
349 goto set_timer;
350
351 ath9k_ps_wakeup(sc);
352
ff37e337 353 /* Long calibration runs independently of short calibration. */
17d7904d 354 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 355 longcal = true;
04bd4638 356 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
17d7904d 357 sc->ani.longcal_timer = timestamp;
ff37e337
S		 358 }
359
17d7904d
S		 360 /* Short calibration applies only while caldone is false */
361 if (!sc->ani.caldone) {
20977d3e 362 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 363 shortcal = true;
04bd4638 364 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
17d7904d
S		 365 sc->ani.shortcal_timer = timestamp;
366 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 367 }
368 } else {
17d7904d 369 if ((timestamp - sc->ani.resetcal_timer) >=
ff37e337 370 ATH_RESTART_CALINTERVAL) {
17d7904d
S		 371 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
372 if (sc->ani.caldone)
373 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 374 }
375 }
376
377 /* Verify whether we must check ANI */
20977d3e 378 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
ff37e337 379 aniflag = true;
17d7904d 380 sc->ani.checkani_timer = timestamp;
ff37e337
S		 381 }
382
383 /* Skip all processing if there's nothing to do. */
384 if (longcal || shortcal || aniflag) {
385 /* Call ANI routine if necessary */
386 if (aniflag)
22e66a4c 387 ath9k_hw_ani_monitor(ah, ah->curchan);
ff37e337
S		 388
389 /* Perform calibration if necessary */
390 if (longcal || shortcal) {
379f0440
S		 391 sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
392 sc->rx_chainmask, longcal);
393
394 if (longcal)
395 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
396 ah->curchan);
397
398 DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
399 ah->curchan->channel, ah->curchan->channelFlags,
400 sc->ani.noise_floor);
ff37e337
S		 401 }
402 }
403
1ffc1c61
JM		 404 ath9k_ps_restore(sc);
405
20977d3e 406set_timer:
e5f0921a 407 spin_unlock(&sc->ani_lock);
ff37e337
S		 408 /*
409 * Set timer interval based on previous results.
410 * The interval must be the shortest necessary to satisfy ANI,
411 * short calibration and long calibration.
412 */
aac9207e 413 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 414 if (sc->sc_ah->config.enable_ani)
aac9207e 415 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
17d7904d 416 if (!sc->ani.caldone)
20977d3e 417 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 418
17d7904d 419 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S		 420}
421
415f738e
S		 422static void ath_start_ani(struct ath_softc *sc)
423{
424 unsigned long timestamp = jiffies_to_msecs(jiffies);
425
426 sc->ani.longcal_timer = timestamp;
427 sc->ani.shortcal_timer = timestamp;
428 sc->ani.checkani_timer = timestamp;
429
430 mod_timer(&sc->ani.timer,
431 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
432}
433
ff37e337
S		 434/*
435 * Update tx/rx chainmask. For legacy association,
436 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 437 * the chainmask configuration, for bt coexistence, use
438 * the chainmask configuration even in legacy mode.
ff37e337 439 */
0e2dedf9 440void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337 441{
3d832611 442 if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
81fa16fb 443 (sc->btcoex_info.btcoex_scheme != ATH_BTCOEX_CFG_NONE)) {
2660b81a
S		 444 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
445 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
ff37e337 446 } else {
17d7904d
S		 447 sc->tx_chainmask = 1;
448 sc->rx_chainmask = 1;
ff37e337
S		 449 }
450
04bd4638 451 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
17d7904d 452 sc->tx_chainmask, sc->rx_chainmask);
ff37e337
S		 453}
454
455static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
456{
457 struct ath_node *an;
458
459 an = (struct ath_node *)sta->drv_priv;
460
87792efc 461 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 462 ath_tx_node_init(sc, an);
9e98ac65 463 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S		 464 sta->ht_cap.ampdu_factor);
465 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
a59b5a5e 466 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
87792efc 467 }
ff37e337
S		 468}
469
470static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
471{
472 struct ath_node *an = (struct ath_node *)sta->drv_priv;
473
474 if (sc->sc_flags & SC_OP_TXAGGR)
475 ath_tx_node_cleanup(sc, an);
476}
477
478static void ath9k_tasklet(unsigned long data)
479{
480 struct ath_softc *sc = (struct ath_softc *)data;
17d7904d 481 u32 status = sc->intrstatus;
ff37e337 482
153e080d
VT		 483 ath9k_ps_wakeup(sc);
484
ff37e337 485 if (status & ATH9K_INT_FATAL) {
ff37e337 486 ath_reset(sc, false);
153e080d 487 ath9k_ps_restore(sc);
ff37e337 488 return;
063d8be3 489 }
ff37e337 490
063d8be3
S		 491 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
492 spin_lock_bh(&sc->rx.rxflushlock);
493 ath_rx_tasklet(sc, 0);
494 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 495 }
496
063d8be3
S		 497 if (status & ATH9K_INT_TX)
498 ath_tx_tasklet(sc);
499
96148326 500 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
54ce846e
JM		 501 /*
502 * TSF sync does not look correct; remain awake to sync with
503 * the next Beacon.
504 */
505 DPRINTF(sc, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
ccdfeab6 506 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
54ce846e
JM		 507 }
508
ff37e337 509 /* re-enable hardware interrupt */
17d7904d 510 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
153e080d 511 ath9k_ps_restore(sc);
ff37e337
S		 512}
513
6baff7f9 514irqreturn_t ath_isr(int irq, void *dev)
ff37e337 515{
063d8be3
S		 516#define SCHED_INTR ( \
517 ATH9K_INT_FATAL | \
518 ATH9K_INT_RXORN | \
519 ATH9K_INT_RXEOL | \
520 ATH9K_INT_RX | \
521 ATH9K_INT_TX | \
522 ATH9K_INT_BMISS | \
523 ATH9K_INT_CST | \
524 ATH9K_INT_TSFOOR)
525
ff37e337 526 struct ath_softc *sc = dev;
cbe61d8a 527 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 528 enum ath9k_int status;
529 bool sched = false;
530
063d8be3
S		 531 /*
532 * The hardware is not ready/present, don't
533 * touch anything. Note this can happen early
534 * on if the IRQ is shared.
535 */
536 if (sc->sc_flags & SC_OP_INVALID)
537 return IRQ_NONE;
ff37e337 538
063d8be3
S		 539
540 /* shared irq, not for us */
541
153e080d 542 if (!ath9k_hw_intrpend(ah))
063d8be3 543 return IRQ_NONE;
063d8be3
S		 544
545 /*
546 * Figure out the reason(s) for the interrupt. Note
547 * that the hal returns a pseudo-ISR that may include
548 * bits we haven't explicitly enabled so we mask the
549 * value to insure we only process bits we requested.
550 */
551 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
552 status &= sc->imask; /* discard unasked-for bits */
ff37e337 553
063d8be3
S		 554 /*
555 * If there are no status bits set, then this interrupt was not
556 * for me (should have been caught above).
557 */
153e080d 558 if (!status)
063d8be3 559 return IRQ_NONE;
ff37e337 560
063d8be3
S		 561 /* Cache the status */
562 sc->intrstatus = status;
563
564 if (status & SCHED_INTR)
565 sched = true;
566
567 /*
568 * If a FATAL or RXORN interrupt is received, we have to reset the
569 * chip immediately.
570 */
571 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
572 goto chip_reset;
573
574 if (status & ATH9K_INT_SWBA)
575 tasklet_schedule(&sc->bcon_tasklet);
576
577 if (status & ATH9K_INT_TXURN)
578 ath9k_hw_updatetxtriglevel(ah, true);
579
580 if (status & ATH9K_INT_MIB) {
ff37e337 581 /*
063d8be3
S		 582 * Disable interrupts until we service the MIB
583 * interrupt; otherwise it will continue to
584 * fire.
ff37e337 585 */
063d8be3
S		 586 ath9k_hw_set_interrupts(ah, 0);
587 /*
588 * Let the hal handle the event. We assume
589 * it will clear whatever condition caused
590 * the interrupt.
591 */
22e66a4c 592 ath9k_hw_procmibevent(ah);
063d8be3
S		 593 ath9k_hw_set_interrupts(ah, sc->imask);
594 }
ff37e337 595
153e080d
VT		 596 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
597 if (status & ATH9K_INT_TIM_TIMER) {
063d8be3
S		 598 /* Clear RxAbort bit so that we can
599 * receive frames */
600 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
153e080d 601 ath9k_hw_setrxabort(sc->sc_ah, 0);
063d8be3 602 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337 603 }
063d8be3 604
1773912b
VT		 605 if (sc->btcoex_info.btcoex_scheme == ATH_BTCOEX_CFG_3WIRE)
606 if (status & ATH9K_INT_GENTIMER)
607 ath_gen_timer_isr(ah);
608
063d8be3 609chip_reset:
ff37e337 610
817e11de
S		 611 ath_debug_stat_interrupt(sc, status);
612
ff37e337
S		 613 if (sched) {
614 /* turn off every interrupt except SWBA */
17d7904d 615 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S		 616 tasklet_schedule(&sc->intr_tq);
617 }
618
619 return IRQ_HANDLED;
063d8be3
S		 620
621#undef SCHED_INTR
ff37e337
S		 622}
623
f078f209 624static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 625 struct ieee80211_channel *chan,
094d05dc 626 enum nl80211_channel_type channel_type)
f078f209
LR		 627{
628 u32 chanmode = 0;
f078f209
LR		 629
630 switch (chan->band) {
631 case IEEE80211_BAND_2GHZ:
094d05dc
S		 632 switch(channel_type) {
633 case NL80211_CHAN_NO_HT:
634 case NL80211_CHAN_HT20:
f078f209 635 chanmode = CHANNEL_G_HT20;
094d05dc
S		 636 break;
637 case NL80211_CHAN_HT40PLUS:
f078f209 638 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 639 break;
640 case NL80211_CHAN_HT40MINUS:
f078f209 641 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 642 break;
643 }
f078f209
LR		 644 break;
645 case IEEE80211_BAND_5GHZ:
094d05dc
S		 646 switch(channel_type) {
647 case NL80211_CHAN_NO_HT:
648 case NL80211_CHAN_HT20:
f078f209 649 chanmode = CHANNEL_A_HT20;
094d05dc
S		 650 break;
651 case NL80211_CHAN_HT40PLUS:
f078f209 652 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 653 break;
654 case NL80211_CHAN_HT40MINUS:
f078f209 655 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 656 break;
657 }
f078f209
LR		 658 break;
659 default:
660 break;
661 }
662
663 return chanmode;
664}
665
6ace2891 666static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
3f53dd64
JM		 667 struct ath9k_keyval *hk, const u8 *addr,
668 bool authenticator)
f078f209 669{
6ace2891
JM		 670 const u8 *key_rxmic;
671 const u8 *key_txmic;
f078f209 672
6ace2891
JM		 673 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
674 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 675
676 if (addr == NULL) {
d216aaa6
JM		 677 /*
678 * Group key installation - only two key cache entries are used
679 * regardless of splitmic capability since group key is only
680 * used either for TX or RX.
681 */
3f53dd64
JM		 682 if (authenticator) {
683 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
684 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
685 } else {
686 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
687 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
688 }
d216aaa6 689 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 690 }
17d7904d 691 if (!sc->splitmic) {
d216aaa6 692 /* TX and RX keys share the same key cache entry. */
f078f209
LR		 693 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
694 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
d216aaa6 695 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 696 }
d216aaa6
JM		 697
698 /* Separate key cache entries for TX and RX */
699
700 /* TX key goes at first index, RX key at +32. */
f078f209 701 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
d216aaa6
JM		 702 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
703 /* TX MIC entry failed. No need to proceed further */
d8baa939 704 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 705 "Setting TX MIC Key Failed\n");
f078f209
LR		 706 return 0;
707 }
708
709 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
710 /* XXX delete tx key on failure? */
d216aaa6 711 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
6ace2891
JM		 712}
713
714static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
715{
716 int i;
717
17d7904d
S		 718 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
719 if (test_bit(i, sc->keymap) ||
720 test_bit(i + 64, sc->keymap))
6ace2891 721 continue; /* At least one part of TKIP key allocated */
17d7904d
S		 722 if (sc->splitmic &&
723 (test_bit(i + 32, sc->keymap) ||
724 test_bit(i + 64 + 32, sc->keymap)))
6ace2891
JM		 725 continue; /* At least one part of TKIP key allocated */
726
727 /* Found a free slot for a TKIP key */
728 return i;
729 }
730 return -1;
731}
732
733static int ath_reserve_key_cache_slot(struct ath_softc *sc)
734{
735 int i;
736
737 /* First, try to find slots that would not be available for TKIP. */
17d7904d
S		 738 if (sc->splitmic) {
739 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
740 if (!test_bit(i, sc->keymap) &&
741 (test_bit(i + 32, sc->keymap) ||
742 test_bit(i + 64, sc->keymap) ||
743 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 744 return i;
17d7904d
S		 745 if (!test_bit(i + 32, sc->keymap) &&
746 (test_bit(i, sc->keymap) ||
747 test_bit(i + 64, sc->keymap) ||
748 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 749 return i + 32;
17d7904d
S		 750 if (!test_bit(i + 64, sc->keymap) &&
751 (test_bit(i , sc->keymap) ||
752 test_bit(i + 32, sc->keymap) ||
753 test_bit(i + 64 + 32, sc->keymap)))
ea612132 754 return i + 64;
17d7904d
S		 755 if (!test_bit(i + 64 + 32, sc->keymap) &&
756 (test_bit(i, sc->keymap) ||
757 test_bit(i + 32, sc->keymap) ||
758 test_bit(i + 64, sc->keymap)))
ea612132 759 return i + 64 + 32;
6ace2891
JM		 760 }
761 } else {
17d7904d
S		 762 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
763 if (!test_bit(i, sc->keymap) &&
764 test_bit(i + 64, sc->keymap))
6ace2891 765 return i;
17d7904d
S		 766 if (test_bit(i, sc->keymap) &&
767 !test_bit(i + 64, sc->keymap))
6ace2891
JM		 768 return i + 64;
769 }
770 }
771
772 /* No partially used TKIP slots, pick any available slot */
17d7904d 773 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
be2864cf
JM		 774 /* Do not allow slots that could be needed for TKIP group keys
775 * to be used. This limitation could be removed if we know that
776 * TKIP will not be used. */
777 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
778 continue;
17d7904d 779 if (sc->splitmic) {
be2864cf
JM		 780 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
781 continue;
782 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
783 continue;
784 }
785
17d7904d 786 if (!test_bit(i, sc->keymap))
6ace2891
JM		 787 return i; /* Found a free slot for a key */
788 }
789
790 /* No free slot found */
791 return -1;
f078f209
LR		 792}
793
794static int ath_key_config(struct ath_softc *sc,
3f53dd64 795 struct ieee80211_vif *vif,
dc822b5d 796 struct ieee80211_sta *sta,
f078f209
LR		 797 struct ieee80211_key_conf *key)
798{
f078f209
LR		 799 struct ath9k_keyval hk;
800 const u8 *mac = NULL;
801 int ret = 0;
6ace2891 802 int idx;
f078f209
LR		 803
804 memset(&hk, 0, sizeof(hk));
805
806 switch (key->alg) {
807 case ALG_WEP:
808 hk.kv_type = ATH9K_CIPHER_WEP;
809 break;
810 case ALG_TKIP:
811 hk.kv_type = ATH9K_CIPHER_TKIP;
812 break;
813 case ALG_CCMP:
814 hk.kv_type = ATH9K_CIPHER_AES_CCM;
815 break;
816 default:
ca470b29 817 return -EOPNOTSUPP;
f078f209
LR		 818 }
819
6ace2891 820 hk.kv_len = key->keylen;
f078f209
LR		 821 memcpy(hk.kv_val, key->key, key->keylen);
822
6ace2891
JM		 823 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
824 /* For now, use the default keys for broadcast keys. This may
825 * need to change with virtual interfaces. */
826 idx = key->keyidx;
827 } else if (key->keyidx) {
dc822b5d
JB		 828 if (WARN_ON(!sta))
829 return -EOPNOTSUPP;
830 mac = sta->addr;
831
6ace2891
JM		 832 if (vif->type != NL80211_IFTYPE_AP) {
833 /* Only keyidx 0 should be used with unicast key, but
834 * allow this for client mode for now. */
835 idx = key->keyidx;
836 } else
837 return -EIO;
f078f209 838 } else {
dc822b5d
JB		 839 if (WARN_ON(!sta))
840 return -EOPNOTSUPP;
841 mac = sta->addr;
842
6ace2891
JM		 843 if (key->alg == ALG_TKIP)
844 idx = ath_reserve_key_cache_slot_tkip(sc);
845 else
846 idx = ath_reserve_key_cache_slot(sc);
847 if (idx < 0)
ca470b29 848 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 849 }
850
851 if (key->alg == ALG_TKIP)
3f53dd64
JM		 852 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
853 vif->type == NL80211_IFTYPE_AP);
f078f209 854 else
d216aaa6 855 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
f078f209
LR		 856
857 if (!ret)
858 return -EIO;
859
17d7904d 860 set_bit(idx, sc->keymap);
6ace2891 861 if (key->alg == ALG_TKIP) {
17d7904d
S		 862 set_bit(idx + 64, sc->keymap);
863 if (sc->splitmic) {
864 set_bit(idx + 32, sc->keymap);
865 set_bit(idx + 64 + 32, sc->keymap);
6ace2891
JM		 866 }
867 }
868
869 return idx;
f078f209
LR		 870}
871
872static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
873{
6ace2891
JM		 874 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
875 if (key->hw_key_idx < IEEE80211_WEP_NKID)
876 return;
877
17d7904d 878 clear_bit(key->hw_key_idx, sc->keymap);
6ace2891
JM		 879 if (key->alg != ALG_TKIP)
880 return;
f078f209 881
17d7904d
S		 882 clear_bit(key->hw_key_idx + 64, sc->keymap);
883 if (sc->splitmic) {
884 clear_bit(key->hw_key_idx + 32, sc->keymap);
885 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
6ace2891 886 }
f078f209
LR		 887}
888
eb2599ca
S		 889static void setup_ht_cap(struct ath_softc *sc,
890 struct ieee80211_sta_ht_cap *ht_info)
f078f209 891{
140add21 892 u8 tx_streams, rx_streams;
f078f209 893
d9fe60de
JB		 894 ht_info->ht_supported = true;
895 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
896 IEEE80211_HT_CAP_SM_PS |
897 IEEE80211_HT_CAP_SGI_40 |
898 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 899
9e98ac65
S		 900 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
901 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
eb2599ca 902
d9fe60de
JB		 903 /* set up supported mcs set */
904 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
140add21
SB		 905 tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2;
906 rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;
907
908 if (tx_streams != rx_streams) {
909 DPRINTF(sc, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n",
910 tx_streams, rx_streams);
911 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
912 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
913 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
914 }
eb2599ca 915
140add21
SB		 916 ht_info->mcs.rx_mask[0] = 0xff;
917 if (rx_streams >= 2)
eb2599ca 918 ht_info->mcs.rx_mask[1] = 0xff;
eb2599ca 919
140add21 920 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 921}
922
8feceb67 923static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 924 struct ieee80211_vif *vif,
8feceb67 925 struct ieee80211_bss_conf *bss_conf)
f078f209 926{
f078f209 927
8feceb67 928 if (bss_conf->assoc) {
094d05dc 929 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
17d7904d 930 bss_conf->aid, sc->curbssid);
f078f209 931
8feceb67 932 /* New association, store aid */
2664f201
SB		 933 sc->curaid = bss_conf->aid;
934 ath9k_hw_write_associd(sc);
935
936 /*
937 * Request a re-configuration of Beacon related timers
938 * on the receipt of the first Beacon frame (i.e.,
939 * after time sync with the AP).
940 */
941 sc->sc_flags |= SC_OP_BEACON_SYNC;
f078f209 942
8feceb67 943 /* Configure the beacon */
2c3db3d5 944 ath_beacon_config(sc, vif);
f078f209 945
8feceb67 946 /* Reset rssi stats */
22e66a4c 947 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
f078f209 948
415f738e 949 ath_start_ani(sc);
8feceb67 950 } else {
1ffb0610 951 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
17d7904d 952 sc->curaid = 0;
f38faa31
SB		 953 /* Stop ANI */
954 del_timer_sync(&sc->ani.timer);
f078f209 955 }
8feceb67 956}
f078f209 957
8feceb67
VT		 958/********************************/
959/* LED functions */
960/********************************/
f078f209 961
f2bffa7e
VT		 962static void ath_led_blink_work(struct work_struct *work)
963{
964 struct ath_softc *sc = container_of(work, struct ath_softc,
965 ath_led_blink_work.work);
966
967 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
968 return;
85067c06
VT		 969
970 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
971 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
08fc5c1b 972 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
85067c06 973 else
08fc5c1b 974 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
85067c06 975 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
f2bffa7e 976
42935eca
LR		 977 ieee80211_queue_delayed_work(sc->hw,
978 &sc->ath_led_blink_work,
979 (sc->sc_flags & SC_OP_LED_ON) ?
980 msecs_to_jiffies(sc->led_off_duration) :
981 msecs_to_jiffies(sc->led_on_duration));
f2bffa7e 982
85067c06
VT		 983 sc->led_on_duration = sc->led_on_cnt ?
984 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
985 ATH_LED_ON_DURATION_IDLE;
986 sc->led_off_duration = sc->led_off_cnt ?
987 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
988 ATH_LED_OFF_DURATION_IDLE;
f2bffa7e
VT		 989 sc->led_on_cnt = sc->led_off_cnt = 0;
990 if (sc->sc_flags & SC_OP_LED_ON)
991 sc->sc_flags &= ~SC_OP_LED_ON;
992 else
993 sc->sc_flags |= SC_OP_LED_ON;
994}
995
8feceb67
VT		 996static void ath_led_brightness(struct led_classdev *led_cdev,
997 enum led_brightness brightness)
998{
999 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1000 struct ath_softc *sc = led->sc;
f078f209 1001
8feceb67
VT		 1002 switch (brightness) {
1003 case LED_OFF:
1004 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e 1005 led->led_type == ATH_LED_RADIO) {
08fc5c1b 1006 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
f2bffa7e 1007 (led->led_type == ATH_LED_RADIO));
8feceb67 1008 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 1009 if (led->led_type == ATH_LED_RADIO)
1010 sc->sc_flags &= ~SC_OP_LED_ON;
1011 } else {
1012 sc->led_off_cnt++;
1013 }
8feceb67
VT		 1014 break;
1015 case LED_FULL:
f2bffa7e 1016 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 1017 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
42935eca
LR		 1018 ieee80211_queue_delayed_work(sc->hw,
1019 &sc->ath_led_blink_work, 0);
f2bffa7e 1020 } else if (led->led_type == ATH_LED_RADIO) {
08fc5c1b 1021 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
f2bffa7e
VT		 1022 sc->sc_flags |= SC_OP_LED_ON;
1023 } else {
1024 sc->led_on_cnt++;
1025 }
8feceb67
VT		 1026 break;
1027 default:
1028 break;
f078f209 1029 }
8feceb67 1030}
f078f209 1031
8feceb67
VT		 1032static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1033 char *trigger)
1034{
1035 int ret;
f078f209 1036
8feceb67
VT		 1037 led->sc = sc;
1038 led->led_cdev.name = led->name;
1039 led->led_cdev.default_trigger = trigger;
1040 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 1041
8feceb67
VT		 1042 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1043 if (ret)
1044 DPRINTF(sc, ATH_DBG_FATAL,
1045 "Failed to register led:%s", led->name);
1046 else
1047 led->registered = 1;
1048 return ret;
1049}
f078f209 1050
8feceb67
VT		 1051static void ath_unregister_led(struct ath_led *led)
1052{
1053 if (led->registered) {
1054 led_classdev_unregister(&led->led_cdev);
1055 led->registered = 0;
f078f209 1056 }
f078f209
LR		 1057}
1058
8feceb67 1059static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1060{
8feceb67
VT		 1061 ath_unregister_led(&sc->assoc_led);
1062 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1063 ath_unregister_led(&sc->tx_led);
1064 ath_unregister_led(&sc->rx_led);
1065 ath_unregister_led(&sc->radio_led);
08fc5c1b 1066 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
8feceb67 1067}
f078f209 1068
8feceb67
VT		 1069static void ath_init_leds(struct ath_softc *sc)
1070{
1071 char *trigger;
1072 int ret;
f078f209 1073
08fc5c1b
VN		 1074 if (AR_SREV_9287(sc->sc_ah))
1075 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
1076 else
1077 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
1078
8feceb67 1079 /* Configure gpio 1 for output */
08fc5c1b 1080 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
8feceb67
VT		 1081 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1082 /* LED off, active low */
08fc5c1b 1083 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
7dcfdcd9 1084
f2bffa7e
VT		 1085 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1086
8feceb67
VT		 1087 trigger = ieee80211_get_radio_led_name(sc->hw);
1088 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
0818cb8a 1089 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1090 ret = ath_register_led(sc, &sc->radio_led, trigger);
1091 sc->radio_led.led_type = ATH_LED_RADIO;
1092 if (ret)
1093 goto fail;
7dcfdcd9 1094
8feceb67
VT		 1095 trigger = ieee80211_get_assoc_led_name(sc->hw);
1096 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
0818cb8a 1097 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1098 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1099 sc->assoc_led.led_type = ATH_LED_ASSOC;
1100 if (ret)
1101 goto fail;
f078f209 1102
8feceb67
VT		 1103 trigger = ieee80211_get_tx_led_name(sc->hw);
1104 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
0818cb8a 1105 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1106 ret = ath_register_led(sc, &sc->tx_led, trigger);
1107 sc->tx_led.led_type = ATH_LED_TX;
1108 if (ret)
1109 goto fail;
f078f209 1110
8feceb67
VT		 1111 trigger = ieee80211_get_rx_led_name(sc->hw);
1112 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
0818cb8a 1113 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1114 ret = ath_register_led(sc, &sc->rx_led, trigger);
1115 sc->rx_led.led_type = ATH_LED_RX;
1116 if (ret)
1117 goto fail;
f078f209 1118
8feceb67
VT		 1119 return;
1120
1121fail:
35c95ab9 1122 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67 1123 ath_deinit_leds(sc);
f078f209
LR		 1124}
1125
7ec3e514 1126void ath_radio_enable(struct ath_softc *sc)
500c064d 1127{
cbe61d8a 1128 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1129 struct ieee80211_channel *channel = sc->hw->conf.channel;
1130 int r;
500c064d 1131
3cbb5dd7 1132 ath9k_ps_wakeup(sc);
d2f5b3a6 1133 ath9k_hw_configpcipowersave(ah, 0);
ae8d2858 1134
159cd468
VT		 1135 if (!ah->curchan)
1136 ah->curchan = ath_get_curchannel(sc, sc->hw);
1137
d2f5b3a6 1138 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1139 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1140 if (r) {
500c064d 1141 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1142 "Unable to reset channel %u (%uMhz) ",
6b45784f 1143 "reset status %d\n",
ae8d2858 1144 channel->center_freq, r);
500c064d
VT		 1145 }
1146 spin_unlock_bh(&sc->sc_resetlock);
1147
1148 ath_update_txpow(sc);
1149 if (ath_startrecv(sc) != 0) {
1150 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1151 "Unable to restart recv logic\n");
500c064d
VT		 1152 return;
1153 }
1154
1155 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1156 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT		 1157
1158 /* Re-Enable interrupts */
17d7904d 1159 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT		 1160
1161 /* Enable LED */
08fc5c1b 1162 ath9k_hw_cfg_output(ah, ah->led_pin,
500c064d 1163 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b 1164 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
500c064d
VT		 1165
1166 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1167 ath9k_ps_restore(sc);
500c064d
VT		 1168}
1169
7ec3e514 1170void ath_radio_disable(struct ath_softc *sc)
500c064d 1171{
cbe61d8a 1172 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1173 struct ieee80211_channel *channel = sc->hw->conf.channel;
1174 int r;
500c064d 1175
3cbb5dd7 1176 ath9k_ps_wakeup(sc);
500c064d
VT		 1177 ieee80211_stop_queues(sc->hw);
1178
1179 /* Disable LED */
08fc5c1b
VN		 1180 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1181 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
500c064d
VT		 1182
1183 /* Disable interrupts */
1184 ath9k_hw_set_interrupts(ah, 0);
1185
043a0405 1186 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1187 ath_stoprecv(sc); /* turn off frame recv */
1188 ath_flushrecv(sc); /* flush recv queue */
1189
159cd468
VT		 1190 if (!ah->curchan)
1191 ah->curchan = ath_get_curchannel(sc, sc->hw);
1192
500c064d 1193 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1194 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1195 if (r) {
500c064d 1196 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1197 "Unable to reset channel %u (%uMhz) "
6b45784f 1198 "reset status %d\n",
ae8d2858 1199 channel->center_freq, r);
500c064d
VT		 1200 }
1201 spin_unlock_bh(&sc->sc_resetlock);
1202
1203 ath9k_hw_phy_disable(ah);
d2f5b3a6 1204 ath9k_hw_configpcipowersave(ah, 1);
3cbb5dd7 1205 ath9k_ps_restore(sc);
38ab422e 1206 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
500c064d
VT		 1207}
1208
5077fd35
GJ		 1209/*******************/
1210/* Rfkill */
1211/*******************/
1212
500c064d
VT		 1213static bool ath_is_rfkill_set(struct ath_softc *sc)
1214{
cbe61d8a 1215 struct ath_hw *ah = sc->sc_ah;
500c064d 1216
2660b81a
S		 1217 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1218 ah->rfkill_polarity;
500c064d
VT		 1219}
1220
3b319aae 1221static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
500c064d 1222{
3b319aae
JB		 1223 struct ath_wiphy *aphy = hw->priv;
1224 struct ath_softc *sc = aphy->sc;
19d337df 1225 bool blocked = !!ath_is_rfkill_set(sc);
500c064d 1226
3b319aae
JB		 1227 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1228
1229 if (blocked)
19d337df
JB		 1230 ath_radio_disable(sc);
1231 else
1232 ath_radio_enable(sc);
500c064d
VT		 1233}
1234
3b319aae 1235static void ath_start_rfkill_poll(struct ath_softc *sc)
500c064d 1236{
3b319aae 1237 struct ath_hw *ah = sc->sc_ah;
9c84b797 1238
3b319aae
JB		 1239 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1240 wiphy_rfkill_start_polling(sc->hw->wiphy);
9c84b797 1241}
500c064d 1242
6baff7f9 1243void ath_cleanup(struct ath_softc *sc)
39c3c2f2
GJ		 1244{
1245 ath_detach(sc);
1246 free_irq(sc->irq, sc);
1247 ath_bus_cleanup(sc);
c52f33d0 1248 kfree(sc->sec_wiphy);
39c3c2f2
GJ		 1249 ieee80211_free_hw(sc->hw);
1250}
1251
6baff7f9 1252void ath_detach(struct ath_softc *sc)
f078f209 1253{
8feceb67 1254 struct ieee80211_hw *hw = sc->hw;
9c84b797 1255 int i = 0;
f078f209 1256
3cbb5dd7
VN		 1257 ath9k_ps_wakeup(sc);
1258
04bd4638 1259 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1260
35c95ab9
LR		 1261 ath_deinit_leds(sc);
1262
c52f33d0
JM		 1263 for (i = 0; i < sc->num_sec_wiphy; i++) {
1264 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1265 if (aphy == NULL)
1266 continue;
1267 sc->sec_wiphy[i] = NULL;
1268 ieee80211_unregister_hw(aphy->hw);
1269 ieee80211_free_hw(aphy->hw);
1270 }
3fcdfb4b 1271 ieee80211_unregister_hw(hw);
8feceb67
VT		 1272 ath_rx_cleanup(sc);
1273 ath_tx_cleanup(sc);
f078f209 1274
9c84b797
S		 1275 tasklet_kill(&sc->intr_tq);
1276 tasklet_kill(&sc->bcon_tasklet);
f078f209 1277
9c84b797
S		 1278 if (!(sc->sc_flags & SC_OP_INVALID))
1279 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1280
9c84b797
S		 1281 /* cleanup tx queues */
1282 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1283 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1284 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797 1285
1773912b
VT		 1286 if ((sc->btcoex_info.no_stomp_timer) &&
1287 sc->btcoex_info.btcoex_scheme == ATH_BTCOEX_CFG_3WIRE)
1288 ath_gen_timer_free(sc->sc_ah, sc->btcoex_info.no_stomp_timer);
1289
9c84b797 1290 ath9k_hw_detach(sc->sc_ah);
3ce1b1a9 1291 sc->sc_ah = NULL;
826d2680 1292 ath9k_exit_debug(sc);
f078f209
LR		 1293}
1294
e3bb249b
BC		 1295static int ath9k_reg_notifier(struct wiphy *wiphy,
1296 struct regulatory_request *request)
1297{
1298 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1299 struct ath_wiphy *aphy = hw->priv;
1300 struct ath_softc *sc = aphy->sc;
608b88cb 1301 struct ath_regulatory *reg = &sc->common.regulatory;
e3bb249b
BC		 1302
1303 return ath_reg_notifier_apply(wiphy, request, reg);
1304}
1305
1e40bcfa
LR		 1306/*
1307 * Initialize and fill ath_softc, ath_sofct is the
1308 * "Software Carrier" struct. Historically it has existed
1309 * to allow the separation between hardware specific
1310 * variables (now in ath_hw) and driver specific variables.
1311 */
1312static int ath_init_softc(u16 devid, struct ath_softc *sc)
ff37e337 1313{
cbe61d8a 1314 struct ath_hw *ah = NULL;
4f3acf81 1315 int r = 0, i;
ff37e337
S		 1316 int csz = 0;
1317
1318 /* XXX: hardware will not be ready until ath_open() being called */
1319 sc->sc_flags |= SC_OP_INVALID;
88b126af 1320
826d2680
S		 1321 if (ath9k_init_debug(sc) < 0)
1322 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337 1323
c52f33d0 1324 spin_lock_init(&sc->wiphy_lock);
ff37e337 1325 spin_lock_init(&sc->sc_resetlock);
6158425b 1326 spin_lock_init(&sc->sc_serial_rw);
e5f0921a 1327 spin_lock_init(&sc->ani_lock);
04717ccd 1328 spin_lock_init(&sc->sc_pm_lock);
aa33de09 1329 mutex_init(&sc->mutex);
ff37e337 1330 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
9fc9ab0a 1331 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
ff37e337
S		 1332 (unsigned long)sc);
1333
1334 /*
1335 * Cache line size is used to size and align various
1336 * structures used to communicate with the hardware.
1337 */
88d15707 1338 ath_read_cachesize(sc, &csz);
ff37e337 1339 /* XXX assert csz is non-zero */
d15dd3e5 1340 sc->common.cachelsz = csz << 2; /* convert to bytes */
ff37e337 1341
4f3acf81
LR		 1342 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
1343 if (!ah) {
4f3acf81
LR		 1344 r = -ENOMEM;
1345 goto bad_no_ah;
1346 }
1347
1348 ah->ah_sc = sc;
8df5d1b7 1349 ah->hw_version.devid = devid;
e1e2f93f 1350 sc->sc_ah = ah;
4f3acf81 1351
f637cfd6 1352 r = ath9k_hw_init(ah);
4f3acf81 1353 if (r) {
ff37e337 1354 DPRINTF(sc, ATH_DBG_FATAL,
f637cfd6 1355 "Unable to initialize hardware; "
4f3acf81 1356 "initialization status: %d\n", r);
ff37e337
S		 1357 goto bad;
1358 }
ff37e337
S		 1359
1360 /* Get the hardware key cache size. */
2660b81a 1361 sc->keymax = ah->caps.keycache_size;
17d7904d 1362 if (sc->keymax > ATH_KEYMAX) {
d8baa939 1363 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 1364 "Warning, using only %u entries in %u key cache\n",
17d7904d
S		 1365 ATH_KEYMAX, sc->keymax);
1366 sc->keymax = ATH_KEYMAX;
ff37e337
S		 1367 }
1368
1369 /*
1370 * Reset the key cache since some parts do not
1371 * reset the contents on initial power up.
1372 */
17d7904d 1373 for (i = 0; i < sc->keymax; i++)
ff37e337 1374 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1375
ff37e337 1376 /* default to MONITOR mode */
2660b81a 1377 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
d97809db 1378
ff37e337
S		 1379 /* Setup rate tables */
1380
1381 ath_rate_attach(sc);
1382 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1383 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1384
1385 /*
1386 * Allocate hardware transmit queues: one queue for
1387 * beacon frames and one data queue for each QoS
1388 * priority. Note that the hal handles reseting
1389 * these queues at the needed time.
1390 */
b77f483f
S		 1391 sc->beacon.beaconq = ath_beaconq_setup(ah);
1392 if (sc->beacon.beaconq == -1) {
ff37e337 1393 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1394 "Unable to setup a beacon xmit queue\n");
4f3acf81 1395 r = -EIO;
ff37e337
S		 1396 goto bad2;
1397 }
b77f483f
S		 1398 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1399 if (sc->beacon.cabq == NULL) {
ff37e337 1400 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1401 "Unable to setup CAB xmit queue\n");
4f3acf81 1402 r = -EIO;
ff37e337
S		 1403 goto bad2;
1404 }
1405
17d7904d 1406 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
ff37e337
S		 1407 ath_cabq_update(sc);
1408
b77f483f
S		 1409 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1410 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1411
1412 /* Setup data queues */
1413 /* NB: ensure BK queue is the lowest priority h/w queue */
1414 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1415 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1416 "Unable to setup xmit queue for BK traffic\n");
4f3acf81 1417 r = -EIO;
ff37e337
S		 1418 goto bad2;
1419 }
1420
1421 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1422 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1423 "Unable to setup xmit queue for BE traffic\n");
4f3acf81 1424 r = -EIO;
ff37e337
S		 1425 goto bad2;
1426 }
1427 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1428 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1429 "Unable to setup xmit queue for VI traffic\n");
4f3acf81 1430 r = -EIO;
ff37e337
S		 1431 goto bad2;
1432 }
1433 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1434 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1435 "Unable to setup xmit queue for VO traffic\n");
4f3acf81 1436 r = -EIO;
ff37e337
S		 1437 goto bad2;
1438 }
1439
1440 /* Initializes the noise floor to a reasonable default value.
1441 * Later on this will be updated during ANI processing. */
1442
17d7904d
S		 1443 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1444 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
ff37e337
S		 1445
1446 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1447 ATH9K_CIPHER_TKIP, NULL)) {
1448 /*
1449 * Whether we should enable h/w TKIP MIC.
1450 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1451 * report WMM capable, so it's always safe to turn on
1452 * TKIP MIC in this case.
1453 */
1454 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1455 0, 1, NULL);
1456 }
1457
1458 /*
1459 * Check whether the separate key cache entries
1460 * are required to handle both tx+rx MIC keys.
1461 * With split mic keys the number of stations is limited
1462 * to 27 otherwise 59.
1463 */
1464 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1465 ATH9K_CIPHER_TKIP, NULL)
1466 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1467 ATH9K_CIPHER_MIC, NULL)
1468 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1469 0, NULL))
17d7904d 1470 sc->splitmic = 1;
ff37e337
S		 1471
1472 /* turn on mcast key search if possible */
1473 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1474 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1475 1, NULL);
1476
17d7904d 1477 sc->config.txpowlimit = ATH_TXPOWER_MAX;
ff37e337
S		 1478
1479 /* 11n Capabilities */
2660b81a 1480 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337
S		 1481 sc->sc_flags |= SC_OP_TXAGGR;
1482 sc->sc_flags |= SC_OP_RXAGGR;
1483 }
1484
2660b81a
S		 1485 sc->tx_chainmask = ah->caps.tx_chainmask;
1486 sc->rx_chainmask = ah->caps.rx_chainmask;
ff37e337
S		 1487
1488 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1489 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337 1490
8ca21f01 1491 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
ba52da58 1492 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
ff37e337 1493
b77f483f 1494 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1495
1496 /* initialize beacon slots */
c52f33d0 1497 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2c3db3d5 1498 sc->beacon.bslot[i] = NULL;
c52f33d0
JM		 1499 sc->beacon.bslot_aphy[i] = NULL;
1500 }
ff37e337 1501
ff37e337
S		 1502 /* setup channels and rates */
1503
5f8e077c 1504 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1505 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1506 sc->rates[IEEE80211_BAND_2GHZ];
1507 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1508 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1509 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337 1510
2660b81a 1511 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
5f8e077c 1512 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1513 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1514 sc->rates[IEEE80211_BAND_5GHZ];
1515 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1516 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1517 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1518 }
1519
1773912b
VT		 1520 if (sc->btcoex_info.btcoex_scheme != ATH_BTCOEX_CFG_NONE) {
1521 r = ath9k_hw_btcoex_init(ah);
1522 if (r)
1523 goto bad2;
1524 }
c97c92d9 1525
ff37e337
S		 1526 return 0;
1527bad2:
1528 /* cleanup tx queues */
1529 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1530 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1531 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337 1532bad:
95fafca2 1533 ath9k_hw_detach(ah);
3ce1b1a9 1534 sc->sc_ah = NULL;
4f3acf81 1535bad_no_ah:
40b130a9 1536 ath9k_exit_debug(sc);
ff37e337 1537
4f3acf81 1538 return r;
ff37e337
S		 1539}
1540
c52f33d0 1541void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
f078f209 1542{
9c84b797
S		 1543 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1544 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1545 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1546 IEEE80211_HW_AMPDU_AGGREGATION |
1547 IEEE80211_HW_SUPPORTS_PS |
eeee1320
S		 1548 IEEE80211_HW_PS_NULLFUNC_STACK |
1549 IEEE80211_HW_SPECTRUM_MGMT;
f078f209 1550
b3bd89ce 1551 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
0ced0e17
JM		 1552 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1553
9c84b797
S		 1554 hw->wiphy->interface_modes =
1555 BIT(NL80211_IFTYPE_AP) |
1556 BIT(NL80211_IFTYPE_STATION) |
9cb5412b
PE		 1557 BIT(NL80211_IFTYPE_ADHOC) |
1558 BIT(NL80211_IFTYPE_MESH_POINT);
f078f209 1559
8feceb67 1560 hw->queues = 4;
e63835b0 1561 hw->max_rates = 4;
171387ef 1562 hw->channel_change_time = 5000;
465ca84d 1563 hw->max_listen_interval = 10;
dd190183
LR		 1564 /* Hardware supports 10 but we use 4 */
1565 hw->max_rate_tries = 4;
528f0c6b 1566 hw->sta_data_size = sizeof(struct ath_node);
17d7904d 1567 hw->vif_data_size = sizeof(struct ath_vif);
f078f209 1568
8feceb67 1569 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1570
c52f33d0
JM		 1571 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1572 &sc->sbands[IEEE80211_BAND_2GHZ];
1573 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1574 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1575 &sc->sbands[IEEE80211_BAND_5GHZ];
1576}
1577
1e40bcfa
LR		 1578/* Device driver core initialization */
1579int ath_init_device(u16 devid, struct ath_softc *sc)
c52f33d0
JM		 1580{
1581 struct ieee80211_hw *hw = sc->hw;
c52f33d0 1582 int error = 0, i;
3a702e49 1583 struct ath_regulatory *reg;
c52f33d0
JM		 1584
1585 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1586
1e40bcfa 1587 error = ath_init_softc(devid, sc);
c52f33d0
JM		 1588 if (error != 0)
1589 return error;
1590
1591 /* get mac address from hardware and set in mac80211 */
1592
1593 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1594
1595 ath_set_hw_capab(sc, hw);
1596
608b88cb 1597 error = ath_regd_init(&sc->common.regulatory, sc->hw->wiphy,
c26c2e57
LR		 1598 ath9k_reg_notifier);
1599 if (error)
1600 return error;
1601
608b88cb 1602 reg = &sc->common.regulatory;
c26c2e57 1603
2660b81a 1604 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1605 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
2660b81a 1606 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
eb2599ca 1607 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1608 }
1609
db93e7b5
SB		 1610 /* initialize tx/rx engine */
1611 error = ath_tx_init(sc, ATH_TXBUF);
1612 if (error != 0)
40b130a9 1613 goto error_attach;
8feceb67 1614
db93e7b5
SB		 1615 error = ath_rx_init(sc, ATH_RXBUF);
1616 if (error != 0)
40b130a9 1617 goto error_attach;
8feceb67 1618
0e2dedf9 1619 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
f98c3bd2
JM		 1620 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1621 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
0e2dedf9 1622
db93e7b5 1623 error = ieee80211_register_hw(hw);
8feceb67 1624
3a702e49 1625 if (!ath_is_world_regd(reg)) {
c02cf373 1626 error = regulatory_hint(hw->wiphy, reg->alpha2);
fe33eb39
LR		 1627 if (error)
1628 goto error_attach;
1629 }
5f8e077c 1630
db93e7b5
SB		 1631 /* Initialize LED control */
1632 ath_init_leds(sc);
8feceb67 1633
3b319aae 1634 ath_start_rfkill_poll(sc);
5f8e077c 1635
8feceb67 1636 return 0;
40b130a9
VT		 1637
1638error_attach:
1639 /* cleanup tx queues */
1640 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1641 if (ATH_TXQ_SETUP(sc, i))
1642 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1643
1644 ath9k_hw_detach(sc->sc_ah);
3ce1b1a9 1645 sc->sc_ah = NULL;
40b130a9
VT		 1646 ath9k_exit_debug(sc);
1647
8feceb67 1648 return error;
f078f209
LR		 1649}
1650
ff37e337
S		 1651int ath_reset(struct ath_softc *sc, bool retry_tx)
1652{
cbe61d8a 1653 struct ath_hw *ah = sc->sc_ah;
030bb495 1654 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1655 int r;
ff37e337
S		 1656
1657 ath9k_hw_set_interrupts(ah, 0);
043a0405 1658 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1659 ath_stoprecv(sc);
1660 ath_flushrecv(sc);
1661
1662 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1663 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 1664 if (r)
ff37e337 1665 DPRINTF(sc, ATH_DBG_FATAL,
6b45784f 1666 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S		 1667 spin_unlock_bh(&sc->sc_resetlock);
1668
1669 if (ath_startrecv(sc) != 0)
04bd4638 1670 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1671
1672 /*
1673 * We may be doing a reset in response to a request
1674 * that changes the channel so update any state that
1675 * might change as a result.
1676 */
ce111bad 1677 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1678
1679 ath_update_txpow(sc);
1680
1681 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1682 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 1683
17d7904d 1684 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 1685
1686 if (retry_tx) {
1687 int i;
1688 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1689 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1690 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1691 ath_txq_schedule(sc, &sc->tx.txq[i]);
1692 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1693 }
1694 }
1695 }
1696
ae8d2858 1697 return r;
ff37e337
S		 1698}
1699
1700/*
1701 * This function will allocate both the DMA descriptor structure, and the
1702 * buffers it contains. These are used to contain the descriptors used
1703 * by the system.
1704*/
1705int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1706 struct list_head *head, const char *name,
1707 int nbuf, int ndesc)
1708{
1709#define DS2PHYS(_dd, _ds) \
1710 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1711#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1712#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1713
1714 struct ath_desc *ds;
1715 struct ath_buf *bf;
1716 int i, bsize, error;
1717
04bd4638
S		 1718 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1719 name, nbuf, ndesc);
ff37e337 1720
b03a9db9 1721 INIT_LIST_HEAD(head);
ff37e337
S		 1722 /* ath_desc must be a multiple of DWORDs */
1723 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1724 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1725 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1726 error = -ENOMEM;
1727 goto fail;
1728 }
1729
ff37e337
S		 1730 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1731
1732 /*
1733 * Need additional DMA memory because we can't use
1734 * descriptors that cross the 4K page boundary. Assume
1735 * one skipped descriptor per 4K page.
1736 */
2660b81a 1737 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
ff37e337
S		 1738 u32 ndesc_skipped =
1739 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1740 u32 dma_len;
1741
1742 while (ndesc_skipped) {
1743 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1744 dd->dd_desc_len += dma_len;
1745
1746 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1747 };
1748 }
1749
1750 /* allocate descriptors */
7da3c55c 1751 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
f0e6ce13 1752 &dd->dd_desc_paddr, GFP_KERNEL);
ff37e337
S		 1753 if (dd->dd_desc == NULL) {
1754 error = -ENOMEM;
1755 goto fail;
1756 }
1757 ds = dd->dd_desc;
04bd4638 1758 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
ae459af1 1759 name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1760 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1761
1762 /* allocate buffers */
1763 bsize = sizeof(struct ath_buf) * nbuf;
f0e6ce13 1764 bf = kzalloc(bsize, GFP_KERNEL);
ff37e337
S		 1765 if (bf == NULL) {
1766 error = -ENOMEM;
1767 goto fail2;
1768 }
ff37e337
S		 1769 dd->dd_bufptr = bf;
1770
ff37e337
S		 1771 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1772 bf->bf_desc = ds;
1773 bf->bf_daddr = DS2PHYS(dd, ds);
1774
2660b81a 1775 if (!(sc->sc_ah->caps.hw_caps &
ff37e337
S		 1776 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1777 /*
1778 * Skip descriptor addresses which can cause 4KB
1779 * boundary crossing (addr + length) with a 32 dword
1780 * descriptor fetch.
1781 */
1782 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1783 ASSERT((caddr_t) bf->bf_desc <
1784 ((caddr_t) dd->dd_desc +
1785 dd->dd_desc_len));
1786
1787 ds += ndesc;
1788 bf->bf_desc = ds;
1789 bf->bf_daddr = DS2PHYS(dd, ds);
1790 }
1791 }
1792 list_add_tail(&bf->list, head);
1793 }
1794 return 0;
1795fail2:
7da3c55c
GJ		 1796 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1797 dd->dd_desc_paddr);
ff37e337
S		 1798fail:
1799 memset(dd, 0, sizeof(*dd));
1800 return error;
1801#undef ATH_DESC_4KB_BOUND_CHECK
1802#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1803#undef DS2PHYS
1804}
1805
1806void ath_descdma_cleanup(struct ath_softc *sc,
1807 struct ath_descdma *dd,
1808 struct list_head *head)
1809{
7da3c55c
GJ		 1810 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1811 dd->dd_desc_paddr);
ff37e337
S		 1812
1813 INIT_LIST_HEAD(head);
1814 kfree(dd->dd_bufptr);
1815 memset(dd, 0, sizeof(*dd));
1816}
1817
1818int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1819{
1820 int qnum;
1821
1822 switch (queue) {
1823 case 0:
b77f483f 1824 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1825 break;
1826 case 1:
b77f483f 1827 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 1828 break;
1829 case 2:
b77f483f 1830 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1831 break;
1832 case 3:
b77f483f 1833 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 1834 break;
1835 default:
b77f483f 1836 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1837 break;
1838 }
1839
1840 return qnum;
1841}
1842
1843int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1844{
1845 int qnum;
1846
1847 switch (queue) {
1848 case ATH9K_WME_AC_VO:
1849 qnum = 0;
1850 break;
1851 case ATH9K_WME_AC_VI:
1852 qnum = 1;
1853 break;
1854 case ATH9K_WME_AC_BE:
1855 qnum = 2;
1856 break;
1857 case ATH9K_WME_AC_BK:
1858 qnum = 3;
1859 break;
1860 default:
1861 qnum = -1;
1862 break;
1863 }
1864
1865 return qnum;
1866}
1867
5f8e077c
LR		 1868/* XXX: Remove me once we don't depend on ath9k_channel for all
1869 * this redundant data */
0e2dedf9
JM		 1870void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1871 struct ath9k_channel *ichan)
5f8e077c 1872{
5f8e077c
LR		 1873 struct ieee80211_channel *chan = hw->conf.channel;
1874 struct ieee80211_conf *conf = &hw->conf;
1875
1876 ichan->channel = chan->center_freq;
1877 ichan->chan = chan;
1878
1879 if (chan->band == IEEE80211_BAND_2GHZ) {
1880 ichan->chanmode = CHANNEL_G;
1881 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1882 } else {
1883 ichan->chanmode = CHANNEL_A;
1884 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1885 }
1886
1887 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1888
1889 if (conf_is_ht(conf)) {
1890 if (conf_is_ht40(conf))
1891 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1892
1893 ichan->chanmode = ath_get_extchanmode(sc, chan,
1894 conf->channel_type);
1895 }
1896}
1897
ff37e337
S		 1898/**********************/
1899/* mac80211 callbacks */
1900/**********************/
1901
8feceb67 1902static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1903{
bce048d7
JM		 1904 struct ath_wiphy *aphy = hw->priv;
1905 struct ath_softc *sc = aphy->sc;
8feceb67 1906 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1907 struct ath9k_channel *init_channel;
82880a7c 1908 int r;
f078f209 1909
04bd4638
S		 1910 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1911 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1912
141b38b6
S		 1913 mutex_lock(&sc->mutex);
1914
9580a222
JM		 1915 if (ath9k_wiphy_started(sc)) {
1916 if (sc->chan_idx == curchan->hw_value) {
1917 /*
1918 * Already on the operational channel, the new wiphy
1919 * can be marked active.
1920 */
1921 aphy->state = ATH_WIPHY_ACTIVE;
1922 ieee80211_wake_queues(hw);
1923 } else {
1924 /*
1925 * Another wiphy is on another channel, start the new
1926 * wiphy in paused state.
1927 */
1928 aphy->state = ATH_WIPHY_PAUSED;
1929 ieee80211_stop_queues(hw);
1930 }
1931 mutex_unlock(&sc->mutex);
1932 return 0;
1933 }
1934 aphy->state = ATH_WIPHY_ACTIVE;
1935
8feceb67 1936 /* setup initial channel */
f078f209 1937
82880a7c 1938 sc->chan_idx = curchan->hw_value;
f078f209 1939
82880a7c 1940 init_channel = ath_get_curchannel(sc, hw);
ff37e337
S		 1941
1942 /* Reset SERDES registers */
1943 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1944
1945 /*
1946 * The basic interface to setting the hardware in a good
1947 * state is ``reset''. On return the hardware is known to
1948 * be powered up and with interrupts disabled. This must
1949 * be followed by initialization of the appropriate bits
1950 * and then setup of the interrupt mask.
1951 */
1952 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1953 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1954 if (r) {
ff37e337 1955 DPRINTF(sc, ATH_DBG_FATAL,
6b45784f 1956 "Unable to reset hardware; reset status %d "
ae8d2858
LR		 1957 "(freq %u MHz)\n", r,
1958 curchan->center_freq);
ff37e337 1959 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 1960 goto mutex_unlock;
ff37e337
S		 1961 }
1962 spin_unlock_bh(&sc->sc_resetlock);
1963
1964 /*
1965 * This is needed only to setup initial state
1966 * but it's best done after a reset.
1967 */
1968 ath_update_txpow(sc);
8feceb67 1969
ff37e337
S		 1970 /*
1971 * Setup the hardware after reset:
1972 * The receive engine is set going.
1973 * Frame transmit is handled entirely
1974 * in the frame output path; there's nothing to do
1975 * here except setup the interrupt mask.
1976 */
1977 if (ath_startrecv(sc) != 0) {
1ffb0610 1978 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
141b38b6
S		 1979 r = -EIO;
1980 goto mutex_unlock;
f078f209 1981 }
8feceb67 1982
ff37e337 1983 /* Setup our intr mask. */
17d7904d 1984 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S		 1985 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1986 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1987
2660b81a 1988 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 1989 sc->imask |= ATH9K_INT_GTT;
ff37e337 1990
2660b81a 1991 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 1992 sc->imask |= ATH9K_INT_CST;
ff37e337 1993
ce111bad 1994 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1995
1996 sc->sc_flags &= ~SC_OP_INVALID;
1997
1998 /* Disable BMISS interrupt when we're not associated */
17d7904d
S		 1999 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2000 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337 2001
bce048d7 2002 ieee80211_wake_queues(hw);
ff37e337 2003
42935eca 2004 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
164ace38 2005
1773912b
VT		 2006 if ((sc->btcoex_info.btcoex_scheme != ATH_BTCOEX_CFG_NONE) &&
2007 !(sc->sc_flags & SC_OP_BTCOEX_ENABLED)) {
2008 ath_btcoex_set_weight(&sc->btcoex_info, AR_BT_COEX_WGHT,
2009 AR_STOMP_LOW_WLAN_WGHT);
f985ad12
VT		 2010 ath9k_hw_btcoex_enable(sc->sc_ah);
2011
1773912b
VT		 2012 if (sc->btcoex_info.btcoex_scheme == ATH_BTCOEX_CFG_3WIRE)
2013 ath_btcoex_timer_resume(sc, &sc->btcoex_info);
2014 }
2015
141b38b6
S		 2016mutex_unlock:
2017 mutex_unlock(&sc->mutex);
2018
ae8d2858 2019 return r;
f078f209
LR		 2020}
2021
8feceb67
VT		 2022static int ath9k_tx(struct ieee80211_hw *hw,
2023 struct sk_buff *skb)
f078f209 2024{
528f0c6b 2025 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM		 2026 struct ath_wiphy *aphy = hw->priv;
2027 struct ath_softc *sc = aphy->sc;
528f0c6b 2028 struct ath_tx_control txctl;
8feceb67 2029 int hdrlen, padsize;
528f0c6b 2030
8089cc47 2031 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
ee166a0e
JM		 2032 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2033 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2034 goto exit;
2035 }
2036
96148326 2037 if (sc->ps_enabled) {
dc8c4585
JM		 2038 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2039 /*
2040 * mac80211 does not set PM field for normal data frames, so we
2041 * need to update that based on the current PS mode.
2042 */
2043 if (ieee80211_is_data(hdr->frame_control) &&
2044 !ieee80211_is_nullfunc(hdr->frame_control) &&
2045 !ieee80211_has_pm(hdr->frame_control)) {
2046 DPRINTF(sc, ATH_DBG_PS, "Add PM=1 for a TX frame "
2047 "while in PS mode\n");
2048 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2049 }
2050 }
2051
9a23f9ca
JM		 2052 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2053 /*
2054 * We are using PS-Poll and mac80211 can request TX while in
2055 * power save mode. Need to wake up hardware for the TX to be
2056 * completed and if needed, also for RX of buffered frames.
2057 */
2058 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2059 ath9k_ps_wakeup(sc);
2060 ath9k_hw_setrxabort(sc->sc_ah, 0);
2061 if (ieee80211_is_pspoll(hdr->frame_control)) {
2062 DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a "
2063 "buffered frame\n");
2064 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2065 } else {
2066 DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n");
2067 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2068 }
2069 /*
2070 * The actual restore operation will happen only after
2071 * the sc_flags bit is cleared. We are just dropping
2072 * the ps_usecount here.
2073 */
2074 ath9k_ps_restore(sc);
2075 }
2076
528f0c6b 2077 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2078
8feceb67
VT		 2079 /*
2080 * As a temporary workaround, assign seq# here; this will likely need
2081 * to be cleaned up to work better with Beacon transmission and virtual
2082 * BSSes.
2083 */
2084 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2085 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2086 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2087 sc->tx.seq_no += 0x10;
8feceb67 2088 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2089 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2090 }
f078f209 2091
8feceb67
VT		 2092 /* Add the padding after the header if this is not already done */
2093 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2094 if (hdrlen & 3) {
2095 padsize = hdrlen % 4;
2096 if (skb_headroom(skb) < padsize)
2097 return -1;
2098 skb_push(skb, padsize);
2099 memmove(skb->data, skb->data + padsize, hdrlen);
2100 }
2101
528f0c6b
S		 2102 /* Check if a tx queue is available */
2103
2104 txctl.txq = ath_test_get_txq(sc, skb);
2105 if (!txctl.txq)
2106 goto exit;
2107
04bd4638 2108 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2109
c52f33d0 2110 if (ath_tx_start(hw, skb, &txctl) != 0) {
04bd4638 2111 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2112 goto exit;
8feceb67
VT		 2113 }
2114
528f0c6b
S		 2115 return 0;
2116exit:
2117 dev_kfree_skb_any(skb);
8feceb67 2118 return 0;
f078f209
LR		 2119}
2120
8feceb67 2121static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 2122{
bce048d7
JM		 2123 struct ath_wiphy *aphy = hw->priv;
2124 struct ath_softc *sc = aphy->sc;
f078f209 2125
4c483817
S		 2126 mutex_lock(&sc->mutex);
2127
9580a222
JM		 2128 aphy->state = ATH_WIPHY_INACTIVE;
2129
c94dbff7
LR		 2130 cancel_delayed_work_sync(&sc->ath_led_blink_work);
2131 cancel_delayed_work_sync(&sc->tx_complete_work);
2132
2133 if (!sc->num_sec_wiphy) {
2134 cancel_delayed_work_sync(&sc->wiphy_work);
2135 cancel_work_sync(&sc->chan_work);
2136 }
2137
9c84b797 2138 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 2139 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
4c483817 2140 mutex_unlock(&sc->mutex);
9c84b797
S		 2141 return;
2142 }
8feceb67 2143
9580a222
JM		 2144 if (ath9k_wiphy_started(sc)) {
2145 mutex_unlock(&sc->mutex);
2146 return; /* another wiphy still in use */
2147 }
2148
1773912b
VT		 2149 if (sc->sc_flags & SC_OP_BTCOEX_ENABLED) {
2150 ath9k_hw_btcoex_disable(sc->sc_ah);
2151 if (sc->btcoex_info.btcoex_scheme == ATH_BTCOEX_CFG_3WIRE)
2152 ath_btcoex_timer_pause(sc, &sc->btcoex_info);
2153 }
2154
ff37e337
S		 2155 /* make sure h/w will not generate any interrupt
2156 * before setting the invalid flag. */
2157 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2158
2159 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2160 ath_drain_all_txq(sc, false);
ff37e337
S		 2161 ath_stoprecv(sc);
2162 ath9k_hw_phy_disable(sc->sc_ah);
2163 } else
b77f483f 2164 sc->rx.rxlink = NULL;
ff37e337 2165
3b319aae 2166 wiphy_rfkill_stop_polling(sc->hw->wiphy);
19d337df 2167
ff37e337
S		 2168 /* disable HAL and put h/w to sleep */
2169 ath9k_hw_disable(sc->sc_ah);
2170 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
eff563cf 2171 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
ff37e337
S		 2172
2173 sc->sc_flags |= SC_OP_INVALID;
500c064d 2174
141b38b6
S		 2175 mutex_unlock(&sc->mutex);
2176
04bd4638 2177 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2178}
2179
8feceb67
VT		 2180static int ath9k_add_interface(struct ieee80211_hw *hw,
2181 struct ieee80211_if_init_conf *conf)
f078f209 2182{
bce048d7
JM		 2183 struct ath_wiphy *aphy = hw->priv;
2184 struct ath_softc *sc = aphy->sc;
17d7904d 2185 struct ath_vif *avp = (void *)conf->vif->drv_priv;
d97809db 2186 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 2187 int ret = 0;
8feceb67 2188
141b38b6
S		 2189 mutex_lock(&sc->mutex);
2190
8ca21f01
JM		 2191 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2192 sc->nvifs > 0) {
2193 ret = -ENOBUFS;
2194 goto out;
2195 }
2196
8feceb67 2197 switch (conf->type) {
05c914fe 2198 case NL80211_IFTYPE_STATION:
d97809db 2199 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2200 break;
05c914fe 2201 case NL80211_IFTYPE_ADHOC:
05c914fe 2202 case NL80211_IFTYPE_AP:
9cb5412b 2203 case NL80211_IFTYPE_MESH_POINT:
2c3db3d5
JM		 2204 if (sc->nbcnvifs >= ATH_BCBUF) {
2205 ret = -ENOBUFS;
2206 goto out;
2207 }
9cb5412b 2208 ic_opmode = conf->type;
f078f209
LR		 2209 break;
2210 default:
2211 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2212 "Interface type %d not yet supported\n", conf->type);
2c3db3d5
JM		 2213 ret = -EOPNOTSUPP;
2214 goto out;
f078f209
LR		 2215 }
2216
17d7904d 2217 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 2218
17d7904d 2219 /* Set the VIF opmode */
5640b08e
S		 2220 avp->av_opmode = ic_opmode;
2221 avp->av_bslot = -1;
2222
2c3db3d5 2223 sc->nvifs++;
8ca21f01
JM		 2224
2225 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2226 ath9k_set_bssid_mask(hw);
2227
2c3db3d5
JM		 2228 if (sc->nvifs > 1)
2229 goto out; /* skip global settings for secondary vif */
2230
b238e90e 2231 if (ic_opmode == NL80211_IFTYPE_AP) {
5640b08e 2232 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
b238e90e
S		 2233 sc->sc_flags |= SC_OP_TSF_RESET;
2234 }
5640b08e 2235
5640b08e 2236 /* Set the device opmode */
2660b81a 2237 sc->sc_ah->opmode = ic_opmode;
5640b08e 2238
4e30ffa2
VN		 2239 /*
2240 * Enable MIB interrupts when there are hardware phy counters.
2241 * Note we only do this (at the moment) for station mode.
2242 */
4af9cf4f 2243 if ((conf->type == NL80211_IFTYPE_STATION) ||
9cb5412b
PE		 2244 (conf->type == NL80211_IFTYPE_ADHOC) ||
2245 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
1aa8e847 2246 sc->imask |= ATH9K_INT_MIB;
4af9cf4f
S		 2247 sc->imask |= ATH9K_INT_TSFOOR;
2248 }
2249
17d7904d 2250 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 2251
f38faa31
SB		 2252 if (conf->type == NL80211_IFTYPE_AP ||
2253 conf->type == NL80211_IFTYPE_ADHOC ||
2254 conf->type == NL80211_IFTYPE_MONITOR)
415f738e 2255 ath_start_ani(sc);
6f255425 2256
2c3db3d5 2257out:
141b38b6 2258 mutex_unlock(&sc->mutex);
2c3db3d5 2259 return ret;
f078f209
LR		 2260}
2261
8feceb67
VT		 2262static void ath9k_remove_interface(struct ieee80211_hw *hw,
2263 struct ieee80211_if_init_conf *conf)
f078f209 2264{
bce048d7
JM		 2265 struct ath_wiphy *aphy = hw->priv;
2266 struct ath_softc *sc = aphy->sc;
17d7904d 2267 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2c3db3d5 2268 int i;
f078f209 2269
04bd4638 2270 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2271
141b38b6
S		 2272 mutex_lock(&sc->mutex);
2273
6f255425 2274 /* Stop ANI */
17d7904d 2275 del_timer_sync(&sc->ani.timer);
580f0b8a 2276
8feceb67 2277 /* Reclaim beacon resources */
9cb5412b
PE		 2278 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2279 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2280 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
b77f483f 2281 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2282 ath_beacon_return(sc, avp);
580f0b8a 2283 }
f078f209 2284
8feceb67 2285 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2286
2c3db3d5
JM		 2287 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2288 if (sc->beacon.bslot[i] == conf->vif) {
2289 printk(KERN_DEBUG "%s: vif had allocated beacon "
2290 "slot\n", __func__);
2291 sc->beacon.bslot[i] = NULL;
c52f33d0 2292 sc->beacon.bslot_aphy[i] = NULL;
2c3db3d5
JM		 2293 }
2294 }
2295
17d7904d 2296 sc->nvifs--;
141b38b6
S		 2297
2298 mutex_unlock(&sc->mutex);
f078f209
LR		 2299}
2300
e8975581 2301static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2302{
bce048d7
JM		 2303 struct ath_wiphy *aphy = hw->priv;
2304 struct ath_softc *sc = aphy->sc;
e8975581 2305 struct ieee80211_conf *conf = &hw->conf;
8782b41d 2306 struct ath_hw *ah = sc->sc_ah;
64839170 2307 bool all_wiphys_idle = false, disable_radio = false;
f078f209 2308
aa33de09 2309 mutex_lock(&sc->mutex);
141b38b6 2310
64839170
LR		 2311 /* Leave this as the first check */
2312 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
2313
2314 spin_lock_bh(&sc->wiphy_lock);
2315 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
2316 spin_unlock_bh(&sc->wiphy_lock);
2317
2318 if (conf->flags & IEEE80211_CONF_IDLE){
2319 if (all_wiphys_idle)
2320 disable_radio = true;
2321 }
2322 else if (all_wiphys_idle) {
2323 ath_radio_enable(sc);
2324 DPRINTF(sc, ATH_DBG_CONFIG,
2325 "not-idle: enabling radio\n");
2326 }
2327 }
2328
3cbb5dd7
VN		 2329 if (changed & IEEE80211_CONF_CHANGE_PS) {
2330 if (conf->flags & IEEE80211_CONF_PS) {
8782b41d
VN		 2331 if (!(ah->caps.hw_caps &
2332 ATH9K_HW_CAP_AUTOSLEEP)) {
2333 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2334 sc->imask |= ATH9K_INT_TIM_TIMER;
2335 ath9k_hw_set_interrupts(sc->sc_ah,
2336 sc->imask);
2337 }
2338 ath9k_hw_setrxabort(sc->sc_ah, 1);
3cbb5dd7 2339 }
96148326 2340 sc->ps_enabled = true;
3cbb5dd7 2341 } else {
96148326 2342 sc->ps_enabled = false;
3cbb5dd7 2343 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8782b41d
VN		 2344 if (!(ah->caps.hw_caps &
2345 ATH9K_HW_CAP_AUTOSLEEP)) {
2346 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca
JM		 2347 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2348 SC_OP_WAIT_FOR_CAB |
2349 SC_OP_WAIT_FOR_PSPOLL_DATA |
2350 SC_OP_WAIT_FOR_TX_ACK);
8782b41d
VN		 2351 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2352 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2353 ath9k_hw_set_interrupts(sc->sc_ah,
2354 sc->imask);
2355 }
3cbb5dd7
VN		 2356 }
2357 }
2358 }
2359
4797938c 2360 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2361 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2362 int pos = curchan->hw_value;
ae5eb026 2363
0e2dedf9
JM		 2364 aphy->chan_idx = pos;
2365 aphy->chan_is_ht = conf_is_ht(conf);
2366
8089cc47
JM		 2367 if (aphy->state == ATH_WIPHY_SCAN ||
2368 aphy->state == ATH_WIPHY_ACTIVE)
2369 ath9k_wiphy_pause_all_forced(sc, aphy);
2370 else {
2371 /*
2372 * Do not change operational channel based on a paused
2373 * wiphy changes.
2374 */
2375 goto skip_chan_change;
2376 }
0e2dedf9 2377
04bd4638
S		 2378 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2379 curchan->center_freq);
f078f209 2380
5f8e077c 2381 /* XXX: remove me eventualy */
0e2dedf9 2382 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 2383
ecf70441 2384 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2385
0e2dedf9 2386 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
04bd4638 2387 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2388 mutex_unlock(&sc->mutex);
e11602b7
S		 2389 return -EINVAL;
2390 }
094d05dc 2391 }
f078f209 2392
8089cc47 2393skip_chan_change:
5c020dc6 2394 if (changed & IEEE80211_CONF_CHANGE_POWER)
17d7904d 2395 sc->config.txpowlimit = 2 * conf->power_level;
f078f209 2396
64839170
LR		 2397 if (disable_radio) {
2398 DPRINTF(sc, ATH_DBG_CONFIG, "idle: disabling radio\n");
2399 ath_radio_disable(sc);
2400 }
2401
aa33de09 2402 mutex_unlock(&sc->mutex);
141b38b6 2403
f078f209
LR		 2404 return 0;
2405}
2406
8feceb67
VT		 2407#define SUPPORTED_FILTERS \
2408 (FIF_PROMISC_IN_BSS | \
2409 FIF_ALLMULTI | \
2410 FIF_CONTROL | \
af6a3fc7 2411 FIF_PSPOLL | \
8feceb67
VT		 2412 FIF_OTHER_BSS | \
2413 FIF_BCN_PRBRESP_PROMISC | \
2414 FIF_FCSFAIL)
c83be688 2415
8feceb67
VT		 2416/* FIXME: sc->sc_full_reset ? */
2417static void ath9k_configure_filter(struct ieee80211_hw *hw,
2418 unsigned int changed_flags,
2419 unsigned int *total_flags,
3ac64bee 2420 u64 multicast)
8feceb67 2421{
bce048d7
JM		 2422 struct ath_wiphy *aphy = hw->priv;
2423 struct ath_softc *sc = aphy->sc;
8feceb67 2424 u32 rfilt;
f078f209 2425
8feceb67
VT		 2426 changed_flags &= SUPPORTED_FILTERS;
2427 *total_flags &= SUPPORTED_FILTERS;
f078f209 2428
b77f483f 2429 sc->rx.rxfilter = *total_flags;
aa68aeaa 2430 ath9k_ps_wakeup(sc);
8feceb67
VT		 2431 rfilt = ath_calcrxfilter(sc);
2432 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 2433 ath9k_ps_restore(sc);
f078f209 2434
b77f483f 2435 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
8feceb67 2436}
f078f209 2437
8feceb67
VT		 2438static void ath9k_sta_notify(struct ieee80211_hw *hw,
2439 struct ieee80211_vif *vif,
2440 enum sta_notify_cmd cmd,
17741cdc 2441 struct ieee80211_sta *sta)
8feceb67 2442{
bce048d7
JM		 2443 struct ath_wiphy *aphy = hw->priv;
2444 struct ath_softc *sc = aphy->sc;
f078f209 2445
8feceb67
VT		 2446 switch (cmd) {
2447 case STA_NOTIFY_ADD:
5640b08e 2448 ath_node_attach(sc, sta);
8feceb67
VT		 2449 break;
2450 case STA_NOTIFY_REMOVE:
b5aa9bf9 2451 ath_node_detach(sc, sta);
8feceb67
VT		 2452 break;
2453 default:
2454 break;
2455 }
f078f209
LR		 2456}
2457
141b38b6 2458static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 2459 const struct ieee80211_tx_queue_params *params)
f078f209 2460{
bce048d7
JM		 2461 struct ath_wiphy *aphy = hw->priv;
2462 struct ath_softc *sc = aphy->sc;
8feceb67
VT		 2463 struct ath9k_tx_queue_info qi;
2464 int ret = 0, qnum;
f078f209 2465
8feceb67
VT		 2466 if (queue >= WME_NUM_AC)
2467 return 0;
f078f209 2468
141b38b6
S		 2469 mutex_lock(&sc->mutex);
2470
1ffb0610
S		 2471 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2472
8feceb67
VT		 2473 qi.tqi_aifs = params->aifs;
2474 qi.tqi_cwmin = params->cw_min;
2475 qi.tqi_cwmax = params->cw_max;
2476 qi.tqi_burstTime = params->txop;
2477 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2478
8feceb67 2479 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2480 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2481 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2482 queue, qnum, params->aifs, params->cw_min,
2483 params->cw_max, params->txop);
f078f209 2484
8feceb67
VT		 2485 ret = ath_txq_update(sc, qnum, &qi);
2486 if (ret)
04bd4638 2487 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2488
141b38b6
S		 2489 mutex_unlock(&sc->mutex);
2490
8feceb67
VT		 2491 return ret;
2492}
f078f209 2493
8feceb67
VT		 2494static int ath9k_set_key(struct ieee80211_hw *hw,
2495 enum set_key_cmd cmd,
dc822b5d
JB		 2496 struct ieee80211_vif *vif,
2497 struct ieee80211_sta *sta,
8feceb67
VT		 2498 struct ieee80211_key_conf *key)
2499{
bce048d7
JM		 2500 struct ath_wiphy *aphy = hw->priv;
2501 struct ath_softc *sc = aphy->sc;
8feceb67 2502 int ret = 0;
f078f209 2503
b3bd89ce
JM		 2504 if (modparam_nohwcrypt)
2505 return -ENOSPC;
2506
141b38b6 2507 mutex_lock(&sc->mutex);
3cbb5dd7 2508 ath9k_ps_wakeup(sc);
d8baa939 2509 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 2510
8feceb67
VT		 2511 switch (cmd) {
2512 case SET_KEY:
3f53dd64 2513 ret = ath_key_config(sc, vif, sta, key);
6ace2891
JM		 2514 if (ret >= 0) {
2515 key->hw_key_idx = ret;
8feceb67
VT		 2516 /* push IV and Michael MIC generation to stack */
2517 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2518 if (key->alg == ALG_TKIP)
2519 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2520 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2521 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2522 ret = 0;
8feceb67
VT		 2523 }
2524 break;
2525 case DISABLE_KEY:
2526 ath_key_delete(sc, key);
8feceb67
VT		 2527 break;
2528 default:
2529 ret = -EINVAL;
2530 }
f078f209 2531
3cbb5dd7 2532 ath9k_ps_restore(sc);
141b38b6
S		 2533 mutex_unlock(&sc->mutex);
2534
8feceb67
VT		 2535 return ret;
2536}
f078f209 2537
8feceb67
VT		 2538static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2539 struct ieee80211_vif *vif,
2540 struct ieee80211_bss_conf *bss_conf,
2541 u32 changed)
2542{
bce048d7
JM		 2543 struct ath_wiphy *aphy = hw->priv;
2544 struct ath_softc *sc = aphy->sc;
2d0ddec5
JB		 2545 struct ath_hw *ah = sc->sc_ah;
2546 struct ath_vif *avp = (void *)vif->drv_priv;
2547 u32 rfilt = 0;
2548 int error, i;
f078f209 2549
141b38b6
S		 2550 mutex_lock(&sc->mutex);
2551
2d0ddec5
JB		 2552 /*
2553 * TODO: Need to decide which hw opmode to use for
2554 * multi-interface cases
2555 * XXX: This belongs into add_interface!
2556 */
2557 if (vif->type == NL80211_IFTYPE_AP &&
2558 ah->opmode != NL80211_IFTYPE_AP) {
2559 ah->opmode = NL80211_IFTYPE_STATION;
2560 ath9k_hw_setopmode(ah);
2561 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2562 sc->curaid = 0;
2563 ath9k_hw_write_associd(sc);
2564 /* Request full reset to get hw opmode changed properly */
2565 sc->sc_flags |= SC_OP_FULL_RESET;
2566 }
2567
2568 if ((changed & BSS_CHANGED_BSSID) &&
2569 !is_zero_ether_addr(bss_conf->bssid)) {
2570 switch (vif->type) {
2571 case NL80211_IFTYPE_STATION:
2572 case NL80211_IFTYPE_ADHOC:
2573 case NL80211_IFTYPE_MESH_POINT:
2574 /* Set BSSID */
2575 memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2576 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2577 sc->curaid = 0;
2578 ath9k_hw_write_associd(sc);
2579
2580 /* Set aggregation protection mode parameters */
2581 sc->config.ath_aggr_prot = 0;
2582
2583 DPRINTF(sc, ATH_DBG_CONFIG,
2584 "RX filter 0x%x bssid %pM aid 0x%x\n",
2585 rfilt, sc->curbssid, sc->curaid);
2586
2587 /* need to reconfigure the beacon */
2588 sc->sc_flags &= ~SC_OP_BEACONS ;
2589
2590 break;
2591 default:
2592 break;
2593 }
2594 }
2595
2596 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2597 (vif->type == NL80211_IFTYPE_AP) ||
2598 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2599 if ((changed & BSS_CHANGED_BEACON) ||
2600 (changed & BSS_CHANGED_BEACON_ENABLED &&
2601 bss_conf->enable_beacon)) {
2602 /*
2603 * Allocate and setup the beacon frame.
2604 *
2605 * Stop any previous beacon DMA. This may be
2606 * necessary, for example, when an ibss merge
2607 * causes reconfiguration; we may be called
2608 * with beacon transmission active.
2609 */
2610 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2611
2612 error = ath_beacon_alloc(aphy, vif);
2613 if (!error)
2614 ath_beacon_config(sc, vif);
2615 }
2616 }
2617
2618 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2619 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2620 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2621 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2622 ath9k_hw_keysetmac(sc->sc_ah,
2623 (u16)i,
2624 sc->curbssid);
2625 }
2626
2627 /* Only legacy IBSS for now */
2628 if (vif->type == NL80211_IFTYPE_ADHOC)
2629 ath_update_chainmask(sc, 0);
2630
8feceb67 2631 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2632 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2633 bss_conf->use_short_preamble);
2634 if (bss_conf->use_short_preamble)
2635 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2636 else
2637 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2638 }
f078f209 2639
8feceb67 2640 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2641 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2642 bss_conf->use_cts_prot);
2643 if (bss_conf->use_cts_prot &&
2644 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2645 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2646 else
2647 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2648 }
f078f209 2649
8feceb67 2650 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2651 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2652 bss_conf->assoc);
5640b08e 2653 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 2654 }
141b38b6 2655
57c4d7b4
JB		 2656 /*
2657 * The HW TSF has to be reset when the beacon interval changes.
2658 * We set the flag here, and ath_beacon_config_ap() would take this
2659 * into account when it gets called through the subsequent
2660 * config_interface() call - with IFCC_BEACON in the changed field.
2661 */
2662
2663 if (changed & BSS_CHANGED_BEACON_INT) {
2664 sc->sc_flags |= SC_OP_TSF_RESET;
2665 sc->beacon_interval = bss_conf->beacon_int;
2666 }
2667
141b38b6 2668 mutex_unlock(&sc->mutex);
8feceb67 2669}
f078f209 2670
8feceb67
VT		 2671static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2672{
2673 u64 tsf;
bce048d7
JM		 2674 struct ath_wiphy *aphy = hw->priv;
2675 struct ath_softc *sc = aphy->sc;
f078f209 2676
141b38b6
S		 2677 mutex_lock(&sc->mutex);
2678 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2679 mutex_unlock(&sc->mutex);
f078f209 2680
8feceb67
VT		 2681 return tsf;
2682}
f078f209 2683
3b5d665b
AF		 2684static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2685{
bce048d7
JM		 2686 struct ath_wiphy *aphy = hw->priv;
2687 struct ath_softc *sc = aphy->sc;
3b5d665b 2688
141b38b6
S		 2689 mutex_lock(&sc->mutex);
2690 ath9k_hw_settsf64(sc->sc_ah, tsf);
2691 mutex_unlock(&sc->mutex);
3b5d665b
AF		 2692}
2693
8feceb67
VT		 2694static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2695{
bce048d7
JM		 2696 struct ath_wiphy *aphy = hw->priv;
2697 struct ath_softc *sc = aphy->sc;
c83be688 2698
141b38b6
S		 2699 mutex_lock(&sc->mutex);
2700 ath9k_hw_reset_tsf(sc->sc_ah);
2701 mutex_unlock(&sc->mutex);
8feceb67 2702}
f078f209 2703
8feceb67 2704static int ath9k_ampdu_action(struct ieee80211_hw *hw,
141b38b6
S		 2705 enum ieee80211_ampdu_mlme_action action,
2706 struct ieee80211_sta *sta,
2707 u16 tid, u16 *ssn)
8feceb67 2708{
bce048d7
JM		 2709 struct ath_wiphy *aphy = hw->priv;
2710 struct ath_softc *sc = aphy->sc;
8feceb67 2711 int ret = 0;
f078f209 2712
8feceb67
VT		 2713 switch (action) {
2714 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2715 if (!(sc->sc_flags & SC_OP_RXAGGR))
2716 ret = -ENOTSUPP;
8feceb67
VT		 2717 break;
2718 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2719 break;
2720 case IEEE80211_AMPDU_TX_START:
f83da965
S		 2721 ath_tx_aggr_start(sc, sta, tid, ssn);
2722 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2723 break;
2724 case IEEE80211_AMPDU_TX_STOP:
f83da965 2725 ath_tx_aggr_stop(sc, sta, tid);
17741cdc 2726 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2727 break;
b1720231 2728 case IEEE80211_AMPDU_TX_OPERATIONAL:
8469cdef
S		 2729 ath_tx_aggr_resume(sc, sta, tid);
2730 break;
8feceb67 2731 default:
04bd4638 2732 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2733 }
2734
2735 return ret;
f078f209
LR		 2736}
2737
0c98de65
S		 2738static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2739{
bce048d7
JM		 2740 struct ath_wiphy *aphy = hw->priv;
2741 struct ath_softc *sc = aphy->sc;
0c98de65 2742
3d832611 2743 mutex_lock(&sc->mutex);
8089cc47
JM		 2744 if (ath9k_wiphy_scanning(sc)) {
2745 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2746 "same time\n");
2747 /*
2748 * Do not allow the concurrent scanning state for now. This
2749 * could be improved with scanning control moved into ath9k.
2750 */
3d832611 2751 mutex_unlock(&sc->mutex);
8089cc47
JM		 2752 return;
2753 }
2754
2755 aphy->state = ATH_WIPHY_SCAN;
2756 ath9k_wiphy_pause_all_forced(sc, aphy);
2757
e5f0921a 2758 spin_lock_bh(&sc->ani_lock);
0c98de65 2759 sc->sc_flags |= SC_OP_SCANNING;
e5f0921a 2760 spin_unlock_bh(&sc->ani_lock);
3d832611 2761 mutex_unlock(&sc->mutex);
0c98de65
S		 2762}
2763
2764static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2765{
bce048d7
JM		 2766 struct ath_wiphy *aphy = hw->priv;
2767 struct ath_softc *sc = aphy->sc;
0c98de65 2768
3d832611 2769 mutex_lock(&sc->mutex);
e5f0921a 2770 spin_lock_bh(&sc->ani_lock);
8089cc47 2771 aphy->state = ATH_WIPHY_ACTIVE;
0c98de65 2772 sc->sc_flags &= ~SC_OP_SCANNING;
9c07a777 2773 sc->sc_flags |= SC_OP_FULL_RESET;
e5f0921a 2774 spin_unlock_bh(&sc->ani_lock);
3d832611 2775 mutex_unlock(&sc->mutex);
0c98de65
S		 2776}
2777
6baff7f9 2778struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2779 .tx = ath9k_tx,
2780 .start = ath9k_start,
2781 .stop = ath9k_stop,
2782 .add_interface = ath9k_add_interface,
2783 .remove_interface = ath9k_remove_interface,
2784 .config = ath9k_config,
8feceb67 2785 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2786 .sta_notify = ath9k_sta_notify,
2787 .conf_tx = ath9k_conf_tx,
8feceb67 2788 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2789 .set_key = ath9k_set_key,
8feceb67 2790 .get_tsf = ath9k_get_tsf,
3b5d665b 2791 .set_tsf = ath9k_set_tsf,
8feceb67 2792 .reset_tsf = ath9k_reset_tsf,
4233df6b 2793 .ampdu_action = ath9k_ampdu_action,
0c98de65
S		 2794 .sw_scan_start = ath9k_sw_scan_start,
2795 .sw_scan_complete = ath9k_sw_scan_complete,
3b319aae 2796 .rfkill_poll = ath9k_rfkill_poll_state,
8feceb67
VT		 2797};
2798
392dff83
BP		 2799static struct {
2800 u32 version;
2801 const char * name;
2802} ath_mac_bb_names[] = {
2803 { AR_SREV_VERSION_5416_PCI, "5416" },
2804 { AR_SREV_VERSION_5416_PCIE, "5418" },
2805 { AR_SREV_VERSION_9100, "9100" },
2806 { AR_SREV_VERSION_9160, "9160" },
2807 { AR_SREV_VERSION_9280, "9280" },
ac88b6ec
VN		 2808 { AR_SREV_VERSION_9285, "9285" },
2809 { AR_SREV_VERSION_9287, "9287" }
392dff83
BP		 2810};
2811
2812static struct {
2813 u16 version;
2814 const char * name;
2815} ath_rf_names[] = {
2816 { 0, "5133" },
2817 { AR_RAD5133_SREV_MAJOR, "5133" },
2818 { AR_RAD5122_SREV_MAJOR, "5122" },
2819 { AR_RAD2133_SREV_MAJOR, "2133" },
2820 { AR_RAD2122_SREV_MAJOR, "2122" }
2821};
2822
2823/*
2824 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2825 */
6baff7f9 2826const char *
392dff83
BP		 2827ath_mac_bb_name(u32 mac_bb_version)
2828{
2829 int i;
2830
2831 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2832 if (ath_mac_bb_names[i].version == mac_bb_version) {
2833 return ath_mac_bb_names[i].name;
2834 }
2835 }
2836
2837 return "????";
2838}
2839
2840/*
2841 * Return the RF name. "????" is returned if the RF is unknown.
2842 */
6baff7f9 2843const char *
392dff83
BP		 2844ath_rf_name(u16 rf_version)
2845{
2846 int i;
2847
2848 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2849 if (ath_rf_names[i].version == rf_version) {
2850 return ath_rf_names[i].name;
2851 }
2852 }
2853
2854 return "????";
2855}
2856
6baff7f9 2857static int __init ath9k_init(void)
f078f209 2858{
ca8a8560
VT		 2859 int error;
2860
ca8a8560
VT		 2861 /* Register rate control algorithm */
2862 error = ath_rate_control_register();
2863 if (error != 0) {
2864 printk(KERN_ERR
b51bb3cd
LR		 2865 "ath9k: Unable to register rate control "
2866 "algorithm: %d\n",
ca8a8560 2867 error);
6baff7f9 2868 goto err_out;
ca8a8560
VT		 2869 }
2870
19d8bc22
GJ		 2871 error = ath9k_debug_create_root();
2872 if (error) {
2873 printk(KERN_ERR
2874 "ath9k: Unable to create debugfs root: %d\n",
2875 error);
2876 goto err_rate_unregister;
2877 }
2878
6baff7f9
GJ		 2879 error = ath_pci_init();
2880 if (error < 0) {
f078f209 2881 printk(KERN_ERR
b51bb3cd 2882 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9 2883 error = -ENODEV;
19d8bc22 2884 goto err_remove_root;
f078f209
LR		 2885 }
2886
09329d37
GJ		 2887 error = ath_ahb_init();
2888 if (error < 0) {
2889 error = -ENODEV;
2890 goto err_pci_exit;
2891 }
2892
f078f209 2893 return 0;
6baff7f9 2894
09329d37
GJ		 2895 err_pci_exit:
2896 ath_pci_exit();
2897
19d8bc22
GJ		 2898 err_remove_root:
2899 ath9k_debug_remove_root();
6baff7f9
GJ		 2900 err_rate_unregister:
2901 ath_rate_control_unregister();
2902 err_out:
2903 return error;
f078f209 2904}
6baff7f9 2905module_init(ath9k_init);
f078f209 2906
6baff7f9 2907static void __exit ath9k_exit(void)
f078f209 2908{
09329d37 2909 ath_ahb_exit();
6baff7f9 2910 ath_pci_exit();
19d8bc22 2911 ath9k_debug_remove_root();
ca8a8560 2912 ath_rate_control_unregister();
04bd4638 2913 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 2914}
6baff7f9 2915module_exit(ath9k_exit);
Linux kernel - Deliverables
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