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ath9k: Wake up for TX in mac80211 timeout=0 sleep mode
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
f078f209
LR		 19
20#define ATH_PCI_VERSION "0.1"
21
f078f209
LR		 22static char *dev_info = "ath9k";
23
24MODULE_AUTHOR("Atheros Communications");
25MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27MODULE_LICENSE("Dual BSD/GPL");
28
b3bd89ce
JM		 29static int modparam_nohwcrypt;
30module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
31MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
32
5f8e077c
LR		 33/* We use the hw_value as an index into our private channel structure */
34
35#define CHAN2G(_freq, _idx) { \
36 .center_freq = (_freq), \
37 .hw_value = (_idx), \
38 .max_power = 30, \
39}
40
41#define CHAN5G(_freq, _idx) { \
42 .band = IEEE80211_BAND_5GHZ, \
43 .center_freq = (_freq), \
44 .hw_value = (_idx), \
45 .max_power = 30, \
46}
47
48/* Some 2 GHz radios are actually tunable on 2312-2732
49 * on 5 MHz steps, we support the channels which we know
50 * we have calibration data for all cards though to make
51 * this static */
52static struct ieee80211_channel ath9k_2ghz_chantable[] = {
53 CHAN2G(2412, 0), /* Channel 1 */
54 CHAN2G(2417, 1), /* Channel 2 */
55 CHAN2G(2422, 2), /* Channel 3 */
56 CHAN2G(2427, 3), /* Channel 4 */
57 CHAN2G(2432, 4), /* Channel 5 */
58 CHAN2G(2437, 5), /* Channel 6 */
59 CHAN2G(2442, 6), /* Channel 7 */
60 CHAN2G(2447, 7), /* Channel 8 */
61 CHAN2G(2452, 8), /* Channel 9 */
62 CHAN2G(2457, 9), /* Channel 10 */
63 CHAN2G(2462, 10), /* Channel 11 */
64 CHAN2G(2467, 11), /* Channel 12 */
65 CHAN2G(2472, 12), /* Channel 13 */
66 CHAN2G(2484, 13), /* Channel 14 */
67};
68
69/* Some 5 GHz radios are actually tunable on XXXX-YYYY
70 * on 5 MHz steps, we support the channels which we know
71 * we have calibration data for all cards though to make
72 * this static */
73static struct ieee80211_channel ath9k_5ghz_chantable[] = {
74 /* _We_ call this UNII 1 */
75 CHAN5G(5180, 14), /* Channel 36 */
76 CHAN5G(5200, 15), /* Channel 40 */
77 CHAN5G(5220, 16), /* Channel 44 */
78 CHAN5G(5240, 17), /* Channel 48 */
79 /* _We_ call this UNII 2 */
80 CHAN5G(5260, 18), /* Channel 52 */
81 CHAN5G(5280, 19), /* Channel 56 */
82 CHAN5G(5300, 20), /* Channel 60 */
83 CHAN5G(5320, 21), /* Channel 64 */
84 /* _We_ call this "Middle band" */
85 CHAN5G(5500, 22), /* Channel 100 */
86 CHAN5G(5520, 23), /* Channel 104 */
87 CHAN5G(5540, 24), /* Channel 108 */
88 CHAN5G(5560, 25), /* Channel 112 */
89 CHAN5G(5580, 26), /* Channel 116 */
90 CHAN5G(5600, 27), /* Channel 120 */
91 CHAN5G(5620, 28), /* Channel 124 */
92 CHAN5G(5640, 29), /* Channel 128 */
93 CHAN5G(5660, 30), /* Channel 132 */
94 CHAN5G(5680, 31), /* Channel 136 */
95 CHAN5G(5700, 32), /* Channel 140 */
96 /* _We_ call this UNII 3 */
97 CHAN5G(5745, 33), /* Channel 149 */
98 CHAN5G(5765, 34), /* Channel 153 */
99 CHAN5G(5785, 35), /* Channel 157 */
100 CHAN5G(5805, 36), /* Channel 161 */
101 CHAN5G(5825, 37), /* Channel 165 */
102};
103
ce111bad
LR		 104static void ath_cache_conf_rate(struct ath_softc *sc,
105 struct ieee80211_conf *conf)
ff37e337 106{
030bb495
LR		 107 switch (conf->channel->band) {
108 case IEEE80211_BAND_2GHZ:
109 if (conf_is_ht20(conf))
110 sc->cur_rate_table =
111 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
112 else if (conf_is_ht40_minus(conf))
113 sc->cur_rate_table =
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
115 else if (conf_is_ht40_plus(conf))
116 sc->cur_rate_table =
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 118 else
030bb495
LR		 119 sc->cur_rate_table =
120 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 121 break;
122 case IEEE80211_BAND_5GHZ:
123 if (conf_is_ht20(conf))
124 sc->cur_rate_table =
125 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
126 else if (conf_is_ht40_minus(conf))
127 sc->cur_rate_table =
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
129 else if (conf_is_ht40_plus(conf))
130 sc->cur_rate_table =
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
132 else
96742256
LR		 133 sc->cur_rate_table =
134 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 135 break;
136 default:
ce111bad 137 BUG_ON(1);
030bb495
LR		 138 break;
139 }
ff37e337
S		 140}
141
142static void ath_update_txpow(struct ath_softc *sc)
143{
cbe61d8a 144 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 145 u32 txpow;
146
17d7904d
S		 147 if (sc->curtxpow != sc->config.txpowlimit) {
148 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S		 149 /* read back in case value is clamped */
150 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 151 sc->curtxpow = txpow;
ff37e337
S		 152 }
153}
154
155static u8 parse_mpdudensity(u8 mpdudensity)
156{
157 /*
158 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
159 * 0 for no restriction
160 * 1 for 1/4 us
161 * 2 for 1/2 us
162 * 3 for 1 us
163 * 4 for 2 us
164 * 5 for 4 us
165 * 6 for 8 us
166 * 7 for 16 us
167 */
168 switch (mpdudensity) {
169 case 0:
170 return 0;
171 case 1:
172 case 2:
173 case 3:
174 /* Our lower layer calculations limit our precision to
175 1 microsecond */
176 return 1;
177 case 4:
178 return 2;
179 case 5:
180 return 4;
181 case 6:
182 return 8;
183 case 7:
184 return 16;
185 default:
186 return 0;
187 }
188}
189
190static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
191{
4f0fc7c3 192 const struct ath_rate_table *rate_table = NULL;
ff37e337
S		 193 struct ieee80211_supported_band *sband;
194 struct ieee80211_rate *rate;
195 int i, maxrates;
196
197 switch (band) {
198 case IEEE80211_BAND_2GHZ:
199 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
200 break;
201 case IEEE80211_BAND_5GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
203 break;
204 default:
205 break;
206 }
207
208 if (rate_table == NULL)
209 return;
210
211 sband = &sc->sbands[band];
212 rate = sc->rates[band];
213
214 if (rate_table->rate_cnt > ATH_RATE_MAX)
215 maxrates = ATH_RATE_MAX;
216 else
217 maxrates = rate_table->rate_cnt;
218
219 for (i = 0; i < maxrates; i++) {
220 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
221 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 222 if (rate_table->info[i].short_preamble) {
223 rate[i].hw_value_short = rate_table->info[i].ratecode |
224 rate_table->info[i].short_preamble;
225 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
226 }
ff37e337 227 sband->n_bitrates++;
f46730d1 228
04bd4638
S		 229 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
230 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 231 }
232}
233
ff37e337
S		 234/*
235 * Set/change channels. If the channel is really being changed, it's done
236 * by reseting the chip. To accomplish this we must first cleanup any pending
237 * DMA, then restart stuff.
238*/
0e2dedf9
JM		 239int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
240 struct ath9k_channel *hchan)
ff37e337 241{
cbe61d8a 242 struct ath_hw *ah = sc->sc_ah;
ff37e337 243 bool fastcc = true, stopped;
ae8d2858
LR		 244 struct ieee80211_channel *channel = hw->conf.channel;
245 int r;
ff37e337
S		 246
247 if (sc->sc_flags & SC_OP_INVALID)
248 return -EIO;
249
3cbb5dd7
VN		 250 ath9k_ps_wakeup(sc);
251
c0d7c7af
LR		 252 /*
253 * This is only performed if the channel settings have
254 * actually changed.
255 *
256 * To switch channels clear any pending DMA operations;
257 * wait long enough for the RX fifo to drain, reset the
258 * hardware at the new frequency, and then re-enable
259 * the relevant bits of the h/w.
260 */
261 ath9k_hw_set_interrupts(ah, 0);
043a0405 262 ath_drain_all_txq(sc, false);
c0d7c7af 263 stopped = ath_stoprecv(sc);
ff37e337 264
c0d7c7af
LR		 265 /* XXX: do not flush receive queue here. We don't want
266 * to flush data frames already in queue because of
267 * changing channel. */
ff37e337 268
c0d7c7af
LR		 269 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
270 fastcc = false;
271
272 DPRINTF(sc, ATH_DBG_CONFIG,
273 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
2660b81a 274 sc->sc_ah->curchan->channel,
c0d7c7af 275 channel->center_freq, sc->tx_chan_width);
ff37e337 276
c0d7c7af
LR		 277 spin_lock_bh(&sc->sc_resetlock);
278
279 r = ath9k_hw_reset(ah, hchan, fastcc);
280 if (r) {
281 DPRINTF(sc, ATH_DBG_FATAL,
282 "Unable to reset channel (%u Mhz) "
6b45784f 283 "reset status %d\n",
c0d7c7af
LR		 284 channel->center_freq, r);
285 spin_unlock_bh(&sc->sc_resetlock);
286 return r;
ff37e337 287 }
c0d7c7af
LR		 288 spin_unlock_bh(&sc->sc_resetlock);
289
c0d7c7af
LR		 290 sc->sc_flags &= ~SC_OP_FULL_RESET;
291
292 if (ath_startrecv(sc) != 0) {
293 DPRINTF(sc, ATH_DBG_FATAL,
294 "Unable to restart recv logic\n");
295 return -EIO;
296 }
297
298 ath_cache_conf_rate(sc, &hw->conf);
299 ath_update_txpow(sc);
17d7904d 300 ath9k_hw_set_interrupts(ah, sc->imask);
3cbb5dd7 301 ath9k_ps_restore(sc);
ff37e337
S		 302 return 0;
303}
304
305/*
306 * This routine performs the periodic noise floor calibration function
307 * that is used to adjust and optimize the chip performance. This
308 * takes environmental changes (location, temperature) into account.
309 * When the task is complete, it reschedules itself depending on the
310 * appropriate interval that was calculated.
311 */
312static void ath_ani_calibrate(unsigned long data)
313{
20977d3e
S		 314 struct ath_softc *sc = (struct ath_softc *)data;
315 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 316 bool longcal = false;
317 bool shortcal = false;
318 bool aniflag = false;
319 unsigned int timestamp = jiffies_to_msecs(jiffies);
20977d3e 320 u32 cal_interval, short_cal_interval;
ff37e337 321
20977d3e
S		 322 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
323 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337
S		 324
325 /*
326 * don't calibrate when we're scanning.
327 * we are most likely not on our home channel.
328 */
0c98de65 329 if (sc->sc_flags & SC_OP_SCANNING)
20977d3e 330 goto set_timer;
ff37e337
S		 331
332 /* Long calibration runs independently of short calibration. */
17d7904d 333 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 334 longcal = true;
04bd4638 335 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
17d7904d 336 sc->ani.longcal_timer = timestamp;
ff37e337
S		 337 }
338
17d7904d
S		 339 /* Short calibration applies only while caldone is false */
340 if (!sc->ani.caldone) {
20977d3e 341 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 342 shortcal = true;
04bd4638 343 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
17d7904d
S		 344 sc->ani.shortcal_timer = timestamp;
345 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 346 }
347 } else {
17d7904d 348 if ((timestamp - sc->ani.resetcal_timer) >=
ff37e337 349 ATH_RESTART_CALINTERVAL) {
17d7904d
S		 350 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
351 if (sc->ani.caldone)
352 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 353 }
354 }
355
356 /* Verify whether we must check ANI */
20977d3e 357 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
ff37e337 358 aniflag = true;
17d7904d 359 sc->ani.checkani_timer = timestamp;
ff37e337
S		 360 }
361
362 /* Skip all processing if there's nothing to do. */
363 if (longcal || shortcal || aniflag) {
364 /* Call ANI routine if necessary */
365 if (aniflag)
20977d3e 366 ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
ff37e337
S		 367
368 /* Perform calibration if necessary */
369 if (longcal || shortcal) {
379f0440
S		 370 sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
371 sc->rx_chainmask, longcal);
372
373 if (longcal)
374 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
375 ah->curchan);
376
377 DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
378 ah->curchan->channel, ah->curchan->channelFlags,
379 sc->ani.noise_floor);
ff37e337
S		 380 }
381 }
382
20977d3e 383set_timer:
ff37e337
S		 384 /*
385 * Set timer interval based on previous results.
386 * The interval must be the shortest necessary to satisfy ANI,
387 * short calibration and long calibration.
388 */
aac9207e 389 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 390 if (sc->sc_ah->config.enable_ani)
aac9207e 391 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
17d7904d 392 if (!sc->ani.caldone)
20977d3e 393 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 394
17d7904d 395 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S		 396}
397
415f738e
S		 398static void ath_start_ani(struct ath_softc *sc)
399{
400 unsigned long timestamp = jiffies_to_msecs(jiffies);
401
402 sc->ani.longcal_timer = timestamp;
403 sc->ani.shortcal_timer = timestamp;
404 sc->ani.checkani_timer = timestamp;
405
406 mod_timer(&sc->ani.timer,
407 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
408}
409
ff37e337
S		 410/*
411 * Update tx/rx chainmask. For legacy association,
412 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 413 * the chainmask configuration, for bt coexistence, use
414 * the chainmask configuration even in legacy mode.
ff37e337 415 */
0e2dedf9 416void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337 417{
c97c92d9 418 if (is_ht ||
2660b81a
S		 419 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
420 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
421 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
ff37e337 422 } else {
17d7904d
S		 423 sc->tx_chainmask = 1;
424 sc->rx_chainmask = 1;
ff37e337
S		 425 }
426
04bd4638 427 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
17d7904d 428 sc->tx_chainmask, sc->rx_chainmask);
ff37e337
S		 429}
430
431static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
432{
433 struct ath_node *an;
434
435 an = (struct ath_node *)sta->drv_priv;
436
87792efc 437 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 438 ath_tx_node_init(sc, an);
87792efc
S		 439 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
440 sta->ht_cap.ampdu_factor);
441 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
442 }
ff37e337
S		 443}
444
445static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
446{
447 struct ath_node *an = (struct ath_node *)sta->drv_priv;
448
449 if (sc->sc_flags & SC_OP_TXAGGR)
450 ath_tx_node_cleanup(sc, an);
451}
452
453static void ath9k_tasklet(unsigned long data)
454{
455 struct ath_softc *sc = (struct ath_softc *)data;
17d7904d 456 u32 status = sc->intrstatus;
ff37e337 457
153e080d
VT		 458 ath9k_ps_wakeup(sc);
459
ff37e337 460 if (status & ATH9K_INT_FATAL) {
ff37e337 461 ath_reset(sc, false);
153e080d 462 ath9k_ps_restore(sc);
ff37e337 463 return;
063d8be3 464 }
ff37e337 465
063d8be3
S		 466 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
467 spin_lock_bh(&sc->rx.rxflushlock);
468 ath_rx_tasklet(sc, 0);
469 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 470 }
471
063d8be3
S		 472 if (status & ATH9K_INT_TX)
473 ath_tx_tasklet(sc);
474
ff37e337 475 /* re-enable hardware interrupt */
17d7904d 476 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
153e080d 477 ath9k_ps_restore(sc);
ff37e337
S		 478}
479
6baff7f9 480irqreturn_t ath_isr(int irq, void *dev)
ff37e337 481{
063d8be3
S		 482#define SCHED_INTR ( \
483 ATH9K_INT_FATAL | \
484 ATH9K_INT_RXORN | \
485 ATH9K_INT_RXEOL | \
486 ATH9K_INT_RX | \
487 ATH9K_INT_TX | \
488 ATH9K_INT_BMISS | \
489 ATH9K_INT_CST | \
490 ATH9K_INT_TSFOOR)
491
ff37e337 492 struct ath_softc *sc = dev;
cbe61d8a 493 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 494 enum ath9k_int status;
495 bool sched = false;
496
063d8be3
S		 497 /*
498 * The hardware is not ready/present, don't
499 * touch anything. Note this can happen early
500 * on if the IRQ is shared.
501 */
502 if (sc->sc_flags & SC_OP_INVALID)
503 return IRQ_NONE;
ff37e337 504
063d8be3
S		 505
506 /* shared irq, not for us */
507
153e080d 508 if (!ath9k_hw_intrpend(ah))
063d8be3 509 return IRQ_NONE;
063d8be3
S		 510
511 /*
512 * Figure out the reason(s) for the interrupt. Note
513 * that the hal returns a pseudo-ISR that may include
514 * bits we haven't explicitly enabled so we mask the
515 * value to insure we only process bits we requested.
516 */
517 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
518 status &= sc->imask; /* discard unasked-for bits */
ff37e337 519
063d8be3
S		 520 /*
521 * If there are no status bits set, then this interrupt was not
522 * for me (should have been caught above).
523 */
153e080d 524 if (!status)
063d8be3 525 return IRQ_NONE;
ff37e337 526
063d8be3
S		 527 /* Cache the status */
528 sc->intrstatus = status;
529
530 if (status & SCHED_INTR)
531 sched = true;
532
533 /*
534 * If a FATAL or RXORN interrupt is received, we have to reset the
535 * chip immediately.
536 */
537 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
538 goto chip_reset;
539
540 if (status & ATH9K_INT_SWBA)
541 tasklet_schedule(&sc->bcon_tasklet);
542
543 if (status & ATH9K_INT_TXURN)
544 ath9k_hw_updatetxtriglevel(ah, true);
545
546 if (status & ATH9K_INT_MIB) {
ff37e337 547 /*
063d8be3
S		 548 * Disable interrupts until we service the MIB
549 * interrupt; otherwise it will continue to
550 * fire.
ff37e337 551 */
063d8be3
S		 552 ath9k_hw_set_interrupts(ah, 0);
553 /*
554 * Let the hal handle the event. We assume
555 * it will clear whatever condition caused
556 * the interrupt.
557 */
558 ath9k_hw_procmibevent(ah, &sc->nodestats);
559 ath9k_hw_set_interrupts(ah, sc->imask);
560 }
ff37e337 561
153e080d
VT		 562 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
563 if (status & ATH9K_INT_TIM_TIMER) {
063d8be3
S		 564 /* Clear RxAbort bit so that we can
565 * receive frames */
566 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
153e080d 567 ath9k_hw_setrxabort(sc->sc_ah, 0);
063d8be3 568 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337 569 }
063d8be3
S		 570
571chip_reset:
ff37e337 572
817e11de
S		 573 ath_debug_stat_interrupt(sc, status);
574
ff37e337
S		 575 if (sched) {
576 /* turn off every interrupt except SWBA */
17d7904d 577 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S		 578 tasklet_schedule(&sc->intr_tq);
579 }
580
581 return IRQ_HANDLED;
063d8be3
S		 582
583#undef SCHED_INTR
ff37e337
S		 584}
585
f078f209 586static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 587 struct ieee80211_channel *chan,
094d05dc 588 enum nl80211_channel_type channel_type)
f078f209
LR		 589{
590 u32 chanmode = 0;
f078f209
LR		 591
592 switch (chan->band) {
593 case IEEE80211_BAND_2GHZ:
094d05dc
S		 594 switch(channel_type) {
595 case NL80211_CHAN_NO_HT:
596 case NL80211_CHAN_HT20:
f078f209 597 chanmode = CHANNEL_G_HT20;
094d05dc
S		 598 break;
599 case NL80211_CHAN_HT40PLUS:
f078f209 600 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 601 break;
602 case NL80211_CHAN_HT40MINUS:
f078f209 603 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 604 break;
605 }
f078f209
LR		 606 break;
607 case IEEE80211_BAND_5GHZ:
094d05dc
S		 608 switch(channel_type) {
609 case NL80211_CHAN_NO_HT:
610 case NL80211_CHAN_HT20:
f078f209 611 chanmode = CHANNEL_A_HT20;
094d05dc
S		 612 break;
613 case NL80211_CHAN_HT40PLUS:
f078f209 614 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 615 break;
616 case NL80211_CHAN_HT40MINUS:
f078f209 617 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 618 break;
619 }
f078f209
LR		 620 break;
621 default:
622 break;
623 }
624
625 return chanmode;
626}
627
6ace2891 628static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
3f53dd64
JM		 629 struct ath9k_keyval *hk, const u8 *addr,
630 bool authenticator)
f078f209 631{
6ace2891
JM		 632 const u8 *key_rxmic;
633 const u8 *key_txmic;
f078f209 634
6ace2891
JM		 635 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
636 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 637
638 if (addr == NULL) {
d216aaa6
JM		 639 /*
640 * Group key installation - only two key cache entries are used
641 * regardless of splitmic capability since group key is only
642 * used either for TX or RX.
643 */
3f53dd64
JM		 644 if (authenticator) {
645 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
646 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
647 } else {
648 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
649 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
650 }
d216aaa6 651 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 652 }
17d7904d 653 if (!sc->splitmic) {
d216aaa6 654 /* TX and RX keys share the same key cache entry. */
f078f209
LR		 655 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
656 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
d216aaa6 657 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 658 }
d216aaa6
JM		 659
660 /* Separate key cache entries for TX and RX */
661
662 /* TX key goes at first index, RX key at +32. */
f078f209 663 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
d216aaa6
JM		 664 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
665 /* TX MIC entry failed. No need to proceed further */
d8baa939 666 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 667 "Setting TX MIC Key Failed\n");
f078f209
LR		 668 return 0;
669 }
670
671 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
672 /* XXX delete tx key on failure? */
d216aaa6 673 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
6ace2891
JM		 674}
675
676static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
677{
678 int i;
679
17d7904d
S		 680 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
681 if (test_bit(i, sc->keymap) ||
682 test_bit(i + 64, sc->keymap))
6ace2891 683 continue; /* At least one part of TKIP key allocated */
17d7904d
S		 684 if (sc->splitmic &&
685 (test_bit(i + 32, sc->keymap) ||
686 test_bit(i + 64 + 32, sc->keymap)))
6ace2891
JM		 687 continue; /* At least one part of TKIP key allocated */
688
689 /* Found a free slot for a TKIP key */
690 return i;
691 }
692 return -1;
693}
694
695static int ath_reserve_key_cache_slot(struct ath_softc *sc)
696{
697 int i;
698
699 /* First, try to find slots that would not be available for TKIP. */
17d7904d
S		 700 if (sc->splitmic) {
701 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
702 if (!test_bit(i, sc->keymap) &&
703 (test_bit(i + 32, sc->keymap) ||
704 test_bit(i + 64, sc->keymap) ||
705 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 706 return i;
17d7904d
S		 707 if (!test_bit(i + 32, sc->keymap) &&
708 (test_bit(i, sc->keymap) ||
709 test_bit(i + 64, sc->keymap) ||
710 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 711 return i + 32;
17d7904d
S		 712 if (!test_bit(i + 64, sc->keymap) &&
713 (test_bit(i , sc->keymap) ||
714 test_bit(i + 32, sc->keymap) ||
715 test_bit(i + 64 + 32, sc->keymap)))
ea612132 716 return i + 64;
17d7904d
S		 717 if (!test_bit(i + 64 + 32, sc->keymap) &&
718 (test_bit(i, sc->keymap) ||
719 test_bit(i + 32, sc->keymap) ||
720 test_bit(i + 64, sc->keymap)))
ea612132 721 return i + 64 + 32;
6ace2891
JM		 722 }
723 } else {
17d7904d
S		 724 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
725 if (!test_bit(i, sc->keymap) &&
726 test_bit(i + 64, sc->keymap))
6ace2891 727 return i;
17d7904d
S		 728 if (test_bit(i, sc->keymap) &&
729 !test_bit(i + 64, sc->keymap))
6ace2891
JM		 730 return i + 64;
731 }
732 }
733
734 /* No partially used TKIP slots, pick any available slot */
17d7904d 735 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
be2864cf
JM		 736 /* Do not allow slots that could be needed for TKIP group keys
737 * to be used. This limitation could be removed if we know that
738 * TKIP will not be used. */
739 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
740 continue;
17d7904d 741 if (sc->splitmic) {
be2864cf
JM		 742 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
743 continue;
744 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
745 continue;
746 }
747
17d7904d 748 if (!test_bit(i, sc->keymap))
6ace2891
JM		 749 return i; /* Found a free slot for a key */
750 }
751
752 /* No free slot found */
753 return -1;
f078f209
LR		 754}
755
756static int ath_key_config(struct ath_softc *sc,
3f53dd64 757 struct ieee80211_vif *vif,
dc822b5d 758 struct ieee80211_sta *sta,
f078f209
LR		 759 struct ieee80211_key_conf *key)
760{
f078f209
LR		 761 struct ath9k_keyval hk;
762 const u8 *mac = NULL;
763 int ret = 0;
6ace2891 764 int idx;
f078f209
LR		 765
766 memset(&hk, 0, sizeof(hk));
767
768 switch (key->alg) {
769 case ALG_WEP:
770 hk.kv_type = ATH9K_CIPHER_WEP;
771 break;
772 case ALG_TKIP:
773 hk.kv_type = ATH9K_CIPHER_TKIP;
774 break;
775 case ALG_CCMP:
776 hk.kv_type = ATH9K_CIPHER_AES_CCM;
777 break;
778 default:
ca470b29 779 return -EOPNOTSUPP;
f078f209
LR		 780 }
781
6ace2891 782 hk.kv_len = key->keylen;
f078f209
LR		 783 memcpy(hk.kv_val, key->key, key->keylen);
784
6ace2891
JM		 785 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
786 /* For now, use the default keys for broadcast keys. This may
787 * need to change with virtual interfaces. */
788 idx = key->keyidx;
789 } else if (key->keyidx) {
dc822b5d
JB		 790 if (WARN_ON(!sta))
791 return -EOPNOTSUPP;
792 mac = sta->addr;
793
6ace2891
JM		 794 if (vif->type != NL80211_IFTYPE_AP) {
795 /* Only keyidx 0 should be used with unicast key, but
796 * allow this for client mode for now. */
797 idx = key->keyidx;
798 } else
799 return -EIO;
f078f209 800 } else {
dc822b5d
JB		 801 if (WARN_ON(!sta))
802 return -EOPNOTSUPP;
803 mac = sta->addr;
804
6ace2891
JM		 805 if (key->alg == ALG_TKIP)
806 idx = ath_reserve_key_cache_slot_tkip(sc);
807 else
808 idx = ath_reserve_key_cache_slot(sc);
809 if (idx < 0)
ca470b29 810 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 811 }
812
813 if (key->alg == ALG_TKIP)
3f53dd64
JM		 814 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
815 vif->type == NL80211_IFTYPE_AP);
f078f209 816 else
d216aaa6 817 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
f078f209
LR		 818
819 if (!ret)
820 return -EIO;
821
17d7904d 822 set_bit(idx, sc->keymap);
6ace2891 823 if (key->alg == ALG_TKIP) {
17d7904d
S		 824 set_bit(idx + 64, sc->keymap);
825 if (sc->splitmic) {
826 set_bit(idx + 32, sc->keymap);
827 set_bit(idx + 64 + 32, sc->keymap);
6ace2891
JM		 828 }
829 }
830
831 return idx;
f078f209
LR		 832}
833
834static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
835{
6ace2891
JM		 836 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
837 if (key->hw_key_idx < IEEE80211_WEP_NKID)
838 return;
839
17d7904d 840 clear_bit(key->hw_key_idx, sc->keymap);
6ace2891
JM		 841 if (key->alg != ALG_TKIP)
842 return;
f078f209 843
17d7904d
S		 844 clear_bit(key->hw_key_idx + 64, sc->keymap);
845 if (sc->splitmic) {
846 clear_bit(key->hw_key_idx + 32, sc->keymap);
847 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
6ace2891 848 }
f078f209
LR		 849}
850
eb2599ca
S		 851static void setup_ht_cap(struct ath_softc *sc,
852 struct ieee80211_sta_ht_cap *ht_info)
f078f209 853{
60653678
S		 854#define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
855#define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
f078f209 856
d9fe60de
JB		 857 ht_info->ht_supported = true;
858 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
859 IEEE80211_HT_CAP_SM_PS |
860 IEEE80211_HT_CAP_SGI_40 |
861 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 862
60653678
S		 863 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
864 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
eb2599ca 865
d9fe60de
JB		 866 /* set up supported mcs set */
867 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
eb2599ca 868
17d7904d 869 switch(sc->rx_chainmask) {
eb2599ca
S		 870 case 1:
871 ht_info->mcs.rx_mask[0] = 0xff;
872 break;
3c457265 873 case 3:
eb2599ca
S		 874 case 5:
875 case 7:
876 default:
877 ht_info->mcs.rx_mask[0] = 0xff;
878 ht_info->mcs.rx_mask[1] = 0xff;
879 break;
880 }
881
d9fe60de 882 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 883}
884
8feceb67 885static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 886 struct ieee80211_vif *vif,
8feceb67 887 struct ieee80211_bss_conf *bss_conf)
f078f209 888{
17d7904d 889 struct ath_vif *avp = (void *)vif->drv_priv;
f078f209 890
8feceb67 891 if (bss_conf->assoc) {
094d05dc 892 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
17d7904d 893 bss_conf->aid, sc->curbssid);
f078f209 894
8feceb67 895 /* New association, store aid */
d97809db 896 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
17d7904d 897 sc->curaid = bss_conf->aid;
ba52da58 898 ath9k_hw_write_associd(sc);
8feceb67 899 }
f078f209 900
8feceb67 901 /* Configure the beacon */
2c3db3d5 902 ath_beacon_config(sc, vif);
f078f209 903
8feceb67 904 /* Reset rssi stats */
17d7904d
S		 905 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
906 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
907 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
908 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 909
415f738e 910 ath_start_ani(sc);
8feceb67 911 } else {
1ffb0610 912 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
17d7904d 913 sc->curaid = 0;
f078f209 914 }
8feceb67 915}
f078f209 916
8feceb67
VT		 917/********************************/
918/* LED functions */
919/********************************/
f078f209 920
f2bffa7e
VT		 921static void ath_led_blink_work(struct work_struct *work)
922{
923 struct ath_softc *sc = container_of(work, struct ath_softc,
924 ath_led_blink_work.work);
925
926 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
927 return;
85067c06
VT		 928
929 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
930 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
931 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
932 else
933 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
934 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
f2bffa7e
VT		 935
936 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
937 (sc->sc_flags & SC_OP_LED_ON) ?
938 msecs_to_jiffies(sc->led_off_duration) :
939 msecs_to_jiffies(sc->led_on_duration));
940
85067c06
VT		 941 sc->led_on_duration = sc->led_on_cnt ?
942 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
943 ATH_LED_ON_DURATION_IDLE;
944 sc->led_off_duration = sc->led_off_cnt ?
945 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
946 ATH_LED_OFF_DURATION_IDLE;
f2bffa7e
VT		 947 sc->led_on_cnt = sc->led_off_cnt = 0;
948 if (sc->sc_flags & SC_OP_LED_ON)
949 sc->sc_flags &= ~SC_OP_LED_ON;
950 else
951 sc->sc_flags |= SC_OP_LED_ON;
952}
953
8feceb67
VT		 954static void ath_led_brightness(struct led_classdev *led_cdev,
955 enum led_brightness brightness)
956{
957 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
958 struct ath_softc *sc = led->sc;
f078f209 959
8feceb67
VT		 960 switch (brightness) {
961 case LED_OFF:
962 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e
VT		 963 led->led_type == ATH_LED_RADIO) {
964 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
965 (led->led_type == ATH_LED_RADIO));
8feceb67 966 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 967 if (led->led_type == ATH_LED_RADIO)
968 sc->sc_flags &= ~SC_OP_LED_ON;
969 } else {
970 sc->led_off_cnt++;
971 }
8feceb67
VT		 972 break;
973 case LED_FULL:
f2bffa7e 974 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 975 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 976 queue_delayed_work(sc->hw->workqueue,
977 &sc->ath_led_blink_work, 0);
978 } else if (led->led_type == ATH_LED_RADIO) {
979 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
980 sc->sc_flags |= SC_OP_LED_ON;
981 } else {
982 sc->led_on_cnt++;
983 }
8feceb67
VT		 984 break;
985 default:
986 break;
f078f209 987 }
8feceb67 988}
f078f209 989
8feceb67
VT		 990static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
991 char *trigger)
992{
993 int ret;
f078f209 994
8feceb67
VT		 995 led->sc = sc;
996 led->led_cdev.name = led->name;
997 led->led_cdev.default_trigger = trigger;
998 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 999
8feceb67
VT		 1000 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1001 if (ret)
1002 DPRINTF(sc, ATH_DBG_FATAL,
1003 "Failed to register led:%s", led->name);
1004 else
1005 led->registered = 1;
1006 return ret;
1007}
f078f209 1008
8feceb67
VT		 1009static void ath_unregister_led(struct ath_led *led)
1010{
1011 if (led->registered) {
1012 led_classdev_unregister(&led->led_cdev);
1013 led->registered = 0;
f078f209 1014 }
f078f209
LR		 1015}
1016
8feceb67 1017static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1018{
f2bffa7e 1019 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67
VT		 1020 ath_unregister_led(&sc->assoc_led);
1021 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1022 ath_unregister_led(&sc->tx_led);
1023 ath_unregister_led(&sc->rx_led);
1024 ath_unregister_led(&sc->radio_led);
1025 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1026}
f078f209 1027
8feceb67
VT		 1028static void ath_init_leds(struct ath_softc *sc)
1029{
1030 char *trigger;
1031 int ret;
f078f209 1032
8feceb67
VT		 1033 /* Configure gpio 1 for output */
1034 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1035 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1036 /* LED off, active low */
1037 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 1038
f2bffa7e
VT		 1039 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1040
8feceb67
VT		 1041 trigger = ieee80211_get_radio_led_name(sc->hw);
1042 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
0818cb8a 1043 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1044 ret = ath_register_led(sc, &sc->radio_led, trigger);
1045 sc->radio_led.led_type = ATH_LED_RADIO;
1046 if (ret)
1047 goto fail;
7dcfdcd9 1048
8feceb67
VT		 1049 trigger = ieee80211_get_assoc_led_name(sc->hw);
1050 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
0818cb8a 1051 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1052 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1053 sc->assoc_led.led_type = ATH_LED_ASSOC;
1054 if (ret)
1055 goto fail;
f078f209 1056
8feceb67
VT		 1057 trigger = ieee80211_get_tx_led_name(sc->hw);
1058 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
0818cb8a 1059 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1060 ret = ath_register_led(sc, &sc->tx_led, trigger);
1061 sc->tx_led.led_type = ATH_LED_TX;
1062 if (ret)
1063 goto fail;
f078f209 1064
8feceb67
VT		 1065 trigger = ieee80211_get_rx_led_name(sc->hw);
1066 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
0818cb8a 1067 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1068 ret = ath_register_led(sc, &sc->rx_led, trigger);
1069 sc->rx_led.led_type = ATH_LED_RX;
1070 if (ret)
1071 goto fail;
f078f209 1072
8feceb67
VT		 1073 return;
1074
1075fail:
1076 ath_deinit_leds(sc);
f078f209
LR		 1077}
1078
7ec3e514 1079void ath_radio_enable(struct ath_softc *sc)
500c064d 1080{
cbe61d8a 1081 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1082 struct ieee80211_channel *channel = sc->hw->conf.channel;
1083 int r;
500c064d 1084
3cbb5dd7 1085 ath9k_ps_wakeup(sc);
d2f5b3a6 1086 ath9k_hw_configpcipowersave(ah, 0);
ae8d2858 1087
d2f5b3a6 1088 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1089 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1090 if (r) {
500c064d 1091 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1092 "Unable to reset channel %u (%uMhz) ",
6b45784f 1093 "reset status %d\n",
ae8d2858 1094 channel->center_freq, r);
500c064d
VT		 1095 }
1096 spin_unlock_bh(&sc->sc_resetlock);
1097
1098 ath_update_txpow(sc);
1099 if (ath_startrecv(sc) != 0) {
1100 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1101 "Unable to restart recv logic\n");
500c064d
VT		 1102 return;
1103 }
1104
1105 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1106 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT		 1107
1108 /* Re-Enable interrupts */
17d7904d 1109 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT		 1110
1111 /* Enable LED */
1112 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1113 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1114 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1115
1116 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1117 ath9k_ps_restore(sc);
500c064d
VT		 1118}
1119
7ec3e514 1120void ath_radio_disable(struct ath_softc *sc)
500c064d 1121{
cbe61d8a 1122 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1123 struct ieee80211_channel *channel = sc->hw->conf.channel;
1124 int r;
500c064d 1125
3cbb5dd7 1126 ath9k_ps_wakeup(sc);
500c064d
VT		 1127 ieee80211_stop_queues(sc->hw);
1128
1129 /* Disable LED */
1130 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1131 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1132
1133 /* Disable interrupts */
1134 ath9k_hw_set_interrupts(ah, 0);
1135
043a0405 1136 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1137 ath_stoprecv(sc); /* turn off frame recv */
1138 ath_flushrecv(sc); /* flush recv queue */
1139
1140 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1141 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1142 if (r) {
500c064d 1143 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1144 "Unable to reset channel %u (%uMhz) "
6b45784f 1145 "reset status %d\n",
ae8d2858 1146 channel->center_freq, r);
500c064d
VT		 1147 }
1148 spin_unlock_bh(&sc->sc_resetlock);
1149
1150 ath9k_hw_phy_disable(ah);
d2f5b3a6 1151 ath9k_hw_configpcipowersave(ah, 1);
500c064d 1152 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
3cbb5dd7 1153 ath9k_ps_restore(sc);
500c064d
VT		 1154}
1155
5077fd35
GJ		 1156#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1157
1158/*******************/
1159/* Rfkill */
1160/*******************/
1161
500c064d
VT		 1162static bool ath_is_rfkill_set(struct ath_softc *sc)
1163{
cbe61d8a 1164 struct ath_hw *ah = sc->sc_ah;
500c064d 1165
2660b81a
S		 1166 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1167 ah->rfkill_polarity;
500c064d
VT		 1168}
1169
1170/* h/w rfkill poll function */
1171static void ath_rfkill_poll(struct work_struct *work)
1172{
1173 struct ath_softc *sc = container_of(work, struct ath_softc,
1174 rf_kill.rfkill_poll.work);
1175 bool radio_on;
1176
1177 if (sc->sc_flags & SC_OP_INVALID)
1178 return;
1179
1180 radio_on = !ath_is_rfkill_set(sc);
1181
1182 /*
1183 * enable/disable radio only when there is a
1184 * state change in RF switch
1185 */
1186 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1187 enum rfkill_state state;
1188
1189 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1190 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1191 : RFKILL_STATE_HARD_BLOCKED;
1192 } else if (radio_on) {
1193 ath_radio_enable(sc);
1194 state = RFKILL_STATE_UNBLOCKED;
1195 } else {
1196 ath_radio_disable(sc);
1197 state = RFKILL_STATE_HARD_BLOCKED;
1198 }
1199
1200 if (state == RFKILL_STATE_HARD_BLOCKED)
1201 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1202 else
1203 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1204
1205 rfkill_force_state(sc->rf_kill.rfkill, state);
1206 }
1207
1208 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1209 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1210}
1211
1212/* s/w rfkill handler */
1213static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1214{
1215 struct ath_softc *sc = data;
1216
1217 switch (state) {
1218 case RFKILL_STATE_SOFT_BLOCKED:
1219 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1220 SC_OP_RFKILL_SW_BLOCKED)))
1221 ath_radio_disable(sc);
1222 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1223 return 0;
1224 case RFKILL_STATE_UNBLOCKED:
1225 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1226 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1227 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1228 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
04bd4638 1229 "radio as it is disabled by h/w\n");
500c064d
VT		 1230 return -EPERM;
1231 }
1232 ath_radio_enable(sc);
1233 }
1234 return 0;
1235 default:
1236 return -EINVAL;
1237 }
1238}
1239
1240/* Init s/w rfkill */
1241static int ath_init_sw_rfkill(struct ath_softc *sc)
1242{
1243 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1244 RFKILL_TYPE_WLAN);
1245 if (!sc->rf_kill.rfkill) {
1246 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1247 return -ENOMEM;
1248 }
1249
1250 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
0818cb8a 1251 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
500c064d
VT		 1252 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1253 sc->rf_kill.rfkill->data = sc;
1254 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1255 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
500c064d
VT		 1256
1257 return 0;
1258}
1259
1260/* Deinitialize rfkill */
1261static void ath_deinit_rfkill(struct ath_softc *sc)
1262{
2660b81a 1263 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d
VT		 1264 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1265
1266 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1267 rfkill_unregister(sc->rf_kill.rfkill);
1268 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1269 sc->rf_kill.rfkill = NULL;
1270 }
1271}
9c84b797
S		 1272
1273static int ath_start_rfkill_poll(struct ath_softc *sc)
1274{
2660b81a 1275 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
9c84b797
S		 1276 queue_delayed_work(sc->hw->workqueue,
1277 &sc->rf_kill.rfkill_poll, 0);
1278
1279 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1280 if (rfkill_register(sc->rf_kill.rfkill)) {
1281 DPRINTF(sc, ATH_DBG_FATAL,
1282 "Unable to register rfkill\n");
1283 rfkill_free(sc->rf_kill.rfkill);
1284
1285 /* Deinitialize the device */
39c3c2f2 1286 ath_cleanup(sc);
9c84b797
S		 1287 return -EIO;
1288 } else {
1289 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1290 }
1291 }
1292
1293 return 0;
1294}
500c064d
VT		 1295#endif /* CONFIG_RFKILL */
1296
6baff7f9 1297void ath_cleanup(struct ath_softc *sc)
39c3c2f2
GJ		 1298{
1299 ath_detach(sc);
1300 free_irq(sc->irq, sc);
1301 ath_bus_cleanup(sc);
c52f33d0 1302 kfree(sc->sec_wiphy);
39c3c2f2
GJ		 1303 ieee80211_free_hw(sc->hw);
1304}
1305
6baff7f9 1306void ath_detach(struct ath_softc *sc)
f078f209 1307{
8feceb67 1308 struct ieee80211_hw *hw = sc->hw;
9c84b797 1309 int i = 0;
f078f209 1310
3cbb5dd7
VN		 1311 ath9k_ps_wakeup(sc);
1312
04bd4638 1313 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1314
e97275cb 1315#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1316 ath_deinit_rfkill(sc);
1317#endif
3fcdfb4b 1318 ath_deinit_leds(sc);
0e2dedf9 1319 cancel_work_sync(&sc->chan_work);
f98c3bd2 1320 cancel_delayed_work_sync(&sc->wiphy_work);
3fcdfb4b 1321
c52f33d0
JM		 1322 for (i = 0; i < sc->num_sec_wiphy; i++) {
1323 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1324 if (aphy == NULL)
1325 continue;
1326 sc->sec_wiphy[i] = NULL;
1327 ieee80211_unregister_hw(aphy->hw);
1328 ieee80211_free_hw(aphy->hw);
1329 }
3fcdfb4b 1330 ieee80211_unregister_hw(hw);
8feceb67
VT		 1331 ath_rx_cleanup(sc);
1332 ath_tx_cleanup(sc);
f078f209 1333
9c84b797
S		 1334 tasklet_kill(&sc->intr_tq);
1335 tasklet_kill(&sc->bcon_tasklet);
f078f209 1336
9c84b797
S		 1337 if (!(sc->sc_flags & SC_OP_INVALID))
1338 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1339
9c84b797
S		 1340 /* cleanup tx queues */
1341 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1342 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1343 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797
S		 1344
1345 ath9k_hw_detach(sc->sc_ah);
826d2680 1346 ath9k_exit_debug(sc);
3cbb5dd7 1347 ath9k_ps_restore(sc);
f078f209
LR		 1348}
1349
e3bb249b
BC		 1350static int ath9k_reg_notifier(struct wiphy *wiphy,
1351 struct regulatory_request *request)
1352{
1353 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1354 struct ath_wiphy *aphy = hw->priv;
1355 struct ath_softc *sc = aphy->sc;
1356 struct ath_regulatory *reg = &sc->sc_ah->regulatory;
1357
1358 return ath_reg_notifier_apply(wiphy, request, reg);
1359}
1360
ff37e337
S		 1361static int ath_init(u16 devid, struct ath_softc *sc)
1362{
cbe61d8a 1363 struct ath_hw *ah = NULL;
ff37e337
S		 1364 int status;
1365 int error = 0, i;
1366 int csz = 0;
1367
1368 /* XXX: hardware will not be ready until ath_open() being called */
1369 sc->sc_flags |= SC_OP_INVALID;
88b126af 1370
826d2680
S		 1371 if (ath9k_init_debug(sc) < 0)
1372 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337 1373
c52f33d0 1374 spin_lock_init(&sc->wiphy_lock);
ff37e337 1375 spin_lock_init(&sc->sc_resetlock);
6158425b 1376 spin_lock_init(&sc->sc_serial_rw);
aa33de09 1377 mutex_init(&sc->mutex);
ff37e337 1378 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
9fc9ab0a 1379 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
ff37e337
S		 1380 (unsigned long)sc);
1381
1382 /*
1383 * Cache line size is used to size and align various
1384 * structures used to communicate with the hardware.
1385 */
88d15707 1386 ath_read_cachesize(sc, &csz);
ff37e337 1387 /* XXX assert csz is non-zero */
17d7904d 1388 sc->cachelsz = csz << 2; /* convert to bytes */
ff37e337 1389
cbe61d8a 1390 ah = ath9k_hw_attach(devid, sc, &status);
ff37e337
S		 1391 if (ah == NULL) {
1392 DPRINTF(sc, ATH_DBG_FATAL,
295834fe 1393 "Unable to attach hardware; HAL status %d\n", status);
ff37e337
S		 1394 error = -ENXIO;
1395 goto bad;
1396 }
1397 sc->sc_ah = ah;
1398
1399 /* Get the hardware key cache size. */
2660b81a 1400 sc->keymax = ah->caps.keycache_size;
17d7904d 1401 if (sc->keymax > ATH_KEYMAX) {
d8baa939 1402 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 1403 "Warning, using only %u entries in %u key cache\n",
17d7904d
S		 1404 ATH_KEYMAX, sc->keymax);
1405 sc->keymax = ATH_KEYMAX;
ff37e337
S		 1406 }
1407
1408 /*
1409 * Reset the key cache since some parts do not
1410 * reset the contents on initial power up.
1411 */
17d7904d 1412 for (i = 0; i < sc->keymax; i++)
ff37e337 1413 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1414
85efc86e
LR		 1415 error = ath_regd_init(&sc->sc_ah->regulatory, sc->hw->wiphy,
1416 ath9k_reg_notifier);
1417 if (error)
ff37e337
S		 1418 goto bad;
1419
1420 /* default to MONITOR mode */
2660b81a 1421 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
d97809db 1422
ff37e337
S		 1423 /* Setup rate tables */
1424
1425 ath_rate_attach(sc);
1426 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1427 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1428
1429 /*
1430 * Allocate hardware transmit queues: one queue for
1431 * beacon frames and one data queue for each QoS
1432 * priority. Note that the hal handles reseting
1433 * these queues at the needed time.
1434 */
b77f483f
S		 1435 sc->beacon.beaconq = ath_beaconq_setup(ah);
1436 if (sc->beacon.beaconq == -1) {
ff37e337 1437 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1438 "Unable to setup a beacon xmit queue\n");
ff37e337
S		 1439 error = -EIO;
1440 goto bad2;
1441 }
b77f483f
S		 1442 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1443 if (sc->beacon.cabq == NULL) {
ff37e337 1444 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1445 "Unable to setup CAB xmit queue\n");
ff37e337
S		 1446 error = -EIO;
1447 goto bad2;
1448 }
1449
17d7904d 1450 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
ff37e337
S		 1451 ath_cabq_update(sc);
1452
b77f483f
S		 1453 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1454 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1455
1456 /* Setup data queues */
1457 /* NB: ensure BK queue is the lowest priority h/w queue */
1458 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1459 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1460 "Unable to setup xmit queue for BK traffic\n");
ff37e337
S		 1461 error = -EIO;
1462 goto bad2;
1463 }
1464
1465 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1466 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1467 "Unable to setup xmit queue for BE traffic\n");
ff37e337
S		 1468 error = -EIO;
1469 goto bad2;
1470 }
1471 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1472 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1473 "Unable to setup xmit queue for VI traffic\n");
ff37e337
S		 1474 error = -EIO;
1475 goto bad2;
1476 }
1477 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1478 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1479 "Unable to setup xmit queue for VO traffic\n");
ff37e337
S		 1480 error = -EIO;
1481 goto bad2;
1482 }
1483
1484 /* Initializes the noise floor to a reasonable default value.
1485 * Later on this will be updated during ANI processing. */
1486
17d7904d
S		 1487 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1488 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
ff37e337
S		 1489
1490 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1491 ATH9K_CIPHER_TKIP, NULL)) {
1492 /*
1493 * Whether we should enable h/w TKIP MIC.
1494 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1495 * report WMM capable, so it's always safe to turn on
1496 * TKIP MIC in this case.
1497 */
1498 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1499 0, 1, NULL);
1500 }
1501
1502 /*
1503 * Check whether the separate key cache entries
1504 * are required to handle both tx+rx MIC keys.
1505 * With split mic keys the number of stations is limited
1506 * to 27 otherwise 59.
1507 */
1508 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1509 ATH9K_CIPHER_TKIP, NULL)
1510 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1511 ATH9K_CIPHER_MIC, NULL)
1512 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1513 0, NULL))
17d7904d 1514 sc->splitmic = 1;
ff37e337
S		 1515
1516 /* turn on mcast key search if possible */
1517 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1518 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1519 1, NULL);
1520
17d7904d 1521 sc->config.txpowlimit = ATH_TXPOWER_MAX;
ff37e337
S		 1522
1523 /* 11n Capabilities */
2660b81a 1524 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337
S		 1525 sc->sc_flags |= SC_OP_TXAGGR;
1526 sc->sc_flags |= SC_OP_RXAGGR;
1527 }
1528
2660b81a
S		 1529 sc->tx_chainmask = ah->caps.tx_chainmask;
1530 sc->rx_chainmask = ah->caps.rx_chainmask;
ff37e337
S		 1531
1532 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1533 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337 1534
8ca21f01 1535 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
ba52da58 1536 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
ff37e337 1537
b77f483f 1538 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1539
1540 /* initialize beacon slots */
c52f33d0 1541 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2c3db3d5 1542 sc->beacon.bslot[i] = NULL;
c52f33d0
JM		 1543 sc->beacon.bslot_aphy[i] = NULL;
1544 }
ff37e337 1545
ff37e337
S		 1546 /* setup channels and rates */
1547
5f8e077c 1548 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1549 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1550 sc->rates[IEEE80211_BAND_2GHZ];
1551 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1552 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1553 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337 1554
2660b81a 1555 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
5f8e077c 1556 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1557 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1558 sc->rates[IEEE80211_BAND_5GHZ];
1559 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1560 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1561 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1562 }
1563
2660b81a 1564 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
c97c92d9
VT		 1565 ath9k_hw_btcoex_enable(sc->sc_ah);
1566
ff37e337
S		 1567 return 0;
1568bad2:
1569 /* cleanup tx queues */
1570 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1571 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1572 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337
S		 1573bad:
1574 if (ah)
1575 ath9k_hw_detach(ah);
40b130a9 1576 ath9k_exit_debug(sc);
ff37e337
S		 1577
1578 return error;
1579}
1580
c52f33d0 1581void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
f078f209 1582{
9c84b797
S		 1583 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1584 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1585 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1586 IEEE80211_HW_AMPDU_AGGREGATION |
1587 IEEE80211_HW_SUPPORTS_PS |
eeee1320
S		 1588 IEEE80211_HW_PS_NULLFUNC_STACK |
1589 IEEE80211_HW_SPECTRUM_MGMT;
f078f209 1590
b3bd89ce 1591 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
0ced0e17
JM		 1592 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1593
9c84b797
S		 1594 hw->wiphy->interface_modes =
1595 BIT(NL80211_IFTYPE_AP) |
1596 BIT(NL80211_IFTYPE_STATION) |
9cb5412b
PE		 1597 BIT(NL80211_IFTYPE_ADHOC) |
1598 BIT(NL80211_IFTYPE_MESH_POINT);
f078f209 1599
8feceb67 1600 hw->queues = 4;
e63835b0 1601 hw->max_rates = 4;
171387ef 1602 hw->channel_change_time = 5000;
465ca84d 1603 hw->max_listen_interval = 10;
e63835b0 1604 hw->max_rate_tries = ATH_11N_TXMAXTRY;
528f0c6b 1605 hw->sta_data_size = sizeof(struct ath_node);
17d7904d 1606 hw->vif_data_size = sizeof(struct ath_vif);
f078f209 1607
8feceb67 1608 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1609
c52f33d0
JM		 1610 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1611 &sc->sbands[IEEE80211_BAND_2GHZ];
1612 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1613 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1614 &sc->sbands[IEEE80211_BAND_5GHZ];
1615}
1616
1617int ath_attach(u16 devid, struct ath_softc *sc)
1618{
1619 struct ieee80211_hw *hw = sc->hw;
c52f33d0 1620 int error = 0, i;
3a702e49 1621 struct ath_regulatory *reg;
c52f33d0
JM		 1622
1623 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1624
1625 error = ath_init(devid, sc);
1626 if (error != 0)
1627 return error;
1628
c02cf373
BC		 1629 reg = &sc->sc_ah->regulatory;
1630
c52f33d0
JM		 1631 /* get mac address from hardware and set in mac80211 */
1632
1633 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1634
1635 ath_set_hw_capab(sc, hw);
1636
2660b81a 1637 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1638 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
2660b81a 1639 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
eb2599ca 1640 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1641 }
1642
db93e7b5
SB		 1643 /* initialize tx/rx engine */
1644 error = ath_tx_init(sc, ATH_TXBUF);
1645 if (error != 0)
40b130a9 1646 goto error_attach;
8feceb67 1647
db93e7b5
SB		 1648 error = ath_rx_init(sc, ATH_RXBUF);
1649 if (error != 0)
40b130a9 1650 goto error_attach;
8feceb67 1651
e97275cb 1652#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d 1653 /* Initialze h/w Rfkill */
2660b81a 1654 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d
VT		 1655 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1656
1657 /* Initialize s/w rfkill */
40b130a9
VT		 1658 error = ath_init_sw_rfkill(sc);
1659 if (error)
1660 goto error_attach;
500c064d
VT		 1661#endif
1662
0e2dedf9 1663 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
f98c3bd2
JM		 1664 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1665 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
0e2dedf9 1666
db93e7b5 1667 error = ieee80211_register_hw(hw);
8feceb67 1668
3a702e49 1669 if (!ath_is_world_regd(reg)) {
c02cf373 1670 error = regulatory_hint(hw->wiphy, reg->alpha2);
fe33eb39
LR		 1671 if (error)
1672 goto error_attach;
1673 }
5f8e077c 1674
db93e7b5
SB		 1675 /* Initialize LED control */
1676 ath_init_leds(sc);
8feceb67 1677
5f8e077c 1678
8feceb67 1679 return 0;
40b130a9
VT		 1680
1681error_attach:
1682 /* cleanup tx queues */
1683 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1684 if (ATH_TXQ_SETUP(sc, i))
1685 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1686
1687 ath9k_hw_detach(sc->sc_ah);
1688 ath9k_exit_debug(sc);
1689
8feceb67 1690 return error;
f078f209
LR		 1691}
1692
ff37e337
S		 1693int ath_reset(struct ath_softc *sc, bool retry_tx)
1694{
cbe61d8a 1695 struct ath_hw *ah = sc->sc_ah;
030bb495 1696 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1697 int r;
ff37e337
S		 1698
1699 ath9k_hw_set_interrupts(ah, 0);
043a0405 1700 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1701 ath_stoprecv(sc);
1702 ath_flushrecv(sc);
1703
1704 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1705 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 1706 if (r)
ff37e337 1707 DPRINTF(sc, ATH_DBG_FATAL,
6b45784f 1708 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S		 1709 spin_unlock_bh(&sc->sc_resetlock);
1710
1711 if (ath_startrecv(sc) != 0)
04bd4638 1712 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1713
1714 /*
1715 * We may be doing a reset in response to a request
1716 * that changes the channel so update any state that
1717 * might change as a result.
1718 */
ce111bad 1719 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1720
1721 ath_update_txpow(sc);
1722
1723 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1724 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 1725
17d7904d 1726 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 1727
1728 if (retry_tx) {
1729 int i;
1730 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1731 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1732 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1733 ath_txq_schedule(sc, &sc->tx.txq[i]);
1734 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1735 }
1736 }
1737 }
1738
ae8d2858 1739 return r;
ff37e337
S		 1740}
1741
1742/*
1743 * This function will allocate both the DMA descriptor structure, and the
1744 * buffers it contains. These are used to contain the descriptors used
1745 * by the system.
1746*/
1747int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1748 struct list_head *head, const char *name,
1749 int nbuf, int ndesc)
1750{
1751#define DS2PHYS(_dd, _ds) \
1752 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1753#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1754#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1755
1756 struct ath_desc *ds;
1757 struct ath_buf *bf;
1758 int i, bsize, error;
1759
04bd4638
S		 1760 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1761 name, nbuf, ndesc);
ff37e337 1762
b03a9db9 1763 INIT_LIST_HEAD(head);
ff37e337
S		 1764 /* ath_desc must be a multiple of DWORDs */
1765 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1766 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1767 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1768 error = -ENOMEM;
1769 goto fail;
1770 }
1771
ff37e337
S		 1772 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1773
1774 /*
1775 * Need additional DMA memory because we can't use
1776 * descriptors that cross the 4K page boundary. Assume
1777 * one skipped descriptor per 4K page.
1778 */
2660b81a 1779 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
ff37e337
S		 1780 u32 ndesc_skipped =
1781 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1782 u32 dma_len;
1783
1784 while (ndesc_skipped) {
1785 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1786 dd->dd_desc_len += dma_len;
1787
1788 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1789 };
1790 }
1791
1792 /* allocate descriptors */
7da3c55c 1793 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
f0e6ce13 1794 &dd->dd_desc_paddr, GFP_KERNEL);
ff37e337
S		 1795 if (dd->dd_desc == NULL) {
1796 error = -ENOMEM;
1797 goto fail;
1798 }
1799 ds = dd->dd_desc;
04bd4638 1800 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
ae459af1 1801 name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1802 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1803
1804 /* allocate buffers */
1805 bsize = sizeof(struct ath_buf) * nbuf;
f0e6ce13 1806 bf = kzalloc(bsize, GFP_KERNEL);
ff37e337
S		 1807 if (bf == NULL) {
1808 error = -ENOMEM;
1809 goto fail2;
1810 }
ff37e337
S		 1811 dd->dd_bufptr = bf;
1812
ff37e337
S		 1813 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1814 bf->bf_desc = ds;
1815 bf->bf_daddr = DS2PHYS(dd, ds);
1816
2660b81a 1817 if (!(sc->sc_ah->caps.hw_caps &
ff37e337
S		 1818 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1819 /*
1820 * Skip descriptor addresses which can cause 4KB
1821 * boundary crossing (addr + length) with a 32 dword
1822 * descriptor fetch.
1823 */
1824 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1825 ASSERT((caddr_t) bf->bf_desc <
1826 ((caddr_t) dd->dd_desc +
1827 dd->dd_desc_len));
1828
1829 ds += ndesc;
1830 bf->bf_desc = ds;
1831 bf->bf_daddr = DS2PHYS(dd, ds);
1832 }
1833 }
1834 list_add_tail(&bf->list, head);
1835 }
1836 return 0;
1837fail2:
7da3c55c
GJ		 1838 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1839 dd->dd_desc_paddr);
ff37e337
S		 1840fail:
1841 memset(dd, 0, sizeof(*dd));
1842 return error;
1843#undef ATH_DESC_4KB_BOUND_CHECK
1844#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1845#undef DS2PHYS
1846}
1847
1848void ath_descdma_cleanup(struct ath_softc *sc,
1849 struct ath_descdma *dd,
1850 struct list_head *head)
1851{
7da3c55c
GJ		 1852 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1853 dd->dd_desc_paddr);
ff37e337
S		 1854
1855 INIT_LIST_HEAD(head);
1856 kfree(dd->dd_bufptr);
1857 memset(dd, 0, sizeof(*dd));
1858}
1859
1860int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1861{
1862 int qnum;
1863
1864 switch (queue) {
1865 case 0:
b77f483f 1866 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1867 break;
1868 case 1:
b77f483f 1869 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 1870 break;
1871 case 2:
b77f483f 1872 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1873 break;
1874 case 3:
b77f483f 1875 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 1876 break;
1877 default:
b77f483f 1878 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1879 break;
1880 }
1881
1882 return qnum;
1883}
1884
1885int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1886{
1887 int qnum;
1888
1889 switch (queue) {
1890 case ATH9K_WME_AC_VO:
1891 qnum = 0;
1892 break;
1893 case ATH9K_WME_AC_VI:
1894 qnum = 1;
1895 break;
1896 case ATH9K_WME_AC_BE:
1897 qnum = 2;
1898 break;
1899 case ATH9K_WME_AC_BK:
1900 qnum = 3;
1901 break;
1902 default:
1903 qnum = -1;
1904 break;
1905 }
1906
1907 return qnum;
1908}
1909
5f8e077c
LR		 1910/* XXX: Remove me once we don't depend on ath9k_channel for all
1911 * this redundant data */
0e2dedf9
JM		 1912void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1913 struct ath9k_channel *ichan)
5f8e077c 1914{
5f8e077c
LR		 1915 struct ieee80211_channel *chan = hw->conf.channel;
1916 struct ieee80211_conf *conf = &hw->conf;
1917
1918 ichan->channel = chan->center_freq;
1919 ichan->chan = chan;
1920
1921 if (chan->band == IEEE80211_BAND_2GHZ) {
1922 ichan->chanmode = CHANNEL_G;
1923 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1924 } else {
1925 ichan->chanmode = CHANNEL_A;
1926 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1927 }
1928
1929 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1930
1931 if (conf_is_ht(conf)) {
1932 if (conf_is_ht40(conf))
1933 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1934
1935 ichan->chanmode = ath_get_extchanmode(sc, chan,
1936 conf->channel_type);
1937 }
1938}
1939
ff37e337
S		 1940/**********************/
1941/* mac80211 callbacks */
1942/**********************/
1943
8feceb67 1944static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1945{
bce048d7
JM		 1946 struct ath_wiphy *aphy = hw->priv;
1947 struct ath_softc *sc = aphy->sc;
8feceb67 1948 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1949 struct ath9k_channel *init_channel;
ae8d2858 1950 int r, pos;
f078f209 1951
04bd4638
S		 1952 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1953 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1954
141b38b6
S		 1955 mutex_lock(&sc->mutex);
1956
9580a222
JM		 1957 if (ath9k_wiphy_started(sc)) {
1958 if (sc->chan_idx == curchan->hw_value) {
1959 /*
1960 * Already on the operational channel, the new wiphy
1961 * can be marked active.
1962 */
1963 aphy->state = ATH_WIPHY_ACTIVE;
1964 ieee80211_wake_queues(hw);
1965 } else {
1966 /*
1967 * Another wiphy is on another channel, start the new
1968 * wiphy in paused state.
1969 */
1970 aphy->state = ATH_WIPHY_PAUSED;
1971 ieee80211_stop_queues(hw);
1972 }
1973 mutex_unlock(&sc->mutex);
1974 return 0;
1975 }
1976 aphy->state = ATH_WIPHY_ACTIVE;
1977
8feceb67 1978 /* setup initial channel */
f078f209 1979
5f8e077c 1980 pos = curchan->hw_value;
f078f209 1981
0e2dedf9 1982 sc->chan_idx = pos;
2660b81a 1983 init_channel = &sc->sc_ah->channels[pos];
0e2dedf9 1984 ath9k_update_ichannel(sc, hw, init_channel);
ff37e337
S		 1985
1986 /* Reset SERDES registers */
1987 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1988
1989 /*
1990 * The basic interface to setting the hardware in a good
1991 * state is ``reset''. On return the hardware is known to
1992 * be powered up and with interrupts disabled. This must
1993 * be followed by initialization of the appropriate bits
1994 * and then setup of the interrupt mask.
1995 */
1996 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1997 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1998 if (r) {
ff37e337 1999 DPRINTF(sc, ATH_DBG_FATAL,
6b45784f 2000 "Unable to reset hardware; reset status %d "
ae8d2858
LR		 2001 "(freq %u MHz)\n", r,
2002 curchan->center_freq);
ff37e337 2003 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 2004 goto mutex_unlock;
ff37e337
S		 2005 }
2006 spin_unlock_bh(&sc->sc_resetlock);
2007
2008 /*
2009 * This is needed only to setup initial state
2010 * but it's best done after a reset.
2011 */
2012 ath_update_txpow(sc);
8feceb67 2013
ff37e337
S		 2014 /*
2015 * Setup the hardware after reset:
2016 * The receive engine is set going.
2017 * Frame transmit is handled entirely
2018 * in the frame output path; there's nothing to do
2019 * here except setup the interrupt mask.
2020 */
2021 if (ath_startrecv(sc) != 0) {
1ffb0610 2022 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
141b38b6
S		 2023 r = -EIO;
2024 goto mutex_unlock;
f078f209 2025 }
8feceb67 2026
ff37e337 2027 /* Setup our intr mask. */
17d7904d 2028 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S		 2029 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2030 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2031
2660b81a 2032 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 2033 sc->imask |= ATH9K_INT_GTT;
ff37e337 2034
2660b81a 2035 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 2036 sc->imask |= ATH9K_INT_CST;
ff37e337 2037
ce111bad 2038 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 2039
2040 sc->sc_flags &= ~SC_OP_INVALID;
2041
2042 /* Disable BMISS interrupt when we're not associated */
17d7904d
S		 2043 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2044 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337 2045
bce048d7 2046 ieee80211_wake_queues(hw);
ff37e337 2047
e97275cb 2048#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
ae8d2858 2049 r = ath_start_rfkill_poll(sc);
500c064d 2050#endif
141b38b6
S		 2051
2052mutex_unlock:
2053 mutex_unlock(&sc->mutex);
2054
ae8d2858 2055 return r;
f078f209
LR		 2056}
2057
8feceb67
VT		 2058static int ath9k_tx(struct ieee80211_hw *hw,
2059 struct sk_buff *skb)
f078f209 2060{
528f0c6b 2061 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM		 2062 struct ath_wiphy *aphy = hw->priv;
2063 struct ath_softc *sc = aphy->sc;
528f0c6b 2064 struct ath_tx_control txctl;
8feceb67 2065 int hdrlen, padsize;
528f0c6b 2066
8089cc47 2067 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
ee166a0e
JM		 2068 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2069 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2070 goto exit;
2071 }
2072
9a23f9ca
JM		 2073 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2074 /*
2075 * We are using PS-Poll and mac80211 can request TX while in
2076 * power save mode. Need to wake up hardware for the TX to be
2077 * completed and if needed, also for RX of buffered frames.
2078 */
2079 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2080 ath9k_ps_wakeup(sc);
2081 ath9k_hw_setrxabort(sc->sc_ah, 0);
2082 if (ieee80211_is_pspoll(hdr->frame_control)) {
2083 DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a "
2084 "buffered frame\n");
2085 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2086 } else {
2087 DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n");
2088 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2089 }
2090 /*
2091 * The actual restore operation will happen only after
2092 * the sc_flags bit is cleared. We are just dropping
2093 * the ps_usecount here.
2094 */
2095 ath9k_ps_restore(sc);
2096 }
2097
528f0c6b 2098 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2099
8feceb67
VT		 2100 /*
2101 * As a temporary workaround, assign seq# here; this will likely need
2102 * to be cleaned up to work better with Beacon transmission and virtual
2103 * BSSes.
2104 */
2105 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2106 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2107 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2108 sc->tx.seq_no += 0x10;
8feceb67 2109 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2110 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2111 }
f078f209 2112
8feceb67
VT		 2113 /* Add the padding after the header if this is not already done */
2114 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2115 if (hdrlen & 3) {
2116 padsize = hdrlen % 4;
2117 if (skb_headroom(skb) < padsize)
2118 return -1;
2119 skb_push(skb, padsize);
2120 memmove(skb->data, skb->data + padsize, hdrlen);
2121 }
2122
528f0c6b
S		 2123 /* Check if a tx queue is available */
2124
2125 txctl.txq = ath_test_get_txq(sc, skb);
2126 if (!txctl.txq)
2127 goto exit;
2128
04bd4638 2129 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2130
c52f33d0 2131 if (ath_tx_start(hw, skb, &txctl) != 0) {
04bd4638 2132 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2133 goto exit;
8feceb67
VT		 2134 }
2135
528f0c6b
S		 2136 return 0;
2137exit:
2138 dev_kfree_skb_any(skb);
8feceb67 2139 return 0;
f078f209
LR		 2140}
2141
8feceb67 2142static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 2143{
bce048d7
JM		 2144 struct ath_wiphy *aphy = hw->priv;
2145 struct ath_softc *sc = aphy->sc;
f078f209 2146
9580a222
JM		 2147 aphy->state = ATH_WIPHY_INACTIVE;
2148
9c84b797 2149 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 2150 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
9c84b797
S		 2151 return;
2152 }
8feceb67 2153
141b38b6 2154 mutex_lock(&sc->mutex);
ff37e337 2155
bce048d7 2156 ieee80211_stop_queues(hw);
ff37e337 2157
9580a222
JM		 2158 if (ath9k_wiphy_started(sc)) {
2159 mutex_unlock(&sc->mutex);
2160 return; /* another wiphy still in use */
2161 }
2162
ff37e337
S		 2163 /* make sure h/w will not generate any interrupt
2164 * before setting the invalid flag. */
2165 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2166
2167 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2168 ath_drain_all_txq(sc, false);
ff37e337
S		 2169 ath_stoprecv(sc);
2170 ath9k_hw_phy_disable(sc->sc_ah);
2171 } else
b77f483f 2172 sc->rx.rxlink = NULL;
ff37e337
S		 2173
2174#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a 2175 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
ff37e337
S		 2176 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2177#endif
2178 /* disable HAL and put h/w to sleep */
2179 ath9k_hw_disable(sc->sc_ah);
2180 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2181
2182 sc->sc_flags |= SC_OP_INVALID;
500c064d 2183
141b38b6
S		 2184 mutex_unlock(&sc->mutex);
2185
04bd4638 2186 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2187}
2188
8feceb67
VT		 2189static int ath9k_add_interface(struct ieee80211_hw *hw,
2190 struct ieee80211_if_init_conf *conf)
f078f209 2191{
bce048d7
JM		 2192 struct ath_wiphy *aphy = hw->priv;
2193 struct ath_softc *sc = aphy->sc;
17d7904d 2194 struct ath_vif *avp = (void *)conf->vif->drv_priv;
d97809db 2195 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 2196 int ret = 0;
8feceb67 2197
141b38b6
S		 2198 mutex_lock(&sc->mutex);
2199
8ca21f01
JM		 2200 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2201 sc->nvifs > 0) {
2202 ret = -ENOBUFS;
2203 goto out;
2204 }
2205
8feceb67 2206 switch (conf->type) {
05c914fe 2207 case NL80211_IFTYPE_STATION:
d97809db 2208 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2209 break;
05c914fe 2210 case NL80211_IFTYPE_ADHOC:
05c914fe 2211 case NL80211_IFTYPE_AP:
9cb5412b 2212 case NL80211_IFTYPE_MESH_POINT:
2c3db3d5
JM		 2213 if (sc->nbcnvifs >= ATH_BCBUF) {
2214 ret = -ENOBUFS;
2215 goto out;
2216 }
9cb5412b 2217 ic_opmode = conf->type;
f078f209
LR		 2218 break;
2219 default:
2220 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2221 "Interface type %d not yet supported\n", conf->type);
2c3db3d5
JM		 2222 ret = -EOPNOTSUPP;
2223 goto out;
f078f209
LR		 2224 }
2225
17d7904d 2226 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 2227
17d7904d 2228 /* Set the VIF opmode */
5640b08e
S		 2229 avp->av_opmode = ic_opmode;
2230 avp->av_bslot = -1;
2231
2c3db3d5 2232 sc->nvifs++;
8ca21f01
JM		 2233
2234 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2235 ath9k_set_bssid_mask(hw);
2236
2c3db3d5
JM		 2237 if (sc->nvifs > 1)
2238 goto out; /* skip global settings for secondary vif */
2239
b238e90e 2240 if (ic_opmode == NL80211_IFTYPE_AP) {
5640b08e 2241 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
b238e90e
S		 2242 sc->sc_flags |= SC_OP_TSF_RESET;
2243 }
5640b08e 2244
5640b08e 2245 /* Set the device opmode */
2660b81a 2246 sc->sc_ah->opmode = ic_opmode;
5640b08e 2247
4e30ffa2
VN		 2248 /*
2249 * Enable MIB interrupts when there are hardware phy counters.
2250 * Note we only do this (at the moment) for station mode.
2251 */
4af9cf4f 2252 if ((conf->type == NL80211_IFTYPE_STATION) ||
9cb5412b
PE		 2253 (conf->type == NL80211_IFTYPE_ADHOC) ||
2254 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
4af9cf4f
S		 2255 if (ath9k_hw_phycounters(sc->sc_ah))
2256 sc->imask |= ATH9K_INT_MIB;
2257 sc->imask |= ATH9K_INT_TSFOOR;
2258 }
2259
17d7904d 2260 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 2261
415f738e
S		 2262 if (conf->type == NL80211_IFTYPE_AP)
2263 ath_start_ani(sc);
6f255425 2264
2c3db3d5 2265out:
141b38b6 2266 mutex_unlock(&sc->mutex);
2c3db3d5 2267 return ret;
f078f209
LR		 2268}
2269
8feceb67
VT		 2270static void ath9k_remove_interface(struct ieee80211_hw *hw,
2271 struct ieee80211_if_init_conf *conf)
f078f209 2272{
bce048d7
JM		 2273 struct ath_wiphy *aphy = hw->priv;
2274 struct ath_softc *sc = aphy->sc;
17d7904d 2275 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2c3db3d5 2276 int i;
f078f209 2277
04bd4638 2278 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2279
141b38b6
S		 2280 mutex_lock(&sc->mutex);
2281
6f255425 2282 /* Stop ANI */
17d7904d 2283 del_timer_sync(&sc->ani.timer);
580f0b8a 2284
8feceb67 2285 /* Reclaim beacon resources */
9cb5412b
PE		 2286 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2287 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2288 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
b77f483f 2289 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2290 ath_beacon_return(sc, avp);
580f0b8a 2291 }
f078f209 2292
8feceb67 2293 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2294
2c3db3d5
JM		 2295 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2296 if (sc->beacon.bslot[i] == conf->vif) {
2297 printk(KERN_DEBUG "%s: vif had allocated beacon "
2298 "slot\n", __func__);
2299 sc->beacon.bslot[i] = NULL;
c52f33d0 2300 sc->beacon.bslot_aphy[i] = NULL;
2c3db3d5
JM		 2301 }
2302 }
2303
17d7904d 2304 sc->nvifs--;
141b38b6
S		 2305
2306 mutex_unlock(&sc->mutex);
f078f209
LR		 2307}
2308
e8975581 2309static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2310{
bce048d7
JM		 2311 struct ath_wiphy *aphy = hw->priv;
2312 struct ath_softc *sc = aphy->sc;
e8975581 2313 struct ieee80211_conf *conf = &hw->conf;
8782b41d 2314 struct ath_hw *ah = sc->sc_ah;
f078f209 2315
aa33de09 2316 mutex_lock(&sc->mutex);
141b38b6 2317
3cbb5dd7
VN		 2318 if (changed & IEEE80211_CONF_CHANGE_PS) {
2319 if (conf->flags & IEEE80211_CONF_PS) {
8782b41d
VN		 2320 if (!(ah->caps.hw_caps &
2321 ATH9K_HW_CAP_AUTOSLEEP)) {
2322 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2323 sc->imask |= ATH9K_INT_TIM_TIMER;
2324 ath9k_hw_set_interrupts(sc->sc_ah,
2325 sc->imask);
2326 }
2327 ath9k_hw_setrxabort(sc->sc_ah, 1);
3cbb5dd7 2328 }
3cbb5dd7
VN		 2329 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2330 } else {
2331 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8782b41d
VN		 2332 if (!(ah->caps.hw_caps &
2333 ATH9K_HW_CAP_AUTOSLEEP)) {
2334 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca
JM		 2335 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2336 SC_OP_WAIT_FOR_CAB |
2337 SC_OP_WAIT_FOR_PSPOLL_DATA |
2338 SC_OP_WAIT_FOR_TX_ACK);
8782b41d
VN		 2339 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2340 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2341 ath9k_hw_set_interrupts(sc->sc_ah,
2342 sc->imask);
2343 }
3cbb5dd7
VN		 2344 }
2345 }
2346 }
2347
4797938c 2348 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2349 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2350 int pos = curchan->hw_value;
ae5eb026 2351
0e2dedf9
JM		 2352 aphy->chan_idx = pos;
2353 aphy->chan_is_ht = conf_is_ht(conf);
2354
8089cc47
JM		 2355 if (aphy->state == ATH_WIPHY_SCAN ||
2356 aphy->state == ATH_WIPHY_ACTIVE)
2357 ath9k_wiphy_pause_all_forced(sc, aphy);
2358 else {
2359 /*
2360 * Do not change operational channel based on a paused
2361 * wiphy changes.
2362 */
2363 goto skip_chan_change;
2364 }
0e2dedf9 2365
04bd4638
S		 2366 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2367 curchan->center_freq);
f078f209 2368
5f8e077c 2369 /* XXX: remove me eventualy */
0e2dedf9 2370 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 2371
ecf70441 2372 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2373
0e2dedf9 2374 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
04bd4638 2375 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2376 mutex_unlock(&sc->mutex);
e11602b7
S		 2377 return -EINVAL;
2378 }
094d05dc 2379 }
f078f209 2380
8089cc47 2381skip_chan_change:
5c020dc6 2382 if (changed & IEEE80211_CONF_CHANGE_POWER)
17d7904d 2383 sc->config.txpowlimit = 2 * conf->power_level;
f078f209 2384
aa33de09 2385 mutex_unlock(&sc->mutex);
141b38b6 2386
f078f209
LR		 2387 return 0;
2388}
2389
8feceb67
VT		 2390#define SUPPORTED_FILTERS \
2391 (FIF_PROMISC_IN_BSS | \
2392 FIF_ALLMULTI | \
2393 FIF_CONTROL | \
2394 FIF_OTHER_BSS | \
2395 FIF_BCN_PRBRESP_PROMISC | \
2396 FIF_FCSFAIL)
c83be688 2397
8feceb67
VT		 2398/* FIXME: sc->sc_full_reset ? */
2399static void ath9k_configure_filter(struct ieee80211_hw *hw,
2400 unsigned int changed_flags,
2401 unsigned int *total_flags,
2402 int mc_count,
2403 struct dev_mc_list *mclist)
2404{
bce048d7
JM		 2405 struct ath_wiphy *aphy = hw->priv;
2406 struct ath_softc *sc = aphy->sc;
8feceb67 2407 u32 rfilt;
f078f209 2408
8feceb67
VT		 2409 changed_flags &= SUPPORTED_FILTERS;
2410 *total_flags &= SUPPORTED_FILTERS;
f078f209 2411
b77f483f 2412 sc->rx.rxfilter = *total_flags;
8feceb67
VT		 2413 rfilt = ath_calcrxfilter(sc);
2414 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
f078f209 2415
b77f483f 2416 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
8feceb67 2417}
f078f209 2418
8feceb67
VT		 2419static void ath9k_sta_notify(struct ieee80211_hw *hw,
2420 struct ieee80211_vif *vif,
2421 enum sta_notify_cmd cmd,
17741cdc 2422 struct ieee80211_sta *sta)
8feceb67 2423{
bce048d7
JM		 2424 struct ath_wiphy *aphy = hw->priv;
2425 struct ath_softc *sc = aphy->sc;
f078f209 2426
8feceb67
VT		 2427 switch (cmd) {
2428 case STA_NOTIFY_ADD:
5640b08e 2429 ath_node_attach(sc, sta);
8feceb67
VT		 2430 break;
2431 case STA_NOTIFY_REMOVE:
b5aa9bf9 2432 ath_node_detach(sc, sta);
8feceb67
VT		 2433 break;
2434 default:
2435 break;
2436 }
f078f209
LR		 2437}
2438
141b38b6 2439static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 2440 const struct ieee80211_tx_queue_params *params)
f078f209 2441{
bce048d7
JM		 2442 struct ath_wiphy *aphy = hw->priv;
2443 struct ath_softc *sc = aphy->sc;
8feceb67
VT		 2444 struct ath9k_tx_queue_info qi;
2445 int ret = 0, qnum;
f078f209 2446
8feceb67
VT		 2447 if (queue >= WME_NUM_AC)
2448 return 0;
f078f209 2449
141b38b6
S		 2450 mutex_lock(&sc->mutex);
2451
1ffb0610
S		 2452 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2453
8feceb67
VT		 2454 qi.tqi_aifs = params->aifs;
2455 qi.tqi_cwmin = params->cw_min;
2456 qi.tqi_cwmax = params->cw_max;
2457 qi.tqi_burstTime = params->txop;
2458 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2459
8feceb67 2460 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2461 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2462 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2463 queue, qnum, params->aifs, params->cw_min,
2464 params->cw_max, params->txop);
f078f209 2465
8feceb67
VT		 2466 ret = ath_txq_update(sc, qnum, &qi);
2467 if (ret)
04bd4638 2468 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2469
141b38b6
S		 2470 mutex_unlock(&sc->mutex);
2471
8feceb67
VT		 2472 return ret;
2473}
f078f209 2474
8feceb67
VT		 2475static int ath9k_set_key(struct ieee80211_hw *hw,
2476 enum set_key_cmd cmd,
dc822b5d
JB		 2477 struct ieee80211_vif *vif,
2478 struct ieee80211_sta *sta,
8feceb67
VT		 2479 struct ieee80211_key_conf *key)
2480{
bce048d7
JM		 2481 struct ath_wiphy *aphy = hw->priv;
2482 struct ath_softc *sc = aphy->sc;
8feceb67 2483 int ret = 0;
f078f209 2484
b3bd89ce
JM		 2485 if (modparam_nohwcrypt)
2486 return -ENOSPC;
2487
141b38b6 2488 mutex_lock(&sc->mutex);
3cbb5dd7 2489 ath9k_ps_wakeup(sc);
d8baa939 2490 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 2491
8feceb67
VT		 2492 switch (cmd) {
2493 case SET_KEY:
3f53dd64 2494 ret = ath_key_config(sc, vif, sta, key);
6ace2891
JM		 2495 if (ret >= 0) {
2496 key->hw_key_idx = ret;
8feceb67
VT		 2497 /* push IV and Michael MIC generation to stack */
2498 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2499 if (key->alg == ALG_TKIP)
2500 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2501 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2502 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2503 ret = 0;
8feceb67
VT		 2504 }
2505 break;
2506 case DISABLE_KEY:
2507 ath_key_delete(sc, key);
8feceb67
VT		 2508 break;
2509 default:
2510 ret = -EINVAL;
2511 }
f078f209 2512
3cbb5dd7 2513 ath9k_ps_restore(sc);
141b38b6
S		 2514 mutex_unlock(&sc->mutex);
2515
8feceb67
VT		 2516 return ret;
2517}
f078f209 2518
8feceb67
VT		 2519static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2520 struct ieee80211_vif *vif,
2521 struct ieee80211_bss_conf *bss_conf,
2522 u32 changed)
2523{
bce048d7
JM		 2524 struct ath_wiphy *aphy = hw->priv;
2525 struct ath_softc *sc = aphy->sc;
2d0ddec5
JB		 2526 struct ath_hw *ah = sc->sc_ah;
2527 struct ath_vif *avp = (void *)vif->drv_priv;
2528 u32 rfilt = 0;
2529 int error, i;
f078f209 2530
141b38b6
S		 2531 mutex_lock(&sc->mutex);
2532
2d0ddec5
JB		 2533 /*
2534 * TODO: Need to decide which hw opmode to use for
2535 * multi-interface cases
2536 * XXX: This belongs into add_interface!
2537 */
2538 if (vif->type == NL80211_IFTYPE_AP &&
2539 ah->opmode != NL80211_IFTYPE_AP) {
2540 ah->opmode = NL80211_IFTYPE_STATION;
2541 ath9k_hw_setopmode(ah);
2542 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2543 sc->curaid = 0;
2544 ath9k_hw_write_associd(sc);
2545 /* Request full reset to get hw opmode changed properly */
2546 sc->sc_flags |= SC_OP_FULL_RESET;
2547 }
2548
2549 if ((changed & BSS_CHANGED_BSSID) &&
2550 !is_zero_ether_addr(bss_conf->bssid)) {
2551 switch (vif->type) {
2552 case NL80211_IFTYPE_STATION:
2553 case NL80211_IFTYPE_ADHOC:
2554 case NL80211_IFTYPE_MESH_POINT:
2555 /* Set BSSID */
2556 memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2557 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2558 sc->curaid = 0;
2559 ath9k_hw_write_associd(sc);
2560
2561 /* Set aggregation protection mode parameters */
2562 sc->config.ath_aggr_prot = 0;
2563
2564 DPRINTF(sc, ATH_DBG_CONFIG,
2565 "RX filter 0x%x bssid %pM aid 0x%x\n",
2566 rfilt, sc->curbssid, sc->curaid);
2567
2568 /* need to reconfigure the beacon */
2569 sc->sc_flags &= ~SC_OP_BEACONS ;
2570
2571 break;
2572 default:
2573 break;
2574 }
2575 }
2576
2577 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2578 (vif->type == NL80211_IFTYPE_AP) ||
2579 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2580 if ((changed & BSS_CHANGED_BEACON) ||
2581 (changed & BSS_CHANGED_BEACON_ENABLED &&
2582 bss_conf->enable_beacon)) {
2583 /*
2584 * Allocate and setup the beacon frame.
2585 *
2586 * Stop any previous beacon DMA. This may be
2587 * necessary, for example, when an ibss merge
2588 * causes reconfiguration; we may be called
2589 * with beacon transmission active.
2590 */
2591 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2592
2593 error = ath_beacon_alloc(aphy, vif);
2594 if (!error)
2595 ath_beacon_config(sc, vif);
2596 }
2597 }
2598
2599 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2600 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2601 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2602 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2603 ath9k_hw_keysetmac(sc->sc_ah,
2604 (u16)i,
2605 sc->curbssid);
2606 }
2607
2608 /* Only legacy IBSS for now */
2609 if (vif->type == NL80211_IFTYPE_ADHOC)
2610 ath_update_chainmask(sc, 0);
2611
8feceb67 2612 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2613 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2614 bss_conf->use_short_preamble);
2615 if (bss_conf->use_short_preamble)
2616 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2617 else
2618 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2619 }
f078f209 2620
8feceb67 2621 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2622 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2623 bss_conf->use_cts_prot);
2624 if (bss_conf->use_cts_prot &&
2625 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2626 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2627 else
2628 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2629 }
f078f209 2630
8feceb67 2631 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2632 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2633 bss_conf->assoc);
5640b08e 2634 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 2635 }
141b38b6 2636
57c4d7b4
JB		 2637 /*
2638 * The HW TSF has to be reset when the beacon interval changes.
2639 * We set the flag here, and ath_beacon_config_ap() would take this
2640 * into account when it gets called through the subsequent
2641 * config_interface() call - with IFCC_BEACON in the changed field.
2642 */
2643
2644 if (changed & BSS_CHANGED_BEACON_INT) {
2645 sc->sc_flags |= SC_OP_TSF_RESET;
2646 sc->beacon_interval = bss_conf->beacon_int;
2647 }
2648
141b38b6 2649 mutex_unlock(&sc->mutex);
8feceb67 2650}
f078f209 2651
8feceb67
VT		 2652static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2653{
2654 u64 tsf;
bce048d7
JM		 2655 struct ath_wiphy *aphy = hw->priv;
2656 struct ath_softc *sc = aphy->sc;
f078f209 2657
141b38b6
S		 2658 mutex_lock(&sc->mutex);
2659 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2660 mutex_unlock(&sc->mutex);
f078f209 2661
8feceb67
VT		 2662 return tsf;
2663}
f078f209 2664
3b5d665b
AF		 2665static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2666{
bce048d7
JM		 2667 struct ath_wiphy *aphy = hw->priv;
2668 struct ath_softc *sc = aphy->sc;
3b5d665b 2669
141b38b6
S		 2670 mutex_lock(&sc->mutex);
2671 ath9k_hw_settsf64(sc->sc_ah, tsf);
2672 mutex_unlock(&sc->mutex);
3b5d665b
AF		 2673}
2674
8feceb67
VT		 2675static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2676{
bce048d7
JM		 2677 struct ath_wiphy *aphy = hw->priv;
2678 struct ath_softc *sc = aphy->sc;
c83be688 2679
141b38b6
S		 2680 mutex_lock(&sc->mutex);
2681 ath9k_hw_reset_tsf(sc->sc_ah);
2682 mutex_unlock(&sc->mutex);
8feceb67 2683}
f078f209 2684
8feceb67 2685static int ath9k_ampdu_action(struct ieee80211_hw *hw,
141b38b6
S		 2686 enum ieee80211_ampdu_mlme_action action,
2687 struct ieee80211_sta *sta,
2688 u16 tid, u16 *ssn)
8feceb67 2689{
bce048d7
JM		 2690 struct ath_wiphy *aphy = hw->priv;
2691 struct ath_softc *sc = aphy->sc;
8feceb67 2692 int ret = 0;
f078f209 2693
8feceb67
VT		 2694 switch (action) {
2695 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2696 if (!(sc->sc_flags & SC_OP_RXAGGR))
2697 ret = -ENOTSUPP;
8feceb67
VT		 2698 break;
2699 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2700 break;
2701 case IEEE80211_AMPDU_TX_START:
b5aa9bf9 2702 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
8feceb67
VT		 2703 if (ret < 0)
2704 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2705 "Unable to start TX aggregation\n");
8feceb67 2706 else
17741cdc 2707 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2708 break;
2709 case IEEE80211_AMPDU_TX_STOP:
b5aa9bf9 2710 ret = ath_tx_aggr_stop(sc, sta, tid);
8feceb67
VT		 2711 if (ret < 0)
2712 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2713 "Unable to stop TX aggregation\n");
f078f209 2714
17741cdc 2715 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2716 break;
b1720231 2717 case IEEE80211_AMPDU_TX_OPERATIONAL:
8469cdef
S		 2718 ath_tx_aggr_resume(sc, sta, tid);
2719 break;
8feceb67 2720 default:
04bd4638 2721 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2722 }
2723
2724 return ret;
f078f209
LR		 2725}
2726
0c98de65
S		 2727static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2728{
bce048d7
JM		 2729 struct ath_wiphy *aphy = hw->priv;
2730 struct ath_softc *sc = aphy->sc;
0c98de65 2731
8089cc47
JM		 2732 if (ath9k_wiphy_scanning(sc)) {
2733 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2734 "same time\n");
2735 /*
2736 * Do not allow the concurrent scanning state for now. This
2737 * could be improved with scanning control moved into ath9k.
2738 */
2739 return;
2740 }
2741
2742 aphy->state = ATH_WIPHY_SCAN;
2743 ath9k_wiphy_pause_all_forced(sc, aphy);
2744
0c98de65
S		 2745 mutex_lock(&sc->mutex);
2746 sc->sc_flags |= SC_OP_SCANNING;
2747 mutex_unlock(&sc->mutex);
2748}
2749
2750static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2751{
bce048d7
JM		 2752 struct ath_wiphy *aphy = hw->priv;
2753 struct ath_softc *sc = aphy->sc;
0c98de65
S		 2754
2755 mutex_lock(&sc->mutex);
8089cc47 2756 aphy->state = ATH_WIPHY_ACTIVE;
0c98de65 2757 sc->sc_flags &= ~SC_OP_SCANNING;
9c07a777 2758 sc->sc_flags |= SC_OP_FULL_RESET;
0c98de65
S		 2759 mutex_unlock(&sc->mutex);
2760}
2761
6baff7f9 2762struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2763 .tx = ath9k_tx,
2764 .start = ath9k_start,
2765 .stop = ath9k_stop,
2766 .add_interface = ath9k_add_interface,
2767 .remove_interface = ath9k_remove_interface,
2768 .config = ath9k_config,
8feceb67 2769 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2770 .sta_notify = ath9k_sta_notify,
2771 .conf_tx = ath9k_conf_tx,
8feceb67 2772 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2773 .set_key = ath9k_set_key,
8feceb67 2774 .get_tsf = ath9k_get_tsf,
3b5d665b 2775 .set_tsf = ath9k_set_tsf,
8feceb67 2776 .reset_tsf = ath9k_reset_tsf,
4233df6b 2777 .ampdu_action = ath9k_ampdu_action,
0c98de65
S		 2778 .sw_scan_start = ath9k_sw_scan_start,
2779 .sw_scan_complete = ath9k_sw_scan_complete,
8feceb67
VT		 2780};
2781
392dff83
BP		 2782static struct {
2783 u32 version;
2784 const char * name;
2785} ath_mac_bb_names[] = {
2786 { AR_SREV_VERSION_5416_PCI, "5416" },
2787 { AR_SREV_VERSION_5416_PCIE, "5418" },
2788 { AR_SREV_VERSION_9100, "9100" },
2789 { AR_SREV_VERSION_9160, "9160" },
2790 { AR_SREV_VERSION_9280, "9280" },
2791 { AR_SREV_VERSION_9285, "9285" }
2792};
2793
2794static struct {
2795 u16 version;
2796 const char * name;
2797} ath_rf_names[] = {
2798 { 0, "5133" },
2799 { AR_RAD5133_SREV_MAJOR, "5133" },
2800 { AR_RAD5122_SREV_MAJOR, "5122" },
2801 { AR_RAD2133_SREV_MAJOR, "2133" },
2802 { AR_RAD2122_SREV_MAJOR, "2122" }
2803};
2804
2805/*
2806 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2807 */
6baff7f9 2808const char *
392dff83
BP		 2809ath_mac_bb_name(u32 mac_bb_version)
2810{
2811 int i;
2812
2813 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2814 if (ath_mac_bb_names[i].version == mac_bb_version) {
2815 return ath_mac_bb_names[i].name;
2816 }
2817 }
2818
2819 return "????";
2820}
2821
2822/*
2823 * Return the RF name. "????" is returned if the RF is unknown.
2824 */
6baff7f9 2825const char *
392dff83
BP		 2826ath_rf_name(u16 rf_version)
2827{
2828 int i;
2829
2830 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2831 if (ath_rf_names[i].version == rf_version) {
2832 return ath_rf_names[i].name;
2833 }
2834 }
2835
2836 return "????";
2837}
2838
6baff7f9 2839static int __init ath9k_init(void)
f078f209 2840{
ca8a8560
VT		 2841 int error;
2842
ca8a8560
VT		 2843 /* Register rate control algorithm */
2844 error = ath_rate_control_register();
2845 if (error != 0) {
2846 printk(KERN_ERR
b51bb3cd
LR		 2847 "ath9k: Unable to register rate control "
2848 "algorithm: %d\n",
ca8a8560 2849 error);
6baff7f9 2850 goto err_out;
ca8a8560
VT		 2851 }
2852
19d8bc22
GJ		 2853 error = ath9k_debug_create_root();
2854 if (error) {
2855 printk(KERN_ERR
2856 "ath9k: Unable to create debugfs root: %d\n",
2857 error);
2858 goto err_rate_unregister;
2859 }
2860
6baff7f9
GJ		 2861 error = ath_pci_init();
2862 if (error < 0) {
f078f209 2863 printk(KERN_ERR
b51bb3cd 2864 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9 2865 error = -ENODEV;
19d8bc22 2866 goto err_remove_root;
f078f209
LR		 2867 }
2868
09329d37
GJ		 2869 error = ath_ahb_init();
2870 if (error < 0) {
2871 error = -ENODEV;
2872 goto err_pci_exit;
2873 }
2874
f078f209 2875 return 0;
6baff7f9 2876
09329d37
GJ		 2877 err_pci_exit:
2878 ath_pci_exit();
2879
19d8bc22
GJ		 2880 err_remove_root:
2881 ath9k_debug_remove_root();
6baff7f9
GJ		 2882 err_rate_unregister:
2883 ath_rate_control_unregister();
2884 err_out:
2885 return error;
f078f209 2886}
6baff7f9 2887module_init(ath9k_init);
f078f209 2888
6baff7f9 2889static void __exit ath9k_exit(void)
f078f209 2890{
09329d37 2891 ath_ahb_exit();
6baff7f9 2892 ath_pci_exit();
19d8bc22 2893 ath9k_debug_remove_root();
ca8a8560 2894 ath_rate_control_unregister();
04bd4638 2895 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 2896}
6baff7f9 2897module_exit(ath9k_exit);
Linux kernel - Deliverables
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