Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 | 17 | #include <linux/nl80211.h> |
69081624 | 18 | #include <linux/delay.h> |
394cf0a1 | 19 | #include "ath9k.h" |
af03abec | 20 | #include "btcoex.h" |
f078f209 | 21 | |
ff37e337 S |
22 | static u8 parse_mpdudensity(u8 mpdudensity) |
23 | { | |
24 | /* | |
25 | * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": | |
26 | * 0 for no restriction | |
27 | * 1 for 1/4 us | |
28 | * 2 for 1/2 us | |
29 | * 3 for 1 us | |
30 | * 4 for 2 us | |
31 | * 5 for 4 us | |
32 | * 6 for 8 us | |
33 | * 7 for 16 us | |
34 | */ | |
35 | switch (mpdudensity) { | |
36 | case 0: | |
37 | return 0; | |
38 | case 1: | |
39 | case 2: | |
40 | case 3: | |
41 | /* Our lower layer calculations limit our precision to | |
42 | 1 microsecond */ | |
43 | return 1; | |
44 | case 4: | |
45 | return 2; | |
46 | case 5: | |
47 | return 4; | |
48 | case 6: | |
49 | return 8; | |
50 | case 7: | |
51 | return 16; | |
52 | default: | |
53 | return 0; | |
54 | } | |
55 | } | |
56 | ||
69081624 VT |
57 | static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq) |
58 | { | |
59 | bool pending = false; | |
60 | ||
61 | spin_lock_bh(&txq->axq_lock); | |
62 | ||
63 | if (txq->axq_depth || !list_empty(&txq->axq_acq)) | |
64 | pending = true; | |
69081624 VT |
65 | |
66 | spin_unlock_bh(&txq->axq_lock); | |
67 | return pending; | |
68 | } | |
69 | ||
6d79cb4c | 70 | static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) |
8c77a569 LR |
71 | { |
72 | unsigned long flags; | |
73 | bool ret; | |
74 | ||
9ecdef4b LR |
75 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
76 | ret = ath9k_hw_setpower(sc->sc_ah, mode); | |
77 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
8c77a569 LR |
78 | |
79 | return ret; | |
80 | } | |
81 | ||
a91d75ae LR |
82 | void ath9k_ps_wakeup(struct ath_softc *sc) |
83 | { | |
898c914a | 84 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
a91d75ae | 85 | unsigned long flags; |
fbb078fc | 86 | enum ath9k_power_mode power_mode; |
a91d75ae LR |
87 | |
88 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
89 | if (++sc->ps_usecount != 1) | |
90 | goto unlock; | |
91 | ||
fbb078fc | 92 | power_mode = sc->sc_ah->power_mode; |
9ecdef4b | 93 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); |
a91d75ae | 94 | |
898c914a FF |
95 | /* |
96 | * While the hardware is asleep, the cycle counters contain no | |
97 | * useful data. Better clear them now so that they don't mess up | |
98 | * survey data results. | |
99 | */ | |
fbb078fc FF |
100 | if (power_mode != ATH9K_PM_AWAKE) { |
101 | spin_lock(&common->cc_lock); | |
102 | ath_hw_cycle_counters_update(common); | |
103 | memset(&common->cc_survey, 0, sizeof(common->cc_survey)); | |
104 | spin_unlock(&common->cc_lock); | |
105 | } | |
898c914a | 106 | |
a91d75ae LR |
107 | unlock: |
108 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
109 | } | |
110 | ||
111 | void ath9k_ps_restore(struct ath_softc *sc) | |
112 | { | |
898c914a | 113 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
a91d75ae LR |
114 | unsigned long flags; |
115 | ||
116 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
117 | if (--sc->ps_usecount != 0) | |
118 | goto unlock; | |
119 | ||
898c914a FF |
120 | spin_lock(&common->cc_lock); |
121 | ath_hw_cycle_counters_update(common); | |
122 | spin_unlock(&common->cc_lock); | |
123 | ||
1dbfd9d4 VN |
124 | if (sc->ps_idle) |
125 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); | |
126 | else if (sc->ps_enabled && | |
127 | !(sc->ps_flags & (PS_WAIT_FOR_BEACON | | |
1b04b930 S |
128 | PS_WAIT_FOR_CAB | |
129 | PS_WAIT_FOR_PSPOLL_DATA | | |
130 | PS_WAIT_FOR_TX_ACK))) | |
9ecdef4b | 131 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP); |
a91d75ae LR |
132 | |
133 | unlock: | |
134 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
135 | } | |
136 | ||
05c0be2f | 137 | void ath_start_ani(struct ath_common *common) |
5ee08656 FF |
138 | { |
139 | struct ath_hw *ah = common->ah; | |
140 | unsigned long timestamp = jiffies_to_msecs(jiffies); | |
141 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
142 | ||
143 | if (!(sc->sc_flags & SC_OP_ANI_RUN)) | |
144 | return; | |
145 | ||
146 | if (sc->sc_flags & SC_OP_OFFCHANNEL) | |
147 | return; | |
148 | ||
149 | common->ani.longcal_timer = timestamp; | |
150 | common->ani.shortcal_timer = timestamp; | |
151 | common->ani.checkani_timer = timestamp; | |
152 | ||
153 | mod_timer(&common->ani.timer, | |
154 | jiffies + | |
155 | msecs_to_jiffies((u32)ah->config.ani_poll_interval)); | |
156 | } | |
157 | ||
3430098a FF |
158 | static void ath_update_survey_nf(struct ath_softc *sc, int channel) |
159 | { | |
160 | struct ath_hw *ah = sc->sc_ah; | |
161 | struct ath9k_channel *chan = &ah->channels[channel]; | |
162 | struct survey_info *survey = &sc->survey[channel]; | |
163 | ||
164 | if (chan->noisefloor) { | |
165 | survey->filled |= SURVEY_INFO_NOISE_DBM; | |
f749b946 | 166 | survey->noise = ath9k_hw_getchan_noise(ah, chan); |
3430098a FF |
167 | } |
168 | } | |
169 | ||
cb8d61de FF |
170 | /* |
171 | * Updates the survey statistics and returns the busy time since last | |
172 | * update in %, if the measurement duration was long enough for the | |
173 | * result to be useful, -1 otherwise. | |
174 | */ | |
175 | static int ath_update_survey_stats(struct ath_softc *sc) | |
3430098a FF |
176 | { |
177 | struct ath_hw *ah = sc->sc_ah; | |
178 | struct ath_common *common = ath9k_hw_common(ah); | |
179 | int pos = ah->curchan - &ah->channels[0]; | |
180 | struct survey_info *survey = &sc->survey[pos]; | |
181 | struct ath_cycle_counters *cc = &common->cc_survey; | |
182 | unsigned int div = common->clockrate * 1000; | |
cb8d61de | 183 | int ret = 0; |
3430098a | 184 | |
0845735e | 185 | if (!ah->curchan) |
cb8d61de | 186 | return -1; |
0845735e | 187 | |
898c914a FF |
188 | if (ah->power_mode == ATH9K_PM_AWAKE) |
189 | ath_hw_cycle_counters_update(common); | |
3430098a FF |
190 | |
191 | if (cc->cycles > 0) { | |
192 | survey->filled |= SURVEY_INFO_CHANNEL_TIME | | |
193 | SURVEY_INFO_CHANNEL_TIME_BUSY | | |
194 | SURVEY_INFO_CHANNEL_TIME_RX | | |
195 | SURVEY_INFO_CHANNEL_TIME_TX; | |
196 | survey->channel_time += cc->cycles / div; | |
197 | survey->channel_time_busy += cc->rx_busy / div; | |
198 | survey->channel_time_rx += cc->rx_frame / div; | |
199 | survey->channel_time_tx += cc->tx_frame / div; | |
200 | } | |
cb8d61de FF |
201 | |
202 | if (cc->cycles < div) | |
203 | return -1; | |
204 | ||
205 | if (cc->cycles > 0) | |
206 | ret = cc->rx_busy * 100 / cc->cycles; | |
207 | ||
3430098a FF |
208 | memset(cc, 0, sizeof(*cc)); |
209 | ||
210 | ath_update_survey_nf(sc, pos); | |
cb8d61de FF |
211 | |
212 | return ret; | |
3430098a FF |
213 | } |
214 | ||
9adcf440 | 215 | static void __ath_cancel_work(struct ath_softc *sc) |
ff37e337 | 216 | { |
5ee08656 FF |
217 | cancel_work_sync(&sc->paprd_work); |
218 | cancel_work_sync(&sc->hw_check_work); | |
219 | cancel_delayed_work_sync(&sc->tx_complete_work); | |
181fb18d | 220 | cancel_delayed_work_sync(&sc->hw_pll_work); |
9adcf440 | 221 | } |
5ee08656 | 222 | |
9adcf440 FF |
223 | static void ath_cancel_work(struct ath_softc *sc) |
224 | { | |
225 | __ath_cancel_work(sc); | |
226 | cancel_work_sync(&sc->hw_reset_work); | |
227 | } | |
3cbb5dd7 | 228 | |
9adcf440 FF |
229 | static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush) |
230 | { | |
231 | struct ath_hw *ah = sc->sc_ah; | |
232 | struct ath_common *common = ath9k_hw_common(ah); | |
233 | bool ret; | |
6a6733f2 | 234 | |
9adcf440 | 235 | ieee80211_stop_queues(sc->hw); |
5e848f78 | 236 | |
9adcf440 FF |
237 | sc->hw_busy_count = 0; |
238 | del_timer_sync(&common->ani.timer); | |
ff37e337 | 239 | |
9adcf440 FF |
240 | ath9k_debug_samp_bb_mac(sc); |
241 | ath9k_hw_disable_interrupts(ah); | |
8b3f4616 | 242 | |
9adcf440 | 243 | ret = ath_drain_all_txq(sc, retry_tx); |
ff37e337 | 244 | |
9adcf440 FF |
245 | if (!ath_stoprecv(sc)) |
246 | ret = false; | |
c0d7c7af | 247 | |
9adcf440 FF |
248 | if (!flush) { |
249 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
250 | ath_rx_tasklet(sc, 0, true); | |
251 | ath_rx_tasklet(sc, 0, false); | |
252 | } else { | |
253 | ath_flushrecv(sc); | |
254 | } | |
20bd2a09 | 255 | |
9adcf440 FF |
256 | return ret; |
257 | } | |
ff37e337 | 258 | |
9adcf440 FF |
259 | static bool ath_complete_reset(struct ath_softc *sc, bool start) |
260 | { | |
261 | struct ath_hw *ah = sc->sc_ah; | |
262 | struct ath_common *common = ath9k_hw_common(ah); | |
c0d7c7af | 263 | |
c0d7c7af | 264 | if (ath_startrecv(sc) != 0) { |
3800276a | 265 | ath_err(common, "Unable to restart recv logic\n"); |
9adcf440 | 266 | return false; |
c0d7c7af LR |
267 | } |
268 | ||
5048e8c3 RM |
269 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
270 | sc->config.txpowlimit, &sc->curtxpow); | |
3069168c | 271 | ath9k_hw_set_interrupts(ah, ah->imask); |
b037b693 | 272 | ath9k_hw_enable_interrupts(ah); |
3989279c | 273 | |
9adcf440 | 274 | if (!(sc->sc_flags & (SC_OP_OFFCHANNEL)) && start) { |
1186488b | 275 | if (sc->sc_flags & SC_OP_BEACONS) |
99e4d43a | 276 | ath_set_beacon(sc); |
9adcf440 | 277 | |
5ee08656 | 278 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
181fb18d | 279 | ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2); |
05c0be2f MSS |
280 | if (!common->disable_ani) |
281 | ath_start_ani(common); | |
5ee08656 FF |
282 | } |
283 | ||
9adcf440 FF |
284 | ieee80211_wake_queues(sc->hw); |
285 | ||
286 | return true; | |
287 | } | |
288 | ||
289 | static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan, | |
290 | bool retry_tx) | |
291 | { | |
292 | struct ath_hw *ah = sc->sc_ah; | |
293 | struct ath_common *common = ath9k_hw_common(ah); | |
294 | struct ath9k_hw_cal_data *caldata = NULL; | |
295 | bool fastcc = true; | |
296 | bool flush = false; | |
297 | int r; | |
298 | ||
299 | __ath_cancel_work(sc); | |
300 | ||
301 | spin_lock_bh(&sc->sc_pcu_lock); | |
92460412 | 302 | |
9adcf440 FF |
303 | if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) { |
304 | fastcc = false; | |
305 | caldata = &sc->caldata; | |
306 | } | |
307 | ||
308 | if (!hchan) { | |
309 | fastcc = false; | |
310 | flush = true; | |
311 | hchan = ah->curchan; | |
312 | } | |
313 | ||
314 | if (fastcc && !ath9k_hw_check_alive(ah)) | |
315 | fastcc = false; | |
316 | ||
317 | if (!ath_prepare_reset(sc, retry_tx, flush)) | |
318 | fastcc = false; | |
319 | ||
320 | ath_dbg(common, ATH_DBG_CONFIG, | |
321 | "Reset to %u MHz, HT40: %d fastcc: %d\n", | |
322 | hchan->channel, !!(hchan->channelFlags & (CHANNEL_HT40MINUS | | |
323 | CHANNEL_HT40PLUS)), | |
324 | fastcc); | |
325 | ||
326 | r = ath9k_hw_reset(ah, hchan, caldata, fastcc); | |
327 | if (r) { | |
328 | ath_err(common, | |
329 | "Unable to reset channel, reset status %d\n", r); | |
330 | goto out; | |
331 | } | |
332 | ||
333 | if (!ath_complete_reset(sc, true)) | |
334 | r = -EIO; | |
335 | ||
336 | out: | |
6a6733f2 | 337 | spin_unlock_bh(&sc->sc_pcu_lock); |
9adcf440 FF |
338 | return r; |
339 | } | |
340 | ||
341 | ||
342 | /* | |
343 | * Set/change channels. If the channel is really being changed, it's done | |
344 | * by reseting the chip. To accomplish this we must first cleanup any pending | |
345 | * DMA, then restart stuff. | |
346 | */ | |
347 | static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, | |
348 | struct ath9k_channel *hchan) | |
349 | { | |
350 | int r; | |
351 | ||
352 | if (sc->sc_flags & SC_OP_INVALID) | |
353 | return -EIO; | |
354 | ||
355 | ath9k_ps_wakeup(sc); | |
356 | ||
357 | r = ath_reset_internal(sc, hchan, false); | |
6a6733f2 | 358 | |
3cbb5dd7 | 359 | ath9k_ps_restore(sc); |
9adcf440 | 360 | |
3989279c | 361 | return r; |
ff37e337 S |
362 | } |
363 | ||
9f42c2b6 FF |
364 | static void ath_paprd_activate(struct ath_softc *sc) |
365 | { | |
366 | struct ath_hw *ah = sc->sc_ah; | |
20bd2a09 | 367 | struct ath9k_hw_cal_data *caldata = ah->caldata; |
9f42c2b6 FF |
368 | int chain; |
369 | ||
20bd2a09 | 370 | if (!caldata || !caldata->paprd_done) |
9f42c2b6 FF |
371 | return; |
372 | ||
373 | ath9k_ps_wakeup(sc); | |
ddfef792 | 374 | ar9003_paprd_enable(ah, false); |
9f42c2b6 | 375 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { |
82b2d334 | 376 | if (!(ah->txchainmask & BIT(chain))) |
9f42c2b6 FF |
377 | continue; |
378 | ||
20bd2a09 | 379 | ar9003_paprd_populate_single_table(ah, caldata, chain); |
9f42c2b6 FF |
380 | } |
381 | ||
382 | ar9003_paprd_enable(ah, true); | |
383 | ath9k_ps_restore(sc); | |
384 | } | |
385 | ||
7607cbe2 FF |
386 | static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain) |
387 | { | |
388 | struct ieee80211_hw *hw = sc->hw; | |
389 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
47960077 MSS |
390 | struct ath_hw *ah = sc->sc_ah; |
391 | struct ath_common *common = ath9k_hw_common(ah); | |
7607cbe2 FF |
392 | struct ath_tx_control txctl; |
393 | int time_left; | |
394 | ||
395 | memset(&txctl, 0, sizeof(txctl)); | |
396 | txctl.txq = sc->tx.txq_map[WME_AC_BE]; | |
397 | ||
398 | memset(tx_info, 0, sizeof(*tx_info)); | |
399 | tx_info->band = hw->conf.channel->band; | |
400 | tx_info->flags |= IEEE80211_TX_CTL_NO_ACK; | |
401 | tx_info->control.rates[0].idx = 0; | |
402 | tx_info->control.rates[0].count = 1; | |
403 | tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS; | |
404 | tx_info->control.rates[1].idx = -1; | |
405 | ||
406 | init_completion(&sc->paprd_complete); | |
7607cbe2 | 407 | txctl.paprd = BIT(chain); |
47960077 MSS |
408 | |
409 | if (ath_tx_start(hw, skb, &txctl) != 0) { | |
d4bb17c4 | 410 | ath_dbg(common, ATH_DBG_CALIBRATE, "PAPRD TX failed\n"); |
47960077 | 411 | dev_kfree_skb_any(skb); |
7607cbe2 | 412 | return false; |
47960077 | 413 | } |
7607cbe2 FF |
414 | |
415 | time_left = wait_for_completion_timeout(&sc->paprd_complete, | |
416 | msecs_to_jiffies(ATH_PAPRD_TIMEOUT)); | |
7607cbe2 FF |
417 | |
418 | if (!time_left) | |
d4bb17c4 | 419 | ath_dbg(common, ATH_DBG_CALIBRATE, |
7607cbe2 FF |
420 | "Timeout waiting for paprd training on TX chain %d\n", |
421 | chain); | |
422 | ||
423 | return !!time_left; | |
424 | } | |
425 | ||
9f42c2b6 FF |
426 | void ath_paprd_calibrate(struct work_struct *work) |
427 | { | |
428 | struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work); | |
429 | struct ieee80211_hw *hw = sc->hw; | |
430 | struct ath_hw *ah = sc->sc_ah; | |
431 | struct ieee80211_hdr *hdr; | |
432 | struct sk_buff *skb = NULL; | |
20bd2a09 | 433 | struct ath9k_hw_cal_data *caldata = ah->caldata; |
9094537c | 434 | struct ath_common *common = ath9k_hw_common(ah); |
066dae93 | 435 | int ftype; |
9f42c2b6 FF |
436 | int chain_ok = 0; |
437 | int chain; | |
438 | int len = 1800; | |
9f42c2b6 | 439 | |
20bd2a09 FF |
440 | if (!caldata) |
441 | return; | |
442 | ||
b942471b MSS |
443 | ath9k_ps_wakeup(sc); |
444 | ||
1bf38661 | 445 | if (ar9003_paprd_init_table(ah) < 0) |
b942471b | 446 | goto fail_paprd; |
1bf38661 | 447 | |
9f42c2b6 FF |
448 | skb = alloc_skb(len, GFP_KERNEL); |
449 | if (!skb) | |
b942471b | 450 | goto fail_paprd; |
9f42c2b6 | 451 | |
9f42c2b6 FF |
452 | skb_put(skb, len); |
453 | memset(skb->data, 0, len); | |
454 | hdr = (struct ieee80211_hdr *)skb->data; | |
455 | ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC; | |
456 | hdr->frame_control = cpu_to_le16(ftype); | |
a3d3da14 | 457 | hdr->duration_id = cpu_to_le16(10); |
9f42c2b6 FF |
458 | memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN); |
459 | memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN); | |
460 | memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN); | |
461 | ||
9f42c2b6 | 462 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { |
82b2d334 | 463 | if (!(ah->txchainmask & BIT(chain))) |
9f42c2b6 FF |
464 | continue; |
465 | ||
466 | chain_ok = 0; | |
9f42c2b6 | 467 | |
7607cbe2 FF |
468 | ath_dbg(common, ATH_DBG_CALIBRATE, |
469 | "Sending PAPRD frame for thermal measurement " | |
470 | "on chain %d\n", chain); | |
471 | if (!ath_paprd_send_frame(sc, skb, chain)) | |
472 | goto fail_paprd; | |
9f42c2b6 | 473 | |
9f42c2b6 | 474 | ar9003_paprd_setup_gain_table(ah, chain); |
9f42c2b6 | 475 | |
7607cbe2 FF |
476 | ath_dbg(common, ATH_DBG_CALIBRATE, |
477 | "Sending PAPRD training frame on chain %d\n", chain); | |
478 | if (!ath_paprd_send_frame(sc, skb, chain)) | |
ca369eb4 | 479 | goto fail_paprd; |
9f42c2b6 | 480 | |
d4bb17c4 MSS |
481 | if (!ar9003_paprd_is_done(ah)) { |
482 | ath_dbg(common, ATH_DBG_CALIBRATE, | |
483 | "PAPRD not yet done on chain %d\n", chain); | |
9f42c2b6 | 484 | break; |
d4bb17c4 | 485 | } |
9f42c2b6 | 486 | |
d4bb17c4 MSS |
487 | if (ar9003_paprd_create_curve(ah, caldata, chain)) { |
488 | ath_dbg(common, ATH_DBG_CALIBRATE, | |
489 | "PAPRD create curve failed on chain %d\n", | |
490 | chain); | |
9f42c2b6 | 491 | break; |
d4bb17c4 | 492 | } |
9f42c2b6 FF |
493 | |
494 | chain_ok = 1; | |
495 | } | |
496 | kfree_skb(skb); | |
497 | ||
498 | if (chain_ok) { | |
20bd2a09 | 499 | caldata->paprd_done = true; |
9f42c2b6 FF |
500 | ath_paprd_activate(sc); |
501 | } | |
502 | ||
ca369eb4 | 503 | fail_paprd: |
9f42c2b6 FF |
504 | ath9k_ps_restore(sc); |
505 | } | |
506 | ||
ff37e337 S |
507 | /* |
508 | * This routine performs the periodic noise floor calibration function | |
509 | * that is used to adjust and optimize the chip performance. This | |
510 | * takes environmental changes (location, temperature) into account. | |
511 | * When the task is complete, it reschedules itself depending on the | |
512 | * appropriate interval that was calculated. | |
513 | */ | |
55624204 | 514 | void ath_ani_calibrate(unsigned long data) |
ff37e337 | 515 | { |
20977d3e S |
516 | struct ath_softc *sc = (struct ath_softc *)data; |
517 | struct ath_hw *ah = sc->sc_ah; | |
c46917bb | 518 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
519 | bool longcal = false; |
520 | bool shortcal = false; | |
521 | bool aniflag = false; | |
522 | unsigned int timestamp = jiffies_to_msecs(jiffies); | |
6044474e | 523 | u32 cal_interval, short_cal_interval, long_cal_interval; |
b5bfc568 | 524 | unsigned long flags; |
6044474e FF |
525 | |
526 | if (ah->caldata && ah->caldata->nfcal_interference) | |
527 | long_cal_interval = ATH_LONG_CALINTERVAL_INT; | |
528 | else | |
529 | long_cal_interval = ATH_LONG_CALINTERVAL; | |
ff37e337 | 530 | |
20977d3e S |
531 | short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ? |
532 | ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL; | |
ff37e337 | 533 | |
1ffc1c61 JM |
534 | /* Only calibrate if awake */ |
535 | if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) | |
536 | goto set_timer; | |
537 | ||
538 | ath9k_ps_wakeup(sc); | |
539 | ||
ff37e337 | 540 | /* Long calibration runs independently of short calibration. */ |
6044474e | 541 | if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) { |
ff37e337 | 542 | longcal = true; |
226afe68 | 543 | ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies); |
3d536acf | 544 | common->ani.longcal_timer = timestamp; |
ff37e337 S |
545 | } |
546 | ||
17d7904d | 547 | /* Short calibration applies only while caldone is false */ |
3d536acf LR |
548 | if (!common->ani.caldone) { |
549 | if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) { | |
ff37e337 | 550 | shortcal = true; |
226afe68 JP |
551 | ath_dbg(common, ATH_DBG_ANI, |
552 | "shortcal @%lu\n", jiffies); | |
3d536acf LR |
553 | common->ani.shortcal_timer = timestamp; |
554 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
555 | } |
556 | } else { | |
3d536acf | 557 | if ((timestamp - common->ani.resetcal_timer) >= |
ff37e337 | 558 | ATH_RESTART_CALINTERVAL) { |
3d536acf LR |
559 | common->ani.caldone = ath9k_hw_reset_calvalid(ah); |
560 | if (common->ani.caldone) | |
561 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
562 | } |
563 | } | |
564 | ||
565 | /* Verify whether we must check ANI */ | |
e36b27af LR |
566 | if ((timestamp - common->ani.checkani_timer) >= |
567 | ah->config.ani_poll_interval) { | |
ff37e337 | 568 | aniflag = true; |
3d536acf | 569 | common->ani.checkani_timer = timestamp; |
ff37e337 S |
570 | } |
571 | ||
e62ddec9 MSS |
572 | /* Call ANI routine if necessary */ |
573 | if (aniflag) { | |
574 | spin_lock_irqsave(&common->cc_lock, flags); | |
575 | ath9k_hw_ani_monitor(ah, ah->curchan); | |
576 | ath_update_survey_stats(sc); | |
577 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
578 | } | |
ff37e337 | 579 | |
e62ddec9 MSS |
580 | /* Perform calibration if necessary */ |
581 | if (longcal || shortcal) { | |
582 | common->ani.caldone = | |
583 | ath9k_hw_calibrate(ah, ah->curchan, | |
82b2d334 | 584 | ah->rxchainmask, longcal); |
ff37e337 S |
585 | } |
586 | ||
1ffc1c61 JM |
587 | ath9k_ps_restore(sc); |
588 | ||
20977d3e | 589 | set_timer: |
ff37e337 S |
590 | /* |
591 | * Set timer interval based on previous results. | |
592 | * The interval must be the shortest necessary to satisfy ANI, | |
593 | * short calibration and long calibration. | |
594 | */ | |
cf3af748 | 595 | ath9k_debug_samp_bb_mac(sc); |
aac9207e | 596 | cal_interval = ATH_LONG_CALINTERVAL; |
2660b81a | 597 | if (sc->sc_ah->config.enable_ani) |
e36b27af LR |
598 | cal_interval = min(cal_interval, |
599 | (u32)ah->config.ani_poll_interval); | |
3d536acf | 600 | if (!common->ani.caldone) |
20977d3e | 601 | cal_interval = min(cal_interval, (u32)short_cal_interval); |
ff37e337 | 602 | |
3d536acf | 603 | mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval)); |
20bd2a09 FF |
604 | if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) { |
605 | if (!ah->caldata->paprd_done) | |
9f42c2b6 | 606 | ieee80211_queue_work(sc->hw, &sc->paprd_work); |
45ef6a0b | 607 | else if (!ah->paprd_table_write_done) |
9f42c2b6 FF |
608 | ath_paprd_activate(sc); |
609 | } | |
ff37e337 S |
610 | } |
611 | ||
ff37e337 S |
612 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) |
613 | { | |
614 | struct ath_node *an; | |
ff37e337 S |
615 | an = (struct ath_node *)sta->drv_priv; |
616 | ||
7f010c93 BG |
617 | #ifdef CONFIG_ATH9K_DEBUGFS |
618 | spin_lock(&sc->nodes_lock); | |
619 | list_add(&an->list, &sc->nodes); | |
620 | spin_unlock(&sc->nodes_lock); | |
621 | an->sta = sta; | |
622 | #endif | |
87792efc | 623 | if (sc->sc_flags & SC_OP_TXAGGR) { |
ff37e337 | 624 | ath_tx_node_init(sc, an); |
9e98ac65 | 625 | an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + |
87792efc S |
626 | sta->ht_cap.ampdu_factor); |
627 | an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density); | |
628 | } | |
ff37e337 S |
629 | } |
630 | ||
631 | static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
632 | { | |
633 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
634 | ||
7f010c93 BG |
635 | #ifdef CONFIG_ATH9K_DEBUGFS |
636 | spin_lock(&sc->nodes_lock); | |
637 | list_del(&an->list); | |
638 | spin_unlock(&sc->nodes_lock); | |
639 | an->sta = NULL; | |
640 | #endif | |
641 | ||
ff37e337 S |
642 | if (sc->sc_flags & SC_OP_TXAGGR) |
643 | ath_tx_node_cleanup(sc, an); | |
644 | } | |
645 | ||
9eab61c2 | 646 | |
55624204 | 647 | void ath9k_tasklet(unsigned long data) |
ff37e337 S |
648 | { |
649 | struct ath_softc *sc = (struct ath_softc *)data; | |
af03abec | 650 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 651 | struct ath_common *common = ath9k_hw_common(ah); |
af03abec | 652 | |
17d7904d | 653 | u32 status = sc->intrstatus; |
b5c80475 | 654 | u32 rxmask; |
ff37e337 | 655 | |
a4d86d95 RM |
656 | if ((status & ATH9K_INT_FATAL) || |
657 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
236de514 | 658 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); |
ff37e337 | 659 | return; |
063d8be3 | 660 | } |
ff37e337 | 661 | |
783cd01e | 662 | ath9k_ps_wakeup(sc); |
52671e43 | 663 | spin_lock(&sc->sc_pcu_lock); |
6a6733f2 | 664 | |
8b3f4616 FF |
665 | /* |
666 | * Only run the baseband hang check if beacons stop working in AP or | |
667 | * IBSS mode, because it has a high false positive rate. For station | |
668 | * mode it should not be necessary, since the upper layers will detect | |
669 | * this through a beacon miss automatically and the following channel | |
670 | * change will trigger a hardware reset anyway | |
671 | */ | |
672 | if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 && | |
673 | !ath9k_hw_check_alive(ah)) | |
347809fc FF |
674 | ieee80211_queue_work(sc->hw, &sc->hw_check_work); |
675 | ||
4105f807 RM |
676 | if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { |
677 | /* | |
678 | * TSF sync does not look correct; remain awake to sync with | |
679 | * the next Beacon. | |
680 | */ | |
681 | ath_dbg(common, ATH_DBG_PS, | |
682 | "TSFOOR - Sync with next Beacon\n"); | |
e8fe7336 | 683 | sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; |
4105f807 RM |
684 | } |
685 | ||
b5c80475 FF |
686 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
687 | rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | | |
688 | ATH9K_INT_RXORN); | |
689 | else | |
690 | rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
691 | ||
692 | if (status & rxmask) { | |
b5c80475 FF |
693 | /* Check for high priority Rx first */ |
694 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && | |
695 | (status & ATH9K_INT_RXHP)) | |
696 | ath_rx_tasklet(sc, 0, true); | |
697 | ||
698 | ath_rx_tasklet(sc, 0, false); | |
ff37e337 S |
699 | } |
700 | ||
e5003249 VT |
701 | if (status & ATH9K_INT_TX) { |
702 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
703 | ath_tx_edma_tasklet(sc); | |
704 | else | |
705 | ath_tx_tasklet(sc); | |
706 | } | |
063d8be3 | 707 | |
766ec4a9 | 708 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
ebb8e1d7 VT |
709 | if (status & ATH9K_INT_GENTIMER) |
710 | ath_gen_timer_isr(sc->sc_ah); | |
711 | ||
ff37e337 | 712 | /* re-enable hardware interrupt */ |
4df3071e | 713 | ath9k_hw_enable_interrupts(ah); |
6a6733f2 | 714 | |
52671e43 | 715 | spin_unlock(&sc->sc_pcu_lock); |
153e080d | 716 | ath9k_ps_restore(sc); |
ff37e337 S |
717 | } |
718 | ||
6baff7f9 | 719 | irqreturn_t ath_isr(int irq, void *dev) |
ff37e337 | 720 | { |
063d8be3 S |
721 | #define SCHED_INTR ( \ |
722 | ATH9K_INT_FATAL | \ | |
a4d86d95 | 723 | ATH9K_INT_BB_WATCHDOG | \ |
063d8be3 S |
724 | ATH9K_INT_RXORN | \ |
725 | ATH9K_INT_RXEOL | \ | |
726 | ATH9K_INT_RX | \ | |
b5c80475 FF |
727 | ATH9K_INT_RXLP | \ |
728 | ATH9K_INT_RXHP | \ | |
063d8be3 S |
729 | ATH9K_INT_TX | \ |
730 | ATH9K_INT_BMISS | \ | |
731 | ATH9K_INT_CST | \ | |
ebb8e1d7 VT |
732 | ATH9K_INT_TSFOOR | \ |
733 | ATH9K_INT_GENTIMER) | |
063d8be3 | 734 | |
ff37e337 | 735 | struct ath_softc *sc = dev; |
cbe61d8a | 736 | struct ath_hw *ah = sc->sc_ah; |
b5bfc568 | 737 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
738 | enum ath9k_int status; |
739 | bool sched = false; | |
740 | ||
063d8be3 S |
741 | /* |
742 | * The hardware is not ready/present, don't | |
743 | * touch anything. Note this can happen early | |
744 | * on if the IRQ is shared. | |
745 | */ | |
746 | if (sc->sc_flags & SC_OP_INVALID) | |
747 | return IRQ_NONE; | |
ff37e337 | 748 | |
063d8be3 S |
749 | |
750 | /* shared irq, not for us */ | |
751 | ||
153e080d | 752 | if (!ath9k_hw_intrpend(ah)) |
063d8be3 | 753 | return IRQ_NONE; |
063d8be3 S |
754 | |
755 | /* | |
756 | * Figure out the reason(s) for the interrupt. Note | |
757 | * that the hal returns a pseudo-ISR that may include | |
758 | * bits we haven't explicitly enabled so we mask the | |
759 | * value to insure we only process bits we requested. | |
760 | */ | |
761 | ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ | |
3069168c | 762 | status &= ah->imask; /* discard unasked-for bits */ |
ff37e337 | 763 | |
063d8be3 S |
764 | /* |
765 | * If there are no status bits set, then this interrupt was not | |
766 | * for me (should have been caught above). | |
767 | */ | |
153e080d | 768 | if (!status) |
063d8be3 | 769 | return IRQ_NONE; |
ff37e337 | 770 | |
063d8be3 S |
771 | /* Cache the status */ |
772 | sc->intrstatus = status; | |
773 | ||
774 | if (status & SCHED_INTR) | |
775 | sched = true; | |
776 | ||
777 | /* | |
778 | * If a FATAL or RXORN interrupt is received, we have to reset the | |
779 | * chip immediately. | |
780 | */ | |
b5c80475 FF |
781 | if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && |
782 | !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) | |
063d8be3 S |
783 | goto chip_reset; |
784 | ||
08578b8f LR |
785 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && |
786 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
b5bfc568 FF |
787 | |
788 | spin_lock(&common->cc_lock); | |
789 | ath_hw_cycle_counters_update(common); | |
08578b8f | 790 | ar9003_hw_bb_watchdog_dbg_info(ah); |
b5bfc568 FF |
791 | spin_unlock(&common->cc_lock); |
792 | ||
08578b8f LR |
793 | goto chip_reset; |
794 | } | |
795 | ||
063d8be3 S |
796 | if (status & ATH9K_INT_SWBA) |
797 | tasklet_schedule(&sc->bcon_tasklet); | |
798 | ||
799 | if (status & ATH9K_INT_TXURN) | |
800 | ath9k_hw_updatetxtriglevel(ah, true); | |
801 | ||
0682c9b5 RM |
802 | if (status & ATH9K_INT_RXEOL) { |
803 | ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
804 | ath9k_hw_set_interrupts(ah, ah->imask); | |
b5c80475 FF |
805 | } |
806 | ||
063d8be3 | 807 | if (status & ATH9K_INT_MIB) { |
ff37e337 | 808 | /* |
063d8be3 S |
809 | * Disable interrupts until we service the MIB |
810 | * interrupt; otherwise it will continue to | |
811 | * fire. | |
ff37e337 | 812 | */ |
4df3071e | 813 | ath9k_hw_disable_interrupts(ah); |
063d8be3 S |
814 | /* |
815 | * Let the hal handle the event. We assume | |
816 | * it will clear whatever condition caused | |
817 | * the interrupt. | |
818 | */ | |
88eac2da | 819 | spin_lock(&common->cc_lock); |
bfc472bb | 820 | ath9k_hw_proc_mib_event(ah); |
88eac2da | 821 | spin_unlock(&common->cc_lock); |
4df3071e | 822 | ath9k_hw_enable_interrupts(ah); |
063d8be3 | 823 | } |
ff37e337 | 824 | |
153e080d VT |
825 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
826 | if (status & ATH9K_INT_TIM_TIMER) { | |
ff9f0b63 LR |
827 | if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) |
828 | goto chip_reset; | |
063d8be3 S |
829 | /* Clear RxAbort bit so that we can |
830 | * receive frames */ | |
9ecdef4b | 831 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
153e080d | 832 | ath9k_hw_setrxabort(sc->sc_ah, 0); |
1b04b930 | 833 | sc->ps_flags |= PS_WAIT_FOR_BEACON; |
ff37e337 | 834 | } |
063d8be3 S |
835 | |
836 | chip_reset: | |
ff37e337 | 837 | |
817e11de S |
838 | ath_debug_stat_interrupt(sc, status); |
839 | ||
ff37e337 | 840 | if (sched) { |
4df3071e FF |
841 | /* turn off every interrupt */ |
842 | ath9k_hw_disable_interrupts(ah); | |
ff37e337 S |
843 | tasklet_schedule(&sc->intr_tq); |
844 | } | |
845 | ||
846 | return IRQ_HANDLED; | |
063d8be3 S |
847 | |
848 | #undef SCHED_INTR | |
ff37e337 S |
849 | } |
850 | ||
5595f119 | 851 | static void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 852 | { |
cbe61d8a | 853 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 854 | struct ath_common *common = ath9k_hw_common(ah); |
68a89116 | 855 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 856 | int r; |
500c064d | 857 | |
3cbb5dd7 | 858 | ath9k_ps_wakeup(sc); |
6a6733f2 | 859 | spin_lock_bh(&sc->sc_pcu_lock); |
e8fe7336 | 860 | atomic_set(&ah->intr_ref_cnt, -1); |
6a6733f2 | 861 | |
84c87dc8 | 862 | ath9k_hw_configpcipowersave(ah, false); |
ae8d2858 | 863 | |
159cd468 | 864 | if (!ah->curchan) |
c344c9cb | 865 | ah->curchan = ath9k_cmn_get_curchannel(sc->hw, ah); |
159cd468 | 866 | |
20bd2a09 | 867 | r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); |
ae8d2858 | 868 | if (r) { |
3800276a JP |
869 | ath_err(common, |
870 | "Unable to reset channel (%u MHz), reset status %d\n", | |
871 | channel->center_freq, r); | |
500c064d | 872 | } |
500c064d | 873 | |
9adcf440 | 874 | ath_complete_reset(sc, true); |
500c064d VT |
875 | |
876 | /* Enable LED */ | |
08fc5c1b | 877 | ath9k_hw_cfg_output(ah, ah->led_pin, |
500c064d | 878 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); |
08fc5c1b | 879 | ath9k_hw_set_gpio(ah, ah->led_pin, 0); |
500c064d | 880 | |
6a6733f2 LR |
881 | spin_unlock_bh(&sc->sc_pcu_lock); |
882 | ||
3cbb5dd7 | 883 | ath9k_ps_restore(sc); |
500c064d VT |
884 | } |
885 | ||
68a89116 | 886 | void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 887 | { |
cbe61d8a | 888 | struct ath_hw *ah = sc->sc_ah; |
68a89116 | 889 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 890 | int r; |
500c064d | 891 | |
3cbb5dd7 | 892 | ath9k_ps_wakeup(sc); |
7e3514fd | 893 | |
9adcf440 | 894 | ath_cancel_work(sc); |
6a6733f2 | 895 | |
9adcf440 | 896 | spin_lock_bh(&sc->sc_pcu_lock); |
500c064d | 897 | |
982723df VN |
898 | /* |
899 | * Keep the LED on when the radio is disabled | |
900 | * during idle unassociated state. | |
901 | */ | |
902 | if (!sc->ps_idle) { | |
903 | ath9k_hw_set_gpio(ah, ah->led_pin, 1); | |
904 | ath9k_hw_cfg_gpio_input(ah, ah->led_pin); | |
905 | } | |
500c064d | 906 | |
9adcf440 | 907 | ath_prepare_reset(sc, false, true); |
500c064d | 908 | |
159cd468 | 909 | if (!ah->curchan) |
c344c9cb | 910 | ah->curchan = ath9k_cmn_get_curchannel(hw, ah); |
159cd468 | 911 | |
20bd2a09 | 912 | r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); |
ae8d2858 | 913 | if (r) { |
3800276a JP |
914 | ath_err(ath9k_hw_common(sc->sc_ah), |
915 | "Unable to reset channel (%u MHz), reset status %d\n", | |
916 | channel->center_freq, r); | |
500c064d | 917 | } |
500c064d VT |
918 | |
919 | ath9k_hw_phy_disable(ah); | |
5e848f78 | 920 | |
84c87dc8 | 921 | ath9k_hw_configpcipowersave(ah, true); |
6a6733f2 LR |
922 | |
923 | spin_unlock_bh(&sc->sc_pcu_lock); | |
3cbb5dd7 | 924 | ath9k_ps_restore(sc); |
500c064d VT |
925 | } |
926 | ||
236de514 | 927 | static int ath_reset(struct ath_softc *sc, bool retry_tx) |
ff37e337 | 928 | { |
ae8d2858 | 929 | int r; |
ff37e337 | 930 | |
783cd01e | 931 | ath9k_ps_wakeup(sc); |
6a6733f2 | 932 | |
9adcf440 | 933 | r = ath_reset_internal(sc, NULL, retry_tx); |
ff37e337 S |
934 | |
935 | if (retry_tx) { | |
936 | int i; | |
937 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
938 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f S |
939 | spin_lock_bh(&sc->tx.txq[i].axq_lock); |
940 | ath_txq_schedule(sc, &sc->tx.txq[i]); | |
941 | spin_unlock_bh(&sc->tx.txq[i].axq_lock); | |
ff37e337 S |
942 | } |
943 | } | |
944 | } | |
945 | ||
783cd01e | 946 | ath9k_ps_restore(sc); |
2ab81d4a | 947 | |
ae8d2858 | 948 | return r; |
ff37e337 S |
949 | } |
950 | ||
236de514 FF |
951 | void ath_reset_work(struct work_struct *work) |
952 | { | |
953 | struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work); | |
954 | ||
236de514 | 955 | ath_reset(sc, true); |
236de514 FF |
956 | } |
957 | ||
e8cfe9f8 FF |
958 | void ath_hw_check(struct work_struct *work) |
959 | { | |
960 | struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work); | |
961 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
962 | unsigned long flags; | |
963 | int busy; | |
964 | ||
965 | ath9k_ps_wakeup(sc); | |
966 | if (ath9k_hw_check_alive(sc->sc_ah)) | |
967 | goto out; | |
968 | ||
969 | spin_lock_irqsave(&common->cc_lock, flags); | |
970 | busy = ath_update_survey_stats(sc); | |
971 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
972 | ||
973 | ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, " | |
974 | "busy=%d (try %d)\n", busy, sc->hw_busy_count + 1); | |
975 | if (busy >= 99) { | |
9adcf440 FF |
976 | if (++sc->hw_busy_count >= 3) |
977 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); | |
e8cfe9f8 FF |
978 | |
979 | } else if (busy >= 0) | |
980 | sc->hw_busy_count = 0; | |
981 | ||
982 | out: | |
983 | ath9k_ps_restore(sc); | |
984 | } | |
985 | ||
986 | static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum) | |
987 | { | |
988 | static int count; | |
989 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
990 | ||
991 | if (pll_sqsum >= 0x40000) { | |
992 | count++; | |
993 | if (count == 3) { | |
994 | /* Rx is hung for more than 500ms. Reset it */ | |
995 | ath_dbg(common, ATH_DBG_RESET, | |
996 | "Possible RX hang, resetting"); | |
9adcf440 | 997 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); |
e8cfe9f8 FF |
998 | count = 0; |
999 | } | |
1000 | } else | |
1001 | count = 0; | |
1002 | } | |
1003 | ||
1004 | void ath_hw_pll_work(struct work_struct *work) | |
1005 | { | |
1006 | struct ath_softc *sc = container_of(work, struct ath_softc, | |
1007 | hw_pll_work.work); | |
1008 | u32 pll_sqsum; | |
1009 | ||
1010 | if (AR_SREV_9485(sc->sc_ah)) { | |
1011 | ||
1012 | ath9k_ps_wakeup(sc); | |
1013 | pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah); | |
1014 | ath9k_ps_restore(sc); | |
1015 | ||
1016 | ath_hw_pll_rx_hang_check(sc, pll_sqsum); | |
1017 | ||
1018 | ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5); | |
1019 | } | |
1020 | } | |
1021 | ||
ff37e337 S |
1022 | /**********************/ |
1023 | /* mac80211 callbacks */ | |
1024 | /**********************/ | |
1025 | ||
8feceb67 | 1026 | static int ath9k_start(struct ieee80211_hw *hw) |
f078f209 | 1027 | { |
9ac58615 | 1028 | struct ath_softc *sc = hw->priv; |
af03abec | 1029 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1030 | struct ath_common *common = ath9k_hw_common(ah); |
8feceb67 | 1031 | struct ieee80211_channel *curchan = hw->conf.channel; |
ff37e337 | 1032 | struct ath9k_channel *init_channel; |
82880a7c | 1033 | int r; |
f078f209 | 1034 | |
226afe68 JP |
1035 | ath_dbg(common, ATH_DBG_CONFIG, |
1036 | "Starting driver with initial channel: %d MHz\n", | |
1037 | curchan->center_freq); | |
f078f209 | 1038 | |
f62d816f FF |
1039 | ath9k_ps_wakeup(sc); |
1040 | ||
141b38b6 S |
1041 | mutex_lock(&sc->mutex); |
1042 | ||
8feceb67 | 1043 | /* setup initial channel */ |
82880a7c | 1044 | sc->chan_idx = curchan->hw_value; |
f078f209 | 1045 | |
c344c9cb | 1046 | init_channel = ath9k_cmn_get_curchannel(hw, ah); |
ff37e337 S |
1047 | |
1048 | /* Reset SERDES registers */ | |
84c87dc8 | 1049 | ath9k_hw_configpcipowersave(ah, false); |
ff37e337 S |
1050 | |
1051 | /* | |
1052 | * The basic interface to setting the hardware in a good | |
1053 | * state is ``reset''. On return the hardware is known to | |
1054 | * be powered up and with interrupts disabled. This must | |
1055 | * be followed by initialization of the appropriate bits | |
1056 | * and then setup of the interrupt mask. | |
1057 | */ | |
4bdd1e97 | 1058 | spin_lock_bh(&sc->sc_pcu_lock); |
20bd2a09 | 1059 | r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); |
ae8d2858 | 1060 | if (r) { |
3800276a JP |
1061 | ath_err(common, |
1062 | "Unable to reset hardware; reset status %d (freq %u MHz)\n", | |
1063 | r, curchan->center_freq); | |
4bdd1e97 | 1064 | spin_unlock_bh(&sc->sc_pcu_lock); |
141b38b6 | 1065 | goto mutex_unlock; |
ff37e337 | 1066 | } |
ff37e337 | 1067 | |
ff37e337 | 1068 | /* Setup our intr mask. */ |
b5c80475 FF |
1069 | ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | |
1070 | ATH9K_INT_RXORN | ATH9K_INT_FATAL | | |
1071 | ATH9K_INT_GLOBAL; | |
1072 | ||
1073 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
08578b8f LR |
1074 | ah->imask |= ATH9K_INT_RXHP | |
1075 | ATH9K_INT_RXLP | | |
1076 | ATH9K_INT_BB_WATCHDOG; | |
b5c80475 FF |
1077 | else |
1078 | ah->imask |= ATH9K_INT_RX; | |
ff37e337 | 1079 | |
364734fa | 1080 | ah->imask |= ATH9K_INT_GTT; |
ff37e337 | 1081 | |
af03abec | 1082 | if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
3069168c | 1083 | ah->imask |= ATH9K_INT_CST; |
ff37e337 | 1084 | |
ff37e337 | 1085 | sc->sc_flags &= ~SC_OP_INVALID; |
5f841b41 | 1086 | sc->sc_ah->is_monitoring = false; |
ff37e337 S |
1087 | |
1088 | /* Disable BMISS interrupt when we're not associated */ | |
3069168c | 1089 | ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); |
ff37e337 | 1090 | |
9adcf440 FF |
1091 | if (!ath_complete_reset(sc, false)) { |
1092 | r = -EIO; | |
1093 | spin_unlock_bh(&sc->sc_pcu_lock); | |
1094 | goto mutex_unlock; | |
1095 | } | |
ff37e337 | 1096 | |
9adcf440 | 1097 | spin_unlock_bh(&sc->sc_pcu_lock); |
164ace38 | 1098 | |
766ec4a9 LR |
1099 | if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) && |
1100 | !ah->btcoex_hw.enabled) { | |
5e197292 LR |
1101 | ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT, |
1102 | AR_STOMP_LOW_WLAN_WGHT); | |
af03abec | 1103 | ath9k_hw_btcoex_enable(ah); |
f985ad12 | 1104 | |
766ec4a9 | 1105 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1106 | ath9k_btcoex_timer_resume(sc); |
1773912b VT |
1107 | } |
1108 | ||
8060e169 VT |
1109 | if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en) |
1110 | common->bus_ops->extn_synch_en(common); | |
1111 | ||
141b38b6 S |
1112 | mutex_unlock: |
1113 | mutex_unlock(&sc->mutex); | |
1114 | ||
f62d816f FF |
1115 | ath9k_ps_restore(sc); |
1116 | ||
ae8d2858 | 1117 | return r; |
f078f209 LR |
1118 | } |
1119 | ||
7bb45683 | 1120 | static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
f078f209 | 1121 | { |
9ac58615 | 1122 | struct ath_softc *sc = hw->priv; |
c46917bb | 1123 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
528f0c6b | 1124 | struct ath_tx_control txctl; |
1bc14880 | 1125 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; |
528f0c6b | 1126 | |
96148326 | 1127 | if (sc->ps_enabled) { |
dc8c4585 JM |
1128 | /* |
1129 | * mac80211 does not set PM field for normal data frames, so we | |
1130 | * need to update that based on the current PS mode. | |
1131 | */ | |
1132 | if (ieee80211_is_data(hdr->frame_control) && | |
1133 | !ieee80211_is_nullfunc(hdr->frame_control) && | |
1134 | !ieee80211_has_pm(hdr->frame_control)) { | |
226afe68 JP |
1135 | ath_dbg(common, ATH_DBG_PS, |
1136 | "Add PM=1 for a TX frame while in PS mode\n"); | |
dc8c4585 JM |
1137 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); |
1138 | } | |
1139 | } | |
1140 | ||
9a23f9ca JM |
1141 | if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) { |
1142 | /* | |
1143 | * We are using PS-Poll and mac80211 can request TX while in | |
1144 | * power save mode. Need to wake up hardware for the TX to be | |
1145 | * completed and if needed, also for RX of buffered frames. | |
1146 | */ | |
9a23f9ca | 1147 | ath9k_ps_wakeup(sc); |
fdf76622 VT |
1148 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
1149 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
9a23f9ca | 1150 | if (ieee80211_is_pspoll(hdr->frame_control)) { |
226afe68 JP |
1151 | ath_dbg(common, ATH_DBG_PS, |
1152 | "Sending PS-Poll to pick a buffered frame\n"); | |
1b04b930 | 1153 | sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; |
9a23f9ca | 1154 | } else { |
226afe68 JP |
1155 | ath_dbg(common, ATH_DBG_PS, |
1156 | "Wake up to complete TX\n"); | |
1b04b930 | 1157 | sc->ps_flags |= PS_WAIT_FOR_TX_ACK; |
9a23f9ca JM |
1158 | } |
1159 | /* | |
1160 | * The actual restore operation will happen only after | |
1161 | * the sc_flags bit is cleared. We are just dropping | |
1162 | * the ps_usecount here. | |
1163 | */ | |
1164 | ath9k_ps_restore(sc); | |
1165 | } | |
1166 | ||
528f0c6b | 1167 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
066dae93 | 1168 | txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; |
528f0c6b | 1169 | |
226afe68 | 1170 | ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); |
8feceb67 | 1171 | |
c52f33d0 | 1172 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
226afe68 | 1173 | ath_dbg(common, ATH_DBG_XMIT, "TX failed\n"); |
528f0c6b | 1174 | goto exit; |
8feceb67 VT |
1175 | } |
1176 | ||
7bb45683 | 1177 | return; |
528f0c6b S |
1178 | exit: |
1179 | dev_kfree_skb_any(skb); | |
f078f209 LR |
1180 | } |
1181 | ||
8feceb67 | 1182 | static void ath9k_stop(struct ieee80211_hw *hw) |
f078f209 | 1183 | { |
9ac58615 | 1184 | struct ath_softc *sc = hw->priv; |
af03abec | 1185 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1186 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 1187 | |
4c483817 S |
1188 | mutex_lock(&sc->mutex); |
1189 | ||
9adcf440 | 1190 | ath_cancel_work(sc); |
c94dbff7 | 1191 | |
9c84b797 | 1192 | if (sc->sc_flags & SC_OP_INVALID) { |
226afe68 | 1193 | ath_dbg(common, ATH_DBG_ANY, "Device not present\n"); |
4c483817 | 1194 | mutex_unlock(&sc->mutex); |
9c84b797 S |
1195 | return; |
1196 | } | |
8feceb67 | 1197 | |
3867cf6a S |
1198 | /* Ensure HW is awake when we try to shut it down. */ |
1199 | ath9k_ps_wakeup(sc); | |
1200 | ||
766ec4a9 | 1201 | if (ah->btcoex_hw.enabled) { |
af03abec | 1202 | ath9k_hw_btcoex_disable(ah); |
766ec4a9 | 1203 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1204 | ath9k_btcoex_timer_pause(sc); |
1773912b VT |
1205 | } |
1206 | ||
6a6733f2 LR |
1207 | spin_lock_bh(&sc->sc_pcu_lock); |
1208 | ||
203043f5 SG |
1209 | /* prevent tasklets to enable interrupts once we disable them */ |
1210 | ah->imask &= ~ATH9K_INT_GLOBAL; | |
1211 | ||
ff37e337 S |
1212 | /* make sure h/w will not generate any interrupt |
1213 | * before setting the invalid flag. */ | |
4df3071e | 1214 | ath9k_hw_disable_interrupts(ah); |
ff37e337 S |
1215 | |
1216 | if (!(sc->sc_flags & SC_OP_INVALID)) { | |
043a0405 | 1217 | ath_drain_all_txq(sc, false); |
ff37e337 | 1218 | ath_stoprecv(sc); |
af03abec | 1219 | ath9k_hw_phy_disable(ah); |
6a6733f2 | 1220 | } else |
b77f483f | 1221 | sc->rx.rxlink = NULL; |
ff37e337 | 1222 | |
0d95521e FF |
1223 | if (sc->rx.frag) { |
1224 | dev_kfree_skb_any(sc->rx.frag); | |
1225 | sc->rx.frag = NULL; | |
1226 | } | |
1227 | ||
ff37e337 | 1228 | /* disable HAL and put h/w to sleep */ |
af03abec | 1229 | ath9k_hw_disable(ah); |
6a6733f2 LR |
1230 | |
1231 | spin_unlock_bh(&sc->sc_pcu_lock); | |
1232 | ||
203043f5 SG |
1233 | /* we can now sync irq and kill any running tasklets, since we already |
1234 | * disabled interrupts and not holding a spin lock */ | |
1235 | synchronize_irq(sc->irq); | |
1236 | tasklet_kill(&sc->intr_tq); | |
1237 | tasklet_kill(&sc->bcon_tasklet); | |
1238 | ||
3867cf6a S |
1239 | ath9k_ps_restore(sc); |
1240 | ||
a08e7ade LR |
1241 | sc->ps_idle = true; |
1242 | ath_radio_disable(sc, hw); | |
ff37e337 S |
1243 | |
1244 | sc->sc_flags |= SC_OP_INVALID; | |
500c064d | 1245 | |
141b38b6 S |
1246 | mutex_unlock(&sc->mutex); |
1247 | ||
226afe68 | 1248 | ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n"); |
f078f209 LR |
1249 | } |
1250 | ||
4801416c BG |
1251 | bool ath9k_uses_beacons(int type) |
1252 | { | |
1253 | switch (type) { | |
1254 | case NL80211_IFTYPE_AP: | |
1255 | case NL80211_IFTYPE_ADHOC: | |
1256 | case NL80211_IFTYPE_MESH_POINT: | |
1257 | return true; | |
1258 | default: | |
1259 | return false; | |
1260 | } | |
1261 | } | |
1262 | ||
1263 | static void ath9k_reclaim_beacon(struct ath_softc *sc, | |
1264 | struct ieee80211_vif *vif) | |
f078f209 | 1265 | { |
1ed32e4f | 1266 | struct ath_vif *avp = (void *)vif->drv_priv; |
8feceb67 | 1267 | |
014cf3bb | 1268 | ath9k_set_beaconing_status(sc, false); |
4801416c | 1269 | ath_beacon_return(sc, avp); |
014cf3bb | 1270 | ath9k_set_beaconing_status(sc, true); |
4801416c | 1271 | sc->sc_flags &= ~SC_OP_BEACONS; |
4801416c BG |
1272 | } |
1273 | ||
1274 | static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) | |
1275 | { | |
1276 | struct ath9k_vif_iter_data *iter_data = data; | |
1277 | int i; | |
1278 | ||
1279 | if (iter_data->hw_macaddr) | |
1280 | for (i = 0; i < ETH_ALEN; i++) | |
1281 | iter_data->mask[i] &= | |
1282 | ~(iter_data->hw_macaddr[i] ^ mac[i]); | |
141b38b6 | 1283 | |
1ed32e4f | 1284 | switch (vif->type) { |
4801416c BG |
1285 | case NL80211_IFTYPE_AP: |
1286 | iter_data->naps++; | |
f078f209 | 1287 | break; |
4801416c BG |
1288 | case NL80211_IFTYPE_STATION: |
1289 | iter_data->nstations++; | |
e51f3eff | 1290 | break; |
05c914fe | 1291 | case NL80211_IFTYPE_ADHOC: |
4801416c BG |
1292 | iter_data->nadhocs++; |
1293 | break; | |
9cb5412b | 1294 | case NL80211_IFTYPE_MESH_POINT: |
4801416c BG |
1295 | iter_data->nmeshes++; |
1296 | break; | |
1297 | case NL80211_IFTYPE_WDS: | |
1298 | iter_data->nwds++; | |
f078f209 LR |
1299 | break; |
1300 | default: | |
4801416c BG |
1301 | iter_data->nothers++; |
1302 | break; | |
f078f209 | 1303 | } |
4801416c | 1304 | } |
f078f209 | 1305 | |
4801416c BG |
1306 | /* Called with sc->mutex held. */ |
1307 | void ath9k_calculate_iter_data(struct ieee80211_hw *hw, | |
1308 | struct ieee80211_vif *vif, | |
1309 | struct ath9k_vif_iter_data *iter_data) | |
1310 | { | |
9ac58615 | 1311 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1312 | struct ath_hw *ah = sc->sc_ah; |
1313 | struct ath_common *common = ath9k_hw_common(ah); | |
8feceb67 | 1314 | |
4801416c BG |
1315 | /* |
1316 | * Use the hardware MAC address as reference, the hardware uses it | |
1317 | * together with the BSSID mask when matching addresses. | |
1318 | */ | |
1319 | memset(iter_data, 0, sizeof(*iter_data)); | |
1320 | iter_data->hw_macaddr = common->macaddr; | |
1321 | memset(&iter_data->mask, 0xff, ETH_ALEN); | |
5640b08e | 1322 | |
4801416c BG |
1323 | if (vif) |
1324 | ath9k_vif_iter(iter_data, vif->addr, vif); | |
1325 | ||
1326 | /* Get list of all active MAC addresses */ | |
4801416c BG |
1327 | ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter, |
1328 | iter_data); | |
4801416c | 1329 | } |
8ca21f01 | 1330 | |
4801416c BG |
1331 | /* Called with sc->mutex held. */ |
1332 | static void ath9k_calculate_summary_state(struct ieee80211_hw *hw, | |
1333 | struct ieee80211_vif *vif) | |
1334 | { | |
9ac58615 | 1335 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1336 | struct ath_hw *ah = sc->sc_ah; |
1337 | struct ath_common *common = ath9k_hw_common(ah); | |
1338 | struct ath9k_vif_iter_data iter_data; | |
8ca21f01 | 1339 | |
4801416c | 1340 | ath9k_calculate_iter_data(hw, vif, &iter_data); |
2c3db3d5 | 1341 | |
4801416c BG |
1342 | /* Set BSSID mask. */ |
1343 | memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); | |
1344 | ath_hw_setbssidmask(common); | |
1345 | ||
1346 | /* Set op-mode & TSF */ | |
1347 | if (iter_data.naps > 0) { | |
3069168c | 1348 | ath9k_hw_set_tsfadjust(ah, 1); |
b238e90e | 1349 | sc->sc_flags |= SC_OP_TSF_RESET; |
4801416c BG |
1350 | ah->opmode = NL80211_IFTYPE_AP; |
1351 | } else { | |
1352 | ath9k_hw_set_tsfadjust(ah, 0); | |
1353 | sc->sc_flags &= ~SC_OP_TSF_RESET; | |
5640b08e | 1354 | |
fd5999cf JC |
1355 | if (iter_data.nmeshes) |
1356 | ah->opmode = NL80211_IFTYPE_MESH_POINT; | |
1357 | else if (iter_data.nwds) | |
4801416c BG |
1358 | ah->opmode = NL80211_IFTYPE_AP; |
1359 | else if (iter_data.nadhocs) | |
1360 | ah->opmode = NL80211_IFTYPE_ADHOC; | |
1361 | else | |
1362 | ah->opmode = NL80211_IFTYPE_STATION; | |
1363 | } | |
5640b08e | 1364 | |
4e30ffa2 VN |
1365 | /* |
1366 | * Enable MIB interrupts when there are hardware phy counters. | |
4e30ffa2 | 1367 | */ |
4801416c | 1368 | if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) { |
3448f912 LR |
1369 | if (ah->config.enable_ani) |
1370 | ah->imask |= ATH9K_INT_MIB; | |
3069168c | 1371 | ah->imask |= ATH9K_INT_TSFOOR; |
4801416c BG |
1372 | } else { |
1373 | ah->imask &= ~ATH9K_INT_MIB; | |
1374 | ah->imask &= ~ATH9K_INT_TSFOOR; | |
4af9cf4f S |
1375 | } |
1376 | ||
3069168c | 1377 | ath9k_hw_set_interrupts(ah, ah->imask); |
4e30ffa2 | 1378 | |
4801416c | 1379 | /* Set up ANI */ |
2e5ef459 | 1380 | if (iter_data.naps > 0) { |
729da390 | 1381 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; |
05c0be2f MSS |
1382 | |
1383 | if (!common->disable_ani) { | |
1384 | sc->sc_flags |= SC_OP_ANI_RUN; | |
1385 | ath_start_ani(common); | |
1386 | } | |
1387 | ||
f60c49b6 RM |
1388 | } else { |
1389 | sc->sc_flags &= ~SC_OP_ANI_RUN; | |
1390 | del_timer_sync(&common->ani.timer); | |
6c3118e2 | 1391 | } |
4801416c | 1392 | } |
6f255425 | 1393 | |
4801416c BG |
1394 | /* Called with sc->mutex held, vif counts set up properly. */ |
1395 | static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw, | |
1396 | struct ieee80211_vif *vif) | |
1397 | { | |
9ac58615 | 1398 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1399 | |
1400 | ath9k_calculate_summary_state(hw, vif); | |
1401 | ||
1402 | if (ath9k_uses_beacons(vif->type)) { | |
1403 | int error; | |
4801416c BG |
1404 | /* This may fail because upper levels do not have beacons |
1405 | * properly configured yet. That's OK, we assume it | |
1406 | * will be properly configured and then we will be notified | |
1407 | * in the info_changed method and set up beacons properly | |
1408 | * there. | |
1409 | */ | |
014cf3bb | 1410 | ath9k_set_beaconing_status(sc, false); |
9ac58615 | 1411 | error = ath_beacon_alloc(sc, vif); |
391bd1c4 | 1412 | if (!error) |
4801416c | 1413 | ath_beacon_config(sc, vif); |
014cf3bb | 1414 | ath9k_set_beaconing_status(sc, true); |
4801416c | 1415 | } |
f078f209 LR |
1416 | } |
1417 | ||
4801416c BG |
1418 | |
1419 | static int ath9k_add_interface(struct ieee80211_hw *hw, | |
1420 | struct ieee80211_vif *vif) | |
6b3b991d | 1421 | { |
9ac58615 | 1422 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1423 | struct ath_hw *ah = sc->sc_ah; |
1424 | struct ath_common *common = ath9k_hw_common(ah); | |
4801416c | 1425 | int ret = 0; |
6b3b991d | 1426 | |
96f372c9 | 1427 | ath9k_ps_wakeup(sc); |
4801416c | 1428 | mutex_lock(&sc->mutex); |
6b3b991d | 1429 | |
4801416c BG |
1430 | switch (vif->type) { |
1431 | case NL80211_IFTYPE_STATION: | |
1432 | case NL80211_IFTYPE_WDS: | |
1433 | case NL80211_IFTYPE_ADHOC: | |
1434 | case NL80211_IFTYPE_AP: | |
1435 | case NL80211_IFTYPE_MESH_POINT: | |
1436 | break; | |
1437 | default: | |
1438 | ath_err(common, "Interface type %d not yet supported\n", | |
1439 | vif->type); | |
1440 | ret = -EOPNOTSUPP; | |
1441 | goto out; | |
1442 | } | |
6b3b991d | 1443 | |
4801416c BG |
1444 | if (ath9k_uses_beacons(vif->type)) { |
1445 | if (sc->nbcnvifs >= ATH_BCBUF) { | |
1446 | ath_err(common, "Not enough beacon buffers when adding" | |
1447 | " new interface of type: %i\n", | |
1448 | vif->type); | |
1449 | ret = -ENOBUFS; | |
1450 | goto out; | |
1451 | } | |
1452 | } | |
1453 | ||
59575d1c RM |
1454 | if ((ah->opmode == NL80211_IFTYPE_ADHOC) || |
1455 | ((vif->type == NL80211_IFTYPE_ADHOC) && | |
1456 | sc->nvifs > 0)) { | |
4801416c BG |
1457 | ath_err(common, "Cannot create ADHOC interface when other" |
1458 | " interfaces already exist.\n"); | |
1459 | ret = -EINVAL; | |
1460 | goto out; | |
6b3b991d | 1461 | } |
4801416c BG |
1462 | |
1463 | ath_dbg(common, ATH_DBG_CONFIG, | |
1464 | "Attach a VIF of type: %d\n", vif->type); | |
1465 | ||
4801416c BG |
1466 | sc->nvifs++; |
1467 | ||
1468 | ath9k_do_vif_add_setup(hw, vif); | |
1469 | out: | |
1470 | mutex_unlock(&sc->mutex); | |
96f372c9 | 1471 | ath9k_ps_restore(sc); |
4801416c | 1472 | return ret; |
6b3b991d RM |
1473 | } |
1474 | ||
1475 | static int ath9k_change_interface(struct ieee80211_hw *hw, | |
1476 | struct ieee80211_vif *vif, | |
1477 | enum nl80211_iftype new_type, | |
1478 | bool p2p) | |
1479 | { | |
9ac58615 | 1480 | struct ath_softc *sc = hw->priv; |
6b3b991d | 1481 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
6dab55bf | 1482 | int ret = 0; |
6b3b991d RM |
1483 | |
1484 | ath_dbg(common, ATH_DBG_CONFIG, "Change Interface\n"); | |
1485 | mutex_lock(&sc->mutex); | |
96f372c9 | 1486 | ath9k_ps_wakeup(sc); |
6b3b991d | 1487 | |
4801416c BG |
1488 | /* See if new interface type is valid. */ |
1489 | if ((new_type == NL80211_IFTYPE_ADHOC) && | |
1490 | (sc->nvifs > 1)) { | |
1491 | ath_err(common, "When using ADHOC, it must be the only" | |
1492 | " interface.\n"); | |
1493 | ret = -EINVAL; | |
1494 | goto out; | |
1495 | } | |
1496 | ||
1497 | if (ath9k_uses_beacons(new_type) && | |
1498 | !ath9k_uses_beacons(vif->type)) { | |
6b3b991d RM |
1499 | if (sc->nbcnvifs >= ATH_BCBUF) { |
1500 | ath_err(common, "No beacon slot available\n"); | |
6dab55bf DC |
1501 | ret = -ENOBUFS; |
1502 | goto out; | |
6b3b991d | 1503 | } |
6b3b991d | 1504 | } |
4801416c BG |
1505 | |
1506 | /* Clean up old vif stuff */ | |
1507 | if (ath9k_uses_beacons(vif->type)) | |
1508 | ath9k_reclaim_beacon(sc, vif); | |
1509 | ||
1510 | /* Add new settings */ | |
6b3b991d RM |
1511 | vif->type = new_type; |
1512 | vif->p2p = p2p; | |
1513 | ||
4801416c | 1514 | ath9k_do_vif_add_setup(hw, vif); |
6dab55bf | 1515 | out: |
96f372c9 | 1516 | ath9k_ps_restore(sc); |
6b3b991d | 1517 | mutex_unlock(&sc->mutex); |
6dab55bf | 1518 | return ret; |
6b3b991d RM |
1519 | } |
1520 | ||
8feceb67 | 1521 | static void ath9k_remove_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1522 | struct ieee80211_vif *vif) |
f078f209 | 1523 | { |
9ac58615 | 1524 | struct ath_softc *sc = hw->priv; |
c46917bb | 1525 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
f078f209 | 1526 | |
226afe68 | 1527 | ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n"); |
f078f209 | 1528 | |
96f372c9 | 1529 | ath9k_ps_wakeup(sc); |
141b38b6 S |
1530 | mutex_lock(&sc->mutex); |
1531 | ||
4801416c | 1532 | sc->nvifs--; |
580f0b8a | 1533 | |
8feceb67 | 1534 | /* Reclaim beacon resources */ |
4801416c | 1535 | if (ath9k_uses_beacons(vif->type)) |
6b3b991d | 1536 | ath9k_reclaim_beacon(sc, vif); |
2c3db3d5 | 1537 | |
4801416c | 1538 | ath9k_calculate_summary_state(hw, NULL); |
141b38b6 S |
1539 | |
1540 | mutex_unlock(&sc->mutex); | |
96f372c9 | 1541 | ath9k_ps_restore(sc); |
f078f209 LR |
1542 | } |
1543 | ||
fbab7390 | 1544 | static void ath9k_enable_ps(struct ath_softc *sc) |
3f7c5c10 | 1545 | { |
3069168c PR |
1546 | struct ath_hw *ah = sc->sc_ah; |
1547 | ||
3f7c5c10 | 1548 | sc->ps_enabled = true; |
3069168c PR |
1549 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
1550 | if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { | |
1551 | ah->imask |= ATH9K_INT_TIM_TIMER; | |
1552 | ath9k_hw_set_interrupts(ah, ah->imask); | |
3f7c5c10 | 1553 | } |
fdf76622 | 1554 | ath9k_hw_setrxabort(ah, 1); |
3f7c5c10 | 1555 | } |
3f7c5c10 SB |
1556 | } |
1557 | ||
845d708e SB |
1558 | static void ath9k_disable_ps(struct ath_softc *sc) |
1559 | { | |
1560 | struct ath_hw *ah = sc->sc_ah; | |
1561 | ||
1562 | sc->ps_enabled = false; | |
1563 | ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); | |
1564 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { | |
1565 | ath9k_hw_setrxabort(ah, 0); | |
1566 | sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | | |
1567 | PS_WAIT_FOR_CAB | | |
1568 | PS_WAIT_FOR_PSPOLL_DATA | | |
1569 | PS_WAIT_FOR_TX_ACK); | |
1570 | if (ah->imask & ATH9K_INT_TIM_TIMER) { | |
1571 | ah->imask &= ~ATH9K_INT_TIM_TIMER; | |
1572 | ath9k_hw_set_interrupts(ah, ah->imask); | |
1573 | } | |
1574 | } | |
1575 | ||
1576 | } | |
1577 | ||
e8975581 | 1578 | static int ath9k_config(struct ieee80211_hw *hw, u32 changed) |
f078f209 | 1579 | { |
9ac58615 | 1580 | struct ath_softc *sc = hw->priv; |
3430098a FF |
1581 | struct ath_hw *ah = sc->sc_ah; |
1582 | struct ath_common *common = ath9k_hw_common(ah); | |
e8975581 | 1583 | struct ieee80211_conf *conf = &hw->conf; |
7545daf4 | 1584 | bool disable_radio = false; |
f078f209 | 1585 | |
aa33de09 | 1586 | mutex_lock(&sc->mutex); |
141b38b6 | 1587 | |
194b7c13 LR |
1588 | /* |
1589 | * Leave this as the first check because we need to turn on the | |
1590 | * radio if it was disabled before prior to processing the rest | |
1591 | * of the changes. Likewise we must only disable the radio towards | |
1592 | * the end. | |
1593 | */ | |
64839170 | 1594 | if (changed & IEEE80211_CONF_CHANGE_IDLE) { |
7545daf4 FF |
1595 | sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); |
1596 | if (!sc->ps_idle) { | |
68a89116 | 1597 | ath_radio_enable(sc, hw); |
226afe68 JP |
1598 | ath_dbg(common, ATH_DBG_CONFIG, |
1599 | "not-idle: enabling radio\n"); | |
7545daf4 FF |
1600 | } else { |
1601 | disable_radio = true; | |
64839170 LR |
1602 | } |
1603 | } | |
1604 | ||
e7824a50 LR |
1605 | /* |
1606 | * We just prepare to enable PS. We have to wait until our AP has | |
1607 | * ACK'd our null data frame to disable RX otherwise we'll ignore | |
1608 | * those ACKs and end up retransmitting the same null data frames. | |
1609 | * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. | |
1610 | */ | |
3cbb5dd7 | 1611 | if (changed & IEEE80211_CONF_CHANGE_PS) { |
8ab2cd09 LR |
1612 | unsigned long flags; |
1613 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
fbab7390 SB |
1614 | if (conf->flags & IEEE80211_CONF_PS) |
1615 | ath9k_enable_ps(sc); | |
845d708e SB |
1616 | else |
1617 | ath9k_disable_ps(sc); | |
8ab2cd09 | 1618 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
3cbb5dd7 VN |
1619 | } |
1620 | ||
199afd9d S |
1621 | if (changed & IEEE80211_CONF_CHANGE_MONITOR) { |
1622 | if (conf->flags & IEEE80211_CONF_MONITOR) { | |
226afe68 JP |
1623 | ath_dbg(common, ATH_DBG_CONFIG, |
1624 | "Monitor mode is enabled\n"); | |
5f841b41 RM |
1625 | sc->sc_ah->is_monitoring = true; |
1626 | } else { | |
226afe68 JP |
1627 | ath_dbg(common, ATH_DBG_CONFIG, |
1628 | "Monitor mode is disabled\n"); | |
5f841b41 | 1629 | sc->sc_ah->is_monitoring = false; |
199afd9d S |
1630 | } |
1631 | } | |
1632 | ||
4797938c | 1633 | if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { |
99405f93 | 1634 | struct ieee80211_channel *curchan = hw->conf.channel; |
e338a85e | 1635 | struct ath9k_channel old_chan; |
5f8e077c | 1636 | int pos = curchan->hw_value; |
3430098a FF |
1637 | int old_pos = -1; |
1638 | unsigned long flags; | |
1639 | ||
1640 | if (ah->curchan) | |
1641 | old_pos = ah->curchan - &ah->channels[0]; | |
ae5eb026 | 1642 | |
5ee08656 FF |
1643 | if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) |
1644 | sc->sc_flags |= SC_OP_OFFCHANNEL; | |
1645 | else | |
1646 | sc->sc_flags &= ~SC_OP_OFFCHANNEL; | |
0e2dedf9 | 1647 | |
8c79a610 BG |
1648 | ath_dbg(common, ATH_DBG_CONFIG, |
1649 | "Set channel: %d MHz type: %d\n", | |
1650 | curchan->center_freq, conf->channel_type); | |
f078f209 | 1651 | |
3430098a FF |
1652 | /* update survey stats for the old channel before switching */ |
1653 | spin_lock_irqsave(&common->cc_lock, flags); | |
1654 | ath_update_survey_stats(sc); | |
1655 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
1656 | ||
e338a85e RM |
1657 | /* |
1658 | * Preserve the current channel values, before updating | |
1659 | * the same channel | |
1660 | */ | |
1661 | if (old_pos == pos) { | |
1662 | memcpy(&old_chan, &sc->sc_ah->channels[pos], | |
1663 | sizeof(struct ath9k_channel)); | |
1664 | ah->curchan = &old_chan; | |
1665 | } | |
1666 | ||
1667 | ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos], | |
1668 | curchan, conf->channel_type); | |
1669 | ||
3430098a FF |
1670 | /* |
1671 | * If the operating channel changes, change the survey in-use flags | |
1672 | * along with it. | |
1673 | * Reset the survey data for the new channel, unless we're switching | |
1674 | * back to the operating channel from an off-channel operation. | |
1675 | */ | |
1676 | if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && | |
1677 | sc->cur_survey != &sc->survey[pos]) { | |
1678 | ||
1679 | if (sc->cur_survey) | |
1680 | sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE; | |
1681 | ||
1682 | sc->cur_survey = &sc->survey[pos]; | |
1683 | ||
1684 | memset(sc->cur_survey, 0, sizeof(struct survey_info)); | |
1685 | sc->cur_survey->filled |= SURVEY_INFO_IN_USE; | |
1686 | } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) { | |
1687 | memset(&sc->survey[pos], 0, sizeof(struct survey_info)); | |
1688 | } | |
1689 | ||
0e2dedf9 | 1690 | if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { |
3800276a | 1691 | ath_err(common, "Unable to set channel\n"); |
aa33de09 | 1692 | mutex_unlock(&sc->mutex); |
e11602b7 S |
1693 | return -EINVAL; |
1694 | } | |
3430098a FF |
1695 | |
1696 | /* | |
1697 | * The most recent snapshot of channel->noisefloor for the old | |
1698 | * channel is only available after the hardware reset. Copy it to | |
1699 | * the survey stats now. | |
1700 | */ | |
1701 | if (old_pos >= 0) | |
1702 | ath_update_survey_nf(sc, old_pos); | |
094d05dc | 1703 | } |
f078f209 | 1704 | |
c9f6a656 | 1705 | if (changed & IEEE80211_CONF_CHANGE_POWER) { |
603b3eef BG |
1706 | ath_dbg(common, ATH_DBG_CONFIG, |
1707 | "Set power: %d\n", conf->power_level); | |
17d7904d | 1708 | sc->config.txpowlimit = 2 * conf->power_level; |
783cd01e | 1709 | ath9k_ps_wakeup(sc); |
5048e8c3 RM |
1710 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
1711 | sc->config.txpowlimit, &sc->curtxpow); | |
783cd01e | 1712 | ath9k_ps_restore(sc); |
c9f6a656 | 1713 | } |
f078f209 | 1714 | |
64839170 | 1715 | if (disable_radio) { |
226afe68 | 1716 | ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n"); |
68a89116 | 1717 | ath_radio_disable(sc, hw); |
64839170 LR |
1718 | } |
1719 | ||
aa33de09 | 1720 | mutex_unlock(&sc->mutex); |
141b38b6 | 1721 | |
f078f209 LR |
1722 | return 0; |
1723 | } | |
1724 | ||
8feceb67 VT |
1725 | #define SUPPORTED_FILTERS \ |
1726 | (FIF_PROMISC_IN_BSS | \ | |
1727 | FIF_ALLMULTI | \ | |
1728 | FIF_CONTROL | \ | |
af6a3fc7 | 1729 | FIF_PSPOLL | \ |
8feceb67 VT |
1730 | FIF_OTHER_BSS | \ |
1731 | FIF_BCN_PRBRESP_PROMISC | \ | |
9c1d8e4a | 1732 | FIF_PROBE_REQ | \ |
8feceb67 | 1733 | FIF_FCSFAIL) |
c83be688 | 1734 | |
8feceb67 VT |
1735 | /* FIXME: sc->sc_full_reset ? */ |
1736 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | |
1737 | unsigned int changed_flags, | |
1738 | unsigned int *total_flags, | |
3ac64bee | 1739 | u64 multicast) |
8feceb67 | 1740 | { |
9ac58615 | 1741 | struct ath_softc *sc = hw->priv; |
8feceb67 | 1742 | u32 rfilt; |
f078f209 | 1743 | |
8feceb67 VT |
1744 | changed_flags &= SUPPORTED_FILTERS; |
1745 | *total_flags &= SUPPORTED_FILTERS; | |
f078f209 | 1746 | |
b77f483f | 1747 | sc->rx.rxfilter = *total_flags; |
aa68aeaa | 1748 | ath9k_ps_wakeup(sc); |
8feceb67 VT |
1749 | rfilt = ath_calcrxfilter(sc); |
1750 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | |
aa68aeaa | 1751 | ath9k_ps_restore(sc); |
f078f209 | 1752 | |
226afe68 JP |
1753 | ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG, |
1754 | "Set HW RX filter: 0x%x\n", rfilt); | |
8feceb67 | 1755 | } |
f078f209 | 1756 | |
4ca77860 JB |
1757 | static int ath9k_sta_add(struct ieee80211_hw *hw, |
1758 | struct ieee80211_vif *vif, | |
1759 | struct ieee80211_sta *sta) | |
8feceb67 | 1760 | { |
9ac58615 | 1761 | struct ath_softc *sc = hw->priv; |
93ae2dd2 FF |
1762 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
1763 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1764 | struct ieee80211_key_conf ps_key = { }; | |
f078f209 | 1765 | |
4ca77860 | 1766 | ath_node_attach(sc, sta); |
f59a59fe FF |
1767 | |
1768 | if (vif->type != NL80211_IFTYPE_AP && | |
1769 | vif->type != NL80211_IFTYPE_AP_VLAN) | |
1770 | return 0; | |
1771 | ||
93ae2dd2 | 1772 | an->ps_key = ath_key_config(common, vif, sta, &ps_key); |
4ca77860 JB |
1773 | |
1774 | return 0; | |
1775 | } | |
1776 | ||
93ae2dd2 FF |
1777 | static void ath9k_del_ps_key(struct ath_softc *sc, |
1778 | struct ieee80211_vif *vif, | |
1779 | struct ieee80211_sta *sta) | |
1780 | { | |
1781 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
1782 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1783 | struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key }; | |
1784 | ||
1785 | if (!an->ps_key) | |
1786 | return; | |
1787 | ||
1788 | ath_key_delete(common, &ps_key); | |
1789 | } | |
1790 | ||
4ca77860 JB |
1791 | static int ath9k_sta_remove(struct ieee80211_hw *hw, |
1792 | struct ieee80211_vif *vif, | |
1793 | struct ieee80211_sta *sta) | |
1794 | { | |
9ac58615 | 1795 | struct ath_softc *sc = hw->priv; |
4ca77860 | 1796 | |
93ae2dd2 | 1797 | ath9k_del_ps_key(sc, vif, sta); |
4ca77860 JB |
1798 | ath_node_detach(sc, sta); |
1799 | ||
1800 | return 0; | |
f078f209 LR |
1801 | } |
1802 | ||
5519541d FF |
1803 | static void ath9k_sta_notify(struct ieee80211_hw *hw, |
1804 | struct ieee80211_vif *vif, | |
1805 | enum sta_notify_cmd cmd, | |
1806 | struct ieee80211_sta *sta) | |
1807 | { | |
1808 | struct ath_softc *sc = hw->priv; | |
1809 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1810 | ||
1811 | switch (cmd) { | |
1812 | case STA_NOTIFY_SLEEP: | |
1813 | an->sleeping = true; | |
1814 | if (ath_tx_aggr_sleep(sc, an)) | |
1815 | ieee80211_sta_set_tim(sta); | |
1816 | break; | |
1817 | case STA_NOTIFY_AWAKE: | |
1818 | an->sleeping = false; | |
1819 | ath_tx_aggr_wakeup(sc, an); | |
1820 | break; | |
1821 | } | |
1822 | } | |
1823 | ||
141b38b6 | 1824 | static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue, |
8feceb67 | 1825 | const struct ieee80211_tx_queue_params *params) |
f078f209 | 1826 | { |
9ac58615 | 1827 | struct ath_softc *sc = hw->priv; |
c46917bb | 1828 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
066dae93 | 1829 | struct ath_txq *txq; |
8feceb67 | 1830 | struct ath9k_tx_queue_info qi; |
066dae93 | 1831 | int ret = 0; |
f078f209 | 1832 | |
8feceb67 VT |
1833 | if (queue >= WME_NUM_AC) |
1834 | return 0; | |
f078f209 | 1835 | |
066dae93 FF |
1836 | txq = sc->tx.txq_map[queue]; |
1837 | ||
96f372c9 | 1838 | ath9k_ps_wakeup(sc); |
141b38b6 S |
1839 | mutex_lock(&sc->mutex); |
1840 | ||
1ffb0610 S |
1841 | memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); |
1842 | ||
8feceb67 VT |
1843 | qi.tqi_aifs = params->aifs; |
1844 | qi.tqi_cwmin = params->cw_min; | |
1845 | qi.tqi_cwmax = params->cw_max; | |
1846 | qi.tqi_burstTime = params->txop; | |
f078f209 | 1847 | |
226afe68 JP |
1848 | ath_dbg(common, ATH_DBG_CONFIG, |
1849 | "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", | |
1850 | queue, txq->axq_qnum, params->aifs, params->cw_min, | |
1851 | params->cw_max, params->txop); | |
f078f209 | 1852 | |
066dae93 | 1853 | ret = ath_txq_update(sc, txq->axq_qnum, &qi); |
8feceb67 | 1854 | if (ret) |
3800276a | 1855 | ath_err(common, "TXQ Update failed\n"); |
f078f209 | 1856 | |
94db2936 | 1857 | if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) |
066dae93 | 1858 | if (queue == WME_AC_BE && !ret) |
94db2936 VN |
1859 | ath_beaconq_config(sc); |
1860 | ||
141b38b6 | 1861 | mutex_unlock(&sc->mutex); |
96f372c9 | 1862 | ath9k_ps_restore(sc); |
141b38b6 | 1863 | |
8feceb67 VT |
1864 | return ret; |
1865 | } | |
f078f209 | 1866 | |
8feceb67 VT |
1867 | static int ath9k_set_key(struct ieee80211_hw *hw, |
1868 | enum set_key_cmd cmd, | |
dc822b5d JB |
1869 | struct ieee80211_vif *vif, |
1870 | struct ieee80211_sta *sta, | |
8feceb67 VT |
1871 | struct ieee80211_key_conf *key) |
1872 | { | |
9ac58615 | 1873 | struct ath_softc *sc = hw->priv; |
c46917bb | 1874 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 | 1875 | int ret = 0; |
f078f209 | 1876 | |
3e6109c5 | 1877 | if (ath9k_modparam_nohwcrypt) |
b3bd89ce JM |
1878 | return -ENOSPC; |
1879 | ||
cfdc9a8b JM |
1880 | if (vif->type == NL80211_IFTYPE_ADHOC && |
1881 | (key->cipher == WLAN_CIPHER_SUITE_TKIP || | |
1882 | key->cipher == WLAN_CIPHER_SUITE_CCMP) && | |
1883 | !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { | |
1884 | /* | |
1885 | * For now, disable hw crypto for the RSN IBSS group keys. This | |
1886 | * could be optimized in the future to use a modified key cache | |
1887 | * design to support per-STA RX GTK, but until that gets | |
1888 | * implemented, use of software crypto for group addressed | |
1889 | * frames is a acceptable to allow RSN IBSS to be used. | |
1890 | */ | |
1891 | return -EOPNOTSUPP; | |
1892 | } | |
1893 | ||
141b38b6 | 1894 | mutex_lock(&sc->mutex); |
3cbb5dd7 | 1895 | ath9k_ps_wakeup(sc); |
226afe68 | 1896 | ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n"); |
f078f209 | 1897 | |
8feceb67 VT |
1898 | switch (cmd) { |
1899 | case SET_KEY: | |
93ae2dd2 FF |
1900 | if (sta) |
1901 | ath9k_del_ps_key(sc, vif, sta); | |
1902 | ||
040e539e | 1903 | ret = ath_key_config(common, vif, sta, key); |
6ace2891 JM |
1904 | if (ret >= 0) { |
1905 | key->hw_key_idx = ret; | |
8feceb67 VT |
1906 | /* push IV and Michael MIC generation to stack */ |
1907 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
97359d12 | 1908 | if (key->cipher == WLAN_CIPHER_SUITE_TKIP) |
8feceb67 | 1909 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; |
97359d12 JB |
1910 | if (sc->sc_ah->sw_mgmt_crypto && |
1911 | key->cipher == WLAN_CIPHER_SUITE_CCMP) | |
0ced0e17 | 1912 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT; |
6ace2891 | 1913 | ret = 0; |
8feceb67 VT |
1914 | } |
1915 | break; | |
1916 | case DISABLE_KEY: | |
040e539e | 1917 | ath_key_delete(common, key); |
8feceb67 VT |
1918 | break; |
1919 | default: | |
1920 | ret = -EINVAL; | |
1921 | } | |
f078f209 | 1922 | |
3cbb5dd7 | 1923 | ath9k_ps_restore(sc); |
141b38b6 S |
1924 | mutex_unlock(&sc->mutex); |
1925 | ||
8feceb67 VT |
1926 | return ret; |
1927 | } | |
4f5ef75b RM |
1928 | static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif) |
1929 | { | |
1930 | struct ath_softc *sc = data; | |
1931 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
1932 | struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; | |
1933 | struct ath_vif *avp = (void *)vif->drv_priv; | |
1934 | ||
2e5ef459 RM |
1935 | /* |
1936 | * Skip iteration if primary station vif's bss info | |
1937 | * was not changed | |
1938 | */ | |
1939 | if (sc->sc_flags & SC_OP_PRIM_STA_VIF) | |
1940 | return; | |
1941 | ||
1942 | if (bss_conf->assoc) { | |
1943 | sc->sc_flags |= SC_OP_PRIM_STA_VIF; | |
1944 | avp->primary_sta_vif = true; | |
4f5ef75b RM |
1945 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); |
1946 | common->curaid = bss_conf->aid; | |
1947 | ath9k_hw_write_associd(sc->sc_ah); | |
2e5ef459 | 1948 | ath_dbg(common, ATH_DBG_CONFIG, |
99e4d43a RM |
1949 | "Bss Info ASSOC %d, bssid: %pM\n", |
1950 | bss_conf->aid, common->curbssid); | |
2e5ef459 RM |
1951 | ath_beacon_config(sc, vif); |
1952 | /* | |
1953 | * Request a re-configuration of Beacon related timers | |
1954 | * on the receipt of the first Beacon frame (i.e., | |
1955 | * after time sync with the AP). | |
1956 | */ | |
1957 | sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; | |
1958 | /* Reset rssi stats */ | |
1959 | sc->last_rssi = ATH_RSSI_DUMMY_MARKER; | |
1960 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; | |
99e4d43a | 1961 | |
05c0be2f MSS |
1962 | if (!common->disable_ani) { |
1963 | sc->sc_flags |= SC_OP_ANI_RUN; | |
1964 | ath_start_ani(common); | |
1965 | } | |
1966 | ||
4f5ef75b RM |
1967 | } |
1968 | } | |
1969 | ||
1970 | static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif) | |
1971 | { | |
1972 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
1973 | struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; | |
1974 | struct ath_vif *avp = (void *)vif->drv_priv; | |
1975 | ||
2e5ef459 RM |
1976 | if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) |
1977 | return; | |
1978 | ||
4f5ef75b RM |
1979 | /* Reconfigure bss info */ |
1980 | if (avp->primary_sta_vif && !bss_conf->assoc) { | |
99e4d43a RM |
1981 | ath_dbg(common, ATH_DBG_CONFIG, |
1982 | "Bss Info DISASSOC %d, bssid %pM\n", | |
1983 | common->curaid, common->curbssid); | |
1984 | sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS); | |
4f5ef75b RM |
1985 | avp->primary_sta_vif = false; |
1986 | memset(common->curbssid, 0, ETH_ALEN); | |
1987 | common->curaid = 0; | |
1988 | } | |
1989 | ||
1990 | ieee80211_iterate_active_interfaces_atomic( | |
1991 | sc->hw, ath9k_bss_iter, sc); | |
1992 | ||
1993 | /* | |
1994 | * None of station vifs are associated. | |
1995 | * Clear bssid & aid | |
1996 | */ | |
2e5ef459 | 1997 | if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF)) { |
4f5ef75b | 1998 | ath9k_hw_write_associd(sc->sc_ah); |
99e4d43a RM |
1999 | /* Stop ANI */ |
2000 | sc->sc_flags &= ~SC_OP_ANI_RUN; | |
2001 | del_timer_sync(&common->ani.timer); | |
2002 | } | |
4f5ef75b | 2003 | } |
f078f209 | 2004 | |
8feceb67 VT |
2005 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, |
2006 | struct ieee80211_vif *vif, | |
2007 | struct ieee80211_bss_conf *bss_conf, | |
2008 | u32 changed) | |
2009 | { | |
9ac58615 | 2010 | struct ath_softc *sc = hw->priv; |
2d0ddec5 | 2011 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 2012 | struct ath_common *common = ath9k_hw_common(ah); |
2d0ddec5 | 2013 | struct ath_vif *avp = (void *)vif->drv_priv; |
0005baf4 | 2014 | int slottime; |
c6089ccc | 2015 | int error; |
f078f209 | 2016 | |
96f372c9 | 2017 | ath9k_ps_wakeup(sc); |
141b38b6 S |
2018 | mutex_lock(&sc->mutex); |
2019 | ||
c6089ccc | 2020 | if (changed & BSS_CHANGED_BSSID) { |
4f5ef75b | 2021 | ath9k_config_bss(sc, vif); |
2d0ddec5 | 2022 | |
226afe68 JP |
2023 | ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n", |
2024 | common->curbssid, common->curaid); | |
c6089ccc | 2025 | } |
2d0ddec5 | 2026 | |
2e5ef459 RM |
2027 | if (changed & BSS_CHANGED_IBSS) { |
2028 | /* There can be only one vif available */ | |
2029 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); | |
2030 | common->curaid = bss_conf->aid; | |
2031 | ath9k_hw_write_associd(sc->sc_ah); | |
2032 | ||
2033 | if (bss_conf->ibss_joined) { | |
2034 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; | |
05c0be2f MSS |
2035 | |
2036 | if (!common->disable_ani) { | |
2037 | sc->sc_flags |= SC_OP_ANI_RUN; | |
2038 | ath_start_ani(common); | |
2039 | } | |
2040 | ||
2e5ef459 RM |
2041 | } else { |
2042 | sc->sc_flags &= ~SC_OP_ANI_RUN; | |
2043 | del_timer_sync(&common->ani.timer); | |
2044 | } | |
2045 | } | |
2046 | ||
c6089ccc S |
2047 | /* Enable transmission of beacons (AP, IBSS, MESH) */ |
2048 | if ((changed & BSS_CHANGED_BEACON) || | |
2049 | ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) { | |
014cf3bb | 2050 | ath9k_set_beaconing_status(sc, false); |
9ac58615 | 2051 | error = ath_beacon_alloc(sc, vif); |
c6089ccc S |
2052 | if (!error) |
2053 | ath_beacon_config(sc, vif); | |
014cf3bb | 2054 | ath9k_set_beaconing_status(sc, true); |
0005baf4 FF |
2055 | } |
2056 | ||
2057 | if (changed & BSS_CHANGED_ERP_SLOT) { | |
2058 | if (bss_conf->use_short_slot) | |
2059 | slottime = 9; | |
2060 | else | |
2061 | slottime = 20; | |
2062 | if (vif->type == NL80211_IFTYPE_AP) { | |
2063 | /* | |
2064 | * Defer update, so that connected stations can adjust | |
2065 | * their settings at the same time. | |
2066 | * See beacon.c for more details | |
2067 | */ | |
2068 | sc->beacon.slottime = slottime; | |
2069 | sc->beacon.updateslot = UPDATE; | |
2070 | } else { | |
2071 | ah->slottime = slottime; | |
2072 | ath9k_hw_init_global_settings(ah); | |
2073 | } | |
2d0ddec5 JB |
2074 | } |
2075 | ||
c6089ccc | 2076 | /* Disable transmission of beacons */ |
014cf3bb RM |
2077 | if ((changed & BSS_CHANGED_BEACON_ENABLED) && |
2078 | !bss_conf->enable_beacon) { | |
2079 | ath9k_set_beaconing_status(sc, false); | |
2080 | avp->is_bslot_active = false; | |
2081 | ath9k_set_beaconing_status(sc, true); | |
2082 | } | |
2d0ddec5 | 2083 | |
c6089ccc | 2084 | if (changed & BSS_CHANGED_BEACON_INT) { |
c6089ccc S |
2085 | /* |
2086 | * In case of AP mode, the HW TSF has to be reset | |
2087 | * when the beacon interval changes. | |
2088 | */ | |
2089 | if (vif->type == NL80211_IFTYPE_AP) { | |
2090 | sc->sc_flags |= SC_OP_TSF_RESET; | |
014cf3bb | 2091 | ath9k_set_beaconing_status(sc, false); |
9ac58615 | 2092 | error = ath_beacon_alloc(sc, vif); |
2d0ddec5 JB |
2093 | if (!error) |
2094 | ath_beacon_config(sc, vif); | |
014cf3bb | 2095 | ath9k_set_beaconing_status(sc, true); |
99e4d43a | 2096 | } else |
c6089ccc | 2097 | ath_beacon_config(sc, vif); |
2d0ddec5 JB |
2098 | } |
2099 | ||
8feceb67 | 2100 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
226afe68 JP |
2101 | ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", |
2102 | bss_conf->use_short_preamble); | |
8feceb67 VT |
2103 | if (bss_conf->use_short_preamble) |
2104 | sc->sc_flags |= SC_OP_PREAMBLE_SHORT; | |
2105 | else | |
2106 | sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT; | |
2107 | } | |
f078f209 | 2108 | |
8feceb67 | 2109 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { |
226afe68 JP |
2110 | ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", |
2111 | bss_conf->use_cts_prot); | |
8feceb67 VT |
2112 | if (bss_conf->use_cts_prot && |
2113 | hw->conf.channel->band != IEEE80211_BAND_5GHZ) | |
2114 | sc->sc_flags |= SC_OP_PROTECT_ENABLE; | |
2115 | else | |
2116 | sc->sc_flags &= ~SC_OP_PROTECT_ENABLE; | |
2117 | } | |
f078f209 | 2118 | |
141b38b6 | 2119 | mutex_unlock(&sc->mutex); |
96f372c9 | 2120 | ath9k_ps_restore(sc); |
8feceb67 | 2121 | } |
f078f209 | 2122 | |
8feceb67 VT |
2123 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw) |
2124 | { | |
9ac58615 | 2125 | struct ath_softc *sc = hw->priv; |
8feceb67 | 2126 | u64 tsf; |
f078f209 | 2127 | |
141b38b6 | 2128 | mutex_lock(&sc->mutex); |
9abbfb27 | 2129 | ath9k_ps_wakeup(sc); |
141b38b6 | 2130 | tsf = ath9k_hw_gettsf64(sc->sc_ah); |
9abbfb27 | 2131 | ath9k_ps_restore(sc); |
141b38b6 | 2132 | mutex_unlock(&sc->mutex); |
f078f209 | 2133 | |
8feceb67 VT |
2134 | return tsf; |
2135 | } | |
f078f209 | 2136 | |
3b5d665b AF |
2137 | static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf) |
2138 | { | |
9ac58615 | 2139 | struct ath_softc *sc = hw->priv; |
3b5d665b | 2140 | |
141b38b6 | 2141 | mutex_lock(&sc->mutex); |
9abbfb27 | 2142 | ath9k_ps_wakeup(sc); |
141b38b6 | 2143 | ath9k_hw_settsf64(sc->sc_ah, tsf); |
9abbfb27 | 2144 | ath9k_ps_restore(sc); |
141b38b6 | 2145 | mutex_unlock(&sc->mutex); |
3b5d665b AF |
2146 | } |
2147 | ||
8feceb67 VT |
2148 | static void ath9k_reset_tsf(struct ieee80211_hw *hw) |
2149 | { | |
9ac58615 | 2150 | struct ath_softc *sc = hw->priv; |
c83be688 | 2151 | |
141b38b6 | 2152 | mutex_lock(&sc->mutex); |
21526d57 LR |
2153 | |
2154 | ath9k_ps_wakeup(sc); | |
141b38b6 | 2155 | ath9k_hw_reset_tsf(sc->sc_ah); |
21526d57 LR |
2156 | ath9k_ps_restore(sc); |
2157 | ||
141b38b6 | 2158 | mutex_unlock(&sc->mutex); |
8feceb67 | 2159 | } |
f078f209 | 2160 | |
8feceb67 | 2161 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, |
c951ad35 | 2162 | struct ieee80211_vif *vif, |
141b38b6 S |
2163 | enum ieee80211_ampdu_mlme_action action, |
2164 | struct ieee80211_sta *sta, | |
0b01f030 | 2165 | u16 tid, u16 *ssn, u8 buf_size) |
8feceb67 | 2166 | { |
9ac58615 | 2167 | struct ath_softc *sc = hw->priv; |
8feceb67 | 2168 | int ret = 0; |
f078f209 | 2169 | |
85ad181e JB |
2170 | local_bh_disable(); |
2171 | ||
8feceb67 VT |
2172 | switch (action) { |
2173 | case IEEE80211_AMPDU_RX_START: | |
dca3edb8 S |
2174 | if (!(sc->sc_flags & SC_OP_RXAGGR)) |
2175 | ret = -ENOTSUPP; | |
8feceb67 VT |
2176 | break; |
2177 | case IEEE80211_AMPDU_RX_STOP: | |
8feceb67 VT |
2178 | break; |
2179 | case IEEE80211_AMPDU_TX_START: | |
71a3bf3e FF |
2180 | if (!(sc->sc_flags & SC_OP_TXAGGR)) |
2181 | return -EOPNOTSUPP; | |
2182 | ||
8b685ba9 | 2183 | ath9k_ps_wakeup(sc); |
231c3a1f FF |
2184 | ret = ath_tx_aggr_start(sc, sta, tid, ssn); |
2185 | if (!ret) | |
2186 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); | |
8b685ba9 | 2187 | ath9k_ps_restore(sc); |
8feceb67 VT |
2188 | break; |
2189 | case IEEE80211_AMPDU_TX_STOP: | |
8b685ba9 | 2190 | ath9k_ps_wakeup(sc); |
f83da965 | 2191 | ath_tx_aggr_stop(sc, sta, tid); |
c951ad35 | 2192 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 2193 | ath9k_ps_restore(sc); |
8feceb67 | 2194 | break; |
b1720231 | 2195 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
8b685ba9 | 2196 | ath9k_ps_wakeup(sc); |
8469cdef | 2197 | ath_tx_aggr_resume(sc, sta, tid); |
8b685ba9 | 2198 | ath9k_ps_restore(sc); |
8469cdef | 2199 | break; |
8feceb67 | 2200 | default: |
3800276a | 2201 | ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); |
8feceb67 VT |
2202 | } |
2203 | ||
85ad181e JB |
2204 | local_bh_enable(); |
2205 | ||
8feceb67 | 2206 | return ret; |
f078f209 LR |
2207 | } |
2208 | ||
62dad5b0 BP |
2209 | static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, |
2210 | struct survey_info *survey) | |
2211 | { | |
9ac58615 | 2212 | struct ath_softc *sc = hw->priv; |
3430098a | 2213 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39162dbe | 2214 | struct ieee80211_supported_band *sband; |
3430098a FF |
2215 | struct ieee80211_channel *chan; |
2216 | unsigned long flags; | |
2217 | int pos; | |
2218 | ||
2219 | spin_lock_irqsave(&common->cc_lock, flags); | |
2220 | if (idx == 0) | |
2221 | ath_update_survey_stats(sc); | |
39162dbe FF |
2222 | |
2223 | sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; | |
2224 | if (sband && idx >= sband->n_channels) { | |
2225 | idx -= sband->n_channels; | |
2226 | sband = NULL; | |
2227 | } | |
62dad5b0 | 2228 | |
39162dbe FF |
2229 | if (!sband) |
2230 | sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; | |
62dad5b0 | 2231 | |
3430098a FF |
2232 | if (!sband || idx >= sband->n_channels) { |
2233 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
2234 | return -ENOENT; | |
4f1a5a4b | 2235 | } |
62dad5b0 | 2236 | |
3430098a FF |
2237 | chan = &sband->channels[idx]; |
2238 | pos = chan->hw_value; | |
2239 | memcpy(survey, &sc->survey[pos], sizeof(*survey)); | |
2240 | survey->channel = chan; | |
2241 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
2242 | ||
62dad5b0 BP |
2243 | return 0; |
2244 | } | |
2245 | ||
e239d859 FF |
2246 | static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) |
2247 | { | |
9ac58615 | 2248 | struct ath_softc *sc = hw->priv; |
e239d859 FF |
2249 | struct ath_hw *ah = sc->sc_ah; |
2250 | ||
2251 | mutex_lock(&sc->mutex); | |
2252 | ah->coverage_class = coverage_class; | |
2253 | ath9k_hw_init_global_settings(ah); | |
2254 | mutex_unlock(&sc->mutex); | |
2255 | } | |
2256 | ||
69081624 VT |
2257 | static void ath9k_flush(struct ieee80211_hw *hw, bool drop) |
2258 | { | |
69081624 | 2259 | struct ath_softc *sc = hw->priv; |
99aa55b6 MSS |
2260 | struct ath_hw *ah = sc->sc_ah; |
2261 | struct ath_common *common = ath9k_hw_common(ah); | |
86271e46 FF |
2262 | int timeout = 200; /* ms */ |
2263 | int i, j; | |
2f6fc351 | 2264 | bool drain_txq; |
69081624 VT |
2265 | |
2266 | mutex_lock(&sc->mutex); | |
69081624 VT |
2267 | cancel_delayed_work_sync(&sc->tx_complete_work); |
2268 | ||
99aa55b6 MSS |
2269 | if (sc->sc_flags & SC_OP_INVALID) { |
2270 | ath_dbg(common, ATH_DBG_ANY, "Device not present\n"); | |
2271 | mutex_unlock(&sc->mutex); | |
2272 | return; | |
2273 | } | |
2274 | ||
86271e46 FF |
2275 | if (drop) |
2276 | timeout = 1; | |
69081624 | 2277 | |
86271e46 | 2278 | for (j = 0; j < timeout; j++) { |
108697c4 | 2279 | bool npend = false; |
86271e46 FF |
2280 | |
2281 | if (j) | |
2282 | usleep_range(1000, 2000); | |
69081624 | 2283 | |
86271e46 FF |
2284 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
2285 | if (!ATH_TXQ_SETUP(sc, i)) | |
2286 | continue; | |
2287 | ||
108697c4 MSS |
2288 | npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]); |
2289 | ||
2290 | if (npend) | |
2291 | break; | |
69081624 | 2292 | } |
86271e46 FF |
2293 | |
2294 | if (!npend) | |
2295 | goto out; | |
69081624 VT |
2296 | } |
2297 | ||
51513906 | 2298 | ath9k_ps_wakeup(sc); |
2f6fc351 RM |
2299 | spin_lock_bh(&sc->sc_pcu_lock); |
2300 | drain_txq = ath_drain_all_txq(sc, false); | |
9adcf440 FF |
2301 | spin_unlock_bh(&sc->sc_pcu_lock); |
2302 | ||
2f6fc351 | 2303 | if (!drain_txq) |
69081624 | 2304 | ath_reset(sc, false); |
9adcf440 | 2305 | |
51513906 | 2306 | ath9k_ps_restore(sc); |
d78f4b3e SB |
2307 | ieee80211_wake_queues(hw); |
2308 | ||
86271e46 | 2309 | out: |
69081624 VT |
2310 | ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0); |
2311 | mutex_unlock(&sc->mutex); | |
2312 | } | |
2313 | ||
15b91e83 VN |
2314 | static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) |
2315 | { | |
2316 | struct ath_softc *sc = hw->priv; | |
2317 | int i; | |
2318 | ||
2319 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
2320 | if (!ATH_TXQ_SETUP(sc, i)) | |
2321 | continue; | |
2322 | ||
2323 | if (ath9k_has_pending_frames(sc, &sc->tx.txq[i])) | |
2324 | return true; | |
2325 | } | |
2326 | return false; | |
2327 | } | |
2328 | ||
5595f119 | 2329 | static int ath9k_tx_last_beacon(struct ieee80211_hw *hw) |
ba4903f9 FF |
2330 | { |
2331 | struct ath_softc *sc = hw->priv; | |
2332 | struct ath_hw *ah = sc->sc_ah; | |
2333 | struct ieee80211_vif *vif; | |
2334 | struct ath_vif *avp; | |
2335 | struct ath_buf *bf; | |
2336 | struct ath_tx_status ts; | |
2337 | int status; | |
2338 | ||
2339 | vif = sc->beacon.bslot[0]; | |
2340 | if (!vif) | |
2341 | return 0; | |
2342 | ||
2343 | avp = (void *)vif->drv_priv; | |
2344 | if (!avp->is_bslot_active) | |
2345 | return 0; | |
2346 | ||
2347 | if (!sc->beacon.tx_processed) { | |
2348 | tasklet_disable(&sc->bcon_tasklet); | |
2349 | ||
2350 | bf = avp->av_bcbuf; | |
2351 | if (!bf || !bf->bf_mpdu) | |
2352 | goto skip; | |
2353 | ||
2354 | status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts); | |
2355 | if (status == -EINPROGRESS) | |
2356 | goto skip; | |
2357 | ||
2358 | sc->beacon.tx_processed = true; | |
2359 | sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); | |
2360 | ||
2361 | skip: | |
2362 | tasklet_enable(&sc->bcon_tasklet); | |
2363 | } | |
2364 | ||
2365 | return sc->beacon.tx_last; | |
2366 | } | |
2367 | ||
52c94f41 MSS |
2368 | static int ath9k_get_stats(struct ieee80211_hw *hw, |
2369 | struct ieee80211_low_level_stats *stats) | |
2370 | { | |
2371 | struct ath_softc *sc = hw->priv; | |
2372 | struct ath_hw *ah = sc->sc_ah; | |
2373 | struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats; | |
2374 | ||
2375 | stats->dot11ACKFailureCount = mib_stats->ackrcv_bad; | |
2376 | stats->dot11RTSFailureCount = mib_stats->rts_bad; | |
2377 | stats->dot11FCSErrorCount = mib_stats->fcs_bad; | |
2378 | stats->dot11RTSSuccessCount = mib_stats->rts_good; | |
2379 | return 0; | |
2380 | } | |
2381 | ||
6baff7f9 | 2382 | struct ieee80211_ops ath9k_ops = { |
8feceb67 VT |
2383 | .tx = ath9k_tx, |
2384 | .start = ath9k_start, | |
2385 | .stop = ath9k_stop, | |
2386 | .add_interface = ath9k_add_interface, | |
6b3b991d | 2387 | .change_interface = ath9k_change_interface, |
8feceb67 VT |
2388 | .remove_interface = ath9k_remove_interface, |
2389 | .config = ath9k_config, | |
8feceb67 | 2390 | .configure_filter = ath9k_configure_filter, |
4ca77860 JB |
2391 | .sta_add = ath9k_sta_add, |
2392 | .sta_remove = ath9k_sta_remove, | |
5519541d | 2393 | .sta_notify = ath9k_sta_notify, |
8feceb67 | 2394 | .conf_tx = ath9k_conf_tx, |
8feceb67 | 2395 | .bss_info_changed = ath9k_bss_info_changed, |
8feceb67 | 2396 | .set_key = ath9k_set_key, |
8feceb67 | 2397 | .get_tsf = ath9k_get_tsf, |
3b5d665b | 2398 | .set_tsf = ath9k_set_tsf, |
8feceb67 | 2399 | .reset_tsf = ath9k_reset_tsf, |
4233df6b | 2400 | .ampdu_action = ath9k_ampdu_action, |
62dad5b0 | 2401 | .get_survey = ath9k_get_survey, |
3b319aae | 2402 | .rfkill_poll = ath9k_rfkill_poll_state, |
e239d859 | 2403 | .set_coverage_class = ath9k_set_coverage_class, |
69081624 | 2404 | .flush = ath9k_flush, |
15b91e83 | 2405 | .tx_frames_pending = ath9k_tx_frames_pending, |
52c94f41 MSS |
2406 | .tx_last_beacon = ath9k_tx_last_beacon, |
2407 | .get_stats = ath9k_get_stats, | |
8feceb67 | 2408 | }; |