ath9k: do not enable interrupt on set interrupt mask
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
69081624 18#include <linux/delay.h>
394cf0a1 19#include "ath9k.h"
af03abec 20#include "btcoex.h"
f078f209 21
ff37e337
S
22static u8 parse_mpdudensity(u8 mpdudensity)
23{
24 /*
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
26 * 0 for no restriction
27 * 1 for 1/4 us
28 * 2 for 1/2 us
29 * 3 for 1 us
30 * 4 for 2 us
31 * 5 for 4 us
32 * 6 for 8 us
33 * 7 for 16 us
34 */
35 switch (mpdudensity) {
36 case 0:
37 return 0;
38 case 1:
39 case 2:
40 case 3:
41 /* Our lower layer calculations limit our precision to
42 1 microsecond */
43 return 1;
44 case 4:
45 return 2;
46 case 5:
47 return 4;
48 case 6:
49 return 8;
50 case 7:
51 return 16;
52 default:
53 return 0;
54 }
55}
56
69081624
VT
57static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
58{
59 bool pending = false;
60
61 spin_lock_bh(&txq->axq_lock);
62
63 if (txq->axq_depth || !list_empty(&txq->axq_acq))
64 pending = true;
69081624
VT
65
66 spin_unlock_bh(&txq->axq_lock);
67 return pending;
68}
69
6d79cb4c 70static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR
71{
72 unsigned long flags;
73 bool ret;
74
9ecdef4b
LR
75 spin_lock_irqsave(&sc->sc_pm_lock, flags);
76 ret = ath9k_hw_setpower(sc->sc_ah, mode);
77 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR
78
79 return ret;
80}
81
a91d75ae
LR
82void ath9k_ps_wakeup(struct ath_softc *sc)
83{
898c914a 84 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae 85 unsigned long flags;
fbb078fc 86 enum ath9k_power_mode power_mode;
a91d75ae
LR
87
88 spin_lock_irqsave(&sc->sc_pm_lock, flags);
89 if (++sc->ps_usecount != 1)
90 goto unlock;
91
fbb078fc 92 power_mode = sc->sc_ah->power_mode;
9ecdef4b 93 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae 94
898c914a
FF
95 /*
96 * While the hardware is asleep, the cycle counters contain no
97 * useful data. Better clear them now so that they don't mess up
98 * survey data results.
99 */
fbb078fc
FF
100 if (power_mode != ATH9K_PM_AWAKE) {
101 spin_lock(&common->cc_lock);
102 ath_hw_cycle_counters_update(common);
103 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
104 spin_unlock(&common->cc_lock);
105 }
898c914a 106
a91d75ae
LR
107 unlock:
108 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
109}
110
111void ath9k_ps_restore(struct ath_softc *sc)
112{
898c914a 113 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae
LR
114 unsigned long flags;
115
116 spin_lock_irqsave(&sc->sc_pm_lock, flags);
117 if (--sc->ps_usecount != 0)
118 goto unlock;
119
898c914a
FF
120 spin_lock(&common->cc_lock);
121 ath_hw_cycle_counters_update(common);
122 spin_unlock(&common->cc_lock);
123
1dbfd9d4
VN
124 if (sc->ps_idle)
125 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
126 else if (sc->ps_enabled &&
127 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
1b04b930
S
128 PS_WAIT_FOR_CAB |
129 PS_WAIT_FOR_PSPOLL_DATA |
130 PS_WAIT_FOR_TX_ACK)))
9ecdef4b 131 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
a91d75ae
LR
132
133 unlock:
134 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
135}
136
05c0be2f 137void ath_start_ani(struct ath_common *common)
5ee08656
FF
138{
139 struct ath_hw *ah = common->ah;
140 unsigned long timestamp = jiffies_to_msecs(jiffies);
141 struct ath_softc *sc = (struct ath_softc *) common->priv;
142
143 if (!(sc->sc_flags & SC_OP_ANI_RUN))
144 return;
145
146 if (sc->sc_flags & SC_OP_OFFCHANNEL)
147 return;
148
149 common->ani.longcal_timer = timestamp;
150 common->ani.shortcal_timer = timestamp;
151 common->ani.checkani_timer = timestamp;
152
153 mod_timer(&common->ani.timer,
154 jiffies +
155 msecs_to_jiffies((u32)ah->config.ani_poll_interval));
156}
157
3430098a
FF
158static void ath_update_survey_nf(struct ath_softc *sc, int channel)
159{
160 struct ath_hw *ah = sc->sc_ah;
161 struct ath9k_channel *chan = &ah->channels[channel];
162 struct survey_info *survey = &sc->survey[channel];
163
164 if (chan->noisefloor) {
165 survey->filled |= SURVEY_INFO_NOISE_DBM;
f749b946 166 survey->noise = ath9k_hw_getchan_noise(ah, chan);
3430098a
FF
167 }
168}
169
cb8d61de
FF
170/*
171 * Updates the survey statistics and returns the busy time since last
172 * update in %, if the measurement duration was long enough for the
173 * result to be useful, -1 otherwise.
174 */
175static int ath_update_survey_stats(struct ath_softc *sc)
3430098a
FF
176{
177 struct ath_hw *ah = sc->sc_ah;
178 struct ath_common *common = ath9k_hw_common(ah);
179 int pos = ah->curchan - &ah->channels[0];
180 struct survey_info *survey = &sc->survey[pos];
181 struct ath_cycle_counters *cc = &common->cc_survey;
182 unsigned int div = common->clockrate * 1000;
cb8d61de 183 int ret = 0;
3430098a 184
0845735e 185 if (!ah->curchan)
cb8d61de 186 return -1;
0845735e 187
898c914a
FF
188 if (ah->power_mode == ATH9K_PM_AWAKE)
189 ath_hw_cycle_counters_update(common);
3430098a
FF
190
191 if (cc->cycles > 0) {
192 survey->filled |= SURVEY_INFO_CHANNEL_TIME |
193 SURVEY_INFO_CHANNEL_TIME_BUSY |
194 SURVEY_INFO_CHANNEL_TIME_RX |
195 SURVEY_INFO_CHANNEL_TIME_TX;
196 survey->channel_time += cc->cycles / div;
197 survey->channel_time_busy += cc->rx_busy / div;
198 survey->channel_time_rx += cc->rx_frame / div;
199 survey->channel_time_tx += cc->tx_frame / div;
200 }
cb8d61de
FF
201
202 if (cc->cycles < div)
203 return -1;
204
205 if (cc->cycles > 0)
206 ret = cc->rx_busy * 100 / cc->cycles;
207
3430098a
FF
208 memset(cc, 0, sizeof(*cc));
209
210 ath_update_survey_nf(sc, pos);
cb8d61de
FF
211
212 return ret;
3430098a
FF
213}
214
ff37e337
S
215/*
216 * Set/change channels. If the channel is really being changed, it's done
217 * by reseting the chip. To accomplish this we must first cleanup any pending
218 * DMA, then restart stuff.
219*/
5595f119 220static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
0e2dedf9 221 struct ath9k_channel *hchan)
ff37e337 222{
cbe61d8a 223 struct ath_hw *ah = sc->sc_ah;
c46917bb 224 struct ath_common *common = ath9k_hw_common(ah);
25c56eec 225 struct ieee80211_conf *conf = &common->hw->conf;
ff37e337 226 bool fastcc = true, stopped;
ae8d2858 227 struct ieee80211_channel *channel = hw->conf.channel;
20bd2a09 228 struct ath9k_hw_cal_data *caldata = NULL;
ae8d2858 229 int r;
ff37e337
S
230
231 if (sc->sc_flags & SC_OP_INVALID)
232 return -EIO;
233
cb8d61de
FF
234 sc->hw_busy_count = 0;
235
5ee08656
FF
236 del_timer_sync(&common->ani.timer);
237 cancel_work_sync(&sc->paprd_work);
238 cancel_work_sync(&sc->hw_check_work);
239 cancel_delayed_work_sync(&sc->tx_complete_work);
181fb18d 240 cancel_delayed_work_sync(&sc->hw_pll_work);
5ee08656 241
3cbb5dd7
VN
242 ath9k_ps_wakeup(sc);
243
6a6733f2
LR
244 spin_lock_bh(&sc->sc_pcu_lock);
245
c0d7c7af
LR
246 /*
247 * This is only performed if the channel settings have
248 * actually changed.
249 *
250 * To switch channels clear any pending DMA operations;
251 * wait long enough for the RX fifo to drain, reset the
252 * hardware at the new frequency, and then re-enable
253 * the relevant bits of the h/w.
254 */
4df3071e 255 ath9k_hw_disable_interrupts(ah);
080e1a25 256 stopped = ath_drain_all_txq(sc, false);
5e848f78 257
080e1a25
FF
258 if (!ath_stoprecv(sc))
259 stopped = false;
ff37e337 260
8b3f4616
FF
261 if (!ath9k_hw_check_alive(ah))
262 stopped = false;
263
c0d7c7af
LR
264 /* XXX: do not flush receive queue here. We don't want
265 * to flush data frames already in queue because of
266 * changing channel. */
ff37e337 267
5ee08656 268 if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL))
c0d7c7af
LR
269 fastcc = false;
270
20bd2a09 271 if (!(sc->sc_flags & SC_OP_OFFCHANNEL))
9ac58615 272 caldata = &sc->caldata;
20bd2a09 273
226afe68
JP
274 ath_dbg(common, ATH_DBG_CONFIG,
275 "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n",
276 sc->sc_ah->curchan->channel,
277 channel->center_freq, conf_is_ht40(conf),
278 fastcc);
ff37e337 279
20bd2a09 280 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
c0d7c7af 281 if (r) {
3800276a
JP
282 ath_err(common,
283 "Unable to reset channel (%u MHz), reset status %d\n",
284 channel->center_freq, r);
3989279c 285 goto ps_restore;
ff37e337 286 }
c0d7c7af 287
c0d7c7af 288 if (ath_startrecv(sc) != 0) {
3800276a 289 ath_err(common, "Unable to restart recv logic\n");
3989279c
GJ
290 r = -EIO;
291 goto ps_restore;
c0d7c7af
LR
292 }
293
5048e8c3
RM
294 ath9k_cmn_update_txpow(ah, sc->curtxpow,
295 sc->config.txpowlimit, &sc->curtxpow);
3069168c 296 ath9k_hw_set_interrupts(ah, ah->imask);
b037b693 297 ath9k_hw_enable_interrupts(ah);
3989279c 298
48a6a468 299 if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) {
1186488b 300 if (sc->sc_flags & SC_OP_BEACONS)
99e4d43a 301 ath_set_beacon(sc);
5ee08656 302 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
181fb18d 303 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
05c0be2f
MSS
304 if (!common->disable_ani)
305 ath_start_ani(common);
5ee08656
FF
306 }
307
3989279c 308 ps_restore:
92460412
FF
309 ieee80211_wake_queues(hw);
310
6a6733f2
LR
311 spin_unlock_bh(&sc->sc_pcu_lock);
312
3cbb5dd7 313 ath9k_ps_restore(sc);
3989279c 314 return r;
ff37e337
S
315}
316
9f42c2b6
FF
317static void ath_paprd_activate(struct ath_softc *sc)
318{
319 struct ath_hw *ah = sc->sc_ah;
20bd2a09 320 struct ath9k_hw_cal_data *caldata = ah->caldata;
9094537c 321 struct ath_common *common = ath9k_hw_common(ah);
9f42c2b6
FF
322 int chain;
323
20bd2a09 324 if (!caldata || !caldata->paprd_done)
9f42c2b6
FF
325 return;
326
327 ath9k_ps_wakeup(sc);
ddfef792 328 ar9003_paprd_enable(ah, false);
9f42c2b6 329 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
9094537c 330 if (!(common->tx_chainmask & BIT(chain)))
9f42c2b6
FF
331 continue;
332
20bd2a09 333 ar9003_paprd_populate_single_table(ah, caldata, chain);
9f42c2b6
FF
334 }
335
336 ar9003_paprd_enable(ah, true);
337 ath9k_ps_restore(sc);
338}
339
7607cbe2
FF
340static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
341{
342 struct ieee80211_hw *hw = sc->hw;
343 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
47960077
MSS
344 struct ath_hw *ah = sc->sc_ah;
345 struct ath_common *common = ath9k_hw_common(ah);
7607cbe2
FF
346 struct ath_tx_control txctl;
347 int time_left;
348
349 memset(&txctl, 0, sizeof(txctl));
350 txctl.txq = sc->tx.txq_map[WME_AC_BE];
351
352 memset(tx_info, 0, sizeof(*tx_info));
353 tx_info->band = hw->conf.channel->band;
354 tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
355 tx_info->control.rates[0].idx = 0;
356 tx_info->control.rates[0].count = 1;
357 tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
358 tx_info->control.rates[1].idx = -1;
359
360 init_completion(&sc->paprd_complete);
7607cbe2 361 txctl.paprd = BIT(chain);
47960077
MSS
362
363 if (ath_tx_start(hw, skb, &txctl) != 0) {
d4bb17c4 364 ath_dbg(common, ATH_DBG_CALIBRATE, "PAPRD TX failed\n");
47960077 365 dev_kfree_skb_any(skb);
7607cbe2 366 return false;
47960077 367 }
7607cbe2
FF
368
369 time_left = wait_for_completion_timeout(&sc->paprd_complete,
370 msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
7607cbe2
FF
371
372 if (!time_left)
d4bb17c4 373 ath_dbg(common, ATH_DBG_CALIBRATE,
7607cbe2
FF
374 "Timeout waiting for paprd training on TX chain %d\n",
375 chain);
376
377 return !!time_left;
378}
379
9f42c2b6
FF
380void ath_paprd_calibrate(struct work_struct *work)
381{
382 struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
383 struct ieee80211_hw *hw = sc->hw;
384 struct ath_hw *ah = sc->sc_ah;
385 struct ieee80211_hdr *hdr;
386 struct sk_buff *skb = NULL;
20bd2a09 387 struct ath9k_hw_cal_data *caldata = ah->caldata;
9094537c 388 struct ath_common *common = ath9k_hw_common(ah);
066dae93 389 int ftype;
9f42c2b6
FF
390 int chain_ok = 0;
391 int chain;
392 int len = 1800;
9f42c2b6 393
20bd2a09
FF
394 if (!caldata)
395 return;
396
b942471b
MSS
397 ath9k_ps_wakeup(sc);
398
1bf38661 399 if (ar9003_paprd_init_table(ah) < 0)
b942471b 400 goto fail_paprd;
1bf38661 401
9f42c2b6
FF
402 skb = alloc_skb(len, GFP_KERNEL);
403 if (!skb)
b942471b 404 goto fail_paprd;
9f42c2b6 405
9f42c2b6
FF
406 skb_put(skb, len);
407 memset(skb->data, 0, len);
408 hdr = (struct ieee80211_hdr *)skb->data;
409 ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
410 hdr->frame_control = cpu_to_le16(ftype);
a3d3da14 411 hdr->duration_id = cpu_to_le16(10);
9f42c2b6
FF
412 memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
413 memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
414 memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
415
9f42c2b6 416 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
9094537c 417 if (!(common->tx_chainmask & BIT(chain)))
9f42c2b6
FF
418 continue;
419
420 chain_ok = 0;
9f42c2b6 421
7607cbe2
FF
422 ath_dbg(common, ATH_DBG_CALIBRATE,
423 "Sending PAPRD frame for thermal measurement "
424 "on chain %d\n", chain);
425 if (!ath_paprd_send_frame(sc, skb, chain))
426 goto fail_paprd;
9f42c2b6 427
9f42c2b6 428 ar9003_paprd_setup_gain_table(ah, chain);
9f42c2b6 429
7607cbe2
FF
430 ath_dbg(common, ATH_DBG_CALIBRATE,
431 "Sending PAPRD training frame on chain %d\n", chain);
432 if (!ath_paprd_send_frame(sc, skb, chain))
ca369eb4 433 goto fail_paprd;
9f42c2b6 434
d4bb17c4
MSS
435 if (!ar9003_paprd_is_done(ah)) {
436 ath_dbg(common, ATH_DBG_CALIBRATE,
437 "PAPRD not yet done on chain %d\n", chain);
9f42c2b6 438 break;
d4bb17c4 439 }
9f42c2b6 440
d4bb17c4
MSS
441 if (ar9003_paprd_create_curve(ah, caldata, chain)) {
442 ath_dbg(common, ATH_DBG_CALIBRATE,
443 "PAPRD create curve failed on chain %d\n",
444 chain);
9f42c2b6 445 break;
d4bb17c4 446 }
9f42c2b6
FF
447
448 chain_ok = 1;
449 }
450 kfree_skb(skb);
451
452 if (chain_ok) {
20bd2a09 453 caldata->paprd_done = true;
9f42c2b6
FF
454 ath_paprd_activate(sc);
455 }
456
ca369eb4 457fail_paprd:
9f42c2b6
FF
458 ath9k_ps_restore(sc);
459}
460
ff37e337
S
461/*
462 * This routine performs the periodic noise floor calibration function
463 * that is used to adjust and optimize the chip performance. This
464 * takes environmental changes (location, temperature) into account.
465 * When the task is complete, it reschedules itself depending on the
466 * appropriate interval that was calculated.
467 */
55624204 468void ath_ani_calibrate(unsigned long data)
ff37e337 469{
20977d3e
S
470 struct ath_softc *sc = (struct ath_softc *)data;
471 struct ath_hw *ah = sc->sc_ah;
c46917bb 472 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
473 bool longcal = false;
474 bool shortcal = false;
475 bool aniflag = false;
476 unsigned int timestamp = jiffies_to_msecs(jiffies);
6044474e 477 u32 cal_interval, short_cal_interval, long_cal_interval;
b5bfc568 478 unsigned long flags;
6044474e
FF
479
480 if (ah->caldata && ah->caldata->nfcal_interference)
481 long_cal_interval = ATH_LONG_CALINTERVAL_INT;
482 else
483 long_cal_interval = ATH_LONG_CALINTERVAL;
ff37e337 484
20977d3e
S
485 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
486 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337 487
1ffc1c61
JM
488 /* Only calibrate if awake */
489 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
490 goto set_timer;
491
492 ath9k_ps_wakeup(sc);
493
ff37e337 494 /* Long calibration runs independently of short calibration. */
6044474e 495 if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
ff37e337 496 longcal = true;
226afe68 497 ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
3d536acf 498 common->ani.longcal_timer = timestamp;
ff37e337
S
499 }
500
17d7904d 501 /* Short calibration applies only while caldone is false */
3d536acf
LR
502 if (!common->ani.caldone) {
503 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 504 shortcal = true;
226afe68
JP
505 ath_dbg(common, ATH_DBG_ANI,
506 "shortcal @%lu\n", jiffies);
3d536acf
LR
507 common->ani.shortcal_timer = timestamp;
508 common->ani.resetcal_timer = timestamp;
ff37e337
S
509 }
510 } else {
3d536acf 511 if ((timestamp - common->ani.resetcal_timer) >=
ff37e337 512 ATH_RESTART_CALINTERVAL) {
3d536acf
LR
513 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
514 if (common->ani.caldone)
515 common->ani.resetcal_timer = timestamp;
ff37e337
S
516 }
517 }
518
519 /* Verify whether we must check ANI */
e36b27af
LR
520 if ((timestamp - common->ani.checkani_timer) >=
521 ah->config.ani_poll_interval) {
ff37e337 522 aniflag = true;
3d536acf 523 common->ani.checkani_timer = timestamp;
ff37e337
S
524 }
525
e62ddec9
MSS
526 /* Call ANI routine if necessary */
527 if (aniflag) {
528 spin_lock_irqsave(&common->cc_lock, flags);
529 ath9k_hw_ani_monitor(ah, ah->curchan);
530 ath_update_survey_stats(sc);
531 spin_unlock_irqrestore(&common->cc_lock, flags);
532 }
ff37e337 533
e62ddec9
MSS
534 /* Perform calibration if necessary */
535 if (longcal || shortcal) {
536 common->ani.caldone =
537 ath9k_hw_calibrate(ah, ah->curchan,
538 common->rx_chainmask, longcal);
ff37e337
S
539 }
540
1ffc1c61
JM
541 ath9k_ps_restore(sc);
542
20977d3e 543set_timer:
ff37e337
S
544 /*
545 * Set timer interval based on previous results.
546 * The interval must be the shortest necessary to satisfy ANI,
547 * short calibration and long calibration.
548 */
aac9207e 549 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 550 if (sc->sc_ah->config.enable_ani)
e36b27af
LR
551 cal_interval = min(cal_interval,
552 (u32)ah->config.ani_poll_interval);
3d536acf 553 if (!common->ani.caldone)
20977d3e 554 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 555
3d536acf 556 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
20bd2a09
FF
557 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
558 if (!ah->caldata->paprd_done)
9f42c2b6 559 ieee80211_queue_work(sc->hw, &sc->paprd_work);
45ef6a0b 560 else if (!ah->paprd_table_write_done)
9f42c2b6
FF
561 ath_paprd_activate(sc);
562 }
ff37e337
S
563}
564
ff37e337
S
565static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
566{
567 struct ath_node *an;
ea066d5a 568 struct ath_hw *ah = sc->sc_ah;
ff37e337
S
569 an = (struct ath_node *)sta->drv_priv;
570
7f010c93
BG
571#ifdef CONFIG_ATH9K_DEBUGFS
572 spin_lock(&sc->nodes_lock);
573 list_add(&an->list, &sc->nodes);
574 spin_unlock(&sc->nodes_lock);
575 an->sta = sta;
576#endif
ea066d5a
MSS
577 if ((ah->caps.hw_caps) & ATH9K_HW_CAP_APM)
578 sc->sc_flags |= SC_OP_ENABLE_APM;
579
87792efc 580 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 581 ath_tx_node_init(sc, an);
9e98ac65 582 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S
583 sta->ht_cap.ampdu_factor);
584 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
585 }
ff37e337
S
586}
587
588static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
589{
590 struct ath_node *an = (struct ath_node *)sta->drv_priv;
591
7f010c93
BG
592#ifdef CONFIG_ATH9K_DEBUGFS
593 spin_lock(&sc->nodes_lock);
594 list_del(&an->list);
595 spin_unlock(&sc->nodes_lock);
596 an->sta = NULL;
597#endif
598
ff37e337
S
599 if (sc->sc_flags & SC_OP_TXAGGR)
600 ath_tx_node_cleanup(sc, an);
601}
602
347809fc
FF
603void ath_hw_check(struct work_struct *work)
604{
605 struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
cb8d61de
FF
606 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
607 unsigned long flags;
608 int busy;
347809fc
FF
609
610 ath9k_ps_wakeup(sc);
cb8d61de
FF
611 if (ath9k_hw_check_alive(sc->sc_ah))
612 goto out;
347809fc 613
cb8d61de
FF
614 spin_lock_irqsave(&common->cc_lock, flags);
615 busy = ath_update_survey_stats(sc);
616 spin_unlock_irqrestore(&common->cc_lock, flags);
347809fc 617
cb8d61de
FF
618 ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, "
619 "busy=%d (try %d)\n", busy, sc->hw_busy_count + 1);
620 if (busy >= 99) {
f6b4e4d4
RM
621 if (++sc->hw_busy_count >= 3) {
622 spin_lock_bh(&sc->sc_pcu_lock);
cb8d61de 623 ath_reset(sc, true);
f6b4e4d4
RM
624 spin_unlock_bh(&sc->sc_pcu_lock);
625 }
cb8d61de
FF
626 } else if (busy >= 0)
627 sc->hw_busy_count = 0;
347809fc
FF
628
629out:
630 ath9k_ps_restore(sc);
631}
632
b84628eb
SB
633static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)
634{
635 static int count;
636 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
637
638 if (pll_sqsum >= 0x40000) {
639 count++;
640 if (count == 3) {
641 /* Rx is hung for more than 500ms. Reset it */
642 ath_dbg(common, ATH_DBG_RESET,
643 "Possible RX hang, resetting");
f6b4e4d4 644 spin_lock_bh(&sc->sc_pcu_lock);
b84628eb 645 ath_reset(sc, true);
f6b4e4d4 646 spin_unlock_bh(&sc->sc_pcu_lock);
b84628eb
SB
647 count = 0;
648 }
649 } else
650 count = 0;
651}
652
9eab61c2
SB
653void ath_hw_pll_work(struct work_struct *work)
654{
655 struct ath_softc *sc = container_of(work, struct ath_softc,
656 hw_pll_work.work);
b84628eb 657 u32 pll_sqsum;
9eab61c2
SB
658
659 if (AR_SREV_9485(sc->sc_ah)) {
b84628eb
SB
660
661 ath9k_ps_wakeup(sc);
662 pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah);
663 ath9k_ps_restore(sc);
664
665 ath_hw_pll_rx_hang_check(sc, pll_sqsum);
9eab61c2
SB
666
667 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5);
668 }
669}
670
671
55624204 672void ath9k_tasklet(unsigned long data)
ff37e337
S
673{
674 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 675 struct ath_hw *ah = sc->sc_ah;
c46917bb 676 struct ath_common *common = ath9k_hw_common(ah);
af03abec 677
17d7904d 678 u32 status = sc->intrstatus;
b5c80475 679 u32 rxmask;
ff37e337 680
a4d86d95
RM
681 if ((status & ATH9K_INT_FATAL) ||
682 (status & ATH9K_INT_BB_WATCHDOG)) {
f6b4e4d4 683 spin_lock(&sc->sc_pcu_lock);
fac6b6a0 684 ath_reset(sc, true);
f6b4e4d4 685 spin_unlock(&sc->sc_pcu_lock);
ff37e337 686 return;
063d8be3 687 }
ff37e337 688
783cd01e 689 ath9k_ps_wakeup(sc);
52671e43 690 spin_lock(&sc->sc_pcu_lock);
6a6733f2 691
8b3f4616
FF
692 /*
693 * Only run the baseband hang check if beacons stop working in AP or
694 * IBSS mode, because it has a high false positive rate. For station
695 * mode it should not be necessary, since the upper layers will detect
696 * this through a beacon miss automatically and the following channel
697 * change will trigger a hardware reset anyway
698 */
699 if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 &&
700 !ath9k_hw_check_alive(ah))
347809fc
FF
701 ieee80211_queue_work(sc->hw, &sc->hw_check_work);
702
4105f807
RM
703 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
704 /*
705 * TSF sync does not look correct; remain awake to sync with
706 * the next Beacon.
707 */
708 ath_dbg(common, ATH_DBG_PS,
709 "TSFOOR - Sync with next Beacon\n");
710 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC |
711 PS_TSFOOR_SYNC;
712 }
713
b5c80475
FF
714 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
715 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
716 ATH9K_INT_RXORN);
717 else
718 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
719
720 if (status & rxmask) {
b5c80475
FF
721 /* Check for high priority Rx first */
722 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
723 (status & ATH9K_INT_RXHP))
724 ath_rx_tasklet(sc, 0, true);
725
726 ath_rx_tasklet(sc, 0, false);
ff37e337
S
727 }
728
e5003249
VT
729 if (status & ATH9K_INT_TX) {
730 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
731 ath_tx_edma_tasklet(sc);
732 else
733 ath_tx_tasklet(sc);
734 }
063d8be3 735
766ec4a9 736 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
ebb8e1d7
VT
737 if (status & ATH9K_INT_GENTIMER)
738 ath_gen_timer_isr(sc->sc_ah);
739
ff37e337 740 /* re-enable hardware interrupt */
4df3071e 741 ath9k_hw_enable_interrupts(ah);
6a6733f2 742
52671e43 743 spin_unlock(&sc->sc_pcu_lock);
153e080d 744 ath9k_ps_restore(sc);
ff37e337
S
745}
746
6baff7f9 747irqreturn_t ath_isr(int irq, void *dev)
ff37e337 748{
063d8be3
S
749#define SCHED_INTR ( \
750 ATH9K_INT_FATAL | \
a4d86d95 751 ATH9K_INT_BB_WATCHDOG | \
063d8be3
S
752 ATH9K_INT_RXORN | \
753 ATH9K_INT_RXEOL | \
754 ATH9K_INT_RX | \
b5c80475
FF
755 ATH9K_INT_RXLP | \
756 ATH9K_INT_RXHP | \
063d8be3
S
757 ATH9K_INT_TX | \
758 ATH9K_INT_BMISS | \
759 ATH9K_INT_CST | \
ebb8e1d7
VT
760 ATH9K_INT_TSFOOR | \
761 ATH9K_INT_GENTIMER)
063d8be3 762
ff37e337 763 struct ath_softc *sc = dev;
cbe61d8a 764 struct ath_hw *ah = sc->sc_ah;
b5bfc568 765 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
766 enum ath9k_int status;
767 bool sched = false;
768
063d8be3
S
769 /*
770 * The hardware is not ready/present, don't
771 * touch anything. Note this can happen early
772 * on if the IRQ is shared.
773 */
774 if (sc->sc_flags & SC_OP_INVALID)
775 return IRQ_NONE;
ff37e337 776
063d8be3
S
777
778 /* shared irq, not for us */
779
153e080d 780 if (!ath9k_hw_intrpend(ah))
063d8be3 781 return IRQ_NONE;
063d8be3
S
782
783 /*
784 * Figure out the reason(s) for the interrupt. Note
785 * that the hal returns a pseudo-ISR that may include
786 * bits we haven't explicitly enabled so we mask the
787 * value to insure we only process bits we requested.
788 */
789 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
3069168c 790 status &= ah->imask; /* discard unasked-for bits */
ff37e337 791
063d8be3
S
792 /*
793 * If there are no status bits set, then this interrupt was not
794 * for me (should have been caught above).
795 */
153e080d 796 if (!status)
063d8be3 797 return IRQ_NONE;
ff37e337 798
063d8be3
S
799 /* Cache the status */
800 sc->intrstatus = status;
801
802 if (status & SCHED_INTR)
803 sched = true;
804
805 /*
806 * If a FATAL or RXORN interrupt is received, we have to reset the
807 * chip immediately.
808 */
b5c80475
FF
809 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
810 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
063d8be3
S
811 goto chip_reset;
812
08578b8f
LR
813 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
814 (status & ATH9K_INT_BB_WATCHDOG)) {
b5bfc568
FF
815
816 spin_lock(&common->cc_lock);
817 ath_hw_cycle_counters_update(common);
08578b8f 818 ar9003_hw_bb_watchdog_dbg_info(ah);
b5bfc568
FF
819 spin_unlock(&common->cc_lock);
820
08578b8f
LR
821 goto chip_reset;
822 }
823
063d8be3
S
824 if (status & ATH9K_INT_SWBA)
825 tasklet_schedule(&sc->bcon_tasklet);
826
827 if (status & ATH9K_INT_TXURN)
828 ath9k_hw_updatetxtriglevel(ah, true);
829
b5c80475
FF
830 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
831 if (status & ATH9K_INT_RXEOL) {
832 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
833 ath9k_hw_set_interrupts(ah, ah->imask);
834 }
835 }
836
063d8be3 837 if (status & ATH9K_INT_MIB) {
ff37e337 838 /*
063d8be3
S
839 * Disable interrupts until we service the MIB
840 * interrupt; otherwise it will continue to
841 * fire.
ff37e337 842 */
4df3071e 843 ath9k_hw_disable_interrupts(ah);
063d8be3
S
844 /*
845 * Let the hal handle the event. We assume
846 * it will clear whatever condition caused
847 * the interrupt.
848 */
88eac2da 849 spin_lock(&common->cc_lock);
bfc472bb 850 ath9k_hw_proc_mib_event(ah);
88eac2da 851 spin_unlock(&common->cc_lock);
4df3071e 852 ath9k_hw_enable_interrupts(ah);
063d8be3 853 }
ff37e337 854
153e080d
VT
855 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
856 if (status & ATH9K_INT_TIM_TIMER) {
ff9f0b63
LR
857 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
858 goto chip_reset;
063d8be3
S
859 /* Clear RxAbort bit so that we can
860 * receive frames */
9ecdef4b 861 ath9k_setpower(sc, ATH9K_PM_AWAKE);
153e080d 862 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930 863 sc->ps_flags |= PS_WAIT_FOR_BEACON;
ff37e337 864 }
063d8be3
S
865
866chip_reset:
ff37e337 867
817e11de
S
868 ath_debug_stat_interrupt(sc, status);
869
ff37e337 870 if (sched) {
4df3071e
FF
871 /* turn off every interrupt */
872 ath9k_hw_disable_interrupts(ah);
ff37e337
S
873 tasklet_schedule(&sc->intr_tq);
874 }
875
876 return IRQ_HANDLED;
063d8be3
S
877
878#undef SCHED_INTR
ff37e337
S
879}
880
5595f119 881static void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 882{
cbe61d8a 883 struct ath_hw *ah = sc->sc_ah;
c46917bb 884 struct ath_common *common = ath9k_hw_common(ah);
68a89116 885 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 886 int r;
500c064d 887
3cbb5dd7 888 ath9k_ps_wakeup(sc);
6a6733f2
LR
889 spin_lock_bh(&sc->sc_pcu_lock);
890
93b1b37f 891 ath9k_hw_configpcipowersave(ah, 0, 0);
ae8d2858 892
159cd468 893 if (!ah->curchan)
c344c9cb 894 ah->curchan = ath9k_cmn_get_curchannel(sc->hw, ah);
159cd468 895
20bd2a09 896 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ae8d2858 897 if (r) {
3800276a
JP
898 ath_err(common,
899 "Unable to reset channel (%u MHz), reset status %d\n",
900 channel->center_freq, r);
500c064d 901 }
500c064d 902
5048e8c3
RM
903 ath9k_cmn_update_txpow(ah, sc->curtxpow,
904 sc->config.txpowlimit, &sc->curtxpow);
500c064d 905 if (ath_startrecv(sc) != 0) {
3800276a 906 ath_err(common, "Unable to restart recv logic\n");
c2731b81 907 goto out;
500c064d 908 }
500c064d 909 if (sc->sc_flags & SC_OP_BEACONS)
99e4d43a 910 ath_set_beacon(sc); /* restart beacons */
500c064d
VT
911
912 /* Re-Enable interrupts */
3069168c 913 ath9k_hw_set_interrupts(ah, ah->imask);
b037b693 914 ath9k_hw_enable_interrupts(ah);
500c064d
VT
915
916 /* Enable LED */
08fc5c1b 917 ath9k_hw_cfg_output(ah, ah->led_pin,
500c064d 918 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b 919 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
500c064d 920
68a89116 921 ieee80211_wake_queues(hw);
7e3514fd
VN
922 ieee80211_queue_delayed_work(hw, &sc->hw_pll_work, HZ/2);
923
c2731b81 924out:
6a6733f2
LR
925 spin_unlock_bh(&sc->sc_pcu_lock);
926
3cbb5dd7 927 ath9k_ps_restore(sc);
500c064d
VT
928}
929
68a89116 930void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 931{
cbe61d8a 932 struct ath_hw *ah = sc->sc_ah;
68a89116 933 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 934 int r;
500c064d 935
3cbb5dd7 936 ath9k_ps_wakeup(sc);
7e3514fd
VN
937 cancel_delayed_work_sync(&sc->hw_pll_work);
938
6a6733f2
LR
939 spin_lock_bh(&sc->sc_pcu_lock);
940
68a89116 941 ieee80211_stop_queues(hw);
500c064d 942
982723df
VN
943 /*
944 * Keep the LED on when the radio is disabled
945 * during idle unassociated state.
946 */
947 if (!sc->ps_idle) {
948 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
949 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
950 }
500c064d
VT
951
952 /* Disable interrupts */
4df3071e 953 ath9k_hw_disable_interrupts(ah);
500c064d 954
043a0405 955 ath_drain_all_txq(sc, false); /* clear pending tx frames */
5e848f78 956
500c064d
VT
957 ath_stoprecv(sc); /* turn off frame recv */
958 ath_flushrecv(sc); /* flush recv queue */
959
159cd468 960 if (!ah->curchan)
c344c9cb 961 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
159cd468 962
20bd2a09 963 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ae8d2858 964 if (r) {
3800276a
JP
965 ath_err(ath9k_hw_common(sc->sc_ah),
966 "Unable to reset channel (%u MHz), reset status %d\n",
967 channel->center_freq, r);
500c064d 968 }
500c064d
VT
969
970 ath9k_hw_phy_disable(ah);
5e848f78 971
93b1b37f 972 ath9k_hw_configpcipowersave(ah, 1, 1);
6a6733f2
LR
973
974 spin_unlock_bh(&sc->sc_pcu_lock);
3cbb5dd7 975 ath9k_ps_restore(sc);
500c064d
VT
976}
977
ff37e337
S
978int ath_reset(struct ath_softc *sc, bool retry_tx)
979{
cbe61d8a 980 struct ath_hw *ah = sc->sc_ah;
c46917bb 981 struct ath_common *common = ath9k_hw_common(ah);
030bb495 982 struct ieee80211_hw *hw = sc->hw;
ae8d2858 983 int r;
ff37e337 984
cb8d61de
FF
985 sc->hw_busy_count = 0;
986
2ab81d4a 987 /* Stop ANI */
05c0be2f 988
2ab81d4a
S
989 del_timer_sync(&common->ani.timer);
990
783cd01e 991 ath9k_ps_wakeup(sc);
6a6733f2 992
cc9c378a
S
993 ieee80211_stop_queues(hw);
994
4df3071e 995 ath9k_hw_disable_interrupts(ah);
043a0405 996 ath_drain_all_txq(sc, retry_tx);
5e848f78 997
ff37e337
S
998 ath_stoprecv(sc);
999 ath_flushrecv(sc);
1000
20bd2a09 1001 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
ae8d2858 1002 if (r)
3800276a
JP
1003 ath_err(common,
1004 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S
1005
1006 if (ath_startrecv(sc) != 0)
3800276a 1007 ath_err(common, "Unable to start recv logic\n");
ff37e337
S
1008
1009 /*
1010 * We may be doing a reset in response to a request
1011 * that changes the channel so update any state that
1012 * might change as a result.
1013 */
5048e8c3
RM
1014 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1015 sc->config.txpowlimit, &sc->curtxpow);
ff37e337 1016
52b8ac92 1017 if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL)))
99e4d43a 1018 ath_set_beacon(sc); /* restart beacons */
ff37e337 1019
3069168c 1020 ath9k_hw_set_interrupts(ah, ah->imask);
b037b693 1021 ath9k_hw_enable_interrupts(ah);
ff37e337
S
1022
1023 if (retry_tx) {
1024 int i;
1025 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1026 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S
1027 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1028 ath_txq_schedule(sc, &sc->tx.txq[i]);
1029 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S
1030 }
1031 }
1032 }
1033
cc9c378a
S
1034 ieee80211_wake_queues(hw);
1035
2ab81d4a 1036 /* Start ANI */
05c0be2f
MSS
1037 if (!common->disable_ani)
1038 ath_start_ani(common);
1039
783cd01e 1040 ath9k_ps_restore(sc);
2ab81d4a 1041
ae8d2858 1042 return r;
ff37e337
S
1043}
1044
ff37e337
S
1045/**********************/
1046/* mac80211 callbacks */
1047/**********************/
1048
8feceb67 1049static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1050{
9ac58615 1051 struct ath_softc *sc = hw->priv;
af03abec 1052 struct ath_hw *ah = sc->sc_ah;
c46917bb 1053 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 1054 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1055 struct ath9k_channel *init_channel;
82880a7c 1056 int r;
f078f209 1057
226afe68
JP
1058 ath_dbg(common, ATH_DBG_CONFIG,
1059 "Starting driver with initial channel: %d MHz\n",
1060 curchan->center_freq);
f078f209 1061
f62d816f
FF
1062 ath9k_ps_wakeup(sc);
1063
141b38b6
S
1064 mutex_lock(&sc->mutex);
1065
8feceb67 1066 /* setup initial channel */
82880a7c 1067 sc->chan_idx = curchan->hw_value;
f078f209 1068
c344c9cb 1069 init_channel = ath9k_cmn_get_curchannel(hw, ah);
ff37e337
S
1070
1071 /* Reset SERDES registers */
af03abec 1072 ath9k_hw_configpcipowersave(ah, 0, 0);
ff37e337
S
1073
1074 /*
1075 * The basic interface to setting the hardware in a good
1076 * state is ``reset''. On return the hardware is known to
1077 * be powered up and with interrupts disabled. This must
1078 * be followed by initialization of the appropriate bits
1079 * and then setup of the interrupt mask.
1080 */
4bdd1e97 1081 spin_lock_bh(&sc->sc_pcu_lock);
20bd2a09 1082 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
ae8d2858 1083 if (r) {
3800276a
JP
1084 ath_err(common,
1085 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
1086 r, curchan->center_freq);
4bdd1e97 1087 spin_unlock_bh(&sc->sc_pcu_lock);
141b38b6 1088 goto mutex_unlock;
ff37e337 1089 }
ff37e337
S
1090
1091 /*
1092 * This is needed only to setup initial state
1093 * but it's best done after a reset.
1094 */
5048e8c3
RM
1095 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1096 sc->config.txpowlimit, &sc->curtxpow);
8feceb67 1097
ff37e337
S
1098 /*
1099 * Setup the hardware after reset:
1100 * The receive engine is set going.
1101 * Frame transmit is handled entirely
1102 * in the frame output path; there's nothing to do
1103 * here except setup the interrupt mask.
1104 */
1105 if (ath_startrecv(sc) != 0) {
3800276a 1106 ath_err(common, "Unable to start recv logic\n");
141b38b6 1107 r = -EIO;
4bdd1e97 1108 spin_unlock_bh(&sc->sc_pcu_lock);
141b38b6 1109 goto mutex_unlock;
f078f209 1110 }
4bdd1e97 1111 spin_unlock_bh(&sc->sc_pcu_lock);
8feceb67 1112
ff37e337 1113 /* Setup our intr mask. */
b5c80475
FF
1114 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
1115 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
1116 ATH9K_INT_GLOBAL;
1117
1118 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
08578b8f
LR
1119 ah->imask |= ATH9K_INT_RXHP |
1120 ATH9K_INT_RXLP |
1121 ATH9K_INT_BB_WATCHDOG;
b5c80475
FF
1122 else
1123 ah->imask |= ATH9K_INT_RX;
ff37e337 1124
364734fa 1125 ah->imask |= ATH9K_INT_GTT;
ff37e337 1126
af03abec 1127 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
3069168c 1128 ah->imask |= ATH9K_INT_CST;
ff37e337 1129
ff37e337 1130 sc->sc_flags &= ~SC_OP_INVALID;
5f841b41 1131 sc->sc_ah->is_monitoring = false;
ff37e337
S
1132
1133 /* Disable BMISS interrupt when we're not associated */
3069168c
PR
1134 ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1135 ath9k_hw_set_interrupts(ah, ah->imask);
b037b693 1136 ath9k_hw_enable_interrupts(ah);
ff37e337 1137
bce048d7 1138 ieee80211_wake_queues(hw);
ff37e337 1139
42935eca 1140 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
164ace38 1141
766ec4a9
LR
1142 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
1143 !ah->btcoex_hw.enabled) {
5e197292
LR
1144 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1145 AR_STOMP_LOW_WLAN_WGHT);
af03abec 1146 ath9k_hw_btcoex_enable(ah);
f985ad12 1147
5bb12791
LR
1148 if (common->bus_ops->bt_coex_prep)
1149 common->bus_ops->bt_coex_prep(common);
766ec4a9 1150 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1151 ath9k_btcoex_timer_resume(sc);
1773912b
VT
1152 }
1153
8060e169
VT
1154 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
1155 common->bus_ops->extn_synch_en(common);
1156
141b38b6
S
1157mutex_unlock:
1158 mutex_unlock(&sc->mutex);
1159
f62d816f
FF
1160 ath9k_ps_restore(sc);
1161
ae8d2858 1162 return r;
f078f209
LR
1163}
1164
7bb45683 1165static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
f078f209 1166{
9ac58615 1167 struct ath_softc *sc = hw->priv;
c46917bb 1168 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 1169 struct ath_tx_control txctl;
1bc14880 1170 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
528f0c6b 1171
96148326 1172 if (sc->ps_enabled) {
dc8c4585
JM
1173 /*
1174 * mac80211 does not set PM field for normal data frames, so we
1175 * need to update that based on the current PS mode.
1176 */
1177 if (ieee80211_is_data(hdr->frame_control) &&
1178 !ieee80211_is_nullfunc(hdr->frame_control) &&
1179 !ieee80211_has_pm(hdr->frame_control)) {
226afe68
JP
1180 ath_dbg(common, ATH_DBG_PS,
1181 "Add PM=1 for a TX frame while in PS mode\n");
dc8c4585
JM
1182 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1183 }
1184 }
1185
9a23f9ca
JM
1186 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
1187 /*
1188 * We are using PS-Poll and mac80211 can request TX while in
1189 * power save mode. Need to wake up hardware for the TX to be
1190 * completed and if needed, also for RX of buffered frames.
1191 */
9a23f9ca 1192 ath9k_ps_wakeup(sc);
fdf76622
VT
1193 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
1194 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca 1195 if (ieee80211_is_pspoll(hdr->frame_control)) {
226afe68
JP
1196 ath_dbg(common, ATH_DBG_PS,
1197 "Sending PS-Poll to pick a buffered frame\n");
1b04b930 1198 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
9a23f9ca 1199 } else {
226afe68
JP
1200 ath_dbg(common, ATH_DBG_PS,
1201 "Wake up to complete TX\n");
1b04b930 1202 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
9a23f9ca
JM
1203 }
1204 /*
1205 * The actual restore operation will happen only after
1206 * the sc_flags bit is cleared. We are just dropping
1207 * the ps_usecount here.
1208 */
1209 ath9k_ps_restore(sc);
1210 }
1211
528f0c6b 1212 memset(&txctl, 0, sizeof(struct ath_tx_control));
066dae93 1213 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
528f0c6b 1214
226afe68 1215 ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 1216
c52f33d0 1217 if (ath_tx_start(hw, skb, &txctl) != 0) {
226afe68 1218 ath_dbg(common, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 1219 goto exit;
8feceb67
VT
1220 }
1221
7bb45683 1222 return;
528f0c6b
S
1223exit:
1224 dev_kfree_skb_any(skb);
f078f209
LR
1225}
1226
8feceb67 1227static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 1228{
9ac58615 1229 struct ath_softc *sc = hw->priv;
af03abec 1230 struct ath_hw *ah = sc->sc_ah;
c46917bb 1231 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1232
4c483817
S
1233 mutex_lock(&sc->mutex);
1234
c94dbff7 1235 cancel_delayed_work_sync(&sc->tx_complete_work);
181fb18d 1236 cancel_delayed_work_sync(&sc->hw_pll_work);
9f42c2b6 1237 cancel_work_sync(&sc->paprd_work);
347809fc 1238 cancel_work_sync(&sc->hw_check_work);
c94dbff7 1239
9c84b797 1240 if (sc->sc_flags & SC_OP_INVALID) {
226afe68 1241 ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
4c483817 1242 mutex_unlock(&sc->mutex);
9c84b797
S
1243 return;
1244 }
8feceb67 1245
3867cf6a
S
1246 /* Ensure HW is awake when we try to shut it down. */
1247 ath9k_ps_wakeup(sc);
1248
766ec4a9 1249 if (ah->btcoex_hw.enabled) {
af03abec 1250 ath9k_hw_btcoex_disable(ah);
766ec4a9 1251 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1252 ath9k_btcoex_timer_pause(sc);
1773912b
VT
1253 }
1254
6a6733f2
LR
1255 spin_lock_bh(&sc->sc_pcu_lock);
1256
203043f5
SG
1257 /* prevent tasklets to enable interrupts once we disable them */
1258 ah->imask &= ~ATH9K_INT_GLOBAL;
1259
ff37e337
S
1260 /* make sure h/w will not generate any interrupt
1261 * before setting the invalid flag. */
4df3071e 1262 ath9k_hw_disable_interrupts(ah);
ff37e337
S
1263
1264 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 1265 ath_drain_all_txq(sc, false);
ff37e337 1266 ath_stoprecv(sc);
af03abec 1267 ath9k_hw_phy_disable(ah);
6a6733f2 1268 } else
b77f483f 1269 sc->rx.rxlink = NULL;
ff37e337 1270
0d95521e
FF
1271 if (sc->rx.frag) {
1272 dev_kfree_skb_any(sc->rx.frag);
1273 sc->rx.frag = NULL;
1274 }
1275
ff37e337 1276 /* disable HAL and put h/w to sleep */
af03abec 1277 ath9k_hw_disable(ah);
6a6733f2
LR
1278
1279 spin_unlock_bh(&sc->sc_pcu_lock);
1280
203043f5
SG
1281 /* we can now sync irq and kill any running tasklets, since we already
1282 * disabled interrupts and not holding a spin lock */
1283 synchronize_irq(sc->irq);
1284 tasklet_kill(&sc->intr_tq);
1285 tasklet_kill(&sc->bcon_tasklet);
1286
3867cf6a
S
1287 ath9k_ps_restore(sc);
1288
a08e7ade
LR
1289 sc->ps_idle = true;
1290 ath_radio_disable(sc, hw);
ff37e337
S
1291
1292 sc->sc_flags |= SC_OP_INVALID;
500c064d 1293
141b38b6
S
1294 mutex_unlock(&sc->mutex);
1295
226afe68 1296 ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR
1297}
1298
4801416c
BG
1299bool ath9k_uses_beacons(int type)
1300{
1301 switch (type) {
1302 case NL80211_IFTYPE_AP:
1303 case NL80211_IFTYPE_ADHOC:
1304 case NL80211_IFTYPE_MESH_POINT:
1305 return true;
1306 default:
1307 return false;
1308 }
1309}
1310
1311static void ath9k_reclaim_beacon(struct ath_softc *sc,
1312 struct ieee80211_vif *vif)
f078f209 1313{
1ed32e4f 1314 struct ath_vif *avp = (void *)vif->drv_priv;
8feceb67 1315
014cf3bb 1316 ath9k_set_beaconing_status(sc, false);
4801416c 1317 ath_beacon_return(sc, avp);
014cf3bb 1318 ath9k_set_beaconing_status(sc, true);
4801416c 1319 sc->sc_flags &= ~SC_OP_BEACONS;
4801416c
BG
1320}
1321
1322static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1323{
1324 struct ath9k_vif_iter_data *iter_data = data;
1325 int i;
1326
1327 if (iter_data->hw_macaddr)
1328 for (i = 0; i < ETH_ALEN; i++)
1329 iter_data->mask[i] &=
1330 ~(iter_data->hw_macaddr[i] ^ mac[i]);
141b38b6 1331
1ed32e4f 1332 switch (vif->type) {
4801416c
BG
1333 case NL80211_IFTYPE_AP:
1334 iter_data->naps++;
f078f209 1335 break;
4801416c
BG
1336 case NL80211_IFTYPE_STATION:
1337 iter_data->nstations++;
e51f3eff 1338 break;
05c914fe 1339 case NL80211_IFTYPE_ADHOC:
4801416c
BG
1340 iter_data->nadhocs++;
1341 break;
9cb5412b 1342 case NL80211_IFTYPE_MESH_POINT:
4801416c
BG
1343 iter_data->nmeshes++;
1344 break;
1345 case NL80211_IFTYPE_WDS:
1346 iter_data->nwds++;
f078f209
LR
1347 break;
1348 default:
4801416c
BG
1349 iter_data->nothers++;
1350 break;
f078f209 1351 }
4801416c 1352}
f078f209 1353
4801416c
BG
1354/* Called with sc->mutex held. */
1355void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
1356 struct ieee80211_vif *vif,
1357 struct ath9k_vif_iter_data *iter_data)
1358{
9ac58615 1359 struct ath_softc *sc = hw->priv;
4801416c
BG
1360 struct ath_hw *ah = sc->sc_ah;
1361 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 1362
4801416c
BG
1363 /*
1364 * Use the hardware MAC address as reference, the hardware uses it
1365 * together with the BSSID mask when matching addresses.
1366 */
1367 memset(iter_data, 0, sizeof(*iter_data));
1368 iter_data->hw_macaddr = common->macaddr;
1369 memset(&iter_data->mask, 0xff, ETH_ALEN);
5640b08e 1370
4801416c
BG
1371 if (vif)
1372 ath9k_vif_iter(iter_data, vif->addr, vif);
1373
1374 /* Get list of all active MAC addresses */
4801416c
BG
1375 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
1376 iter_data);
4801416c 1377}
8ca21f01 1378
4801416c
BG
1379/* Called with sc->mutex held. */
1380static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
1381 struct ieee80211_vif *vif)
1382{
9ac58615 1383 struct ath_softc *sc = hw->priv;
4801416c
BG
1384 struct ath_hw *ah = sc->sc_ah;
1385 struct ath_common *common = ath9k_hw_common(ah);
1386 struct ath9k_vif_iter_data iter_data;
8ca21f01 1387
4801416c 1388 ath9k_calculate_iter_data(hw, vif, &iter_data);
2c3db3d5 1389
4801416c
BG
1390 /* Set BSSID mask. */
1391 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1392 ath_hw_setbssidmask(common);
1393
1394 /* Set op-mode & TSF */
1395 if (iter_data.naps > 0) {
3069168c 1396 ath9k_hw_set_tsfadjust(ah, 1);
b238e90e 1397 sc->sc_flags |= SC_OP_TSF_RESET;
4801416c
BG
1398 ah->opmode = NL80211_IFTYPE_AP;
1399 } else {
1400 ath9k_hw_set_tsfadjust(ah, 0);
1401 sc->sc_flags &= ~SC_OP_TSF_RESET;
5640b08e 1402
fd5999cf
JC
1403 if (iter_data.nmeshes)
1404 ah->opmode = NL80211_IFTYPE_MESH_POINT;
1405 else if (iter_data.nwds)
4801416c
BG
1406 ah->opmode = NL80211_IFTYPE_AP;
1407 else if (iter_data.nadhocs)
1408 ah->opmode = NL80211_IFTYPE_ADHOC;
1409 else
1410 ah->opmode = NL80211_IFTYPE_STATION;
1411 }
5640b08e 1412
4e30ffa2
VN
1413 /*
1414 * Enable MIB interrupts when there are hardware phy counters.
4e30ffa2 1415 */
4801416c 1416 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
3448f912
LR
1417 if (ah->config.enable_ani)
1418 ah->imask |= ATH9K_INT_MIB;
3069168c 1419 ah->imask |= ATH9K_INT_TSFOOR;
4801416c
BG
1420 } else {
1421 ah->imask &= ~ATH9K_INT_MIB;
1422 ah->imask &= ~ATH9K_INT_TSFOOR;
4af9cf4f
S
1423 }
1424
3069168c 1425 ath9k_hw_set_interrupts(ah, ah->imask);
4e30ffa2 1426
4801416c 1427 /* Set up ANI */
2e5ef459 1428 if (iter_data.naps > 0) {
729da390 1429 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
05c0be2f
MSS
1430
1431 if (!common->disable_ani) {
1432 sc->sc_flags |= SC_OP_ANI_RUN;
1433 ath_start_ani(common);
1434 }
1435
f60c49b6
RM
1436 } else {
1437 sc->sc_flags &= ~SC_OP_ANI_RUN;
1438 del_timer_sync(&common->ani.timer);
6c3118e2 1439 }
4801416c 1440}
6f255425 1441
4801416c
BG
1442/* Called with sc->mutex held, vif counts set up properly. */
1443static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
1444 struct ieee80211_vif *vif)
1445{
9ac58615 1446 struct ath_softc *sc = hw->priv;
4801416c
BG
1447
1448 ath9k_calculate_summary_state(hw, vif);
1449
1450 if (ath9k_uses_beacons(vif->type)) {
1451 int error;
4801416c
BG
1452 /* This may fail because upper levels do not have beacons
1453 * properly configured yet. That's OK, we assume it
1454 * will be properly configured and then we will be notified
1455 * in the info_changed method and set up beacons properly
1456 * there.
1457 */
014cf3bb 1458 ath9k_set_beaconing_status(sc, false);
9ac58615 1459 error = ath_beacon_alloc(sc, vif);
391bd1c4 1460 if (!error)
4801416c 1461 ath_beacon_config(sc, vif);
014cf3bb 1462 ath9k_set_beaconing_status(sc, true);
4801416c 1463 }
f078f209
LR
1464}
1465
4801416c
BG
1466
1467static int ath9k_add_interface(struct ieee80211_hw *hw,
1468 struct ieee80211_vif *vif)
6b3b991d 1469{
9ac58615 1470 struct ath_softc *sc = hw->priv;
4801416c
BG
1471 struct ath_hw *ah = sc->sc_ah;
1472 struct ath_common *common = ath9k_hw_common(ah);
4801416c 1473 int ret = 0;
6b3b991d 1474
96f372c9 1475 ath9k_ps_wakeup(sc);
4801416c 1476 mutex_lock(&sc->mutex);
6b3b991d 1477
4801416c
BG
1478 switch (vif->type) {
1479 case NL80211_IFTYPE_STATION:
1480 case NL80211_IFTYPE_WDS:
1481 case NL80211_IFTYPE_ADHOC:
1482 case NL80211_IFTYPE_AP:
1483 case NL80211_IFTYPE_MESH_POINT:
1484 break;
1485 default:
1486 ath_err(common, "Interface type %d not yet supported\n",
1487 vif->type);
1488 ret = -EOPNOTSUPP;
1489 goto out;
1490 }
6b3b991d 1491
4801416c
BG
1492 if (ath9k_uses_beacons(vif->type)) {
1493 if (sc->nbcnvifs >= ATH_BCBUF) {
1494 ath_err(common, "Not enough beacon buffers when adding"
1495 " new interface of type: %i\n",
1496 vif->type);
1497 ret = -ENOBUFS;
1498 goto out;
1499 }
1500 }
1501
59575d1c
RM
1502 if ((ah->opmode == NL80211_IFTYPE_ADHOC) ||
1503 ((vif->type == NL80211_IFTYPE_ADHOC) &&
1504 sc->nvifs > 0)) {
4801416c
BG
1505 ath_err(common, "Cannot create ADHOC interface when other"
1506 " interfaces already exist.\n");
1507 ret = -EINVAL;
1508 goto out;
6b3b991d 1509 }
4801416c
BG
1510
1511 ath_dbg(common, ATH_DBG_CONFIG,
1512 "Attach a VIF of type: %d\n", vif->type);
1513
4801416c
BG
1514 sc->nvifs++;
1515
1516 ath9k_do_vif_add_setup(hw, vif);
1517out:
1518 mutex_unlock(&sc->mutex);
96f372c9 1519 ath9k_ps_restore(sc);
4801416c 1520 return ret;
6b3b991d
RM
1521}
1522
1523static int ath9k_change_interface(struct ieee80211_hw *hw,
1524 struct ieee80211_vif *vif,
1525 enum nl80211_iftype new_type,
1526 bool p2p)
1527{
9ac58615 1528 struct ath_softc *sc = hw->priv;
6b3b991d 1529 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
6dab55bf 1530 int ret = 0;
6b3b991d
RM
1531
1532 ath_dbg(common, ATH_DBG_CONFIG, "Change Interface\n");
1533 mutex_lock(&sc->mutex);
96f372c9 1534 ath9k_ps_wakeup(sc);
6b3b991d 1535
4801416c
BG
1536 /* See if new interface type is valid. */
1537 if ((new_type == NL80211_IFTYPE_ADHOC) &&
1538 (sc->nvifs > 1)) {
1539 ath_err(common, "When using ADHOC, it must be the only"
1540 " interface.\n");
1541 ret = -EINVAL;
1542 goto out;
1543 }
1544
1545 if (ath9k_uses_beacons(new_type) &&
1546 !ath9k_uses_beacons(vif->type)) {
6b3b991d
RM
1547 if (sc->nbcnvifs >= ATH_BCBUF) {
1548 ath_err(common, "No beacon slot available\n");
6dab55bf
DC
1549 ret = -ENOBUFS;
1550 goto out;
6b3b991d 1551 }
6b3b991d 1552 }
4801416c
BG
1553
1554 /* Clean up old vif stuff */
1555 if (ath9k_uses_beacons(vif->type))
1556 ath9k_reclaim_beacon(sc, vif);
1557
1558 /* Add new settings */
6b3b991d
RM
1559 vif->type = new_type;
1560 vif->p2p = p2p;
1561
4801416c 1562 ath9k_do_vif_add_setup(hw, vif);
6dab55bf 1563out:
96f372c9 1564 ath9k_ps_restore(sc);
6b3b991d 1565 mutex_unlock(&sc->mutex);
6dab55bf 1566 return ret;
6b3b991d
RM
1567}
1568
8feceb67 1569static void ath9k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1570 struct ieee80211_vif *vif)
f078f209 1571{
9ac58615 1572 struct ath_softc *sc = hw->priv;
c46917bb 1573 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
f078f209 1574
226afe68 1575 ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 1576
96f372c9 1577 ath9k_ps_wakeup(sc);
141b38b6
S
1578 mutex_lock(&sc->mutex);
1579
4801416c 1580 sc->nvifs--;
580f0b8a 1581
8feceb67 1582 /* Reclaim beacon resources */
4801416c 1583 if (ath9k_uses_beacons(vif->type))
6b3b991d 1584 ath9k_reclaim_beacon(sc, vif);
2c3db3d5 1585
4801416c 1586 ath9k_calculate_summary_state(hw, NULL);
141b38b6
S
1587
1588 mutex_unlock(&sc->mutex);
96f372c9 1589 ath9k_ps_restore(sc);
f078f209
LR
1590}
1591
fbab7390 1592static void ath9k_enable_ps(struct ath_softc *sc)
3f7c5c10 1593{
3069168c
PR
1594 struct ath_hw *ah = sc->sc_ah;
1595
3f7c5c10 1596 sc->ps_enabled = true;
3069168c
PR
1597 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1598 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1599 ah->imask |= ATH9K_INT_TIM_TIMER;
1600 ath9k_hw_set_interrupts(ah, ah->imask);
3f7c5c10 1601 }
fdf76622 1602 ath9k_hw_setrxabort(ah, 1);
3f7c5c10 1603 }
3f7c5c10
SB
1604}
1605
845d708e
SB
1606static void ath9k_disable_ps(struct ath_softc *sc)
1607{
1608 struct ath_hw *ah = sc->sc_ah;
1609
1610 sc->ps_enabled = false;
1611 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1612 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1613 ath9k_hw_setrxabort(ah, 0);
1614 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1615 PS_WAIT_FOR_CAB |
1616 PS_WAIT_FOR_PSPOLL_DATA |
1617 PS_WAIT_FOR_TX_ACK);
1618 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1619 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1620 ath9k_hw_set_interrupts(ah, ah->imask);
1621 }
1622 }
1623
1624}
1625
e8975581 1626static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1627{
9ac58615 1628 struct ath_softc *sc = hw->priv;
3430098a
FF
1629 struct ath_hw *ah = sc->sc_ah;
1630 struct ath_common *common = ath9k_hw_common(ah);
e8975581 1631 struct ieee80211_conf *conf = &hw->conf;
7545daf4 1632 bool disable_radio = false;
f078f209 1633
aa33de09 1634 mutex_lock(&sc->mutex);
141b38b6 1635
194b7c13
LR
1636 /*
1637 * Leave this as the first check because we need to turn on the
1638 * radio if it was disabled before prior to processing the rest
1639 * of the changes. Likewise we must only disable the radio towards
1640 * the end.
1641 */
64839170 1642 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
7545daf4
FF
1643 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1644 if (!sc->ps_idle) {
68a89116 1645 ath_radio_enable(sc, hw);
226afe68
JP
1646 ath_dbg(common, ATH_DBG_CONFIG,
1647 "not-idle: enabling radio\n");
7545daf4
FF
1648 } else {
1649 disable_radio = true;
64839170
LR
1650 }
1651 }
1652
e7824a50
LR
1653 /*
1654 * We just prepare to enable PS. We have to wait until our AP has
1655 * ACK'd our null data frame to disable RX otherwise we'll ignore
1656 * those ACKs and end up retransmitting the same null data frames.
1657 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1658 */
3cbb5dd7 1659 if (changed & IEEE80211_CONF_CHANGE_PS) {
8ab2cd09
LR
1660 unsigned long flags;
1661 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fbab7390
SB
1662 if (conf->flags & IEEE80211_CONF_PS)
1663 ath9k_enable_ps(sc);
845d708e
SB
1664 else
1665 ath9k_disable_ps(sc);
8ab2cd09 1666 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3cbb5dd7
VN
1667 }
1668
199afd9d
S
1669 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1670 if (conf->flags & IEEE80211_CONF_MONITOR) {
226afe68
JP
1671 ath_dbg(common, ATH_DBG_CONFIG,
1672 "Monitor mode is enabled\n");
5f841b41
RM
1673 sc->sc_ah->is_monitoring = true;
1674 } else {
226afe68
JP
1675 ath_dbg(common, ATH_DBG_CONFIG,
1676 "Monitor mode is disabled\n");
5f841b41 1677 sc->sc_ah->is_monitoring = false;
199afd9d
S
1678 }
1679 }
1680
4797938c 1681 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 1682 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 1683 int pos = curchan->hw_value;
3430098a
FF
1684 int old_pos = -1;
1685 unsigned long flags;
1686
1687 if (ah->curchan)
1688 old_pos = ah->curchan - &ah->channels[0];
ae5eb026 1689
5ee08656
FF
1690 if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
1691 sc->sc_flags |= SC_OP_OFFCHANNEL;
1692 else
1693 sc->sc_flags &= ~SC_OP_OFFCHANNEL;
0e2dedf9 1694
8c79a610
BG
1695 ath_dbg(common, ATH_DBG_CONFIG,
1696 "Set channel: %d MHz type: %d\n",
1697 curchan->center_freq, conf->channel_type);
f078f209 1698
de87f736
RM
1699 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
1700 curchan, conf->channel_type);
e11602b7 1701
3430098a
FF
1702 /* update survey stats for the old channel before switching */
1703 spin_lock_irqsave(&common->cc_lock, flags);
1704 ath_update_survey_stats(sc);
1705 spin_unlock_irqrestore(&common->cc_lock, flags);
1706
1707 /*
1708 * If the operating channel changes, change the survey in-use flags
1709 * along with it.
1710 * Reset the survey data for the new channel, unless we're switching
1711 * back to the operating channel from an off-channel operation.
1712 */
1713 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1714 sc->cur_survey != &sc->survey[pos]) {
1715
1716 if (sc->cur_survey)
1717 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1718
1719 sc->cur_survey = &sc->survey[pos];
1720
1721 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1722 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1723 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1724 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1725 }
1726
0e2dedf9 1727 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
3800276a 1728 ath_err(common, "Unable to set channel\n");
aa33de09 1729 mutex_unlock(&sc->mutex);
e11602b7
S
1730 return -EINVAL;
1731 }
3430098a
FF
1732
1733 /*
1734 * The most recent snapshot of channel->noisefloor for the old
1735 * channel is only available after the hardware reset. Copy it to
1736 * the survey stats now.
1737 */
1738 if (old_pos >= 0)
1739 ath_update_survey_nf(sc, old_pos);
094d05dc 1740 }
f078f209 1741
c9f6a656 1742 if (changed & IEEE80211_CONF_CHANGE_POWER) {
603b3eef
BG
1743 ath_dbg(common, ATH_DBG_CONFIG,
1744 "Set power: %d\n", conf->power_level);
17d7904d 1745 sc->config.txpowlimit = 2 * conf->power_level;
783cd01e 1746 ath9k_ps_wakeup(sc);
5048e8c3
RM
1747 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1748 sc->config.txpowlimit, &sc->curtxpow);
783cd01e 1749 ath9k_ps_restore(sc);
c9f6a656 1750 }
f078f209 1751
64839170 1752 if (disable_radio) {
226afe68 1753 ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
68a89116 1754 ath_radio_disable(sc, hw);
64839170
LR
1755 }
1756
aa33de09 1757 mutex_unlock(&sc->mutex);
141b38b6 1758
f078f209
LR
1759 return 0;
1760}
1761
8feceb67
VT
1762#define SUPPORTED_FILTERS \
1763 (FIF_PROMISC_IN_BSS | \
1764 FIF_ALLMULTI | \
1765 FIF_CONTROL | \
af6a3fc7 1766 FIF_PSPOLL | \
8feceb67
VT
1767 FIF_OTHER_BSS | \
1768 FIF_BCN_PRBRESP_PROMISC | \
9c1d8e4a 1769 FIF_PROBE_REQ | \
8feceb67 1770 FIF_FCSFAIL)
c83be688 1771
8feceb67
VT
1772/* FIXME: sc->sc_full_reset ? */
1773static void ath9k_configure_filter(struct ieee80211_hw *hw,
1774 unsigned int changed_flags,
1775 unsigned int *total_flags,
3ac64bee 1776 u64 multicast)
8feceb67 1777{
9ac58615 1778 struct ath_softc *sc = hw->priv;
8feceb67 1779 u32 rfilt;
f078f209 1780
8feceb67
VT
1781 changed_flags &= SUPPORTED_FILTERS;
1782 *total_flags &= SUPPORTED_FILTERS;
f078f209 1783
b77f483f 1784 sc->rx.rxfilter = *total_flags;
aa68aeaa 1785 ath9k_ps_wakeup(sc);
8feceb67
VT
1786 rfilt = ath_calcrxfilter(sc);
1787 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 1788 ath9k_ps_restore(sc);
f078f209 1789
226afe68
JP
1790 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
1791 "Set HW RX filter: 0x%x\n", rfilt);
8feceb67 1792}
f078f209 1793
4ca77860
JB
1794static int ath9k_sta_add(struct ieee80211_hw *hw,
1795 struct ieee80211_vif *vif,
1796 struct ieee80211_sta *sta)
8feceb67 1797{
9ac58615 1798 struct ath_softc *sc = hw->priv;
93ae2dd2
FF
1799 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1800 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1801 struct ieee80211_key_conf ps_key = { };
f078f209 1802
4ca77860 1803 ath_node_attach(sc, sta);
f59a59fe
FF
1804
1805 if (vif->type != NL80211_IFTYPE_AP &&
1806 vif->type != NL80211_IFTYPE_AP_VLAN)
1807 return 0;
1808
93ae2dd2 1809 an->ps_key = ath_key_config(common, vif, sta, &ps_key);
4ca77860
JB
1810
1811 return 0;
1812}
1813
93ae2dd2
FF
1814static void ath9k_del_ps_key(struct ath_softc *sc,
1815 struct ieee80211_vif *vif,
1816 struct ieee80211_sta *sta)
1817{
1818 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1819 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1820 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1821
1822 if (!an->ps_key)
1823 return;
1824
1825 ath_key_delete(common, &ps_key);
1826}
1827
4ca77860
JB
1828static int ath9k_sta_remove(struct ieee80211_hw *hw,
1829 struct ieee80211_vif *vif,
1830 struct ieee80211_sta *sta)
1831{
9ac58615 1832 struct ath_softc *sc = hw->priv;
4ca77860 1833
93ae2dd2 1834 ath9k_del_ps_key(sc, vif, sta);
4ca77860
JB
1835 ath_node_detach(sc, sta);
1836
1837 return 0;
f078f209
LR
1838}
1839
5519541d
FF
1840static void ath9k_sta_notify(struct ieee80211_hw *hw,
1841 struct ieee80211_vif *vif,
1842 enum sta_notify_cmd cmd,
1843 struct ieee80211_sta *sta)
1844{
1845 struct ath_softc *sc = hw->priv;
1846 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1847
1848 switch (cmd) {
1849 case STA_NOTIFY_SLEEP:
1850 an->sleeping = true;
1851 if (ath_tx_aggr_sleep(sc, an))
1852 ieee80211_sta_set_tim(sta);
1853 break;
1854 case STA_NOTIFY_AWAKE:
1855 an->sleeping = false;
1856 ath_tx_aggr_wakeup(sc, an);
1857 break;
1858 }
1859}
1860
141b38b6 1861static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 1862 const struct ieee80211_tx_queue_params *params)
f078f209 1863{
9ac58615 1864 struct ath_softc *sc = hw->priv;
c46917bb 1865 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
066dae93 1866 struct ath_txq *txq;
8feceb67 1867 struct ath9k_tx_queue_info qi;
066dae93 1868 int ret = 0;
f078f209 1869
8feceb67
VT
1870 if (queue >= WME_NUM_AC)
1871 return 0;
f078f209 1872
066dae93
FF
1873 txq = sc->tx.txq_map[queue];
1874
96f372c9 1875 ath9k_ps_wakeup(sc);
141b38b6
S
1876 mutex_lock(&sc->mutex);
1877
1ffb0610
S
1878 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1879
8feceb67
VT
1880 qi.tqi_aifs = params->aifs;
1881 qi.tqi_cwmin = params->cw_min;
1882 qi.tqi_cwmax = params->cw_max;
1883 qi.tqi_burstTime = params->txop;
f078f209 1884
226afe68
JP
1885 ath_dbg(common, ATH_DBG_CONFIG,
1886 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1887 queue, txq->axq_qnum, params->aifs, params->cw_min,
1888 params->cw_max, params->txop);
f078f209 1889
066dae93 1890 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
8feceb67 1891 if (ret)
3800276a 1892 ath_err(common, "TXQ Update failed\n");
f078f209 1893
94db2936 1894 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
066dae93 1895 if (queue == WME_AC_BE && !ret)
94db2936
VN
1896 ath_beaconq_config(sc);
1897
141b38b6 1898 mutex_unlock(&sc->mutex);
96f372c9 1899 ath9k_ps_restore(sc);
141b38b6 1900
8feceb67
VT
1901 return ret;
1902}
f078f209 1903
8feceb67
VT
1904static int ath9k_set_key(struct ieee80211_hw *hw,
1905 enum set_key_cmd cmd,
dc822b5d
JB
1906 struct ieee80211_vif *vif,
1907 struct ieee80211_sta *sta,
8feceb67
VT
1908 struct ieee80211_key_conf *key)
1909{
9ac58615 1910 struct ath_softc *sc = hw->priv;
c46917bb 1911 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67 1912 int ret = 0;
f078f209 1913
3e6109c5 1914 if (ath9k_modparam_nohwcrypt)
b3bd89ce
JM
1915 return -ENOSPC;
1916
cfdc9a8b
JM
1917 if (vif->type == NL80211_IFTYPE_ADHOC &&
1918 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1919 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1920 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1921 /*
1922 * For now, disable hw crypto for the RSN IBSS group keys. This
1923 * could be optimized in the future to use a modified key cache
1924 * design to support per-STA RX GTK, but until that gets
1925 * implemented, use of software crypto for group addressed
1926 * frames is a acceptable to allow RSN IBSS to be used.
1927 */
1928 return -EOPNOTSUPP;
1929 }
1930
141b38b6 1931 mutex_lock(&sc->mutex);
3cbb5dd7 1932 ath9k_ps_wakeup(sc);
226afe68 1933 ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 1934
8feceb67
VT
1935 switch (cmd) {
1936 case SET_KEY:
93ae2dd2
FF
1937 if (sta)
1938 ath9k_del_ps_key(sc, vif, sta);
1939
040e539e 1940 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM
1941 if (ret >= 0) {
1942 key->hw_key_idx = ret;
8feceb67
VT
1943 /* push IV and Michael MIC generation to stack */
1944 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
97359d12 1945 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
8feceb67 1946 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
97359d12
JB
1947 if (sc->sc_ah->sw_mgmt_crypto &&
1948 key->cipher == WLAN_CIPHER_SUITE_CCMP)
0ced0e17 1949 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 1950 ret = 0;
8feceb67
VT
1951 }
1952 break;
1953 case DISABLE_KEY:
040e539e 1954 ath_key_delete(common, key);
8feceb67
VT
1955 break;
1956 default:
1957 ret = -EINVAL;
1958 }
f078f209 1959
3cbb5dd7 1960 ath9k_ps_restore(sc);
141b38b6
S
1961 mutex_unlock(&sc->mutex);
1962
8feceb67
VT
1963 return ret;
1964}
4f5ef75b
RM
1965static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1966{
1967 struct ath_softc *sc = data;
1968 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1969 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1970 struct ath_vif *avp = (void *)vif->drv_priv;
1971
2e5ef459
RM
1972 /*
1973 * Skip iteration if primary station vif's bss info
1974 * was not changed
1975 */
1976 if (sc->sc_flags & SC_OP_PRIM_STA_VIF)
1977 return;
1978
1979 if (bss_conf->assoc) {
1980 sc->sc_flags |= SC_OP_PRIM_STA_VIF;
1981 avp->primary_sta_vif = true;
4f5ef75b
RM
1982 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1983 common->curaid = bss_conf->aid;
1984 ath9k_hw_write_associd(sc->sc_ah);
2e5ef459 1985 ath_dbg(common, ATH_DBG_CONFIG,
99e4d43a
RM
1986 "Bss Info ASSOC %d, bssid: %pM\n",
1987 bss_conf->aid, common->curbssid);
2e5ef459
RM
1988 ath_beacon_config(sc, vif);
1989 /*
1990 * Request a re-configuration of Beacon related timers
1991 * on the receipt of the first Beacon frame (i.e.,
1992 * after time sync with the AP).
1993 */
1994 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1995 /* Reset rssi stats */
1996 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
1997 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
99e4d43a 1998
05c0be2f
MSS
1999 if (!common->disable_ani) {
2000 sc->sc_flags |= SC_OP_ANI_RUN;
2001 ath_start_ani(common);
2002 }
2003
4f5ef75b
RM
2004 }
2005}
2006
2007static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
2008{
2009 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2010 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
2011 struct ath_vif *avp = (void *)vif->drv_priv;
2012
2e5ef459
RM
2013 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
2014 return;
2015
4f5ef75b
RM
2016 /* Reconfigure bss info */
2017 if (avp->primary_sta_vif && !bss_conf->assoc) {
99e4d43a
RM
2018 ath_dbg(common, ATH_DBG_CONFIG,
2019 "Bss Info DISASSOC %d, bssid %pM\n",
2020 common->curaid, common->curbssid);
2021 sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS);
4f5ef75b
RM
2022 avp->primary_sta_vif = false;
2023 memset(common->curbssid, 0, ETH_ALEN);
2024 common->curaid = 0;
2025 }
2026
2027 ieee80211_iterate_active_interfaces_atomic(
2028 sc->hw, ath9k_bss_iter, sc);
2029
2030 /*
2031 * None of station vifs are associated.
2032 * Clear bssid & aid
2033 */
2e5ef459 2034 if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF)) {
4f5ef75b 2035 ath9k_hw_write_associd(sc->sc_ah);
99e4d43a
RM
2036 /* Stop ANI */
2037 sc->sc_flags &= ~SC_OP_ANI_RUN;
2038 del_timer_sync(&common->ani.timer);
2039 }
4f5ef75b 2040}
f078f209 2041
8feceb67
VT
2042static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2043 struct ieee80211_vif *vif,
2044 struct ieee80211_bss_conf *bss_conf,
2045 u32 changed)
2046{
9ac58615 2047 struct ath_softc *sc = hw->priv;
2d0ddec5 2048 struct ath_hw *ah = sc->sc_ah;
1510718d 2049 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 2050 struct ath_vif *avp = (void *)vif->drv_priv;
0005baf4 2051 int slottime;
c6089ccc 2052 int error;
f078f209 2053
96f372c9 2054 ath9k_ps_wakeup(sc);
141b38b6
S
2055 mutex_lock(&sc->mutex);
2056
c6089ccc 2057 if (changed & BSS_CHANGED_BSSID) {
4f5ef75b 2058 ath9k_config_bss(sc, vif);
2d0ddec5 2059
226afe68
JP
2060 ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n",
2061 common->curbssid, common->curaid);
c6089ccc 2062 }
2d0ddec5 2063
2e5ef459
RM
2064 if (changed & BSS_CHANGED_IBSS) {
2065 /* There can be only one vif available */
2066 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2067 common->curaid = bss_conf->aid;
2068 ath9k_hw_write_associd(sc->sc_ah);
2069
2070 if (bss_conf->ibss_joined) {
2071 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
05c0be2f
MSS
2072
2073 if (!common->disable_ani) {
2074 sc->sc_flags |= SC_OP_ANI_RUN;
2075 ath_start_ani(common);
2076 }
2077
2e5ef459
RM
2078 } else {
2079 sc->sc_flags &= ~SC_OP_ANI_RUN;
2080 del_timer_sync(&common->ani.timer);
2081 }
2082 }
2083
c6089ccc
S
2084 /* Enable transmission of beacons (AP, IBSS, MESH) */
2085 if ((changed & BSS_CHANGED_BEACON) ||
2086 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
014cf3bb 2087 ath9k_set_beaconing_status(sc, false);
9ac58615 2088 error = ath_beacon_alloc(sc, vif);
c6089ccc
S
2089 if (!error)
2090 ath_beacon_config(sc, vif);
014cf3bb 2091 ath9k_set_beaconing_status(sc, true);
0005baf4
FF
2092 }
2093
2094 if (changed & BSS_CHANGED_ERP_SLOT) {
2095 if (bss_conf->use_short_slot)
2096 slottime = 9;
2097 else
2098 slottime = 20;
2099 if (vif->type == NL80211_IFTYPE_AP) {
2100 /*
2101 * Defer update, so that connected stations can adjust
2102 * their settings at the same time.
2103 * See beacon.c for more details
2104 */
2105 sc->beacon.slottime = slottime;
2106 sc->beacon.updateslot = UPDATE;
2107 } else {
2108 ah->slottime = slottime;
2109 ath9k_hw_init_global_settings(ah);
2110 }
2d0ddec5
JB
2111 }
2112
c6089ccc 2113 /* Disable transmission of beacons */
014cf3bb
RM
2114 if ((changed & BSS_CHANGED_BEACON_ENABLED) &&
2115 !bss_conf->enable_beacon) {
2116 ath9k_set_beaconing_status(sc, false);
2117 avp->is_bslot_active = false;
2118 ath9k_set_beaconing_status(sc, true);
2119 }
2d0ddec5 2120
c6089ccc 2121 if (changed & BSS_CHANGED_BEACON_INT) {
c6089ccc
S
2122 /*
2123 * In case of AP mode, the HW TSF has to be reset
2124 * when the beacon interval changes.
2125 */
2126 if (vif->type == NL80211_IFTYPE_AP) {
2127 sc->sc_flags |= SC_OP_TSF_RESET;
014cf3bb 2128 ath9k_set_beaconing_status(sc, false);
9ac58615 2129 error = ath_beacon_alloc(sc, vif);
2d0ddec5
JB
2130 if (!error)
2131 ath_beacon_config(sc, vif);
014cf3bb 2132 ath9k_set_beaconing_status(sc, true);
99e4d43a 2133 } else
c6089ccc 2134 ath_beacon_config(sc, vif);
2d0ddec5
JB
2135 }
2136
8feceb67 2137 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
226afe68
JP
2138 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2139 bss_conf->use_short_preamble);
8feceb67
VT
2140 if (bss_conf->use_short_preamble)
2141 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2142 else
2143 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2144 }
f078f209 2145
8feceb67 2146 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
226afe68
JP
2147 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2148 bss_conf->use_cts_prot);
8feceb67
VT
2149 if (bss_conf->use_cts_prot &&
2150 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2151 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2152 else
2153 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2154 }
f078f209 2155
141b38b6 2156 mutex_unlock(&sc->mutex);
96f372c9 2157 ath9k_ps_restore(sc);
8feceb67 2158}
f078f209 2159
8feceb67
VT
2160static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2161{
9ac58615 2162 struct ath_softc *sc = hw->priv;
8feceb67 2163 u64 tsf;
f078f209 2164
141b38b6 2165 mutex_lock(&sc->mutex);
9abbfb27 2166 ath9k_ps_wakeup(sc);
141b38b6 2167 tsf = ath9k_hw_gettsf64(sc->sc_ah);
9abbfb27 2168 ath9k_ps_restore(sc);
141b38b6 2169 mutex_unlock(&sc->mutex);
f078f209 2170
8feceb67
VT
2171 return tsf;
2172}
f078f209 2173
3b5d665b
AF
2174static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2175{
9ac58615 2176 struct ath_softc *sc = hw->priv;
3b5d665b 2177
141b38b6 2178 mutex_lock(&sc->mutex);
9abbfb27 2179 ath9k_ps_wakeup(sc);
141b38b6 2180 ath9k_hw_settsf64(sc->sc_ah, tsf);
9abbfb27 2181 ath9k_ps_restore(sc);
141b38b6 2182 mutex_unlock(&sc->mutex);
3b5d665b
AF
2183}
2184
8feceb67
VT
2185static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2186{
9ac58615 2187 struct ath_softc *sc = hw->priv;
c83be688 2188
141b38b6 2189 mutex_lock(&sc->mutex);
21526d57
LR
2190
2191 ath9k_ps_wakeup(sc);
141b38b6 2192 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR
2193 ath9k_ps_restore(sc);
2194
141b38b6 2195 mutex_unlock(&sc->mutex);
8feceb67 2196}
f078f209 2197
8feceb67 2198static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 2199 struct ieee80211_vif *vif,
141b38b6
S
2200 enum ieee80211_ampdu_mlme_action action,
2201 struct ieee80211_sta *sta,
0b01f030 2202 u16 tid, u16 *ssn, u8 buf_size)
8feceb67 2203{
9ac58615 2204 struct ath_softc *sc = hw->priv;
8feceb67 2205 int ret = 0;
f078f209 2206
85ad181e
JB
2207 local_bh_disable();
2208
8feceb67
VT
2209 switch (action) {
2210 case IEEE80211_AMPDU_RX_START:
dca3edb8
S
2211 if (!(sc->sc_flags & SC_OP_RXAGGR))
2212 ret = -ENOTSUPP;
8feceb67
VT
2213 break;
2214 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT
2215 break;
2216 case IEEE80211_AMPDU_TX_START:
71a3bf3e
FF
2217 if (!(sc->sc_flags & SC_OP_TXAGGR))
2218 return -EOPNOTSUPP;
2219
8b685ba9 2220 ath9k_ps_wakeup(sc);
231c3a1f
FF
2221 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2222 if (!ret)
2223 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2224 ath9k_ps_restore(sc);
8feceb67
VT
2225 break;
2226 case IEEE80211_AMPDU_TX_STOP:
8b685ba9 2227 ath9k_ps_wakeup(sc);
f83da965 2228 ath_tx_aggr_stop(sc, sta, tid);
c951ad35 2229 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2230 ath9k_ps_restore(sc);
8feceb67 2231 break;
b1720231 2232 case IEEE80211_AMPDU_TX_OPERATIONAL:
8b685ba9 2233 ath9k_ps_wakeup(sc);
8469cdef 2234 ath_tx_aggr_resume(sc, sta, tid);
8b685ba9 2235 ath9k_ps_restore(sc);
8469cdef 2236 break;
8feceb67 2237 default:
3800276a 2238 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
8feceb67
VT
2239 }
2240
85ad181e
JB
2241 local_bh_enable();
2242
8feceb67 2243 return ret;
f078f209
LR
2244}
2245
62dad5b0
BP
2246static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2247 struct survey_info *survey)
2248{
9ac58615 2249 struct ath_softc *sc = hw->priv;
3430098a 2250 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39162dbe 2251 struct ieee80211_supported_band *sband;
3430098a
FF
2252 struct ieee80211_channel *chan;
2253 unsigned long flags;
2254 int pos;
2255
2256 spin_lock_irqsave(&common->cc_lock, flags);
2257 if (idx == 0)
2258 ath_update_survey_stats(sc);
39162dbe
FF
2259
2260 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2261 if (sband && idx >= sband->n_channels) {
2262 idx -= sband->n_channels;
2263 sband = NULL;
2264 }
62dad5b0 2265
39162dbe
FF
2266 if (!sband)
2267 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
62dad5b0 2268
3430098a
FF
2269 if (!sband || idx >= sband->n_channels) {
2270 spin_unlock_irqrestore(&common->cc_lock, flags);
2271 return -ENOENT;
4f1a5a4b 2272 }
62dad5b0 2273
3430098a
FF
2274 chan = &sband->channels[idx];
2275 pos = chan->hw_value;
2276 memcpy(survey, &sc->survey[pos], sizeof(*survey));
2277 survey->channel = chan;
2278 spin_unlock_irqrestore(&common->cc_lock, flags);
2279
62dad5b0
BP
2280 return 0;
2281}
2282
e239d859
FF
2283static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
2284{
9ac58615 2285 struct ath_softc *sc = hw->priv;
e239d859
FF
2286 struct ath_hw *ah = sc->sc_ah;
2287
2288 mutex_lock(&sc->mutex);
2289 ah->coverage_class = coverage_class;
2290 ath9k_hw_init_global_settings(ah);
2291 mutex_unlock(&sc->mutex);
2292}
2293
69081624
VT
2294static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
2295{
69081624 2296 struct ath_softc *sc = hw->priv;
99aa55b6
MSS
2297 struct ath_hw *ah = sc->sc_ah;
2298 struct ath_common *common = ath9k_hw_common(ah);
86271e46
FF
2299 int timeout = 200; /* ms */
2300 int i, j;
2f6fc351 2301 bool drain_txq;
69081624
VT
2302
2303 mutex_lock(&sc->mutex);
69081624
VT
2304 cancel_delayed_work_sync(&sc->tx_complete_work);
2305
99aa55b6
MSS
2306 if (sc->sc_flags & SC_OP_INVALID) {
2307 ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
2308 mutex_unlock(&sc->mutex);
2309 return;
2310 }
2311
86271e46
FF
2312 if (drop)
2313 timeout = 1;
69081624 2314
86271e46 2315 for (j = 0; j < timeout; j++) {
108697c4 2316 bool npend = false;
86271e46
FF
2317
2318 if (j)
2319 usleep_range(1000, 2000);
69081624 2320
86271e46
FF
2321 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2322 if (!ATH_TXQ_SETUP(sc, i))
2323 continue;
2324
108697c4
MSS
2325 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
2326
2327 if (npend)
2328 break;
69081624 2329 }
86271e46
FF
2330
2331 if (!npend)
2332 goto out;
69081624
VT
2333 }
2334
51513906 2335 ath9k_ps_wakeup(sc);
2f6fc351
RM
2336 spin_lock_bh(&sc->sc_pcu_lock);
2337 drain_txq = ath_drain_all_txq(sc, false);
2f6fc351 2338 if (!drain_txq)
69081624 2339 ath_reset(sc, false);
f6b4e4d4 2340 spin_unlock_bh(&sc->sc_pcu_lock);
51513906 2341 ath9k_ps_restore(sc);
d78f4b3e
SB
2342 ieee80211_wake_queues(hw);
2343
86271e46 2344out:
69081624
VT
2345 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
2346 mutex_unlock(&sc->mutex);
2347}
2348
15b91e83
VN
2349static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2350{
2351 struct ath_softc *sc = hw->priv;
2352 int i;
2353
2354 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2355 if (!ATH_TXQ_SETUP(sc, i))
2356 continue;
2357
2358 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
2359 return true;
2360 }
2361 return false;
2362}
2363
5595f119 2364static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
ba4903f9
FF
2365{
2366 struct ath_softc *sc = hw->priv;
2367 struct ath_hw *ah = sc->sc_ah;
2368 struct ieee80211_vif *vif;
2369 struct ath_vif *avp;
2370 struct ath_buf *bf;
2371 struct ath_tx_status ts;
2372 int status;
2373
2374 vif = sc->beacon.bslot[0];
2375 if (!vif)
2376 return 0;
2377
2378 avp = (void *)vif->drv_priv;
2379 if (!avp->is_bslot_active)
2380 return 0;
2381
2382 if (!sc->beacon.tx_processed) {
2383 tasklet_disable(&sc->bcon_tasklet);
2384
2385 bf = avp->av_bcbuf;
2386 if (!bf || !bf->bf_mpdu)
2387 goto skip;
2388
2389 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2390 if (status == -EINPROGRESS)
2391 goto skip;
2392
2393 sc->beacon.tx_processed = true;
2394 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2395
2396skip:
2397 tasklet_enable(&sc->bcon_tasklet);
2398 }
2399
2400 return sc->beacon.tx_last;
2401}
2402
6baff7f9 2403struct ieee80211_ops ath9k_ops = {
8feceb67
VT
2404 .tx = ath9k_tx,
2405 .start = ath9k_start,
2406 .stop = ath9k_stop,
2407 .add_interface = ath9k_add_interface,
6b3b991d 2408 .change_interface = ath9k_change_interface,
8feceb67
VT
2409 .remove_interface = ath9k_remove_interface,
2410 .config = ath9k_config,
8feceb67 2411 .configure_filter = ath9k_configure_filter,
4ca77860
JB
2412 .sta_add = ath9k_sta_add,
2413 .sta_remove = ath9k_sta_remove,
5519541d 2414 .sta_notify = ath9k_sta_notify,
8feceb67 2415 .conf_tx = ath9k_conf_tx,
8feceb67 2416 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2417 .set_key = ath9k_set_key,
8feceb67 2418 .get_tsf = ath9k_get_tsf,
3b5d665b 2419 .set_tsf = ath9k_set_tsf,
8feceb67 2420 .reset_tsf = ath9k_reset_tsf,
4233df6b 2421 .ampdu_action = ath9k_ampdu_action,
62dad5b0 2422 .get_survey = ath9k_get_survey,
3b319aae 2423 .rfkill_poll = ath9k_rfkill_poll_state,
e239d859 2424 .set_coverage_class = ath9k_set_coverage_class,
69081624 2425 .flush = ath9k_flush,
15b91e83 2426 .tx_frames_pending = ath9k_tx_frames_pending,
ba4903f9 2427 .tx_last_beacon = ath9k_tx_last_beacon,
8feceb67 2428};
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