ath9k: fix stuck beacon detection
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
69081624 18#include <linux/delay.h>
394cf0a1 19#include "ath9k.h"
af03abec 20#include "btcoex.h"
f078f209 21
ff37e337
S
22static u8 parse_mpdudensity(u8 mpdudensity)
23{
24 /*
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
26 * 0 for no restriction
27 * 1 for 1/4 us
28 * 2 for 1/2 us
29 * 3 for 1 us
30 * 4 for 2 us
31 * 5 for 4 us
32 * 6 for 8 us
33 * 7 for 16 us
34 */
35 switch (mpdudensity) {
36 case 0:
37 return 0;
38 case 1:
39 case 2:
40 case 3:
41 /* Our lower layer calculations limit our precision to
42 1 microsecond */
43 return 1;
44 case 4:
45 return 2;
46 case 5:
47 return 4;
48 case 6:
49 return 8;
50 case 7:
51 return 16;
52 default:
53 return 0;
54 }
55}
56
69081624
VT
57static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
58{
59 bool pending = false;
60
61 spin_lock_bh(&txq->axq_lock);
62
63 if (txq->axq_depth || !list_empty(&txq->axq_acq))
64 pending = true;
65 else if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
66 pending = !list_empty(&txq->txq_fifo_pending);
67
68 spin_unlock_bh(&txq->axq_lock);
69 return pending;
70}
71
55624204 72bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR
73{
74 unsigned long flags;
75 bool ret;
76
9ecdef4b
LR
77 spin_lock_irqsave(&sc->sc_pm_lock, flags);
78 ret = ath9k_hw_setpower(sc->sc_ah, mode);
79 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR
80
81 return ret;
82}
83
a91d75ae
LR
84void ath9k_ps_wakeup(struct ath_softc *sc)
85{
898c914a 86 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae 87 unsigned long flags;
fbb078fc 88 enum ath9k_power_mode power_mode;
a91d75ae
LR
89
90 spin_lock_irqsave(&sc->sc_pm_lock, flags);
91 if (++sc->ps_usecount != 1)
92 goto unlock;
93
fbb078fc 94 power_mode = sc->sc_ah->power_mode;
9ecdef4b 95 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae 96
898c914a
FF
97 /*
98 * While the hardware is asleep, the cycle counters contain no
99 * useful data. Better clear them now so that they don't mess up
100 * survey data results.
101 */
fbb078fc
FF
102 if (power_mode != ATH9K_PM_AWAKE) {
103 spin_lock(&common->cc_lock);
104 ath_hw_cycle_counters_update(common);
105 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
106 spin_unlock(&common->cc_lock);
107 }
898c914a 108
a91d75ae
LR
109 unlock:
110 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
111}
112
113void ath9k_ps_restore(struct ath_softc *sc)
114{
898c914a 115 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae
LR
116 unsigned long flags;
117
118 spin_lock_irqsave(&sc->sc_pm_lock, flags);
119 if (--sc->ps_usecount != 0)
120 goto unlock;
121
898c914a
FF
122 spin_lock(&common->cc_lock);
123 ath_hw_cycle_counters_update(common);
124 spin_unlock(&common->cc_lock);
125
1dbfd9d4
VN
126 if (sc->ps_idle)
127 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
128 else if (sc->ps_enabled &&
129 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
1b04b930
S
130 PS_WAIT_FOR_CAB |
131 PS_WAIT_FOR_PSPOLL_DATA |
132 PS_WAIT_FOR_TX_ACK)))
9ecdef4b 133 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
a91d75ae
LR
134
135 unlock:
136 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
137}
138
5ee08656
FF
139static void ath_start_ani(struct ath_common *common)
140{
141 struct ath_hw *ah = common->ah;
142 unsigned long timestamp = jiffies_to_msecs(jiffies);
143 struct ath_softc *sc = (struct ath_softc *) common->priv;
144
145 if (!(sc->sc_flags & SC_OP_ANI_RUN))
146 return;
147
148 if (sc->sc_flags & SC_OP_OFFCHANNEL)
149 return;
150
151 common->ani.longcal_timer = timestamp;
152 common->ani.shortcal_timer = timestamp;
153 common->ani.checkani_timer = timestamp;
154
155 mod_timer(&common->ani.timer,
156 jiffies +
157 msecs_to_jiffies((u32)ah->config.ani_poll_interval));
158}
159
3430098a
FF
160static void ath_update_survey_nf(struct ath_softc *sc, int channel)
161{
162 struct ath_hw *ah = sc->sc_ah;
163 struct ath9k_channel *chan = &ah->channels[channel];
164 struct survey_info *survey = &sc->survey[channel];
165
166 if (chan->noisefloor) {
167 survey->filled |= SURVEY_INFO_NOISE_DBM;
168 survey->noise = chan->noisefloor;
169 }
170}
171
cb8d61de
FF
172/*
173 * Updates the survey statistics and returns the busy time since last
174 * update in %, if the measurement duration was long enough for the
175 * result to be useful, -1 otherwise.
176 */
177static int ath_update_survey_stats(struct ath_softc *sc)
3430098a
FF
178{
179 struct ath_hw *ah = sc->sc_ah;
180 struct ath_common *common = ath9k_hw_common(ah);
181 int pos = ah->curchan - &ah->channels[0];
182 struct survey_info *survey = &sc->survey[pos];
183 struct ath_cycle_counters *cc = &common->cc_survey;
184 unsigned int div = common->clockrate * 1000;
cb8d61de 185 int ret = 0;
3430098a 186
0845735e 187 if (!ah->curchan)
cb8d61de 188 return -1;
0845735e 189
898c914a
FF
190 if (ah->power_mode == ATH9K_PM_AWAKE)
191 ath_hw_cycle_counters_update(common);
3430098a
FF
192
193 if (cc->cycles > 0) {
194 survey->filled |= SURVEY_INFO_CHANNEL_TIME |
195 SURVEY_INFO_CHANNEL_TIME_BUSY |
196 SURVEY_INFO_CHANNEL_TIME_RX |
197 SURVEY_INFO_CHANNEL_TIME_TX;
198 survey->channel_time += cc->cycles / div;
199 survey->channel_time_busy += cc->rx_busy / div;
200 survey->channel_time_rx += cc->rx_frame / div;
201 survey->channel_time_tx += cc->tx_frame / div;
202 }
cb8d61de
FF
203
204 if (cc->cycles < div)
205 return -1;
206
207 if (cc->cycles > 0)
208 ret = cc->rx_busy * 100 / cc->cycles;
209
3430098a
FF
210 memset(cc, 0, sizeof(*cc));
211
212 ath_update_survey_nf(sc, pos);
cb8d61de
FF
213
214 return ret;
3430098a
FF
215}
216
ff37e337
S
217/*
218 * Set/change channels. If the channel is really being changed, it's done
219 * by reseting the chip. To accomplish this we must first cleanup any pending
220 * DMA, then restart stuff.
221*/
0e2dedf9
JM
222int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
223 struct ath9k_channel *hchan)
ff37e337 224{
cbe61d8a 225 struct ath_hw *ah = sc->sc_ah;
c46917bb 226 struct ath_common *common = ath9k_hw_common(ah);
25c56eec 227 struct ieee80211_conf *conf = &common->hw->conf;
ff37e337 228 bool fastcc = true, stopped;
ae8d2858 229 struct ieee80211_channel *channel = hw->conf.channel;
20bd2a09 230 struct ath9k_hw_cal_data *caldata = NULL;
ae8d2858 231 int r;
ff37e337
S
232
233 if (sc->sc_flags & SC_OP_INVALID)
234 return -EIO;
235
cb8d61de
FF
236 sc->hw_busy_count = 0;
237
5ee08656
FF
238 del_timer_sync(&common->ani.timer);
239 cancel_work_sync(&sc->paprd_work);
240 cancel_work_sync(&sc->hw_check_work);
241 cancel_delayed_work_sync(&sc->tx_complete_work);
181fb18d 242 cancel_delayed_work_sync(&sc->hw_pll_work);
5ee08656 243
3cbb5dd7
VN
244 ath9k_ps_wakeup(sc);
245
6a6733f2
LR
246 spin_lock_bh(&sc->sc_pcu_lock);
247
c0d7c7af
LR
248 /*
249 * This is only performed if the channel settings have
250 * actually changed.
251 *
252 * To switch channels clear any pending DMA operations;
253 * wait long enough for the RX fifo to drain, reset the
254 * hardware at the new frequency, and then re-enable
255 * the relevant bits of the h/w.
256 */
4df3071e 257 ath9k_hw_disable_interrupts(ah);
080e1a25 258 stopped = ath_drain_all_txq(sc, false);
5e848f78 259
080e1a25
FF
260 if (!ath_stoprecv(sc))
261 stopped = false;
ff37e337 262
8b3f4616
FF
263 if (!ath9k_hw_check_alive(ah))
264 stopped = false;
265
c0d7c7af
LR
266 /* XXX: do not flush receive queue here. We don't want
267 * to flush data frames already in queue because of
268 * changing channel. */
ff37e337 269
5ee08656 270 if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL))
c0d7c7af
LR
271 fastcc = false;
272
20bd2a09 273 if (!(sc->sc_flags & SC_OP_OFFCHANNEL))
9ac58615 274 caldata = &sc->caldata;
20bd2a09 275
226afe68
JP
276 ath_dbg(common, ATH_DBG_CONFIG,
277 "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n",
278 sc->sc_ah->curchan->channel,
279 channel->center_freq, conf_is_ht40(conf),
280 fastcc);
ff37e337 281
20bd2a09 282 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
c0d7c7af 283 if (r) {
3800276a
JP
284 ath_err(common,
285 "Unable to reset channel (%u MHz), reset status %d\n",
286 channel->center_freq, r);
3989279c 287 goto ps_restore;
ff37e337 288 }
c0d7c7af 289
c0d7c7af 290 if (ath_startrecv(sc) != 0) {
3800276a 291 ath_err(common, "Unable to restart recv logic\n");
3989279c
GJ
292 r = -EIO;
293 goto ps_restore;
c0d7c7af
LR
294 }
295
5048e8c3
RM
296 ath9k_cmn_update_txpow(ah, sc->curtxpow,
297 sc->config.txpowlimit, &sc->curtxpow);
3069168c 298 ath9k_hw_set_interrupts(ah, ah->imask);
3989279c 299
48a6a468 300 if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) {
1186488b
RM
301 if (sc->sc_flags & SC_OP_BEACONS)
302 ath_beacon_config(sc, NULL);
5ee08656 303 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
181fb18d 304 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
48a6a468 305 ath_start_ani(common);
5ee08656
FF
306 }
307
3989279c 308 ps_restore:
92460412
FF
309 ieee80211_wake_queues(hw);
310
6a6733f2
LR
311 spin_unlock_bh(&sc->sc_pcu_lock);
312
3cbb5dd7 313 ath9k_ps_restore(sc);
3989279c 314 return r;
ff37e337
S
315}
316
9f42c2b6
FF
317static void ath_paprd_activate(struct ath_softc *sc)
318{
319 struct ath_hw *ah = sc->sc_ah;
20bd2a09 320 struct ath9k_hw_cal_data *caldata = ah->caldata;
9094537c 321 struct ath_common *common = ath9k_hw_common(ah);
9f42c2b6
FF
322 int chain;
323
20bd2a09 324 if (!caldata || !caldata->paprd_done)
9f42c2b6
FF
325 return;
326
327 ath9k_ps_wakeup(sc);
ddfef792 328 ar9003_paprd_enable(ah, false);
9f42c2b6 329 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
9094537c 330 if (!(common->tx_chainmask & BIT(chain)))
9f42c2b6
FF
331 continue;
332
20bd2a09 333 ar9003_paprd_populate_single_table(ah, caldata, chain);
9f42c2b6
FF
334 }
335
336 ar9003_paprd_enable(ah, true);
337 ath9k_ps_restore(sc);
338}
339
7607cbe2
FF
340static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
341{
342 struct ieee80211_hw *hw = sc->hw;
343 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
47960077
MSS
344 struct ath_hw *ah = sc->sc_ah;
345 struct ath_common *common = ath9k_hw_common(ah);
7607cbe2
FF
346 struct ath_tx_control txctl;
347 int time_left;
348
349 memset(&txctl, 0, sizeof(txctl));
350 txctl.txq = sc->tx.txq_map[WME_AC_BE];
351
352 memset(tx_info, 0, sizeof(*tx_info));
353 tx_info->band = hw->conf.channel->band;
354 tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
355 tx_info->control.rates[0].idx = 0;
356 tx_info->control.rates[0].count = 1;
357 tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
358 tx_info->control.rates[1].idx = -1;
359
360 init_completion(&sc->paprd_complete);
7607cbe2 361 txctl.paprd = BIT(chain);
47960077
MSS
362
363 if (ath_tx_start(hw, skb, &txctl) != 0) {
364 ath_dbg(common, ATH_DBG_XMIT, "PAPRD TX failed\n");
365 dev_kfree_skb_any(skb);
7607cbe2 366 return false;
47960077 367 }
7607cbe2
FF
368
369 time_left = wait_for_completion_timeout(&sc->paprd_complete,
370 msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
7607cbe2
FF
371
372 if (!time_left)
373 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CALIBRATE,
374 "Timeout waiting for paprd training on TX chain %d\n",
375 chain);
376
377 return !!time_left;
378}
379
9f42c2b6
FF
380void ath_paprd_calibrate(struct work_struct *work)
381{
382 struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
383 struct ieee80211_hw *hw = sc->hw;
384 struct ath_hw *ah = sc->sc_ah;
385 struct ieee80211_hdr *hdr;
386 struct sk_buff *skb = NULL;
20bd2a09 387 struct ath9k_hw_cal_data *caldata = ah->caldata;
9094537c 388 struct ath_common *common = ath9k_hw_common(ah);
066dae93 389 int ftype;
9f42c2b6
FF
390 int chain_ok = 0;
391 int chain;
392 int len = 1800;
9f42c2b6 393
20bd2a09
FF
394 if (!caldata)
395 return;
396
1bf38661
FF
397 if (ar9003_paprd_init_table(ah) < 0)
398 return;
399
9f42c2b6
FF
400 skb = alloc_skb(len, GFP_KERNEL);
401 if (!skb)
402 return;
403
9f42c2b6
FF
404 skb_put(skb, len);
405 memset(skb->data, 0, len);
406 hdr = (struct ieee80211_hdr *)skb->data;
407 ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
408 hdr->frame_control = cpu_to_le16(ftype);
a3d3da14 409 hdr->duration_id = cpu_to_le16(10);
9f42c2b6
FF
410 memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
411 memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
412 memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
413
47399f1a 414 ath9k_ps_wakeup(sc);
9f42c2b6 415 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
9094537c 416 if (!(common->tx_chainmask & BIT(chain)))
9f42c2b6
FF
417 continue;
418
419 chain_ok = 0;
9f42c2b6 420
7607cbe2
FF
421 ath_dbg(common, ATH_DBG_CALIBRATE,
422 "Sending PAPRD frame for thermal measurement "
423 "on chain %d\n", chain);
424 if (!ath_paprd_send_frame(sc, skb, chain))
425 goto fail_paprd;
9f42c2b6 426
9f42c2b6 427 ar9003_paprd_setup_gain_table(ah, chain);
9f42c2b6 428
7607cbe2
FF
429 ath_dbg(common, ATH_DBG_CALIBRATE,
430 "Sending PAPRD training frame on chain %d\n", chain);
431 if (!ath_paprd_send_frame(sc, skb, chain))
ca369eb4 432 goto fail_paprd;
9f42c2b6
FF
433
434 if (!ar9003_paprd_is_done(ah))
435 break;
436
20bd2a09 437 if (ar9003_paprd_create_curve(ah, caldata, chain) != 0)
9f42c2b6
FF
438 break;
439
440 chain_ok = 1;
441 }
442 kfree_skb(skb);
443
444 if (chain_ok) {
20bd2a09 445 caldata->paprd_done = true;
9f42c2b6
FF
446 ath_paprd_activate(sc);
447 }
448
ca369eb4 449fail_paprd:
9f42c2b6
FF
450 ath9k_ps_restore(sc);
451}
452
ff37e337
S
453/*
454 * This routine performs the periodic noise floor calibration function
455 * that is used to adjust and optimize the chip performance. This
456 * takes environmental changes (location, temperature) into account.
457 * When the task is complete, it reschedules itself depending on the
458 * appropriate interval that was calculated.
459 */
55624204 460void ath_ani_calibrate(unsigned long data)
ff37e337 461{
20977d3e
S
462 struct ath_softc *sc = (struct ath_softc *)data;
463 struct ath_hw *ah = sc->sc_ah;
c46917bb 464 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
465 bool longcal = false;
466 bool shortcal = false;
467 bool aniflag = false;
468 unsigned int timestamp = jiffies_to_msecs(jiffies);
6044474e 469 u32 cal_interval, short_cal_interval, long_cal_interval;
b5bfc568 470 unsigned long flags;
6044474e
FF
471
472 if (ah->caldata && ah->caldata->nfcal_interference)
473 long_cal_interval = ATH_LONG_CALINTERVAL_INT;
474 else
475 long_cal_interval = ATH_LONG_CALINTERVAL;
ff37e337 476
20977d3e
S
477 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
478 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337 479
1ffc1c61
JM
480 /* Only calibrate if awake */
481 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
482 goto set_timer;
483
484 ath9k_ps_wakeup(sc);
485
ff37e337 486 /* Long calibration runs independently of short calibration. */
6044474e 487 if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
ff37e337 488 longcal = true;
226afe68 489 ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
3d536acf 490 common->ani.longcal_timer = timestamp;
ff37e337
S
491 }
492
17d7904d 493 /* Short calibration applies only while caldone is false */
3d536acf
LR
494 if (!common->ani.caldone) {
495 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 496 shortcal = true;
226afe68
JP
497 ath_dbg(common, ATH_DBG_ANI,
498 "shortcal @%lu\n", jiffies);
3d536acf
LR
499 common->ani.shortcal_timer = timestamp;
500 common->ani.resetcal_timer = timestamp;
ff37e337
S
501 }
502 } else {
3d536acf 503 if ((timestamp - common->ani.resetcal_timer) >=
ff37e337 504 ATH_RESTART_CALINTERVAL) {
3d536acf
LR
505 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
506 if (common->ani.caldone)
507 common->ani.resetcal_timer = timestamp;
ff37e337
S
508 }
509 }
510
511 /* Verify whether we must check ANI */
e36b27af
LR
512 if ((timestamp - common->ani.checkani_timer) >=
513 ah->config.ani_poll_interval) {
ff37e337 514 aniflag = true;
3d536acf 515 common->ani.checkani_timer = timestamp;
ff37e337
S
516 }
517
518 /* Skip all processing if there's nothing to do. */
519 if (longcal || shortcal || aniflag) {
520 /* Call ANI routine if necessary */
b5bfc568
FF
521 if (aniflag) {
522 spin_lock_irqsave(&common->cc_lock, flags);
22e66a4c 523 ath9k_hw_ani_monitor(ah, ah->curchan);
3430098a 524 ath_update_survey_stats(sc);
b5bfc568
FF
525 spin_unlock_irqrestore(&common->cc_lock, flags);
526 }
ff37e337
S
527
528 /* Perform calibration if necessary */
529 if (longcal || shortcal) {
3d536acf 530 common->ani.caldone =
43c27613
LR
531 ath9k_hw_calibrate(ah,
532 ah->curchan,
533 common->rx_chainmask,
534 longcal);
ff37e337
S
535 }
536 }
537
1ffc1c61
JM
538 ath9k_ps_restore(sc);
539
20977d3e 540set_timer:
ff37e337
S
541 /*
542 * Set timer interval based on previous results.
543 * The interval must be the shortest necessary to satisfy ANI,
544 * short calibration and long calibration.
545 */
aac9207e 546 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 547 if (sc->sc_ah->config.enable_ani)
e36b27af
LR
548 cal_interval = min(cal_interval,
549 (u32)ah->config.ani_poll_interval);
3d536acf 550 if (!common->ani.caldone)
20977d3e 551 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 552
3d536acf 553 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
20bd2a09
FF
554 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
555 if (!ah->caldata->paprd_done)
9f42c2b6 556 ieee80211_queue_work(sc->hw, &sc->paprd_work);
45ef6a0b 557 else if (!ah->paprd_table_write_done)
9f42c2b6
FF
558 ath_paprd_activate(sc);
559 }
ff37e337
S
560}
561
ff37e337
S
562static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
563{
564 struct ath_node *an;
ea066d5a 565 struct ath_hw *ah = sc->sc_ah;
ff37e337
S
566 an = (struct ath_node *)sta->drv_priv;
567
7f010c93
BG
568#ifdef CONFIG_ATH9K_DEBUGFS
569 spin_lock(&sc->nodes_lock);
570 list_add(&an->list, &sc->nodes);
571 spin_unlock(&sc->nodes_lock);
572 an->sta = sta;
573#endif
ea066d5a
MSS
574 if ((ah->caps.hw_caps) & ATH9K_HW_CAP_APM)
575 sc->sc_flags |= SC_OP_ENABLE_APM;
576
87792efc 577 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 578 ath_tx_node_init(sc, an);
9e98ac65 579 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S
580 sta->ht_cap.ampdu_factor);
581 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
582 }
ff37e337
S
583}
584
585static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
586{
587 struct ath_node *an = (struct ath_node *)sta->drv_priv;
588
7f010c93
BG
589#ifdef CONFIG_ATH9K_DEBUGFS
590 spin_lock(&sc->nodes_lock);
591 list_del(&an->list);
592 spin_unlock(&sc->nodes_lock);
593 an->sta = NULL;
594#endif
595
ff37e337
S
596 if (sc->sc_flags & SC_OP_TXAGGR)
597 ath_tx_node_cleanup(sc, an);
598}
599
347809fc
FF
600void ath_hw_check(struct work_struct *work)
601{
602 struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
cb8d61de
FF
603 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
604 unsigned long flags;
605 int busy;
347809fc
FF
606
607 ath9k_ps_wakeup(sc);
cb8d61de
FF
608 if (ath9k_hw_check_alive(sc->sc_ah))
609 goto out;
347809fc 610
cb8d61de
FF
611 spin_lock_irqsave(&common->cc_lock, flags);
612 busy = ath_update_survey_stats(sc);
613 spin_unlock_irqrestore(&common->cc_lock, flags);
347809fc 614
cb8d61de
FF
615 ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, "
616 "busy=%d (try %d)\n", busy, sc->hw_busy_count + 1);
617 if (busy >= 99) {
618 if (++sc->hw_busy_count >= 3)
619 ath_reset(sc, true);
620 } else if (busy >= 0)
621 sc->hw_busy_count = 0;
347809fc
FF
622
623out:
624 ath9k_ps_restore(sc);
625}
626
55624204 627void ath9k_tasklet(unsigned long data)
ff37e337
S
628{
629 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 630 struct ath_hw *ah = sc->sc_ah;
c46917bb 631 struct ath_common *common = ath9k_hw_common(ah);
af03abec 632
17d7904d 633 u32 status = sc->intrstatus;
b5c80475 634 u32 rxmask;
ff37e337 635
347809fc 636 if (status & ATH9K_INT_FATAL) {
fac6b6a0 637 ath_reset(sc, true);
ff37e337 638 return;
063d8be3 639 }
ff37e337 640
783cd01e 641 ath9k_ps_wakeup(sc);
52671e43 642 spin_lock(&sc->sc_pcu_lock);
6a6733f2 643
8b3f4616
FF
644 /*
645 * Only run the baseband hang check if beacons stop working in AP or
646 * IBSS mode, because it has a high false positive rate. For station
647 * mode it should not be necessary, since the upper layers will detect
648 * this through a beacon miss automatically and the following channel
649 * change will trigger a hardware reset anyway
650 */
651 if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 &&
652 !ath9k_hw_check_alive(ah))
347809fc
FF
653 ieee80211_queue_work(sc->hw, &sc->hw_check_work);
654
b5c80475
FF
655 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
656 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
657 ATH9K_INT_RXORN);
658 else
659 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
660
661 if (status & rxmask) {
b5c80475
FF
662 /* Check for high priority Rx first */
663 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
664 (status & ATH9K_INT_RXHP))
665 ath_rx_tasklet(sc, 0, true);
666
667 ath_rx_tasklet(sc, 0, false);
ff37e337
S
668 }
669
e5003249
VT
670 if (status & ATH9K_INT_TX) {
671 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
672 ath_tx_edma_tasklet(sc);
673 else
674 ath_tx_tasklet(sc);
675 }
063d8be3 676
96148326 677 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
54ce846e
JM
678 /*
679 * TSF sync does not look correct; remain awake to sync with
680 * the next Beacon.
681 */
226afe68
JP
682 ath_dbg(common, ATH_DBG_PS,
683 "TSFOOR - Sync with next Beacon\n");
1b04b930 684 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
54ce846e
JM
685 }
686
766ec4a9 687 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
ebb8e1d7
VT
688 if (status & ATH9K_INT_GENTIMER)
689 ath_gen_timer_isr(sc->sc_ah);
690
ff37e337 691 /* re-enable hardware interrupt */
4df3071e 692 ath9k_hw_enable_interrupts(ah);
6a6733f2 693
52671e43 694 spin_unlock(&sc->sc_pcu_lock);
153e080d 695 ath9k_ps_restore(sc);
ff37e337
S
696}
697
6baff7f9 698irqreturn_t ath_isr(int irq, void *dev)
ff37e337 699{
063d8be3
S
700#define SCHED_INTR ( \
701 ATH9K_INT_FATAL | \
702 ATH9K_INT_RXORN | \
703 ATH9K_INT_RXEOL | \
704 ATH9K_INT_RX | \
b5c80475
FF
705 ATH9K_INT_RXLP | \
706 ATH9K_INT_RXHP | \
063d8be3
S
707 ATH9K_INT_TX | \
708 ATH9K_INT_BMISS | \
709 ATH9K_INT_CST | \
ebb8e1d7
VT
710 ATH9K_INT_TSFOOR | \
711 ATH9K_INT_GENTIMER)
063d8be3 712
ff37e337 713 struct ath_softc *sc = dev;
cbe61d8a 714 struct ath_hw *ah = sc->sc_ah;
b5bfc568 715 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
716 enum ath9k_int status;
717 bool sched = false;
718
063d8be3
S
719 /*
720 * The hardware is not ready/present, don't
721 * touch anything. Note this can happen early
722 * on if the IRQ is shared.
723 */
724 if (sc->sc_flags & SC_OP_INVALID)
725 return IRQ_NONE;
ff37e337 726
063d8be3
S
727
728 /* shared irq, not for us */
729
153e080d 730 if (!ath9k_hw_intrpend(ah))
063d8be3 731 return IRQ_NONE;
063d8be3
S
732
733 /*
734 * Figure out the reason(s) for the interrupt. Note
735 * that the hal returns a pseudo-ISR that may include
736 * bits we haven't explicitly enabled so we mask the
737 * value to insure we only process bits we requested.
738 */
739 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
3069168c 740 status &= ah->imask; /* discard unasked-for bits */
ff37e337 741
063d8be3
S
742 /*
743 * If there are no status bits set, then this interrupt was not
744 * for me (should have been caught above).
745 */
153e080d 746 if (!status)
063d8be3 747 return IRQ_NONE;
ff37e337 748
063d8be3
S
749 /* Cache the status */
750 sc->intrstatus = status;
751
752 if (status & SCHED_INTR)
753 sched = true;
754
755 /*
756 * If a FATAL or RXORN interrupt is received, we have to reset the
757 * chip immediately.
758 */
b5c80475
FF
759 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
760 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
063d8be3
S
761 goto chip_reset;
762
08578b8f
LR
763 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
764 (status & ATH9K_INT_BB_WATCHDOG)) {
b5bfc568
FF
765
766 spin_lock(&common->cc_lock);
767 ath_hw_cycle_counters_update(common);
08578b8f 768 ar9003_hw_bb_watchdog_dbg_info(ah);
b5bfc568
FF
769 spin_unlock(&common->cc_lock);
770
08578b8f
LR
771 goto chip_reset;
772 }
773
063d8be3
S
774 if (status & ATH9K_INT_SWBA)
775 tasklet_schedule(&sc->bcon_tasklet);
776
777 if (status & ATH9K_INT_TXURN)
778 ath9k_hw_updatetxtriglevel(ah, true);
779
b5c80475
FF
780 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
781 if (status & ATH9K_INT_RXEOL) {
782 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
783 ath9k_hw_set_interrupts(ah, ah->imask);
784 }
785 }
786
063d8be3 787 if (status & ATH9K_INT_MIB) {
ff37e337 788 /*
063d8be3
S
789 * Disable interrupts until we service the MIB
790 * interrupt; otherwise it will continue to
791 * fire.
ff37e337 792 */
4df3071e 793 ath9k_hw_disable_interrupts(ah);
063d8be3
S
794 /*
795 * Let the hal handle the event. We assume
796 * it will clear whatever condition caused
797 * the interrupt.
798 */
88eac2da 799 spin_lock(&common->cc_lock);
bfc472bb 800 ath9k_hw_proc_mib_event(ah);
88eac2da 801 spin_unlock(&common->cc_lock);
4df3071e 802 ath9k_hw_enable_interrupts(ah);
063d8be3 803 }
ff37e337 804
153e080d
VT
805 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
806 if (status & ATH9K_INT_TIM_TIMER) {
ff9f0b63
LR
807 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
808 goto chip_reset;
063d8be3
S
809 /* Clear RxAbort bit so that we can
810 * receive frames */
9ecdef4b 811 ath9k_setpower(sc, ATH9K_PM_AWAKE);
153e080d 812 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930 813 sc->ps_flags |= PS_WAIT_FOR_BEACON;
ff37e337 814 }
063d8be3
S
815
816chip_reset:
ff37e337 817
817e11de
S
818 ath_debug_stat_interrupt(sc, status);
819
ff37e337 820 if (sched) {
4df3071e
FF
821 /* turn off every interrupt */
822 ath9k_hw_disable_interrupts(ah);
ff37e337
S
823 tasklet_schedule(&sc->intr_tq);
824 }
825
826 return IRQ_HANDLED;
063d8be3
S
827
828#undef SCHED_INTR
ff37e337
S
829}
830
8feceb67 831static void ath9k_bss_assoc_info(struct ath_softc *sc,
9fa23e17 832 struct ieee80211_hw *hw,
5640b08e 833 struct ieee80211_vif *vif,
8feceb67 834 struct ieee80211_bss_conf *bss_conf)
f078f209 835{
f2b2143e 836 struct ath_hw *ah = sc->sc_ah;
1510718d 837 struct ath_common *common = ath9k_hw_common(ah);
f078f209 838
8feceb67 839 if (bss_conf->assoc) {
226afe68
JP
840 ath_dbg(common, ATH_DBG_CONFIG,
841 "Bss Info ASSOC %d, bssid: %pM\n",
842 bss_conf->aid, common->curbssid);
f078f209 843
8feceb67 844 /* New association, store aid */
1510718d 845 common->curaid = bss_conf->aid;
f2b2143e 846 ath9k_hw_write_associd(ah);
2664f201
SB
847
848 /*
849 * Request a re-configuration of Beacon related timers
850 * on the receipt of the first Beacon frame (i.e.,
851 * after time sync with the AP).
852 */
1b04b930 853 sc->ps_flags |= PS_BEACON_SYNC;
f078f209 854
8feceb67 855 /* Configure the beacon */
2c3db3d5 856 ath_beacon_config(sc, vif);
f078f209 857
8feceb67 858 /* Reset rssi stats */
9ac58615 859 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
22e66a4c 860 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
f078f209 861
6c3118e2 862 sc->sc_flags |= SC_OP_ANI_RUN;
3d536acf 863 ath_start_ani(common);
8feceb67 864 } else {
226afe68 865 ath_dbg(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
1510718d 866 common->curaid = 0;
f38faa31 867 /* Stop ANI */
6c3118e2 868 sc->sc_flags &= ~SC_OP_ANI_RUN;
3d536acf 869 del_timer_sync(&common->ani.timer);
f078f209 870 }
8feceb67 871}
f078f209 872
68a89116 873void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 874{
cbe61d8a 875 struct ath_hw *ah = sc->sc_ah;
c46917bb 876 struct ath_common *common = ath9k_hw_common(ah);
68a89116 877 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 878 int r;
500c064d 879
3cbb5dd7 880 ath9k_ps_wakeup(sc);
6a6733f2
LR
881 spin_lock_bh(&sc->sc_pcu_lock);
882
93b1b37f 883 ath9k_hw_configpcipowersave(ah, 0, 0);
ae8d2858 884
159cd468 885 if (!ah->curchan)
c344c9cb 886 ah->curchan = ath9k_cmn_get_curchannel(sc->hw, ah);
159cd468 887
20bd2a09 888 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ae8d2858 889 if (r) {
3800276a
JP
890 ath_err(common,
891 "Unable to reset channel (%u MHz), reset status %d\n",
892 channel->center_freq, r);
500c064d 893 }
500c064d 894
5048e8c3
RM
895 ath9k_cmn_update_txpow(ah, sc->curtxpow,
896 sc->config.txpowlimit, &sc->curtxpow);
500c064d 897 if (ath_startrecv(sc) != 0) {
3800276a 898 ath_err(common, "Unable to restart recv logic\n");
c2731b81 899 goto out;
500c064d 900 }
500c064d 901 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 902 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT
903
904 /* Re-Enable interrupts */
3069168c 905 ath9k_hw_set_interrupts(ah, ah->imask);
500c064d
VT
906
907 /* Enable LED */
08fc5c1b 908 ath9k_hw_cfg_output(ah, ah->led_pin,
500c064d 909 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b 910 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
500c064d 911
68a89116 912 ieee80211_wake_queues(hw);
7e3514fd
VN
913 ieee80211_queue_delayed_work(hw, &sc->hw_pll_work, HZ/2);
914
c2731b81 915out:
6a6733f2
LR
916 spin_unlock_bh(&sc->sc_pcu_lock);
917
3cbb5dd7 918 ath9k_ps_restore(sc);
500c064d
VT
919}
920
68a89116 921void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 922{
cbe61d8a 923 struct ath_hw *ah = sc->sc_ah;
68a89116 924 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 925 int r;
500c064d 926
3cbb5dd7 927 ath9k_ps_wakeup(sc);
7e3514fd
VN
928 cancel_delayed_work_sync(&sc->hw_pll_work);
929
6a6733f2
LR
930 spin_lock_bh(&sc->sc_pcu_lock);
931
68a89116 932 ieee80211_stop_queues(hw);
500c064d 933
982723df
VN
934 /*
935 * Keep the LED on when the radio is disabled
936 * during idle unassociated state.
937 */
938 if (!sc->ps_idle) {
939 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
940 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
941 }
500c064d
VT
942
943 /* Disable interrupts */
4df3071e 944 ath9k_hw_disable_interrupts(ah);
500c064d 945
043a0405 946 ath_drain_all_txq(sc, false); /* clear pending tx frames */
5e848f78 947
500c064d
VT
948 ath_stoprecv(sc); /* turn off frame recv */
949 ath_flushrecv(sc); /* flush recv queue */
950
159cd468 951 if (!ah->curchan)
c344c9cb 952 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
159cd468 953
20bd2a09 954 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ae8d2858 955 if (r) {
3800276a
JP
956 ath_err(ath9k_hw_common(sc->sc_ah),
957 "Unable to reset channel (%u MHz), reset status %d\n",
958 channel->center_freq, r);
500c064d 959 }
500c064d
VT
960
961 ath9k_hw_phy_disable(ah);
5e848f78 962
93b1b37f 963 ath9k_hw_configpcipowersave(ah, 1, 1);
6a6733f2
LR
964
965 spin_unlock_bh(&sc->sc_pcu_lock);
3cbb5dd7 966 ath9k_ps_restore(sc);
500c064d
VT
967}
968
ff37e337
S
969int ath_reset(struct ath_softc *sc, bool retry_tx)
970{
cbe61d8a 971 struct ath_hw *ah = sc->sc_ah;
c46917bb 972 struct ath_common *common = ath9k_hw_common(ah);
030bb495 973 struct ieee80211_hw *hw = sc->hw;
ae8d2858 974 int r;
ff37e337 975
cb8d61de
FF
976 sc->hw_busy_count = 0;
977
2ab81d4a
S
978 /* Stop ANI */
979 del_timer_sync(&common->ani.timer);
980
783cd01e 981 ath9k_ps_wakeup(sc);
6a6733f2
LR
982 spin_lock_bh(&sc->sc_pcu_lock);
983
cc9c378a
S
984 ieee80211_stop_queues(hw);
985
4df3071e 986 ath9k_hw_disable_interrupts(ah);
043a0405 987 ath_drain_all_txq(sc, retry_tx);
5e848f78 988
ff37e337
S
989 ath_stoprecv(sc);
990 ath_flushrecv(sc);
991
20bd2a09 992 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
ae8d2858 993 if (r)
3800276a
JP
994 ath_err(common,
995 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S
996
997 if (ath_startrecv(sc) != 0)
3800276a 998 ath_err(common, "Unable to start recv logic\n");
ff37e337
S
999
1000 /*
1001 * We may be doing a reset in response to a request
1002 * that changes the channel so update any state that
1003 * might change as a result.
1004 */
5048e8c3
RM
1005 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1006 sc->config.txpowlimit, &sc->curtxpow);
ff37e337 1007
52b8ac92 1008 if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL)))
2c3db3d5 1009 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 1010
3069168c 1011 ath9k_hw_set_interrupts(ah, ah->imask);
ff37e337
S
1012
1013 if (retry_tx) {
1014 int i;
1015 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1016 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S
1017 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1018 ath_txq_schedule(sc, &sc->tx.txq[i]);
1019 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S
1020 }
1021 }
1022 }
1023
cc9c378a 1024 ieee80211_wake_queues(hw);
6a6733f2 1025 spin_unlock_bh(&sc->sc_pcu_lock);
cc9c378a 1026
2ab81d4a
S
1027 /* Start ANI */
1028 ath_start_ani(common);
783cd01e 1029 ath9k_ps_restore(sc);
2ab81d4a 1030
ae8d2858 1031 return r;
ff37e337
S
1032}
1033
ff37e337
S
1034/**********************/
1035/* mac80211 callbacks */
1036/**********************/
1037
8feceb67 1038static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1039{
9ac58615 1040 struct ath_softc *sc = hw->priv;
af03abec 1041 struct ath_hw *ah = sc->sc_ah;
c46917bb 1042 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 1043 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1044 struct ath9k_channel *init_channel;
82880a7c 1045 int r;
f078f209 1046
226afe68
JP
1047 ath_dbg(common, ATH_DBG_CONFIG,
1048 "Starting driver with initial channel: %d MHz\n",
1049 curchan->center_freq);
f078f209 1050
141b38b6
S
1051 mutex_lock(&sc->mutex);
1052
8feceb67 1053 /* setup initial channel */
82880a7c 1054 sc->chan_idx = curchan->hw_value;
f078f209 1055
c344c9cb 1056 init_channel = ath9k_cmn_get_curchannel(hw, ah);
ff37e337
S
1057
1058 /* Reset SERDES registers */
af03abec 1059 ath9k_hw_configpcipowersave(ah, 0, 0);
ff37e337
S
1060
1061 /*
1062 * The basic interface to setting the hardware in a good
1063 * state is ``reset''. On return the hardware is known to
1064 * be powered up and with interrupts disabled. This must
1065 * be followed by initialization of the appropriate bits
1066 * and then setup of the interrupt mask.
1067 */
4bdd1e97 1068 spin_lock_bh(&sc->sc_pcu_lock);
20bd2a09 1069 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
ae8d2858 1070 if (r) {
3800276a
JP
1071 ath_err(common,
1072 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
1073 r, curchan->center_freq);
4bdd1e97 1074 spin_unlock_bh(&sc->sc_pcu_lock);
141b38b6 1075 goto mutex_unlock;
ff37e337 1076 }
ff37e337
S
1077
1078 /*
1079 * This is needed only to setup initial state
1080 * but it's best done after a reset.
1081 */
5048e8c3
RM
1082 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1083 sc->config.txpowlimit, &sc->curtxpow);
8feceb67 1084
ff37e337
S
1085 /*
1086 * Setup the hardware after reset:
1087 * The receive engine is set going.
1088 * Frame transmit is handled entirely
1089 * in the frame output path; there's nothing to do
1090 * here except setup the interrupt mask.
1091 */
1092 if (ath_startrecv(sc) != 0) {
3800276a 1093 ath_err(common, "Unable to start recv logic\n");
141b38b6 1094 r = -EIO;
4bdd1e97 1095 spin_unlock_bh(&sc->sc_pcu_lock);
141b38b6 1096 goto mutex_unlock;
f078f209 1097 }
4bdd1e97 1098 spin_unlock_bh(&sc->sc_pcu_lock);
8feceb67 1099
ff37e337 1100 /* Setup our intr mask. */
b5c80475
FF
1101 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
1102 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
1103 ATH9K_INT_GLOBAL;
1104
1105 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
08578b8f
LR
1106 ah->imask |= ATH9K_INT_RXHP |
1107 ATH9K_INT_RXLP |
1108 ATH9K_INT_BB_WATCHDOG;
b5c80475
FF
1109 else
1110 ah->imask |= ATH9K_INT_RX;
ff37e337 1111
364734fa 1112 ah->imask |= ATH9K_INT_GTT;
ff37e337 1113
af03abec 1114 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
3069168c 1115 ah->imask |= ATH9K_INT_CST;
ff37e337 1116
ff37e337 1117 sc->sc_flags &= ~SC_OP_INVALID;
5f841b41 1118 sc->sc_ah->is_monitoring = false;
ff37e337
S
1119
1120 /* Disable BMISS interrupt when we're not associated */
3069168c
PR
1121 ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1122 ath9k_hw_set_interrupts(ah, ah->imask);
ff37e337 1123
bce048d7 1124 ieee80211_wake_queues(hw);
ff37e337 1125
42935eca 1126 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
164ace38 1127
766ec4a9
LR
1128 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
1129 !ah->btcoex_hw.enabled) {
5e197292
LR
1130 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1131 AR_STOMP_LOW_WLAN_WGHT);
af03abec 1132 ath9k_hw_btcoex_enable(ah);
f985ad12 1133
5bb12791
LR
1134 if (common->bus_ops->bt_coex_prep)
1135 common->bus_ops->bt_coex_prep(common);
766ec4a9 1136 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1137 ath9k_btcoex_timer_resume(sc);
1773912b
VT
1138 }
1139
8060e169
VT
1140 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
1141 common->bus_ops->extn_synch_en(common);
1142
141b38b6
S
1143mutex_unlock:
1144 mutex_unlock(&sc->mutex);
1145
ae8d2858 1146 return r;
f078f209
LR
1147}
1148
7bb45683 1149static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
f078f209 1150{
9ac58615 1151 struct ath_softc *sc = hw->priv;
c46917bb 1152 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 1153 struct ath_tx_control txctl;
1bc14880 1154 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
528f0c6b 1155
96148326 1156 if (sc->ps_enabled) {
dc8c4585
JM
1157 /*
1158 * mac80211 does not set PM field for normal data frames, so we
1159 * need to update that based on the current PS mode.
1160 */
1161 if (ieee80211_is_data(hdr->frame_control) &&
1162 !ieee80211_is_nullfunc(hdr->frame_control) &&
1163 !ieee80211_has_pm(hdr->frame_control)) {
226afe68
JP
1164 ath_dbg(common, ATH_DBG_PS,
1165 "Add PM=1 for a TX frame while in PS mode\n");
dc8c4585
JM
1166 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1167 }
1168 }
1169
9a23f9ca
JM
1170 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
1171 /*
1172 * We are using PS-Poll and mac80211 can request TX while in
1173 * power save mode. Need to wake up hardware for the TX to be
1174 * completed and if needed, also for RX of buffered frames.
1175 */
9a23f9ca 1176 ath9k_ps_wakeup(sc);
fdf76622
VT
1177 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
1178 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca 1179 if (ieee80211_is_pspoll(hdr->frame_control)) {
226afe68
JP
1180 ath_dbg(common, ATH_DBG_PS,
1181 "Sending PS-Poll to pick a buffered frame\n");
1b04b930 1182 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
9a23f9ca 1183 } else {
226afe68
JP
1184 ath_dbg(common, ATH_DBG_PS,
1185 "Wake up to complete TX\n");
1b04b930 1186 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
9a23f9ca
JM
1187 }
1188 /*
1189 * The actual restore operation will happen only after
1190 * the sc_flags bit is cleared. We are just dropping
1191 * the ps_usecount here.
1192 */
1193 ath9k_ps_restore(sc);
1194 }
1195
528f0c6b 1196 memset(&txctl, 0, sizeof(struct ath_tx_control));
066dae93 1197 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
528f0c6b 1198
226afe68 1199 ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 1200
c52f33d0 1201 if (ath_tx_start(hw, skb, &txctl) != 0) {
226afe68 1202 ath_dbg(common, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 1203 goto exit;
8feceb67
VT
1204 }
1205
7bb45683 1206 return;
528f0c6b
S
1207exit:
1208 dev_kfree_skb_any(skb);
f078f209
LR
1209}
1210
8feceb67 1211static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 1212{
9ac58615 1213 struct ath_softc *sc = hw->priv;
af03abec 1214 struct ath_hw *ah = sc->sc_ah;
c46917bb 1215 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1216
4c483817
S
1217 mutex_lock(&sc->mutex);
1218
c94dbff7 1219 cancel_delayed_work_sync(&sc->tx_complete_work);
181fb18d 1220 cancel_delayed_work_sync(&sc->hw_pll_work);
9f42c2b6 1221 cancel_work_sync(&sc->paprd_work);
347809fc 1222 cancel_work_sync(&sc->hw_check_work);
c94dbff7 1223
9c84b797 1224 if (sc->sc_flags & SC_OP_INVALID) {
226afe68 1225 ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
4c483817 1226 mutex_unlock(&sc->mutex);
9c84b797
S
1227 return;
1228 }
8feceb67 1229
3867cf6a
S
1230 /* Ensure HW is awake when we try to shut it down. */
1231 ath9k_ps_wakeup(sc);
1232
766ec4a9 1233 if (ah->btcoex_hw.enabled) {
af03abec 1234 ath9k_hw_btcoex_disable(ah);
766ec4a9 1235 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1236 ath9k_btcoex_timer_pause(sc);
1773912b
VT
1237 }
1238
6a6733f2
LR
1239 spin_lock_bh(&sc->sc_pcu_lock);
1240
203043f5
SG
1241 /* prevent tasklets to enable interrupts once we disable them */
1242 ah->imask &= ~ATH9K_INT_GLOBAL;
1243
ff37e337
S
1244 /* make sure h/w will not generate any interrupt
1245 * before setting the invalid flag. */
4df3071e 1246 ath9k_hw_disable_interrupts(ah);
ff37e337
S
1247
1248 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 1249 ath_drain_all_txq(sc, false);
ff37e337 1250 ath_stoprecv(sc);
af03abec 1251 ath9k_hw_phy_disable(ah);
6a6733f2 1252 } else
b77f483f 1253 sc->rx.rxlink = NULL;
ff37e337 1254
0d95521e
FF
1255 if (sc->rx.frag) {
1256 dev_kfree_skb_any(sc->rx.frag);
1257 sc->rx.frag = NULL;
1258 }
1259
ff37e337 1260 /* disable HAL and put h/w to sleep */
af03abec
LR
1261 ath9k_hw_disable(ah);
1262 ath9k_hw_configpcipowersave(ah, 1, 1);
6a6733f2
LR
1263
1264 spin_unlock_bh(&sc->sc_pcu_lock);
1265
203043f5
SG
1266 /* we can now sync irq and kill any running tasklets, since we already
1267 * disabled interrupts and not holding a spin lock */
1268 synchronize_irq(sc->irq);
1269 tasklet_kill(&sc->intr_tq);
1270 tasklet_kill(&sc->bcon_tasklet);
1271
3867cf6a
S
1272 ath9k_ps_restore(sc);
1273
a08e7ade
LR
1274 sc->ps_idle = true;
1275 ath_radio_disable(sc, hw);
ff37e337
S
1276
1277 sc->sc_flags |= SC_OP_INVALID;
500c064d 1278
141b38b6
S
1279 mutex_unlock(&sc->mutex);
1280
226afe68 1281 ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR
1282}
1283
4801416c
BG
1284bool ath9k_uses_beacons(int type)
1285{
1286 switch (type) {
1287 case NL80211_IFTYPE_AP:
1288 case NL80211_IFTYPE_ADHOC:
1289 case NL80211_IFTYPE_MESH_POINT:
1290 return true;
1291 default:
1292 return false;
1293 }
1294}
1295
1296static void ath9k_reclaim_beacon(struct ath_softc *sc,
1297 struct ieee80211_vif *vif)
f078f209 1298{
1ed32e4f 1299 struct ath_vif *avp = (void *)vif->drv_priv;
8feceb67 1300
014cf3bb 1301 ath9k_set_beaconing_status(sc, false);
4801416c 1302 ath_beacon_return(sc, avp);
014cf3bb 1303 ath9k_set_beaconing_status(sc, true);
4801416c 1304 sc->sc_flags &= ~SC_OP_BEACONS;
4801416c
BG
1305}
1306
1307static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1308{
1309 struct ath9k_vif_iter_data *iter_data = data;
1310 int i;
1311
1312 if (iter_data->hw_macaddr)
1313 for (i = 0; i < ETH_ALEN; i++)
1314 iter_data->mask[i] &=
1315 ~(iter_data->hw_macaddr[i] ^ mac[i]);
141b38b6 1316
1ed32e4f 1317 switch (vif->type) {
4801416c
BG
1318 case NL80211_IFTYPE_AP:
1319 iter_data->naps++;
f078f209 1320 break;
4801416c
BG
1321 case NL80211_IFTYPE_STATION:
1322 iter_data->nstations++;
e51f3eff 1323 break;
05c914fe 1324 case NL80211_IFTYPE_ADHOC:
4801416c
BG
1325 iter_data->nadhocs++;
1326 break;
9cb5412b 1327 case NL80211_IFTYPE_MESH_POINT:
4801416c
BG
1328 iter_data->nmeshes++;
1329 break;
1330 case NL80211_IFTYPE_WDS:
1331 iter_data->nwds++;
f078f209
LR
1332 break;
1333 default:
4801416c
BG
1334 iter_data->nothers++;
1335 break;
f078f209 1336 }
4801416c 1337}
f078f209 1338
4801416c
BG
1339/* Called with sc->mutex held. */
1340void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
1341 struct ieee80211_vif *vif,
1342 struct ath9k_vif_iter_data *iter_data)
1343{
9ac58615 1344 struct ath_softc *sc = hw->priv;
4801416c
BG
1345 struct ath_hw *ah = sc->sc_ah;
1346 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 1347
4801416c
BG
1348 /*
1349 * Use the hardware MAC address as reference, the hardware uses it
1350 * together with the BSSID mask when matching addresses.
1351 */
1352 memset(iter_data, 0, sizeof(*iter_data));
1353 iter_data->hw_macaddr = common->macaddr;
1354 memset(&iter_data->mask, 0xff, ETH_ALEN);
5640b08e 1355
4801416c
BG
1356 if (vif)
1357 ath9k_vif_iter(iter_data, vif->addr, vif);
1358
1359 /* Get list of all active MAC addresses */
4801416c
BG
1360 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
1361 iter_data);
4801416c 1362}
8ca21f01 1363
4801416c
BG
1364/* Called with sc->mutex held. */
1365static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
1366 struct ieee80211_vif *vif)
1367{
9ac58615 1368 struct ath_softc *sc = hw->priv;
4801416c
BG
1369 struct ath_hw *ah = sc->sc_ah;
1370 struct ath_common *common = ath9k_hw_common(ah);
1371 struct ath9k_vif_iter_data iter_data;
8ca21f01 1372
4801416c 1373 ath9k_calculate_iter_data(hw, vif, &iter_data);
2c3db3d5 1374
4c89fe95 1375 ath9k_ps_wakeup(sc);
4801416c
BG
1376 /* Set BSSID mask. */
1377 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1378 ath_hw_setbssidmask(common);
1379
1380 /* Set op-mode & TSF */
1381 if (iter_data.naps > 0) {
3069168c 1382 ath9k_hw_set_tsfadjust(ah, 1);
b238e90e 1383 sc->sc_flags |= SC_OP_TSF_RESET;
4801416c
BG
1384 ah->opmode = NL80211_IFTYPE_AP;
1385 } else {
1386 ath9k_hw_set_tsfadjust(ah, 0);
1387 sc->sc_flags &= ~SC_OP_TSF_RESET;
5640b08e 1388
4801416c
BG
1389 if (iter_data.nwds + iter_data.nmeshes)
1390 ah->opmode = NL80211_IFTYPE_AP;
1391 else if (iter_data.nadhocs)
1392 ah->opmode = NL80211_IFTYPE_ADHOC;
1393 else
1394 ah->opmode = NL80211_IFTYPE_STATION;
1395 }
5640b08e 1396
4e30ffa2
VN
1397 /*
1398 * Enable MIB interrupts when there are hardware phy counters.
4e30ffa2 1399 */
4801416c 1400 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
3448f912
LR
1401 if (ah->config.enable_ani)
1402 ah->imask |= ATH9K_INT_MIB;
3069168c 1403 ah->imask |= ATH9K_INT_TSFOOR;
4801416c
BG
1404 } else {
1405 ah->imask &= ~ATH9K_INT_MIB;
1406 ah->imask &= ~ATH9K_INT_TSFOOR;
4af9cf4f
S
1407 }
1408
3069168c 1409 ath9k_hw_set_interrupts(ah, ah->imask);
4c89fe95 1410 ath9k_ps_restore(sc);
4e30ffa2 1411
4801416c
BG
1412 /* Set up ANI */
1413 if ((iter_data.naps + iter_data.nadhocs) > 0) {
6c3118e2 1414 sc->sc_flags |= SC_OP_ANI_RUN;
3d536acf 1415 ath_start_ani(common);
4801416c
BG
1416 } else {
1417 sc->sc_flags &= ~SC_OP_ANI_RUN;
1418 del_timer_sync(&common->ani.timer);
6c3118e2 1419 }
4801416c 1420}
6f255425 1421
4801416c
BG
1422/* Called with sc->mutex held, vif counts set up properly. */
1423static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
1424 struct ieee80211_vif *vif)
1425{
9ac58615 1426 struct ath_softc *sc = hw->priv;
4801416c
BG
1427
1428 ath9k_calculate_summary_state(hw, vif);
1429
1430 if (ath9k_uses_beacons(vif->type)) {
1431 int error;
4801416c
BG
1432 /* This may fail because upper levels do not have beacons
1433 * properly configured yet. That's OK, we assume it
1434 * will be properly configured and then we will be notified
1435 * in the info_changed method and set up beacons properly
1436 * there.
1437 */
014cf3bb 1438 ath9k_set_beaconing_status(sc, false);
9ac58615 1439 error = ath_beacon_alloc(sc, vif);
391bd1c4 1440 if (!error)
4801416c 1441 ath_beacon_config(sc, vif);
014cf3bb 1442 ath9k_set_beaconing_status(sc, true);
4801416c 1443 }
f078f209
LR
1444}
1445
4801416c
BG
1446
1447static int ath9k_add_interface(struct ieee80211_hw *hw,
1448 struct ieee80211_vif *vif)
6b3b991d 1449{
9ac58615 1450 struct ath_softc *sc = hw->priv;
4801416c
BG
1451 struct ath_hw *ah = sc->sc_ah;
1452 struct ath_common *common = ath9k_hw_common(ah);
6b3b991d 1453 struct ath_vif *avp = (void *)vif->drv_priv;
4801416c 1454 int ret = 0;
6b3b991d 1455
4801416c 1456 mutex_lock(&sc->mutex);
6b3b991d 1457
4801416c
BG
1458 switch (vif->type) {
1459 case NL80211_IFTYPE_STATION:
1460 case NL80211_IFTYPE_WDS:
1461 case NL80211_IFTYPE_ADHOC:
1462 case NL80211_IFTYPE_AP:
1463 case NL80211_IFTYPE_MESH_POINT:
1464 break;
1465 default:
1466 ath_err(common, "Interface type %d not yet supported\n",
1467 vif->type);
1468 ret = -EOPNOTSUPP;
1469 goto out;
1470 }
6b3b991d 1471
4801416c
BG
1472 if (ath9k_uses_beacons(vif->type)) {
1473 if (sc->nbcnvifs >= ATH_BCBUF) {
1474 ath_err(common, "Not enough beacon buffers when adding"
1475 " new interface of type: %i\n",
1476 vif->type);
1477 ret = -ENOBUFS;
1478 goto out;
1479 }
1480 }
1481
1482 if ((vif->type == NL80211_IFTYPE_ADHOC) &&
1483 sc->nvifs > 0) {
1484 ath_err(common, "Cannot create ADHOC interface when other"
1485 " interfaces already exist.\n");
1486 ret = -EINVAL;
1487 goto out;
6b3b991d 1488 }
4801416c
BG
1489
1490 ath_dbg(common, ATH_DBG_CONFIG,
1491 "Attach a VIF of type: %d\n", vif->type);
1492
1493 /* Set the VIF opmode */
1494 avp->av_opmode = vif->type;
1495 avp->av_bslot = -1;
1496
1497 sc->nvifs++;
1498
1499 ath9k_do_vif_add_setup(hw, vif);
1500out:
1501 mutex_unlock(&sc->mutex);
1502 return ret;
6b3b991d
RM
1503}
1504
1505static int ath9k_change_interface(struct ieee80211_hw *hw,
1506 struct ieee80211_vif *vif,
1507 enum nl80211_iftype new_type,
1508 bool p2p)
1509{
9ac58615 1510 struct ath_softc *sc = hw->priv;
6b3b991d 1511 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
6dab55bf 1512 int ret = 0;
6b3b991d
RM
1513
1514 ath_dbg(common, ATH_DBG_CONFIG, "Change Interface\n");
1515 mutex_lock(&sc->mutex);
1516
4801416c
BG
1517 /* See if new interface type is valid. */
1518 if ((new_type == NL80211_IFTYPE_ADHOC) &&
1519 (sc->nvifs > 1)) {
1520 ath_err(common, "When using ADHOC, it must be the only"
1521 " interface.\n");
1522 ret = -EINVAL;
1523 goto out;
1524 }
1525
1526 if (ath9k_uses_beacons(new_type) &&
1527 !ath9k_uses_beacons(vif->type)) {
6b3b991d
RM
1528 if (sc->nbcnvifs >= ATH_BCBUF) {
1529 ath_err(common, "No beacon slot available\n");
6dab55bf
DC
1530 ret = -ENOBUFS;
1531 goto out;
6b3b991d 1532 }
6b3b991d 1533 }
4801416c
BG
1534
1535 /* Clean up old vif stuff */
1536 if (ath9k_uses_beacons(vif->type))
1537 ath9k_reclaim_beacon(sc, vif);
1538
1539 /* Add new settings */
6b3b991d
RM
1540 vif->type = new_type;
1541 vif->p2p = p2p;
1542
4801416c 1543 ath9k_do_vif_add_setup(hw, vif);
6dab55bf 1544out:
6b3b991d 1545 mutex_unlock(&sc->mutex);
6dab55bf 1546 return ret;
6b3b991d
RM
1547}
1548
8feceb67 1549static void ath9k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1550 struct ieee80211_vif *vif)
f078f209 1551{
9ac58615 1552 struct ath_softc *sc = hw->priv;
c46917bb 1553 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
f078f209 1554
226afe68 1555 ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 1556
141b38b6
S
1557 mutex_lock(&sc->mutex);
1558
4801416c 1559 sc->nvifs--;
580f0b8a 1560
8feceb67 1561 /* Reclaim beacon resources */
4801416c 1562 if (ath9k_uses_beacons(vif->type))
6b3b991d 1563 ath9k_reclaim_beacon(sc, vif);
2c3db3d5 1564
4801416c 1565 ath9k_calculate_summary_state(hw, NULL);
141b38b6
S
1566
1567 mutex_unlock(&sc->mutex);
f078f209
LR
1568}
1569
fbab7390 1570static void ath9k_enable_ps(struct ath_softc *sc)
3f7c5c10 1571{
3069168c
PR
1572 struct ath_hw *ah = sc->sc_ah;
1573
3f7c5c10 1574 sc->ps_enabled = true;
3069168c
PR
1575 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1576 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1577 ah->imask |= ATH9K_INT_TIM_TIMER;
1578 ath9k_hw_set_interrupts(ah, ah->imask);
3f7c5c10 1579 }
fdf76622 1580 ath9k_hw_setrxabort(ah, 1);
3f7c5c10 1581 }
3f7c5c10
SB
1582}
1583
845d708e
SB
1584static void ath9k_disable_ps(struct ath_softc *sc)
1585{
1586 struct ath_hw *ah = sc->sc_ah;
1587
1588 sc->ps_enabled = false;
1589 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1590 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1591 ath9k_hw_setrxabort(ah, 0);
1592 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1593 PS_WAIT_FOR_CAB |
1594 PS_WAIT_FOR_PSPOLL_DATA |
1595 PS_WAIT_FOR_TX_ACK);
1596 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1597 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1598 ath9k_hw_set_interrupts(ah, ah->imask);
1599 }
1600 }
1601
1602}
1603
e8975581 1604static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1605{
9ac58615 1606 struct ath_softc *sc = hw->priv;
3430098a
FF
1607 struct ath_hw *ah = sc->sc_ah;
1608 struct ath_common *common = ath9k_hw_common(ah);
e8975581 1609 struct ieee80211_conf *conf = &hw->conf;
7545daf4 1610 bool disable_radio = false;
f078f209 1611
aa33de09 1612 mutex_lock(&sc->mutex);
141b38b6 1613
194b7c13
LR
1614 /*
1615 * Leave this as the first check because we need to turn on the
1616 * radio if it was disabled before prior to processing the rest
1617 * of the changes. Likewise we must only disable the radio towards
1618 * the end.
1619 */
64839170 1620 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
7545daf4
FF
1621 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1622 if (!sc->ps_idle) {
68a89116 1623 ath_radio_enable(sc, hw);
226afe68
JP
1624 ath_dbg(common, ATH_DBG_CONFIG,
1625 "not-idle: enabling radio\n");
7545daf4
FF
1626 } else {
1627 disable_radio = true;
64839170
LR
1628 }
1629 }
1630
e7824a50
LR
1631 /*
1632 * We just prepare to enable PS. We have to wait until our AP has
1633 * ACK'd our null data frame to disable RX otherwise we'll ignore
1634 * those ACKs and end up retransmitting the same null data frames.
1635 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1636 */
3cbb5dd7 1637 if (changed & IEEE80211_CONF_CHANGE_PS) {
8ab2cd09
LR
1638 unsigned long flags;
1639 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fbab7390
SB
1640 if (conf->flags & IEEE80211_CONF_PS)
1641 ath9k_enable_ps(sc);
845d708e
SB
1642 else
1643 ath9k_disable_ps(sc);
8ab2cd09 1644 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3cbb5dd7
VN
1645 }
1646
199afd9d
S
1647 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1648 if (conf->flags & IEEE80211_CONF_MONITOR) {
226afe68
JP
1649 ath_dbg(common, ATH_DBG_CONFIG,
1650 "Monitor mode is enabled\n");
5f841b41
RM
1651 sc->sc_ah->is_monitoring = true;
1652 } else {
226afe68
JP
1653 ath_dbg(common, ATH_DBG_CONFIG,
1654 "Monitor mode is disabled\n");
5f841b41 1655 sc->sc_ah->is_monitoring = false;
199afd9d
S
1656 }
1657 }
1658
4797938c 1659 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 1660 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 1661 int pos = curchan->hw_value;
3430098a
FF
1662 int old_pos = -1;
1663 unsigned long flags;
1664
1665 if (ah->curchan)
1666 old_pos = ah->curchan - &ah->channels[0];
ae5eb026 1667
5ee08656
FF
1668 if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
1669 sc->sc_flags |= SC_OP_OFFCHANNEL;
1670 else
1671 sc->sc_flags &= ~SC_OP_OFFCHANNEL;
0e2dedf9 1672
8c79a610
BG
1673 ath_dbg(common, ATH_DBG_CONFIG,
1674 "Set channel: %d MHz type: %d\n",
1675 curchan->center_freq, conf->channel_type);
f078f209 1676
de87f736
RM
1677 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
1678 curchan, conf->channel_type);
e11602b7 1679
3430098a
FF
1680 /* update survey stats for the old channel before switching */
1681 spin_lock_irqsave(&common->cc_lock, flags);
1682 ath_update_survey_stats(sc);
1683 spin_unlock_irqrestore(&common->cc_lock, flags);
1684
1685 /*
1686 * If the operating channel changes, change the survey in-use flags
1687 * along with it.
1688 * Reset the survey data for the new channel, unless we're switching
1689 * back to the operating channel from an off-channel operation.
1690 */
1691 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1692 sc->cur_survey != &sc->survey[pos]) {
1693
1694 if (sc->cur_survey)
1695 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1696
1697 sc->cur_survey = &sc->survey[pos];
1698
1699 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1700 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1701 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1702 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1703 }
1704
0e2dedf9 1705 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
3800276a 1706 ath_err(common, "Unable to set channel\n");
aa33de09 1707 mutex_unlock(&sc->mutex);
e11602b7
S
1708 return -EINVAL;
1709 }
3430098a
FF
1710
1711 /*
1712 * The most recent snapshot of channel->noisefloor for the old
1713 * channel is only available after the hardware reset. Copy it to
1714 * the survey stats now.
1715 */
1716 if (old_pos >= 0)
1717 ath_update_survey_nf(sc, old_pos);
094d05dc 1718 }
f078f209 1719
c9f6a656 1720 if (changed & IEEE80211_CONF_CHANGE_POWER) {
603b3eef
BG
1721 ath_dbg(common, ATH_DBG_CONFIG,
1722 "Set power: %d\n", conf->power_level);
17d7904d 1723 sc->config.txpowlimit = 2 * conf->power_level;
783cd01e 1724 ath9k_ps_wakeup(sc);
5048e8c3
RM
1725 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1726 sc->config.txpowlimit, &sc->curtxpow);
783cd01e 1727 ath9k_ps_restore(sc);
c9f6a656 1728 }
f078f209 1729
64839170 1730 if (disable_radio) {
226afe68 1731 ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
68a89116 1732 ath_radio_disable(sc, hw);
64839170
LR
1733 }
1734
aa33de09 1735 mutex_unlock(&sc->mutex);
141b38b6 1736
f078f209
LR
1737 return 0;
1738}
1739
8feceb67
VT
1740#define SUPPORTED_FILTERS \
1741 (FIF_PROMISC_IN_BSS | \
1742 FIF_ALLMULTI | \
1743 FIF_CONTROL | \
af6a3fc7 1744 FIF_PSPOLL | \
8feceb67
VT
1745 FIF_OTHER_BSS | \
1746 FIF_BCN_PRBRESP_PROMISC | \
9c1d8e4a 1747 FIF_PROBE_REQ | \
8feceb67 1748 FIF_FCSFAIL)
c83be688 1749
8feceb67
VT
1750/* FIXME: sc->sc_full_reset ? */
1751static void ath9k_configure_filter(struct ieee80211_hw *hw,
1752 unsigned int changed_flags,
1753 unsigned int *total_flags,
3ac64bee 1754 u64 multicast)
8feceb67 1755{
9ac58615 1756 struct ath_softc *sc = hw->priv;
8feceb67 1757 u32 rfilt;
f078f209 1758
8feceb67
VT
1759 changed_flags &= SUPPORTED_FILTERS;
1760 *total_flags &= SUPPORTED_FILTERS;
f078f209 1761
b77f483f 1762 sc->rx.rxfilter = *total_flags;
aa68aeaa 1763 ath9k_ps_wakeup(sc);
8feceb67
VT
1764 rfilt = ath_calcrxfilter(sc);
1765 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 1766 ath9k_ps_restore(sc);
f078f209 1767
226afe68
JP
1768 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
1769 "Set HW RX filter: 0x%x\n", rfilt);
8feceb67 1770}
f078f209 1771
4ca77860
JB
1772static int ath9k_sta_add(struct ieee80211_hw *hw,
1773 struct ieee80211_vif *vif,
1774 struct ieee80211_sta *sta)
8feceb67 1775{
9ac58615 1776 struct ath_softc *sc = hw->priv;
f078f209 1777
4ca77860
JB
1778 ath_node_attach(sc, sta);
1779
1780 return 0;
1781}
1782
1783static int ath9k_sta_remove(struct ieee80211_hw *hw,
1784 struct ieee80211_vif *vif,
1785 struct ieee80211_sta *sta)
1786{
9ac58615 1787 struct ath_softc *sc = hw->priv;
4ca77860
JB
1788
1789 ath_node_detach(sc, sta);
1790
1791 return 0;
f078f209
LR
1792}
1793
141b38b6 1794static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 1795 const struct ieee80211_tx_queue_params *params)
f078f209 1796{
9ac58615 1797 struct ath_softc *sc = hw->priv;
c46917bb 1798 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
066dae93 1799 struct ath_txq *txq;
8feceb67 1800 struct ath9k_tx_queue_info qi;
066dae93 1801 int ret = 0;
f078f209 1802
8feceb67
VT
1803 if (queue >= WME_NUM_AC)
1804 return 0;
f078f209 1805
066dae93
FF
1806 txq = sc->tx.txq_map[queue];
1807
141b38b6
S
1808 mutex_lock(&sc->mutex);
1809
1ffb0610
S
1810 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1811
8feceb67
VT
1812 qi.tqi_aifs = params->aifs;
1813 qi.tqi_cwmin = params->cw_min;
1814 qi.tqi_cwmax = params->cw_max;
1815 qi.tqi_burstTime = params->txop;
f078f209 1816
226afe68
JP
1817 ath_dbg(common, ATH_DBG_CONFIG,
1818 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1819 queue, txq->axq_qnum, params->aifs, params->cw_min,
1820 params->cw_max, params->txop);
f078f209 1821
066dae93 1822 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
8feceb67 1823 if (ret)
3800276a 1824 ath_err(common, "TXQ Update failed\n");
f078f209 1825
94db2936 1826 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
066dae93 1827 if (queue == WME_AC_BE && !ret)
94db2936
VN
1828 ath_beaconq_config(sc);
1829
141b38b6
S
1830 mutex_unlock(&sc->mutex);
1831
8feceb67
VT
1832 return ret;
1833}
f078f209 1834
8feceb67
VT
1835static int ath9k_set_key(struct ieee80211_hw *hw,
1836 enum set_key_cmd cmd,
dc822b5d
JB
1837 struct ieee80211_vif *vif,
1838 struct ieee80211_sta *sta,
8feceb67
VT
1839 struct ieee80211_key_conf *key)
1840{
9ac58615 1841 struct ath_softc *sc = hw->priv;
c46917bb 1842 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67 1843 int ret = 0;
f078f209 1844
3e6109c5 1845 if (ath9k_modparam_nohwcrypt)
b3bd89ce
JM
1846 return -ENOSPC;
1847
141b38b6 1848 mutex_lock(&sc->mutex);
3cbb5dd7 1849 ath9k_ps_wakeup(sc);
226afe68 1850 ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 1851
8feceb67
VT
1852 switch (cmd) {
1853 case SET_KEY:
040e539e 1854 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM
1855 if (ret >= 0) {
1856 key->hw_key_idx = ret;
8feceb67
VT
1857 /* push IV and Michael MIC generation to stack */
1858 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
97359d12 1859 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
8feceb67 1860 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
97359d12
JB
1861 if (sc->sc_ah->sw_mgmt_crypto &&
1862 key->cipher == WLAN_CIPHER_SUITE_CCMP)
0ced0e17 1863 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 1864 ret = 0;
8feceb67
VT
1865 }
1866 break;
1867 case DISABLE_KEY:
040e539e 1868 ath_key_delete(common, key);
8feceb67
VT
1869 break;
1870 default:
1871 ret = -EINVAL;
1872 }
f078f209 1873
3cbb5dd7 1874 ath9k_ps_restore(sc);
141b38b6
S
1875 mutex_unlock(&sc->mutex);
1876
8feceb67
VT
1877 return ret;
1878}
f078f209 1879
8feceb67
VT
1880static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1881 struct ieee80211_vif *vif,
1882 struct ieee80211_bss_conf *bss_conf,
1883 u32 changed)
1884{
9ac58615 1885 struct ath_softc *sc = hw->priv;
9814f6b3 1886 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
2d0ddec5 1887 struct ath_hw *ah = sc->sc_ah;
1510718d 1888 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 1889 struct ath_vif *avp = (void *)vif->drv_priv;
0005baf4 1890 int slottime;
c6089ccc 1891 int error;
f078f209 1892
141b38b6
S
1893 mutex_lock(&sc->mutex);
1894
c6089ccc
S
1895 if (changed & BSS_CHANGED_BSSID) {
1896 /* Set BSSID */
1897 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1898 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1510718d 1899 common->curaid = 0;
f2b2143e 1900 ath9k_hw_write_associd(ah);
2d0ddec5 1901
c6089ccc
S
1902 /* Set aggregation protection mode parameters */
1903 sc->config.ath_aggr_prot = 0;
2d0ddec5 1904
226afe68
JP
1905 ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n",
1906 common->curbssid, common->curaid);
2d0ddec5 1907
c6089ccc
S
1908 /* need to reconfigure the beacon */
1909 sc->sc_flags &= ~SC_OP_BEACONS ;
1910 }
2d0ddec5 1911
c6089ccc
S
1912 /* Enable transmission of beacons (AP, IBSS, MESH) */
1913 if ((changed & BSS_CHANGED_BEACON) ||
1914 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
014cf3bb 1915 ath9k_set_beaconing_status(sc, false);
9ac58615 1916 error = ath_beacon_alloc(sc, vif);
c6089ccc
S
1917 if (!error)
1918 ath_beacon_config(sc, vif);
014cf3bb 1919 ath9k_set_beaconing_status(sc, true);
0005baf4
FF
1920 }
1921
1922 if (changed & BSS_CHANGED_ERP_SLOT) {
1923 if (bss_conf->use_short_slot)
1924 slottime = 9;
1925 else
1926 slottime = 20;
1927 if (vif->type == NL80211_IFTYPE_AP) {
1928 /*
1929 * Defer update, so that connected stations can adjust
1930 * their settings at the same time.
1931 * See beacon.c for more details
1932 */
1933 sc->beacon.slottime = slottime;
1934 sc->beacon.updateslot = UPDATE;
1935 } else {
1936 ah->slottime = slottime;
1937 ath9k_hw_init_global_settings(ah);
1938 }
2d0ddec5
JB
1939 }
1940
c6089ccc 1941 /* Disable transmission of beacons */
014cf3bb
RM
1942 if ((changed & BSS_CHANGED_BEACON_ENABLED) &&
1943 !bss_conf->enable_beacon) {
1944 ath9k_set_beaconing_status(sc, false);
1945 avp->is_bslot_active = false;
1946 ath9k_set_beaconing_status(sc, true);
1947 }
2d0ddec5 1948
c6089ccc 1949 if (changed & BSS_CHANGED_BEACON_INT) {
9814f6b3 1950 cur_conf->beacon_interval = bss_conf->beacon_int;
c6089ccc
S
1951 /*
1952 * In case of AP mode, the HW TSF has to be reset
1953 * when the beacon interval changes.
1954 */
1955 if (vif->type == NL80211_IFTYPE_AP) {
1956 sc->sc_flags |= SC_OP_TSF_RESET;
014cf3bb 1957 ath9k_set_beaconing_status(sc, false);
9ac58615 1958 error = ath_beacon_alloc(sc, vif);
2d0ddec5
JB
1959 if (!error)
1960 ath_beacon_config(sc, vif);
014cf3bb 1961 ath9k_set_beaconing_status(sc, true);
c6089ccc
S
1962 } else {
1963 ath_beacon_config(sc, vif);
2d0ddec5
JB
1964 }
1965 }
1966
8feceb67 1967 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
226afe68
JP
1968 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
1969 bss_conf->use_short_preamble);
8feceb67
VT
1970 if (bss_conf->use_short_preamble)
1971 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
1972 else
1973 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
1974 }
f078f209 1975
8feceb67 1976 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
226afe68
JP
1977 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
1978 bss_conf->use_cts_prot);
8feceb67
VT
1979 if (bss_conf->use_cts_prot &&
1980 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
1981 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
1982 else
1983 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
1984 }
f078f209 1985
8feceb67 1986 if (changed & BSS_CHANGED_ASSOC) {
226afe68 1987 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 1988 bss_conf->assoc);
9fa23e17 1989 ath9k_bss_assoc_info(sc, hw, vif, bss_conf);
8feceb67 1990 }
141b38b6
S
1991
1992 mutex_unlock(&sc->mutex);
8feceb67 1993}
f078f209 1994
8feceb67
VT
1995static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
1996{
9ac58615 1997 struct ath_softc *sc = hw->priv;
8feceb67 1998 u64 tsf;
f078f209 1999
141b38b6 2000 mutex_lock(&sc->mutex);
9abbfb27 2001 ath9k_ps_wakeup(sc);
141b38b6 2002 tsf = ath9k_hw_gettsf64(sc->sc_ah);
9abbfb27 2003 ath9k_ps_restore(sc);
141b38b6 2004 mutex_unlock(&sc->mutex);
f078f209 2005
8feceb67
VT
2006 return tsf;
2007}
f078f209 2008
3b5d665b
AF
2009static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2010{
9ac58615 2011 struct ath_softc *sc = hw->priv;
3b5d665b 2012
141b38b6 2013 mutex_lock(&sc->mutex);
9abbfb27 2014 ath9k_ps_wakeup(sc);
141b38b6 2015 ath9k_hw_settsf64(sc->sc_ah, tsf);
9abbfb27 2016 ath9k_ps_restore(sc);
141b38b6 2017 mutex_unlock(&sc->mutex);
3b5d665b
AF
2018}
2019
8feceb67
VT
2020static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2021{
9ac58615 2022 struct ath_softc *sc = hw->priv;
c83be688 2023
141b38b6 2024 mutex_lock(&sc->mutex);
21526d57
LR
2025
2026 ath9k_ps_wakeup(sc);
141b38b6 2027 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR
2028 ath9k_ps_restore(sc);
2029
141b38b6 2030 mutex_unlock(&sc->mutex);
8feceb67 2031}
f078f209 2032
8feceb67 2033static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 2034 struct ieee80211_vif *vif,
141b38b6
S
2035 enum ieee80211_ampdu_mlme_action action,
2036 struct ieee80211_sta *sta,
0b01f030 2037 u16 tid, u16 *ssn, u8 buf_size)
8feceb67 2038{
9ac58615 2039 struct ath_softc *sc = hw->priv;
8feceb67 2040 int ret = 0;
f078f209 2041
85ad181e
JB
2042 local_bh_disable();
2043
8feceb67
VT
2044 switch (action) {
2045 case IEEE80211_AMPDU_RX_START:
dca3edb8
S
2046 if (!(sc->sc_flags & SC_OP_RXAGGR))
2047 ret = -ENOTSUPP;
8feceb67
VT
2048 break;
2049 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT
2050 break;
2051 case IEEE80211_AMPDU_TX_START:
71a3bf3e
FF
2052 if (!(sc->sc_flags & SC_OP_TXAGGR))
2053 return -EOPNOTSUPP;
2054
8b685ba9 2055 ath9k_ps_wakeup(sc);
231c3a1f
FF
2056 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2057 if (!ret)
2058 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2059 ath9k_ps_restore(sc);
8feceb67
VT
2060 break;
2061 case IEEE80211_AMPDU_TX_STOP:
8b685ba9 2062 ath9k_ps_wakeup(sc);
f83da965 2063 ath_tx_aggr_stop(sc, sta, tid);
c951ad35 2064 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2065 ath9k_ps_restore(sc);
8feceb67 2066 break;
b1720231 2067 case IEEE80211_AMPDU_TX_OPERATIONAL:
8b685ba9 2068 ath9k_ps_wakeup(sc);
8469cdef 2069 ath_tx_aggr_resume(sc, sta, tid);
8b685ba9 2070 ath9k_ps_restore(sc);
8469cdef 2071 break;
8feceb67 2072 default:
3800276a 2073 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
8feceb67
VT
2074 }
2075
85ad181e
JB
2076 local_bh_enable();
2077
8feceb67 2078 return ret;
f078f209
LR
2079}
2080
62dad5b0
BP
2081static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2082 struct survey_info *survey)
2083{
9ac58615 2084 struct ath_softc *sc = hw->priv;
3430098a 2085 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39162dbe 2086 struct ieee80211_supported_band *sband;
3430098a
FF
2087 struct ieee80211_channel *chan;
2088 unsigned long flags;
2089 int pos;
2090
2091 spin_lock_irqsave(&common->cc_lock, flags);
2092 if (idx == 0)
2093 ath_update_survey_stats(sc);
39162dbe
FF
2094
2095 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2096 if (sband && idx >= sband->n_channels) {
2097 idx -= sband->n_channels;
2098 sband = NULL;
2099 }
62dad5b0 2100
39162dbe
FF
2101 if (!sband)
2102 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
62dad5b0 2103
3430098a
FF
2104 if (!sband || idx >= sband->n_channels) {
2105 spin_unlock_irqrestore(&common->cc_lock, flags);
2106 return -ENOENT;
4f1a5a4b 2107 }
62dad5b0 2108
3430098a
FF
2109 chan = &sband->channels[idx];
2110 pos = chan->hw_value;
2111 memcpy(survey, &sc->survey[pos], sizeof(*survey));
2112 survey->channel = chan;
2113 spin_unlock_irqrestore(&common->cc_lock, flags);
2114
62dad5b0
BP
2115 return 0;
2116}
2117
e239d859
FF
2118static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
2119{
9ac58615 2120 struct ath_softc *sc = hw->priv;
e239d859
FF
2121 struct ath_hw *ah = sc->sc_ah;
2122
2123 mutex_lock(&sc->mutex);
2124 ah->coverage_class = coverage_class;
2125 ath9k_hw_init_global_settings(ah);
2126 mutex_unlock(&sc->mutex);
2127}
2128
69081624
VT
2129static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
2130{
69081624 2131 struct ath_softc *sc = hw->priv;
86271e46
FF
2132 int timeout = 200; /* ms */
2133 int i, j;
69081624 2134
86271e46 2135 ath9k_ps_wakeup(sc);
69081624
VT
2136 mutex_lock(&sc->mutex);
2137
2138 cancel_delayed_work_sync(&sc->tx_complete_work);
2139
86271e46
FF
2140 if (drop)
2141 timeout = 1;
69081624 2142
86271e46
FF
2143 for (j = 0; j < timeout; j++) {
2144 int npend = 0;
2145
2146 if (j)
2147 usleep_range(1000, 2000);
69081624 2148
86271e46
FF
2149 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2150 if (!ATH_TXQ_SETUP(sc, i))
2151 continue;
2152
2153 npend += ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
69081624 2154 }
86271e46
FF
2155
2156 if (!npend)
2157 goto out;
69081624
VT
2158 }
2159
86271e46 2160 if (!ath_drain_all_txq(sc, false))
69081624 2161 ath_reset(sc, false);
69081624 2162
d78f4b3e
SB
2163 ieee80211_wake_queues(hw);
2164
86271e46 2165out:
69081624
VT
2166 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
2167 mutex_unlock(&sc->mutex);
86271e46 2168 ath9k_ps_restore(sc);
69081624
VT
2169}
2170
6baff7f9 2171struct ieee80211_ops ath9k_ops = {
8feceb67
VT
2172 .tx = ath9k_tx,
2173 .start = ath9k_start,
2174 .stop = ath9k_stop,
2175 .add_interface = ath9k_add_interface,
6b3b991d 2176 .change_interface = ath9k_change_interface,
8feceb67
VT
2177 .remove_interface = ath9k_remove_interface,
2178 .config = ath9k_config,
8feceb67 2179 .configure_filter = ath9k_configure_filter,
4ca77860
JB
2180 .sta_add = ath9k_sta_add,
2181 .sta_remove = ath9k_sta_remove,
8feceb67 2182 .conf_tx = ath9k_conf_tx,
8feceb67 2183 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2184 .set_key = ath9k_set_key,
8feceb67 2185 .get_tsf = ath9k_get_tsf,
3b5d665b 2186 .set_tsf = ath9k_set_tsf,
8feceb67 2187 .reset_tsf = ath9k_reset_tsf,
4233df6b 2188 .ampdu_action = ath9k_ampdu_action,
62dad5b0 2189 .get_survey = ath9k_get_survey,
3b319aae 2190 .rfkill_poll = ath9k_rfkill_poll_state,
e239d859 2191 .set_coverage_class = ath9k_set_coverage_class,
69081624 2192 .flush = ath9k_flush,
8feceb67 2193};
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