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ath9k: Add infrastructure for generic hw timers
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
f078f209 19
f078f209
LR		 20static char *dev_info = "ath9k";
21
22MODULE_AUTHOR("Atheros Communications");
23MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
24MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
25MODULE_LICENSE("Dual BSD/GPL");
26
b3bd89ce
JM		 27static int modparam_nohwcrypt;
28module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
29MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
30
5f8e077c
LR		 31/* We use the hw_value as an index into our private channel structure */
32
33#define CHAN2G(_freq, _idx) { \
34 .center_freq = (_freq), \
35 .hw_value = (_idx), \
eeddfd9d 36 .max_power = 20, \
5f8e077c
LR		 37}
38
39#define CHAN5G(_freq, _idx) { \
40 .band = IEEE80211_BAND_5GHZ, \
41 .center_freq = (_freq), \
42 .hw_value = (_idx), \
eeddfd9d 43 .max_power = 20, \
5f8e077c
LR		 44}
45
46/* Some 2 GHz radios are actually tunable on 2312-2732
47 * on 5 MHz steps, we support the channels which we know
48 * we have calibration data for all cards though to make
49 * this static */
50static struct ieee80211_channel ath9k_2ghz_chantable[] = {
51 CHAN2G(2412, 0), /* Channel 1 */
52 CHAN2G(2417, 1), /* Channel 2 */
53 CHAN2G(2422, 2), /* Channel 3 */
54 CHAN2G(2427, 3), /* Channel 4 */
55 CHAN2G(2432, 4), /* Channel 5 */
56 CHAN2G(2437, 5), /* Channel 6 */
57 CHAN2G(2442, 6), /* Channel 7 */
58 CHAN2G(2447, 7), /* Channel 8 */
59 CHAN2G(2452, 8), /* Channel 9 */
60 CHAN2G(2457, 9), /* Channel 10 */
61 CHAN2G(2462, 10), /* Channel 11 */
62 CHAN2G(2467, 11), /* Channel 12 */
63 CHAN2G(2472, 12), /* Channel 13 */
64 CHAN2G(2484, 13), /* Channel 14 */
65};
66
67/* Some 5 GHz radios are actually tunable on XXXX-YYYY
68 * on 5 MHz steps, we support the channels which we know
69 * we have calibration data for all cards though to make
70 * this static */
71static struct ieee80211_channel ath9k_5ghz_chantable[] = {
72 /* _We_ call this UNII 1 */
73 CHAN5G(5180, 14), /* Channel 36 */
74 CHAN5G(5200, 15), /* Channel 40 */
75 CHAN5G(5220, 16), /* Channel 44 */
76 CHAN5G(5240, 17), /* Channel 48 */
77 /* _We_ call this UNII 2 */
78 CHAN5G(5260, 18), /* Channel 52 */
79 CHAN5G(5280, 19), /* Channel 56 */
80 CHAN5G(5300, 20), /* Channel 60 */
81 CHAN5G(5320, 21), /* Channel 64 */
82 /* _We_ call this "Middle band" */
83 CHAN5G(5500, 22), /* Channel 100 */
84 CHAN5G(5520, 23), /* Channel 104 */
85 CHAN5G(5540, 24), /* Channel 108 */
86 CHAN5G(5560, 25), /* Channel 112 */
87 CHAN5G(5580, 26), /* Channel 116 */
88 CHAN5G(5600, 27), /* Channel 120 */
89 CHAN5G(5620, 28), /* Channel 124 */
90 CHAN5G(5640, 29), /* Channel 128 */
91 CHAN5G(5660, 30), /* Channel 132 */
92 CHAN5G(5680, 31), /* Channel 136 */
93 CHAN5G(5700, 32), /* Channel 140 */
94 /* _We_ call this UNII 3 */
95 CHAN5G(5745, 33), /* Channel 149 */
96 CHAN5G(5765, 34), /* Channel 153 */
97 CHAN5G(5785, 35), /* Channel 157 */
98 CHAN5G(5805, 36), /* Channel 161 */
99 CHAN5G(5825, 37), /* Channel 165 */
100};
101
ce111bad
LR		 102static void ath_cache_conf_rate(struct ath_softc *sc,
103 struct ieee80211_conf *conf)
ff37e337 104{
030bb495
LR		 105 switch (conf->channel->band) {
106 case IEEE80211_BAND_2GHZ:
107 if (conf_is_ht20(conf))
108 sc->cur_rate_table =
109 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
110 else if (conf_is_ht40_minus(conf))
111 sc->cur_rate_table =
112 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
113 else if (conf_is_ht40_plus(conf))
114 sc->cur_rate_table =
115 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 116 else
030bb495
LR		 117 sc->cur_rate_table =
118 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 119 break;
120 case IEEE80211_BAND_5GHZ:
121 if (conf_is_ht20(conf))
122 sc->cur_rate_table =
123 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
124 else if (conf_is_ht40_minus(conf))
125 sc->cur_rate_table =
126 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
127 else if (conf_is_ht40_plus(conf))
128 sc->cur_rate_table =
129 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
130 else
96742256
LR		 131 sc->cur_rate_table =
132 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 133 break;
134 default:
ce111bad 135 BUG_ON(1);
030bb495
LR		 136 break;
137 }
ff37e337
S		 138}
139
140static void ath_update_txpow(struct ath_softc *sc)
141{
cbe61d8a 142 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 143 u32 txpow;
144
17d7904d
S		 145 if (sc->curtxpow != sc->config.txpowlimit) {
146 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S		 147 /* read back in case value is clamped */
148 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 149 sc->curtxpow = txpow;
ff37e337
S		 150 }
151}
152
153static u8 parse_mpdudensity(u8 mpdudensity)
154{
155 /*
156 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
157 * 0 for no restriction
158 * 1 for 1/4 us
159 * 2 for 1/2 us
160 * 3 for 1 us
161 * 4 for 2 us
162 * 5 for 4 us
163 * 6 for 8 us
164 * 7 for 16 us
165 */
166 switch (mpdudensity) {
167 case 0:
168 return 0;
169 case 1:
170 case 2:
171 case 3:
172 /* Our lower layer calculations limit our precision to
173 1 microsecond */
174 return 1;
175 case 4:
176 return 2;
177 case 5:
178 return 4;
179 case 6:
180 return 8;
181 case 7:
182 return 16;
183 default:
184 return 0;
185 }
186}
187
188static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
189{
4f0fc7c3 190 const struct ath_rate_table *rate_table = NULL;
ff37e337
S		 191 struct ieee80211_supported_band *sband;
192 struct ieee80211_rate *rate;
193 int i, maxrates;
194
195 switch (band) {
196 case IEEE80211_BAND_2GHZ:
197 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
198 break;
199 case IEEE80211_BAND_5GHZ:
200 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
201 break;
202 default:
203 break;
204 }
205
206 if (rate_table == NULL)
207 return;
208
209 sband = &sc->sbands[band];
210 rate = sc->rates[band];
211
212 if (rate_table->rate_cnt > ATH_RATE_MAX)
213 maxrates = ATH_RATE_MAX;
214 else
215 maxrates = rate_table->rate_cnt;
216
217 for (i = 0; i < maxrates; i++) {
218 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
219 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 220 if (rate_table->info[i].short_preamble) {
221 rate[i].hw_value_short = rate_table->info[i].ratecode |
222 rate_table->info[i].short_preamble;
223 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
224 }
ff37e337 225 sband->n_bitrates++;
f46730d1 226
04bd4638
S		 227 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
228 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 229 }
230}
231
82880a7c
VT		 232static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
233 struct ieee80211_hw *hw)
234{
235 struct ieee80211_channel *curchan = hw->conf.channel;
236 struct ath9k_channel *channel;
237 u8 chan_idx;
238
239 chan_idx = curchan->hw_value;
240 channel = &sc->sc_ah->channels[chan_idx];
241 ath9k_update_ichannel(sc, hw, channel);
242 return channel;
243}
244
ff37e337
S		 245/*
246 * Set/change channels. If the channel is really being changed, it's done
247 * by reseting the chip. To accomplish this we must first cleanup any pending
248 * DMA, then restart stuff.
249*/
0e2dedf9
JM		 250int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
251 struct ath9k_channel *hchan)
ff37e337 252{
cbe61d8a 253 struct ath_hw *ah = sc->sc_ah;
ff37e337 254 bool fastcc = true, stopped;
ae8d2858
LR		 255 struct ieee80211_channel *channel = hw->conf.channel;
256 int r;
ff37e337
S		 257
258 if (sc->sc_flags & SC_OP_INVALID)
259 return -EIO;
260
3cbb5dd7
VN		 261 ath9k_ps_wakeup(sc);
262
c0d7c7af
LR		 263 /*
264 * This is only performed if the channel settings have
265 * actually changed.
266 *
267 * To switch channels clear any pending DMA operations;
268 * wait long enough for the RX fifo to drain, reset the
269 * hardware at the new frequency, and then re-enable
270 * the relevant bits of the h/w.
271 */
272 ath9k_hw_set_interrupts(ah, 0);
043a0405 273 ath_drain_all_txq(sc, false);
c0d7c7af 274 stopped = ath_stoprecv(sc);
ff37e337 275
c0d7c7af
LR		 276 /* XXX: do not flush receive queue here. We don't want
277 * to flush data frames already in queue because of
278 * changing channel. */
ff37e337 279
c0d7c7af
LR		 280 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
281 fastcc = false;
282
283 DPRINTF(sc, ATH_DBG_CONFIG,
284 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
2660b81a 285 sc->sc_ah->curchan->channel,
c0d7c7af 286 channel->center_freq, sc->tx_chan_width);
ff37e337 287
c0d7c7af
LR		 288 spin_lock_bh(&sc->sc_resetlock);
289
290 r = ath9k_hw_reset(ah, hchan, fastcc);
291 if (r) {
292 DPRINTF(sc, ATH_DBG_FATAL,
293 "Unable to reset channel (%u Mhz) "
6b45784f 294 "reset status %d\n",
c0d7c7af
LR		 295 channel->center_freq, r);
296 spin_unlock_bh(&sc->sc_resetlock);
3989279c 297 goto ps_restore;
ff37e337 298 }
c0d7c7af
LR		 299 spin_unlock_bh(&sc->sc_resetlock);
300
c0d7c7af
LR		 301 sc->sc_flags &= ~SC_OP_FULL_RESET;
302
303 if (ath_startrecv(sc) != 0) {
304 DPRINTF(sc, ATH_DBG_FATAL,
305 "Unable to restart recv logic\n");
3989279c
GJ		 306 r = -EIO;
307 goto ps_restore;
c0d7c7af
LR		 308 }
309
310 ath_cache_conf_rate(sc, &hw->conf);
311 ath_update_txpow(sc);
17d7904d 312 ath9k_hw_set_interrupts(ah, sc->imask);
3989279c
GJ		 313
314 ps_restore:
3cbb5dd7 315 ath9k_ps_restore(sc);
3989279c 316 return r;
ff37e337
S		 317}
318
319/*
320 * This routine performs the periodic noise floor calibration function
321 * that is used to adjust and optimize the chip performance. This
322 * takes environmental changes (location, temperature) into account.
323 * When the task is complete, it reschedules itself depending on the
324 * appropriate interval that was calculated.
325 */
326static void ath_ani_calibrate(unsigned long data)
327{
20977d3e
S		 328 struct ath_softc *sc = (struct ath_softc *)data;
329 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 330 bool longcal = false;
331 bool shortcal = false;
332 bool aniflag = false;
333 unsigned int timestamp = jiffies_to_msecs(jiffies);
20977d3e 334 u32 cal_interval, short_cal_interval;
ff37e337 335
20977d3e
S		 336 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
337 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337
S		 338
339 /*
340 * don't calibrate when we're scanning.
341 * we are most likely not on our home channel.
342 */
e5f0921a 343 spin_lock(&sc->ani_lock);
0c98de65 344 if (sc->sc_flags & SC_OP_SCANNING)
20977d3e 345 goto set_timer;
ff37e337 346
1ffc1c61
JM		 347 /* Only calibrate if awake */
348 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
349 goto set_timer;
350
351 ath9k_ps_wakeup(sc);
352
ff37e337 353 /* Long calibration runs independently of short calibration. */
17d7904d 354 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 355 longcal = true;
04bd4638 356 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
17d7904d 357 sc->ani.longcal_timer = timestamp;
ff37e337
S		 358 }
359
17d7904d
S		 360 /* Short calibration applies only while caldone is false */
361 if (!sc->ani.caldone) {
20977d3e 362 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 363 shortcal = true;
04bd4638 364 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
17d7904d
S		 365 sc->ani.shortcal_timer = timestamp;
366 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 367 }
368 } else {
17d7904d 369 if ((timestamp - sc->ani.resetcal_timer) >=
ff37e337 370 ATH_RESTART_CALINTERVAL) {
17d7904d
S		 371 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
372 if (sc->ani.caldone)
373 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 374 }
375 }
376
377 /* Verify whether we must check ANI */
20977d3e 378 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
ff37e337 379 aniflag = true;
17d7904d 380 sc->ani.checkani_timer = timestamp;
ff37e337
S		 381 }
382
383 /* Skip all processing if there's nothing to do. */
384 if (longcal || shortcal || aniflag) {
385 /* Call ANI routine if necessary */
386 if (aniflag)
22e66a4c 387 ath9k_hw_ani_monitor(ah, ah->curchan);
ff37e337
S		 388
389 /* Perform calibration if necessary */
390 if (longcal || shortcal) {
379f0440
S		 391 sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
392 sc->rx_chainmask, longcal);
393
394 if (longcal)
395 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
396 ah->curchan);
397
398 DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
399 ah->curchan->channel, ah->curchan->channelFlags,
400 sc->ani.noise_floor);
ff37e337
S		 401 }
402 }
403
1ffc1c61
JM		 404 ath9k_ps_restore(sc);
405
20977d3e 406set_timer:
e5f0921a 407 spin_unlock(&sc->ani_lock);
ff37e337
S		 408 /*
409 * Set timer interval based on previous results.
410 * The interval must be the shortest necessary to satisfy ANI,
411 * short calibration and long calibration.
412 */
aac9207e 413 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 414 if (sc->sc_ah->config.enable_ani)
aac9207e 415 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
17d7904d 416 if (!sc->ani.caldone)
20977d3e 417 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 418
17d7904d 419 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S		 420}
421
415f738e
S		 422static void ath_start_ani(struct ath_softc *sc)
423{
424 unsigned long timestamp = jiffies_to_msecs(jiffies);
425
426 sc->ani.longcal_timer = timestamp;
427 sc->ani.shortcal_timer = timestamp;
428 sc->ani.checkani_timer = timestamp;
429
430 mod_timer(&sc->ani.timer,
431 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
432}
433
ff37e337
S		 434/*
435 * Update tx/rx chainmask. For legacy association,
436 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 437 * the chainmask configuration, for bt coexistence, use
438 * the chainmask configuration even in legacy mode.
ff37e337 439 */
0e2dedf9 440void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337 441{
3d832611 442 if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
81fa16fb 443 (sc->btcoex_info.btcoex_scheme != ATH_BTCOEX_CFG_NONE)) {
2660b81a
S		 444 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
445 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
ff37e337 446 } else {
17d7904d
S		 447 sc->tx_chainmask = 1;
448 sc->rx_chainmask = 1;
ff37e337
S		 449 }
450
04bd4638 451 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
17d7904d 452 sc->tx_chainmask, sc->rx_chainmask);
ff37e337
S		 453}
454
455static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
456{
457 struct ath_node *an;
458
459 an = (struct ath_node *)sta->drv_priv;
460
87792efc 461 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 462 ath_tx_node_init(sc, an);
9e98ac65 463 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S		 464 sta->ht_cap.ampdu_factor);
465 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
a59b5a5e 466 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
87792efc 467 }
ff37e337
S		 468}
469
470static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
471{
472 struct ath_node *an = (struct ath_node *)sta->drv_priv;
473
474 if (sc->sc_flags & SC_OP_TXAGGR)
475 ath_tx_node_cleanup(sc, an);
476}
477
478static void ath9k_tasklet(unsigned long data)
479{
480 struct ath_softc *sc = (struct ath_softc *)data;
17d7904d 481 u32 status = sc->intrstatus;
ff37e337 482
153e080d
VT		 483 ath9k_ps_wakeup(sc);
484
ff37e337 485 if (status & ATH9K_INT_FATAL) {
ff37e337 486 ath_reset(sc, false);
153e080d 487 ath9k_ps_restore(sc);
ff37e337 488 return;
063d8be3 489 }
ff37e337 490
063d8be3
S		 491 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
492 spin_lock_bh(&sc->rx.rxflushlock);
493 ath_rx_tasklet(sc, 0);
494 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 495 }
496
063d8be3
S		 497 if (status & ATH9K_INT_TX)
498 ath_tx_tasklet(sc);
499
96148326 500 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
54ce846e
JM		 501 /*
502 * TSF sync does not look correct; remain awake to sync with
503 * the next Beacon.
504 */
505 DPRINTF(sc, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
ccdfeab6 506 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
54ce846e
JM		 507 }
508
ff37e337 509 /* re-enable hardware interrupt */
17d7904d 510 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
153e080d 511 ath9k_ps_restore(sc);
ff37e337
S		 512}
513
6baff7f9 514irqreturn_t ath_isr(int irq, void *dev)
ff37e337 515{
063d8be3
S		 516#define SCHED_INTR ( \
517 ATH9K_INT_FATAL | \
518 ATH9K_INT_RXORN | \
519 ATH9K_INT_RXEOL | \
520 ATH9K_INT_RX | \
521 ATH9K_INT_TX | \
522 ATH9K_INT_BMISS | \
523 ATH9K_INT_CST | \
524 ATH9K_INT_TSFOOR)
525
ff37e337 526 struct ath_softc *sc = dev;
cbe61d8a 527 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 528 enum ath9k_int status;
529 bool sched = false;
530
063d8be3
S		 531 /*
532 * The hardware is not ready/present, don't
533 * touch anything. Note this can happen early
534 * on if the IRQ is shared.
535 */
536 if (sc->sc_flags & SC_OP_INVALID)
537 return IRQ_NONE;
ff37e337 538
063d8be3
S		 539
540 /* shared irq, not for us */
541
153e080d 542 if (!ath9k_hw_intrpend(ah))
063d8be3 543 return IRQ_NONE;
063d8be3
S		 544
545 /*
546 * Figure out the reason(s) for the interrupt. Note
547 * that the hal returns a pseudo-ISR that may include
548 * bits we haven't explicitly enabled so we mask the
549 * value to insure we only process bits we requested.
550 */
551 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
552 status &= sc->imask; /* discard unasked-for bits */
ff37e337 553
063d8be3
S		 554 /*
555 * If there are no status bits set, then this interrupt was not
556 * for me (should have been caught above).
557 */
153e080d 558 if (!status)
063d8be3 559 return IRQ_NONE;
ff37e337 560
063d8be3
S		 561 /* Cache the status */
562 sc->intrstatus = status;
563
564 if (status & SCHED_INTR)
565 sched = true;
566
567 /*
568 * If a FATAL or RXORN interrupt is received, we have to reset the
569 * chip immediately.
570 */
571 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
572 goto chip_reset;
573
574 if (status & ATH9K_INT_SWBA)
575 tasklet_schedule(&sc->bcon_tasklet);
576
577 if (status & ATH9K_INT_TXURN)
578 ath9k_hw_updatetxtriglevel(ah, true);
579
580 if (status & ATH9K_INT_MIB) {
ff37e337 581 /*
063d8be3
S		 582 * Disable interrupts until we service the MIB
583 * interrupt; otherwise it will continue to
584 * fire.
ff37e337 585 */
063d8be3
S		 586 ath9k_hw_set_interrupts(ah, 0);
587 /*
588 * Let the hal handle the event. We assume
589 * it will clear whatever condition caused
590 * the interrupt.
591 */
22e66a4c 592 ath9k_hw_procmibevent(ah);
063d8be3
S		 593 ath9k_hw_set_interrupts(ah, sc->imask);
594 }
ff37e337 595
153e080d
VT		 596 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
597 if (status & ATH9K_INT_TIM_TIMER) {
063d8be3
S		 598 /* Clear RxAbort bit so that we can
599 * receive frames */
600 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
153e080d 601 ath9k_hw_setrxabort(sc->sc_ah, 0);
063d8be3 602 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337 603 }
063d8be3
S		 604
605chip_reset:
ff37e337 606
817e11de
S		 607 ath_debug_stat_interrupt(sc, status);
608
ff37e337
S		 609 if (sched) {
610 /* turn off every interrupt except SWBA */
17d7904d 611 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S		 612 tasklet_schedule(&sc->intr_tq);
613 }
614
615 return IRQ_HANDLED;
063d8be3
S		 616
617#undef SCHED_INTR
ff37e337
S		 618}
619
f078f209 620static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 621 struct ieee80211_channel *chan,
094d05dc 622 enum nl80211_channel_type channel_type)
f078f209
LR		 623{
624 u32 chanmode = 0;
f078f209
LR		 625
626 switch (chan->band) {
627 case IEEE80211_BAND_2GHZ:
094d05dc
S		 628 switch(channel_type) {
629 case NL80211_CHAN_NO_HT:
630 case NL80211_CHAN_HT20:
f078f209 631 chanmode = CHANNEL_G_HT20;
094d05dc
S		 632 break;
633 case NL80211_CHAN_HT40PLUS:
f078f209 634 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 635 break;
636 case NL80211_CHAN_HT40MINUS:
f078f209 637 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 638 break;
639 }
f078f209
LR		 640 break;
641 case IEEE80211_BAND_5GHZ:
094d05dc
S		 642 switch(channel_type) {
643 case NL80211_CHAN_NO_HT:
644 case NL80211_CHAN_HT20:
f078f209 645 chanmode = CHANNEL_A_HT20;
094d05dc
S		 646 break;
647 case NL80211_CHAN_HT40PLUS:
f078f209 648 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 649 break;
650 case NL80211_CHAN_HT40MINUS:
f078f209 651 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 652 break;
653 }
f078f209
LR		 654 break;
655 default:
656 break;
657 }
658
659 return chanmode;
660}
661
6ace2891 662static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
3f53dd64
JM		 663 struct ath9k_keyval *hk, const u8 *addr,
664 bool authenticator)
f078f209 665{
6ace2891
JM		 666 const u8 *key_rxmic;
667 const u8 *key_txmic;
f078f209 668
6ace2891
JM		 669 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
670 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 671
672 if (addr == NULL) {
d216aaa6
JM		 673 /*
674 * Group key installation - only two key cache entries are used
675 * regardless of splitmic capability since group key is only
676 * used either for TX or RX.
677 */
3f53dd64
JM		 678 if (authenticator) {
679 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
680 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
681 } else {
682 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
683 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
684 }
d216aaa6 685 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 686 }
17d7904d 687 if (!sc->splitmic) {
d216aaa6 688 /* TX and RX keys share the same key cache entry. */
f078f209
LR		 689 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
690 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
d216aaa6 691 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 692 }
d216aaa6
JM		 693
694 /* Separate key cache entries for TX and RX */
695
696 /* TX key goes at first index, RX key at +32. */
f078f209 697 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
d216aaa6
JM		 698 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
699 /* TX MIC entry failed. No need to proceed further */
d8baa939 700 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 701 "Setting TX MIC Key Failed\n");
f078f209
LR		 702 return 0;
703 }
704
705 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
706 /* XXX delete tx key on failure? */
d216aaa6 707 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
6ace2891
JM		 708}
709
710static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
711{
712 int i;
713
17d7904d
S		 714 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
715 if (test_bit(i, sc->keymap) ||
716 test_bit(i + 64, sc->keymap))
6ace2891 717 continue; /* At least one part of TKIP key allocated */
17d7904d
S		 718 if (sc->splitmic &&
719 (test_bit(i + 32, sc->keymap) ||
720 test_bit(i + 64 + 32, sc->keymap)))
6ace2891
JM		 721 continue; /* At least one part of TKIP key allocated */
722
723 /* Found a free slot for a TKIP key */
724 return i;
725 }
726 return -1;
727}
728
729static int ath_reserve_key_cache_slot(struct ath_softc *sc)
730{
731 int i;
732
733 /* First, try to find slots that would not be available for TKIP. */
17d7904d
S		 734 if (sc->splitmic) {
735 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
736 if (!test_bit(i, sc->keymap) &&
737 (test_bit(i + 32, sc->keymap) ||
738 test_bit(i + 64, sc->keymap) ||
739 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 740 return i;
17d7904d
S		 741 if (!test_bit(i + 32, sc->keymap) &&
742 (test_bit(i, sc->keymap) ||
743 test_bit(i + 64, sc->keymap) ||
744 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 745 return i + 32;
17d7904d
S		 746 if (!test_bit(i + 64, sc->keymap) &&
747 (test_bit(i , sc->keymap) ||
748 test_bit(i + 32, sc->keymap) ||
749 test_bit(i + 64 + 32, sc->keymap)))
ea612132 750 return i + 64;
17d7904d
S		 751 if (!test_bit(i + 64 + 32, sc->keymap) &&
752 (test_bit(i, sc->keymap) ||
753 test_bit(i + 32, sc->keymap) ||
754 test_bit(i + 64, sc->keymap)))
ea612132 755 return i + 64 + 32;
6ace2891
JM		 756 }
757 } else {
17d7904d
S		 758 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
759 if (!test_bit(i, sc->keymap) &&
760 test_bit(i + 64, sc->keymap))
6ace2891 761 return i;
17d7904d
S		 762 if (test_bit(i, sc->keymap) &&
763 !test_bit(i + 64, sc->keymap))
6ace2891
JM		 764 return i + 64;
765 }
766 }
767
768 /* No partially used TKIP slots, pick any available slot */
17d7904d 769 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
be2864cf
JM		 770 /* Do not allow slots that could be needed for TKIP group keys
771 * to be used. This limitation could be removed if we know that
772 * TKIP will not be used. */
773 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
774 continue;
17d7904d 775 if (sc->splitmic) {
be2864cf
JM		 776 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
777 continue;
778 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
779 continue;
780 }
781
17d7904d 782 if (!test_bit(i, sc->keymap))
6ace2891
JM		 783 return i; /* Found a free slot for a key */
784 }
785
786 /* No free slot found */
787 return -1;
f078f209
LR		 788}
789
790static int ath_key_config(struct ath_softc *sc,
3f53dd64 791 struct ieee80211_vif *vif,
dc822b5d 792 struct ieee80211_sta *sta,
f078f209
LR		 793 struct ieee80211_key_conf *key)
794{
f078f209
LR		 795 struct ath9k_keyval hk;
796 const u8 *mac = NULL;
797 int ret = 0;
6ace2891 798 int idx;
f078f209
LR		 799
800 memset(&hk, 0, sizeof(hk));
801
802 switch (key->alg) {
803 case ALG_WEP:
804 hk.kv_type = ATH9K_CIPHER_WEP;
805 break;
806 case ALG_TKIP:
807 hk.kv_type = ATH9K_CIPHER_TKIP;
808 break;
809 case ALG_CCMP:
810 hk.kv_type = ATH9K_CIPHER_AES_CCM;
811 break;
812 default:
ca470b29 813 return -EOPNOTSUPP;
f078f209
LR		 814 }
815
6ace2891 816 hk.kv_len = key->keylen;
f078f209
LR		 817 memcpy(hk.kv_val, key->key, key->keylen);
818
6ace2891
JM		 819 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
820 /* For now, use the default keys for broadcast keys. This may
821 * need to change with virtual interfaces. */
822 idx = key->keyidx;
823 } else if (key->keyidx) {
dc822b5d
JB		 824 if (WARN_ON(!sta))
825 return -EOPNOTSUPP;
826 mac = sta->addr;
827
6ace2891
JM		 828 if (vif->type != NL80211_IFTYPE_AP) {
829 /* Only keyidx 0 should be used with unicast key, but
830 * allow this for client mode for now. */
831 idx = key->keyidx;
832 } else
833 return -EIO;
f078f209 834 } else {
dc822b5d
JB		 835 if (WARN_ON(!sta))
836 return -EOPNOTSUPP;
837 mac = sta->addr;
838
6ace2891
JM		 839 if (key->alg == ALG_TKIP)
840 idx = ath_reserve_key_cache_slot_tkip(sc);
841 else
842 idx = ath_reserve_key_cache_slot(sc);
843 if (idx < 0)
ca470b29 844 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 845 }
846
847 if (key->alg == ALG_TKIP)
3f53dd64
JM		 848 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
849 vif->type == NL80211_IFTYPE_AP);
f078f209 850 else
d216aaa6 851 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
f078f209
LR		 852
853 if (!ret)
854 return -EIO;
855
17d7904d 856 set_bit(idx, sc->keymap);
6ace2891 857 if (key->alg == ALG_TKIP) {
17d7904d
S		 858 set_bit(idx + 64, sc->keymap);
859 if (sc->splitmic) {
860 set_bit(idx + 32, sc->keymap);
861 set_bit(idx + 64 + 32, sc->keymap);
6ace2891
JM		 862 }
863 }
864
865 return idx;
f078f209
LR		 866}
867
868static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
869{
6ace2891
JM		 870 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
871 if (key->hw_key_idx < IEEE80211_WEP_NKID)
872 return;
873
17d7904d 874 clear_bit(key->hw_key_idx, sc->keymap);
6ace2891
JM		 875 if (key->alg != ALG_TKIP)
876 return;
f078f209 877
17d7904d
S		 878 clear_bit(key->hw_key_idx + 64, sc->keymap);
879 if (sc->splitmic) {
880 clear_bit(key->hw_key_idx + 32, sc->keymap);
881 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
6ace2891 882 }
f078f209
LR		 883}
884
eb2599ca
S		 885static void setup_ht_cap(struct ath_softc *sc,
886 struct ieee80211_sta_ht_cap *ht_info)
f078f209 887{
140add21 888 u8 tx_streams, rx_streams;
f078f209 889
d9fe60de
JB		 890 ht_info->ht_supported = true;
891 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
892 IEEE80211_HT_CAP_SM_PS |
893 IEEE80211_HT_CAP_SGI_40 |
894 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 895
9e98ac65
S		 896 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
897 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
eb2599ca 898
d9fe60de
JB		 899 /* set up supported mcs set */
900 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
140add21
SB		 901 tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2;
902 rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;
903
904 if (tx_streams != rx_streams) {
905 DPRINTF(sc, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n",
906 tx_streams, rx_streams);
907 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
908 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
909 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
910 }
eb2599ca 911
140add21
SB		 912 ht_info->mcs.rx_mask[0] = 0xff;
913 if (rx_streams >= 2)
eb2599ca 914 ht_info->mcs.rx_mask[1] = 0xff;
eb2599ca 915
140add21 916 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 917}
918
8feceb67 919static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 920 struct ieee80211_vif *vif,
8feceb67 921 struct ieee80211_bss_conf *bss_conf)
f078f209 922{
f078f209 923
8feceb67 924 if (bss_conf->assoc) {
094d05dc 925 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
17d7904d 926 bss_conf->aid, sc->curbssid);
f078f209 927
8feceb67 928 /* New association, store aid */
2664f201
SB		 929 sc->curaid = bss_conf->aid;
930 ath9k_hw_write_associd(sc);
931
932 /*
933 * Request a re-configuration of Beacon related timers
934 * on the receipt of the first Beacon frame (i.e.,
935 * after time sync with the AP).
936 */
937 sc->sc_flags |= SC_OP_BEACON_SYNC;
f078f209 938
8feceb67 939 /* Configure the beacon */
2c3db3d5 940 ath_beacon_config(sc, vif);
f078f209 941
8feceb67 942 /* Reset rssi stats */
22e66a4c 943 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
f078f209 944
415f738e 945 ath_start_ani(sc);
8feceb67 946 } else {
1ffb0610 947 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
17d7904d 948 sc->curaid = 0;
f38faa31
SB		 949 /* Stop ANI */
950 del_timer_sync(&sc->ani.timer);
f078f209 951 }
8feceb67 952}
f078f209 953
8feceb67
VT		 954/********************************/
955/* LED functions */
956/********************************/
f078f209 957
f2bffa7e
VT		 958static void ath_led_blink_work(struct work_struct *work)
959{
960 struct ath_softc *sc = container_of(work, struct ath_softc,
961 ath_led_blink_work.work);
962
963 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
964 return;
85067c06
VT		 965
966 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
967 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
08fc5c1b 968 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
85067c06 969 else
08fc5c1b 970 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
85067c06 971 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
f2bffa7e 972
42935eca
LR		 973 ieee80211_queue_delayed_work(sc->hw,
974 &sc->ath_led_blink_work,
975 (sc->sc_flags & SC_OP_LED_ON) ?
976 msecs_to_jiffies(sc->led_off_duration) :
977 msecs_to_jiffies(sc->led_on_duration));
f2bffa7e 978
85067c06
VT		 979 sc->led_on_duration = sc->led_on_cnt ?
980 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
981 ATH_LED_ON_DURATION_IDLE;
982 sc->led_off_duration = sc->led_off_cnt ?
983 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
984 ATH_LED_OFF_DURATION_IDLE;
f2bffa7e
VT		 985 sc->led_on_cnt = sc->led_off_cnt = 0;
986 if (sc->sc_flags & SC_OP_LED_ON)
987 sc->sc_flags &= ~SC_OP_LED_ON;
988 else
989 sc->sc_flags |= SC_OP_LED_ON;
990}
991
8feceb67
VT		 992static void ath_led_brightness(struct led_classdev *led_cdev,
993 enum led_brightness brightness)
994{
995 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
996 struct ath_softc *sc = led->sc;
f078f209 997
8feceb67
VT		 998 switch (brightness) {
999 case LED_OFF:
1000 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e 1001 led->led_type == ATH_LED_RADIO) {
08fc5c1b 1002 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
f2bffa7e 1003 (led->led_type == ATH_LED_RADIO));
8feceb67 1004 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 1005 if (led->led_type == ATH_LED_RADIO)
1006 sc->sc_flags &= ~SC_OP_LED_ON;
1007 } else {
1008 sc->led_off_cnt++;
1009 }
8feceb67
VT		 1010 break;
1011 case LED_FULL:
f2bffa7e 1012 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 1013 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
42935eca
LR		 1014 ieee80211_queue_delayed_work(sc->hw,
1015 &sc->ath_led_blink_work, 0);
f2bffa7e 1016 } else if (led->led_type == ATH_LED_RADIO) {
08fc5c1b 1017 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
f2bffa7e
VT		 1018 sc->sc_flags |= SC_OP_LED_ON;
1019 } else {
1020 sc->led_on_cnt++;
1021 }
8feceb67
VT		 1022 break;
1023 default:
1024 break;
f078f209 1025 }
8feceb67 1026}
f078f209 1027
8feceb67
VT		 1028static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1029 char *trigger)
1030{
1031 int ret;
f078f209 1032
8feceb67
VT		 1033 led->sc = sc;
1034 led->led_cdev.name = led->name;
1035 led->led_cdev.default_trigger = trigger;
1036 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 1037
8feceb67
VT		 1038 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1039 if (ret)
1040 DPRINTF(sc, ATH_DBG_FATAL,
1041 "Failed to register led:%s", led->name);
1042 else
1043 led->registered = 1;
1044 return ret;
1045}
f078f209 1046
8feceb67
VT		 1047static void ath_unregister_led(struct ath_led *led)
1048{
1049 if (led->registered) {
1050 led_classdev_unregister(&led->led_cdev);
1051 led->registered = 0;
f078f209 1052 }
f078f209
LR		 1053}
1054
8feceb67 1055static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1056{
8feceb67
VT		 1057 ath_unregister_led(&sc->assoc_led);
1058 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1059 ath_unregister_led(&sc->tx_led);
1060 ath_unregister_led(&sc->rx_led);
1061 ath_unregister_led(&sc->radio_led);
08fc5c1b 1062 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
8feceb67 1063}
f078f209 1064
8feceb67
VT		 1065static void ath_init_leds(struct ath_softc *sc)
1066{
1067 char *trigger;
1068 int ret;
f078f209 1069
08fc5c1b
VN		 1070 if (AR_SREV_9287(sc->sc_ah))
1071 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
1072 else
1073 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
1074
8feceb67 1075 /* Configure gpio 1 for output */
08fc5c1b 1076 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
8feceb67
VT		 1077 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1078 /* LED off, active low */
08fc5c1b 1079 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
7dcfdcd9 1080
f2bffa7e
VT		 1081 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1082
8feceb67
VT		 1083 trigger = ieee80211_get_radio_led_name(sc->hw);
1084 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
0818cb8a 1085 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1086 ret = ath_register_led(sc, &sc->radio_led, trigger);
1087 sc->radio_led.led_type = ATH_LED_RADIO;
1088 if (ret)
1089 goto fail;
7dcfdcd9 1090
8feceb67
VT		 1091 trigger = ieee80211_get_assoc_led_name(sc->hw);
1092 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
0818cb8a 1093 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1094 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1095 sc->assoc_led.led_type = ATH_LED_ASSOC;
1096 if (ret)
1097 goto fail;
f078f209 1098
8feceb67
VT		 1099 trigger = ieee80211_get_tx_led_name(sc->hw);
1100 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
0818cb8a 1101 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1102 ret = ath_register_led(sc, &sc->tx_led, trigger);
1103 sc->tx_led.led_type = ATH_LED_TX;
1104 if (ret)
1105 goto fail;
f078f209 1106
8feceb67
VT		 1107 trigger = ieee80211_get_rx_led_name(sc->hw);
1108 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
0818cb8a 1109 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1110 ret = ath_register_led(sc, &sc->rx_led, trigger);
1111 sc->rx_led.led_type = ATH_LED_RX;
1112 if (ret)
1113 goto fail;
f078f209 1114
8feceb67
VT		 1115 return;
1116
1117fail:
35c95ab9 1118 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67 1119 ath_deinit_leds(sc);
f078f209
LR		 1120}
1121
7ec3e514 1122void ath_radio_enable(struct ath_softc *sc)
500c064d 1123{
cbe61d8a 1124 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1125 struct ieee80211_channel *channel = sc->hw->conf.channel;
1126 int r;
500c064d 1127
3cbb5dd7 1128 ath9k_ps_wakeup(sc);
d2f5b3a6 1129 ath9k_hw_configpcipowersave(ah, 0);
ae8d2858 1130
159cd468
VT		 1131 if (!ah->curchan)
1132 ah->curchan = ath_get_curchannel(sc, sc->hw);
1133
d2f5b3a6 1134 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1135 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1136 if (r) {
500c064d 1137 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1138 "Unable to reset channel %u (%uMhz) ",
6b45784f 1139 "reset status %d\n",
ae8d2858 1140 channel->center_freq, r);
500c064d
VT		 1141 }
1142 spin_unlock_bh(&sc->sc_resetlock);
1143
1144 ath_update_txpow(sc);
1145 if (ath_startrecv(sc) != 0) {
1146 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1147 "Unable to restart recv logic\n");
500c064d
VT		 1148 return;
1149 }
1150
1151 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1152 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT		 1153
1154 /* Re-Enable interrupts */
17d7904d 1155 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT		 1156
1157 /* Enable LED */
08fc5c1b 1158 ath9k_hw_cfg_output(ah, ah->led_pin,
500c064d 1159 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b 1160 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
500c064d
VT		 1161
1162 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1163 ath9k_ps_restore(sc);
500c064d
VT		 1164}
1165
7ec3e514 1166void ath_radio_disable(struct ath_softc *sc)
500c064d 1167{
cbe61d8a 1168 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1169 struct ieee80211_channel *channel = sc->hw->conf.channel;
1170 int r;
500c064d 1171
3cbb5dd7 1172 ath9k_ps_wakeup(sc);
500c064d
VT		 1173 ieee80211_stop_queues(sc->hw);
1174
1175 /* Disable LED */
08fc5c1b
VN		 1176 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1177 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
500c064d
VT		 1178
1179 /* Disable interrupts */
1180 ath9k_hw_set_interrupts(ah, 0);
1181
043a0405 1182 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1183 ath_stoprecv(sc); /* turn off frame recv */
1184 ath_flushrecv(sc); /* flush recv queue */
1185
159cd468
VT		 1186 if (!ah->curchan)
1187 ah->curchan = ath_get_curchannel(sc, sc->hw);
1188
500c064d 1189 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1190 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1191 if (r) {
500c064d 1192 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1193 "Unable to reset channel %u (%uMhz) "
6b45784f 1194 "reset status %d\n",
ae8d2858 1195 channel->center_freq, r);
500c064d
VT		 1196 }
1197 spin_unlock_bh(&sc->sc_resetlock);
1198
1199 ath9k_hw_phy_disable(ah);
d2f5b3a6 1200 ath9k_hw_configpcipowersave(ah, 1);
3cbb5dd7 1201 ath9k_ps_restore(sc);
38ab422e 1202 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
500c064d
VT		 1203}
1204
5077fd35
GJ		 1205/*******************/
1206/* Rfkill */
1207/*******************/
1208
500c064d
VT		 1209static bool ath_is_rfkill_set(struct ath_softc *sc)
1210{
cbe61d8a 1211 struct ath_hw *ah = sc->sc_ah;
500c064d 1212
2660b81a
S		 1213 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1214 ah->rfkill_polarity;
500c064d
VT		 1215}
1216
3b319aae 1217static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
500c064d 1218{
3b319aae
JB		 1219 struct ath_wiphy *aphy = hw->priv;
1220 struct ath_softc *sc = aphy->sc;
19d337df 1221 bool blocked = !!ath_is_rfkill_set(sc);
500c064d 1222
3b319aae
JB		 1223 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1224
1225 if (blocked)
19d337df
JB		 1226 ath_radio_disable(sc);
1227 else
1228 ath_radio_enable(sc);
500c064d
VT		 1229}
1230
3b319aae 1231static void ath_start_rfkill_poll(struct ath_softc *sc)
500c064d 1232{
3b319aae 1233 struct ath_hw *ah = sc->sc_ah;
9c84b797 1234
3b319aae
JB		 1235 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1236 wiphy_rfkill_start_polling(sc->hw->wiphy);
9c84b797 1237}
500c064d 1238
6baff7f9 1239void ath_cleanup(struct ath_softc *sc)
39c3c2f2
GJ		 1240{
1241 ath_detach(sc);
1242 free_irq(sc->irq, sc);
1243 ath_bus_cleanup(sc);
c52f33d0 1244 kfree(sc->sec_wiphy);
39c3c2f2
GJ		 1245 ieee80211_free_hw(sc->hw);
1246}
1247
6baff7f9 1248void ath_detach(struct ath_softc *sc)
f078f209 1249{
8feceb67 1250 struct ieee80211_hw *hw = sc->hw;
9c84b797 1251 int i = 0;
f078f209 1252
3cbb5dd7
VN		 1253 ath9k_ps_wakeup(sc);
1254
04bd4638 1255 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1256
35c95ab9
LR		 1257 ath_deinit_leds(sc);
1258
c52f33d0
JM		 1259 for (i = 0; i < sc->num_sec_wiphy; i++) {
1260 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1261 if (aphy == NULL)
1262 continue;
1263 sc->sec_wiphy[i] = NULL;
1264 ieee80211_unregister_hw(aphy->hw);
1265 ieee80211_free_hw(aphy->hw);
1266 }
3fcdfb4b 1267 ieee80211_unregister_hw(hw);
8feceb67
VT		 1268 ath_rx_cleanup(sc);
1269 ath_tx_cleanup(sc);
f078f209 1270
9c84b797
S		 1271 tasklet_kill(&sc->intr_tq);
1272 tasklet_kill(&sc->bcon_tasklet);
f078f209 1273
9c84b797
S		 1274 if (!(sc->sc_flags & SC_OP_INVALID))
1275 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1276
9c84b797
S		 1277 /* cleanup tx queues */
1278 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1279 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1280 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797
S		 1281
1282 ath9k_hw_detach(sc->sc_ah);
3ce1b1a9 1283 sc->sc_ah = NULL;
826d2680 1284 ath9k_exit_debug(sc);
f078f209
LR		 1285}
1286
e3bb249b
BC		 1287static int ath9k_reg_notifier(struct wiphy *wiphy,
1288 struct regulatory_request *request)
1289{
1290 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1291 struct ath_wiphy *aphy = hw->priv;
1292 struct ath_softc *sc = aphy->sc;
608b88cb 1293 struct ath_regulatory *reg = &sc->common.regulatory;
e3bb249b
BC		 1294
1295 return ath_reg_notifier_apply(wiphy, request, reg);
1296}
1297
1e40bcfa
LR		 1298/*
1299 * Initialize and fill ath_softc, ath_sofct is the
1300 * "Software Carrier" struct. Historically it has existed
1301 * to allow the separation between hardware specific
1302 * variables (now in ath_hw) and driver specific variables.
1303 */
1304static int ath_init_softc(u16 devid, struct ath_softc *sc)
ff37e337 1305{
cbe61d8a 1306 struct ath_hw *ah = NULL;
4f3acf81 1307 int r = 0, i;
ff37e337
S		 1308 int csz = 0;
1309
1310 /* XXX: hardware will not be ready until ath_open() being called */
1311 sc->sc_flags |= SC_OP_INVALID;
88b126af 1312
826d2680
S		 1313 if (ath9k_init_debug(sc) < 0)
1314 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337 1315
c52f33d0 1316 spin_lock_init(&sc->wiphy_lock);
ff37e337 1317 spin_lock_init(&sc->sc_resetlock);
6158425b 1318 spin_lock_init(&sc->sc_serial_rw);
e5f0921a 1319 spin_lock_init(&sc->ani_lock);
04717ccd 1320 spin_lock_init(&sc->sc_pm_lock);
aa33de09 1321 mutex_init(&sc->mutex);
ff37e337 1322 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
9fc9ab0a 1323 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
ff37e337
S		 1324 (unsigned long)sc);
1325
1326 /*
1327 * Cache line size is used to size and align various
1328 * structures used to communicate with the hardware.
1329 */
88d15707 1330 ath_read_cachesize(sc, &csz);
ff37e337 1331 /* XXX assert csz is non-zero */
d15dd3e5 1332 sc->common.cachelsz = csz << 2; /* convert to bytes */
ff37e337 1333
4f3acf81
LR		 1334 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
1335 if (!ah) {
4f3acf81
LR		 1336 r = -ENOMEM;
1337 goto bad_no_ah;
1338 }
1339
1340 ah->ah_sc = sc;
8df5d1b7 1341 ah->hw_version.devid = devid;
e1e2f93f 1342 sc->sc_ah = ah;
4f3acf81 1343
f637cfd6 1344 r = ath9k_hw_init(ah);
4f3acf81 1345 if (r) {
ff37e337 1346 DPRINTF(sc, ATH_DBG_FATAL,
f637cfd6 1347 "Unable to initialize hardware; "
4f3acf81 1348 "initialization status: %d\n", r);
ff37e337
S		 1349 goto bad;
1350 }
ff37e337
S		 1351
1352 /* Get the hardware key cache size. */
2660b81a 1353 sc->keymax = ah->caps.keycache_size;
17d7904d 1354 if (sc->keymax > ATH_KEYMAX) {
d8baa939 1355 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 1356 "Warning, using only %u entries in %u key cache\n",
17d7904d
S		 1357 ATH_KEYMAX, sc->keymax);
1358 sc->keymax = ATH_KEYMAX;
ff37e337
S		 1359 }
1360
1361 /*
1362 * Reset the key cache since some parts do not
1363 * reset the contents on initial power up.
1364 */
17d7904d 1365 for (i = 0; i < sc->keymax; i++)
ff37e337 1366 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1367
ff37e337 1368 /* default to MONITOR mode */
2660b81a 1369 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
d97809db 1370
ff37e337
S		 1371 /* Setup rate tables */
1372
1373 ath_rate_attach(sc);
1374 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1375 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1376
1377 /*
1378 * Allocate hardware transmit queues: one queue for
1379 * beacon frames and one data queue for each QoS
1380 * priority. Note that the hal handles reseting
1381 * these queues at the needed time.
1382 */
b77f483f
S		 1383 sc->beacon.beaconq = ath_beaconq_setup(ah);
1384 if (sc->beacon.beaconq == -1) {
ff37e337 1385 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1386 "Unable to setup a beacon xmit queue\n");
4f3acf81 1387 r = -EIO;
ff37e337
S		 1388 goto bad2;
1389 }
b77f483f
S		 1390 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1391 if (sc->beacon.cabq == NULL) {
ff37e337 1392 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1393 "Unable to setup CAB xmit queue\n");
4f3acf81 1394 r = -EIO;
ff37e337
S		 1395 goto bad2;
1396 }
1397
17d7904d 1398 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
ff37e337
S		 1399 ath_cabq_update(sc);
1400
b77f483f
S		 1401 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1402 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1403
1404 /* Setup data queues */
1405 /* NB: ensure BK queue is the lowest priority h/w queue */
1406 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1407 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1408 "Unable to setup xmit queue for BK traffic\n");
4f3acf81 1409 r = -EIO;
ff37e337
S		 1410 goto bad2;
1411 }
1412
1413 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1414 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1415 "Unable to setup xmit queue for BE traffic\n");
4f3acf81 1416 r = -EIO;
ff37e337
S		 1417 goto bad2;
1418 }
1419 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1420 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1421 "Unable to setup xmit queue for VI traffic\n");
4f3acf81 1422 r = -EIO;
ff37e337
S		 1423 goto bad2;
1424 }
1425 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1426 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1427 "Unable to setup xmit queue for VO traffic\n");
4f3acf81 1428 r = -EIO;
ff37e337
S		 1429 goto bad2;
1430 }
1431
1432 /* Initializes the noise floor to a reasonable default value.
1433 * Later on this will be updated during ANI processing. */
1434
17d7904d
S		 1435 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1436 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
ff37e337
S		 1437
1438 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1439 ATH9K_CIPHER_TKIP, NULL)) {
1440 /*
1441 * Whether we should enable h/w TKIP MIC.
1442 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1443 * report WMM capable, so it's always safe to turn on
1444 * TKIP MIC in this case.
1445 */
1446 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1447 0, 1, NULL);
1448 }
1449
1450 /*
1451 * Check whether the separate key cache entries
1452 * are required to handle both tx+rx MIC keys.
1453 * With split mic keys the number of stations is limited
1454 * to 27 otherwise 59.
1455 */
1456 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1457 ATH9K_CIPHER_TKIP, NULL)
1458 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1459 ATH9K_CIPHER_MIC, NULL)
1460 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1461 0, NULL))
17d7904d 1462 sc->splitmic = 1;
ff37e337
S		 1463
1464 /* turn on mcast key search if possible */
1465 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1466 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1467 1, NULL);
1468
17d7904d 1469 sc->config.txpowlimit = ATH_TXPOWER_MAX;
ff37e337
S		 1470
1471 /* 11n Capabilities */
2660b81a 1472 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337
S		 1473 sc->sc_flags |= SC_OP_TXAGGR;
1474 sc->sc_flags |= SC_OP_RXAGGR;
1475 }
1476
2660b81a
S		 1477 sc->tx_chainmask = ah->caps.tx_chainmask;
1478 sc->rx_chainmask = ah->caps.rx_chainmask;
ff37e337
S		 1479
1480 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1481 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337 1482
8ca21f01 1483 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
ba52da58 1484 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
ff37e337 1485
b77f483f 1486 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1487
1488 /* initialize beacon slots */
c52f33d0 1489 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2c3db3d5 1490 sc->beacon.bslot[i] = NULL;
c52f33d0
JM		 1491 sc->beacon.bslot_aphy[i] = NULL;
1492 }
ff37e337 1493
ff37e337
S		 1494 /* setup channels and rates */
1495
5f8e077c 1496 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1497 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1498 sc->rates[IEEE80211_BAND_2GHZ];
1499 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1500 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1501 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337 1502
2660b81a 1503 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
5f8e077c 1504 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1505 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1506 sc->rates[IEEE80211_BAND_5GHZ];
1507 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1508 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1509 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1510 }
1511
81fa16fb 1512 if (sc->btcoex_info.btcoex_scheme == ATH_BTCOEX_CFG_2WIRE)
f985ad12 1513 ath9k_hw_btcoex_init(ah);
c97c92d9 1514
ff37e337
S		 1515 return 0;
1516bad2:
1517 /* cleanup tx queues */
1518 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1519 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1520 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337 1521bad:
95fafca2 1522 ath9k_hw_detach(ah);
3ce1b1a9 1523 sc->sc_ah = NULL;
4f3acf81 1524bad_no_ah:
40b130a9 1525 ath9k_exit_debug(sc);
ff37e337 1526
4f3acf81 1527 return r;
ff37e337
S		 1528}
1529
c52f33d0 1530void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
f078f209 1531{
9c84b797
S		 1532 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1533 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1534 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1535 IEEE80211_HW_AMPDU_AGGREGATION |
1536 IEEE80211_HW_SUPPORTS_PS |
eeee1320
S		 1537 IEEE80211_HW_PS_NULLFUNC_STACK |
1538 IEEE80211_HW_SPECTRUM_MGMT;
f078f209 1539
b3bd89ce 1540 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
0ced0e17
JM		 1541 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1542
9c84b797
S		 1543 hw->wiphy->interface_modes =
1544 BIT(NL80211_IFTYPE_AP) |
1545 BIT(NL80211_IFTYPE_STATION) |
9cb5412b
PE		 1546 BIT(NL80211_IFTYPE_ADHOC) |
1547 BIT(NL80211_IFTYPE_MESH_POINT);
f078f209 1548
8feceb67 1549 hw->queues = 4;
e63835b0 1550 hw->max_rates = 4;
171387ef 1551 hw->channel_change_time = 5000;
465ca84d 1552 hw->max_listen_interval = 10;
dd190183
LR		 1553 /* Hardware supports 10 but we use 4 */
1554 hw->max_rate_tries = 4;
528f0c6b 1555 hw->sta_data_size = sizeof(struct ath_node);
17d7904d 1556 hw->vif_data_size = sizeof(struct ath_vif);
f078f209 1557
8feceb67 1558 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1559
c52f33d0
JM		 1560 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1561 &sc->sbands[IEEE80211_BAND_2GHZ];
1562 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1563 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1564 &sc->sbands[IEEE80211_BAND_5GHZ];
1565}
1566
1e40bcfa
LR		 1567/* Device driver core initialization */
1568int ath_init_device(u16 devid, struct ath_softc *sc)
c52f33d0
JM		 1569{
1570 struct ieee80211_hw *hw = sc->hw;
c52f33d0 1571 int error = 0, i;
3a702e49 1572 struct ath_regulatory *reg;
c52f33d0
JM		 1573
1574 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1575
1e40bcfa 1576 error = ath_init_softc(devid, sc);
c52f33d0
JM		 1577 if (error != 0)
1578 return error;
1579
1580 /* get mac address from hardware and set in mac80211 */
1581
1582 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1583
1584 ath_set_hw_capab(sc, hw);
1585
608b88cb 1586 error = ath_regd_init(&sc->common.regulatory, sc->hw->wiphy,
c26c2e57
LR		 1587 ath9k_reg_notifier);
1588 if (error)
1589 return error;
1590
608b88cb 1591 reg = &sc->common.regulatory;
c26c2e57 1592
2660b81a 1593 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1594 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
2660b81a 1595 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
eb2599ca 1596 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1597 }
1598
db93e7b5
SB		 1599 /* initialize tx/rx engine */
1600 error = ath_tx_init(sc, ATH_TXBUF);
1601 if (error != 0)
40b130a9 1602 goto error_attach;
8feceb67 1603
db93e7b5
SB		 1604 error = ath_rx_init(sc, ATH_RXBUF);
1605 if (error != 0)
40b130a9 1606 goto error_attach;
8feceb67 1607
0e2dedf9 1608 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
f98c3bd2
JM		 1609 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1610 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
0e2dedf9 1611
db93e7b5 1612 error = ieee80211_register_hw(hw);
8feceb67 1613
3a702e49 1614 if (!ath_is_world_regd(reg)) {
c02cf373 1615 error = regulatory_hint(hw->wiphy, reg->alpha2);
fe33eb39
LR		 1616 if (error)
1617 goto error_attach;
1618 }
5f8e077c 1619
db93e7b5
SB		 1620 /* Initialize LED control */
1621 ath_init_leds(sc);
8feceb67 1622
3b319aae 1623 ath_start_rfkill_poll(sc);
5f8e077c 1624
8feceb67 1625 return 0;
40b130a9
VT		 1626
1627error_attach:
1628 /* cleanup tx queues */
1629 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1630 if (ATH_TXQ_SETUP(sc, i))
1631 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1632
1633 ath9k_hw_detach(sc->sc_ah);
3ce1b1a9 1634 sc->sc_ah = NULL;
40b130a9
VT		 1635 ath9k_exit_debug(sc);
1636
8feceb67 1637 return error;
f078f209
LR		 1638}
1639
ff37e337
S		 1640int ath_reset(struct ath_softc *sc, bool retry_tx)
1641{
cbe61d8a 1642 struct ath_hw *ah = sc->sc_ah;
030bb495 1643 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1644 int r;
ff37e337
S		 1645
1646 ath9k_hw_set_interrupts(ah, 0);
043a0405 1647 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1648 ath_stoprecv(sc);
1649 ath_flushrecv(sc);
1650
1651 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1652 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 1653 if (r)
ff37e337 1654 DPRINTF(sc, ATH_DBG_FATAL,
6b45784f 1655 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S		 1656 spin_unlock_bh(&sc->sc_resetlock);
1657
1658 if (ath_startrecv(sc) != 0)
04bd4638 1659 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1660
1661 /*
1662 * We may be doing a reset in response to a request
1663 * that changes the channel so update any state that
1664 * might change as a result.
1665 */
ce111bad 1666 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1667
1668 ath_update_txpow(sc);
1669
1670 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1671 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 1672
17d7904d 1673 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 1674
1675 if (retry_tx) {
1676 int i;
1677 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1678 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1679 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1680 ath_txq_schedule(sc, &sc->tx.txq[i]);
1681 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1682 }
1683 }
1684 }
1685
ae8d2858 1686 return r;
ff37e337
S		 1687}
1688
1689/*
1690 * This function will allocate both the DMA descriptor structure, and the
1691 * buffers it contains. These are used to contain the descriptors used
1692 * by the system.
1693*/
1694int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1695 struct list_head *head, const char *name,
1696 int nbuf, int ndesc)
1697{
1698#define DS2PHYS(_dd, _ds) \
1699 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1700#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1701#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1702
1703 struct ath_desc *ds;
1704 struct ath_buf *bf;
1705 int i, bsize, error;
1706
04bd4638
S		 1707 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1708 name, nbuf, ndesc);
ff37e337 1709
b03a9db9 1710 INIT_LIST_HEAD(head);
ff37e337
S		 1711 /* ath_desc must be a multiple of DWORDs */
1712 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1713 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1714 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1715 error = -ENOMEM;
1716 goto fail;
1717 }
1718
ff37e337
S		 1719 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1720
1721 /*
1722 * Need additional DMA memory because we can't use
1723 * descriptors that cross the 4K page boundary. Assume
1724 * one skipped descriptor per 4K page.
1725 */
2660b81a 1726 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
ff37e337
S		 1727 u32 ndesc_skipped =
1728 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1729 u32 dma_len;
1730
1731 while (ndesc_skipped) {
1732 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1733 dd->dd_desc_len += dma_len;
1734
1735 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1736 };
1737 }
1738
1739 /* allocate descriptors */
7da3c55c 1740 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
f0e6ce13 1741 &dd->dd_desc_paddr, GFP_KERNEL);
ff37e337
S		 1742 if (dd->dd_desc == NULL) {
1743 error = -ENOMEM;
1744 goto fail;
1745 }
1746 ds = dd->dd_desc;
04bd4638 1747 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
ae459af1 1748 name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1749 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1750
1751 /* allocate buffers */
1752 bsize = sizeof(struct ath_buf) * nbuf;
f0e6ce13 1753 bf = kzalloc(bsize, GFP_KERNEL);
ff37e337
S		 1754 if (bf == NULL) {
1755 error = -ENOMEM;
1756 goto fail2;
1757 }
ff37e337
S		 1758 dd->dd_bufptr = bf;
1759
ff37e337
S		 1760 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1761 bf->bf_desc = ds;
1762 bf->bf_daddr = DS2PHYS(dd, ds);
1763
2660b81a 1764 if (!(sc->sc_ah->caps.hw_caps &
ff37e337
S		 1765 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1766 /*
1767 * Skip descriptor addresses which can cause 4KB
1768 * boundary crossing (addr + length) with a 32 dword
1769 * descriptor fetch.
1770 */
1771 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1772 ASSERT((caddr_t) bf->bf_desc <
1773 ((caddr_t) dd->dd_desc +
1774 dd->dd_desc_len));
1775
1776 ds += ndesc;
1777 bf->bf_desc = ds;
1778 bf->bf_daddr = DS2PHYS(dd, ds);
1779 }
1780 }
1781 list_add_tail(&bf->list, head);
1782 }
1783 return 0;
1784fail2:
7da3c55c
GJ		 1785 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1786 dd->dd_desc_paddr);
ff37e337
S		 1787fail:
1788 memset(dd, 0, sizeof(*dd));
1789 return error;
1790#undef ATH_DESC_4KB_BOUND_CHECK
1791#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1792#undef DS2PHYS
1793}
1794
1795void ath_descdma_cleanup(struct ath_softc *sc,
1796 struct ath_descdma *dd,
1797 struct list_head *head)
1798{
7da3c55c
GJ		 1799 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1800 dd->dd_desc_paddr);
ff37e337
S		 1801
1802 INIT_LIST_HEAD(head);
1803 kfree(dd->dd_bufptr);
1804 memset(dd, 0, sizeof(*dd));
1805}
1806
1807int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1808{
1809 int qnum;
1810
1811 switch (queue) {
1812 case 0:
b77f483f 1813 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1814 break;
1815 case 1:
b77f483f 1816 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 1817 break;
1818 case 2:
b77f483f 1819 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1820 break;
1821 case 3:
b77f483f 1822 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 1823 break;
1824 default:
b77f483f 1825 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1826 break;
1827 }
1828
1829 return qnum;
1830}
1831
1832int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1833{
1834 int qnum;
1835
1836 switch (queue) {
1837 case ATH9K_WME_AC_VO:
1838 qnum = 0;
1839 break;
1840 case ATH9K_WME_AC_VI:
1841 qnum = 1;
1842 break;
1843 case ATH9K_WME_AC_BE:
1844 qnum = 2;
1845 break;
1846 case ATH9K_WME_AC_BK:
1847 qnum = 3;
1848 break;
1849 default:
1850 qnum = -1;
1851 break;
1852 }
1853
1854 return qnum;
1855}
1856
5f8e077c
LR		 1857/* XXX: Remove me once we don't depend on ath9k_channel for all
1858 * this redundant data */
0e2dedf9
JM		 1859void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1860 struct ath9k_channel *ichan)
5f8e077c 1861{
5f8e077c
LR		 1862 struct ieee80211_channel *chan = hw->conf.channel;
1863 struct ieee80211_conf *conf = &hw->conf;
1864
1865 ichan->channel = chan->center_freq;
1866 ichan->chan = chan;
1867
1868 if (chan->band == IEEE80211_BAND_2GHZ) {
1869 ichan->chanmode = CHANNEL_G;
1870 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1871 } else {
1872 ichan->chanmode = CHANNEL_A;
1873 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1874 }
1875
1876 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1877
1878 if (conf_is_ht(conf)) {
1879 if (conf_is_ht40(conf))
1880 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1881
1882 ichan->chanmode = ath_get_extchanmode(sc, chan,
1883 conf->channel_type);
1884 }
1885}
1886
ff37e337
S		 1887/**********************/
1888/* mac80211 callbacks */
1889/**********************/
1890
8feceb67 1891static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1892{
bce048d7
JM		 1893 struct ath_wiphy *aphy = hw->priv;
1894 struct ath_softc *sc = aphy->sc;
8feceb67 1895 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1896 struct ath9k_channel *init_channel;
82880a7c 1897 int r;
f078f209 1898
04bd4638
S		 1899 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1900 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1901
141b38b6
S		 1902 mutex_lock(&sc->mutex);
1903
9580a222
JM		 1904 if (ath9k_wiphy_started(sc)) {
1905 if (sc->chan_idx == curchan->hw_value) {
1906 /*
1907 * Already on the operational channel, the new wiphy
1908 * can be marked active.
1909 */
1910 aphy->state = ATH_WIPHY_ACTIVE;
1911 ieee80211_wake_queues(hw);
1912 } else {
1913 /*
1914 * Another wiphy is on another channel, start the new
1915 * wiphy in paused state.
1916 */
1917 aphy->state = ATH_WIPHY_PAUSED;
1918 ieee80211_stop_queues(hw);
1919 }
1920 mutex_unlock(&sc->mutex);
1921 return 0;
1922 }
1923 aphy->state = ATH_WIPHY_ACTIVE;
1924
8feceb67 1925 /* setup initial channel */
f078f209 1926
82880a7c 1927 sc->chan_idx = curchan->hw_value;
f078f209 1928
82880a7c 1929 init_channel = ath_get_curchannel(sc, hw);
ff37e337
S		 1930
1931 /* Reset SERDES registers */
1932 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1933
1934 /*
1935 * The basic interface to setting the hardware in a good
1936 * state is ``reset''. On return the hardware is known to
1937 * be powered up and with interrupts disabled. This must
1938 * be followed by initialization of the appropriate bits
1939 * and then setup of the interrupt mask.
1940 */
1941 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1942 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1943 if (r) {
ff37e337 1944 DPRINTF(sc, ATH_DBG_FATAL,
6b45784f 1945 "Unable to reset hardware; reset status %d "
ae8d2858
LR		 1946 "(freq %u MHz)\n", r,
1947 curchan->center_freq);
ff37e337 1948 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 1949 goto mutex_unlock;
ff37e337
S		 1950 }
1951 spin_unlock_bh(&sc->sc_resetlock);
1952
1953 /*
1954 * This is needed only to setup initial state
1955 * but it's best done after a reset.
1956 */
1957 ath_update_txpow(sc);
8feceb67 1958
ff37e337
S		 1959 /*
1960 * Setup the hardware after reset:
1961 * The receive engine is set going.
1962 * Frame transmit is handled entirely
1963 * in the frame output path; there's nothing to do
1964 * here except setup the interrupt mask.
1965 */
1966 if (ath_startrecv(sc) != 0) {
1ffb0610 1967 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
141b38b6
S		 1968 r = -EIO;
1969 goto mutex_unlock;
f078f209 1970 }
8feceb67 1971
ff37e337 1972 /* Setup our intr mask. */
17d7904d 1973 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S		 1974 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1975 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1976
2660b81a 1977 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 1978 sc->imask |= ATH9K_INT_GTT;
ff37e337 1979
2660b81a 1980 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 1981 sc->imask |= ATH9K_INT_CST;
ff37e337 1982
ce111bad 1983 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1984
1985 sc->sc_flags &= ~SC_OP_INVALID;
1986
1987 /* Disable BMISS interrupt when we're not associated */
17d7904d
S		 1988 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1989 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337 1990
bce048d7 1991 ieee80211_wake_queues(hw);
ff37e337 1992
42935eca 1993 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
164ace38 1994
81fa16fb 1995 if ((sc->btcoex_info.btcoex_scheme == ATH_BTCOEX_CFG_2WIRE) &&
f985ad12
VT		 1996 !(sc->sc_flags & SC_OP_BTCOEX_ENABLED))
1997 ath9k_hw_btcoex_enable(sc->sc_ah);
1998
141b38b6
S		 1999mutex_unlock:
2000 mutex_unlock(&sc->mutex);
2001
ae8d2858 2002 return r;
f078f209
LR		 2003}
2004
8feceb67
VT		 2005static int ath9k_tx(struct ieee80211_hw *hw,
2006 struct sk_buff *skb)
f078f209 2007{
528f0c6b 2008 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM		 2009 struct ath_wiphy *aphy = hw->priv;
2010 struct ath_softc *sc = aphy->sc;
528f0c6b 2011 struct ath_tx_control txctl;
8feceb67 2012 int hdrlen, padsize;
528f0c6b 2013
8089cc47 2014 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
ee166a0e
JM		 2015 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2016 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2017 goto exit;
2018 }
2019
96148326 2020 if (sc->ps_enabled) {
dc8c4585
JM		 2021 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2022 /*
2023 * mac80211 does not set PM field for normal data frames, so we
2024 * need to update that based on the current PS mode.
2025 */
2026 if (ieee80211_is_data(hdr->frame_control) &&
2027 !ieee80211_is_nullfunc(hdr->frame_control) &&
2028 !ieee80211_has_pm(hdr->frame_control)) {
2029 DPRINTF(sc, ATH_DBG_PS, "Add PM=1 for a TX frame "
2030 "while in PS mode\n");
2031 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2032 }
2033 }
2034
9a23f9ca
JM		 2035 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2036 /*
2037 * We are using PS-Poll and mac80211 can request TX while in
2038 * power save mode. Need to wake up hardware for the TX to be
2039 * completed and if needed, also for RX of buffered frames.
2040 */
2041 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2042 ath9k_ps_wakeup(sc);
2043 ath9k_hw_setrxabort(sc->sc_ah, 0);
2044 if (ieee80211_is_pspoll(hdr->frame_control)) {
2045 DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a "
2046 "buffered frame\n");
2047 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2048 } else {
2049 DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n");
2050 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2051 }
2052 /*
2053 * The actual restore operation will happen only after
2054 * the sc_flags bit is cleared. We are just dropping
2055 * the ps_usecount here.
2056 */
2057 ath9k_ps_restore(sc);
2058 }
2059
528f0c6b 2060 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2061
8feceb67
VT		 2062 /*
2063 * As a temporary workaround, assign seq# here; this will likely need
2064 * to be cleaned up to work better with Beacon transmission and virtual
2065 * BSSes.
2066 */
2067 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2068 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2069 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2070 sc->tx.seq_no += 0x10;
8feceb67 2071 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2072 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2073 }
f078f209 2074
8feceb67
VT		 2075 /* Add the padding after the header if this is not already done */
2076 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2077 if (hdrlen & 3) {
2078 padsize = hdrlen % 4;
2079 if (skb_headroom(skb) < padsize)
2080 return -1;
2081 skb_push(skb, padsize);
2082 memmove(skb->data, skb->data + padsize, hdrlen);
2083 }
2084
528f0c6b
S		 2085 /* Check if a tx queue is available */
2086
2087 txctl.txq = ath_test_get_txq(sc, skb);
2088 if (!txctl.txq)
2089 goto exit;
2090
04bd4638 2091 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2092
c52f33d0 2093 if (ath_tx_start(hw, skb, &txctl) != 0) {
04bd4638 2094 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2095 goto exit;
8feceb67
VT		 2096 }
2097
528f0c6b
S		 2098 return 0;
2099exit:
2100 dev_kfree_skb_any(skb);
8feceb67 2101 return 0;
f078f209
LR		 2102}
2103
8feceb67 2104static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 2105{
bce048d7
JM		 2106 struct ath_wiphy *aphy = hw->priv;
2107 struct ath_softc *sc = aphy->sc;
f078f209 2108
4c483817
S		 2109 mutex_lock(&sc->mutex);
2110
9580a222
JM		 2111 aphy->state = ATH_WIPHY_INACTIVE;
2112
c94dbff7
LR		 2113 cancel_delayed_work_sync(&sc->ath_led_blink_work);
2114 cancel_delayed_work_sync(&sc->tx_complete_work);
2115
2116 if (!sc->num_sec_wiphy) {
2117 cancel_delayed_work_sync(&sc->wiphy_work);
2118 cancel_work_sync(&sc->chan_work);
2119 }
2120
9c84b797 2121 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 2122 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
4c483817 2123 mutex_unlock(&sc->mutex);
9c84b797
S		 2124 return;
2125 }
8feceb67 2126
9580a222
JM		 2127 if (ath9k_wiphy_started(sc)) {
2128 mutex_unlock(&sc->mutex);
2129 return; /* another wiphy still in use */
2130 }
2131
ff37e337
S		 2132 /* make sure h/w will not generate any interrupt
2133 * before setting the invalid flag. */
2134 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2135
2136 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2137 ath_drain_all_txq(sc, false);
ff37e337
S		 2138 ath_stoprecv(sc);
2139 ath9k_hw_phy_disable(sc->sc_ah);
2140 } else
b77f483f 2141 sc->rx.rxlink = NULL;
ff37e337 2142
3b319aae 2143 wiphy_rfkill_stop_polling(sc->hw->wiphy);
19d337df 2144
f985ad12
VT		 2145 if (sc->sc_flags & SC_OP_BTCOEX_ENABLED)
2146 ath9k_hw_btcoex_disable(sc->sc_ah);
2147
ff37e337
S		 2148 /* disable HAL and put h/w to sleep */
2149 ath9k_hw_disable(sc->sc_ah);
2150 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
eff563cf 2151 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
ff37e337
S		 2152
2153 sc->sc_flags |= SC_OP_INVALID;
500c064d 2154
141b38b6
S		 2155 mutex_unlock(&sc->mutex);
2156
04bd4638 2157 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2158}
2159
8feceb67
VT		 2160static int ath9k_add_interface(struct ieee80211_hw *hw,
2161 struct ieee80211_if_init_conf *conf)
f078f209 2162{
bce048d7
JM		 2163 struct ath_wiphy *aphy = hw->priv;
2164 struct ath_softc *sc = aphy->sc;
17d7904d 2165 struct ath_vif *avp = (void *)conf->vif->drv_priv;
d97809db 2166 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 2167 int ret = 0;
8feceb67 2168
141b38b6
S		 2169 mutex_lock(&sc->mutex);
2170
8ca21f01
JM		 2171 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2172 sc->nvifs > 0) {
2173 ret = -ENOBUFS;
2174 goto out;
2175 }
2176
8feceb67 2177 switch (conf->type) {
05c914fe 2178 case NL80211_IFTYPE_STATION:
d97809db 2179 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2180 break;
05c914fe 2181 case NL80211_IFTYPE_ADHOC:
05c914fe 2182 case NL80211_IFTYPE_AP:
9cb5412b 2183 case NL80211_IFTYPE_MESH_POINT:
2c3db3d5
JM		 2184 if (sc->nbcnvifs >= ATH_BCBUF) {
2185 ret = -ENOBUFS;
2186 goto out;
2187 }
9cb5412b 2188 ic_opmode = conf->type;
f078f209
LR		 2189 break;
2190 default:
2191 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2192 "Interface type %d not yet supported\n", conf->type);
2c3db3d5
JM		 2193 ret = -EOPNOTSUPP;
2194 goto out;
f078f209
LR		 2195 }
2196
17d7904d 2197 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 2198
17d7904d 2199 /* Set the VIF opmode */
5640b08e
S		 2200 avp->av_opmode = ic_opmode;
2201 avp->av_bslot = -1;
2202
2c3db3d5 2203 sc->nvifs++;
8ca21f01
JM		 2204
2205 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2206 ath9k_set_bssid_mask(hw);
2207
2c3db3d5
JM		 2208 if (sc->nvifs > 1)
2209 goto out; /* skip global settings for secondary vif */
2210
b238e90e 2211 if (ic_opmode == NL80211_IFTYPE_AP) {
5640b08e 2212 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
b238e90e
S		 2213 sc->sc_flags |= SC_OP_TSF_RESET;
2214 }
5640b08e 2215
5640b08e 2216 /* Set the device opmode */
2660b81a 2217 sc->sc_ah->opmode = ic_opmode;
5640b08e 2218
4e30ffa2
VN		 2219 /*
2220 * Enable MIB interrupts when there are hardware phy counters.
2221 * Note we only do this (at the moment) for station mode.
2222 */
4af9cf4f 2223 if ((conf->type == NL80211_IFTYPE_STATION) ||
9cb5412b
PE		 2224 (conf->type == NL80211_IFTYPE_ADHOC) ||
2225 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
1aa8e847 2226 sc->imask |= ATH9K_INT_MIB;
4af9cf4f
S		 2227 sc->imask |= ATH9K_INT_TSFOOR;
2228 }
2229
17d7904d 2230 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 2231
f38faa31
SB		 2232 if (conf->type == NL80211_IFTYPE_AP ||
2233 conf->type == NL80211_IFTYPE_ADHOC ||
2234 conf->type == NL80211_IFTYPE_MONITOR)
415f738e 2235 ath_start_ani(sc);
6f255425 2236
2c3db3d5 2237out:
141b38b6 2238 mutex_unlock(&sc->mutex);
2c3db3d5 2239 return ret;
f078f209
LR		 2240}
2241
8feceb67
VT		 2242static void ath9k_remove_interface(struct ieee80211_hw *hw,
2243 struct ieee80211_if_init_conf *conf)
f078f209 2244{
bce048d7
JM		 2245 struct ath_wiphy *aphy = hw->priv;
2246 struct ath_softc *sc = aphy->sc;
17d7904d 2247 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2c3db3d5 2248 int i;
f078f209 2249
04bd4638 2250 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2251
141b38b6
S		 2252 mutex_lock(&sc->mutex);
2253
6f255425 2254 /* Stop ANI */
17d7904d 2255 del_timer_sync(&sc->ani.timer);
580f0b8a 2256
8feceb67 2257 /* Reclaim beacon resources */
9cb5412b
PE		 2258 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2259 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2260 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
b77f483f 2261 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2262 ath_beacon_return(sc, avp);
580f0b8a 2263 }
f078f209 2264
8feceb67 2265 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2266
2c3db3d5
JM		 2267 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2268 if (sc->beacon.bslot[i] == conf->vif) {
2269 printk(KERN_DEBUG "%s: vif had allocated beacon "
2270 "slot\n", __func__);
2271 sc->beacon.bslot[i] = NULL;
c52f33d0 2272 sc->beacon.bslot_aphy[i] = NULL;
2c3db3d5
JM		 2273 }
2274 }
2275
17d7904d 2276 sc->nvifs--;
141b38b6
S		 2277
2278 mutex_unlock(&sc->mutex);
f078f209
LR		 2279}
2280
e8975581 2281static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2282{
bce048d7
JM		 2283 struct ath_wiphy *aphy = hw->priv;
2284 struct ath_softc *sc = aphy->sc;
e8975581 2285 struct ieee80211_conf *conf = &hw->conf;
8782b41d 2286 struct ath_hw *ah = sc->sc_ah;
64839170 2287 bool all_wiphys_idle = false, disable_radio = false;
f078f209 2288
aa33de09 2289 mutex_lock(&sc->mutex);
141b38b6 2290
64839170
LR		 2291 /* Leave this as the first check */
2292 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
2293
2294 spin_lock_bh(&sc->wiphy_lock);
2295 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
2296 spin_unlock_bh(&sc->wiphy_lock);
2297
2298 if (conf->flags & IEEE80211_CONF_IDLE){
2299 if (all_wiphys_idle)
2300 disable_radio = true;
2301 }
2302 else if (all_wiphys_idle) {
2303 ath_radio_enable(sc);
2304 DPRINTF(sc, ATH_DBG_CONFIG,
2305 "not-idle: enabling radio\n");
2306 }
2307 }
2308
3cbb5dd7
VN		 2309 if (changed & IEEE80211_CONF_CHANGE_PS) {
2310 if (conf->flags & IEEE80211_CONF_PS) {
8782b41d
VN		 2311 if (!(ah->caps.hw_caps &
2312 ATH9K_HW_CAP_AUTOSLEEP)) {
2313 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2314 sc->imask |= ATH9K_INT_TIM_TIMER;
2315 ath9k_hw_set_interrupts(sc->sc_ah,
2316 sc->imask);
2317 }
2318 ath9k_hw_setrxabort(sc->sc_ah, 1);
3cbb5dd7 2319 }
96148326 2320 sc->ps_enabled = true;
3cbb5dd7 2321 } else {
96148326 2322 sc->ps_enabled = false;
3cbb5dd7 2323 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8782b41d
VN		 2324 if (!(ah->caps.hw_caps &
2325 ATH9K_HW_CAP_AUTOSLEEP)) {
2326 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca
JM		 2327 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2328 SC_OP_WAIT_FOR_CAB |
2329 SC_OP_WAIT_FOR_PSPOLL_DATA |
2330 SC_OP_WAIT_FOR_TX_ACK);
8782b41d
VN		 2331 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2332 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2333 ath9k_hw_set_interrupts(sc->sc_ah,
2334 sc->imask);
2335 }
3cbb5dd7
VN		 2336 }
2337 }
2338 }
2339
4797938c 2340 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2341 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2342 int pos = curchan->hw_value;
ae5eb026 2343
0e2dedf9
JM		 2344 aphy->chan_idx = pos;
2345 aphy->chan_is_ht = conf_is_ht(conf);
2346
8089cc47
JM		 2347 if (aphy->state == ATH_WIPHY_SCAN ||
2348 aphy->state == ATH_WIPHY_ACTIVE)
2349 ath9k_wiphy_pause_all_forced(sc, aphy);
2350 else {
2351 /*
2352 * Do not change operational channel based on a paused
2353 * wiphy changes.
2354 */
2355 goto skip_chan_change;
2356 }
0e2dedf9 2357
04bd4638
S		 2358 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2359 curchan->center_freq);
f078f209 2360
5f8e077c 2361 /* XXX: remove me eventualy */
0e2dedf9 2362 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 2363
ecf70441 2364 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2365
0e2dedf9 2366 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
04bd4638 2367 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2368 mutex_unlock(&sc->mutex);
e11602b7
S		 2369 return -EINVAL;
2370 }
094d05dc 2371 }
f078f209 2372
8089cc47 2373skip_chan_change:
5c020dc6 2374 if (changed & IEEE80211_CONF_CHANGE_POWER)
17d7904d 2375 sc->config.txpowlimit = 2 * conf->power_level;
f078f209 2376
64839170
LR		 2377 if (disable_radio) {
2378 DPRINTF(sc, ATH_DBG_CONFIG, "idle: disabling radio\n");
2379 ath_radio_disable(sc);
2380 }
2381
aa33de09 2382 mutex_unlock(&sc->mutex);
141b38b6 2383
f078f209
LR		 2384 return 0;
2385}
2386
8feceb67
VT		 2387#define SUPPORTED_FILTERS \
2388 (FIF_PROMISC_IN_BSS | \
2389 FIF_ALLMULTI | \
2390 FIF_CONTROL | \
af6a3fc7 2391 FIF_PSPOLL | \
8feceb67
VT		 2392 FIF_OTHER_BSS | \
2393 FIF_BCN_PRBRESP_PROMISC | \
2394 FIF_FCSFAIL)
c83be688 2395
8feceb67
VT		 2396/* FIXME: sc->sc_full_reset ? */
2397static void ath9k_configure_filter(struct ieee80211_hw *hw,
2398 unsigned int changed_flags,
2399 unsigned int *total_flags,
3ac64bee 2400 u64 multicast)
8feceb67 2401{
bce048d7
JM		 2402 struct ath_wiphy *aphy = hw->priv;
2403 struct ath_softc *sc = aphy->sc;
8feceb67 2404 u32 rfilt;
f078f209 2405
8feceb67
VT		 2406 changed_flags &= SUPPORTED_FILTERS;
2407 *total_flags &= SUPPORTED_FILTERS;
f078f209 2408
b77f483f 2409 sc->rx.rxfilter = *total_flags;
aa68aeaa 2410 ath9k_ps_wakeup(sc);
8feceb67
VT		 2411 rfilt = ath_calcrxfilter(sc);
2412 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 2413 ath9k_ps_restore(sc);
f078f209 2414
b77f483f 2415 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
8feceb67 2416}
f078f209 2417
8feceb67
VT		 2418static void ath9k_sta_notify(struct ieee80211_hw *hw,
2419 struct ieee80211_vif *vif,
2420 enum sta_notify_cmd cmd,
17741cdc 2421 struct ieee80211_sta *sta)
8feceb67 2422{
bce048d7
JM		 2423 struct ath_wiphy *aphy = hw->priv;
2424 struct ath_softc *sc = aphy->sc;
f078f209 2425
8feceb67
VT		 2426 switch (cmd) {
2427 case STA_NOTIFY_ADD:
5640b08e 2428 ath_node_attach(sc, sta);
8feceb67
VT		 2429 break;
2430 case STA_NOTIFY_REMOVE:
b5aa9bf9 2431 ath_node_detach(sc, sta);
8feceb67
VT		 2432 break;
2433 default:
2434 break;
2435 }
f078f209
LR		 2436}
2437
141b38b6 2438static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 2439 const struct ieee80211_tx_queue_params *params)
f078f209 2440{
bce048d7
JM		 2441 struct ath_wiphy *aphy = hw->priv;
2442 struct ath_softc *sc = aphy->sc;
8feceb67
VT		 2443 struct ath9k_tx_queue_info qi;
2444 int ret = 0, qnum;
f078f209 2445
8feceb67
VT		 2446 if (queue >= WME_NUM_AC)
2447 return 0;
f078f209 2448
141b38b6
S		 2449 mutex_lock(&sc->mutex);
2450
1ffb0610
S		 2451 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2452
8feceb67
VT		 2453 qi.tqi_aifs = params->aifs;
2454 qi.tqi_cwmin = params->cw_min;
2455 qi.tqi_cwmax = params->cw_max;
2456 qi.tqi_burstTime = params->txop;
2457 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2458
8feceb67 2459 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2460 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2461 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2462 queue, qnum, params->aifs, params->cw_min,
2463 params->cw_max, params->txop);
f078f209 2464
8feceb67
VT		 2465 ret = ath_txq_update(sc, qnum, &qi);
2466 if (ret)
04bd4638 2467 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2468
141b38b6
S		 2469 mutex_unlock(&sc->mutex);
2470
8feceb67
VT		 2471 return ret;
2472}
f078f209 2473
8feceb67
VT		 2474static int ath9k_set_key(struct ieee80211_hw *hw,
2475 enum set_key_cmd cmd,
dc822b5d
JB		 2476 struct ieee80211_vif *vif,
2477 struct ieee80211_sta *sta,
8feceb67
VT		 2478 struct ieee80211_key_conf *key)
2479{
bce048d7
JM		 2480 struct ath_wiphy *aphy = hw->priv;
2481 struct ath_softc *sc = aphy->sc;
8feceb67 2482 int ret = 0;
f078f209 2483
b3bd89ce
JM		 2484 if (modparam_nohwcrypt)
2485 return -ENOSPC;
2486
141b38b6 2487 mutex_lock(&sc->mutex);
3cbb5dd7 2488 ath9k_ps_wakeup(sc);
d8baa939 2489 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 2490
8feceb67
VT		 2491 switch (cmd) {
2492 case SET_KEY:
3f53dd64 2493 ret = ath_key_config(sc, vif, sta, key);
6ace2891
JM		 2494 if (ret >= 0) {
2495 key->hw_key_idx = ret;
8feceb67
VT		 2496 /* push IV and Michael MIC generation to stack */
2497 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2498 if (key->alg == ALG_TKIP)
2499 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2500 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2501 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2502 ret = 0;
8feceb67
VT		 2503 }
2504 break;
2505 case DISABLE_KEY:
2506 ath_key_delete(sc, key);
8feceb67
VT		 2507 break;
2508 default:
2509 ret = -EINVAL;
2510 }
f078f209 2511
3cbb5dd7 2512 ath9k_ps_restore(sc);
141b38b6
S		 2513 mutex_unlock(&sc->mutex);
2514
8feceb67
VT		 2515 return ret;
2516}
f078f209 2517
8feceb67
VT		 2518static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2519 struct ieee80211_vif *vif,
2520 struct ieee80211_bss_conf *bss_conf,
2521 u32 changed)
2522{
bce048d7
JM		 2523 struct ath_wiphy *aphy = hw->priv;
2524 struct ath_softc *sc = aphy->sc;
2d0ddec5
JB		 2525 struct ath_hw *ah = sc->sc_ah;
2526 struct ath_vif *avp = (void *)vif->drv_priv;
2527 u32 rfilt = 0;
2528 int error, i;
f078f209 2529
141b38b6
S		 2530 mutex_lock(&sc->mutex);
2531
2d0ddec5
JB		 2532 /*
2533 * TODO: Need to decide which hw opmode to use for
2534 * multi-interface cases
2535 * XXX: This belongs into add_interface!
2536 */
2537 if (vif->type == NL80211_IFTYPE_AP &&
2538 ah->opmode != NL80211_IFTYPE_AP) {
2539 ah->opmode = NL80211_IFTYPE_STATION;
2540 ath9k_hw_setopmode(ah);
2541 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2542 sc->curaid = 0;
2543 ath9k_hw_write_associd(sc);
2544 /* Request full reset to get hw opmode changed properly */
2545 sc->sc_flags |= SC_OP_FULL_RESET;
2546 }
2547
2548 if ((changed & BSS_CHANGED_BSSID) &&
2549 !is_zero_ether_addr(bss_conf->bssid)) {
2550 switch (vif->type) {
2551 case NL80211_IFTYPE_STATION:
2552 case NL80211_IFTYPE_ADHOC:
2553 case NL80211_IFTYPE_MESH_POINT:
2554 /* Set BSSID */
2555 memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2556 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2557 sc->curaid = 0;
2558 ath9k_hw_write_associd(sc);
2559
2560 /* Set aggregation protection mode parameters */
2561 sc->config.ath_aggr_prot = 0;
2562
2563 DPRINTF(sc, ATH_DBG_CONFIG,
2564 "RX filter 0x%x bssid %pM aid 0x%x\n",
2565 rfilt, sc->curbssid, sc->curaid);
2566
2567 /* need to reconfigure the beacon */
2568 sc->sc_flags &= ~SC_OP_BEACONS ;
2569
2570 break;
2571 default:
2572 break;
2573 }
2574 }
2575
2576 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2577 (vif->type == NL80211_IFTYPE_AP) ||
2578 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2579 if ((changed & BSS_CHANGED_BEACON) ||
2580 (changed & BSS_CHANGED_BEACON_ENABLED &&
2581 bss_conf->enable_beacon)) {
2582 /*
2583 * Allocate and setup the beacon frame.
2584 *
2585 * Stop any previous beacon DMA. This may be
2586 * necessary, for example, when an ibss merge
2587 * causes reconfiguration; we may be called
2588 * with beacon transmission active.
2589 */
2590 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2591
2592 error = ath_beacon_alloc(aphy, vif);
2593 if (!error)
2594 ath_beacon_config(sc, vif);
2595 }
2596 }
2597
2598 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2599 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2600 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2601 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2602 ath9k_hw_keysetmac(sc->sc_ah,
2603 (u16)i,
2604 sc->curbssid);
2605 }
2606
2607 /* Only legacy IBSS for now */
2608 if (vif->type == NL80211_IFTYPE_ADHOC)
2609 ath_update_chainmask(sc, 0);
2610
8feceb67 2611 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2612 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2613 bss_conf->use_short_preamble);
2614 if (bss_conf->use_short_preamble)
2615 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2616 else
2617 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2618 }
f078f209 2619
8feceb67 2620 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2621 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2622 bss_conf->use_cts_prot);
2623 if (bss_conf->use_cts_prot &&
2624 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2625 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2626 else
2627 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2628 }
f078f209 2629
8feceb67 2630 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2631 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2632 bss_conf->assoc);
5640b08e 2633 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 2634 }
141b38b6 2635
57c4d7b4
JB		 2636 /*
2637 * The HW TSF has to be reset when the beacon interval changes.
2638 * We set the flag here, and ath_beacon_config_ap() would take this
2639 * into account when it gets called through the subsequent
2640 * config_interface() call - with IFCC_BEACON in the changed field.
2641 */
2642
2643 if (changed & BSS_CHANGED_BEACON_INT) {
2644 sc->sc_flags |= SC_OP_TSF_RESET;
2645 sc->beacon_interval = bss_conf->beacon_int;
2646 }
2647
141b38b6 2648 mutex_unlock(&sc->mutex);
8feceb67 2649}
f078f209 2650
8feceb67
VT		 2651static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2652{
2653 u64 tsf;
bce048d7
JM		 2654 struct ath_wiphy *aphy = hw->priv;
2655 struct ath_softc *sc = aphy->sc;
f078f209 2656
141b38b6
S		 2657 mutex_lock(&sc->mutex);
2658 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2659 mutex_unlock(&sc->mutex);
f078f209 2660
8feceb67
VT		 2661 return tsf;
2662}
f078f209 2663
3b5d665b
AF		 2664static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2665{
bce048d7
JM		 2666 struct ath_wiphy *aphy = hw->priv;
2667 struct ath_softc *sc = aphy->sc;
3b5d665b 2668
141b38b6
S		 2669 mutex_lock(&sc->mutex);
2670 ath9k_hw_settsf64(sc->sc_ah, tsf);
2671 mutex_unlock(&sc->mutex);
3b5d665b
AF		 2672}
2673
8feceb67
VT		 2674static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2675{
bce048d7
JM		 2676 struct ath_wiphy *aphy = hw->priv;
2677 struct ath_softc *sc = aphy->sc;
c83be688 2678
141b38b6
S		 2679 mutex_lock(&sc->mutex);
2680 ath9k_hw_reset_tsf(sc->sc_ah);
2681 mutex_unlock(&sc->mutex);
8feceb67 2682}
f078f209 2683
8feceb67 2684static int ath9k_ampdu_action(struct ieee80211_hw *hw,
141b38b6
S		 2685 enum ieee80211_ampdu_mlme_action action,
2686 struct ieee80211_sta *sta,
2687 u16 tid, u16 *ssn)
8feceb67 2688{
bce048d7
JM		 2689 struct ath_wiphy *aphy = hw->priv;
2690 struct ath_softc *sc = aphy->sc;
8feceb67 2691 int ret = 0;
f078f209 2692
8feceb67
VT		 2693 switch (action) {
2694 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2695 if (!(sc->sc_flags & SC_OP_RXAGGR))
2696 ret = -ENOTSUPP;
8feceb67
VT		 2697 break;
2698 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2699 break;
2700 case IEEE80211_AMPDU_TX_START:
f83da965
S		 2701 ath_tx_aggr_start(sc, sta, tid, ssn);
2702 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2703 break;
2704 case IEEE80211_AMPDU_TX_STOP:
f83da965 2705 ath_tx_aggr_stop(sc, sta, tid);
17741cdc 2706 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2707 break;
b1720231 2708 case IEEE80211_AMPDU_TX_OPERATIONAL:
8469cdef
S		 2709 ath_tx_aggr_resume(sc, sta, tid);
2710 break;
8feceb67 2711 default:
04bd4638 2712 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2713 }
2714
2715 return ret;
f078f209
LR		 2716}
2717
0c98de65
S		 2718static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2719{
bce048d7
JM		 2720 struct ath_wiphy *aphy = hw->priv;
2721 struct ath_softc *sc = aphy->sc;
0c98de65 2722
3d832611 2723 mutex_lock(&sc->mutex);
8089cc47
JM		 2724 if (ath9k_wiphy_scanning(sc)) {
2725 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2726 "same time\n");
2727 /*
2728 * Do not allow the concurrent scanning state for now. This
2729 * could be improved with scanning control moved into ath9k.
2730 */
3d832611 2731 mutex_unlock(&sc->mutex);
8089cc47
JM		 2732 return;
2733 }
2734
2735 aphy->state = ATH_WIPHY_SCAN;
2736 ath9k_wiphy_pause_all_forced(sc, aphy);
2737
e5f0921a 2738 spin_lock_bh(&sc->ani_lock);
0c98de65 2739 sc->sc_flags |= SC_OP_SCANNING;
e5f0921a 2740 spin_unlock_bh(&sc->ani_lock);
3d832611 2741 mutex_unlock(&sc->mutex);
0c98de65
S		 2742}
2743
2744static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2745{
bce048d7
JM		 2746 struct ath_wiphy *aphy = hw->priv;
2747 struct ath_softc *sc = aphy->sc;
0c98de65 2748
3d832611 2749 mutex_lock(&sc->mutex);
e5f0921a 2750 spin_lock_bh(&sc->ani_lock);
8089cc47 2751 aphy->state = ATH_WIPHY_ACTIVE;
0c98de65 2752 sc->sc_flags &= ~SC_OP_SCANNING;
9c07a777 2753 sc->sc_flags |= SC_OP_FULL_RESET;
e5f0921a 2754 spin_unlock_bh(&sc->ani_lock);
3d832611 2755 mutex_unlock(&sc->mutex);
0c98de65
S		 2756}
2757
6baff7f9 2758struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2759 .tx = ath9k_tx,
2760 .start = ath9k_start,
2761 .stop = ath9k_stop,
2762 .add_interface = ath9k_add_interface,
2763 .remove_interface = ath9k_remove_interface,
2764 .config = ath9k_config,
8feceb67 2765 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2766 .sta_notify = ath9k_sta_notify,
2767 .conf_tx = ath9k_conf_tx,
8feceb67 2768 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2769 .set_key = ath9k_set_key,
8feceb67 2770 .get_tsf = ath9k_get_tsf,
3b5d665b 2771 .set_tsf = ath9k_set_tsf,
8feceb67 2772 .reset_tsf = ath9k_reset_tsf,
4233df6b 2773 .ampdu_action = ath9k_ampdu_action,
0c98de65
S		 2774 .sw_scan_start = ath9k_sw_scan_start,
2775 .sw_scan_complete = ath9k_sw_scan_complete,
3b319aae 2776 .rfkill_poll = ath9k_rfkill_poll_state,
8feceb67
VT		 2777};
2778
392dff83
BP		 2779static struct {
2780 u32 version;
2781 const char * name;
2782} ath_mac_bb_names[] = {
2783 { AR_SREV_VERSION_5416_PCI, "5416" },
2784 { AR_SREV_VERSION_5416_PCIE, "5418" },
2785 { AR_SREV_VERSION_9100, "9100" },
2786 { AR_SREV_VERSION_9160, "9160" },
2787 { AR_SREV_VERSION_9280, "9280" },
ac88b6ec
VN		 2788 { AR_SREV_VERSION_9285, "9285" },
2789 { AR_SREV_VERSION_9287, "9287" }
392dff83
BP		 2790};
2791
2792static struct {
2793 u16 version;
2794 const char * name;
2795} ath_rf_names[] = {
2796 { 0, "5133" },
2797 { AR_RAD5133_SREV_MAJOR, "5133" },
2798 { AR_RAD5122_SREV_MAJOR, "5122" },
2799 { AR_RAD2133_SREV_MAJOR, "2133" },
2800 { AR_RAD2122_SREV_MAJOR, "2122" }
2801};
2802
2803/*
2804 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2805 */
6baff7f9 2806const char *
392dff83
BP		 2807ath_mac_bb_name(u32 mac_bb_version)
2808{
2809 int i;
2810
2811 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2812 if (ath_mac_bb_names[i].version == mac_bb_version) {
2813 return ath_mac_bb_names[i].name;
2814 }
2815 }
2816
2817 return "????";
2818}
2819
2820/*
2821 * Return the RF name. "????" is returned if the RF is unknown.
2822 */
6baff7f9 2823const char *
392dff83
BP		 2824ath_rf_name(u16 rf_version)
2825{
2826 int i;
2827
2828 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2829 if (ath_rf_names[i].version == rf_version) {
2830 return ath_rf_names[i].name;
2831 }
2832 }
2833
2834 return "????";
2835}
2836
6baff7f9 2837static int __init ath9k_init(void)
f078f209 2838{
ca8a8560
VT		 2839 int error;
2840
ca8a8560
VT		 2841 /* Register rate control algorithm */
2842 error = ath_rate_control_register();
2843 if (error != 0) {
2844 printk(KERN_ERR
b51bb3cd
LR		 2845 "ath9k: Unable to register rate control "
2846 "algorithm: %d\n",
ca8a8560 2847 error);
6baff7f9 2848 goto err_out;
ca8a8560
VT		 2849 }
2850
19d8bc22
GJ		 2851 error = ath9k_debug_create_root();
2852 if (error) {
2853 printk(KERN_ERR
2854 "ath9k: Unable to create debugfs root: %d\n",
2855 error);
2856 goto err_rate_unregister;
2857 }
2858
6baff7f9
GJ		 2859 error = ath_pci_init();
2860 if (error < 0) {
f078f209 2861 printk(KERN_ERR
b51bb3cd 2862 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9 2863 error = -ENODEV;
19d8bc22 2864 goto err_remove_root;
f078f209
LR		 2865 }
2866
09329d37
GJ		 2867 error = ath_ahb_init();
2868 if (error < 0) {
2869 error = -ENODEV;
2870 goto err_pci_exit;
2871 }
2872
f078f209 2873 return 0;
6baff7f9 2874
09329d37
GJ		 2875 err_pci_exit:
2876 ath_pci_exit();
2877
19d8bc22
GJ		 2878 err_remove_root:
2879 ath9k_debug_remove_root();
6baff7f9
GJ		 2880 err_rate_unregister:
2881 ath_rate_control_unregister();
2882 err_out:
2883 return error;
f078f209 2884}
6baff7f9 2885module_init(ath9k_init);
f078f209 2886
6baff7f9 2887static void __exit ath9k_exit(void)
f078f209 2888{
09329d37 2889 ath_ahb_exit();
6baff7f9 2890 ath_pci_exit();
19d8bc22 2891 ath9k_debug_remove_root();
ca8a8560 2892 ath_rate_control_unregister();
04bd4638 2893 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 2894}
6baff7f9 2895module_exit(ath9k_exit);
Linux kernel - Deliverables
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