[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / mci.c

/*
 * Copyright (c) 2010-2011 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/dma-mapping.h>
#include <linux/slab.h>

#include "ath9k.h"
#include "mci.h"

static const u8 ath_mci_duty_cycle[] = { 55, 50, 60, 70, 80, 85, 90, 95, 98 };

static struct ath_mci_profile_info*
ath_mci_find_profile(struct ath_mci_profile *mci,
		     struct ath_mci_profile_info *info)
{
	struct ath_mci_profile_info *entry;

	if (list_empty(&mci->info))
		return NULL;

	list_for_each_entry(entry, &mci->info, list) {
		if (entry->conn_handle == info->conn_handle)
			return entry;
	}
	return NULL;
}

static bool ath_mci_add_profile(struct ath_common *common,
				struct ath_mci_profile *mci,
				struct ath_mci_profile_info *info)
{
	struct ath_mci_profile_info *entry;

	if ((mci->num_sco == ATH_MCI_MAX_SCO_PROFILE) &&
	    (info->type == MCI_GPM_COEX_PROFILE_VOICE))
		return false;

	if (((NUM_PROF(mci) - mci->num_sco) == ATH_MCI_MAX_ACL_PROFILE) &&
	    (info->type != MCI_GPM_COEX_PROFILE_VOICE))
		return false;

	entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
	if (!entry)
		return false;

	memcpy(entry, info, 10);
	INC_PROF(mci, info);
	list_add_tail(&entry->list, &mci->info);

	return true;
}

static void ath_mci_del_profile(struct ath_common *common,
				struct ath_mci_profile *mci,
				struct ath_mci_profile_info *entry)
{
	if (!entry)
		return;

	DEC_PROF(mci, entry);
	list_del(&entry->list);
	kfree(entry);
}

void ath_mci_flush_profile(struct ath_mci_profile *mci)
{
	struct ath_mci_profile_info *info, *tinfo;

	mci->aggr_limit = 0;

	if (list_empty(&mci->info))
		return;

	list_for_each_entry_safe(info, tinfo, &mci->info, list) {
		list_del(&info->list);
		DEC_PROF(mci, info);
		kfree(info);
	}
}

static void ath_mci_adjust_aggr_limit(struct ath_btcoex *btcoex)
{
	struct ath_mci_profile *mci = &btcoex->mci;
	u32 wlan_airtime = btcoex->btcoex_period *
				(100 - btcoex->duty_cycle) / 100;

	/*
	 * Scale: wlan_airtime is in ms, aggr_limit is in 0.25 ms.
	 * When wlan_airtime is less than 4ms, aggregation limit has to be
	 * adjusted half of wlan_airtime to ensure that the aggregation can fit
	 * without collision with BT traffic.
	 */
	if ((wlan_airtime <= 4) &&
	    (!mci->aggr_limit || (mci->aggr_limit > (2 * wlan_airtime))))
		mci->aggr_limit = 2 * wlan_airtime;
}

static void ath_mci_update_scheme(struct ath_softc *sc)
{
	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	struct ath_btcoex *btcoex = &sc->btcoex;
	struct ath_mci_profile *mci = &btcoex->mci;
	struct ath9k_hw_mci *mci_hw = &sc->sc_ah->btcoex_hw.mci;
	struct ath_mci_profile_info *info;
	u32 num_profile = NUM_PROF(mci);

	if (mci_hw->config & ATH_MCI_CONFIG_DISABLE_TUNING)
		goto skip_tuning;

	btcoex->duty_cycle = ath_mci_duty_cycle[num_profile];

	if (num_profile == 1) {
		info = list_first_entry(&mci->info,
					struct ath_mci_profile_info,
					list);
		if (mci->num_sco) {
			if (info->T == 12)
				mci->aggr_limit = 8;
			else if (info->T == 6) {
				mci->aggr_limit = 6;
				btcoex->duty_cycle = 30;
			}
			ath_dbg(common, MCI,
				"Single SCO, aggregation limit %d 1/4 ms\n",
				mci->aggr_limit);
		} else if (mci->num_pan || mci->num_other_acl) {
			/*
			 * For single PAN/FTP profile, allocate 35% for BT
			 * to improve WLAN throughput.
			 */
			btcoex->duty_cycle = 35;
			btcoex->btcoex_period = 53;
			ath_dbg(common, MCI,
				"Single PAN/FTP bt period %d ms dutycycle %d\n",
				btcoex->duty_cycle, btcoex->btcoex_period);
		} else if (mci->num_hid) {
			btcoex->duty_cycle = 30;
			mci->aggr_limit = 6;
			ath_dbg(common, MCI,
				"Multiple attempt/timeout single HID "
				"aggregation limit 1.5 ms dutycycle 30%%\n");
		}
	} else if (num_profile == 2) {
		if (mci->num_hid == 2)
			btcoex->duty_cycle = 30;
		mci->aggr_limit = 6;
		ath_dbg(common, MCI,
			"Two BT profiles aggr limit 1.5 ms dutycycle %d%%\n",
			btcoex->duty_cycle);
	} else if (num_profile >= 3) {
		mci->aggr_limit = 4;
		ath_dbg(common, MCI,
			"Three or more profiles aggregation limit 1 ms\n");
	}

skip_tuning:
	if (IS_CHAN_2GHZ(sc->sc_ah->curchan)) {
		if (IS_CHAN_HT(sc->sc_ah->curchan))
			ath_mci_adjust_aggr_limit(btcoex);
		else
			btcoex->btcoex_period >>= 1;
	}

	ath9k_hw_btcoex_disable(sc->sc_ah);
	ath9k_btcoex_timer_pause(sc);

	if (IS_CHAN_5GHZ(sc->sc_ah->curchan))
		return;

	btcoex->duty_cycle += (mci->num_bdr ? ATH_MCI_BDR_DUTY_CYCLE : 0);
	if (btcoex->duty_cycle > ATH_MCI_MAX_DUTY_CYCLE)
		btcoex->duty_cycle = ATH_MCI_MAX_DUTY_CYCLE;

	btcoex->btcoex_no_stomp =  btcoex->btcoex_period * 1000 *
		(100 - btcoex->duty_cycle) / 100;

	ath9k_hw_btcoex_enable(sc->sc_ah);
	ath9k_btcoex_timer_resume(sc);
}

static void ath_mci_cal_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
{
	struct ath_hw *ah = sc->sc_ah;
	struct ath_common *common = ath9k_hw_common(ah);
	struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
	u32 payload[4] = {0, 0, 0, 0};

	switch (opcode) {
	case MCI_GPM_BT_CAL_REQ:
		if (mci_hw->bt_state == MCI_BT_AWAKE) {
			ar9003_mci_state(ah, MCI_STATE_SET_BT_CAL_START);
			ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
		}
		ath_dbg(common, MCI, "MCI State : %d\n", mci_hw->bt_state);
		break;
	case MCI_GPM_BT_CAL_GRANT:
		MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_DONE);
		ar9003_mci_send_message(sc->sc_ah, MCI_GPM, 0, payload,
					16, false, true);
		break;
	default:
		ath_dbg(common, MCI, "Unknown GPM CAL message\n");
		break;
	}
}

static void ath9k_mci_work(struct work_struct *work)
{
	struct ath_softc *sc = container_of(work, struct ath_softc, mci_work);

	ath_mci_update_scheme(sc);
}

static void ath_mci_process_profile(struct ath_softc *sc,
				    struct ath_mci_profile_info *info)
{
	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	struct ath_btcoex *btcoex = &sc->btcoex;
	struct ath_mci_profile *mci = &btcoex->mci;
	struct ath_mci_profile_info *entry = NULL;

	entry = ath_mci_find_profile(mci, info);
	if (entry)
		memcpy(entry, info, 10);

	if (info->start) {
		if (!entry && !ath_mci_add_profile(common, mci, info))
			return;
	} else
		ath_mci_del_profile(common, mci, entry);

	btcoex->btcoex_period = ATH_MCI_DEF_BT_PERIOD;
	mci->aggr_limit = mci->num_sco ? 6 : 0;

	btcoex->duty_cycle = ath_mci_duty_cycle[NUM_PROF(mci)];
	if (NUM_PROF(mci))
		btcoex->bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
	else
		btcoex->bt_stomp_type = mci->num_mgmt ? ATH_BTCOEX_STOMP_ALL :
							ATH_BTCOEX_STOMP_LOW;

	ieee80211_queue_work(sc->hw, &sc->mci_work);
}

static void ath_mci_process_status(struct ath_softc *sc,
				   struct ath_mci_profile_status *status)
{
	struct ath_btcoex *btcoex = &sc->btcoex;
	struct ath_mci_profile *mci = &btcoex->mci;
	struct ath_mci_profile_info info;
	int i = 0, old_num_mgmt = mci->num_mgmt;

	/* Link status type are not handled */
	if (status->is_link)
		return;

	info.conn_handle = status->conn_handle;
	if (ath_mci_find_profile(mci, &info))
		return;

	if (status->conn_handle >= ATH_MCI_MAX_PROFILE)
		return;

	if (status->is_critical)
		__set_bit(status->conn_handle, mci->status);
	else
		__clear_bit(status->conn_handle, mci->status);

	mci->num_mgmt = 0;
	do {
		if (test_bit(i, mci->status))
			mci->num_mgmt++;
	} while (++i < ATH_MCI_MAX_PROFILE);

	if (old_num_mgmt != mci->num_mgmt)
		ieee80211_queue_work(sc->hw, &sc->mci_work);
}

static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
{
	struct ath_hw *ah = sc->sc_ah;
	struct ath_mci_profile_info profile_info;
	struct ath_mci_profile_status profile_status;
	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	u8 major, minor;
	u32 seq_num;

	switch (opcode) {
	case MCI_GPM_COEX_VERSION_QUERY:
		ar9003_mci_state(ah, MCI_STATE_SEND_WLAN_COEX_VERSION);
		break;
	case MCI_GPM_COEX_VERSION_RESPONSE:
		major = *(rx_payload + MCI_GPM_COEX_B_MAJOR_VERSION);
		minor = *(rx_payload + MCI_GPM_COEX_B_MINOR_VERSION);
		ar9003_mci_set_bt_version(ah, major, minor);
		break;
	case MCI_GPM_COEX_STATUS_QUERY:
		ar9003_mci_send_wlan_channels(ah);
		break;
	case MCI_GPM_COEX_BT_PROFILE_INFO:
		memcpy(&profile_info,
		       (rx_payload + MCI_GPM_COEX_B_PROFILE_TYPE), 10);

		if ((profile_info.type == MCI_GPM_COEX_PROFILE_UNKNOWN) ||
		    (profile_info.type >= MCI_GPM_COEX_PROFILE_MAX)) {
			ath_dbg(common, MCI,
				"Illegal profile type = %d, state = %d\n",
				profile_info.type,
				profile_info.start);
			break;
		}

		ath_mci_process_profile(sc, &profile_info);
		break;
	case MCI_GPM_COEX_BT_STATUS_UPDATE:
		profile_status.is_link = *(rx_payload +
					   MCI_GPM_COEX_B_STATUS_TYPE);
		profile_status.conn_handle = *(rx_payload +
					       MCI_GPM_COEX_B_STATUS_LINKID);
		profile_status.is_critical = *(rx_payload +
					       MCI_GPM_COEX_B_STATUS_STATE);

		seq_num = *((u32 *)(rx_payload + 12));
		ath_dbg(common, MCI,
			"BT_Status_Update: is_link=%d, linkId=%d, state=%d, SEQ=%d\n",
			profile_status.is_link, profile_status.conn_handle,
			profile_status.is_critical, seq_num);

		ath_mci_process_status(sc, &profile_status);
		break;
	default:
		ath_dbg(common, MCI, "Unknown GPM COEX message = 0x%02x\n", opcode);
		break;
	}
}

int ath_mci_setup(struct ath_softc *sc)
{
	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	struct ath_mci_coex *mci = &sc->mci_coex;
	struct ath_mci_buf *buf = &mci->sched_buf;

	buf->bf_addr = dma_alloc_coherent(sc->dev,
				  ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
				  &buf->bf_paddr, GFP_KERNEL);

	if (buf->bf_addr == NULL) {
		ath_dbg(common, FATAL, "MCI buffer alloc failed\n");
		return -ENOMEM;
	}

	memset(buf->bf_addr, MCI_GPM_RSVD_PATTERN,
	       ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE);

	mci->sched_buf.bf_len = ATH_MCI_SCHED_BUF_SIZE;

	mci->gpm_buf.bf_len = ATH_MCI_GPM_BUF_SIZE;
	mci->gpm_buf.bf_addr = (u8 *)mci->sched_buf.bf_addr + mci->sched_buf.bf_len;
	mci->gpm_buf.bf_paddr = mci->sched_buf.bf_paddr + mci->sched_buf.bf_len;

	ar9003_mci_setup(sc->sc_ah, mci->gpm_buf.bf_paddr,
			 mci->gpm_buf.bf_addr, (mci->gpm_buf.bf_len >> 4),
			 mci->sched_buf.bf_paddr);

	INIT_WORK(&sc->mci_work, ath9k_mci_work);
	ath_dbg(common, MCI, "MCI Initialized\n");

	return 0;
}

void ath_mci_cleanup(struct ath_softc *sc)
{
	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	struct ath_hw *ah = sc->sc_ah;
	struct ath_mci_coex *mci = &sc->mci_coex;
	struct ath_mci_buf *buf = &mci->sched_buf;

	if (buf->bf_addr)
		dma_free_coherent(sc->dev,
				  ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
				  buf->bf_addr, buf->bf_paddr);

	ar9003_mci_cleanup(ah);

	ath_dbg(common, MCI, "MCI De-Initialized\n");
}

void ath_mci_intr(struct ath_softc *sc)
{
	struct ath_mci_coex *mci = &sc->mci_coex;
	struct ath_hw *ah = sc->sc_ah;
	struct ath_common *common = ath9k_hw_common(ah);
	struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
	u32 mci_int, mci_int_rxmsg;
	u32 offset, subtype, opcode;
	u32 *pgpm;
	u32 more_data = MCI_GPM_MORE;
	bool skip_gpm = false;

	ar9003_mci_get_interrupt(sc->sc_ah, &mci_int, &mci_int_rxmsg);

	if (ar9003_mci_state(ah, MCI_STATE_ENABLE) == 0) {
		ar9003_mci_get_next_gpm_offset(ah, true, NULL);
		return;
	}

	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) {
		u32 payload[4] = { 0xffffffff, 0xffffffff,
				   0xffffffff, 0xffffff00};

		/*
		 * The following REMOTE_RESET and SYS_WAKING used to sent
		 * only when BT wake up. Now they are always sent, as a
		 * recovery method to reset BT MCI's RX alignment.
		 */
		ar9003_mci_send_message(ah, MCI_REMOTE_RESET, 0,
					payload, 16, true, false);
		ar9003_mci_send_message(ah, MCI_SYS_WAKING, 0,
					NULL, 0, true, false);

		mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE;
		ar9003_mci_state(ah, MCI_STATE_RESET_REQ_WAKE);

		/*
		 * always do this for recovery and 2G/5G toggling and LNA_TRANS
		 */
		ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE);
	}

	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING) {
		mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING;

		if ((mci_hw->bt_state == MCI_BT_SLEEP) &&
		    (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP) !=
		     MCI_BT_SLEEP))
			ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE);
	}

	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) {
		mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING;

		if ((mci_hw->bt_state == MCI_BT_AWAKE) &&
		    (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP) !=
		     MCI_BT_AWAKE))
			ar9003_mci_state(ah, MCI_STATE_SET_BT_SLEEP);
	}

	if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
	    (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) {
		ar9003_mci_state(ah, MCI_STATE_RECOVER_RX);
		skip_gpm = true;
	}

	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO) {
		mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO;
		offset = ar9003_mci_state(ah, MCI_STATE_LAST_SCHD_MSG_OFFSET);
	}

	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_GPM) {
		mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_GPM;

		while (more_data == MCI_GPM_MORE) {

			pgpm = mci->gpm_buf.bf_addr;
			offset = ar9003_mci_get_next_gpm_offset(ah, false,
								&more_data);

			if (offset == MCI_GPM_INVALID)
				break;

			pgpm += (offset >> 2);

			/*
			 * The first dword is timer.
			 * The real data starts from 2nd dword.
			 */
			subtype = MCI_GPM_TYPE(pgpm);
			opcode = MCI_GPM_OPCODE(pgpm);

			if (skip_gpm)
				goto recycle;

			if (MCI_GPM_IS_CAL_TYPE(subtype)) {
				ath_mci_cal_msg(sc, subtype, (u8 *)pgpm);
			} else {
				switch (subtype) {
				case MCI_GPM_COEX_AGENT:
					ath_mci_msg(sc, opcode, (u8 *)pgpm);
					break;
				default:
					break;
				}
			}
		recycle:
			MCI_GPM_RECYCLE(pgpm);
		}
	}

	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_HW_MSG_MASK) {
		if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL)
			mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL;

		if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_INFO)
			mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_INFO;

		if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO) {
			int value_dbm = MS(mci_hw->cont_status,
					   AR_MCI_CONT_RSSI_POWER);

			mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_INFO;

			ath_dbg(common, MCI,
				"MCI CONT_INFO: (%s) pri = %d pwr = %d dBm\n",
				MS(mci_hw->cont_status, AR_MCI_CONT_TXRX) ?
				"tx" : "rx",
				MS(mci_hw->cont_status, AR_MCI_CONT_PRIORITY),
				value_dbm);
		}

		if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_NACK)
			mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_NACK;

		if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_RST)
			mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_RST;
	}

	if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
	    (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT))
		mci_int &= ~(AR_MCI_INTERRUPT_RX_INVALID_HDR |
			     AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT);
}

void ath_mci_enable(struct ath_softc *sc)
{
	struct ath_common *common = ath9k_hw_common(sc->sc_ah);

	if (!common->btcoex_enabled)
		return;

	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
		sc->sc_ah->imask |= ATH9K_INT_MCI;
}
Commit	Line	Data
7dc181c2 RM	1	/*
	2	* Copyright (c) 2010-2011 Atheros Communications Inc.
	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
9e25365f MSS	17	#include <linux/dma-mapping.h>
	18	#include <linux/slab.h>
	19
7dc181c2 RM	20	#include "ath9k.h"
	21	#include "mci.h"
	22
a197b76c	23	static const u8 ath_mci_duty_cycle[] = { 55, 50, 60, 70, 80, 85, 90, 95, 98 };
7dc181c2 RM	24
	25	static struct ath_mci_profile_info*
	26	ath_mci_find_profile(struct ath_mci_profile *mci,
	27	struct ath_mci_profile_info *info)
	28	{
	29	struct ath_mci_profile_info *entry;
	30
9e2e0c84 RM	31	if (list_empty(&mci->info))
	32	return NULL;
	33
7dc181c2 RM	34	list_for_each_entry(entry, &mci->info, list) {
7dc181c2 RM	35	if (entry->conn_handle == info->conn_handle)
9e2e0c84	36	return entry;
7dc181c2	37	}
9e2e0c84	38	return NULL;
7dc181c2 RM	39	}
	40
	41	static bool ath_mci_add_profile(struct ath_common *common,
	42	struct ath_mci_profile *mci,
	43	struct ath_mci_profile_info *info)
	44	{
	45	struct ath_mci_profile_info *entry;
	46
	47	if ((mci->num_sco == ATH_MCI_MAX_SCO_PROFILE) &&
682dd04b	48	(info->type == MCI_GPM_COEX_PROFILE_VOICE))
7dc181c2	49	return false;
7dc181c2 RM	50
7dc181c2 RM	51	if (((NUM_PROF(mci) - mci->num_sco) == ATH_MCI_MAX_ACL_PROFILE) &&
682dd04b	52	(info->type != MCI_GPM_COEX_PROFILE_VOICE))
7dc181c2	53	return false;
7dc181c2	54
3c7992e3	55	entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
9e2e0c84 RM	56	if (!entry)
9e2e0c84 RM	57	return false;
7dc181c2	58
9e2e0c84 RM	59	memcpy(entry, info, 10);
	60	INC_PROF(mci, info);
	61	list_add_tail(&entry->list, &mci->info);
682dd04b	62
7dc181c2 RM	63	return true;
	64	}
	65
	66	static void ath_mci_del_profile(struct ath_common *common,
	67	struct ath_mci_profile *mci,
9e2e0c84	68	struct ath_mci_profile_info *entry)
7dc181c2	69	{
682dd04b	70	if (!entry)
7dc181c2	71	return;
682dd04b	72
7dc181c2 RM	73	DEC_PROF(mci, entry);
	74	list_del(&entry->list);
	75	kfree(entry);
	76	}
	77
	78	void ath_mci_flush_profile(struct ath_mci_profile *mci)
	79	{
	80	struct ath_mci_profile_info info, tinfo;
	81
9e2e0c84 RM	82	mci->aggr_limit = 0;
	83
	84	if (list_empty(&mci->info))
	85	return;
	86
7dc181c2 RM	87	list_for_each_entry_safe(info, tinfo, &mci->info, list) {
	88	list_del(&info->list);
	89	DEC_PROF(mci, info);
	90	kfree(info);
	91	}
7dc181c2 RM	92	}
	93
	94	static void ath_mci_adjust_aggr_limit(struct ath_btcoex *btcoex)
	95	{
	96	struct ath_mci_profile *mci = &btcoex->mci;
	97	u32 wlan_airtime = btcoex->btcoex_period *
	98	(100 - btcoex->duty_cycle) / 100;
	99
	100	/*
	101	* Scale: wlan_airtime is in ms, aggr_limit is in 0.25 ms.
	102	* When wlan_airtime is less than 4ms, aggregation limit has to be
	103	* adjusted half of wlan_airtime to ensure that the aggregation can fit
	104	* without collision with BT traffic.
	105	*/
	106	if ((wlan_airtime <= 4) &&
	107	(!mci->aggr_limit \|\| (mci->aggr_limit > (2 * wlan_airtime))))
	108	mci->aggr_limit = 2 * wlan_airtime;
	109	}
	110
	111	static void ath_mci_update_scheme(struct ath_softc *sc)
	112	{
	113	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	114	struct ath_btcoex *btcoex = &sc->btcoex;
	115	struct ath_mci_profile *mci = &btcoex->mci;
0603143e	116	struct ath9k_hw_mci *mci_hw = &sc->sc_ah->btcoex_hw.mci;
7dc181c2 RM	117	struct ath_mci_profile_info *info;
	118	u32 num_profile = NUM_PROF(mci);
	119
0603143e RM	120	if (mci_hw->config & ATH_MCI_CONFIG_DISABLE_TUNING)
	121	goto skip_tuning;
	122
a197b76c RM	123	btcoex->duty_cycle = ath_mci_duty_cycle[num_profile];
a197b76c RM	124
7dc181c2 RM	125	if (num_profile == 1) {
	126	info = list_first_entry(&mci->info,
	127	struct ath_mci_profile_info,
	128	list);
0603143e RM	129	if (mci->num_sco) {
	130	if (info->T == 12)
	131	mci->aggr_limit = 8;
	132	else if (info->T == 6) {
	133	mci->aggr_limit = 6;
	134	btcoex->duty_cycle = 30;
	135	}
d2182b69	136	ath_dbg(common, MCI,
0603143e RM	137	"Single SCO, aggregation limit %d 1/4 ms\n",
	138	mci->aggr_limit);
	139	} else if (mci->num_pan \|\| mci->num_other_acl) {
	140	/*
	141	* For single PAN/FTP profile, allocate 35% for BT
	142	* to improve WLAN throughput.
	143	*/
	144	btcoex->duty_cycle = 35;
	145	btcoex->btcoex_period = 53;
d2182b69	146	ath_dbg(common, MCI,
0603143e RM	147	"Single PAN/FTP bt period %d ms dutycycle %d\n",
	148	btcoex->duty_cycle, btcoex->btcoex_period);
	149	} else if (mci->num_hid) {
7dc181c2	150	btcoex->duty_cycle = 30;
0603143e	151	mci->aggr_limit = 6;
d2182b69	152	ath_dbg(common, MCI,
7dc181c2	153	"Multiple attempt/timeout single HID "
0603143e	154	"aggregation limit 1.5 ms dutycycle 30%%\n");
7dc181c2	155	}
0603143e RM	156	} else if (num_profile == 2) {
	157	if (mci->num_hid == 2)
	158	btcoex->duty_cycle = 30;
7dc181c2	159	mci->aggr_limit = 6;
d2182b69	160	ath_dbg(common, MCI,
0603143e RM	161	"Two BT profiles aggr limit 1.5 ms dutycycle %d%%\n",
	162	btcoex->duty_cycle);
	163	} else if (num_profile >= 3) {
	164	mci->aggr_limit = 4;
	165	ath_dbg(common, MCI,
	166	"Three or more profiles aggregation limit 1 ms\n");
7dc181c2 RM	167	}
7dc181c2 RM	168
0603143e	169	skip_tuning:
7dc181c2 RM	170	if (IS_CHAN_2GHZ(sc->sc_ah->curchan)) {
	171	if (IS_CHAN_HT(sc->sc_ah->curchan))
	172	ath_mci_adjust_aggr_limit(btcoex);
	173	else
	174	btcoex->btcoex_period >>= 1;
	175	}
	176
	177	ath9k_hw_btcoex_disable(sc->sc_ah);
	178	ath9k_btcoex_timer_pause(sc);
	179
	180	if (IS_CHAN_5GHZ(sc->sc_ah->curchan))
	181	return;
	182
a197b76c	183	btcoex->duty_cycle += (mci->num_bdr ? ATH_MCI_BDR_DUTY_CYCLE : 0);
7dc181c2 RM	184	if (btcoex->duty_cycle > ATH_MCI_MAX_DUTY_CYCLE)
	185	btcoex->duty_cycle = ATH_MCI_MAX_DUTY_CYCLE;
	186
dfd0587a	187	btcoex->btcoex_no_stomp = btcoex->btcoex_period * 1000 *
682dd04b	188	(100 - btcoex->duty_cycle) / 100;
7dc181c2 RM	189
	190	ath9k_hw_btcoex_enable(sc->sc_ah);
	191	ath9k_btcoex_timer_resume(sc);
	192	}
	193
19686ddf MSS	194	static void ath_mci_cal_msg(struct ath_softc sc, u8 opcode, u8 rx_payload)
	195	{
	196	struct ath_hw *ah = sc->sc_ah;
	197	struct ath_common *common = ath9k_hw_common(ah);
6d97be48	198	struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
19686ddf MSS	199	u32 payload[4] = {0, 0, 0, 0};
	200
	201	switch (opcode) {
	202	case MCI_GPM_BT_CAL_REQ:
6d97be48	203	if (mci_hw->bt_state == MCI_BT_AWAKE) {
b98ccec0	204	ar9003_mci_state(ah, MCI_STATE_SET_BT_CAL_START);
19686ddf	205	ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
682dd04b	206	}
6d97be48	207	ath_dbg(common, MCI, "MCI State : %d\n", mci_hw->bt_state);
19686ddf	208	break;
19686ddf	209	case MCI_GPM_BT_CAL_GRANT:
19686ddf MSS	210	MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_DONE);
	211	ar9003_mci_send_message(sc->sc_ah, MCI_GPM, 0, payload,
	212	16, false, true);
	213	break;
19686ddf	214	default:
682dd04b	215	ath_dbg(common, MCI, "Unknown GPM CAL message\n");
19686ddf MSS	216	break;
	217	}
	218	}
	219
3c7992e3 RM	220	static void ath9k_mci_work(struct work_struct *work)
	221	{
	222	struct ath_softc *sc = container_of(work, struct ath_softc, mci_work);
	223
	224	ath_mci_update_scheme(sc);
	225	}
	226
e5f0a276 FF	227	static void ath_mci_process_profile(struct ath_softc *sc,
e5f0a276 FF	228	struct ath_mci_profile_info *info)
7dc181c2 RM	229	{
	230	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	231	struct ath_btcoex *btcoex = &sc->btcoex;
	232	struct ath_mci_profile *mci = &btcoex->mci;
9e2e0c84 RM	233	struct ath_mci_profile_info *entry = NULL;
	234
	235	entry = ath_mci_find_profile(mci, info);
	236	if (entry)
	237	memcpy(entry, info, 10);
7dc181c2 RM	238
7dc181c2 RM	239	if (info->start) {
9e2e0c84	240	if (!entry && !ath_mci_add_profile(common, mci, info))
7dc181c2 RM	241	return;
7dc181c2 RM	242	} else
9e2e0c84	243	ath_mci_del_profile(common, mci, entry);
7dc181c2 RM	244
	245	btcoex->btcoex_period = ATH_MCI_DEF_BT_PERIOD;
	246	mci->aggr_limit = mci->num_sco ? 6 : 0;
682dd04b	247
a197b76c RM	248	btcoex->duty_cycle = ath_mci_duty_cycle[NUM_PROF(mci)];
a197b76c RM	249	if (NUM_PROF(mci))
7dc181c2	250	btcoex->bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
a197b76c	251	else
7dc181c2 RM	252	btcoex->bt_stomp_type = mci->num_mgmt ? ATH_BTCOEX_STOMP_ALL :
7dc181c2 RM	253	ATH_BTCOEX_STOMP_LOW;
7dc181c2	254
3c7992e3	255	ieee80211_queue_work(sc->hw, &sc->mci_work);
7dc181c2 RM	256	}
7dc181c2 RM	257
e5f0a276 FF	258	static void ath_mci_process_status(struct ath_softc *sc,
e5f0a276 FF	259	struct ath_mci_profile_status *status)
7dc181c2	260	{
7dc181c2 RM	261	struct ath_btcoex *btcoex = &sc->btcoex;
	262	struct ath_mci_profile *mci = &btcoex->mci;
	263	struct ath_mci_profile_info info;
	264	int i = 0, old_num_mgmt = mci->num_mgmt;
	265
	266	/* Link status type are not handled */
682dd04b	267	if (status->is_link)
7dc181c2	268	return;
7dc181c2	269
7dc181c2	270	info.conn_handle = status->conn_handle;
682dd04b	271	if (ath_mci_find_profile(mci, &info))
7dc181c2	272	return;
682dd04b SM	273
682dd04b SM	274	if (status->conn_handle >= ATH_MCI_MAX_PROFILE)
7dc181c2	275	return;
682dd04b	276
7dc181c2 RM	277	if (status->is_critical)
	278	__set_bit(status->conn_handle, mci->status);
	279	else
	280	__clear_bit(status->conn_handle, mci->status);
	281
	282	mci->num_mgmt = 0;
	283	do {
	284	if (test_bit(i, mci->status))
	285	mci->num_mgmt++;
	286	} while (++i < ATH_MCI_MAX_PROFILE);
	287
	288	if (old_num_mgmt != mci->num_mgmt)
3c7992e3	289	ieee80211_queue_work(sc->hw, &sc->mci_work);
7dc181c2	290	}
9e25365f	291
19686ddf MSS	292	static void ath_mci_msg(struct ath_softc sc, u8 opcode, u8 rx_payload)
	293	{
	294	struct ath_hw *ah = sc->sc_ah;
	295	struct ath_mci_profile_info profile_info;
	296	struct ath_mci_profile_status profile_status;
	297	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
e1763d3f	298	u8 major, minor;
19686ddf MSS	299	u32 seq_num;
	300
	301	switch (opcode) {
19686ddf	302	case MCI_GPM_COEX_VERSION_QUERY:
b98ccec0	303	ar9003_mci_state(ah, MCI_STATE_SEND_WLAN_COEX_VERSION);
19686ddf	304	break;
19686ddf	305	case MCI_GPM_COEX_VERSION_RESPONSE:
19686ddf MSS	306	major = *(rx_payload + MCI_GPM_COEX_B_MAJOR_VERSION);
19686ddf MSS	307	minor = *(rx_payload + MCI_GPM_COEX_B_MINOR_VERSION);
e1763d3f	308	ar9003_mci_set_bt_version(ah, major, minor);
19686ddf	309	break;
19686ddf	310	case MCI_GPM_COEX_STATUS_QUERY:
2d340ac8	311	ar9003_mci_send_wlan_channels(ah);
19686ddf	312	break;
19686ddf	313	case MCI_GPM_COEX_BT_PROFILE_INFO:
19686ddf MSS	314	memcpy(&profile_info,
	315	(rx_payload + MCI_GPM_COEX_B_PROFILE_TYPE), 10);
	316
682dd04b SM	317	if ((profile_info.type == MCI_GPM_COEX_PROFILE_UNKNOWN) \|\|
682dd04b SM	318	(profile_info.type >= MCI_GPM_COEX_PROFILE_MAX)) {
d2182b69	319	ath_dbg(common, MCI,
682dd04b	320	"Illegal profile type = %d, state = %d\n",
d2182b69	321	profile_info.type,
19686ddf MSS	322	profile_info.start);
	323	break;
	324	}
	325
	326	ath_mci_process_profile(sc, &profile_info);
	327	break;
19686ddf MSS	328	case MCI_GPM_COEX_BT_STATUS_UPDATE:
	329	profile_status.is_link = *(rx_payload +
	330	MCI_GPM_COEX_B_STATUS_TYPE);
	331	profile_status.conn_handle = *(rx_payload +
	332	MCI_GPM_COEX_B_STATUS_LINKID);
	333	profile_status.is_critical = *(rx_payload +
	334	MCI_GPM_COEX_B_STATUS_STATE);
	335
	336	seq_num = ((u32 )(rx_payload + 12));
d2182b69	337	ath_dbg(common, MCI,
682dd04b	338	"BT_Status_Update: is_link=%d, linkId=%d, state=%d, SEQ=%d\n",
19686ddf MSS	339	profile_status.is_link, profile_status.conn_handle,
	340	profile_status.is_critical, seq_num);
	341
	342	ath_mci_process_status(sc, &profile_status);
	343	break;
19686ddf	344	default:
682dd04b	345	ath_dbg(common, MCI, "Unknown GPM COEX message = 0x%02x\n", opcode);
19686ddf MSS	346	break;
	347	}
	348	}
9e25365f	349
9e25365f MSS	350	int ath_mci_setup(struct ath_softc *sc)
	351	{
	352	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	353	struct ath_mci_coex *mci = &sc->mci_coex;
ea510e4b	354	struct ath_mci_buf *buf = &mci->sched_buf;
9e25365f	355
ea510e4b SM	356	buf->bf_addr = dma_alloc_coherent(sc->dev,
	357	ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
	358	&buf->bf_paddr, GFP_KERNEL);
9e25365f	359
ea510e4b	360	if (buf->bf_addr == NULL) {
d2182b69	361	ath_dbg(common, FATAL, "MCI buffer alloc failed\n");
ea510e4b	362	return -ENOMEM;
9e25365f MSS	363	}
9e25365f MSS	364
ea510e4b SM	365	memset(buf->bf_addr, MCI_GPM_RSVD_PATTERN,
ea510e4b SM	366	ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE);
9e25365f	367
ea510e4b	368	mci->sched_buf.bf_len = ATH_MCI_SCHED_BUF_SIZE;
9e25365f MSS	369
9e25365f MSS	370	mci->gpm_buf.bf_len = ATH_MCI_GPM_BUF_SIZE;
ea510e4b	371	mci->gpm_buf.bf_addr = (u8 *)mci->sched_buf.bf_addr + mci->sched_buf.bf_len;
9e25365f MSS	372	mci->gpm_buf.bf_paddr = mci->sched_buf.bf_paddr + mci->sched_buf.bf_len;
9e25365f MSS	373
9e25365f MSS	374	ar9003_mci_setup(sc->sc_ah, mci->gpm_buf.bf_paddr,
	375	mci->gpm_buf.bf_addr, (mci->gpm_buf.bf_len >> 4),
	376	mci->sched_buf.bf_paddr);
ea510e4b	377
3c7992e3	378	INIT_WORK(&sc->mci_work, ath9k_mci_work);
ea510e4b SM	379	ath_dbg(common, MCI, "MCI Initialized\n");
	380
	381	return 0;
9e25365f MSS	382	}
	383
	384	void ath_mci_cleanup(struct ath_softc *sc)
	385	{
ea510e4b	386	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
9e25365f MSS	387	struct ath_hw *ah = sc->sc_ah;
9e25365f MSS	388	struct ath_mci_coex *mci = &sc->mci_coex;
ea510e4b	389	struct ath_mci_buf *buf = &mci->sched_buf;
9e25365f	390
ea510e4b SM	391	if (buf->bf_addr)
	392	dma_free_coherent(sc->dev,
	393	ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
	394	buf->bf_addr, buf->bf_paddr);
	395
9e25365f	396	ar9003_mci_cleanup(ah);
ea510e4b SM	397
ea510e4b SM	398	ath_dbg(common, MCI, "MCI De-Initialized\n");
9e25365f	399	}
19686ddf MSS	400
	401	void ath_mci_intr(struct ath_softc *sc)
	402	{
	403	struct ath_mci_coex *mci = &sc->mci_coex;
	404	struct ath_hw *ah = sc->sc_ah;
	405	struct ath_common *common = ath9k_hw_common(ah);
6d97be48	406	struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
19686ddf MSS	407	u32 mci_int, mci_int_rxmsg;
	408	u32 offset, subtype, opcode;
	409	u32 *pgpm;
	410	u32 more_data = MCI_GPM_MORE;
	411	bool skip_gpm = false;
	412
	413	ar9003_mci_get_interrupt(sc->sc_ah, &mci_int, &mci_int_rxmsg);
	414
b98ccec0	415	if (ar9003_mci_state(ah, MCI_STATE_ENABLE) == 0) {
506847ad	416	ar9003_mci_get_next_gpm_offset(ah, true, NULL);
19686ddf MSS	417	return;
	418	}
	419
	420	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) {
	421	u32 payload[4] = { 0xffffffff, 0xffffffff,
	422	0xffffffff, 0xffffff00};
	423
	424	/*
	425	* The following REMOTE_RESET and SYS_WAKING used to sent
	426	* only when BT wake up. Now they are always sent, as a
	427	* recovery method to reset BT MCI's RX alignment.
	428	*/
19686ddf MSS	429	ar9003_mci_send_message(ah, MCI_REMOTE_RESET, 0,
19686ddf MSS	430	payload, 16, true, false);
19686ddf MSS	431	ar9003_mci_send_message(ah, MCI_SYS_WAKING, 0,
	432	NULL, 0, true, false);
	433
	434	mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE;
b98ccec0	435	ar9003_mci_state(ah, MCI_STATE_RESET_REQ_WAKE);
19686ddf MSS	436
	437	/*
	438	* always do this for recovery and 2G/5G toggling and LNA_TRANS
	439	*/
b98ccec0	440	ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE);
19686ddf MSS	441	}
19686ddf MSS	442
19686ddf MSS	443	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING) {
	444	mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING;
	445
6d97be48	446	if ((mci_hw->bt_state == MCI_BT_SLEEP) &&
b98ccec0 RM	447	(ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP) !=
	448	MCI_BT_SLEEP))
	449	ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE);
19686ddf MSS	450	}
	451
	452	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) {
19686ddf MSS	453	mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING;
19686ddf MSS	454
6d97be48	455	if ((mci_hw->bt_state == MCI_BT_AWAKE) &&
b98ccec0 RM	456	(ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP) !=
	457	MCI_BT_AWAKE))
	458	ar9003_mci_state(ah, MCI_STATE_SET_BT_SLEEP);
19686ddf MSS	459	}
	460
	461	if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) \|\|
	462	(mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) {
b98ccec0	463	ar9003_mci_state(ah, MCI_STATE_RECOVER_RX);
19686ddf MSS	464	skip_gpm = true;
	465	}
	466
	467	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO) {
19686ddf	468	mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO;
b98ccec0	469	offset = ar9003_mci_state(ah, MCI_STATE_LAST_SCHD_MSG_OFFSET);
19686ddf MSS	470	}
	471
	472	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_GPM) {
19686ddf MSS	473	mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_GPM;
	474
	475	while (more_data == MCI_GPM_MORE) {
	476
	477	pgpm = mci->gpm_buf.bf_addr;
506847ad RM	478	offset = ar9003_mci_get_next_gpm_offset(ah, false,
506847ad RM	479	&more_data);
19686ddf MSS	480
	481	if (offset == MCI_GPM_INVALID)
	482	break;
	483
	484	pgpm += (offset >> 2);
	485
	486	/*
	487	* The first dword is timer.
	488	* The real data starts from 2nd dword.
	489	*/
19686ddf MSS	490	subtype = MCI_GPM_TYPE(pgpm);
	491	opcode = MCI_GPM_OPCODE(pgpm);
	492
682dd04b SM	493	if (skip_gpm)
	494	goto recycle;
	495
	496	if (MCI_GPM_IS_CAL_TYPE(subtype)) {
	497	ath_mci_cal_msg(sc, subtype, (u8 *)pgpm);
	498	} else {
	499	switch (subtype) {
	500	case MCI_GPM_COEX_AGENT:
	501	ath_mci_msg(sc, opcode, (u8 *)pgpm);
	502	break;
	503	default:
	504	break;
19686ddf MSS	505	}
19686ddf MSS	506	}
682dd04b	507	recycle:
19686ddf MSS	508	MCI_GPM_RECYCLE(pgpm);
	509	}
	510	}
	511
	512	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_HW_MSG_MASK) {
19686ddf MSS	513	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL)
	514	mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL;
	515
682dd04b	516	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_INFO)
19686ddf	517	mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_INFO;
19686ddf MSS	518
19686ddf MSS	519	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO) {
26e942b7 RM	520	int value_dbm = MS(mci_hw->cont_status,
26e942b7 RM	521	AR_MCI_CONT_RSSI_POWER);
19686ddf MSS	522
	523	mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_INFO;
	524
26e942b7 RM	525	ath_dbg(common, MCI,
	526	"MCI CONT_INFO: (%s) pri = %d pwr = %d dBm\n",
	527	MS(mci_hw->cont_status, AR_MCI_CONT_TXRX) ?
	528	"tx" : "rx",
	529	MS(mci_hw->cont_status, AR_MCI_CONT_PRIORITY),
	530	value_dbm);
19686ddf MSS	531	}
19686ddf MSS	532
682dd04b	533	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_NACK)
19686ddf	534	mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_NACK;
19686ddf	535
682dd04b	536	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_RST)
19686ddf	537	mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_RST;
19686ddf MSS	538	}
	539
	540	if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) \|\|
	541	(mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT))
	542	mci_int &= ~(AR_MCI_INTERRUPT_RX_INVALID_HDR \|
	543	AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT);
19686ddf	544	}
e270e776 SM	545
	546	void ath_mci_enable(struct ath_softc *sc)
	547	{
	548	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	549
	550	if (!common->btcoex_enabled)
	551	return;
	552
	553	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
	554	sc->sc_ah->imask \|= ATH9K_INT_MCI;
	555	}