ath9k_hw: Set default MCI config for AR9565
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / mci.c
CommitLineData
7dc181c2
RM
1/*
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
9e25365f
MSS
17#include <linux/dma-mapping.h>
18#include <linux/slab.h>
19
7dc181c2
RM
20#include "ath9k.h"
21#include "mci.h"
22
a197b76c 23static const u8 ath_mci_duty_cycle[] = { 55, 50, 60, 70, 80, 85, 90, 95, 98 };
7dc181c2
RM
24
25static struct ath_mci_profile_info*
26ath_mci_find_profile(struct ath_mci_profile *mci,
27 struct ath_mci_profile_info *info)
28{
29 struct ath_mci_profile_info *entry;
30
9e2e0c84
RM
31 if (list_empty(&mci->info))
32 return NULL;
33
7dc181c2
RM
34 list_for_each_entry(entry, &mci->info, list) {
35 if (entry->conn_handle == info->conn_handle)
9e2e0c84 36 return entry;
7dc181c2 37 }
9e2e0c84 38 return NULL;
7dc181c2
RM
39}
40
41static bool ath_mci_add_profile(struct ath_common *common,
42 struct ath_mci_profile *mci,
43 struct ath_mci_profile_info *info)
44{
45 struct ath_mci_profile_info *entry;
db60428b 46 u8 voice_priority[] = { 110, 110, 110, 112, 110, 110, 114, 116, 118 };
7dc181c2
RM
47
48 if ((mci->num_sco == ATH_MCI_MAX_SCO_PROFILE) &&
682dd04b 49 (info->type == MCI_GPM_COEX_PROFILE_VOICE))
7dc181c2 50 return false;
7dc181c2
RM
51
52 if (((NUM_PROF(mci) - mci->num_sco) == ATH_MCI_MAX_ACL_PROFILE) &&
682dd04b 53 (info->type != MCI_GPM_COEX_PROFILE_VOICE))
7dc181c2 54 return false;
7dc181c2 55
3c7992e3 56 entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
9e2e0c84
RM
57 if (!entry)
58 return false;
7dc181c2 59
9e2e0c84
RM
60 memcpy(entry, info, 10);
61 INC_PROF(mci, info);
62 list_add_tail(&entry->list, &mci->info);
db60428b
RM
63 if (info->type == MCI_GPM_COEX_PROFILE_VOICE) {
64 if (info->voice_type < sizeof(voice_priority))
65 mci->voice_priority = voice_priority[info->voice_type];
66 else
67 mci->voice_priority = 110;
68 }
682dd04b 69
7dc181c2
RM
70 return true;
71}
72
73static void ath_mci_del_profile(struct ath_common *common,
74 struct ath_mci_profile *mci,
9e2e0c84 75 struct ath_mci_profile_info *entry)
7dc181c2 76{
682dd04b 77 if (!entry)
7dc181c2 78 return;
682dd04b 79
7dc181c2
RM
80 DEC_PROF(mci, entry);
81 list_del(&entry->list);
82 kfree(entry);
83}
84
85void ath_mci_flush_profile(struct ath_mci_profile *mci)
86{
87 struct ath_mci_profile_info *info, *tinfo;
88
9e2e0c84 89 mci->aggr_limit = 0;
d92bb98f 90 mci->num_mgmt = 0;
9e2e0c84
RM
91
92 if (list_empty(&mci->info))
93 return;
94
7dc181c2
RM
95 list_for_each_entry_safe(info, tinfo, &mci->info, list) {
96 list_del(&info->list);
97 DEC_PROF(mci, info);
98 kfree(info);
99 }
7dc181c2
RM
100}
101
102static void ath_mci_adjust_aggr_limit(struct ath_btcoex *btcoex)
103{
104 struct ath_mci_profile *mci = &btcoex->mci;
105 u32 wlan_airtime = btcoex->btcoex_period *
106 (100 - btcoex->duty_cycle) / 100;
107
108 /*
109 * Scale: wlan_airtime is in ms, aggr_limit is in 0.25 ms.
110 * When wlan_airtime is less than 4ms, aggregation limit has to be
111 * adjusted half of wlan_airtime to ensure that the aggregation can fit
112 * without collision with BT traffic.
113 */
114 if ((wlan_airtime <= 4) &&
115 (!mci->aggr_limit || (mci->aggr_limit > (2 * wlan_airtime))))
116 mci->aggr_limit = 2 * wlan_airtime;
117}
118
119static void ath_mci_update_scheme(struct ath_softc *sc)
120{
121 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
122 struct ath_btcoex *btcoex = &sc->btcoex;
123 struct ath_mci_profile *mci = &btcoex->mci;
0603143e 124 struct ath9k_hw_mci *mci_hw = &sc->sc_ah->btcoex_hw.mci;
7dc181c2
RM
125 struct ath_mci_profile_info *info;
126 u32 num_profile = NUM_PROF(mci);
127
0603143e
RM
128 if (mci_hw->config & ATH_MCI_CONFIG_DISABLE_TUNING)
129 goto skip_tuning;
130
9e62817b 131 mci->aggr_limit = 0;
a197b76c 132 btcoex->duty_cycle = ath_mci_duty_cycle[num_profile];
9e62817b
RM
133 btcoex->btcoex_period = ATH_MCI_DEF_BT_PERIOD;
134 if (NUM_PROF(mci))
135 btcoex->bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
136 else
137 btcoex->bt_stomp_type = mci->num_mgmt ? ATH_BTCOEX_STOMP_ALL :
138 ATH_BTCOEX_STOMP_LOW;
a197b76c 139
7dc181c2
RM
140 if (num_profile == 1) {
141 info = list_first_entry(&mci->info,
142 struct ath_mci_profile_info,
143 list);
0603143e
RM
144 if (mci->num_sco) {
145 if (info->T == 12)
146 mci->aggr_limit = 8;
147 else if (info->T == 6) {
148 mci->aggr_limit = 6;
149 btcoex->duty_cycle = 30;
9e62817b
RM
150 } else
151 mci->aggr_limit = 6;
d2182b69 152 ath_dbg(common, MCI,
0603143e
RM
153 "Single SCO, aggregation limit %d 1/4 ms\n",
154 mci->aggr_limit);
155 } else if (mci->num_pan || mci->num_other_acl) {
156 /*
157 * For single PAN/FTP profile, allocate 35% for BT
158 * to improve WLAN throughput.
159 */
160 btcoex->duty_cycle = 35;
161 btcoex->btcoex_period = 53;
d2182b69 162 ath_dbg(common, MCI,
0603143e
RM
163 "Single PAN/FTP bt period %d ms dutycycle %d\n",
164 btcoex->duty_cycle, btcoex->btcoex_period);
165 } else if (mci->num_hid) {
7dc181c2 166 btcoex->duty_cycle = 30;
0603143e 167 mci->aggr_limit = 6;
d2182b69 168 ath_dbg(common, MCI,
7dc181c2 169 "Multiple attempt/timeout single HID "
0603143e 170 "aggregation limit 1.5 ms dutycycle 30%%\n");
7dc181c2 171 }
0603143e
RM
172 } else if (num_profile == 2) {
173 if (mci->num_hid == 2)
174 btcoex->duty_cycle = 30;
7dc181c2 175 mci->aggr_limit = 6;
d2182b69 176 ath_dbg(common, MCI,
0603143e
RM
177 "Two BT profiles aggr limit 1.5 ms dutycycle %d%%\n",
178 btcoex->duty_cycle);
179 } else if (num_profile >= 3) {
180 mci->aggr_limit = 4;
181 ath_dbg(common, MCI,
182 "Three or more profiles aggregation limit 1 ms\n");
7dc181c2
RM
183 }
184
0603143e 185skip_tuning:
7dc181c2
RM
186 if (IS_CHAN_2GHZ(sc->sc_ah->curchan)) {
187 if (IS_CHAN_HT(sc->sc_ah->curchan))
188 ath_mci_adjust_aggr_limit(btcoex);
189 else
190 btcoex->btcoex_period >>= 1;
191 }
192
7dc181c2 193 ath9k_btcoex_timer_pause(sc);
c32cdbd8 194 ath9k_hw_btcoex_disable(sc->sc_ah);
7dc181c2
RM
195
196 if (IS_CHAN_5GHZ(sc->sc_ah->curchan))
197 return;
198
a197b76c 199 btcoex->duty_cycle += (mci->num_bdr ? ATH_MCI_BDR_DUTY_CYCLE : 0);
7dc181c2
RM
200 if (btcoex->duty_cycle > ATH_MCI_MAX_DUTY_CYCLE)
201 btcoex->duty_cycle = ATH_MCI_MAX_DUTY_CYCLE;
202
dfd0587a 203 btcoex->btcoex_no_stomp = btcoex->btcoex_period * 1000 *
682dd04b 204 (100 - btcoex->duty_cycle) / 100;
7dc181c2
RM
205
206 ath9k_hw_btcoex_enable(sc->sc_ah);
207 ath9k_btcoex_timer_resume(sc);
208}
209
83ad49a9
RM
210static void ath_mci_wait_btcal_done(struct ath_softc *sc)
211{
212 struct ath_hw *ah = sc->sc_ah;
213
214 /* Stop tx & rx */
215 ieee80211_stop_queues(sc->hw);
216 ath_stoprecv(sc);
217 ath_drain_all_txq(sc, false);
218
219 /* Wait for cal done */
220 ar9003_mci_start_reset(ah, ah->curchan);
221
222 /* Resume tx & rx */
223 ath_startrecv(sc);
224 ieee80211_wake_queues(sc->hw);
225}
226
19686ddf
MSS
227static void ath_mci_cal_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
228{
229 struct ath_hw *ah = sc->sc_ah;
230 struct ath_common *common = ath9k_hw_common(ah);
6d97be48 231 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
19686ddf
MSS
232 u32 payload[4] = {0, 0, 0, 0};
233
234 switch (opcode) {
235 case MCI_GPM_BT_CAL_REQ:
6d97be48 236 if (mci_hw->bt_state == MCI_BT_AWAKE) {
4653356f 237 mci_hw->bt_state = MCI_BT_CAL_START;
83ad49a9 238 ath_mci_wait_btcal_done(sc);
682dd04b 239 }
6d97be48 240 ath_dbg(common, MCI, "MCI State : %d\n", mci_hw->bt_state);
19686ddf 241 break;
19686ddf 242 case MCI_GPM_BT_CAL_GRANT:
19686ddf
MSS
243 MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_DONE);
244 ar9003_mci_send_message(sc->sc_ah, MCI_GPM, 0, payload,
245 16, false, true);
246 break;
19686ddf 247 default:
682dd04b 248 ath_dbg(common, MCI, "Unknown GPM CAL message\n");
19686ddf
MSS
249 break;
250 }
251}
252
3c7992e3
RM
253static void ath9k_mci_work(struct work_struct *work)
254{
255 struct ath_softc *sc = container_of(work, struct ath_softc, mci_work);
256
257 ath_mci_update_scheme(sc);
258}
259
db60428b
RM
260static void ath_mci_update_stomp_txprio(u8 cur_txprio, u8 *stomp_prio)
261{
262 if (cur_txprio < stomp_prio[ATH_BTCOEX_STOMP_NONE])
263 stomp_prio[ATH_BTCOEX_STOMP_NONE] = cur_txprio;
264
265 if (cur_txprio > stomp_prio[ATH_BTCOEX_STOMP_ALL])
266 stomp_prio[ATH_BTCOEX_STOMP_ALL] = cur_txprio;
267
268 if ((cur_txprio > ATH_MCI_HI_PRIO) &&
269 (cur_txprio < stomp_prio[ATH_BTCOEX_STOMP_LOW]))
270 stomp_prio[ATH_BTCOEX_STOMP_LOW] = cur_txprio;
271}
272
273static void ath_mci_set_concur_txprio(struct ath_softc *sc)
274{
275 struct ath_btcoex *btcoex = &sc->btcoex;
276 struct ath_mci_profile *mci = &btcoex->mci;
277 u8 stomp_txprio[] = { 0, 0, 0, 0 }; /* all, low, none, low_ftp */
278
279 if (mci->num_mgmt) {
280 stomp_txprio[ATH_BTCOEX_STOMP_ALL] = ATH_MCI_INQUIRY_PRIO;
281 if (!mci->num_pan && !mci->num_other_acl)
282 stomp_txprio[ATH_BTCOEX_STOMP_NONE] =
283 ATH_MCI_INQUIRY_PRIO;
284 } else {
285 u8 prof_prio[] = { 50, 90, 94, 52 };/* RFCOMM, A2DP, HID, PAN */
286
287 stomp_txprio[ATH_BTCOEX_STOMP_LOW] =
288 stomp_txprio[ATH_BTCOEX_STOMP_NONE] = 0xff;
289
290 if (mci->num_sco)
291 ath_mci_update_stomp_txprio(mci->voice_priority,
292 stomp_txprio);
293 if (mci->num_other_acl)
294 ath_mci_update_stomp_txprio(prof_prio[0], stomp_txprio);
295 if (mci->num_a2dp)
296 ath_mci_update_stomp_txprio(prof_prio[1], stomp_txprio);
297 if (mci->num_hid)
298 ath_mci_update_stomp_txprio(prof_prio[2], stomp_txprio);
299 if (mci->num_pan)
300 ath_mci_update_stomp_txprio(prof_prio[3], stomp_txprio);
301
302 if (stomp_txprio[ATH_BTCOEX_STOMP_NONE] == 0xff)
303 stomp_txprio[ATH_BTCOEX_STOMP_NONE] = 0;
304
305 if (stomp_txprio[ATH_BTCOEX_STOMP_LOW] == 0xff)
306 stomp_txprio[ATH_BTCOEX_STOMP_LOW] = 0;
307 }
308 ath9k_hw_btcoex_set_concur_txprio(sc->sc_ah, stomp_txprio);
309}
310
7a034146
RM
311static u8 ath_mci_process_profile(struct ath_softc *sc,
312 struct ath_mci_profile_info *info)
7dc181c2
RM
313{
314 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
315 struct ath_btcoex *btcoex = &sc->btcoex;
316 struct ath_mci_profile *mci = &btcoex->mci;
9e2e0c84
RM
317 struct ath_mci_profile_info *entry = NULL;
318
319 entry = ath_mci_find_profile(mci, info);
305dd09f
BS
320 if (entry) {
321 /*
322 * Two MCI interrupts are generated while connecting to
323 * headset and A2DP profile, but only one MCI interrupt
324 * is generated with last added profile type while disconnecting
325 * both profiles.
326 * So while adding second profile type decrement
327 * the first one.
328 */
329 if (entry->type != info->type) {
330 DEC_PROF(mci, entry);
331 INC_PROF(mci, info);
332 }
9e2e0c84 333 memcpy(entry, info, 10);
305dd09f 334 }
7dc181c2
RM
335
336 if (info->start) {
9e2e0c84 337 if (!entry && !ath_mci_add_profile(common, mci, info))
7a034146 338 return 0;
7dc181c2 339 } else
9e2e0c84 340 ath_mci_del_profile(common, mci, entry);
7dc181c2 341
db60428b 342 ath_mci_set_concur_txprio(sc);
7a034146 343 return 1;
7dc181c2
RM
344}
345
7a034146
RM
346static u8 ath_mci_process_status(struct ath_softc *sc,
347 struct ath_mci_profile_status *status)
7dc181c2 348{
7dc181c2
RM
349 struct ath_btcoex *btcoex = &sc->btcoex;
350 struct ath_mci_profile *mci = &btcoex->mci;
351 struct ath_mci_profile_info info;
352 int i = 0, old_num_mgmt = mci->num_mgmt;
353
354 /* Link status type are not handled */
682dd04b 355 if (status->is_link)
7a034146 356 return 0;
7dc181c2 357
7dc181c2 358 info.conn_handle = status->conn_handle;
682dd04b 359 if (ath_mci_find_profile(mci, &info))
7a034146 360 return 0;
682dd04b
SM
361
362 if (status->conn_handle >= ATH_MCI_MAX_PROFILE)
7a034146 363 return 0;
682dd04b 364
7dc181c2
RM
365 if (status->is_critical)
366 __set_bit(status->conn_handle, mci->status);
367 else
368 __clear_bit(status->conn_handle, mci->status);
369
370 mci->num_mgmt = 0;
371 do {
372 if (test_bit(i, mci->status))
373 mci->num_mgmt++;
374 } while (++i < ATH_MCI_MAX_PROFILE);
375
db60428b 376 ath_mci_set_concur_txprio(sc);
7dc181c2 377 if (old_num_mgmt != mci->num_mgmt)
7a034146
RM
378 return 1;
379
380 return 0;
7dc181c2 381}
9e25365f 382
19686ddf
MSS
383static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
384{
385 struct ath_hw *ah = sc->sc_ah;
386 struct ath_mci_profile_info profile_info;
387 struct ath_mci_profile_status profile_status;
388 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
7a034146 389 u8 major, minor, update_scheme = 0;
19686ddf
MSS
390 u32 seq_num;
391
d92bb98f
RM
392 if (ar9003_mci_state(ah, MCI_STATE_NEED_FLUSH_BT_INFO) &&
393 ar9003_mci_state(ah, MCI_STATE_ENABLE)) {
394 ath_dbg(common, MCI, "(MCI) Need to flush BT profiles\n");
395 ath_mci_flush_profile(&sc->btcoex.mci);
396 ar9003_mci_state(ah, MCI_STATE_SEND_STATUS_QUERY);
397 }
398
19686ddf 399 switch (opcode) {
19686ddf 400 case MCI_GPM_COEX_VERSION_QUERY:
b98ccec0 401 ar9003_mci_state(ah, MCI_STATE_SEND_WLAN_COEX_VERSION);
19686ddf 402 break;
19686ddf 403 case MCI_GPM_COEX_VERSION_RESPONSE:
19686ddf
MSS
404 major = *(rx_payload + MCI_GPM_COEX_B_MAJOR_VERSION);
405 minor = *(rx_payload + MCI_GPM_COEX_B_MINOR_VERSION);
e1763d3f 406 ar9003_mci_set_bt_version(ah, major, minor);
19686ddf 407 break;
19686ddf 408 case MCI_GPM_COEX_STATUS_QUERY:
2d340ac8 409 ar9003_mci_send_wlan_channels(ah);
19686ddf 410 break;
19686ddf 411 case MCI_GPM_COEX_BT_PROFILE_INFO:
19686ddf
MSS
412 memcpy(&profile_info,
413 (rx_payload + MCI_GPM_COEX_B_PROFILE_TYPE), 10);
414
682dd04b
SM
415 if ((profile_info.type == MCI_GPM_COEX_PROFILE_UNKNOWN) ||
416 (profile_info.type >= MCI_GPM_COEX_PROFILE_MAX)) {
d2182b69 417 ath_dbg(common, MCI,
682dd04b 418 "Illegal profile type = %d, state = %d\n",
d2182b69 419 profile_info.type,
19686ddf
MSS
420 profile_info.start);
421 break;
422 }
423
7a034146 424 update_scheme += ath_mci_process_profile(sc, &profile_info);
19686ddf 425 break;
19686ddf
MSS
426 case MCI_GPM_COEX_BT_STATUS_UPDATE:
427 profile_status.is_link = *(rx_payload +
428 MCI_GPM_COEX_B_STATUS_TYPE);
429 profile_status.conn_handle = *(rx_payload +
430 MCI_GPM_COEX_B_STATUS_LINKID);
431 profile_status.is_critical = *(rx_payload +
432 MCI_GPM_COEX_B_STATUS_STATE);
433
434 seq_num = *((u32 *)(rx_payload + 12));
d2182b69 435 ath_dbg(common, MCI,
d8fffb4a 436 "BT_Status_Update: is_link=%d, linkId=%d, state=%d, SEQ=%u\n",
19686ddf
MSS
437 profile_status.is_link, profile_status.conn_handle,
438 profile_status.is_critical, seq_num);
439
7a034146 440 update_scheme += ath_mci_process_status(sc, &profile_status);
19686ddf 441 break;
19686ddf 442 default:
682dd04b 443 ath_dbg(common, MCI, "Unknown GPM COEX message = 0x%02x\n", opcode);
19686ddf
MSS
444 break;
445 }
7a034146
RM
446 if (update_scheme)
447 ieee80211_queue_work(sc->hw, &sc->mci_work);
19686ddf 448}
9e25365f 449
9e25365f
MSS
450int ath_mci_setup(struct ath_softc *sc)
451{
452 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
453 struct ath_mci_coex *mci = &sc->mci_coex;
ea510e4b 454 struct ath_mci_buf *buf = &mci->sched_buf;
69c6ac60 455 int ret;
9e25365f 456
ea510e4b
SM
457 buf->bf_addr = dma_alloc_coherent(sc->dev,
458 ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
459 &buf->bf_paddr, GFP_KERNEL);
9e25365f 460
ea510e4b 461 if (buf->bf_addr == NULL) {
d2182b69 462 ath_dbg(common, FATAL, "MCI buffer alloc failed\n");
ea510e4b 463 return -ENOMEM;
9e25365f
MSS
464 }
465
ea510e4b
SM
466 memset(buf->bf_addr, MCI_GPM_RSVD_PATTERN,
467 ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE);
9e25365f 468
ea510e4b 469 mci->sched_buf.bf_len = ATH_MCI_SCHED_BUF_SIZE;
9e25365f
MSS
470
471 mci->gpm_buf.bf_len = ATH_MCI_GPM_BUF_SIZE;
ea510e4b 472 mci->gpm_buf.bf_addr = (u8 *)mci->sched_buf.bf_addr + mci->sched_buf.bf_len;
9e25365f
MSS
473 mci->gpm_buf.bf_paddr = mci->sched_buf.bf_paddr + mci->sched_buf.bf_len;
474
69c6ac60
SM
475 ret = ar9003_mci_setup(sc->sc_ah, mci->gpm_buf.bf_paddr,
476 mci->gpm_buf.bf_addr, (mci->gpm_buf.bf_len >> 4),
477 mci->sched_buf.bf_paddr);
478 if (ret) {
479 ath_err(common, "Failed to initialize MCI\n");
480 return ret;
481 }
ea510e4b 482
3c7992e3 483 INIT_WORK(&sc->mci_work, ath9k_mci_work);
ea510e4b
SM
484 ath_dbg(common, MCI, "MCI Initialized\n");
485
486 return 0;
9e25365f
MSS
487}
488
489void ath_mci_cleanup(struct ath_softc *sc)
490{
ea510e4b 491 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
9e25365f
MSS
492 struct ath_hw *ah = sc->sc_ah;
493 struct ath_mci_coex *mci = &sc->mci_coex;
ea510e4b 494 struct ath_mci_buf *buf = &mci->sched_buf;
9e25365f 495
ea510e4b
SM
496 if (buf->bf_addr)
497 dma_free_coherent(sc->dev,
498 ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
499 buf->bf_addr, buf->bf_paddr);
500
9e25365f 501 ar9003_mci_cleanup(ah);
ea510e4b
SM
502
503 ath_dbg(common, MCI, "MCI De-Initialized\n");
9e25365f 504}
19686ddf
MSS
505
506void ath_mci_intr(struct ath_softc *sc)
507{
508 struct ath_mci_coex *mci = &sc->mci_coex;
509 struct ath_hw *ah = sc->sc_ah;
510 struct ath_common *common = ath9k_hw_common(ah);
6d97be48 511 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
19686ddf
MSS
512 u32 mci_int, mci_int_rxmsg;
513 u32 offset, subtype, opcode;
514 u32 *pgpm;
515 u32 more_data = MCI_GPM_MORE;
516 bool skip_gpm = false;
517
518 ar9003_mci_get_interrupt(sc->sc_ah, &mci_int, &mci_int_rxmsg);
519
b98ccec0 520 if (ar9003_mci_state(ah, MCI_STATE_ENABLE) == 0) {
506847ad 521 ar9003_mci_get_next_gpm_offset(ah, true, NULL);
19686ddf
MSS
522 return;
523 }
524
525 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) {
526 u32 payload[4] = { 0xffffffff, 0xffffffff,
527 0xffffffff, 0xffffff00};
528
529 /*
530 * The following REMOTE_RESET and SYS_WAKING used to sent
531 * only when BT wake up. Now they are always sent, as a
532 * recovery method to reset BT MCI's RX alignment.
533 */
19686ddf
MSS
534 ar9003_mci_send_message(ah, MCI_REMOTE_RESET, 0,
535 payload, 16, true, false);
19686ddf
MSS
536 ar9003_mci_send_message(ah, MCI_SYS_WAKING, 0,
537 NULL, 0, true, false);
538
539 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE;
b98ccec0 540 ar9003_mci_state(ah, MCI_STATE_RESET_REQ_WAKE);
19686ddf
MSS
541
542 /*
543 * always do this for recovery and 2G/5G toggling and LNA_TRANS
544 */
b98ccec0 545 ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE);
19686ddf
MSS
546 }
547
19686ddf
MSS
548 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING) {
549 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING;
550
6d97be48 551 if ((mci_hw->bt_state == MCI_BT_SLEEP) &&
b98ccec0
RM
552 (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP) !=
553 MCI_BT_SLEEP))
554 ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE);
19686ddf
MSS
555 }
556
557 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) {
19686ddf
MSS
558 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING;
559
6d97be48 560 if ((mci_hw->bt_state == MCI_BT_AWAKE) &&
b98ccec0
RM
561 (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP) !=
562 MCI_BT_AWAKE))
9330969b 563 mci_hw->bt_state = MCI_BT_SLEEP;
19686ddf
MSS
564 }
565
566 if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
567 (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) {
b98ccec0 568 ar9003_mci_state(ah, MCI_STATE_RECOVER_RX);
19686ddf
MSS
569 skip_gpm = true;
570 }
571
572 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO) {
19686ddf 573 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO;
b98ccec0 574 offset = ar9003_mci_state(ah, MCI_STATE_LAST_SCHD_MSG_OFFSET);
19686ddf
MSS
575 }
576
577 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_GPM) {
19686ddf
MSS
578 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_GPM;
579
580 while (more_data == MCI_GPM_MORE) {
581
582 pgpm = mci->gpm_buf.bf_addr;
506847ad
RM
583 offset = ar9003_mci_get_next_gpm_offset(ah, false,
584 &more_data);
19686ddf
MSS
585
586 if (offset == MCI_GPM_INVALID)
587 break;
588
589 pgpm += (offset >> 2);
590
591 /*
592 * The first dword is timer.
593 * The real data starts from 2nd dword.
594 */
19686ddf
MSS
595 subtype = MCI_GPM_TYPE(pgpm);
596 opcode = MCI_GPM_OPCODE(pgpm);
597
682dd04b
SM
598 if (skip_gpm)
599 goto recycle;
600
601 if (MCI_GPM_IS_CAL_TYPE(subtype)) {
602 ath_mci_cal_msg(sc, subtype, (u8 *)pgpm);
603 } else {
604 switch (subtype) {
605 case MCI_GPM_COEX_AGENT:
606 ath_mci_msg(sc, opcode, (u8 *)pgpm);
607 break;
608 default:
609 break;
19686ddf
MSS
610 }
611 }
682dd04b 612 recycle:
19686ddf
MSS
613 MCI_GPM_RECYCLE(pgpm);
614 }
615 }
616
617 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_HW_MSG_MASK) {
19686ddf
MSS
618 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL)
619 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL;
620
682dd04b 621 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_INFO)
19686ddf 622 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_INFO;
19686ddf
MSS
623
624 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO) {
26e942b7
RM
625 int value_dbm = MS(mci_hw->cont_status,
626 AR_MCI_CONT_RSSI_POWER);
19686ddf
MSS
627
628 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_INFO;
629
26e942b7
RM
630 ath_dbg(common, MCI,
631 "MCI CONT_INFO: (%s) pri = %d pwr = %d dBm\n",
632 MS(mci_hw->cont_status, AR_MCI_CONT_TXRX) ?
633 "tx" : "rx",
634 MS(mci_hw->cont_status, AR_MCI_CONT_PRIORITY),
635 value_dbm);
19686ddf
MSS
636 }
637
682dd04b 638 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_NACK)
19686ddf 639 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_NACK;
19686ddf 640
682dd04b 641 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_RST)
19686ddf 642 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_RST;
19686ddf
MSS
643 }
644
645 if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
d92bb98f 646 (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) {
19686ddf
MSS
647 mci_int &= ~(AR_MCI_INTERRUPT_RX_INVALID_HDR |
648 AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT);
d92bb98f
RM
649 ath_mci_msg(sc, MCI_GPM_COEX_NOOP, NULL);
650 }
19686ddf 651}
e270e776
SM
652
653void ath_mci_enable(struct ath_softc *sc)
654{
655 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
656
657 if (!common->btcoex_enabled)
658 return;
659
660 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
661 sc->sc_ah->imask |= ATH9K_INT_MCI;
662}
50072ebc
RM
663
664void ath9k_mci_update_wlan_channels(struct ath_softc *sc, bool allow_all)
665{
666 struct ath_hw *ah = sc->sc_ah;
667 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
668 struct ath9k_channel *chan = ah->curchan;
669 u32 channelmap[] = {0x00000000, 0xffff0000, 0xffffffff, 0x7fffffff};
670 int i;
671 s16 chan_start, chan_end;
672 u16 wlan_chan;
673
674 if (!chan || !IS_CHAN_2GHZ(chan))
675 return;
676
677 if (allow_all)
678 goto send_wlan_chan;
679
680 wlan_chan = chan->channel - 2402;
681
682 chan_start = wlan_chan - 10;
683 chan_end = wlan_chan + 10;
684
685 if (chan->chanmode == CHANNEL_G_HT40PLUS)
686 chan_end += 20;
687 else if (chan->chanmode == CHANNEL_G_HT40MINUS)
688 chan_start -= 20;
689
690 /* adjust side band */
691 chan_start -= 7;
692 chan_end += 7;
693
694 if (chan_start <= 0)
695 chan_start = 0;
696 if (chan_end >= ATH_MCI_NUM_BT_CHANNELS)
697 chan_end = ATH_MCI_NUM_BT_CHANNELS - 1;
698
699 ath_dbg(ath9k_hw_common(ah), MCI,
700 "WLAN current channel %d mask BT channel %d - %d\n",
701 wlan_chan, chan_start, chan_end);
702
703 for (i = chan_start; i < chan_end; i++)
704 MCI_GPM_CLR_CHANNEL_BIT(&channelmap, i);
705
706send_wlan_chan:
707 /* update and send wlan channels info to BT */
708 for (i = 0; i < 4; i++)
709 mci->wlan_channels[i] = channelmap[i];
710 ar9003_mci_send_wlan_channels(ah);
711 ar9003_mci_state(ah, MCI_STATE_SEND_VERSION_QUERY);
712}
e82cb03f
RM
713
714void ath9k_mci_set_txpower(struct ath_softc *sc, bool setchannel,
715 bool concur_tx)
716{
717 struct ath_hw *ah = sc->sc_ah;
718 struct ath9k_hw_mci *mci_hw = &sc->sc_ah->btcoex_hw.mci;
719 bool old_concur_tx = mci_hw->concur_tx;
720
721 if (!(mci_hw->config & ATH_MCI_CONFIG_CONCUR_TX)) {
722 mci_hw->concur_tx = false;
723 return;
724 }
725
726 if (!IS_CHAN_2GHZ(ah->curchan))
727 return;
728
729 if (setchannel) {
730 struct ath9k_hw_cal_data *caldata = &sc->caldata;
731 if ((caldata->chanmode == CHANNEL_G_HT40PLUS) &&
732 (ah->curchan->channel > caldata->channel) &&
733 (ah->curchan->channel <= caldata->channel + 20))
734 return;
735 if ((caldata->chanmode == CHANNEL_G_HT40MINUS) &&
736 (ah->curchan->channel < caldata->channel) &&
737 (ah->curchan->channel >= caldata->channel - 20))
738 return;
739 mci_hw->concur_tx = false;
740 } else
741 mci_hw->concur_tx = concur_tx;
742
743 if (old_concur_tx != mci_hw->concur_tx)
744 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false);
745}
746
747void ath9k_mci_update_rssi(struct ath_softc *sc)
748{
749 struct ath_hw *ah = sc->sc_ah;
750 struct ath_btcoex *btcoex = &sc->btcoex;
751 struct ath9k_hw_mci *mci_hw = &sc->sc_ah->btcoex_hw.mci;
752
753 if (!(mci_hw->config & ATH_MCI_CONFIG_CONCUR_TX))
754 return;
755
756 if (ah->stats.avgbrssi >= 40) {
757 if (btcoex->rssi_count < 0)
758 btcoex->rssi_count = 0;
759 if (++btcoex->rssi_count >= ATH_MCI_CONCUR_TX_SWITCH) {
760 btcoex->rssi_count = 0;
761 ath9k_mci_set_txpower(sc, false, true);
762 }
763 } else {
764 if (btcoex->rssi_count > 0)
765 btcoex->rssi_count = 0;
766 if (--btcoex->rssi_count <= -ATH_MCI_CONCUR_TX_SWITCH) {
767 btcoex->rssi_count = 0;
768 ath9k_mci_set_txpower(sc, false, false);
769 }
770 }
771}
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