[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / mci.c

/*
 * Copyright (c) 2010-2011 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/dma-mapping.h>
#include <linux/slab.h>

#include "ath9k.h"
#include "mci.h"

static const u8 ath_mci_duty_cycle[] = { 55, 50, 60, 70, 80, 85, 90, 95, 98 };

static struct ath_mci_profile_info*
ath_mci_find_profile(struct ath_mci_profile *mci,
		     struct ath_mci_profile_info *info)
{
	struct ath_mci_profile_info *entry;

	if (list_empty(&mci->info))
		return NULL;

	list_for_each_entry(entry, &mci->info, list) {
		if (entry->conn_handle == info->conn_handle)
			return entry;
	}
	return NULL;
}

static bool ath_mci_add_profile(struct ath_common *common,
				struct ath_mci_profile *mci,
				struct ath_mci_profile_info *info)
{
	struct ath_mci_profile_info *entry;

	if ((mci->num_sco == ATH_MCI_MAX_SCO_PROFILE) &&
	    (info->type == MCI_GPM_COEX_PROFILE_VOICE))
		return false;

	if (((NUM_PROF(mci) - mci->num_sco) == ATH_MCI_MAX_ACL_PROFILE) &&
	    (info->type != MCI_GPM_COEX_PROFILE_VOICE))
		return false;

	entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
	if (!entry)
		return false;

	memcpy(entry, info, 10);
	INC_PROF(mci, info);
	list_add_tail(&entry->list, &mci->info);

	return true;
}

static void ath_mci_del_profile(struct ath_common *common,
				struct ath_mci_profile *mci,
				struct ath_mci_profile_info *entry)
{
	if (!entry)
		return;

	DEC_PROF(mci, entry);
	list_del(&entry->list);
	kfree(entry);
}

void ath_mci_flush_profile(struct ath_mci_profile *mci)
{
	struct ath_mci_profile_info *info, *tinfo;

	mci->aggr_limit = 0;
	mci->num_mgmt = 0;

	if (list_empty(&mci->info))
		return;

	list_for_each_entry_safe(info, tinfo, &mci->info, list) {
		list_del(&info->list);
		DEC_PROF(mci, info);
		kfree(info);
	}
}

static void ath_mci_adjust_aggr_limit(struct ath_btcoex *btcoex)
{
	struct ath_mci_profile *mci = &btcoex->mci;
	u32 wlan_airtime = btcoex->btcoex_period *
				(100 - btcoex->duty_cycle) / 100;

	/*
	 * Scale: wlan_airtime is in ms, aggr_limit is in 0.25 ms.
	 * When wlan_airtime is less than 4ms, aggregation limit has to be
	 * adjusted half of wlan_airtime to ensure that the aggregation can fit
	 * without collision with BT traffic.
	 */
	if ((wlan_airtime <= 4) &&
	    (!mci->aggr_limit || (mci->aggr_limit > (2 * wlan_airtime))))
		mci->aggr_limit = 2 * wlan_airtime;
}

static void ath_mci_update_scheme(struct ath_softc *sc)
{
	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	struct ath_btcoex *btcoex = &sc->btcoex;
	struct ath_mci_profile *mci = &btcoex->mci;
	struct ath9k_hw_mci *mci_hw = &sc->sc_ah->btcoex_hw.mci;
	struct ath_mci_profile_info *info;
	u32 num_profile = NUM_PROF(mci);

	if (mci_hw->config & ATH_MCI_CONFIG_DISABLE_TUNING)
		goto skip_tuning;

	mci->aggr_limit = 0;
	btcoex->duty_cycle = ath_mci_duty_cycle[num_profile];
	btcoex->btcoex_period = ATH_MCI_DEF_BT_PERIOD;
	if (NUM_PROF(mci))
		btcoex->bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
	else
		btcoex->bt_stomp_type = mci->num_mgmt ? ATH_BTCOEX_STOMP_ALL :
							ATH_BTCOEX_STOMP_LOW;

	if (num_profile == 1) {
		info = list_first_entry(&mci->info,
					struct ath_mci_profile_info,
					list);
		if (mci->num_sco) {
			if (info->T == 12)
				mci->aggr_limit = 8;
			else if (info->T == 6) {
				mci->aggr_limit = 6;
				btcoex->duty_cycle = 30;
			} else
				mci->aggr_limit = 6;
			ath_dbg(common, MCI,
				"Single SCO, aggregation limit %d 1/4 ms\n",
				mci->aggr_limit);
		} else if (mci->num_pan || mci->num_other_acl) {
			/*
			 * For single PAN/FTP profile, allocate 35% for BT
			 * to improve WLAN throughput.
			 */
			btcoex->duty_cycle = 35;
			btcoex->btcoex_period = 53;
			ath_dbg(common, MCI,
				"Single PAN/FTP bt period %d ms dutycycle %d\n",
				btcoex->duty_cycle, btcoex->btcoex_period);
		} else if (mci->num_hid) {
			btcoex->duty_cycle = 30;
			mci->aggr_limit = 6;
			ath_dbg(common, MCI,
				"Multiple attempt/timeout single HID "
				"aggregation limit 1.5 ms dutycycle 30%%\n");
		}
	} else if (num_profile == 2) {
		if (mci->num_hid == 2)
			btcoex->duty_cycle = 30;
		mci->aggr_limit = 6;
		ath_dbg(common, MCI,
			"Two BT profiles aggr limit 1.5 ms dutycycle %d%%\n",
			btcoex->duty_cycle);
	} else if (num_profile >= 3) {
		mci->aggr_limit = 4;
		ath_dbg(common, MCI,
			"Three or more profiles aggregation limit 1 ms\n");
	}

skip_tuning:
	if (IS_CHAN_2GHZ(sc->sc_ah->curchan)) {
		if (IS_CHAN_HT(sc->sc_ah->curchan))
			ath_mci_adjust_aggr_limit(btcoex);
		else
			btcoex->btcoex_period >>= 1;
	}

	ath9k_btcoex_timer_pause(sc);
	ath9k_hw_btcoex_disable(sc->sc_ah);

	if (IS_CHAN_5GHZ(sc->sc_ah->curchan))
		return;

	btcoex->duty_cycle += (mci->num_bdr ? ATH_MCI_BDR_DUTY_CYCLE : 0);
	if (btcoex->duty_cycle > ATH_MCI_MAX_DUTY_CYCLE)
		btcoex->duty_cycle = ATH_MCI_MAX_DUTY_CYCLE;

	btcoex->btcoex_no_stomp =  btcoex->btcoex_period * 1000 *
		(100 - btcoex->duty_cycle) / 100;

	ath9k_hw_btcoex_enable(sc->sc_ah);
	ath9k_btcoex_timer_resume(sc);
}

static void ath_mci_wait_btcal_done(struct ath_softc *sc)
{
	struct ath_hw *ah = sc->sc_ah;

	/* Stop tx & rx */
	ieee80211_stop_queues(sc->hw);
	ath_stoprecv(sc);
	ath_drain_all_txq(sc, false);

	/* Wait for cal done */
	ar9003_mci_start_reset(ah, ah->curchan);

	/* Resume tx & rx */
	ath_startrecv(sc);
	ieee80211_wake_queues(sc->hw);
}

static void ath_mci_cal_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
{
	struct ath_hw *ah = sc->sc_ah;
	struct ath_common *common = ath9k_hw_common(ah);
	struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
	u32 payload[4] = {0, 0, 0, 0};

	switch (opcode) {
	case MCI_GPM_BT_CAL_REQ:
		if (mci_hw->bt_state == MCI_BT_AWAKE) {
			mci_hw->bt_state = MCI_BT_CAL_START;
			ath_mci_wait_btcal_done(sc);
		}
		ath_dbg(common, MCI, "MCI State : %d\n", mci_hw->bt_state);
		break;
	case MCI_GPM_BT_CAL_GRANT:
		MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_DONE);
		ar9003_mci_send_message(sc->sc_ah, MCI_GPM, 0, payload,
					16, false, true);
		break;
	default:
		ath_dbg(common, MCI, "Unknown GPM CAL message\n");
		break;
	}
}

static void ath9k_mci_work(struct work_struct *work)
{
	struct ath_softc *sc = container_of(work, struct ath_softc, mci_work);

	ath_mci_update_scheme(sc);
}

static void ath_mci_process_profile(struct ath_softc *sc,
				    struct ath_mci_profile_info *info)
{
	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	struct ath_btcoex *btcoex = &sc->btcoex;
	struct ath_mci_profile *mci = &btcoex->mci;
	struct ath_mci_profile_info *entry = NULL;

	entry = ath_mci_find_profile(mci, info);
	if (entry) {
		/*
		 * Two MCI interrupts are generated while connecting to
		 * headset and A2DP profile, but only one MCI interrupt
		 * is generated with last added profile type while disconnecting
		 * both profiles.
		 * So while adding second profile type decrement
		 * the first one.
		 */
		if (entry->type != info->type) {
			DEC_PROF(mci, entry);
			INC_PROF(mci, info);
		}
		memcpy(entry, info, 10);
	}

	if (info->start) {
		if (!entry && !ath_mci_add_profile(common, mci, info))
			return;
	} else
		ath_mci_del_profile(common, mci, entry);

	ieee80211_queue_work(sc->hw, &sc->mci_work);
}

static void ath_mci_process_status(struct ath_softc *sc,
				   struct ath_mci_profile_status *status)
{
	struct ath_btcoex *btcoex = &sc->btcoex;
	struct ath_mci_profile *mci = &btcoex->mci;
	struct ath_mci_profile_info info;
	int i = 0, old_num_mgmt = mci->num_mgmt;

	/* Link status type are not handled */
	if (status->is_link)
		return;

	info.conn_handle = status->conn_handle;
	if (ath_mci_find_profile(mci, &info))
		return;

	if (status->conn_handle >= ATH_MCI_MAX_PROFILE)
		return;

	if (status->is_critical)
		__set_bit(status->conn_handle, mci->status);
	else
		__clear_bit(status->conn_handle, mci->status);

	mci->num_mgmt = 0;
	do {
		if (test_bit(i, mci->status))
			mci->num_mgmt++;
	} while (++i < ATH_MCI_MAX_PROFILE);

	if (old_num_mgmt != mci->num_mgmt)
		ieee80211_queue_work(sc->hw, &sc->mci_work);
}

static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
{
	struct ath_hw *ah = sc->sc_ah;
	struct ath_mci_profile_info profile_info;
	struct ath_mci_profile_status profile_status;
	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	u8 major, minor;
	u32 seq_num;

	if (ar9003_mci_state(ah, MCI_STATE_NEED_FLUSH_BT_INFO) &&
	    ar9003_mci_state(ah, MCI_STATE_ENABLE)) {
		ath_dbg(common, MCI, "(MCI) Need to flush BT profiles\n");
		ath_mci_flush_profile(&sc->btcoex.mci);
		ar9003_mci_state(ah, MCI_STATE_SEND_STATUS_QUERY);
	}

	switch (opcode) {
	case MCI_GPM_COEX_VERSION_QUERY:
		ar9003_mci_state(ah, MCI_STATE_SEND_WLAN_COEX_VERSION);
		break;
	case MCI_GPM_COEX_VERSION_RESPONSE:
		major = *(rx_payload + MCI_GPM_COEX_B_MAJOR_VERSION);
		minor = *(rx_payload + MCI_GPM_COEX_B_MINOR_VERSION);
		ar9003_mci_set_bt_version(ah, major, minor);
		break;
	case MCI_GPM_COEX_STATUS_QUERY:
		ar9003_mci_send_wlan_channels(ah);
		break;
	case MCI_GPM_COEX_BT_PROFILE_INFO:
		memcpy(&profile_info,
		       (rx_payload + MCI_GPM_COEX_B_PROFILE_TYPE), 10);

		if ((profile_info.type == MCI_GPM_COEX_PROFILE_UNKNOWN) ||
		    (profile_info.type >= MCI_GPM_COEX_PROFILE_MAX)) {
			ath_dbg(common, MCI,
				"Illegal profile type = %d, state = %d\n",
				profile_info.type,
				profile_info.start);
			break;
		}

		ath_mci_process_profile(sc, &profile_info);
		break;
	case MCI_GPM_COEX_BT_STATUS_UPDATE:
		profile_status.is_link = *(rx_payload +
					   MCI_GPM_COEX_B_STATUS_TYPE);
		profile_status.conn_handle = *(rx_payload +
					       MCI_GPM_COEX_B_STATUS_LINKID);
		profile_status.is_critical = *(rx_payload +
					       MCI_GPM_COEX_B_STATUS_STATE);

		seq_num = *((u32 *)(rx_payload + 12));
		ath_dbg(common, MCI,
			"BT_Status_Update: is_link=%d, linkId=%d, state=%d, SEQ=%u\n",
			profile_status.is_link, profile_status.conn_handle,
			profile_status.is_critical, seq_num);

		ath_mci_process_status(sc, &profile_status);
		break;
	default:
		ath_dbg(common, MCI, "Unknown GPM COEX message = 0x%02x\n", opcode);
		break;
	}
}

int ath_mci_setup(struct ath_softc *sc)
{
	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	struct ath_mci_coex *mci = &sc->mci_coex;
	struct ath_mci_buf *buf = &mci->sched_buf;

	buf->bf_addr = dma_alloc_coherent(sc->dev,
				  ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
				  &buf->bf_paddr, GFP_KERNEL);

	if (buf->bf_addr == NULL) {
		ath_dbg(common, FATAL, "MCI buffer alloc failed\n");
		return -ENOMEM;
	}

	memset(buf->bf_addr, MCI_GPM_RSVD_PATTERN,
	       ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE);

	mci->sched_buf.bf_len = ATH_MCI_SCHED_BUF_SIZE;

	mci->gpm_buf.bf_len = ATH_MCI_GPM_BUF_SIZE;
	mci->gpm_buf.bf_addr = (u8 *)mci->sched_buf.bf_addr + mci->sched_buf.bf_len;
	mci->gpm_buf.bf_paddr = mci->sched_buf.bf_paddr + mci->sched_buf.bf_len;

	ar9003_mci_setup(sc->sc_ah, mci->gpm_buf.bf_paddr,
			 mci->gpm_buf.bf_addr, (mci->gpm_buf.bf_len >> 4),
			 mci->sched_buf.bf_paddr);

	INIT_WORK(&sc->mci_work, ath9k_mci_work);
	ath_dbg(common, MCI, "MCI Initialized\n");

	return 0;
}

void ath_mci_cleanup(struct ath_softc *sc)
{
	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	struct ath_hw *ah = sc->sc_ah;
	struct ath_mci_coex *mci = &sc->mci_coex;
	struct ath_mci_buf *buf = &mci->sched_buf;

	if (buf->bf_addr)
		dma_free_coherent(sc->dev,
				  ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
				  buf->bf_addr, buf->bf_paddr);

	ar9003_mci_cleanup(ah);

	ath_dbg(common, MCI, "MCI De-Initialized\n");
}

void ath_mci_intr(struct ath_softc *sc)
{
	struct ath_mci_coex *mci = &sc->mci_coex;
	struct ath_hw *ah = sc->sc_ah;
	struct ath_common *common = ath9k_hw_common(ah);
	struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
	u32 mci_int, mci_int_rxmsg;
	u32 offset, subtype, opcode;
	u32 *pgpm;
	u32 more_data = MCI_GPM_MORE;
	bool skip_gpm = false;

	ar9003_mci_get_interrupt(sc->sc_ah, &mci_int, &mci_int_rxmsg);

	if (ar9003_mci_state(ah, MCI_STATE_ENABLE) == 0) {
		ar9003_mci_get_next_gpm_offset(ah, true, NULL);
		return;
	}

	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) {
		u32 payload[4] = { 0xffffffff, 0xffffffff,
				   0xffffffff, 0xffffff00};

		/*
		 * The following REMOTE_RESET and SYS_WAKING used to sent
		 * only when BT wake up. Now they are always sent, as a
		 * recovery method to reset BT MCI's RX alignment.
		 */
		ar9003_mci_send_message(ah, MCI_REMOTE_RESET, 0,
					payload, 16, true, false);
		ar9003_mci_send_message(ah, MCI_SYS_WAKING, 0,
					NULL, 0, true, false);

		mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE;
		ar9003_mci_state(ah, MCI_STATE_RESET_REQ_WAKE);

		/*
		 * always do this for recovery and 2G/5G toggling and LNA_TRANS
		 */
		ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE);
	}

	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING) {
		mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING;

		if ((mci_hw->bt_state == MCI_BT_SLEEP) &&
		    (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP) !=
		     MCI_BT_SLEEP))
			ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE);
	}

	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) {
		mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING;

		if ((mci_hw->bt_state == MCI_BT_AWAKE) &&
		    (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP) !=
		     MCI_BT_AWAKE))
			mci_hw->bt_state = MCI_BT_SLEEP;
	}

	if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
	    (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) {
		ar9003_mci_state(ah, MCI_STATE_RECOVER_RX);
		skip_gpm = true;
	}

	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO) {
		mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO;
		offset = ar9003_mci_state(ah, MCI_STATE_LAST_SCHD_MSG_OFFSET);
	}

	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_GPM) {
		mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_GPM;

		while (more_data == MCI_GPM_MORE) {

			pgpm = mci->gpm_buf.bf_addr;
			offset = ar9003_mci_get_next_gpm_offset(ah, false,
								&more_data);

			if (offset == MCI_GPM_INVALID)
				break;

			pgpm += (offset >> 2);

			/*
			 * The first dword is timer.
			 * The real data starts from 2nd dword.
			 */
			subtype = MCI_GPM_TYPE(pgpm);
			opcode = MCI_GPM_OPCODE(pgpm);

			if (skip_gpm)
				goto recycle;

			if (MCI_GPM_IS_CAL_TYPE(subtype)) {
				ath_mci_cal_msg(sc, subtype, (u8 *)pgpm);
			} else {
				switch (subtype) {
				case MCI_GPM_COEX_AGENT:
					ath_mci_msg(sc, opcode, (u8 *)pgpm);
					break;
				default:
					break;
				}
			}
		recycle:
			MCI_GPM_RECYCLE(pgpm);
		}
	}

	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_HW_MSG_MASK) {
		if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL)
			mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL;

		if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_INFO)
			mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_INFO;

		if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO) {
			int value_dbm = MS(mci_hw->cont_status,
					   AR_MCI_CONT_RSSI_POWER);

			mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_INFO;

			ath_dbg(common, MCI,
				"MCI CONT_INFO: (%s) pri = %d pwr = %d dBm\n",
				MS(mci_hw->cont_status, AR_MCI_CONT_TXRX) ?
				"tx" : "rx",
				MS(mci_hw->cont_status, AR_MCI_CONT_PRIORITY),
				value_dbm);
		}

		if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_NACK)
			mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_NACK;

		if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_RST)
			mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_RST;
	}

	if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
	    (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) {
		mci_int &= ~(AR_MCI_INTERRUPT_RX_INVALID_HDR |
			     AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT);
		ath_mci_msg(sc, MCI_GPM_COEX_NOOP, NULL);
	}
}

void ath_mci_enable(struct ath_softc *sc)
{
	struct ath_common *common = ath9k_hw_common(sc->sc_ah);

	if (!common->btcoex_enabled)
		return;

	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
		sc->sc_ah->imask |= ATH9K_INT_MCI;
}
Commit	Line	Data
7dc181c2 RM	1	/*
	2	* Copyright (c) 2010-2011 Atheros Communications Inc.
	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
9e25365f MSS	17	#include <linux/dma-mapping.h>
	18	#include <linux/slab.h>
	19
7dc181c2 RM	20	#include "ath9k.h"
	21	#include "mci.h"
	22
a197b76c	23	static const u8 ath_mci_duty_cycle[] = { 55, 50, 60, 70, 80, 85, 90, 95, 98 };
7dc181c2 RM	24
	25	static struct ath_mci_profile_info*
	26	ath_mci_find_profile(struct ath_mci_profile *mci,
	27	struct ath_mci_profile_info *info)
	28	{
	29	struct ath_mci_profile_info *entry;
	30
9e2e0c84 RM	31	if (list_empty(&mci->info))
	32	return NULL;
	33
7dc181c2 RM	34	list_for_each_entry(entry, &mci->info, list) {
7dc181c2 RM	35	if (entry->conn_handle == info->conn_handle)
9e2e0c84	36	return entry;
7dc181c2	37	}
9e2e0c84	38	return NULL;
7dc181c2 RM	39	}
	40
	41	static bool ath_mci_add_profile(struct ath_common *common,
	42	struct ath_mci_profile *mci,
	43	struct ath_mci_profile_info *info)
	44	{
	45	struct ath_mci_profile_info *entry;
	46
	47	if ((mci->num_sco == ATH_MCI_MAX_SCO_PROFILE) &&
682dd04b	48	(info->type == MCI_GPM_COEX_PROFILE_VOICE))
7dc181c2	49	return false;
7dc181c2 RM	50
7dc181c2 RM	51	if (((NUM_PROF(mci) - mci->num_sco) == ATH_MCI_MAX_ACL_PROFILE) &&
682dd04b	52	(info->type != MCI_GPM_COEX_PROFILE_VOICE))
7dc181c2	53	return false;
7dc181c2	54
3c7992e3	55	entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
9e2e0c84 RM	56	if (!entry)
9e2e0c84 RM	57	return false;
7dc181c2	58
9e2e0c84 RM	59	memcpy(entry, info, 10);
	60	INC_PROF(mci, info);
	61	list_add_tail(&entry->list, &mci->info);
682dd04b	62
7dc181c2 RM	63	return true;
	64	}
	65
	66	static void ath_mci_del_profile(struct ath_common *common,
	67	struct ath_mci_profile *mci,
9e2e0c84	68	struct ath_mci_profile_info *entry)
7dc181c2	69	{
682dd04b	70	if (!entry)
7dc181c2	71	return;
682dd04b	72
7dc181c2 RM	73	DEC_PROF(mci, entry);
	74	list_del(&entry->list);
	75	kfree(entry);
	76	}
	77
	78	void ath_mci_flush_profile(struct ath_mci_profile *mci)
	79	{
	80	struct ath_mci_profile_info info, tinfo;
	81
9e2e0c84	82	mci->aggr_limit = 0;
d92bb98f	83	mci->num_mgmt = 0;
9e2e0c84 RM	84
	85	if (list_empty(&mci->info))
	86	return;
	87
7dc181c2 RM	88	list_for_each_entry_safe(info, tinfo, &mci->info, list) {
	89	list_del(&info->list);
	90	DEC_PROF(mci, info);
	91	kfree(info);
	92	}
7dc181c2 RM	93	}
	94
	95	static void ath_mci_adjust_aggr_limit(struct ath_btcoex *btcoex)
	96	{
	97	struct ath_mci_profile *mci = &btcoex->mci;
	98	u32 wlan_airtime = btcoex->btcoex_period *
	99	(100 - btcoex->duty_cycle) / 100;
	100
	101	/*
	102	* Scale: wlan_airtime is in ms, aggr_limit is in 0.25 ms.
	103	* When wlan_airtime is less than 4ms, aggregation limit has to be
	104	* adjusted half of wlan_airtime to ensure that the aggregation can fit
	105	* without collision with BT traffic.
	106	*/
	107	if ((wlan_airtime <= 4) &&
	108	(!mci->aggr_limit \|\| (mci->aggr_limit > (2 * wlan_airtime))))
	109	mci->aggr_limit = 2 * wlan_airtime;
	110	}
	111
	112	static void ath_mci_update_scheme(struct ath_softc *sc)
	113	{
	114	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	115	struct ath_btcoex *btcoex = &sc->btcoex;
	116	struct ath_mci_profile *mci = &btcoex->mci;
0603143e	117	struct ath9k_hw_mci *mci_hw = &sc->sc_ah->btcoex_hw.mci;
7dc181c2 RM	118	struct ath_mci_profile_info *info;
	119	u32 num_profile = NUM_PROF(mci);
	120
0603143e RM	121	if (mci_hw->config & ATH_MCI_CONFIG_DISABLE_TUNING)
	122	goto skip_tuning;
	123
9e62817b	124	mci->aggr_limit = 0;
a197b76c	125	btcoex->duty_cycle = ath_mci_duty_cycle[num_profile];
9e62817b RM	126	btcoex->btcoex_period = ATH_MCI_DEF_BT_PERIOD;
	127	if (NUM_PROF(mci))
	128	btcoex->bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
	129	else
	130	btcoex->bt_stomp_type = mci->num_mgmt ? ATH_BTCOEX_STOMP_ALL :
	131	ATH_BTCOEX_STOMP_LOW;
a197b76c	132
7dc181c2 RM	133	if (num_profile == 1) {
	134	info = list_first_entry(&mci->info,
	135	struct ath_mci_profile_info,
	136	list);
0603143e RM	137	if (mci->num_sco) {
	138	if (info->T == 12)
	139	mci->aggr_limit = 8;
	140	else if (info->T == 6) {
	141	mci->aggr_limit = 6;
	142	btcoex->duty_cycle = 30;
9e62817b RM	143	} else
9e62817b RM	144	mci->aggr_limit = 6;
d2182b69	145	ath_dbg(common, MCI,
0603143e RM	146	"Single SCO, aggregation limit %d 1/4 ms\n",
	147	mci->aggr_limit);
	148	} else if (mci->num_pan \|\| mci->num_other_acl) {
	149	/*
	150	* For single PAN/FTP profile, allocate 35% for BT
	151	* to improve WLAN throughput.
	152	*/
	153	btcoex->duty_cycle = 35;
	154	btcoex->btcoex_period = 53;
d2182b69	155	ath_dbg(common, MCI,
0603143e RM	156	"Single PAN/FTP bt period %d ms dutycycle %d\n",
	157	btcoex->duty_cycle, btcoex->btcoex_period);
	158	} else if (mci->num_hid) {
7dc181c2	159	btcoex->duty_cycle = 30;
0603143e	160	mci->aggr_limit = 6;
d2182b69	161	ath_dbg(common, MCI,
7dc181c2	162	"Multiple attempt/timeout single HID "
0603143e	163	"aggregation limit 1.5 ms dutycycle 30%%\n");
7dc181c2	164	}
0603143e RM	165	} else if (num_profile == 2) {
	166	if (mci->num_hid == 2)
	167	btcoex->duty_cycle = 30;
7dc181c2	168	mci->aggr_limit = 6;
d2182b69	169	ath_dbg(common, MCI,
0603143e RM	170	"Two BT profiles aggr limit 1.5 ms dutycycle %d%%\n",
	171	btcoex->duty_cycle);
	172	} else if (num_profile >= 3) {
	173	mci->aggr_limit = 4;
	174	ath_dbg(common, MCI,
	175	"Three or more profiles aggregation limit 1 ms\n");
7dc181c2 RM	176	}
7dc181c2 RM	177
0603143e	178	skip_tuning:
7dc181c2 RM	179	if (IS_CHAN_2GHZ(sc->sc_ah->curchan)) {
	180	if (IS_CHAN_HT(sc->sc_ah->curchan))
	181	ath_mci_adjust_aggr_limit(btcoex);
	182	else
	183	btcoex->btcoex_period >>= 1;
	184	}
	185
7dc181c2	186	ath9k_btcoex_timer_pause(sc);
c32cdbd8	187	ath9k_hw_btcoex_disable(sc->sc_ah);
7dc181c2 RM	188
	189	if (IS_CHAN_5GHZ(sc->sc_ah->curchan))
	190	return;
	191
a197b76c	192	btcoex->duty_cycle += (mci->num_bdr ? ATH_MCI_BDR_DUTY_CYCLE : 0);
7dc181c2 RM	193	if (btcoex->duty_cycle > ATH_MCI_MAX_DUTY_CYCLE)
	194	btcoex->duty_cycle = ATH_MCI_MAX_DUTY_CYCLE;
	195
dfd0587a	196	btcoex->btcoex_no_stomp = btcoex->btcoex_period * 1000 *
682dd04b	197	(100 - btcoex->duty_cycle) / 100;
7dc181c2 RM	198
	199	ath9k_hw_btcoex_enable(sc->sc_ah);
	200	ath9k_btcoex_timer_resume(sc);
	201	}
	202
83ad49a9 RM	203	static void ath_mci_wait_btcal_done(struct ath_softc *sc)
	204	{
	205	struct ath_hw *ah = sc->sc_ah;
	206
	207	/* Stop tx & rx */
	208	ieee80211_stop_queues(sc->hw);
	209	ath_stoprecv(sc);
	210	ath_drain_all_txq(sc, false);
	211
	212	/* Wait for cal done */
	213	ar9003_mci_start_reset(ah, ah->curchan);
	214
	215	/* Resume tx & rx */
	216	ath_startrecv(sc);
	217	ieee80211_wake_queues(sc->hw);
	218	}
	219
19686ddf MSS	220	static void ath_mci_cal_msg(struct ath_softc sc, u8 opcode, u8 rx_payload)
	221	{
	222	struct ath_hw *ah = sc->sc_ah;
	223	struct ath_common *common = ath9k_hw_common(ah);
6d97be48	224	struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
19686ddf MSS	225	u32 payload[4] = {0, 0, 0, 0};
	226
	227	switch (opcode) {
	228	case MCI_GPM_BT_CAL_REQ:
6d97be48	229	if (mci_hw->bt_state == MCI_BT_AWAKE) {
4653356f	230	mci_hw->bt_state = MCI_BT_CAL_START;
83ad49a9	231	ath_mci_wait_btcal_done(sc);
682dd04b	232	}
6d97be48	233	ath_dbg(common, MCI, "MCI State : %d\n", mci_hw->bt_state);
19686ddf	234	break;
19686ddf	235	case MCI_GPM_BT_CAL_GRANT:
19686ddf MSS	236	MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_DONE);
	237	ar9003_mci_send_message(sc->sc_ah, MCI_GPM, 0, payload,
	238	16, false, true);
	239	break;
19686ddf	240	default:
682dd04b	241	ath_dbg(common, MCI, "Unknown GPM CAL message\n");
19686ddf MSS	242	break;
	243	}
	244	}
	245
3c7992e3 RM	246	static void ath9k_mci_work(struct work_struct *work)
	247	{
	248	struct ath_softc *sc = container_of(work, struct ath_softc, mci_work);
	249
	250	ath_mci_update_scheme(sc);
	251	}
	252
e5f0a276 FF	253	static void ath_mci_process_profile(struct ath_softc *sc,
e5f0a276 FF	254	struct ath_mci_profile_info *info)
7dc181c2 RM	255	{
	256	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	257	struct ath_btcoex *btcoex = &sc->btcoex;
	258	struct ath_mci_profile *mci = &btcoex->mci;
9e2e0c84 RM	259	struct ath_mci_profile_info *entry = NULL;
	260
	261	entry = ath_mci_find_profile(mci, info);
305dd09f BS	262	if (entry) {
	263	/*
	264	* Two MCI interrupts are generated while connecting to
	265	* headset and A2DP profile, but only one MCI interrupt
	266	* is generated with last added profile type while disconnecting
	267	* both profiles.
	268	* So while adding second profile type decrement
	269	* the first one.
	270	*/
	271	if (entry->type != info->type) {
	272	DEC_PROF(mci, entry);
	273	INC_PROF(mci, info);
	274	}
9e2e0c84	275	memcpy(entry, info, 10);
305dd09f	276	}
7dc181c2 RM	277
7dc181c2 RM	278	if (info->start) {
9e2e0c84	279	if (!entry && !ath_mci_add_profile(common, mci, info))
7dc181c2 RM	280	return;
7dc181c2 RM	281	} else
9e2e0c84	282	ath_mci_del_profile(common, mci, entry);
7dc181c2	283
3c7992e3	284	ieee80211_queue_work(sc->hw, &sc->mci_work);
7dc181c2 RM	285	}
7dc181c2 RM	286
e5f0a276 FF	287	static void ath_mci_process_status(struct ath_softc *sc,
e5f0a276 FF	288	struct ath_mci_profile_status *status)
7dc181c2	289	{
7dc181c2 RM	290	struct ath_btcoex *btcoex = &sc->btcoex;
	291	struct ath_mci_profile *mci = &btcoex->mci;
	292	struct ath_mci_profile_info info;
	293	int i = 0, old_num_mgmt = mci->num_mgmt;
	294
	295	/* Link status type are not handled */
682dd04b	296	if (status->is_link)
7dc181c2	297	return;
7dc181c2	298
7dc181c2	299	info.conn_handle = status->conn_handle;
682dd04b	300	if (ath_mci_find_profile(mci, &info))
7dc181c2	301	return;
682dd04b SM	302
682dd04b SM	303	if (status->conn_handle >= ATH_MCI_MAX_PROFILE)
7dc181c2	304	return;
682dd04b	305
7dc181c2 RM	306	if (status->is_critical)
	307	__set_bit(status->conn_handle, mci->status);
	308	else
	309	__clear_bit(status->conn_handle, mci->status);
	310
	311	mci->num_mgmt = 0;
	312	do {
	313	if (test_bit(i, mci->status))
	314	mci->num_mgmt++;
	315	} while (++i < ATH_MCI_MAX_PROFILE);
	316
	317	if (old_num_mgmt != mci->num_mgmt)
3c7992e3	318	ieee80211_queue_work(sc->hw, &sc->mci_work);
7dc181c2	319	}
9e25365f	320
19686ddf MSS	321	static void ath_mci_msg(struct ath_softc sc, u8 opcode, u8 rx_payload)
	322	{
	323	struct ath_hw *ah = sc->sc_ah;
	324	struct ath_mci_profile_info profile_info;
	325	struct ath_mci_profile_status profile_status;
	326	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
e1763d3f	327	u8 major, minor;
19686ddf MSS	328	u32 seq_num;
19686ddf MSS	329
d92bb98f RM	330	if (ar9003_mci_state(ah, MCI_STATE_NEED_FLUSH_BT_INFO) &&
	331	ar9003_mci_state(ah, MCI_STATE_ENABLE)) {
	332	ath_dbg(common, MCI, "(MCI) Need to flush BT profiles\n");
	333	ath_mci_flush_profile(&sc->btcoex.mci);
	334	ar9003_mci_state(ah, MCI_STATE_SEND_STATUS_QUERY);
	335	}
	336
19686ddf	337	switch (opcode) {
19686ddf	338	case MCI_GPM_COEX_VERSION_QUERY:
b98ccec0	339	ar9003_mci_state(ah, MCI_STATE_SEND_WLAN_COEX_VERSION);
19686ddf	340	break;
19686ddf	341	case MCI_GPM_COEX_VERSION_RESPONSE:
19686ddf MSS	342	major = *(rx_payload + MCI_GPM_COEX_B_MAJOR_VERSION);
19686ddf MSS	343	minor = *(rx_payload + MCI_GPM_COEX_B_MINOR_VERSION);
e1763d3f	344	ar9003_mci_set_bt_version(ah, major, minor);
19686ddf	345	break;
19686ddf	346	case MCI_GPM_COEX_STATUS_QUERY:
2d340ac8	347	ar9003_mci_send_wlan_channels(ah);
19686ddf	348	break;
19686ddf	349	case MCI_GPM_COEX_BT_PROFILE_INFO:
19686ddf MSS	350	memcpy(&profile_info,
	351	(rx_payload + MCI_GPM_COEX_B_PROFILE_TYPE), 10);
	352
682dd04b SM	353	if ((profile_info.type == MCI_GPM_COEX_PROFILE_UNKNOWN) \|\|
682dd04b SM	354	(profile_info.type >= MCI_GPM_COEX_PROFILE_MAX)) {
d2182b69	355	ath_dbg(common, MCI,
682dd04b	356	"Illegal profile type = %d, state = %d\n",
d2182b69	357	profile_info.type,
19686ddf MSS	358	profile_info.start);
	359	break;
	360	}
	361
	362	ath_mci_process_profile(sc, &profile_info);
	363	break;
19686ddf MSS	364	case MCI_GPM_COEX_BT_STATUS_UPDATE:
	365	profile_status.is_link = *(rx_payload +
	366	MCI_GPM_COEX_B_STATUS_TYPE);
	367	profile_status.conn_handle = *(rx_payload +
	368	MCI_GPM_COEX_B_STATUS_LINKID);
	369	profile_status.is_critical = *(rx_payload +
	370	MCI_GPM_COEX_B_STATUS_STATE);
	371
	372	seq_num = ((u32 )(rx_payload + 12));
d2182b69	373	ath_dbg(common, MCI,
d8fffb4a	374	"BT_Status_Update: is_link=%d, linkId=%d, state=%d, SEQ=%u\n",
19686ddf MSS	375	profile_status.is_link, profile_status.conn_handle,
	376	profile_status.is_critical, seq_num);
	377
	378	ath_mci_process_status(sc, &profile_status);
	379	break;
19686ddf	380	default:
682dd04b	381	ath_dbg(common, MCI, "Unknown GPM COEX message = 0x%02x\n", opcode);
19686ddf MSS	382	break;
	383	}
	384	}
9e25365f	385
9e25365f MSS	386	int ath_mci_setup(struct ath_softc *sc)
	387	{
	388	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	389	struct ath_mci_coex *mci = &sc->mci_coex;
ea510e4b	390	struct ath_mci_buf *buf = &mci->sched_buf;
9e25365f	391
ea510e4b SM	392	buf->bf_addr = dma_alloc_coherent(sc->dev,
	393	ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
	394	&buf->bf_paddr, GFP_KERNEL);
9e25365f	395
ea510e4b	396	if (buf->bf_addr == NULL) {
d2182b69	397	ath_dbg(common, FATAL, "MCI buffer alloc failed\n");
ea510e4b	398	return -ENOMEM;
9e25365f MSS	399	}
9e25365f MSS	400
ea510e4b SM	401	memset(buf->bf_addr, MCI_GPM_RSVD_PATTERN,
ea510e4b SM	402	ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE);
9e25365f	403
ea510e4b	404	mci->sched_buf.bf_len = ATH_MCI_SCHED_BUF_SIZE;
9e25365f MSS	405
9e25365f MSS	406	mci->gpm_buf.bf_len = ATH_MCI_GPM_BUF_SIZE;
ea510e4b	407	mci->gpm_buf.bf_addr = (u8 *)mci->sched_buf.bf_addr + mci->sched_buf.bf_len;
9e25365f MSS	408	mci->gpm_buf.bf_paddr = mci->sched_buf.bf_paddr + mci->sched_buf.bf_len;
9e25365f MSS	409
9e25365f MSS	410	ar9003_mci_setup(sc->sc_ah, mci->gpm_buf.bf_paddr,
	411	mci->gpm_buf.bf_addr, (mci->gpm_buf.bf_len >> 4),
	412	mci->sched_buf.bf_paddr);
ea510e4b	413
3c7992e3	414	INIT_WORK(&sc->mci_work, ath9k_mci_work);
ea510e4b SM	415	ath_dbg(common, MCI, "MCI Initialized\n");
	416
	417	return 0;
9e25365f MSS	418	}
	419
	420	void ath_mci_cleanup(struct ath_softc *sc)
	421	{
ea510e4b	422	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
9e25365f MSS	423	struct ath_hw *ah = sc->sc_ah;
9e25365f MSS	424	struct ath_mci_coex *mci = &sc->mci_coex;
ea510e4b	425	struct ath_mci_buf *buf = &mci->sched_buf;
9e25365f	426
ea510e4b SM	427	if (buf->bf_addr)
	428	dma_free_coherent(sc->dev,
	429	ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
	430	buf->bf_addr, buf->bf_paddr);
	431
9e25365f	432	ar9003_mci_cleanup(ah);
ea510e4b SM	433
ea510e4b SM	434	ath_dbg(common, MCI, "MCI De-Initialized\n");
9e25365f	435	}
19686ddf MSS	436
	437	void ath_mci_intr(struct ath_softc *sc)
	438	{
	439	struct ath_mci_coex *mci = &sc->mci_coex;
	440	struct ath_hw *ah = sc->sc_ah;
	441	struct ath_common *common = ath9k_hw_common(ah);
6d97be48	442	struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
19686ddf MSS	443	u32 mci_int, mci_int_rxmsg;
	444	u32 offset, subtype, opcode;
	445	u32 *pgpm;
	446	u32 more_data = MCI_GPM_MORE;
	447	bool skip_gpm = false;
	448
	449	ar9003_mci_get_interrupt(sc->sc_ah, &mci_int, &mci_int_rxmsg);
	450
b98ccec0	451	if (ar9003_mci_state(ah, MCI_STATE_ENABLE) == 0) {
506847ad	452	ar9003_mci_get_next_gpm_offset(ah, true, NULL);
19686ddf MSS	453	return;
	454	}
	455
	456	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) {
	457	u32 payload[4] = { 0xffffffff, 0xffffffff,
	458	0xffffffff, 0xffffff00};
	459
	460	/*
	461	* The following REMOTE_RESET and SYS_WAKING used to sent
	462	* only when BT wake up. Now they are always sent, as a
	463	* recovery method to reset BT MCI's RX alignment.
	464	*/
19686ddf MSS	465	ar9003_mci_send_message(ah, MCI_REMOTE_RESET, 0,
19686ddf MSS	466	payload, 16, true, false);
19686ddf MSS	467	ar9003_mci_send_message(ah, MCI_SYS_WAKING, 0,
	468	NULL, 0, true, false);
	469
	470	mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE;
b98ccec0	471	ar9003_mci_state(ah, MCI_STATE_RESET_REQ_WAKE);
19686ddf MSS	472
	473	/*
	474	* always do this for recovery and 2G/5G toggling and LNA_TRANS
	475	*/
b98ccec0	476	ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE);
19686ddf MSS	477	}
19686ddf MSS	478
19686ddf MSS	479	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING) {
	480	mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING;
	481
6d97be48	482	if ((mci_hw->bt_state == MCI_BT_SLEEP) &&
b98ccec0 RM	483	(ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP) !=
	484	MCI_BT_SLEEP))
	485	ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE);
19686ddf MSS	486	}
	487
	488	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) {
19686ddf MSS	489	mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING;
19686ddf MSS	490
6d97be48	491	if ((mci_hw->bt_state == MCI_BT_AWAKE) &&
b98ccec0 RM	492	(ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP) !=
b98ccec0 RM	493	MCI_BT_AWAKE))
9330969b	494	mci_hw->bt_state = MCI_BT_SLEEP;
19686ddf MSS	495	}
	496
	497	if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) \|\|
	498	(mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) {
b98ccec0	499	ar9003_mci_state(ah, MCI_STATE_RECOVER_RX);
19686ddf MSS	500	skip_gpm = true;
	501	}
	502
	503	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO) {
19686ddf	504	mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO;
b98ccec0	505	offset = ar9003_mci_state(ah, MCI_STATE_LAST_SCHD_MSG_OFFSET);
19686ddf MSS	506	}
	507
	508	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_GPM) {
19686ddf MSS	509	mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_GPM;
	510
	511	while (more_data == MCI_GPM_MORE) {
	512
	513	pgpm = mci->gpm_buf.bf_addr;
506847ad RM	514	offset = ar9003_mci_get_next_gpm_offset(ah, false,
506847ad RM	515	&more_data);
19686ddf MSS	516
	517	if (offset == MCI_GPM_INVALID)
	518	break;
	519
	520	pgpm += (offset >> 2);
	521
	522	/*
	523	* The first dword is timer.
	524	* The real data starts from 2nd dword.
	525	*/
19686ddf MSS	526	subtype = MCI_GPM_TYPE(pgpm);
	527	opcode = MCI_GPM_OPCODE(pgpm);
	528
682dd04b SM	529	if (skip_gpm)
	530	goto recycle;
	531
	532	if (MCI_GPM_IS_CAL_TYPE(subtype)) {
	533	ath_mci_cal_msg(sc, subtype, (u8 *)pgpm);
	534	} else {
	535	switch (subtype) {
	536	case MCI_GPM_COEX_AGENT:
	537	ath_mci_msg(sc, opcode, (u8 *)pgpm);
	538	break;
	539	default:
	540	break;
19686ddf MSS	541	}
19686ddf MSS	542	}
682dd04b	543	recycle:
19686ddf MSS	544	MCI_GPM_RECYCLE(pgpm);
	545	}
	546	}
	547
	548	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_HW_MSG_MASK) {
19686ddf MSS	549	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL)
	550	mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL;
	551
682dd04b	552	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_INFO)
19686ddf	553	mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_INFO;
19686ddf MSS	554
19686ddf MSS	555	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO) {
26e942b7 RM	556	int value_dbm = MS(mci_hw->cont_status,
26e942b7 RM	557	AR_MCI_CONT_RSSI_POWER);
19686ddf MSS	558
	559	mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_INFO;
	560
26e942b7 RM	561	ath_dbg(common, MCI,
	562	"MCI CONT_INFO: (%s) pri = %d pwr = %d dBm\n",
	563	MS(mci_hw->cont_status, AR_MCI_CONT_TXRX) ?
	564	"tx" : "rx",
	565	MS(mci_hw->cont_status, AR_MCI_CONT_PRIORITY),
	566	value_dbm);
19686ddf MSS	567	}
19686ddf MSS	568
682dd04b	569	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_NACK)
19686ddf	570	mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_NACK;
19686ddf	571
682dd04b	572	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_RST)
19686ddf	573	mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_RST;
19686ddf MSS	574	}
	575
	576	if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) \|\|
d92bb98f	577	(mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) {
19686ddf MSS	578	mci_int &= ~(AR_MCI_INTERRUPT_RX_INVALID_HDR \|
19686ddf MSS	579	AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT);
d92bb98f RM	580	ath_mci_msg(sc, MCI_GPM_COEX_NOOP, NULL);
d92bb98f RM	581	}
19686ddf	582	}
e270e776 SM	583
	584	void ath_mci_enable(struct ath_softc *sc)
	585	{
	586	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	587
	588	if (!common->btcoex_enabled)
	589	return;
	590
	591	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
	592	sc->sc_ah->imask \|= ATH9K_INT_MCI;
	593	}