Commit | Line | Data |
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7dc181c2 RM |
1 | /* |
2 | * Copyright (c) 2010-2011 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
9e25365f MSS |
17 | #include <linux/dma-mapping.h> |
18 | #include <linux/slab.h> | |
19 | ||
7dc181c2 RM |
20 | #include "ath9k.h" |
21 | #include "mci.h" | |
22 | ||
a197b76c | 23 | static const u8 ath_mci_duty_cycle[] = { 55, 50, 60, 70, 80, 85, 90, 95, 98 }; |
7dc181c2 RM |
24 | |
25 | static struct ath_mci_profile_info* | |
26 | ath_mci_find_profile(struct ath_mci_profile *mci, | |
27 | struct ath_mci_profile_info *info) | |
28 | { | |
29 | struct ath_mci_profile_info *entry; | |
30 | ||
9e2e0c84 RM |
31 | if (list_empty(&mci->info)) |
32 | return NULL; | |
33 | ||
7dc181c2 RM |
34 | list_for_each_entry(entry, &mci->info, list) { |
35 | if (entry->conn_handle == info->conn_handle) | |
9e2e0c84 | 36 | return entry; |
7dc181c2 | 37 | } |
9e2e0c84 | 38 | return NULL; |
7dc181c2 RM |
39 | } |
40 | ||
41 | static bool ath_mci_add_profile(struct ath_common *common, | |
42 | struct ath_mci_profile *mci, | |
43 | struct ath_mci_profile_info *info) | |
44 | { | |
45 | struct ath_mci_profile_info *entry; | |
46 | ||
47 | if ((mci->num_sco == ATH_MCI_MAX_SCO_PROFILE) && | |
682dd04b | 48 | (info->type == MCI_GPM_COEX_PROFILE_VOICE)) |
7dc181c2 | 49 | return false; |
7dc181c2 RM |
50 | |
51 | if (((NUM_PROF(mci) - mci->num_sco) == ATH_MCI_MAX_ACL_PROFILE) && | |
682dd04b | 52 | (info->type != MCI_GPM_COEX_PROFILE_VOICE)) |
7dc181c2 | 53 | return false; |
7dc181c2 | 54 | |
3c7992e3 | 55 | entry = kzalloc(sizeof(*entry), GFP_ATOMIC); |
9e2e0c84 RM |
56 | if (!entry) |
57 | return false; | |
7dc181c2 | 58 | |
9e2e0c84 RM |
59 | memcpy(entry, info, 10); |
60 | INC_PROF(mci, info); | |
61 | list_add_tail(&entry->list, &mci->info); | |
682dd04b | 62 | |
7dc181c2 RM |
63 | return true; |
64 | } | |
65 | ||
66 | static void ath_mci_del_profile(struct ath_common *common, | |
67 | struct ath_mci_profile *mci, | |
9e2e0c84 | 68 | struct ath_mci_profile_info *entry) |
7dc181c2 | 69 | { |
682dd04b | 70 | if (!entry) |
7dc181c2 | 71 | return; |
682dd04b | 72 | |
7dc181c2 RM |
73 | DEC_PROF(mci, entry); |
74 | list_del(&entry->list); | |
75 | kfree(entry); | |
76 | } | |
77 | ||
78 | void ath_mci_flush_profile(struct ath_mci_profile *mci) | |
79 | { | |
80 | struct ath_mci_profile_info *info, *tinfo; | |
81 | ||
9e2e0c84 RM |
82 | mci->aggr_limit = 0; |
83 | ||
84 | if (list_empty(&mci->info)) | |
85 | return; | |
86 | ||
7dc181c2 RM |
87 | list_for_each_entry_safe(info, tinfo, &mci->info, list) { |
88 | list_del(&info->list); | |
89 | DEC_PROF(mci, info); | |
90 | kfree(info); | |
91 | } | |
7dc181c2 RM |
92 | } |
93 | ||
94 | static void ath_mci_adjust_aggr_limit(struct ath_btcoex *btcoex) | |
95 | { | |
96 | struct ath_mci_profile *mci = &btcoex->mci; | |
97 | u32 wlan_airtime = btcoex->btcoex_period * | |
98 | (100 - btcoex->duty_cycle) / 100; | |
99 | ||
100 | /* | |
101 | * Scale: wlan_airtime is in ms, aggr_limit is in 0.25 ms. | |
102 | * When wlan_airtime is less than 4ms, aggregation limit has to be | |
103 | * adjusted half of wlan_airtime to ensure that the aggregation can fit | |
104 | * without collision with BT traffic. | |
105 | */ | |
106 | if ((wlan_airtime <= 4) && | |
107 | (!mci->aggr_limit || (mci->aggr_limit > (2 * wlan_airtime)))) | |
108 | mci->aggr_limit = 2 * wlan_airtime; | |
109 | } | |
110 | ||
111 | static void ath_mci_update_scheme(struct ath_softc *sc) | |
112 | { | |
113 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
114 | struct ath_btcoex *btcoex = &sc->btcoex; | |
115 | struct ath_mci_profile *mci = &btcoex->mci; | |
0603143e | 116 | struct ath9k_hw_mci *mci_hw = &sc->sc_ah->btcoex_hw.mci; |
7dc181c2 RM |
117 | struct ath_mci_profile_info *info; |
118 | u32 num_profile = NUM_PROF(mci); | |
119 | ||
0603143e RM |
120 | if (mci_hw->config & ATH_MCI_CONFIG_DISABLE_TUNING) |
121 | goto skip_tuning; | |
122 | ||
a197b76c RM |
123 | btcoex->duty_cycle = ath_mci_duty_cycle[num_profile]; |
124 | ||
7dc181c2 RM |
125 | if (num_profile == 1) { |
126 | info = list_first_entry(&mci->info, | |
127 | struct ath_mci_profile_info, | |
128 | list); | |
0603143e RM |
129 | if (mci->num_sco) { |
130 | if (info->T == 12) | |
131 | mci->aggr_limit = 8; | |
132 | else if (info->T == 6) { | |
133 | mci->aggr_limit = 6; | |
134 | btcoex->duty_cycle = 30; | |
135 | } | |
d2182b69 | 136 | ath_dbg(common, MCI, |
0603143e RM |
137 | "Single SCO, aggregation limit %d 1/4 ms\n", |
138 | mci->aggr_limit); | |
139 | } else if (mci->num_pan || mci->num_other_acl) { | |
140 | /* | |
141 | * For single PAN/FTP profile, allocate 35% for BT | |
142 | * to improve WLAN throughput. | |
143 | */ | |
144 | btcoex->duty_cycle = 35; | |
145 | btcoex->btcoex_period = 53; | |
d2182b69 | 146 | ath_dbg(common, MCI, |
0603143e RM |
147 | "Single PAN/FTP bt period %d ms dutycycle %d\n", |
148 | btcoex->duty_cycle, btcoex->btcoex_period); | |
149 | } else if (mci->num_hid) { | |
7dc181c2 | 150 | btcoex->duty_cycle = 30; |
0603143e | 151 | mci->aggr_limit = 6; |
d2182b69 | 152 | ath_dbg(common, MCI, |
7dc181c2 | 153 | "Multiple attempt/timeout single HID " |
0603143e | 154 | "aggregation limit 1.5 ms dutycycle 30%%\n"); |
7dc181c2 | 155 | } |
0603143e RM |
156 | } else if (num_profile == 2) { |
157 | if (mci->num_hid == 2) | |
158 | btcoex->duty_cycle = 30; | |
7dc181c2 | 159 | mci->aggr_limit = 6; |
d2182b69 | 160 | ath_dbg(common, MCI, |
0603143e RM |
161 | "Two BT profiles aggr limit 1.5 ms dutycycle %d%%\n", |
162 | btcoex->duty_cycle); | |
163 | } else if (num_profile >= 3) { | |
164 | mci->aggr_limit = 4; | |
165 | ath_dbg(common, MCI, | |
166 | "Three or more profiles aggregation limit 1 ms\n"); | |
7dc181c2 RM |
167 | } |
168 | ||
0603143e | 169 | skip_tuning: |
7dc181c2 RM |
170 | if (IS_CHAN_2GHZ(sc->sc_ah->curchan)) { |
171 | if (IS_CHAN_HT(sc->sc_ah->curchan)) | |
172 | ath_mci_adjust_aggr_limit(btcoex); | |
173 | else | |
174 | btcoex->btcoex_period >>= 1; | |
175 | } | |
176 | ||
177 | ath9k_hw_btcoex_disable(sc->sc_ah); | |
178 | ath9k_btcoex_timer_pause(sc); | |
179 | ||
180 | if (IS_CHAN_5GHZ(sc->sc_ah->curchan)) | |
181 | return; | |
182 | ||
a197b76c | 183 | btcoex->duty_cycle += (mci->num_bdr ? ATH_MCI_BDR_DUTY_CYCLE : 0); |
7dc181c2 RM |
184 | if (btcoex->duty_cycle > ATH_MCI_MAX_DUTY_CYCLE) |
185 | btcoex->duty_cycle = ATH_MCI_MAX_DUTY_CYCLE; | |
186 | ||
dfd0587a | 187 | btcoex->btcoex_no_stomp = btcoex->btcoex_period * 1000 * |
682dd04b | 188 | (100 - btcoex->duty_cycle) / 100; |
7dc181c2 RM |
189 | |
190 | ath9k_hw_btcoex_enable(sc->sc_ah); | |
191 | ath9k_btcoex_timer_resume(sc); | |
192 | } | |
193 | ||
19686ddf MSS |
194 | static void ath_mci_cal_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload) |
195 | { | |
196 | struct ath_hw *ah = sc->sc_ah; | |
197 | struct ath_common *common = ath9k_hw_common(ah); | |
198 | u32 payload[4] = {0, 0, 0, 0}; | |
199 | ||
200 | switch (opcode) { | |
201 | case MCI_GPM_BT_CAL_REQ: | |
b98ccec0 RM |
202 | if (ar9003_mci_state(ah, MCI_STATE_BT) == MCI_BT_AWAKE) { |
203 | ar9003_mci_state(ah, MCI_STATE_SET_BT_CAL_START); | |
19686ddf | 204 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); |
682dd04b SM |
205 | } else { |
206 | ath_dbg(common, MCI, "MCI State mismatch: %d\n", | |
b98ccec0 | 207 | ar9003_mci_state(ah, MCI_STATE_BT)); |
682dd04b | 208 | } |
19686ddf | 209 | break; |
19686ddf | 210 | case MCI_GPM_BT_CAL_DONE: |
b98ccec0 | 211 | ar9003_mci_state(ah, MCI_STATE_BT); |
19686ddf | 212 | break; |
19686ddf | 213 | case MCI_GPM_BT_CAL_GRANT: |
19686ddf MSS |
214 | MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_DONE); |
215 | ar9003_mci_send_message(sc->sc_ah, MCI_GPM, 0, payload, | |
216 | 16, false, true); | |
217 | break; | |
19686ddf | 218 | default: |
682dd04b | 219 | ath_dbg(common, MCI, "Unknown GPM CAL message\n"); |
19686ddf MSS |
220 | break; |
221 | } | |
222 | } | |
223 | ||
3c7992e3 RM |
224 | static void ath9k_mci_work(struct work_struct *work) |
225 | { | |
226 | struct ath_softc *sc = container_of(work, struct ath_softc, mci_work); | |
227 | ||
228 | ath_mci_update_scheme(sc); | |
229 | } | |
230 | ||
e5f0a276 FF |
231 | static void ath_mci_process_profile(struct ath_softc *sc, |
232 | struct ath_mci_profile_info *info) | |
7dc181c2 RM |
233 | { |
234 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
235 | struct ath_btcoex *btcoex = &sc->btcoex; | |
236 | struct ath_mci_profile *mci = &btcoex->mci; | |
9e2e0c84 RM |
237 | struct ath_mci_profile_info *entry = NULL; |
238 | ||
239 | entry = ath_mci_find_profile(mci, info); | |
240 | if (entry) | |
241 | memcpy(entry, info, 10); | |
7dc181c2 RM |
242 | |
243 | if (info->start) { | |
9e2e0c84 | 244 | if (!entry && !ath_mci_add_profile(common, mci, info)) |
7dc181c2 RM |
245 | return; |
246 | } else | |
9e2e0c84 | 247 | ath_mci_del_profile(common, mci, entry); |
7dc181c2 RM |
248 | |
249 | btcoex->btcoex_period = ATH_MCI_DEF_BT_PERIOD; | |
250 | mci->aggr_limit = mci->num_sco ? 6 : 0; | |
682dd04b | 251 | |
a197b76c RM |
252 | btcoex->duty_cycle = ath_mci_duty_cycle[NUM_PROF(mci)]; |
253 | if (NUM_PROF(mci)) | |
7dc181c2 | 254 | btcoex->bt_stomp_type = ATH_BTCOEX_STOMP_LOW; |
a197b76c | 255 | else |
7dc181c2 RM |
256 | btcoex->bt_stomp_type = mci->num_mgmt ? ATH_BTCOEX_STOMP_ALL : |
257 | ATH_BTCOEX_STOMP_LOW; | |
7dc181c2 | 258 | |
3c7992e3 | 259 | ieee80211_queue_work(sc->hw, &sc->mci_work); |
7dc181c2 RM |
260 | } |
261 | ||
e5f0a276 FF |
262 | static void ath_mci_process_status(struct ath_softc *sc, |
263 | struct ath_mci_profile_status *status) | |
7dc181c2 | 264 | { |
7dc181c2 RM |
265 | struct ath_btcoex *btcoex = &sc->btcoex; |
266 | struct ath_mci_profile *mci = &btcoex->mci; | |
267 | struct ath_mci_profile_info info; | |
268 | int i = 0, old_num_mgmt = mci->num_mgmt; | |
269 | ||
270 | /* Link status type are not handled */ | |
682dd04b | 271 | if (status->is_link) |
7dc181c2 | 272 | return; |
7dc181c2 | 273 | |
7dc181c2 | 274 | info.conn_handle = status->conn_handle; |
682dd04b | 275 | if (ath_mci_find_profile(mci, &info)) |
7dc181c2 | 276 | return; |
682dd04b SM |
277 | |
278 | if (status->conn_handle >= ATH_MCI_MAX_PROFILE) | |
7dc181c2 | 279 | return; |
682dd04b | 280 | |
7dc181c2 RM |
281 | if (status->is_critical) |
282 | __set_bit(status->conn_handle, mci->status); | |
283 | else | |
284 | __clear_bit(status->conn_handle, mci->status); | |
285 | ||
286 | mci->num_mgmt = 0; | |
287 | do { | |
288 | if (test_bit(i, mci->status)) | |
289 | mci->num_mgmt++; | |
290 | } while (++i < ATH_MCI_MAX_PROFILE); | |
291 | ||
292 | if (old_num_mgmt != mci->num_mgmt) | |
3c7992e3 | 293 | ieee80211_queue_work(sc->hw, &sc->mci_work); |
7dc181c2 | 294 | } |
9e25365f | 295 | |
19686ddf MSS |
296 | static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload) |
297 | { | |
298 | struct ath_hw *ah = sc->sc_ah; | |
299 | struct ath_mci_profile_info profile_info; | |
300 | struct ath_mci_profile_status profile_status; | |
301 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
e1763d3f | 302 | u8 major, minor; |
19686ddf MSS |
303 | u32 seq_num; |
304 | ||
305 | switch (opcode) { | |
19686ddf | 306 | case MCI_GPM_COEX_VERSION_QUERY: |
b98ccec0 | 307 | ar9003_mci_state(ah, MCI_STATE_SEND_WLAN_COEX_VERSION); |
19686ddf | 308 | break; |
19686ddf | 309 | case MCI_GPM_COEX_VERSION_RESPONSE: |
19686ddf MSS |
310 | major = *(rx_payload + MCI_GPM_COEX_B_MAJOR_VERSION); |
311 | minor = *(rx_payload + MCI_GPM_COEX_B_MINOR_VERSION); | |
e1763d3f | 312 | ar9003_mci_set_bt_version(ah, major, minor); |
19686ddf | 313 | break; |
19686ddf | 314 | case MCI_GPM_COEX_STATUS_QUERY: |
2d340ac8 | 315 | ar9003_mci_send_wlan_channels(ah); |
19686ddf | 316 | break; |
19686ddf | 317 | case MCI_GPM_COEX_BT_PROFILE_INFO: |
19686ddf MSS |
318 | memcpy(&profile_info, |
319 | (rx_payload + MCI_GPM_COEX_B_PROFILE_TYPE), 10); | |
320 | ||
682dd04b SM |
321 | if ((profile_info.type == MCI_GPM_COEX_PROFILE_UNKNOWN) || |
322 | (profile_info.type >= MCI_GPM_COEX_PROFILE_MAX)) { | |
d2182b69 | 323 | ath_dbg(common, MCI, |
682dd04b | 324 | "Illegal profile type = %d, state = %d\n", |
d2182b69 | 325 | profile_info.type, |
19686ddf MSS |
326 | profile_info.start); |
327 | break; | |
328 | } | |
329 | ||
330 | ath_mci_process_profile(sc, &profile_info); | |
331 | break; | |
19686ddf MSS |
332 | case MCI_GPM_COEX_BT_STATUS_UPDATE: |
333 | profile_status.is_link = *(rx_payload + | |
334 | MCI_GPM_COEX_B_STATUS_TYPE); | |
335 | profile_status.conn_handle = *(rx_payload + | |
336 | MCI_GPM_COEX_B_STATUS_LINKID); | |
337 | profile_status.is_critical = *(rx_payload + | |
338 | MCI_GPM_COEX_B_STATUS_STATE); | |
339 | ||
340 | seq_num = *((u32 *)(rx_payload + 12)); | |
d2182b69 | 341 | ath_dbg(common, MCI, |
682dd04b | 342 | "BT_Status_Update: is_link=%d, linkId=%d, state=%d, SEQ=%d\n", |
19686ddf MSS |
343 | profile_status.is_link, profile_status.conn_handle, |
344 | profile_status.is_critical, seq_num); | |
345 | ||
346 | ath_mci_process_status(sc, &profile_status); | |
347 | break; | |
19686ddf | 348 | default: |
682dd04b | 349 | ath_dbg(common, MCI, "Unknown GPM COEX message = 0x%02x\n", opcode); |
19686ddf MSS |
350 | break; |
351 | } | |
352 | } | |
9e25365f | 353 | |
9e25365f MSS |
354 | int ath_mci_setup(struct ath_softc *sc) |
355 | { | |
356 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
357 | struct ath_mci_coex *mci = &sc->mci_coex; | |
ea510e4b | 358 | struct ath_mci_buf *buf = &mci->sched_buf; |
9e25365f | 359 | |
ea510e4b SM |
360 | buf->bf_addr = dma_alloc_coherent(sc->dev, |
361 | ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE, | |
362 | &buf->bf_paddr, GFP_KERNEL); | |
9e25365f | 363 | |
ea510e4b | 364 | if (buf->bf_addr == NULL) { |
d2182b69 | 365 | ath_dbg(common, FATAL, "MCI buffer alloc failed\n"); |
ea510e4b | 366 | return -ENOMEM; |
9e25365f MSS |
367 | } |
368 | ||
ea510e4b SM |
369 | memset(buf->bf_addr, MCI_GPM_RSVD_PATTERN, |
370 | ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE); | |
9e25365f | 371 | |
ea510e4b | 372 | mci->sched_buf.bf_len = ATH_MCI_SCHED_BUF_SIZE; |
9e25365f MSS |
373 | |
374 | mci->gpm_buf.bf_len = ATH_MCI_GPM_BUF_SIZE; | |
ea510e4b | 375 | mci->gpm_buf.bf_addr = (u8 *)mci->sched_buf.bf_addr + mci->sched_buf.bf_len; |
9e25365f MSS |
376 | mci->gpm_buf.bf_paddr = mci->sched_buf.bf_paddr + mci->sched_buf.bf_len; |
377 | ||
9e25365f MSS |
378 | ar9003_mci_setup(sc->sc_ah, mci->gpm_buf.bf_paddr, |
379 | mci->gpm_buf.bf_addr, (mci->gpm_buf.bf_len >> 4), | |
380 | mci->sched_buf.bf_paddr); | |
ea510e4b | 381 | |
3c7992e3 | 382 | INIT_WORK(&sc->mci_work, ath9k_mci_work); |
ea510e4b SM |
383 | ath_dbg(common, MCI, "MCI Initialized\n"); |
384 | ||
385 | return 0; | |
9e25365f MSS |
386 | } |
387 | ||
388 | void ath_mci_cleanup(struct ath_softc *sc) | |
389 | { | |
ea510e4b | 390 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
9e25365f MSS |
391 | struct ath_hw *ah = sc->sc_ah; |
392 | struct ath_mci_coex *mci = &sc->mci_coex; | |
ea510e4b | 393 | struct ath_mci_buf *buf = &mci->sched_buf; |
9e25365f | 394 | |
ea510e4b SM |
395 | if (buf->bf_addr) |
396 | dma_free_coherent(sc->dev, | |
397 | ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE, | |
398 | buf->bf_addr, buf->bf_paddr); | |
399 | ||
9e25365f | 400 | ar9003_mci_cleanup(ah); |
ea510e4b SM |
401 | |
402 | ath_dbg(common, MCI, "MCI De-Initialized\n"); | |
9e25365f | 403 | } |
19686ddf MSS |
404 | |
405 | void ath_mci_intr(struct ath_softc *sc) | |
406 | { | |
407 | struct ath_mci_coex *mci = &sc->mci_coex; | |
408 | struct ath_hw *ah = sc->sc_ah; | |
409 | struct ath_common *common = ath9k_hw_common(ah); | |
410 | u32 mci_int, mci_int_rxmsg; | |
411 | u32 offset, subtype, opcode; | |
412 | u32 *pgpm; | |
413 | u32 more_data = MCI_GPM_MORE; | |
414 | bool skip_gpm = false; | |
415 | ||
416 | ar9003_mci_get_interrupt(sc->sc_ah, &mci_int, &mci_int_rxmsg); | |
417 | ||
b98ccec0 | 418 | if (ar9003_mci_state(ah, MCI_STATE_ENABLE) == 0) { |
506847ad | 419 | ar9003_mci_get_next_gpm_offset(ah, true, NULL); |
19686ddf MSS |
420 | return; |
421 | } | |
422 | ||
423 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) { | |
424 | u32 payload[4] = { 0xffffffff, 0xffffffff, | |
425 | 0xffffffff, 0xffffff00}; | |
426 | ||
427 | /* | |
428 | * The following REMOTE_RESET and SYS_WAKING used to sent | |
429 | * only when BT wake up. Now they are always sent, as a | |
430 | * recovery method to reset BT MCI's RX alignment. | |
431 | */ | |
19686ddf MSS |
432 | ar9003_mci_send_message(ah, MCI_REMOTE_RESET, 0, |
433 | payload, 16, true, false); | |
19686ddf MSS |
434 | ar9003_mci_send_message(ah, MCI_SYS_WAKING, 0, |
435 | NULL, 0, true, false); | |
436 | ||
437 | mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE; | |
b98ccec0 | 438 | ar9003_mci_state(ah, MCI_STATE_RESET_REQ_WAKE); |
19686ddf MSS |
439 | |
440 | /* | |
441 | * always do this for recovery and 2G/5G toggling and LNA_TRANS | |
442 | */ | |
b98ccec0 | 443 | ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE); |
19686ddf MSS |
444 | } |
445 | ||
19686ddf MSS |
446 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING) { |
447 | mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING; | |
448 | ||
b98ccec0 RM |
449 | if ((ar9003_mci_state(ah, MCI_STATE_BT) == MCI_BT_SLEEP) && |
450 | (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP) != | |
451 | MCI_BT_SLEEP)) | |
452 | ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE); | |
19686ddf MSS |
453 | } |
454 | ||
455 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) { | |
19686ddf MSS |
456 | mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING; |
457 | ||
b98ccec0 RM |
458 | if ((ar9003_mci_state(ah, MCI_STATE_BT) == MCI_BT_AWAKE) && |
459 | (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP) != | |
460 | MCI_BT_AWAKE)) | |
461 | ar9003_mci_state(ah, MCI_STATE_SET_BT_SLEEP); | |
19686ddf MSS |
462 | } |
463 | ||
464 | if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) || | |
465 | (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) { | |
b98ccec0 | 466 | ar9003_mci_state(ah, MCI_STATE_RECOVER_RX); |
19686ddf MSS |
467 | skip_gpm = true; |
468 | } | |
469 | ||
470 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO) { | |
19686ddf | 471 | mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO; |
b98ccec0 | 472 | offset = ar9003_mci_state(ah, MCI_STATE_LAST_SCHD_MSG_OFFSET); |
19686ddf MSS |
473 | } |
474 | ||
475 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_GPM) { | |
19686ddf MSS |
476 | mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_GPM; |
477 | ||
478 | while (more_data == MCI_GPM_MORE) { | |
479 | ||
480 | pgpm = mci->gpm_buf.bf_addr; | |
506847ad RM |
481 | offset = ar9003_mci_get_next_gpm_offset(ah, false, |
482 | &more_data); | |
19686ddf MSS |
483 | |
484 | if (offset == MCI_GPM_INVALID) | |
485 | break; | |
486 | ||
487 | pgpm += (offset >> 2); | |
488 | ||
489 | /* | |
490 | * The first dword is timer. | |
491 | * The real data starts from 2nd dword. | |
492 | */ | |
19686ddf MSS |
493 | subtype = MCI_GPM_TYPE(pgpm); |
494 | opcode = MCI_GPM_OPCODE(pgpm); | |
495 | ||
682dd04b SM |
496 | if (skip_gpm) |
497 | goto recycle; | |
498 | ||
499 | if (MCI_GPM_IS_CAL_TYPE(subtype)) { | |
500 | ath_mci_cal_msg(sc, subtype, (u8 *)pgpm); | |
501 | } else { | |
502 | switch (subtype) { | |
503 | case MCI_GPM_COEX_AGENT: | |
504 | ath_mci_msg(sc, opcode, (u8 *)pgpm); | |
505 | break; | |
506 | default: | |
507 | break; | |
19686ddf MSS |
508 | } |
509 | } | |
682dd04b | 510 | recycle: |
19686ddf MSS |
511 | MCI_GPM_RECYCLE(pgpm); |
512 | } | |
513 | } | |
514 | ||
515 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_HW_MSG_MASK) { | |
19686ddf MSS |
516 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL) |
517 | mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL; | |
518 | ||
682dd04b | 519 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_INFO) |
19686ddf | 520 | mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_INFO; |
19686ddf MSS |
521 | |
522 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO) { | |
19686ddf | 523 | int value_dbm = ar9003_mci_state(ah, |
b98ccec0 | 524 | MCI_STATE_CONT_RSSI_POWER); |
19686ddf MSS |
525 | |
526 | mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_INFO; | |
527 | ||
b98ccec0 | 528 | if (ar9003_mci_state(ah, MCI_STATE_CONT_TXRX)) |
d2182b69 JP |
529 | ath_dbg(common, MCI, |
530 | "MCI CONT_INFO: (tx) pri = %d, pwr = %d dBm\n", | |
19686ddf | 531 | ar9003_mci_state(ah, |
b98ccec0 | 532 | MCI_STATE_CONT_PRIORITY), |
19686ddf MSS |
533 | value_dbm); |
534 | else | |
d2182b69 JP |
535 | ath_dbg(common, MCI, |
536 | "MCI CONT_INFO: (rx) pri = %d,pwr = %d dBm\n", | |
19686ddf | 537 | ar9003_mci_state(ah, |
b98ccec0 | 538 | MCI_STATE_CONT_PRIORITY), |
19686ddf MSS |
539 | value_dbm); |
540 | } | |
541 | ||
682dd04b | 542 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_NACK) |
19686ddf | 543 | mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_NACK; |
19686ddf | 544 | |
682dd04b | 545 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_RST) |
19686ddf | 546 | mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_RST; |
19686ddf MSS |
547 | } |
548 | ||
549 | if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) || | |
550 | (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) | |
551 | mci_int &= ~(AR_MCI_INTERRUPT_RX_INVALID_HDR | | |
552 | AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT); | |
19686ddf | 553 | } |
e270e776 SM |
554 | |
555 | void ath_mci_enable(struct ath_softc *sc) | |
556 | { | |
557 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
558 | ||
559 | if (!common->btcoex_enabled) | |
560 | return; | |
561 | ||
562 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI) | |
563 | sc->sc_ah->imask |= ATH9K_INT_MCI; | |
564 | } |