[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / mci.c

/*
 * Copyright (c) 2010-2011 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/dma-mapping.h>
#include <linux/slab.h>

#include "ath9k.h"
#include "mci.h"

static const u8 ath_mci_duty_cycle[] = { 55, 50, 60, 70, 80, 85, 90, 95, 98 };

static struct ath_mci_profile_info*
ath_mci_find_profile(struct ath_mci_profile *mci,
		     struct ath_mci_profile_info *info)
{
	struct ath_mci_profile_info *entry;

	if (list_empty(&mci->info))
		return NULL;

	list_for_each_entry(entry, &mci->info, list) {
		if (entry->conn_handle == info->conn_handle)
			return entry;
	}
	return NULL;
}

static bool ath_mci_add_profile(struct ath_common *common,
				struct ath_mci_profile *mci,
				struct ath_mci_profile_info *info)
{
	struct ath_mci_profile_info *entry;

	if ((mci->num_sco == ATH_MCI_MAX_SCO_PROFILE) &&
	    (info->type == MCI_GPM_COEX_PROFILE_VOICE))
		return false;

	if (((NUM_PROF(mci) - mci->num_sco) == ATH_MCI_MAX_ACL_PROFILE) &&
	    (info->type != MCI_GPM_COEX_PROFILE_VOICE))
		return false;

	entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
	if (!entry)
		return false;

	memcpy(entry, info, 10);
	INC_PROF(mci, info);
	list_add_tail(&entry->list, &mci->info);

	return true;
}

static void ath_mci_del_profile(struct ath_common *common,
				struct ath_mci_profile *mci,
				struct ath_mci_profile_info *entry)
{
	if (!entry)
		return;

	DEC_PROF(mci, entry);
	list_del(&entry->list);
	kfree(entry);
}

void ath_mci_flush_profile(struct ath_mci_profile *mci)
{
	struct ath_mci_profile_info *info, *tinfo;

	mci->aggr_limit = 0;
	mci->num_mgmt = 0;

	if (list_empty(&mci->info))
		return;

	list_for_each_entry_safe(info, tinfo, &mci->info, list) {
		list_del(&info->list);
		DEC_PROF(mci, info);
		kfree(info);
	}
}

static void ath_mci_adjust_aggr_limit(struct ath_btcoex *btcoex)
{
	struct ath_mci_profile *mci = &btcoex->mci;
	u32 wlan_airtime = btcoex->btcoex_period *
				(100 - btcoex->duty_cycle) / 100;

	/*
	 * Scale: wlan_airtime is in ms, aggr_limit is in 0.25 ms.
	 * When wlan_airtime is less than 4ms, aggregation limit has to be
	 * adjusted half of wlan_airtime to ensure that the aggregation can fit
	 * without collision with BT traffic.
	 */
	if ((wlan_airtime <= 4) &&
	    (!mci->aggr_limit || (mci->aggr_limit > (2 * wlan_airtime))))
		mci->aggr_limit = 2 * wlan_airtime;
}

static void ath_mci_update_scheme(struct ath_softc *sc)
{
	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	struct ath_btcoex *btcoex = &sc->btcoex;
	struct ath_mci_profile *mci = &btcoex->mci;
	struct ath9k_hw_mci *mci_hw = &sc->sc_ah->btcoex_hw.mci;
	struct ath_mci_profile_info *info;
	u32 num_profile = NUM_PROF(mci);

	if (mci_hw->config & ATH_MCI_CONFIG_DISABLE_TUNING)
		goto skip_tuning;

	btcoex->duty_cycle = ath_mci_duty_cycle[num_profile];

	if (num_profile == 1) {
		info = list_first_entry(&mci->info,
					struct ath_mci_profile_info,
					list);
		if (mci->num_sco) {
			if (info->T == 12)
				mci->aggr_limit = 8;
			else if (info->T == 6) {
				mci->aggr_limit = 6;
				btcoex->duty_cycle = 30;
			}
			ath_dbg(common, MCI,
				"Single SCO, aggregation limit %d 1/4 ms\n",
				mci->aggr_limit);
		} else if (mci->num_pan || mci->num_other_acl) {
			/*
			 * For single PAN/FTP profile, allocate 35% for BT
			 * to improve WLAN throughput.
			 */
			btcoex->duty_cycle = 35;
			btcoex->btcoex_period = 53;
			ath_dbg(common, MCI,
				"Single PAN/FTP bt period %d ms dutycycle %d\n",
				btcoex->duty_cycle, btcoex->btcoex_period);
		} else if (mci->num_hid) {
			btcoex->duty_cycle = 30;
			mci->aggr_limit = 6;
			ath_dbg(common, MCI,
				"Multiple attempt/timeout single HID "
				"aggregation limit 1.5 ms dutycycle 30%%\n");
		}
	} else if (num_profile == 2) {
		if (mci->num_hid == 2)
			btcoex->duty_cycle = 30;
		mci->aggr_limit = 6;
		ath_dbg(common, MCI,
			"Two BT profiles aggr limit 1.5 ms dutycycle %d%%\n",
			btcoex->duty_cycle);
	} else if (num_profile >= 3) {
		mci->aggr_limit = 4;
		ath_dbg(common, MCI,
			"Three or more profiles aggregation limit 1 ms\n");
	}

skip_tuning:
	if (IS_CHAN_2GHZ(sc->sc_ah->curchan)) {
		if (IS_CHAN_HT(sc->sc_ah->curchan))
			ath_mci_adjust_aggr_limit(btcoex);
		else
			btcoex->btcoex_period >>= 1;
	}

	ath9k_btcoex_timer_pause(sc);
	ath9k_hw_btcoex_disable(sc->sc_ah);

	if (IS_CHAN_5GHZ(sc->sc_ah->curchan))
		return;

	btcoex->duty_cycle += (mci->num_bdr ? ATH_MCI_BDR_DUTY_CYCLE : 0);
	if (btcoex->duty_cycle > ATH_MCI_MAX_DUTY_CYCLE)
		btcoex->duty_cycle = ATH_MCI_MAX_DUTY_CYCLE;

	btcoex->btcoex_no_stomp =  btcoex->btcoex_period * 1000 *
		(100 - btcoex->duty_cycle) / 100;

	ath9k_hw_btcoex_enable(sc->sc_ah);
	ath9k_btcoex_timer_resume(sc);
}

static void ath_mci_wait_btcal_done(struct ath_softc *sc)
{
	struct ath_hw *ah = sc->sc_ah;

	/* Stop tx & rx */
	ieee80211_stop_queues(sc->hw);
	ath_stoprecv(sc);
	ath_drain_all_txq(sc, false);

	/* Wait for cal done */
	ar9003_mci_start_reset(ah, ah->curchan);

	/* Resume tx & rx */
	ath_startrecv(sc);
	ieee80211_wake_queues(sc->hw);
}

static void ath_mci_cal_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
{
	struct ath_hw *ah = sc->sc_ah;
	struct ath_common *common = ath9k_hw_common(ah);
	struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
	u32 payload[4] = {0, 0, 0, 0};

	switch (opcode) {
	case MCI_GPM_BT_CAL_REQ:
		if (mci_hw->bt_state == MCI_BT_AWAKE) {
			mci_hw->bt_state = MCI_BT_CAL_START;
			ath_mci_wait_btcal_done(sc);
		}
		ath_dbg(common, MCI, "MCI State : %d\n", mci_hw->bt_state);
		break;
	case MCI_GPM_BT_CAL_GRANT:
		MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_DONE);
		ar9003_mci_send_message(sc->sc_ah, MCI_GPM, 0, payload,
					16, false, true);
		break;
	default:
		ath_dbg(common, MCI, "Unknown GPM CAL message\n");
		break;
	}
}

static void ath9k_mci_work(struct work_struct *work)
{
	struct ath_softc *sc = container_of(work, struct ath_softc, mci_work);

	ath_mci_update_scheme(sc);
}

static void ath_mci_process_profile(struct ath_softc *sc,
				    struct ath_mci_profile_info *info)
{
	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	struct ath_btcoex *btcoex = &sc->btcoex;
	struct ath_mci_profile *mci = &btcoex->mci;
	struct ath_mci_profile_info *entry = NULL;

	entry = ath_mci_find_profile(mci, info);
	if (entry) {
		/*
		 * Two MCI interrupts are generated while connecting to
		 * headset and A2DP profile, but only one MCI interrupt
		 * is generated with last added profile type while disconnecting
		 * both profiles.
		 * So while adding second profile type decrement
		 * the first one.
		 */
		if (entry->type != info->type) {
			DEC_PROF(mci, entry);
			INC_PROF(mci, info);
		}
		memcpy(entry, info, 10);
	}

	if (info->start) {
		if (!entry && !ath_mci_add_profile(common, mci, info))
			return;
	} else
		ath_mci_del_profile(common, mci, entry);

	btcoex->btcoex_period = ATH_MCI_DEF_BT_PERIOD;
	mci->aggr_limit = mci->num_sco ? 6 : 0;

	btcoex->duty_cycle = ath_mci_duty_cycle[NUM_PROF(mci)];
	if (NUM_PROF(mci))
		btcoex->bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
	else
		btcoex->bt_stomp_type = mci->num_mgmt ? ATH_BTCOEX_STOMP_ALL :
							ATH_BTCOEX_STOMP_LOW;

	ieee80211_queue_work(sc->hw, &sc->mci_work);
}

static void ath_mci_process_status(struct ath_softc *sc,
				   struct ath_mci_profile_status *status)
{
	struct ath_btcoex *btcoex = &sc->btcoex;
	struct ath_mci_profile *mci = &btcoex->mci;
	struct ath_mci_profile_info info;
	int i = 0, old_num_mgmt = mci->num_mgmt;

	/* Link status type are not handled */
	if (status->is_link)
		return;

	info.conn_handle = status->conn_handle;
	if (ath_mci_find_profile(mci, &info))
		return;

	if (status->conn_handle >= ATH_MCI_MAX_PROFILE)
		return;

	if (status->is_critical)
		__set_bit(status->conn_handle, mci->status);
	else
		__clear_bit(status->conn_handle, mci->status);

	mci->num_mgmt = 0;
	do {
		if (test_bit(i, mci->status))
			mci->num_mgmt++;
	} while (++i < ATH_MCI_MAX_PROFILE);

	if (old_num_mgmt != mci->num_mgmt)
		ieee80211_queue_work(sc->hw, &sc->mci_work);
}

static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
{
	struct ath_hw *ah = sc->sc_ah;
	struct ath_mci_profile_info profile_info;
	struct ath_mci_profile_status profile_status;
	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	u8 major, minor;
	u32 seq_num;

	if (ar9003_mci_state(ah, MCI_STATE_NEED_FLUSH_BT_INFO) &&
	    ar9003_mci_state(ah, MCI_STATE_ENABLE)) {
		ath_dbg(common, MCI, "(MCI) Need to flush BT profiles\n");
		ath_mci_flush_profile(&sc->btcoex.mci);
		ar9003_mci_state(ah, MCI_STATE_SEND_STATUS_QUERY);
	}

	switch (opcode) {
	case MCI_GPM_COEX_VERSION_QUERY:
		ar9003_mci_state(ah, MCI_STATE_SEND_WLAN_COEX_VERSION);
		break;
	case MCI_GPM_COEX_VERSION_RESPONSE:
		major = *(rx_payload + MCI_GPM_COEX_B_MAJOR_VERSION);
		minor = *(rx_payload + MCI_GPM_COEX_B_MINOR_VERSION);
		ar9003_mci_set_bt_version(ah, major, minor);
		break;
	case MCI_GPM_COEX_STATUS_QUERY:
		ar9003_mci_send_wlan_channels(ah);
		break;
	case MCI_GPM_COEX_BT_PROFILE_INFO:
		memcpy(&profile_info,
		       (rx_payload + MCI_GPM_COEX_B_PROFILE_TYPE), 10);

		if ((profile_info.type == MCI_GPM_COEX_PROFILE_UNKNOWN) ||
		    (profile_info.type >= MCI_GPM_COEX_PROFILE_MAX)) {
			ath_dbg(common, MCI,
				"Illegal profile type = %d, state = %d\n",
				profile_info.type,
				profile_info.start);
			break;
		}

		ath_mci_process_profile(sc, &profile_info);
		break;
	case MCI_GPM_COEX_BT_STATUS_UPDATE:
		profile_status.is_link = *(rx_payload +
					   MCI_GPM_COEX_B_STATUS_TYPE);
		profile_status.conn_handle = *(rx_payload +
					       MCI_GPM_COEX_B_STATUS_LINKID);
		profile_status.is_critical = *(rx_payload +
					       MCI_GPM_COEX_B_STATUS_STATE);

		seq_num = *((u32 *)(rx_payload + 12));
		ath_dbg(common, MCI,
			"BT_Status_Update: is_link=%d, linkId=%d, state=%d, SEQ=%u\n",
			profile_status.is_link, profile_status.conn_handle,
			profile_status.is_critical, seq_num);

		ath_mci_process_status(sc, &profile_status);
		break;
	default:
		ath_dbg(common, MCI, "Unknown GPM COEX message = 0x%02x\n", opcode);
		break;
	}
}

int ath_mci_setup(struct ath_softc *sc)
{
	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	struct ath_mci_coex *mci = &sc->mci_coex;
	struct ath_mci_buf *buf = &mci->sched_buf;

	buf->bf_addr = dma_alloc_coherent(sc->dev,
				  ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
				  &buf->bf_paddr, GFP_KERNEL);

	if (buf->bf_addr == NULL) {
		ath_dbg(common, FATAL, "MCI buffer alloc failed\n");
		return -ENOMEM;
	}

	memset(buf->bf_addr, MCI_GPM_RSVD_PATTERN,
	       ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE);

	mci->sched_buf.bf_len = ATH_MCI_SCHED_BUF_SIZE;

	mci->gpm_buf.bf_len = ATH_MCI_GPM_BUF_SIZE;
	mci->gpm_buf.bf_addr = (u8 *)mci->sched_buf.bf_addr + mci->sched_buf.bf_len;
	mci->gpm_buf.bf_paddr = mci->sched_buf.bf_paddr + mci->sched_buf.bf_len;

	ar9003_mci_setup(sc->sc_ah, mci->gpm_buf.bf_paddr,
			 mci->gpm_buf.bf_addr, (mci->gpm_buf.bf_len >> 4),
			 mci->sched_buf.bf_paddr);

	INIT_WORK(&sc->mci_work, ath9k_mci_work);
	ath_dbg(common, MCI, "MCI Initialized\n");

	return 0;
}

void ath_mci_cleanup(struct ath_softc *sc)
{
	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	struct ath_hw *ah = sc->sc_ah;
	struct ath_mci_coex *mci = &sc->mci_coex;
	struct ath_mci_buf *buf = &mci->sched_buf;

	if (buf->bf_addr)
		dma_free_coherent(sc->dev,
				  ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
				  buf->bf_addr, buf->bf_paddr);

	ar9003_mci_cleanup(ah);

	ath_dbg(common, MCI, "MCI De-Initialized\n");
}

void ath_mci_intr(struct ath_softc *sc)
{
	struct ath_mci_coex *mci = &sc->mci_coex;
	struct ath_hw *ah = sc->sc_ah;
	struct ath_common *common = ath9k_hw_common(ah);
	struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
	u32 mci_int, mci_int_rxmsg;
	u32 offset, subtype, opcode;
	u32 *pgpm;
	u32 more_data = MCI_GPM_MORE;
	bool skip_gpm = false;

	ar9003_mci_get_interrupt(sc->sc_ah, &mci_int, &mci_int_rxmsg);

	if (ar9003_mci_state(ah, MCI_STATE_ENABLE) == 0) {
		ar9003_mci_get_next_gpm_offset(ah, true, NULL);
		return;
	}

	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) {
		u32 payload[4] = { 0xffffffff, 0xffffffff,
				   0xffffffff, 0xffffff00};

		/*
		 * The following REMOTE_RESET and SYS_WAKING used to sent
		 * only when BT wake up. Now they are always sent, as a
		 * recovery method to reset BT MCI's RX alignment.
		 */
		ar9003_mci_send_message(ah, MCI_REMOTE_RESET, 0,
					payload, 16, true, false);
		ar9003_mci_send_message(ah, MCI_SYS_WAKING, 0,
					NULL, 0, true, false);

		mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE;
		ar9003_mci_state(ah, MCI_STATE_RESET_REQ_WAKE);

		/*
		 * always do this for recovery and 2G/5G toggling and LNA_TRANS
		 */
		ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE);
	}

	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING) {
		mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING;

		if ((mci_hw->bt_state == MCI_BT_SLEEP) &&
		    (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP) !=
		     MCI_BT_SLEEP))
			ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE);
	}

	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) {
		mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING;

		if ((mci_hw->bt_state == MCI_BT_AWAKE) &&
		    (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP) !=
		     MCI_BT_AWAKE))
			mci_hw->bt_state = MCI_BT_SLEEP;
	}

	if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
	    (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) {
		ar9003_mci_state(ah, MCI_STATE_RECOVER_RX);
		skip_gpm = true;
	}

	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO) {
		mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO;
		offset = ar9003_mci_state(ah, MCI_STATE_LAST_SCHD_MSG_OFFSET);
	}

	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_GPM) {
		mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_GPM;

		while (more_data == MCI_GPM_MORE) {

			pgpm = mci->gpm_buf.bf_addr;
			offset = ar9003_mci_get_next_gpm_offset(ah, false,
								&more_data);

			if (offset == MCI_GPM_INVALID)
				break;

			pgpm += (offset >> 2);

			/*
			 * The first dword is timer.
			 * The real data starts from 2nd dword.
			 */
			subtype = MCI_GPM_TYPE(pgpm);
			opcode = MCI_GPM_OPCODE(pgpm);

			if (skip_gpm)
				goto recycle;

			if (MCI_GPM_IS_CAL_TYPE(subtype)) {
				ath_mci_cal_msg(sc, subtype, (u8 *)pgpm);
			} else {
				switch (subtype) {
				case MCI_GPM_COEX_AGENT:
					ath_mci_msg(sc, opcode, (u8 *)pgpm);
					break;
				default:
					break;
				}
			}
		recycle:
			MCI_GPM_RECYCLE(pgpm);
		}
	}

	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_HW_MSG_MASK) {
		if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL)
			mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL;

		if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_INFO)
			mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_INFO;

		if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO) {
			int value_dbm = MS(mci_hw->cont_status,
					   AR_MCI_CONT_RSSI_POWER);

			mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_INFO;

			ath_dbg(common, MCI,
				"MCI CONT_INFO: (%s) pri = %d pwr = %d dBm\n",
				MS(mci_hw->cont_status, AR_MCI_CONT_TXRX) ?
				"tx" : "rx",
				MS(mci_hw->cont_status, AR_MCI_CONT_PRIORITY),
				value_dbm);
		}

		if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_NACK)
			mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_NACK;

		if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_RST)
			mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_RST;
	}

	if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
	    (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) {
		mci_int &= ~(AR_MCI_INTERRUPT_RX_INVALID_HDR |
			     AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT);
		ath_mci_msg(sc, MCI_GPM_COEX_NOOP, NULL);
	}
}

void ath_mci_enable(struct ath_softc *sc)
{
	struct ath_common *common = ath9k_hw_common(sc->sc_ah);

	if (!common->btcoex_enabled)
		return;

	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
		sc->sc_ah->imask |= ATH9K_INT_MCI;
}
Commit	Line	Data
7dc181c2 RM	1	/*
	2	* Copyright (c) 2010-2011 Atheros Communications Inc.
	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
9e25365f MSS	17	#include <linux/dma-mapping.h>
	18	#include <linux/slab.h>
	19
7dc181c2 RM	20	#include "ath9k.h"
	21	#include "mci.h"
	22
a197b76c	23	static const u8 ath_mci_duty_cycle[] = { 55, 50, 60, 70, 80, 85, 90, 95, 98 };
7dc181c2 RM	24
	25	static struct ath_mci_profile_info*
	26	ath_mci_find_profile(struct ath_mci_profile *mci,
	27	struct ath_mci_profile_info *info)
	28	{
	29	struct ath_mci_profile_info *entry;
	30
9e2e0c84 RM	31	if (list_empty(&mci->info))
	32	return NULL;
	33
7dc181c2 RM	34	list_for_each_entry(entry, &mci->info, list) {
7dc181c2 RM	35	if (entry->conn_handle == info->conn_handle)
9e2e0c84	36	return entry;
7dc181c2	37	}
9e2e0c84	38	return NULL;
7dc181c2 RM	39	}
	40
	41	static bool ath_mci_add_profile(struct ath_common *common,
	42	struct ath_mci_profile *mci,
	43	struct ath_mci_profile_info *info)
	44	{
	45	struct ath_mci_profile_info *entry;
	46
	47	if ((mci->num_sco == ATH_MCI_MAX_SCO_PROFILE) &&
682dd04b	48	(info->type == MCI_GPM_COEX_PROFILE_VOICE))
7dc181c2	49	return false;
7dc181c2 RM	50
7dc181c2 RM	51	if (((NUM_PROF(mci) - mci->num_sco) == ATH_MCI_MAX_ACL_PROFILE) &&
682dd04b	52	(info->type != MCI_GPM_COEX_PROFILE_VOICE))
7dc181c2	53	return false;
7dc181c2	54
3c7992e3	55	entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
9e2e0c84 RM	56	if (!entry)
9e2e0c84 RM	57	return false;
7dc181c2	58
9e2e0c84 RM	59	memcpy(entry, info, 10);
	60	INC_PROF(mci, info);
	61	list_add_tail(&entry->list, &mci->info);
682dd04b	62
7dc181c2 RM	63	return true;
	64	}
	65
	66	static void ath_mci_del_profile(struct ath_common *common,
	67	struct ath_mci_profile *mci,
9e2e0c84	68	struct ath_mci_profile_info *entry)
7dc181c2	69	{
682dd04b	70	if (!entry)
7dc181c2	71	return;
682dd04b	72
7dc181c2 RM	73	DEC_PROF(mci, entry);
	74	list_del(&entry->list);
	75	kfree(entry);
	76	}
	77
	78	void ath_mci_flush_profile(struct ath_mci_profile *mci)
	79	{
	80	struct ath_mci_profile_info info, tinfo;
	81
9e2e0c84	82	mci->aggr_limit = 0;
d92bb98f	83	mci->num_mgmt = 0;
9e2e0c84 RM	84
	85	if (list_empty(&mci->info))
	86	return;
	87
7dc181c2 RM	88	list_for_each_entry_safe(info, tinfo, &mci->info, list) {
	89	list_del(&info->list);
	90	DEC_PROF(mci, info);
	91	kfree(info);
	92	}
7dc181c2 RM	93	}
	94
	95	static void ath_mci_adjust_aggr_limit(struct ath_btcoex *btcoex)
	96	{
	97	struct ath_mci_profile *mci = &btcoex->mci;
	98	u32 wlan_airtime = btcoex->btcoex_period *
	99	(100 - btcoex->duty_cycle) / 100;
	100
	101	/*
	102	* Scale: wlan_airtime is in ms, aggr_limit is in 0.25 ms.
	103	* When wlan_airtime is less than 4ms, aggregation limit has to be
	104	* adjusted half of wlan_airtime to ensure that the aggregation can fit
	105	* without collision with BT traffic.
	106	*/
	107	if ((wlan_airtime <= 4) &&
	108	(!mci->aggr_limit \|\| (mci->aggr_limit > (2 * wlan_airtime))))
	109	mci->aggr_limit = 2 * wlan_airtime;
	110	}
	111
	112	static void ath_mci_update_scheme(struct ath_softc *sc)
	113	{
	114	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	115	struct ath_btcoex *btcoex = &sc->btcoex;
	116	struct ath_mci_profile *mci = &btcoex->mci;
0603143e	117	struct ath9k_hw_mci *mci_hw = &sc->sc_ah->btcoex_hw.mci;
7dc181c2 RM	118	struct ath_mci_profile_info *info;
	119	u32 num_profile = NUM_PROF(mci);
	120
0603143e RM	121	if (mci_hw->config & ATH_MCI_CONFIG_DISABLE_TUNING)
	122	goto skip_tuning;
	123
a197b76c RM	124	btcoex->duty_cycle = ath_mci_duty_cycle[num_profile];
a197b76c RM	125
7dc181c2 RM	126	if (num_profile == 1) {
	127	info = list_first_entry(&mci->info,
	128	struct ath_mci_profile_info,
	129	list);
0603143e RM	130	if (mci->num_sco) {
	131	if (info->T == 12)
	132	mci->aggr_limit = 8;
	133	else if (info->T == 6) {
	134	mci->aggr_limit = 6;
	135	btcoex->duty_cycle = 30;
	136	}
d2182b69	137	ath_dbg(common, MCI,
0603143e RM	138	"Single SCO, aggregation limit %d 1/4 ms\n",
	139	mci->aggr_limit);
	140	} else if (mci->num_pan \|\| mci->num_other_acl) {
	141	/*
	142	* For single PAN/FTP profile, allocate 35% for BT
	143	* to improve WLAN throughput.
	144	*/
	145	btcoex->duty_cycle = 35;
	146	btcoex->btcoex_period = 53;
d2182b69	147	ath_dbg(common, MCI,
0603143e RM	148	"Single PAN/FTP bt period %d ms dutycycle %d\n",
	149	btcoex->duty_cycle, btcoex->btcoex_period);
	150	} else if (mci->num_hid) {
7dc181c2	151	btcoex->duty_cycle = 30;
0603143e	152	mci->aggr_limit = 6;
d2182b69	153	ath_dbg(common, MCI,
7dc181c2	154	"Multiple attempt/timeout single HID "
0603143e	155	"aggregation limit 1.5 ms dutycycle 30%%\n");
7dc181c2	156	}
0603143e RM	157	} else if (num_profile == 2) {
	158	if (mci->num_hid == 2)
	159	btcoex->duty_cycle = 30;
7dc181c2	160	mci->aggr_limit = 6;
d2182b69	161	ath_dbg(common, MCI,
0603143e RM	162	"Two BT profiles aggr limit 1.5 ms dutycycle %d%%\n",
	163	btcoex->duty_cycle);
	164	} else if (num_profile >= 3) {
	165	mci->aggr_limit = 4;
	166	ath_dbg(common, MCI,
	167	"Three or more profiles aggregation limit 1 ms\n");
7dc181c2 RM	168	}
7dc181c2 RM	169
0603143e	170	skip_tuning:
7dc181c2 RM	171	if (IS_CHAN_2GHZ(sc->sc_ah->curchan)) {
	172	if (IS_CHAN_HT(sc->sc_ah->curchan))
	173	ath_mci_adjust_aggr_limit(btcoex);
	174	else
	175	btcoex->btcoex_period >>= 1;
	176	}
	177
7dc181c2	178	ath9k_btcoex_timer_pause(sc);
c32cdbd8	179	ath9k_hw_btcoex_disable(sc->sc_ah);
7dc181c2 RM	180
	181	if (IS_CHAN_5GHZ(sc->sc_ah->curchan))
	182	return;
	183
a197b76c	184	btcoex->duty_cycle += (mci->num_bdr ? ATH_MCI_BDR_DUTY_CYCLE : 0);
7dc181c2 RM	185	if (btcoex->duty_cycle > ATH_MCI_MAX_DUTY_CYCLE)
	186	btcoex->duty_cycle = ATH_MCI_MAX_DUTY_CYCLE;
	187
dfd0587a	188	btcoex->btcoex_no_stomp = btcoex->btcoex_period * 1000 *
682dd04b	189	(100 - btcoex->duty_cycle) / 100;
7dc181c2 RM	190
	191	ath9k_hw_btcoex_enable(sc->sc_ah);
	192	ath9k_btcoex_timer_resume(sc);
	193	}
	194
83ad49a9 RM	195	static void ath_mci_wait_btcal_done(struct ath_softc *sc)
	196	{
	197	struct ath_hw *ah = sc->sc_ah;
	198
	199	/* Stop tx & rx */
	200	ieee80211_stop_queues(sc->hw);
	201	ath_stoprecv(sc);
	202	ath_drain_all_txq(sc, false);
	203
	204	/* Wait for cal done */
	205	ar9003_mci_start_reset(ah, ah->curchan);
	206
	207	/* Resume tx & rx */
	208	ath_startrecv(sc);
	209	ieee80211_wake_queues(sc->hw);
	210	}
	211
19686ddf MSS	212	static void ath_mci_cal_msg(struct ath_softc sc, u8 opcode, u8 rx_payload)
	213	{
	214	struct ath_hw *ah = sc->sc_ah;
	215	struct ath_common *common = ath9k_hw_common(ah);
6d97be48	216	struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
19686ddf MSS	217	u32 payload[4] = {0, 0, 0, 0};
	218
	219	switch (opcode) {
	220	case MCI_GPM_BT_CAL_REQ:
6d97be48	221	if (mci_hw->bt_state == MCI_BT_AWAKE) {
4653356f	222	mci_hw->bt_state = MCI_BT_CAL_START;
83ad49a9	223	ath_mci_wait_btcal_done(sc);
682dd04b	224	}
6d97be48	225	ath_dbg(common, MCI, "MCI State : %d\n", mci_hw->bt_state);
19686ddf	226	break;
19686ddf	227	case MCI_GPM_BT_CAL_GRANT:
19686ddf MSS	228	MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_DONE);
	229	ar9003_mci_send_message(sc->sc_ah, MCI_GPM, 0, payload,
	230	16, false, true);
	231	break;
19686ddf	232	default:
682dd04b	233	ath_dbg(common, MCI, "Unknown GPM CAL message\n");
19686ddf MSS	234	break;
	235	}
	236	}
	237
3c7992e3 RM	238	static void ath9k_mci_work(struct work_struct *work)
	239	{
	240	struct ath_softc *sc = container_of(work, struct ath_softc, mci_work);
	241
	242	ath_mci_update_scheme(sc);
	243	}
	244
e5f0a276 FF	245	static void ath_mci_process_profile(struct ath_softc *sc,
e5f0a276 FF	246	struct ath_mci_profile_info *info)
7dc181c2 RM	247	{
	248	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	249	struct ath_btcoex *btcoex = &sc->btcoex;
	250	struct ath_mci_profile *mci = &btcoex->mci;
9e2e0c84 RM	251	struct ath_mci_profile_info *entry = NULL;
	252
	253	entry = ath_mci_find_profile(mci, info);
305dd09f BS	254	if (entry) {
	255	/*
	256	* Two MCI interrupts are generated while connecting to
	257	* headset and A2DP profile, but only one MCI interrupt
	258	* is generated with last added profile type while disconnecting
	259	* both profiles.
	260	* So while adding second profile type decrement
	261	* the first one.
	262	*/
	263	if (entry->type != info->type) {
	264	DEC_PROF(mci, entry);
	265	INC_PROF(mci, info);
	266	}
9e2e0c84	267	memcpy(entry, info, 10);
305dd09f	268	}
7dc181c2 RM	269
7dc181c2 RM	270	if (info->start) {
9e2e0c84	271	if (!entry && !ath_mci_add_profile(common, mci, info))
7dc181c2 RM	272	return;
7dc181c2 RM	273	} else
9e2e0c84	274	ath_mci_del_profile(common, mci, entry);
7dc181c2 RM	275
	276	btcoex->btcoex_period = ATH_MCI_DEF_BT_PERIOD;
	277	mci->aggr_limit = mci->num_sco ? 6 : 0;
682dd04b	278
a197b76c RM	279	btcoex->duty_cycle = ath_mci_duty_cycle[NUM_PROF(mci)];
a197b76c RM	280	if (NUM_PROF(mci))
7dc181c2	281	btcoex->bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
a197b76c	282	else
7dc181c2 RM	283	btcoex->bt_stomp_type = mci->num_mgmt ? ATH_BTCOEX_STOMP_ALL :
7dc181c2 RM	284	ATH_BTCOEX_STOMP_LOW;
7dc181c2	285
3c7992e3	286	ieee80211_queue_work(sc->hw, &sc->mci_work);
7dc181c2 RM	287	}
7dc181c2 RM	288
e5f0a276 FF	289	static void ath_mci_process_status(struct ath_softc *sc,
e5f0a276 FF	290	struct ath_mci_profile_status *status)
7dc181c2	291	{
7dc181c2 RM	292	struct ath_btcoex *btcoex = &sc->btcoex;
	293	struct ath_mci_profile *mci = &btcoex->mci;
	294	struct ath_mci_profile_info info;
	295	int i = 0, old_num_mgmt = mci->num_mgmt;
	296
	297	/* Link status type are not handled */
682dd04b	298	if (status->is_link)
7dc181c2	299	return;
7dc181c2	300
7dc181c2	301	info.conn_handle = status->conn_handle;
682dd04b	302	if (ath_mci_find_profile(mci, &info))
7dc181c2	303	return;
682dd04b SM	304
682dd04b SM	305	if (status->conn_handle >= ATH_MCI_MAX_PROFILE)
7dc181c2	306	return;
682dd04b	307
7dc181c2 RM	308	if (status->is_critical)
	309	__set_bit(status->conn_handle, mci->status);
	310	else
	311	__clear_bit(status->conn_handle, mci->status);
	312
	313	mci->num_mgmt = 0;
	314	do {
	315	if (test_bit(i, mci->status))
	316	mci->num_mgmt++;
	317	} while (++i < ATH_MCI_MAX_PROFILE);
	318
	319	if (old_num_mgmt != mci->num_mgmt)
3c7992e3	320	ieee80211_queue_work(sc->hw, &sc->mci_work);
7dc181c2	321	}
9e25365f	322
19686ddf MSS	323	static void ath_mci_msg(struct ath_softc sc, u8 opcode, u8 rx_payload)
	324	{
	325	struct ath_hw *ah = sc->sc_ah;
	326	struct ath_mci_profile_info profile_info;
	327	struct ath_mci_profile_status profile_status;
	328	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
e1763d3f	329	u8 major, minor;
19686ddf MSS	330	u32 seq_num;
19686ddf MSS	331
d92bb98f RM	332	if (ar9003_mci_state(ah, MCI_STATE_NEED_FLUSH_BT_INFO) &&
	333	ar9003_mci_state(ah, MCI_STATE_ENABLE)) {
	334	ath_dbg(common, MCI, "(MCI) Need to flush BT profiles\n");
	335	ath_mci_flush_profile(&sc->btcoex.mci);
	336	ar9003_mci_state(ah, MCI_STATE_SEND_STATUS_QUERY);
	337	}
	338
19686ddf	339	switch (opcode) {
19686ddf	340	case MCI_GPM_COEX_VERSION_QUERY:
b98ccec0	341	ar9003_mci_state(ah, MCI_STATE_SEND_WLAN_COEX_VERSION);
19686ddf	342	break;
19686ddf	343	case MCI_GPM_COEX_VERSION_RESPONSE:
19686ddf MSS	344	major = *(rx_payload + MCI_GPM_COEX_B_MAJOR_VERSION);
19686ddf MSS	345	minor = *(rx_payload + MCI_GPM_COEX_B_MINOR_VERSION);
e1763d3f	346	ar9003_mci_set_bt_version(ah, major, minor);
19686ddf	347	break;
19686ddf	348	case MCI_GPM_COEX_STATUS_QUERY:
2d340ac8	349	ar9003_mci_send_wlan_channels(ah);
19686ddf	350	break;
19686ddf	351	case MCI_GPM_COEX_BT_PROFILE_INFO:
19686ddf MSS	352	memcpy(&profile_info,
	353	(rx_payload + MCI_GPM_COEX_B_PROFILE_TYPE), 10);
	354
682dd04b SM	355	if ((profile_info.type == MCI_GPM_COEX_PROFILE_UNKNOWN) \|\|
682dd04b SM	356	(profile_info.type >= MCI_GPM_COEX_PROFILE_MAX)) {
d2182b69	357	ath_dbg(common, MCI,
682dd04b	358	"Illegal profile type = %d, state = %d\n",
d2182b69	359	profile_info.type,
19686ddf MSS	360	profile_info.start);
	361	break;
	362	}
	363
	364	ath_mci_process_profile(sc, &profile_info);
	365	break;
19686ddf MSS	366	case MCI_GPM_COEX_BT_STATUS_UPDATE:
	367	profile_status.is_link = *(rx_payload +
	368	MCI_GPM_COEX_B_STATUS_TYPE);
	369	profile_status.conn_handle = *(rx_payload +
	370	MCI_GPM_COEX_B_STATUS_LINKID);
	371	profile_status.is_critical = *(rx_payload +
	372	MCI_GPM_COEX_B_STATUS_STATE);
	373
	374	seq_num = ((u32 )(rx_payload + 12));
d2182b69	375	ath_dbg(common, MCI,
d8fffb4a	376	"BT_Status_Update: is_link=%d, linkId=%d, state=%d, SEQ=%u\n",
19686ddf MSS	377	profile_status.is_link, profile_status.conn_handle,
	378	profile_status.is_critical, seq_num);
	379
	380	ath_mci_process_status(sc, &profile_status);
	381	break;
19686ddf	382	default:
682dd04b	383	ath_dbg(common, MCI, "Unknown GPM COEX message = 0x%02x\n", opcode);
19686ddf MSS	384	break;
	385	}
	386	}
9e25365f	387
9e25365f MSS	388	int ath_mci_setup(struct ath_softc *sc)
	389	{
	390	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	391	struct ath_mci_coex *mci = &sc->mci_coex;
ea510e4b	392	struct ath_mci_buf *buf = &mci->sched_buf;
9e25365f	393
ea510e4b SM	394	buf->bf_addr = dma_alloc_coherent(sc->dev,
	395	ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
	396	&buf->bf_paddr, GFP_KERNEL);
9e25365f	397
ea510e4b	398	if (buf->bf_addr == NULL) {
d2182b69	399	ath_dbg(common, FATAL, "MCI buffer alloc failed\n");
ea510e4b	400	return -ENOMEM;
9e25365f MSS	401	}
9e25365f MSS	402
ea510e4b SM	403	memset(buf->bf_addr, MCI_GPM_RSVD_PATTERN,
ea510e4b SM	404	ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE);
9e25365f	405
ea510e4b	406	mci->sched_buf.bf_len = ATH_MCI_SCHED_BUF_SIZE;
9e25365f MSS	407
9e25365f MSS	408	mci->gpm_buf.bf_len = ATH_MCI_GPM_BUF_SIZE;
ea510e4b	409	mci->gpm_buf.bf_addr = (u8 *)mci->sched_buf.bf_addr + mci->sched_buf.bf_len;
9e25365f MSS	410	mci->gpm_buf.bf_paddr = mci->sched_buf.bf_paddr + mci->sched_buf.bf_len;
9e25365f MSS	411
9e25365f MSS	412	ar9003_mci_setup(sc->sc_ah, mci->gpm_buf.bf_paddr,
	413	mci->gpm_buf.bf_addr, (mci->gpm_buf.bf_len >> 4),
	414	mci->sched_buf.bf_paddr);
ea510e4b	415
3c7992e3	416	INIT_WORK(&sc->mci_work, ath9k_mci_work);
ea510e4b SM	417	ath_dbg(common, MCI, "MCI Initialized\n");
	418
	419	return 0;
9e25365f MSS	420	}
	421
	422	void ath_mci_cleanup(struct ath_softc *sc)
	423	{
ea510e4b	424	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
9e25365f MSS	425	struct ath_hw *ah = sc->sc_ah;
9e25365f MSS	426	struct ath_mci_coex *mci = &sc->mci_coex;
ea510e4b	427	struct ath_mci_buf *buf = &mci->sched_buf;
9e25365f	428
ea510e4b SM	429	if (buf->bf_addr)
	430	dma_free_coherent(sc->dev,
	431	ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
	432	buf->bf_addr, buf->bf_paddr);
	433
9e25365f	434	ar9003_mci_cleanup(ah);
ea510e4b SM	435
ea510e4b SM	436	ath_dbg(common, MCI, "MCI De-Initialized\n");
9e25365f	437	}
19686ddf MSS	438
	439	void ath_mci_intr(struct ath_softc *sc)
	440	{
	441	struct ath_mci_coex *mci = &sc->mci_coex;
	442	struct ath_hw *ah = sc->sc_ah;
	443	struct ath_common *common = ath9k_hw_common(ah);
6d97be48	444	struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
19686ddf MSS	445	u32 mci_int, mci_int_rxmsg;
	446	u32 offset, subtype, opcode;
	447	u32 *pgpm;
	448	u32 more_data = MCI_GPM_MORE;
	449	bool skip_gpm = false;
	450
	451	ar9003_mci_get_interrupt(sc->sc_ah, &mci_int, &mci_int_rxmsg);
	452
b98ccec0	453	if (ar9003_mci_state(ah, MCI_STATE_ENABLE) == 0) {
506847ad	454	ar9003_mci_get_next_gpm_offset(ah, true, NULL);
19686ddf MSS	455	return;
	456	}
	457
	458	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) {
	459	u32 payload[4] = { 0xffffffff, 0xffffffff,
	460	0xffffffff, 0xffffff00};
	461
	462	/*
	463	* The following REMOTE_RESET and SYS_WAKING used to sent
	464	* only when BT wake up. Now they are always sent, as a
	465	* recovery method to reset BT MCI's RX alignment.
	466	*/
19686ddf MSS	467	ar9003_mci_send_message(ah, MCI_REMOTE_RESET, 0,
19686ddf MSS	468	payload, 16, true, false);
19686ddf MSS	469	ar9003_mci_send_message(ah, MCI_SYS_WAKING, 0,
	470	NULL, 0, true, false);
	471
	472	mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE;
b98ccec0	473	ar9003_mci_state(ah, MCI_STATE_RESET_REQ_WAKE);
19686ddf MSS	474
	475	/*
	476	* always do this for recovery and 2G/5G toggling and LNA_TRANS
	477	*/
b98ccec0	478	ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE);
19686ddf MSS	479	}
19686ddf MSS	480
19686ddf MSS	481	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING) {
	482	mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING;
	483
6d97be48	484	if ((mci_hw->bt_state == MCI_BT_SLEEP) &&
b98ccec0 RM	485	(ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP) !=
	486	MCI_BT_SLEEP))
	487	ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE);
19686ddf MSS	488	}
	489
	490	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) {
19686ddf MSS	491	mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING;
19686ddf MSS	492
6d97be48	493	if ((mci_hw->bt_state == MCI_BT_AWAKE) &&
b98ccec0 RM	494	(ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP) !=
b98ccec0 RM	495	MCI_BT_AWAKE))
9330969b	496	mci_hw->bt_state = MCI_BT_SLEEP;
19686ddf MSS	497	}
	498
	499	if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) \|\|
	500	(mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) {
b98ccec0	501	ar9003_mci_state(ah, MCI_STATE_RECOVER_RX);
19686ddf MSS	502	skip_gpm = true;
	503	}
	504
	505	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO) {
19686ddf	506	mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO;
b98ccec0	507	offset = ar9003_mci_state(ah, MCI_STATE_LAST_SCHD_MSG_OFFSET);
19686ddf MSS	508	}
	509
	510	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_GPM) {
19686ddf MSS	511	mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_GPM;
	512
	513	while (more_data == MCI_GPM_MORE) {
	514
	515	pgpm = mci->gpm_buf.bf_addr;
506847ad RM	516	offset = ar9003_mci_get_next_gpm_offset(ah, false,
506847ad RM	517	&more_data);
19686ddf MSS	518
	519	if (offset == MCI_GPM_INVALID)
	520	break;
	521
	522	pgpm += (offset >> 2);
	523
	524	/*
	525	* The first dword is timer.
	526	* The real data starts from 2nd dword.
	527	*/
19686ddf MSS	528	subtype = MCI_GPM_TYPE(pgpm);
	529	opcode = MCI_GPM_OPCODE(pgpm);
	530
682dd04b SM	531	if (skip_gpm)
	532	goto recycle;
	533
	534	if (MCI_GPM_IS_CAL_TYPE(subtype)) {
	535	ath_mci_cal_msg(sc, subtype, (u8 *)pgpm);
	536	} else {
	537	switch (subtype) {
	538	case MCI_GPM_COEX_AGENT:
	539	ath_mci_msg(sc, opcode, (u8 *)pgpm);
	540	break;
	541	default:
	542	break;
19686ddf MSS	543	}
19686ddf MSS	544	}
682dd04b	545	recycle:
19686ddf MSS	546	MCI_GPM_RECYCLE(pgpm);
	547	}
	548	}
	549
	550	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_HW_MSG_MASK) {
19686ddf MSS	551	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL)
	552	mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL;
	553
682dd04b	554	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_INFO)
19686ddf	555	mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_INFO;
19686ddf MSS	556
19686ddf MSS	557	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO) {
26e942b7 RM	558	int value_dbm = MS(mci_hw->cont_status,
26e942b7 RM	559	AR_MCI_CONT_RSSI_POWER);
19686ddf MSS	560
	561	mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_INFO;
	562
26e942b7 RM	563	ath_dbg(common, MCI,
	564	"MCI CONT_INFO: (%s) pri = %d pwr = %d dBm\n",
	565	MS(mci_hw->cont_status, AR_MCI_CONT_TXRX) ?
	566	"tx" : "rx",
	567	MS(mci_hw->cont_status, AR_MCI_CONT_PRIORITY),
	568	value_dbm);
19686ddf MSS	569	}
19686ddf MSS	570
682dd04b	571	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_NACK)
19686ddf	572	mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_NACK;
19686ddf	573
682dd04b	574	if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_RST)
19686ddf	575	mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_RST;
19686ddf MSS	576	}
	577
	578	if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) \|\|
d92bb98f	579	(mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) {
19686ddf MSS	580	mci_int &= ~(AR_MCI_INTERRUPT_RX_INVALID_HDR \|
19686ddf MSS	581	AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT);
d92bb98f RM	582	ath_mci_msg(sc, MCI_GPM_COEX_NOOP, NULL);
d92bb98f RM	583	}
19686ddf	584	}
e270e776 SM	585
	586	void ath_mci_enable(struct ath_softc *sc)
	587	{
	588	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	589
	590	if (!common->btcoex_enabled)
	591	return;
	592
	593	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
	594	sc->sc_ah->imask \|= ATH9K_INT_MCI;
	595	}