Commit | Line | Data |
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7dc181c2 RM |
1 | /* |
2 | * Copyright (c) 2010-2011 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
9e25365f MSS |
17 | #include <linux/dma-mapping.h> |
18 | #include <linux/slab.h> | |
19 | ||
7dc181c2 RM |
20 | #include "ath9k.h" |
21 | #include "mci.h" | |
22 | ||
6ec414fd | 23 | static const u8 ath_mci_duty_cycle[] = { 0, 50, 60, 70, 80, 85, 90, 95, 98 }; |
7dc181c2 RM |
24 | |
25 | static struct ath_mci_profile_info* | |
26 | ath_mci_find_profile(struct ath_mci_profile *mci, | |
27 | struct ath_mci_profile_info *info) | |
28 | { | |
29 | struct ath_mci_profile_info *entry; | |
30 | ||
9e2e0c84 RM |
31 | if (list_empty(&mci->info)) |
32 | return NULL; | |
33 | ||
7dc181c2 RM |
34 | list_for_each_entry(entry, &mci->info, list) { |
35 | if (entry->conn_handle == info->conn_handle) | |
9e2e0c84 | 36 | return entry; |
7dc181c2 | 37 | } |
9e2e0c84 | 38 | return NULL; |
7dc181c2 RM |
39 | } |
40 | ||
41 | static bool ath_mci_add_profile(struct ath_common *common, | |
42 | struct ath_mci_profile *mci, | |
43 | struct ath_mci_profile_info *info) | |
44 | { | |
45 | struct ath_mci_profile_info *entry; | |
46 | ||
47 | if ((mci->num_sco == ATH_MCI_MAX_SCO_PROFILE) && | |
682dd04b | 48 | (info->type == MCI_GPM_COEX_PROFILE_VOICE)) |
7dc181c2 | 49 | return false; |
7dc181c2 RM |
50 | |
51 | if (((NUM_PROF(mci) - mci->num_sco) == ATH_MCI_MAX_ACL_PROFILE) && | |
682dd04b | 52 | (info->type != MCI_GPM_COEX_PROFILE_VOICE)) |
7dc181c2 | 53 | return false; |
7dc181c2 | 54 | |
9e2e0c84 RM |
55 | entry = kzalloc(sizeof(*entry), GFP_KERNEL); |
56 | if (!entry) | |
57 | return false; | |
7dc181c2 | 58 | |
9e2e0c84 RM |
59 | memcpy(entry, info, 10); |
60 | INC_PROF(mci, info); | |
61 | list_add_tail(&entry->list, &mci->info); | |
682dd04b | 62 | |
7dc181c2 RM |
63 | return true; |
64 | } | |
65 | ||
66 | static void ath_mci_del_profile(struct ath_common *common, | |
67 | struct ath_mci_profile *mci, | |
9e2e0c84 | 68 | struct ath_mci_profile_info *entry) |
7dc181c2 | 69 | { |
682dd04b | 70 | if (!entry) |
7dc181c2 | 71 | return; |
682dd04b | 72 | |
7dc181c2 RM |
73 | DEC_PROF(mci, entry); |
74 | list_del(&entry->list); | |
75 | kfree(entry); | |
76 | } | |
77 | ||
78 | void ath_mci_flush_profile(struct ath_mci_profile *mci) | |
79 | { | |
80 | struct ath_mci_profile_info *info, *tinfo; | |
81 | ||
9e2e0c84 RM |
82 | mci->aggr_limit = 0; |
83 | ||
84 | if (list_empty(&mci->info)) | |
85 | return; | |
86 | ||
7dc181c2 RM |
87 | list_for_each_entry_safe(info, tinfo, &mci->info, list) { |
88 | list_del(&info->list); | |
89 | DEC_PROF(mci, info); | |
90 | kfree(info); | |
91 | } | |
7dc181c2 RM |
92 | } |
93 | ||
94 | static void ath_mci_adjust_aggr_limit(struct ath_btcoex *btcoex) | |
95 | { | |
96 | struct ath_mci_profile *mci = &btcoex->mci; | |
97 | u32 wlan_airtime = btcoex->btcoex_period * | |
98 | (100 - btcoex->duty_cycle) / 100; | |
99 | ||
100 | /* | |
101 | * Scale: wlan_airtime is in ms, aggr_limit is in 0.25 ms. | |
102 | * When wlan_airtime is less than 4ms, aggregation limit has to be | |
103 | * adjusted half of wlan_airtime to ensure that the aggregation can fit | |
104 | * without collision with BT traffic. | |
105 | */ | |
106 | if ((wlan_airtime <= 4) && | |
107 | (!mci->aggr_limit || (mci->aggr_limit > (2 * wlan_airtime)))) | |
108 | mci->aggr_limit = 2 * wlan_airtime; | |
109 | } | |
110 | ||
111 | static void ath_mci_update_scheme(struct ath_softc *sc) | |
112 | { | |
113 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
114 | struct ath_btcoex *btcoex = &sc->btcoex; | |
115 | struct ath_mci_profile *mci = &btcoex->mci; | |
0603143e | 116 | struct ath9k_hw_mci *mci_hw = &sc->sc_ah->btcoex_hw.mci; |
7dc181c2 RM |
117 | struct ath_mci_profile_info *info; |
118 | u32 num_profile = NUM_PROF(mci); | |
119 | ||
0603143e RM |
120 | if (mci_hw->config & ATH_MCI_CONFIG_DISABLE_TUNING) |
121 | goto skip_tuning; | |
122 | ||
7dc181c2 RM |
123 | if (num_profile == 1) { |
124 | info = list_first_entry(&mci->info, | |
125 | struct ath_mci_profile_info, | |
126 | list); | |
0603143e RM |
127 | if (mci->num_sco) { |
128 | if (info->T == 12) | |
129 | mci->aggr_limit = 8; | |
130 | else if (info->T == 6) { | |
131 | mci->aggr_limit = 6; | |
132 | btcoex->duty_cycle = 30; | |
133 | } | |
d2182b69 | 134 | ath_dbg(common, MCI, |
0603143e RM |
135 | "Single SCO, aggregation limit %d 1/4 ms\n", |
136 | mci->aggr_limit); | |
137 | } else if (mci->num_pan || mci->num_other_acl) { | |
138 | /* | |
139 | * For single PAN/FTP profile, allocate 35% for BT | |
140 | * to improve WLAN throughput. | |
141 | */ | |
142 | btcoex->duty_cycle = 35; | |
143 | btcoex->btcoex_period = 53; | |
d2182b69 | 144 | ath_dbg(common, MCI, |
0603143e RM |
145 | "Single PAN/FTP bt period %d ms dutycycle %d\n", |
146 | btcoex->duty_cycle, btcoex->btcoex_period); | |
147 | } else if (mci->num_hid) { | |
7dc181c2 | 148 | btcoex->duty_cycle = 30; |
0603143e | 149 | mci->aggr_limit = 6; |
d2182b69 | 150 | ath_dbg(common, MCI, |
7dc181c2 | 151 | "Multiple attempt/timeout single HID " |
0603143e | 152 | "aggregation limit 1.5 ms dutycycle 30%%\n"); |
7dc181c2 | 153 | } |
0603143e RM |
154 | } else if (num_profile == 2) { |
155 | if (mci->num_hid == 2) | |
156 | btcoex->duty_cycle = 30; | |
7dc181c2 | 157 | mci->aggr_limit = 6; |
d2182b69 | 158 | ath_dbg(common, MCI, |
0603143e RM |
159 | "Two BT profiles aggr limit 1.5 ms dutycycle %d%%\n", |
160 | btcoex->duty_cycle); | |
161 | } else if (num_profile >= 3) { | |
162 | mci->aggr_limit = 4; | |
163 | ath_dbg(common, MCI, | |
164 | "Three or more profiles aggregation limit 1 ms\n"); | |
7dc181c2 RM |
165 | } |
166 | ||
0603143e | 167 | skip_tuning: |
7dc181c2 RM |
168 | if (IS_CHAN_2GHZ(sc->sc_ah->curchan)) { |
169 | if (IS_CHAN_HT(sc->sc_ah->curchan)) | |
170 | ath_mci_adjust_aggr_limit(btcoex); | |
171 | else | |
172 | btcoex->btcoex_period >>= 1; | |
173 | } | |
174 | ||
175 | ath9k_hw_btcoex_disable(sc->sc_ah); | |
176 | ath9k_btcoex_timer_pause(sc); | |
177 | ||
178 | if (IS_CHAN_5GHZ(sc->sc_ah->curchan)) | |
179 | return; | |
180 | ||
181 | btcoex->duty_cycle += (mci->num_bdr ? ATH_MCI_MAX_DUTY_CYCLE : 0); | |
182 | if (btcoex->duty_cycle > ATH_MCI_MAX_DUTY_CYCLE) | |
183 | btcoex->duty_cycle = ATH_MCI_MAX_DUTY_CYCLE; | |
184 | ||
dfd0587a | 185 | btcoex->btcoex_no_stomp = btcoex->btcoex_period * 1000 * |
682dd04b | 186 | (100 - btcoex->duty_cycle) / 100; |
7dc181c2 RM |
187 | |
188 | ath9k_hw_btcoex_enable(sc->sc_ah); | |
189 | ath9k_btcoex_timer_resume(sc); | |
190 | } | |
191 | ||
19686ddf MSS |
192 | static void ath_mci_cal_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload) |
193 | { | |
194 | struct ath_hw *ah = sc->sc_ah; | |
195 | struct ath_common *common = ath9k_hw_common(ah); | |
196 | u32 payload[4] = {0, 0, 0, 0}; | |
197 | ||
198 | switch (opcode) { | |
199 | case MCI_GPM_BT_CAL_REQ: | |
19686ddf MSS |
200 | if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_AWAKE) { |
201 | ar9003_mci_state(ah, MCI_STATE_SET_BT_CAL_START, NULL); | |
202 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); | |
682dd04b SM |
203 | } else { |
204 | ath_dbg(common, MCI, "MCI State mismatch: %d\n", | |
19686ddf | 205 | ar9003_mci_state(ah, MCI_STATE_BT, NULL)); |
682dd04b | 206 | } |
19686ddf | 207 | break; |
19686ddf | 208 | case MCI_GPM_BT_CAL_DONE: |
682dd04b | 209 | ar9003_mci_state(ah, MCI_STATE_BT, NULL); |
19686ddf | 210 | break; |
19686ddf | 211 | case MCI_GPM_BT_CAL_GRANT: |
19686ddf MSS |
212 | MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_DONE); |
213 | ar9003_mci_send_message(sc->sc_ah, MCI_GPM, 0, payload, | |
214 | 16, false, true); | |
215 | break; | |
19686ddf | 216 | default: |
682dd04b | 217 | ath_dbg(common, MCI, "Unknown GPM CAL message\n"); |
19686ddf MSS |
218 | break; |
219 | } | |
220 | } | |
221 | ||
e5f0a276 FF |
222 | static void ath_mci_process_profile(struct ath_softc *sc, |
223 | struct ath_mci_profile_info *info) | |
7dc181c2 RM |
224 | { |
225 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
226 | struct ath_btcoex *btcoex = &sc->btcoex; | |
227 | struct ath_mci_profile *mci = &btcoex->mci; | |
9e2e0c84 RM |
228 | struct ath_mci_profile_info *entry = NULL; |
229 | ||
230 | entry = ath_mci_find_profile(mci, info); | |
231 | if (entry) | |
232 | memcpy(entry, info, 10); | |
7dc181c2 RM |
233 | |
234 | if (info->start) { | |
9e2e0c84 | 235 | if (!entry && !ath_mci_add_profile(common, mci, info)) |
7dc181c2 RM |
236 | return; |
237 | } else | |
9e2e0c84 | 238 | ath_mci_del_profile(common, mci, entry); |
7dc181c2 RM |
239 | |
240 | btcoex->btcoex_period = ATH_MCI_DEF_BT_PERIOD; | |
241 | mci->aggr_limit = mci->num_sco ? 6 : 0; | |
682dd04b | 242 | |
7dc181c2 RM |
243 | if (NUM_PROF(mci)) { |
244 | btcoex->bt_stomp_type = ATH_BTCOEX_STOMP_LOW; | |
245 | btcoex->duty_cycle = ath_mci_duty_cycle[NUM_PROF(mci)]; | |
246 | } else { | |
247 | btcoex->bt_stomp_type = mci->num_mgmt ? ATH_BTCOEX_STOMP_ALL : | |
248 | ATH_BTCOEX_STOMP_LOW; | |
249 | btcoex->duty_cycle = ATH_BTCOEX_DEF_DUTY_CYCLE; | |
250 | } | |
251 | ||
252 | ath_mci_update_scheme(sc); | |
253 | } | |
254 | ||
e5f0a276 FF |
255 | static void ath_mci_process_status(struct ath_softc *sc, |
256 | struct ath_mci_profile_status *status) | |
7dc181c2 | 257 | { |
7dc181c2 RM |
258 | struct ath_btcoex *btcoex = &sc->btcoex; |
259 | struct ath_mci_profile *mci = &btcoex->mci; | |
260 | struct ath_mci_profile_info info; | |
261 | int i = 0, old_num_mgmt = mci->num_mgmt; | |
262 | ||
263 | /* Link status type are not handled */ | |
682dd04b | 264 | if (status->is_link) |
7dc181c2 | 265 | return; |
7dc181c2 | 266 | |
7dc181c2 | 267 | info.conn_handle = status->conn_handle; |
682dd04b | 268 | if (ath_mci_find_profile(mci, &info)) |
7dc181c2 | 269 | return; |
682dd04b SM |
270 | |
271 | if (status->conn_handle >= ATH_MCI_MAX_PROFILE) | |
7dc181c2 | 272 | return; |
682dd04b | 273 | |
7dc181c2 RM |
274 | if (status->is_critical) |
275 | __set_bit(status->conn_handle, mci->status); | |
276 | else | |
277 | __clear_bit(status->conn_handle, mci->status); | |
278 | ||
279 | mci->num_mgmt = 0; | |
280 | do { | |
281 | if (test_bit(i, mci->status)) | |
282 | mci->num_mgmt++; | |
283 | } while (++i < ATH_MCI_MAX_PROFILE); | |
284 | ||
285 | if (old_num_mgmt != mci->num_mgmt) | |
286 | ath_mci_update_scheme(sc); | |
287 | } | |
9e25365f | 288 | |
19686ddf MSS |
289 | static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload) |
290 | { | |
291 | struct ath_hw *ah = sc->sc_ah; | |
292 | struct ath_mci_profile_info profile_info; | |
293 | struct ath_mci_profile_status profile_status; | |
294 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
295 | u32 version; | |
296 | u8 major; | |
297 | u8 minor; | |
298 | u32 seq_num; | |
299 | ||
300 | switch (opcode) { | |
19686ddf | 301 | case MCI_GPM_COEX_VERSION_QUERY: |
682dd04b SM |
302 | version = ar9003_mci_state(ah, MCI_STATE_SEND_WLAN_COEX_VERSION, |
303 | NULL); | |
19686ddf | 304 | break; |
19686ddf | 305 | case MCI_GPM_COEX_VERSION_RESPONSE: |
19686ddf MSS |
306 | major = *(rx_payload + MCI_GPM_COEX_B_MAJOR_VERSION); |
307 | minor = *(rx_payload + MCI_GPM_COEX_B_MINOR_VERSION); | |
19686ddf | 308 | version = (major << 8) + minor; |
682dd04b SM |
309 | version = ar9003_mci_state(ah, MCI_STATE_SET_BT_COEX_VERSION, |
310 | &version); | |
19686ddf | 311 | break; |
19686ddf | 312 | case MCI_GPM_COEX_STATUS_QUERY: |
682dd04b | 313 | ar9003_mci_state(ah, MCI_STATE_SEND_WLAN_CHANNELS, NULL); |
19686ddf | 314 | break; |
19686ddf | 315 | case MCI_GPM_COEX_BT_PROFILE_INFO: |
19686ddf MSS |
316 | memcpy(&profile_info, |
317 | (rx_payload + MCI_GPM_COEX_B_PROFILE_TYPE), 10); | |
318 | ||
682dd04b SM |
319 | if ((profile_info.type == MCI_GPM_COEX_PROFILE_UNKNOWN) || |
320 | (profile_info.type >= MCI_GPM_COEX_PROFILE_MAX)) { | |
d2182b69 | 321 | ath_dbg(common, MCI, |
682dd04b | 322 | "Illegal profile type = %d, state = %d\n", |
d2182b69 | 323 | profile_info.type, |
19686ddf MSS |
324 | profile_info.start); |
325 | break; | |
326 | } | |
327 | ||
328 | ath_mci_process_profile(sc, &profile_info); | |
329 | break; | |
19686ddf MSS |
330 | case MCI_GPM_COEX_BT_STATUS_UPDATE: |
331 | profile_status.is_link = *(rx_payload + | |
332 | MCI_GPM_COEX_B_STATUS_TYPE); | |
333 | profile_status.conn_handle = *(rx_payload + | |
334 | MCI_GPM_COEX_B_STATUS_LINKID); | |
335 | profile_status.is_critical = *(rx_payload + | |
336 | MCI_GPM_COEX_B_STATUS_STATE); | |
337 | ||
338 | seq_num = *((u32 *)(rx_payload + 12)); | |
d2182b69 | 339 | ath_dbg(common, MCI, |
682dd04b | 340 | "BT_Status_Update: is_link=%d, linkId=%d, state=%d, SEQ=%d\n", |
19686ddf MSS |
341 | profile_status.is_link, profile_status.conn_handle, |
342 | profile_status.is_critical, seq_num); | |
343 | ||
344 | ath_mci_process_status(sc, &profile_status); | |
345 | break; | |
19686ddf | 346 | default: |
682dd04b | 347 | ath_dbg(common, MCI, "Unknown GPM COEX message = 0x%02x\n", opcode); |
19686ddf MSS |
348 | break; |
349 | } | |
350 | } | |
9e25365f | 351 | |
9e25365f MSS |
352 | int ath_mci_setup(struct ath_softc *sc) |
353 | { | |
354 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
355 | struct ath_mci_coex *mci = &sc->mci_coex; | |
ea510e4b | 356 | struct ath_mci_buf *buf = &mci->sched_buf; |
9e25365f | 357 | |
ea510e4b SM |
358 | buf->bf_addr = dma_alloc_coherent(sc->dev, |
359 | ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE, | |
360 | &buf->bf_paddr, GFP_KERNEL); | |
9e25365f | 361 | |
ea510e4b | 362 | if (buf->bf_addr == NULL) { |
d2182b69 | 363 | ath_dbg(common, FATAL, "MCI buffer alloc failed\n"); |
ea510e4b | 364 | return -ENOMEM; |
9e25365f MSS |
365 | } |
366 | ||
ea510e4b SM |
367 | memset(buf->bf_addr, MCI_GPM_RSVD_PATTERN, |
368 | ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE); | |
9e25365f | 369 | |
ea510e4b | 370 | mci->sched_buf.bf_len = ATH_MCI_SCHED_BUF_SIZE; |
9e25365f MSS |
371 | |
372 | mci->gpm_buf.bf_len = ATH_MCI_GPM_BUF_SIZE; | |
ea510e4b | 373 | mci->gpm_buf.bf_addr = (u8 *)mci->sched_buf.bf_addr + mci->sched_buf.bf_len; |
9e25365f MSS |
374 | mci->gpm_buf.bf_paddr = mci->sched_buf.bf_paddr + mci->sched_buf.bf_len; |
375 | ||
9e25365f MSS |
376 | ar9003_mci_setup(sc->sc_ah, mci->gpm_buf.bf_paddr, |
377 | mci->gpm_buf.bf_addr, (mci->gpm_buf.bf_len >> 4), | |
378 | mci->sched_buf.bf_paddr); | |
ea510e4b SM |
379 | |
380 | ath_dbg(common, MCI, "MCI Initialized\n"); | |
381 | ||
382 | return 0; | |
9e25365f MSS |
383 | } |
384 | ||
385 | void ath_mci_cleanup(struct ath_softc *sc) | |
386 | { | |
ea510e4b | 387 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
9e25365f MSS |
388 | struct ath_hw *ah = sc->sc_ah; |
389 | struct ath_mci_coex *mci = &sc->mci_coex; | |
ea510e4b | 390 | struct ath_mci_buf *buf = &mci->sched_buf; |
9e25365f | 391 | |
ea510e4b SM |
392 | if (buf->bf_addr) |
393 | dma_free_coherent(sc->dev, | |
394 | ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE, | |
395 | buf->bf_addr, buf->bf_paddr); | |
396 | ||
9e25365f | 397 | ar9003_mci_cleanup(ah); |
ea510e4b SM |
398 | |
399 | ath_dbg(common, MCI, "MCI De-Initialized\n"); | |
9e25365f | 400 | } |
19686ddf MSS |
401 | |
402 | void ath_mci_intr(struct ath_softc *sc) | |
403 | { | |
404 | struct ath_mci_coex *mci = &sc->mci_coex; | |
405 | struct ath_hw *ah = sc->sc_ah; | |
406 | struct ath_common *common = ath9k_hw_common(ah); | |
407 | u32 mci_int, mci_int_rxmsg; | |
408 | u32 offset, subtype, opcode; | |
409 | u32 *pgpm; | |
410 | u32 more_data = MCI_GPM_MORE; | |
411 | bool skip_gpm = false; | |
412 | ||
413 | ar9003_mci_get_interrupt(sc->sc_ah, &mci_int, &mci_int_rxmsg); | |
414 | ||
415 | if (ar9003_mci_state(ah, MCI_STATE_ENABLE, NULL) == 0) { | |
682dd04b | 416 | ar9003_mci_state(ah, MCI_STATE_INIT_GPM_OFFSET, NULL); |
19686ddf MSS |
417 | return; |
418 | } | |
419 | ||
420 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) { | |
421 | u32 payload[4] = { 0xffffffff, 0xffffffff, | |
422 | 0xffffffff, 0xffffff00}; | |
423 | ||
424 | /* | |
425 | * The following REMOTE_RESET and SYS_WAKING used to sent | |
426 | * only when BT wake up. Now they are always sent, as a | |
427 | * recovery method to reset BT MCI's RX alignment. | |
428 | */ | |
19686ddf MSS |
429 | ar9003_mci_send_message(ah, MCI_REMOTE_RESET, 0, |
430 | payload, 16, true, false); | |
19686ddf MSS |
431 | ar9003_mci_send_message(ah, MCI_SYS_WAKING, 0, |
432 | NULL, 0, true, false); | |
433 | ||
434 | mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE; | |
435 | ar9003_mci_state(ah, MCI_STATE_RESET_REQ_WAKE, NULL); | |
436 | ||
437 | /* | |
438 | * always do this for recovery and 2G/5G toggling and LNA_TRANS | |
439 | */ | |
19686ddf MSS |
440 | ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE, NULL); |
441 | } | |
442 | ||
19686ddf MSS |
443 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING) { |
444 | mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING; | |
445 | ||
446 | if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_SLEEP) { | |
682dd04b SM |
447 | if (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL) != |
448 | MCI_BT_SLEEP) | |
449 | ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE, | |
450 | NULL); | |
451 | } | |
19686ddf MSS |
452 | } |
453 | ||
454 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) { | |
19686ddf MSS |
455 | mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING; |
456 | ||
457 | if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_AWAKE) { | |
682dd04b SM |
458 | if (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL) != |
459 | MCI_BT_AWAKE) | |
19686ddf MSS |
460 | ar9003_mci_state(ah, MCI_STATE_SET_BT_SLEEP, |
461 | NULL); | |
682dd04b | 462 | } |
19686ddf MSS |
463 | } |
464 | ||
465 | if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) || | |
466 | (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) { | |
19686ddf MSS |
467 | ar9003_mci_state(ah, MCI_STATE_RECOVER_RX, NULL); |
468 | skip_gpm = true; | |
469 | } | |
470 | ||
471 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO) { | |
19686ddf MSS |
472 | mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO; |
473 | offset = ar9003_mci_state(ah, MCI_STATE_LAST_SCHD_MSG_OFFSET, | |
474 | NULL); | |
475 | } | |
476 | ||
477 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_GPM) { | |
19686ddf MSS |
478 | mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_GPM; |
479 | ||
480 | while (more_data == MCI_GPM_MORE) { | |
481 | ||
482 | pgpm = mci->gpm_buf.bf_addr; | |
682dd04b SM |
483 | offset = ar9003_mci_state(ah, MCI_STATE_NEXT_GPM_OFFSET, |
484 | &more_data); | |
19686ddf MSS |
485 | |
486 | if (offset == MCI_GPM_INVALID) | |
487 | break; | |
488 | ||
489 | pgpm += (offset >> 2); | |
490 | ||
491 | /* | |
492 | * The first dword is timer. | |
493 | * The real data starts from 2nd dword. | |
494 | */ | |
19686ddf MSS |
495 | subtype = MCI_GPM_TYPE(pgpm); |
496 | opcode = MCI_GPM_OPCODE(pgpm); | |
497 | ||
682dd04b SM |
498 | if (skip_gpm) |
499 | goto recycle; | |
500 | ||
501 | if (MCI_GPM_IS_CAL_TYPE(subtype)) { | |
502 | ath_mci_cal_msg(sc, subtype, (u8 *)pgpm); | |
503 | } else { | |
504 | switch (subtype) { | |
505 | case MCI_GPM_COEX_AGENT: | |
506 | ath_mci_msg(sc, opcode, (u8 *)pgpm); | |
507 | break; | |
508 | default: | |
509 | break; | |
19686ddf MSS |
510 | } |
511 | } | |
682dd04b | 512 | recycle: |
19686ddf MSS |
513 | MCI_GPM_RECYCLE(pgpm); |
514 | } | |
515 | } | |
516 | ||
517 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_HW_MSG_MASK) { | |
19686ddf MSS |
518 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL) |
519 | mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL; | |
520 | ||
682dd04b | 521 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_INFO) |
19686ddf | 522 | mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_INFO; |
19686ddf MSS |
523 | |
524 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO) { | |
19686ddf | 525 | int value_dbm = ar9003_mci_state(ah, |
682dd04b | 526 | MCI_STATE_CONT_RSSI_POWER, NULL); |
19686ddf MSS |
527 | |
528 | mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_INFO; | |
529 | ||
530 | if (ar9003_mci_state(ah, MCI_STATE_CONT_TXRX, NULL)) | |
d2182b69 JP |
531 | ath_dbg(common, MCI, |
532 | "MCI CONT_INFO: (tx) pri = %d, pwr = %d dBm\n", | |
19686ddf | 533 | ar9003_mci_state(ah, |
682dd04b | 534 | MCI_STATE_CONT_PRIORITY, NULL), |
19686ddf MSS |
535 | value_dbm); |
536 | else | |
d2182b69 JP |
537 | ath_dbg(common, MCI, |
538 | "MCI CONT_INFO: (rx) pri = %d,pwr = %d dBm\n", | |
19686ddf | 539 | ar9003_mci_state(ah, |
682dd04b | 540 | MCI_STATE_CONT_PRIORITY, NULL), |
19686ddf MSS |
541 | value_dbm); |
542 | } | |
543 | ||
682dd04b | 544 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_NACK) |
19686ddf | 545 | mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_NACK; |
19686ddf | 546 | |
682dd04b | 547 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_RST) |
19686ddf | 548 | mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_RST; |
19686ddf MSS |
549 | } |
550 | ||
551 | if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) || | |
552 | (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) | |
553 | mci_int &= ~(AR_MCI_INTERRUPT_RX_INVALID_HDR | | |
554 | AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT); | |
19686ddf | 555 | } |
e270e776 SM |
556 | |
557 | void ath_mci_enable(struct ath_softc *sc) | |
558 | { | |
559 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
560 | ||
561 | if (!common->btcoex_enabled) | |
562 | return; | |
563 | ||
564 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI) | |
565 | sc->sc_ah->imask |= ATH9K_INT_MCI; | |
566 | } |