[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / pci.c

/*
 * Copyright (c) 2008-2009 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/nl80211.h>
#include <linux/pci.h>
#include "ath9k.h"

static struct pci_device_id ath_pci_id_table[] __devinitdata = {
	{ PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI   */
	{ PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
	{ PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI   */
	{ PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI   */
	{ PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
	{ PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
	{ PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI   */
	{ PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
	{ 0 }
};

/* return bus cachesize in 4B word units */
static void ath_pci_read_cachesize(struct ath_softc *sc, int *csz)
{
	u8 u8tmp;

	pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE,
			     (u8 *)&u8tmp);
	*csz = (int)u8tmp;

	/*
	 * This check was put in to avoid "unplesant" consequences if
	 * the bootrom has not fully initialized all PCI devices.
	 * Sometimes the cache line size register is not set
	 */

	if (*csz == 0)
		*csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
}

static void ath_pci_cleanup(struct ath_softc *sc)
{
	struct pci_dev *pdev = to_pci_dev(sc->dev);

	pci_iounmap(pdev, sc->mem);
	pci_disable_device(pdev);
	pci_release_region(pdev, 0);
}

static bool ath_pci_eeprom_read(struct ath_hw *ah, u32 off, u16 *data)
{
	(void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));

	if (!ath9k_hw_wait(ah,
			   AR_EEPROM_STATUS_DATA,
			   AR_EEPROM_STATUS_DATA_BUSY |
			   AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
			   AH_WAIT_TIMEOUT)) {
		return false;
	}

	*data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
		   AR_EEPROM_STATUS_DATA_VAL);

	return true;
}

static struct ath_bus_ops ath_pci_bus_ops = {
	.read_cachesize = ath_pci_read_cachesize,
	.cleanup = ath_pci_cleanup,
	.eeprom_read = ath_pci_eeprom_read,
};

static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
	void __iomem *mem;
	struct ath_wiphy *aphy;
	struct ath_softc *sc;
	struct ieee80211_hw *hw;
	u8 csz;
	u32 val;
	int ret = 0;
	struct ath_hw *ah;

	if (pci_enable_device(pdev))
		return -EIO;

	ret =  pci_set_dma_mask(pdev, DMA_BIT_MASK(32));

	if (ret) {
		printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
		goto bad;
	}

	ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));

	if (ret) {
		printk(KERN_ERR "ath9k: 32-bit DMA consistent "
			"DMA enable failed\n");
		goto bad;
	}

	/*
	 * Cache line size is used to size and align various
	 * structures used to communicate with the hardware.
	 */
	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
	if (csz == 0) {
		/*
		 * Linux 2.4.18 (at least) writes the cache line size
		 * register as a 16-bit wide register which is wrong.
		 * We must have this setup properly for rx buffer
		 * DMA to work so force a reasonable value here if it
		 * comes up zero.
		 */
		csz = L1_CACHE_BYTES / sizeof(u32);
		pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
	}
	/*
	 * The default setting of latency timer yields poor results,
	 * set it to the value used by other systems. It may be worth
	 * tweaking this setting more.
	 */
	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);

	pci_set_master(pdev);

	/*
	 * Disable the RETRY_TIMEOUT register (0x41) to keep
	 * PCI Tx retries from interfering with C3 CPU state.
	 */
	pci_read_config_dword(pdev, 0x40, &val);
	if ((val & 0x0000ff00) != 0)
		pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);

	ret = pci_request_region(pdev, 0, "ath9k");
	if (ret) {
		dev_err(&pdev->dev, "PCI memory region reserve error\n");
		ret = -ENODEV;
		goto bad;
	}

	mem = pci_iomap(pdev, 0, 0);
	if (!mem) {
		printk(KERN_ERR "PCI memory map error\n") ;
		ret = -EIO;
		goto bad1;
	}

	hw = ieee80211_alloc_hw(sizeof(struct ath_wiphy) +
				sizeof(struct ath_softc), &ath9k_ops);
	if (hw == NULL) {
		printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
		goto bad2;
	}

	SET_IEEE80211_DEV(hw, &pdev->dev);
	pci_set_drvdata(pdev, hw);

	aphy = hw->priv;
	sc = (struct ath_softc *) (aphy + 1);
	aphy->sc = sc;
	aphy->hw = hw;
	sc->pri_wiphy = aphy;
	sc->hw = hw;
	sc->dev = &pdev->dev;
	sc->mem = mem;
	sc->bus_ops = &ath_pci_bus_ops;

	if (ath_init_device(id->device, sc) != 0) {
		ret = -ENODEV;
		goto bad3;
	}

	/* setup interrupt service routine */

	if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
		printk(KERN_ERR "%s: request_irq failed\n",
			wiphy_name(hw->wiphy));
		ret = -EIO;
		goto bad4;
	}

	sc->irq = pdev->irq;

	ah = sc->sc_ah;
	printk(KERN_INFO
	       "%s: Atheros AR%s MAC/BB Rev:%x "
	       "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
	       wiphy_name(hw->wiphy),
	       ath_mac_bb_name(ah->hw_version.macVersion),
	       ah->hw_version.macRev,
	       ath_rf_name((ah->hw_version.analog5GhzRev & AR_RADIO_SREV_MAJOR)),
	       ah->hw_version.phyRev,
	       (unsigned long)mem, pdev->irq);

	return 0;
bad4:
	ath_detach(sc);
bad3:
	ieee80211_free_hw(hw);
bad2:
	pci_iounmap(pdev, mem);
bad1:
	pci_release_region(pdev, 0);
bad:
	pci_disable_device(pdev);
	return ret;
}

static void ath_pci_remove(struct pci_dev *pdev)
{
	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;

	ath_cleanup(sc);
}

#ifdef CONFIG_PM

static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
{
	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;

	ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);

	pci_save_state(pdev);
	pci_disable_device(pdev);
	pci_set_power_state(pdev, PCI_D3hot);

	return 0;
}

static int ath_pci_resume(struct pci_dev *pdev)
{
	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
	u32 val;
	int err;

	pci_restore_state(pdev);

	err = pci_enable_device(pdev);
	if (err)
		return err;

	/*
	 * Suspend/Resume resets the PCI configuration space, so we have to
	 * re-disable the RETRY_TIMEOUT register (0x41) to keep
	 * PCI Tx retries from interfering with C3 CPU state
	 */
	pci_read_config_dword(pdev, 0x40, &val);
	if ((val & 0x0000ff00) != 0)
		pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);

	/* Enable LED */
	ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
			    AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
	ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);

	return 0;
}

#endif /* CONFIG_PM */

MODULE_DEVICE_TABLE(pci, ath_pci_id_table);

static struct pci_driver ath_pci_driver = {
	.name       = "ath9k",
	.id_table   = ath_pci_id_table,
	.probe      = ath_pci_probe,
	.remove     = ath_pci_remove,
#ifdef CONFIG_PM
	.suspend    = ath_pci_suspend,
	.resume     = ath_pci_resume,
#endif /* CONFIG_PM */
};

int ath_pci_init(void)
{
	return pci_register_driver(&ath_pci_driver);
}

void ath_pci_exit(void)
{
	pci_unregister_driver(&ath_pci_driver);
}
Commit	Line	Data
6baff7f9	1	/*
cee075a2	2	* Copyright (c) 2008-2009 Atheros Communications Inc.
6baff7f9 GJ	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#include <linux/nl80211.h>
	18	#include <linux/pci.h>
394cf0a1	19	#include "ath9k.h"
6baff7f9 GJ	20
	21	static struct pci_device_id ath_pci_id_table[] __devinitdata = {
	22	{ PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
	23	{ PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
	24	{ PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
	25	{ PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
	26	{ PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
	27	{ PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
ac88b6ec VN	28	{ PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */
ac88b6ec VN	29	{ PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
6baff7f9 GJ	30	{ 0 }
	31	};
	32
	33	/* return bus cachesize in 4B word units */
	34	static void ath_pci_read_cachesize(struct ath_softc sc, int csz)
	35	{
	36	u8 u8tmp;
	37
	38	pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE,
	39	(u8 *)&u8tmp);
	40	*csz = (int)u8tmp;
	41
	42	/*
	43	* This check was put in to avoid "unplesant" consequences if
	44	* the bootrom has not fully initialized all PCI devices.
	45	* Sometimes the cache line size register is not set
	46	*/
	47
	48	if (*csz == 0)
	49	csz = DEFAULT_CACHELINE >> 2; / Use the default size */
	50	}
	51
	52	static void ath_pci_cleanup(struct ath_softc *sc)
	53	{
	54	struct pci_dev *pdev = to_pci_dev(sc->dev);
	55
	56	pci_iounmap(pdev, sc->mem);
6baff7f9	57	pci_disable_device(pdev);
db0f41f5	58	pci_release_region(pdev, 0);
6baff7f9 GJ	59	}
6baff7f9 GJ	60
cbe61d8a	61	static bool ath_pci_eeprom_read(struct ath_hw ah, u32 off, u16 data)
9dbeb91a GJ	62	{
	63	(void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
	64
	65	if (!ath9k_hw_wait(ah,
	66	AR_EEPROM_STATUS_DATA,
	67	AR_EEPROM_STATUS_DATA_BUSY \|
0caa7b14 S	68	AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
0caa7b14 S	69	AH_WAIT_TIMEOUT)) {
9dbeb91a GJ	70	return false;
	71	}
	72
	73	*data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
	74	AR_EEPROM_STATUS_DATA_VAL);
	75
	76	return true;
	77	}
	78
6baff7f9 GJ	79	static struct ath_bus_ops ath_pci_bus_ops = {
	80	.read_cachesize = ath_pci_read_cachesize,
	81	.cleanup = ath_pci_cleanup,
9dbeb91a	82	.eeprom_read = ath_pci_eeprom_read,
6baff7f9 GJ	83	};
	84
	85	static int ath_pci_probe(struct pci_dev pdev, const struct pci_device_id id)
	86	{
	87	void __iomem *mem;
bce048d7	88	struct ath_wiphy *aphy;
6baff7f9 GJ	89	struct ath_softc *sc;
	90	struct ieee80211_hw *hw;
	91	u8 csz;
f0214843	92	u32 val;
6baff7f9	93	int ret = 0;
cbe61d8a	94	struct ath_hw *ah;
6baff7f9 GJ	95
	96	if (pci_enable_device(pdev))
	97	return -EIO;
	98
e930438c	99	ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6baff7f9 GJ	100
	101	if (ret) {
	102	printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
	103	goto bad;
	104	}
	105
e930438c	106	ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
6baff7f9 GJ	107
	108	if (ret) {
	109	printk(KERN_ERR "ath9k: 32-bit DMA consistent "
	110	"DMA enable failed\n");
	111	goto bad;
	112	}
	113
	114	/*
	115	* Cache line size is used to size and align various
	116	* structures used to communicate with the hardware.
	117	*/
	118	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
	119	if (csz == 0) {
	120	/*
	121	* Linux 2.4.18 (at least) writes the cache line size
	122	* register as a 16-bit wide register which is wrong.
	123	* We must have this setup properly for rx buffer
	124	* DMA to work so force a reasonable value here if it
	125	* comes up zero.
	126	*/
	127	csz = L1_CACHE_BYTES / sizeof(u32);
	128	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
	129	}
	130	/*
	131	* The default setting of latency timer yields poor results,
	132	* set it to the value used by other systems. It may be worth
	133	* tweaking this setting more.
	134	*/
	135	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
	136
	137	pci_set_master(pdev);
	138
f0214843 JM	139	/*
	140	* Disable the RETRY_TIMEOUT register (0x41) to keep
	141	* PCI Tx retries from interfering with C3 CPU state.
	142	*/
	143	pci_read_config_dword(pdev, 0x40, &val);
	144	if ((val & 0x0000ff00) != 0)
	145	pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
	146
6baff7f9 GJ	147	ret = pci_request_region(pdev, 0, "ath9k");
	148	if (ret) {
	149	dev_err(&pdev->dev, "PCI memory region reserve error\n");
	150	ret = -ENODEV;
	151	goto bad;
	152	}
	153
	154	mem = pci_iomap(pdev, 0, 0);
	155	if (!mem) {
	156	printk(KERN_ERR "PCI memory map error\n") ;
	157	ret = -EIO;
	158	goto bad1;
	159	}
	160
bce048d7 JM	161	hw = ieee80211_alloc_hw(sizeof(struct ath_wiphy) +
bce048d7 JM	162	sizeof(struct ath_softc), &ath9k_ops);
6baff7f9 GJ	163	if (hw == NULL) {
	164	printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
	165	goto bad2;
	166	}
	167
	168	SET_IEEE80211_DEV(hw, &pdev->dev);
	169	pci_set_drvdata(pdev, hw);
	170
bce048d7 JM	171	aphy = hw->priv;
	172	sc = (struct ath_softc *) (aphy + 1);
	173	aphy->sc = sc;
	174	aphy->hw = hw;
	175	sc->pri_wiphy = aphy;
6baff7f9 GJ	176	sc->hw = hw;
	177	sc->dev = &pdev->dev;
	178	sc->mem = mem;
	179	sc->bus_ops = &ath_pci_bus_ops;
	180
1e40bcfa	181	if (ath_init_device(id->device, sc) != 0) {
6baff7f9 GJ	182	ret = -ENODEV;
	183	goto bad3;
	184	}
	185
	186	/* setup interrupt service routine */
	187
	188	if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
	189	printk(KERN_ERR "%s: request_irq failed\n",
	190	wiphy_name(hw->wiphy));
	191	ret = -EIO;
	192	goto bad4;
	193	}
	194
	195	sc->irq = pdev->irq;
	196
	197	ah = sc->sc_ah;
	198	printk(KERN_INFO
	199	"%s: Atheros AR%s MAC/BB Rev:%x "
	200	"AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
	201	wiphy_name(hw->wiphy),
d535a42a S	202	ath_mac_bb_name(ah->hw_version.macVersion),
	203	ah->hw_version.macRev,
	204	ath_rf_name((ah->hw_version.analog5GhzRev & AR_RADIO_SREV_MAJOR)),
	205	ah->hw_version.phyRev,
6baff7f9 GJ	206	(unsigned long)mem, pdev->irq);
	207
	208	return 0;
	209	bad4:
	210	ath_detach(sc);
	211	bad3:
	212	ieee80211_free_hw(hw);
	213	bad2:
	214	pci_iounmap(pdev, mem);
	215	bad1:
	216	pci_release_region(pdev, 0);
	217	bad:
	218	pci_disable_device(pdev);
	219	return ret;
	220	}
	221
	222	static void ath_pci_remove(struct pci_dev *pdev)
	223	{
	224	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
bce048d7 JM	225	struct ath_wiphy *aphy = hw->priv;
bce048d7 JM	226	struct ath_softc *sc = aphy->sc;
6baff7f9 GJ	227
	228	ath_cleanup(sc);
	229	}
	230
	231	#ifdef CONFIG_PM
	232
	233	static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
	234	{
	235	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
bce048d7 JM	236	struct ath_wiphy *aphy = hw->priv;
bce048d7 JM	237	struct ath_softc *sc = aphy->sc;
6baff7f9	238
08fc5c1b	239	ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
6baff7f9	240
6baff7f9 GJ	241	pci_save_state(pdev);
	242	pci_disable_device(pdev);
	243	pci_set_power_state(pdev, PCI_D3hot);
	244
	245	return 0;
	246	}
	247
	248	static int ath_pci_resume(struct pci_dev *pdev)
	249	{
	250	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
bce048d7 JM	251	struct ath_wiphy *aphy = hw->priv;
bce048d7 JM	252	struct ath_softc *sc = aphy->sc;
f0214843	253	u32 val;
6baff7f9 GJ	254	int err;
6baff7f9 GJ	255
523c36fc S	256	pci_restore_state(pdev);
523c36fc S	257
6baff7f9 GJ	258	err = pci_enable_device(pdev);
	259	if (err)
	260	return err;
523c36fc	261
f0214843 JM	262	/*
	263	* Suspend/Resume resets the PCI configuration space, so we have to
	264	* re-disable the RETRY_TIMEOUT register (0x41) to keep
	265	* PCI Tx retries from interfering with C3 CPU state
	266	*/
	267	pci_read_config_dword(pdev, 0x40, &val);
	268	if ((val & 0x0000ff00) != 0)
	269	pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
6baff7f9 GJ	270
6baff7f9 GJ	271	/* Enable LED */
08fc5c1b	272	ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
6baff7f9	273	AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b	274	ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
6baff7f9	275
6baff7f9 GJ	276	return 0;
	277	}
	278
	279	#endif /* CONFIG_PM */
	280
	281	MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
	282
	283	static struct pci_driver ath_pci_driver = {
	284	.name = "ath9k",
	285	.id_table = ath_pci_id_table,
	286	.probe = ath_pci_probe,
	287	.remove = ath_pci_remove,
	288	#ifdef CONFIG_PM
	289	.suspend = ath_pci_suspend,
	290	.resume = ath_pci_resume,
	291	#endif /* CONFIG_PM */
	292	};
	293
db0f41f5	294	int ath_pci_init(void)
6baff7f9 GJ	295	{
	296	return pci_register_driver(&ath_pci_driver);
	297	}
	298
	299	void ath_pci_exit(void)
	300	{
	301	pci_unregister_driver(&ath_pci_driver);
	302	}