Commit | Line | Data |
---|---|---|
6baff7f9 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
6baff7f9 GJ |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
516304b0 JP |
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
18 | ||
6baff7f9 GJ |
19 | #include <linux/nl80211.h> |
20 | #include <linux/pci.h> | |
d4930086 | 21 | #include <linux/pci-aspm.h> |
a05b5d45 | 22 | #include <linux/ath9k_platform.h> |
9d9779e7 | 23 | #include <linux/module.h> |
394cf0a1 | 24 | #include "ath9k.h" |
6baff7f9 | 25 | |
a3aa1884 | 26 | static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = { |
6baff7f9 GJ |
27 | { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */ |
28 | { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */ | |
29 | { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */ | |
30 | { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */ | |
31 | { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */ | |
32 | { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */ | |
5ffaf8a3 | 33 | { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */ |
ac88b6ec VN |
34 | { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */ |
35 | { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */ | |
0efabd51 | 36 | { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */ |
9b60b64b SM |
37 | |
38 | /* PCI-E CUS198 */ | |
39 | { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, | |
40 | 0x0032, | |
41 | PCI_VENDOR_ID_AZWAVE, | |
42 | 0x2086), | |
43 | .driver_data = ATH9K_PCI_CUS198 }, | |
44 | { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, | |
45 | 0x0032, | |
46 | PCI_VENDOR_ID_AZWAVE, | |
47 | 0x1237), | |
48 | .driver_data = ATH9K_PCI_CUS198 }, | |
49 | { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, | |
50 | 0x0032, | |
51 | PCI_VENDOR_ID_AZWAVE, | |
52 | 0x2126), | |
53 | .driver_data = ATH9K_PCI_CUS198 }, | |
e861ef52 SM |
54 | |
55 | /* PCI-E CUS230 */ | |
9b60b64b SM |
56 | { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, |
57 | 0x0032, | |
58 | PCI_VENDOR_ID_AZWAVE, | |
59 | 0x2152), | |
e861ef52 | 60 | .driver_data = ATH9K_PCI_CUS230 }, |
9b60b64b SM |
61 | { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, |
62 | 0x0032, | |
63 | PCI_VENDOR_ID_FOXCONN, | |
64 | 0xE075), | |
e861ef52 | 65 | .driver_data = ATH9K_PCI_CUS230 }, |
9b60b64b | 66 | |
1435894d | 67 | { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */ |
a508a6ea | 68 | { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */ |
12eea640 SM |
69 | |
70 | /* PCI-E CUS217 */ | |
71 | { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, | |
72 | 0x0034, | |
73 | PCI_VENDOR_ID_AZWAVE, | |
74 | 0x2116), | |
75 | .driver_data = ATH9K_PCI_CUS217 }, | |
76 | { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, | |
77 | 0x0034, | |
78 | 0x11AD, /* LITEON */ | |
79 | 0x6661), | |
80 | .driver_data = ATH9K_PCI_CUS217 }, | |
81 | ||
423e38e8 | 82 | { PCI_VDEVICE(ATHEROS, 0x0034) }, /* PCI-E AR9462 */ |
d4e5979c | 83 | { PCI_VDEVICE(ATHEROS, 0x0037) }, /* PCI-E AR1111/AR9485 */ |
0c8070f9 | 84 | { PCI_VDEVICE(ATHEROS, 0x0036) }, /* PCI-E AR9565 */ |
6baff7f9 GJ |
85 | { 0 } |
86 | }; | |
87 | ||
84c87dc8 | 88 | |
6baff7f9 | 89 | /* return bus cachesize in 4B word units */ |
5bb12791 | 90 | static void ath_pci_read_cachesize(struct ath_common *common, int *csz) |
6baff7f9 | 91 | { |
bc974f4a | 92 | struct ath_softc *sc = (struct ath_softc *) common->priv; |
6baff7f9 GJ |
93 | u8 u8tmp; |
94 | ||
f020979d | 95 | pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp); |
6baff7f9 GJ |
96 | *csz = (int)u8tmp; |
97 | ||
98 | /* | |
25985edc | 99 | * This check was put in to avoid "unpleasant" consequences if |
6baff7f9 GJ |
100 | * the bootrom has not fully initialized all PCI devices. |
101 | * Sometimes the cache line size register is not set | |
102 | */ | |
103 | ||
104 | if (*csz == 0) | |
105 | *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */ | |
106 | } | |
107 | ||
5bb12791 | 108 | static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data) |
9dbeb91a | 109 | { |
a05b5d45 FF |
110 | struct ath_softc *sc = (struct ath_softc *) common->priv; |
111 | struct ath9k_platform_data *pdata = sc->dev->platform_data; | |
112 | ||
113 | if (pdata) { | |
114 | if (off >= (ARRAY_SIZE(pdata->eeprom_data))) { | |
3800276a JP |
115 | ath_err(common, |
116 | "%s: eeprom read failed, offset %08x is out of range\n", | |
117 | __func__, off); | |
a05b5d45 FF |
118 | } |
119 | ||
120 | *data = pdata->eeprom_data[off]; | |
121 | } else { | |
122 | struct ath_hw *ah = (struct ath_hw *) common->ah; | |
123 | ||
124 | common->ops->read(ah, AR5416_EEPROM_OFFSET + | |
125 | (off << AR5416_EEPROM_S)); | |
126 | ||
127 | if (!ath9k_hw_wait(ah, | |
128 | AR_EEPROM_STATUS_DATA, | |
129 | AR_EEPROM_STATUS_DATA_BUSY | | |
130 | AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0, | |
131 | AH_WAIT_TIMEOUT)) { | |
132 | return false; | |
133 | } | |
134 | ||
135 | *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA), | |
136 | AR_EEPROM_STATUS_DATA_VAL); | |
9dbeb91a GJ |
137 | } |
138 | ||
9dbeb91a GJ |
139 | return true; |
140 | } | |
141 | ||
69ce674b | 142 | /* Need to be called after we discover btcoex capabilities */ |
d4930086 SG |
143 | static void ath_pci_aspm_init(struct ath_common *common) |
144 | { | |
145 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
146 | struct ath_hw *ah = sc->sc_ah; | |
147 | struct pci_dev *pdev = to_pci_dev(sc->dev); | |
148 | struct pci_dev *parent; | |
08bd1080 | 149 | u16 aspm; |
d4930086 | 150 | |
d09f5f4c SM |
151 | if (!ah->is_pciexpress) |
152 | return; | |
153 | ||
d4930086 | 154 | parent = pdev->bus->self; |
22c55e6e JL |
155 | if (!parent) |
156 | return; | |
69ce674b | 157 | |
046b6802 SM |
158 | if ((ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) && |
159 | (AR_SREV_9285(ah))) { | |
a875621e | 160 | /* Bluetooth coexistence requires disabling ASPM. */ |
08bd1080 | 161 | pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, |
a875621e | 162 | PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1); |
69ce674b SG |
163 | |
164 | /* | |
165 | * Both upstream and downstream PCIe components should | |
166 | * have the same ASPM settings. | |
167 | */ | |
08bd1080 | 168 | pcie_capability_clear_word(parent, PCI_EXP_LNKCTL, |
a875621e | 169 | PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1); |
69ce674b | 170 | |
d09f5f4c | 171 | ath_info(common, "Disabling ASPM since BTCOEX is enabled\n"); |
69ce674b SG |
172 | return; |
173 | } | |
174 | ||
08bd1080 | 175 | pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm); |
a875621e | 176 | if (aspm & (PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1)) { |
d4930086 SG |
177 | ah->aspm_enabled = true; |
178 | /* Initialize PCIe PM and SERDES registers. */ | |
84c87dc8 | 179 | ath9k_hw_configpcipowersave(ah, false); |
d09f5f4c | 180 | ath_info(common, "ASPM enabled: 0x%x\n", aspm); |
d4930086 SG |
181 | } |
182 | } | |
183 | ||
83bd11a0 | 184 | static const struct ath_bus_ops ath_pci_bus_ops = { |
497ad9ad | 185 | .ath_bus_type = ATH_PCI, |
6baff7f9 | 186 | .read_cachesize = ath_pci_read_cachesize, |
9dbeb91a | 187 | .eeprom_read = ath_pci_eeprom_read, |
d4930086 | 188 | .aspm_init = ath_pci_aspm_init, |
6baff7f9 GJ |
189 | }; |
190 | ||
191 | static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |
192 | { | |
6baff7f9 GJ |
193 | struct ath_softc *sc; |
194 | struct ieee80211_hw *hw; | |
195 | u8 csz; | |
f0214843 | 196 | u32 val; |
6baff7f9 | 197 | int ret = 0; |
f934c4d9 | 198 | char hw_name[64]; |
6baff7f9 | 199 | |
b81950b1 | 200 | if (pcim_enable_device(pdev)) |
6baff7f9 GJ |
201 | return -EIO; |
202 | ||
e930438c | 203 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
6baff7f9 | 204 | if (ret) { |
516304b0 | 205 | pr_err("32-bit DMA not available\n"); |
b81950b1 | 206 | return ret; |
6baff7f9 GJ |
207 | } |
208 | ||
e930438c | 209 | ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
6baff7f9 | 210 | if (ret) { |
516304b0 | 211 | pr_err("32-bit DMA consistent DMA enable failed\n"); |
b81950b1 | 212 | return ret; |
6baff7f9 GJ |
213 | } |
214 | ||
215 | /* | |
216 | * Cache line size is used to size and align various | |
217 | * structures used to communicate with the hardware. | |
218 | */ | |
219 | pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); | |
220 | if (csz == 0) { | |
221 | /* | |
222 | * Linux 2.4.18 (at least) writes the cache line size | |
223 | * register as a 16-bit wide register which is wrong. | |
224 | * We must have this setup properly for rx buffer | |
225 | * DMA to work so force a reasonable value here if it | |
226 | * comes up zero. | |
227 | */ | |
228 | csz = L1_CACHE_BYTES / sizeof(u32); | |
229 | pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); | |
230 | } | |
231 | /* | |
232 | * The default setting of latency timer yields poor results, | |
233 | * set it to the value used by other systems. It may be worth | |
234 | * tweaking this setting more. | |
235 | */ | |
236 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); | |
237 | ||
238 | pci_set_master(pdev); | |
239 | ||
f0214843 JM |
240 | /* |
241 | * Disable the RETRY_TIMEOUT register (0x41) to keep | |
242 | * PCI Tx retries from interfering with C3 CPU state. | |
243 | */ | |
244 | pci_read_config_dword(pdev, 0x40, &val); | |
245 | if ((val & 0x0000ff00) != 0) | |
246 | pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); | |
247 | ||
b81950b1 | 248 | ret = pcim_iomap_regions(pdev, BIT(0), "ath9k"); |
6baff7f9 GJ |
249 | if (ret) { |
250 | dev_err(&pdev->dev, "PCI memory region reserve error\n"); | |
b81950b1 | 251 | return -ENODEV; |
6baff7f9 GJ |
252 | } |
253 | ||
9ac58615 | 254 | hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops); |
db6be53c | 255 | if (!hw) { |
285f2dda | 256 | dev_err(&pdev->dev, "No memory for ieee80211_hw\n"); |
b81950b1 | 257 | return -ENOMEM; |
6baff7f9 GJ |
258 | } |
259 | ||
260 | SET_IEEE80211_DEV(hw, &pdev->dev); | |
261 | pci_set_drvdata(pdev, hw); | |
262 | ||
9ac58615 | 263 | sc = hw->priv; |
6baff7f9 GJ |
264 | sc->hw = hw; |
265 | sc->dev = &pdev->dev; | |
b81950b1 | 266 | sc->mem = pcim_iomap_table(pdev)[0]; |
9b60b64b | 267 | sc->driver_data = id->driver_data; |
6baff7f9 | 268 | |
5e4ea1f0 | 269 | /* Will be cleared in ath9k_start() */ |
781b14a3 | 270 | set_bit(SC_OP_INVALID, &sc->sc_flags); |
6baff7f9 | 271 | |
fc548af8 | 272 | ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc); |
580171f7 LR |
273 | if (ret) { |
274 | dev_err(&pdev->dev, "request_irq failed\n"); | |
285f2dda | 275 | goto err_irq; |
6baff7f9 GJ |
276 | } |
277 | ||
278 | sc->irq = pdev->irq; | |
279 | ||
eb93e891 | 280 | ret = ath9k_init_device(id->device, sc, &ath_pci_bus_ops); |
285f2dda S |
281 | if (ret) { |
282 | dev_err(&pdev->dev, "Failed to initialize device\n"); | |
283 | goto err_init; | |
284 | } | |
285 | ||
286 | ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name)); | |
c96c31e4 | 287 | wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n", |
b81950b1 | 288 | hw_name, (unsigned long)sc->mem, pdev->irq); |
6baff7f9 GJ |
289 | |
290 | return 0; | |
285f2dda S |
291 | |
292 | err_init: | |
293 | free_irq(sc->irq, sc); | |
294 | err_irq: | |
6baff7f9 | 295 | ieee80211_free_hw(hw); |
6baff7f9 GJ |
296 | return ret; |
297 | } | |
298 | ||
299 | static void ath_pci_remove(struct pci_dev *pdev) | |
300 | { | |
301 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); | |
9ac58615 | 302 | struct ath_softc *sc = hw->priv; |
6baff7f9 | 303 | |
d584747b RM |
304 | if (!is_ath9k_unloaded) |
305 | sc->sc_ah->ah_flags |= AH_UNPLUGGED; | |
285f2dda S |
306 | ath9k_deinit_device(sc); |
307 | free_irq(sc->irq, sc); | |
308 | ieee80211_free_hw(sc->hw); | |
6baff7f9 GJ |
309 | } |
310 | ||
88427588 | 311 | #ifdef CONFIG_PM_SLEEP |
6baff7f9 | 312 | |
f0e94b47 | 313 | static int ath_pci_suspend(struct device *device) |
6baff7f9 | 314 | { |
f0e94b47 | 315 | struct pci_dev *pdev = to_pci_dev(device); |
6baff7f9 | 316 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); |
9ac58615 | 317 | struct ath_softc *sc = hw->priv; |
6baff7f9 | 318 | |
4a17a50d MSS |
319 | if (sc->wow_enabled) |
320 | return 0; | |
321 | ||
c31eb8e9 RM |
322 | /* The device has to be moved to FULLSLEEP forcibly. |
323 | * Otherwise the chip never moved to full sleep, | |
324 | * when no interface is up. | |
325 | */ | |
e19f15ac | 326 | ath9k_stop_btcoex(sc); |
c0c11741 | 327 | ath9k_hw_disable(sc->sc_ah); |
c31eb8e9 RM |
328 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); |
329 | ||
6baff7f9 GJ |
330 | return 0; |
331 | } | |
332 | ||
f0e94b47 | 333 | static int ath_pci_resume(struct device *device) |
6baff7f9 | 334 | { |
f0e94b47 | 335 | struct pci_dev *pdev = to_pci_dev(device); |
93170516 FF |
336 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); |
337 | struct ath_softc *sc = hw->priv; | |
ceb26a60 FF |
338 | struct ath_hw *ah = sc->sc_ah; |
339 | struct ath_common *common = ath9k_hw_common(ah); | |
f0214843 | 340 | u32 val; |
523c36fc | 341 | |
f0214843 JM |
342 | /* |
343 | * Suspend/Resume resets the PCI configuration space, so we have to | |
344 | * re-disable the RETRY_TIMEOUT register (0x41) to keep | |
345 | * PCI Tx retries from interfering with C3 CPU state | |
346 | */ | |
347 | pci_read_config_dword(pdev, 0x40, &val); | |
348 | if ((val & 0x0000ff00) != 0) | |
349 | pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); | |
6baff7f9 | 350 | |
93170516 | 351 | ath_pci_aspm_init(common); |
ceb26a60 | 352 | ah->reset_power_on = false; |
93170516 | 353 | |
6baff7f9 GJ |
354 | return 0; |
355 | } | |
356 | ||
88427588 | 357 | static SIMPLE_DEV_PM_OPS(ath9k_pm_ops, ath_pci_suspend, ath_pci_resume); |
f0e94b47 RW |
358 | |
359 | #define ATH9K_PM_OPS (&ath9k_pm_ops) | |
360 | ||
88427588 | 361 | #else /* !CONFIG_PM_SLEEP */ |
f0e94b47 RW |
362 | |
363 | #define ATH9K_PM_OPS NULL | |
364 | ||
88427588 | 365 | #endif /* !CONFIG_PM_SLEEP */ |
f0e94b47 | 366 | |
6baff7f9 GJ |
367 | |
368 | MODULE_DEVICE_TABLE(pci, ath_pci_id_table); | |
369 | ||
370 | static struct pci_driver ath_pci_driver = { | |
371 | .name = "ath9k", | |
372 | .id_table = ath_pci_id_table, | |
373 | .probe = ath_pci_probe, | |
374 | .remove = ath_pci_remove, | |
f0e94b47 | 375 | .driver.pm = ATH9K_PM_OPS, |
6baff7f9 GJ |
376 | }; |
377 | ||
db0f41f5 | 378 | int ath_pci_init(void) |
6baff7f9 GJ |
379 | { |
380 | return pci_register_driver(&ath_pci_driver); | |
381 | } | |
382 | ||
383 | void ath_pci_exit(void) | |
384 | { | |
385 | pci_unregister_driver(&ath_pci_driver); | |
386 | } |