Commit | Line | Data |
---|---|---|
6baff7f9 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
6baff7f9 GJ |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
516304b0 JP |
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
18 | ||
6baff7f9 GJ |
19 | #include <linux/nl80211.h> |
20 | #include <linux/pci.h> | |
d4930086 | 21 | #include <linux/pci-aspm.h> |
a05b5d45 | 22 | #include <linux/ath9k_platform.h> |
9d9779e7 | 23 | #include <linux/module.h> |
394cf0a1 | 24 | #include "ath9k.h" |
6baff7f9 | 25 | |
a3aa1884 | 26 | static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = { |
6baff7f9 GJ |
27 | { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */ |
28 | { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */ | |
29 | { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */ | |
30 | { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */ | |
31 | { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */ | |
32 | { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */ | |
5ffaf8a3 | 33 | { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */ |
ac88b6ec VN |
34 | { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */ |
35 | { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */ | |
0efabd51 | 36 | { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */ |
1435894d | 37 | { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */ |
a508a6ea | 38 | { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */ |
423e38e8 | 39 | { PCI_VDEVICE(ATHEROS, 0x0034) }, /* PCI-E AR9462 */ |
d4e5979c | 40 | { PCI_VDEVICE(ATHEROS, 0x0037) }, /* PCI-E AR1111/AR9485 */ |
0c8070f9 | 41 | { PCI_VDEVICE(ATHEROS, 0x0036) }, /* PCI-E AR9565 */ |
6baff7f9 GJ |
42 | { 0 } |
43 | }; | |
44 | ||
84c87dc8 | 45 | |
6baff7f9 | 46 | /* return bus cachesize in 4B word units */ |
5bb12791 | 47 | static void ath_pci_read_cachesize(struct ath_common *common, int *csz) |
6baff7f9 | 48 | { |
bc974f4a | 49 | struct ath_softc *sc = (struct ath_softc *) common->priv; |
6baff7f9 GJ |
50 | u8 u8tmp; |
51 | ||
f020979d | 52 | pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp); |
6baff7f9 GJ |
53 | *csz = (int)u8tmp; |
54 | ||
55 | /* | |
25985edc | 56 | * This check was put in to avoid "unpleasant" consequences if |
6baff7f9 GJ |
57 | * the bootrom has not fully initialized all PCI devices. |
58 | * Sometimes the cache line size register is not set | |
59 | */ | |
60 | ||
61 | if (*csz == 0) | |
62 | *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */ | |
63 | } | |
64 | ||
5bb12791 | 65 | static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data) |
9dbeb91a | 66 | { |
a05b5d45 FF |
67 | struct ath_softc *sc = (struct ath_softc *) common->priv; |
68 | struct ath9k_platform_data *pdata = sc->dev->platform_data; | |
69 | ||
70 | if (pdata) { | |
71 | if (off >= (ARRAY_SIZE(pdata->eeprom_data))) { | |
3800276a JP |
72 | ath_err(common, |
73 | "%s: eeprom read failed, offset %08x is out of range\n", | |
74 | __func__, off); | |
a05b5d45 FF |
75 | } |
76 | ||
77 | *data = pdata->eeprom_data[off]; | |
78 | } else { | |
79 | struct ath_hw *ah = (struct ath_hw *) common->ah; | |
80 | ||
81 | common->ops->read(ah, AR5416_EEPROM_OFFSET + | |
82 | (off << AR5416_EEPROM_S)); | |
83 | ||
84 | if (!ath9k_hw_wait(ah, | |
85 | AR_EEPROM_STATUS_DATA, | |
86 | AR_EEPROM_STATUS_DATA_BUSY | | |
87 | AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0, | |
88 | AH_WAIT_TIMEOUT)) { | |
89 | return false; | |
90 | } | |
91 | ||
92 | *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA), | |
93 | AR_EEPROM_STATUS_DATA_VAL); | |
9dbeb91a GJ |
94 | } |
95 | ||
9dbeb91a GJ |
96 | return true; |
97 | } | |
98 | ||
69ce674b | 99 | /* Need to be called after we discover btcoex capabilities */ |
d4930086 SG |
100 | static void ath_pci_aspm_init(struct ath_common *common) |
101 | { | |
102 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
103 | struct ath_hw *ah = sc->sc_ah; | |
104 | struct pci_dev *pdev = to_pci_dev(sc->dev); | |
105 | struct pci_dev *parent; | |
08bd1080 | 106 | u16 aspm; |
d4930086 | 107 | |
d09f5f4c SM |
108 | if (!ah->is_pciexpress) |
109 | return; | |
110 | ||
d4930086 | 111 | parent = pdev->bus->self; |
22c55e6e JL |
112 | if (!parent) |
113 | return; | |
69ce674b | 114 | |
046b6802 SM |
115 | if ((ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) && |
116 | (AR_SREV_9285(ah))) { | |
a875621e | 117 | /* Bluetooth coexistence requires disabling ASPM. */ |
08bd1080 | 118 | pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, |
a875621e | 119 | PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1); |
69ce674b SG |
120 | |
121 | /* | |
122 | * Both upstream and downstream PCIe components should | |
123 | * have the same ASPM settings. | |
124 | */ | |
08bd1080 | 125 | pcie_capability_clear_word(parent, PCI_EXP_LNKCTL, |
a875621e | 126 | PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1); |
69ce674b | 127 | |
d09f5f4c | 128 | ath_info(common, "Disabling ASPM since BTCOEX is enabled\n"); |
69ce674b SG |
129 | return; |
130 | } | |
131 | ||
08bd1080 | 132 | pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm); |
a875621e | 133 | if (aspm & (PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1)) { |
d4930086 SG |
134 | ah->aspm_enabled = true; |
135 | /* Initialize PCIe PM and SERDES registers. */ | |
84c87dc8 | 136 | ath9k_hw_configpcipowersave(ah, false); |
d09f5f4c | 137 | ath_info(common, "ASPM enabled: 0x%x\n", aspm); |
d4930086 SG |
138 | } |
139 | } | |
140 | ||
83bd11a0 | 141 | static const struct ath_bus_ops ath_pci_bus_ops = { |
497ad9ad | 142 | .ath_bus_type = ATH_PCI, |
6baff7f9 | 143 | .read_cachesize = ath_pci_read_cachesize, |
9dbeb91a | 144 | .eeprom_read = ath_pci_eeprom_read, |
d4930086 | 145 | .aspm_init = ath_pci_aspm_init, |
6baff7f9 GJ |
146 | }; |
147 | ||
148 | static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |
149 | { | |
150 | void __iomem *mem; | |
151 | struct ath_softc *sc; | |
152 | struct ieee80211_hw *hw; | |
153 | u8 csz; | |
f0214843 | 154 | u32 val; |
6baff7f9 | 155 | int ret = 0; |
f934c4d9 | 156 | char hw_name[64]; |
6baff7f9 GJ |
157 | |
158 | if (pci_enable_device(pdev)) | |
159 | return -EIO; | |
160 | ||
e930438c | 161 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
6baff7f9 | 162 | if (ret) { |
516304b0 | 163 | pr_err("32-bit DMA not available\n"); |
285f2dda | 164 | goto err_dma; |
6baff7f9 GJ |
165 | } |
166 | ||
e930438c | 167 | ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
6baff7f9 | 168 | if (ret) { |
516304b0 | 169 | pr_err("32-bit DMA consistent DMA enable failed\n"); |
285f2dda | 170 | goto err_dma; |
6baff7f9 GJ |
171 | } |
172 | ||
173 | /* | |
174 | * Cache line size is used to size and align various | |
175 | * structures used to communicate with the hardware. | |
176 | */ | |
177 | pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); | |
178 | if (csz == 0) { | |
179 | /* | |
180 | * Linux 2.4.18 (at least) writes the cache line size | |
181 | * register as a 16-bit wide register which is wrong. | |
182 | * We must have this setup properly for rx buffer | |
183 | * DMA to work so force a reasonable value here if it | |
184 | * comes up zero. | |
185 | */ | |
186 | csz = L1_CACHE_BYTES / sizeof(u32); | |
187 | pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); | |
188 | } | |
189 | /* | |
190 | * The default setting of latency timer yields poor results, | |
191 | * set it to the value used by other systems. It may be worth | |
192 | * tweaking this setting more. | |
193 | */ | |
194 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); | |
195 | ||
196 | pci_set_master(pdev); | |
197 | ||
f0214843 JM |
198 | /* |
199 | * Disable the RETRY_TIMEOUT register (0x41) to keep | |
200 | * PCI Tx retries from interfering with C3 CPU state. | |
201 | */ | |
202 | pci_read_config_dword(pdev, 0x40, &val); | |
203 | if ((val & 0x0000ff00) != 0) | |
204 | pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); | |
205 | ||
6baff7f9 GJ |
206 | ret = pci_request_region(pdev, 0, "ath9k"); |
207 | if (ret) { | |
208 | dev_err(&pdev->dev, "PCI memory region reserve error\n"); | |
209 | ret = -ENODEV; | |
285f2dda | 210 | goto err_region; |
6baff7f9 GJ |
211 | } |
212 | ||
213 | mem = pci_iomap(pdev, 0, 0); | |
214 | if (!mem) { | |
516304b0 | 215 | pr_err("PCI memory map error\n") ; |
6baff7f9 | 216 | ret = -EIO; |
285f2dda | 217 | goto err_iomap; |
6baff7f9 GJ |
218 | } |
219 | ||
9ac58615 | 220 | hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops); |
db6be53c | 221 | if (!hw) { |
285f2dda | 222 | dev_err(&pdev->dev, "No memory for ieee80211_hw\n"); |
db6be53c | 223 | ret = -ENOMEM; |
285f2dda | 224 | goto err_alloc_hw; |
6baff7f9 GJ |
225 | } |
226 | ||
227 | SET_IEEE80211_DEV(hw, &pdev->dev); | |
228 | pci_set_drvdata(pdev, hw); | |
229 | ||
9ac58615 | 230 | sc = hw->priv; |
6baff7f9 GJ |
231 | sc->hw = hw; |
232 | sc->dev = &pdev->dev; | |
233 | sc->mem = mem; | |
6baff7f9 | 234 | |
5e4ea1f0 | 235 | /* Will be cleared in ath9k_start() */ |
781b14a3 | 236 | set_bit(SC_OP_INVALID, &sc->sc_flags); |
6baff7f9 | 237 | |
fc548af8 | 238 | ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc); |
580171f7 LR |
239 | if (ret) { |
240 | dev_err(&pdev->dev, "request_irq failed\n"); | |
285f2dda | 241 | goto err_irq; |
6baff7f9 GJ |
242 | } |
243 | ||
244 | sc->irq = pdev->irq; | |
245 | ||
eb93e891 | 246 | ret = ath9k_init_device(id->device, sc, &ath_pci_bus_ops); |
285f2dda S |
247 | if (ret) { |
248 | dev_err(&pdev->dev, "Failed to initialize device\n"); | |
249 | goto err_init; | |
250 | } | |
251 | ||
252 | ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name)); | |
c96c31e4 JP |
253 | wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n", |
254 | hw_name, (unsigned long)mem, pdev->irq); | |
6baff7f9 GJ |
255 | |
256 | return 0; | |
285f2dda S |
257 | |
258 | err_init: | |
259 | free_irq(sc->irq, sc); | |
260 | err_irq: | |
6baff7f9 | 261 | ieee80211_free_hw(hw); |
285f2dda | 262 | err_alloc_hw: |
6baff7f9 | 263 | pci_iounmap(pdev, mem); |
285f2dda | 264 | err_iomap: |
6baff7f9 | 265 | pci_release_region(pdev, 0); |
285f2dda S |
266 | err_region: |
267 | /* Nothing */ | |
268 | err_dma: | |
6baff7f9 GJ |
269 | pci_disable_device(pdev); |
270 | return ret; | |
271 | } | |
272 | ||
273 | static void ath_pci_remove(struct pci_dev *pdev) | |
274 | { | |
275 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); | |
9ac58615 | 276 | struct ath_softc *sc = hw->priv; |
ab5132a2 | 277 | void __iomem *mem = sc->mem; |
6baff7f9 | 278 | |
d584747b RM |
279 | if (!is_ath9k_unloaded) |
280 | sc->sc_ah->ah_flags |= AH_UNPLUGGED; | |
285f2dda S |
281 | ath9k_deinit_device(sc); |
282 | free_irq(sc->irq, sc); | |
283 | ieee80211_free_hw(sc->hw); | |
ab5132a2 PR |
284 | |
285 | pci_iounmap(pdev, mem); | |
286 | pci_disable_device(pdev); | |
287 | pci_release_region(pdev, 0); | |
6baff7f9 GJ |
288 | } |
289 | ||
88427588 | 290 | #ifdef CONFIG_PM_SLEEP |
6baff7f9 | 291 | |
f0e94b47 | 292 | static int ath_pci_suspend(struct device *device) |
6baff7f9 | 293 | { |
f0e94b47 | 294 | struct pci_dev *pdev = to_pci_dev(device); |
6baff7f9 | 295 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); |
9ac58615 | 296 | struct ath_softc *sc = hw->priv; |
6baff7f9 | 297 | |
4a17a50d MSS |
298 | if (sc->wow_enabled) |
299 | return 0; | |
300 | ||
c31eb8e9 RM |
301 | /* The device has to be moved to FULLSLEEP forcibly. |
302 | * Otherwise the chip never moved to full sleep, | |
303 | * when no interface is up. | |
304 | */ | |
e19f15ac | 305 | ath9k_stop_btcoex(sc); |
c0c11741 | 306 | ath9k_hw_disable(sc->sc_ah); |
c31eb8e9 RM |
307 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); |
308 | ||
6baff7f9 GJ |
309 | return 0; |
310 | } | |
311 | ||
f0e94b47 | 312 | static int ath_pci_resume(struct device *device) |
6baff7f9 | 313 | { |
f0e94b47 | 314 | struct pci_dev *pdev = to_pci_dev(device); |
93170516 FF |
315 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); |
316 | struct ath_softc *sc = hw->priv; | |
ceb26a60 FF |
317 | struct ath_hw *ah = sc->sc_ah; |
318 | struct ath_common *common = ath9k_hw_common(ah); | |
f0214843 | 319 | u32 val; |
523c36fc | 320 | |
f0214843 JM |
321 | /* |
322 | * Suspend/Resume resets the PCI configuration space, so we have to | |
323 | * re-disable the RETRY_TIMEOUT register (0x41) to keep | |
324 | * PCI Tx retries from interfering with C3 CPU state | |
325 | */ | |
326 | pci_read_config_dword(pdev, 0x40, &val); | |
327 | if ((val & 0x0000ff00) != 0) | |
328 | pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); | |
6baff7f9 | 329 | |
93170516 | 330 | ath_pci_aspm_init(common); |
ceb26a60 | 331 | ah->reset_power_on = false; |
93170516 | 332 | |
6baff7f9 GJ |
333 | return 0; |
334 | } | |
335 | ||
88427588 | 336 | static SIMPLE_DEV_PM_OPS(ath9k_pm_ops, ath_pci_suspend, ath_pci_resume); |
f0e94b47 RW |
337 | |
338 | #define ATH9K_PM_OPS (&ath9k_pm_ops) | |
339 | ||
88427588 | 340 | #else /* !CONFIG_PM_SLEEP */ |
f0e94b47 RW |
341 | |
342 | #define ATH9K_PM_OPS NULL | |
343 | ||
88427588 | 344 | #endif /* !CONFIG_PM_SLEEP */ |
f0e94b47 | 345 | |
6baff7f9 GJ |
346 | |
347 | MODULE_DEVICE_TABLE(pci, ath_pci_id_table); | |
348 | ||
349 | static struct pci_driver ath_pci_driver = { | |
350 | .name = "ath9k", | |
351 | .id_table = ath_pci_id_table, | |
352 | .probe = ath_pci_probe, | |
353 | .remove = ath_pci_remove, | |
f0e94b47 | 354 | .driver.pm = ATH9K_PM_OPS, |
6baff7f9 GJ |
355 | }; |
356 | ||
db0f41f5 | 357 | int ath_pci_init(void) |
6baff7f9 GJ |
358 | { |
359 | return pci_register_driver(&ath_pci_driver); | |
360 | } | |
361 | ||
362 | void ath_pci_exit(void) | |
363 | { | |
364 | pci_unregister_driver(&ath_pci_driver); | |
365 | } |