Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
b7f080cf | 17 | #include <linux/dma-mapping.h> |
394cf0a1 | 18 | #include "ath9k.h" |
b622a720 | 19 | #include "ar9003_mac.h" |
f078f209 | 20 | |
b5c80475 FF |
21 | #define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb)) |
22 | ||
ededf1f8 VT |
23 | static inline bool ath9k_check_auto_sleep(struct ath_softc *sc) |
24 | { | |
25 | return sc->ps_enabled && | |
26 | (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP); | |
27 | } | |
28 | ||
f078f209 LR |
29 | /* |
30 | * Setup and link descriptors. | |
31 | * | |
32 | * 11N: we can no longer afford to self link the last descriptor. | |
33 | * MAC acknowledges BA status as long as it copies frames to host | |
34 | * buffer (or rx fifo). This can incorrectly acknowledge packets | |
35 | * to a sender if last desc is self-linked. | |
f078f209 | 36 | */ |
f078f209 LR |
37 | static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf) |
38 | { | |
cbe61d8a | 39 | struct ath_hw *ah = sc->sc_ah; |
cc861f74 | 40 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 LR |
41 | struct ath_desc *ds; |
42 | struct sk_buff *skb; | |
43 | ||
44 | ATH_RXBUF_RESET(bf); | |
45 | ||
46 | ds = bf->bf_desc; | |
be0418ad | 47 | ds->ds_link = 0; /* link to null */ |
f078f209 LR |
48 | ds->ds_data = bf->bf_buf_addr; |
49 | ||
be0418ad | 50 | /* virtual addr of the beginning of the buffer. */ |
f078f209 | 51 | skb = bf->bf_mpdu; |
9680e8a3 | 52 | BUG_ON(skb == NULL); |
f078f209 LR |
53 | ds->ds_vdata = skb->data; |
54 | ||
cc861f74 LR |
55 | /* |
56 | * setup rx descriptors. The rx_bufsize here tells the hardware | |
b4b6cda2 | 57 | * how much data it can DMA to us and that we are prepared |
cc861f74 LR |
58 | * to process |
59 | */ | |
b77f483f | 60 | ath9k_hw_setuprxdesc(ah, ds, |
cc861f74 | 61 | common->rx_bufsize, |
f078f209 LR |
62 | 0); |
63 | ||
b77f483f | 64 | if (sc->rx.rxlink == NULL) |
f078f209 LR |
65 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); |
66 | else | |
b77f483f | 67 | *sc->rx.rxlink = bf->bf_daddr; |
f078f209 | 68 | |
b77f483f | 69 | sc->rx.rxlink = &ds->ds_link; |
f078f209 LR |
70 | } |
71 | ||
ff37e337 S |
72 | static void ath_setdefantenna(struct ath_softc *sc, u32 antenna) |
73 | { | |
74 | /* XXX block beacon interrupts */ | |
75 | ath9k_hw_setantenna(sc->sc_ah, antenna); | |
b77f483f S |
76 | sc->rx.defant = antenna; |
77 | sc->rx.rxotherant = 0; | |
ff37e337 S |
78 | } |
79 | ||
f078f209 LR |
80 | static void ath_opmode_init(struct ath_softc *sc) |
81 | { | |
cbe61d8a | 82 | struct ath_hw *ah = sc->sc_ah; |
1510718d LR |
83 | struct ath_common *common = ath9k_hw_common(ah); |
84 | ||
f078f209 LR |
85 | u32 rfilt, mfilt[2]; |
86 | ||
87 | /* configure rx filter */ | |
88 | rfilt = ath_calcrxfilter(sc); | |
89 | ath9k_hw_setrxfilter(ah, rfilt); | |
90 | ||
91 | /* configure bssid mask */ | |
364734fa | 92 | ath_hw_setbssidmask(common); |
f078f209 LR |
93 | |
94 | /* configure operational mode */ | |
95 | ath9k_hw_setopmode(ah); | |
96 | ||
f078f209 LR |
97 | /* calculate and install multicast filter */ |
98 | mfilt[0] = mfilt[1] = ~0; | |
f078f209 | 99 | ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]); |
f078f209 LR |
100 | } |
101 | ||
b5c80475 FF |
102 | static bool ath_rx_edma_buf_link(struct ath_softc *sc, |
103 | enum ath9k_rx_qtype qtype) | |
f078f209 | 104 | { |
b5c80475 FF |
105 | struct ath_hw *ah = sc->sc_ah; |
106 | struct ath_rx_edma *rx_edma; | |
f078f209 LR |
107 | struct sk_buff *skb; |
108 | struct ath_buf *bf; | |
f078f209 | 109 | |
b5c80475 FF |
110 | rx_edma = &sc->rx.rx_edma[qtype]; |
111 | if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize) | |
112 | return false; | |
f078f209 | 113 | |
b5c80475 FF |
114 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); |
115 | list_del_init(&bf->list); | |
f078f209 | 116 | |
b5c80475 FF |
117 | skb = bf->bf_mpdu; |
118 | ||
119 | ATH_RXBUF_RESET(bf); | |
120 | memset(skb->data, 0, ah->caps.rx_status_len); | |
121 | dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, | |
122 | ah->caps.rx_status_len, DMA_TO_DEVICE); | |
f078f209 | 123 | |
b5c80475 FF |
124 | SKB_CB_ATHBUF(skb) = bf; |
125 | ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype); | |
126 | skb_queue_tail(&rx_edma->rx_fifo, skb); | |
f078f209 | 127 | |
b5c80475 FF |
128 | return true; |
129 | } | |
130 | ||
131 | static void ath_rx_addbuffer_edma(struct ath_softc *sc, | |
132 | enum ath9k_rx_qtype qtype, int size) | |
133 | { | |
b5c80475 | 134 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
6a01f0c0 | 135 | struct ath_buf *bf, *tbf; |
b5c80475 | 136 | |
b5c80475 | 137 | if (list_empty(&sc->rx.rxbuf)) { |
d2182b69 | 138 | ath_dbg(common, QUEUE, "No free rx buf available\n"); |
b5c80475 | 139 | return; |
797fe5cb | 140 | } |
f078f209 | 141 | |
6a01f0c0 | 142 | list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) |
b5c80475 FF |
143 | if (!ath_rx_edma_buf_link(sc, qtype)) |
144 | break; | |
145 | ||
b5c80475 FF |
146 | } |
147 | ||
148 | static void ath_rx_remove_buffer(struct ath_softc *sc, | |
149 | enum ath9k_rx_qtype qtype) | |
150 | { | |
151 | struct ath_buf *bf; | |
152 | struct ath_rx_edma *rx_edma; | |
153 | struct sk_buff *skb; | |
154 | ||
155 | rx_edma = &sc->rx.rx_edma[qtype]; | |
156 | ||
157 | while ((skb = skb_dequeue(&rx_edma->rx_fifo)) != NULL) { | |
158 | bf = SKB_CB_ATHBUF(skb); | |
159 | BUG_ON(!bf); | |
160 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
161 | } | |
162 | } | |
163 | ||
164 | static void ath_rx_edma_cleanup(struct ath_softc *sc) | |
165 | { | |
ba542385 MSS |
166 | struct ath_hw *ah = sc->sc_ah; |
167 | struct ath_common *common = ath9k_hw_common(ah); | |
b5c80475 FF |
168 | struct ath_buf *bf; |
169 | ||
170 | ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP); | |
171 | ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP); | |
172 | ||
797fe5cb | 173 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { |
ba542385 MSS |
174 | if (bf->bf_mpdu) { |
175 | dma_unmap_single(sc->dev, bf->bf_buf_addr, | |
176 | common->rx_bufsize, | |
177 | DMA_BIDIRECTIONAL); | |
b5c80475 | 178 | dev_kfree_skb_any(bf->bf_mpdu); |
ba542385 MSS |
179 | bf->bf_buf_addr = 0; |
180 | bf->bf_mpdu = NULL; | |
181 | } | |
b5c80475 FF |
182 | } |
183 | ||
184 | INIT_LIST_HEAD(&sc->rx.rxbuf); | |
185 | ||
186 | kfree(sc->rx.rx_bufptr); | |
187 | sc->rx.rx_bufptr = NULL; | |
188 | } | |
189 | ||
190 | static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size) | |
191 | { | |
192 | skb_queue_head_init(&rx_edma->rx_fifo); | |
b5c80475 FF |
193 | rx_edma->rx_fifo_hwsize = size; |
194 | } | |
195 | ||
196 | static int ath_rx_edma_init(struct ath_softc *sc, int nbufs) | |
197 | { | |
198 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
199 | struct ath_hw *ah = sc->sc_ah; | |
200 | struct sk_buff *skb; | |
201 | struct ath_buf *bf; | |
202 | int error = 0, i; | |
203 | u32 size; | |
204 | ||
b5c80475 FF |
205 | ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - |
206 | ah->caps.rx_status_len); | |
207 | ||
208 | ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP], | |
209 | ah->caps.rx_lp_qdepth); | |
210 | ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP], | |
211 | ah->caps.rx_hp_qdepth); | |
212 | ||
213 | size = sizeof(struct ath_buf) * nbufs; | |
214 | bf = kzalloc(size, GFP_KERNEL); | |
215 | if (!bf) | |
216 | return -ENOMEM; | |
217 | ||
218 | INIT_LIST_HEAD(&sc->rx.rxbuf); | |
219 | sc->rx.rx_bufptr = bf; | |
220 | ||
221 | for (i = 0; i < nbufs; i++, bf++) { | |
cc861f74 | 222 | skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL); |
b5c80475 | 223 | if (!skb) { |
797fe5cb | 224 | error = -ENOMEM; |
b5c80475 | 225 | goto rx_init_fail; |
f078f209 | 226 | } |
f078f209 | 227 | |
b5c80475 | 228 | memset(skb->data, 0, common->rx_bufsize); |
797fe5cb | 229 | bf->bf_mpdu = skb; |
b5c80475 | 230 | |
797fe5cb | 231 | bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, |
cc861f74 | 232 | common->rx_bufsize, |
b5c80475 | 233 | DMA_BIDIRECTIONAL); |
797fe5cb | 234 | if (unlikely(dma_mapping_error(sc->dev, |
b5c80475 FF |
235 | bf->bf_buf_addr))) { |
236 | dev_kfree_skb_any(skb); | |
237 | bf->bf_mpdu = NULL; | |
6cf9e995 | 238 | bf->bf_buf_addr = 0; |
3800276a | 239 | ath_err(common, |
b5c80475 FF |
240 | "dma_mapping_error() on RX init\n"); |
241 | error = -ENOMEM; | |
242 | goto rx_init_fail; | |
243 | } | |
244 | ||
245 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
246 | } | |
247 | ||
248 | return 0; | |
249 | ||
250 | rx_init_fail: | |
251 | ath_rx_edma_cleanup(sc); | |
252 | return error; | |
253 | } | |
254 | ||
255 | static void ath_edma_start_recv(struct ath_softc *sc) | |
256 | { | |
257 | spin_lock_bh(&sc->rx.rxbuflock); | |
258 | ||
259 | ath9k_hw_rxena(sc->sc_ah); | |
260 | ||
261 | ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP, | |
262 | sc->rx.rx_edma[ATH9K_RX_QUEUE_HP].rx_fifo_hwsize); | |
263 | ||
264 | ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP, | |
265 | sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize); | |
266 | ||
b5c80475 FF |
267 | ath_opmode_init(sc); |
268 | ||
4cb54fa3 | 269 | ath9k_hw_startpcureceive(sc->sc_ah, !!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)); |
7583c550 LR |
270 | |
271 | spin_unlock_bh(&sc->rx.rxbuflock); | |
b5c80475 FF |
272 | } |
273 | ||
274 | static void ath_edma_stop_recv(struct ath_softc *sc) | |
275 | { | |
b5c80475 FF |
276 | ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP); |
277 | ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP); | |
b5c80475 FF |
278 | } |
279 | ||
280 | int ath_rx_init(struct ath_softc *sc, int nbufs) | |
281 | { | |
282 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
283 | struct sk_buff *skb; | |
284 | struct ath_buf *bf; | |
285 | int error = 0; | |
286 | ||
4bdd1e97 | 287 | spin_lock_init(&sc->sc_pcu_lock); |
b5c80475 | 288 | spin_lock_init(&sc->rx.rxbuflock); |
781b14a3 | 289 | clear_bit(SC_OP_RXFLUSH, &sc->sc_flags); |
b5c80475 | 290 | |
0d95521e FF |
291 | common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 + |
292 | sc->sc_ah->caps.rx_status_len; | |
293 | ||
b5c80475 FF |
294 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
295 | return ath_rx_edma_init(sc, nbufs); | |
296 | } else { | |
d2182b69 | 297 | ath_dbg(common, CONFIG, "cachelsz %u rxbufsize %u\n", |
226afe68 | 298 | common->cachelsz, common->rx_bufsize); |
b5c80475 FF |
299 | |
300 | /* Initialize rx descriptors */ | |
301 | ||
302 | error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf, | |
4adfcded | 303 | "rx", nbufs, 1, 0); |
b5c80475 | 304 | if (error != 0) { |
3800276a JP |
305 | ath_err(common, |
306 | "failed to allocate rx descriptors: %d\n", | |
307 | error); | |
797fe5cb S |
308 | goto err; |
309 | } | |
b5c80475 FF |
310 | |
311 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { | |
312 | skb = ath_rxbuf_alloc(common, common->rx_bufsize, | |
313 | GFP_KERNEL); | |
314 | if (skb == NULL) { | |
315 | error = -ENOMEM; | |
316 | goto err; | |
317 | } | |
318 | ||
319 | bf->bf_mpdu = skb; | |
320 | bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, | |
321 | common->rx_bufsize, | |
322 | DMA_FROM_DEVICE); | |
323 | if (unlikely(dma_mapping_error(sc->dev, | |
324 | bf->bf_buf_addr))) { | |
325 | dev_kfree_skb_any(skb); | |
326 | bf->bf_mpdu = NULL; | |
6cf9e995 | 327 | bf->bf_buf_addr = 0; |
3800276a JP |
328 | ath_err(common, |
329 | "dma_mapping_error() on RX init\n"); | |
b5c80475 FF |
330 | error = -ENOMEM; |
331 | goto err; | |
332 | } | |
b5c80475 FF |
333 | } |
334 | sc->rx.rxlink = NULL; | |
797fe5cb | 335 | } |
f078f209 | 336 | |
797fe5cb | 337 | err: |
f078f209 LR |
338 | if (error) |
339 | ath_rx_cleanup(sc); | |
340 | ||
341 | return error; | |
342 | } | |
343 | ||
f078f209 LR |
344 | void ath_rx_cleanup(struct ath_softc *sc) |
345 | { | |
cc861f74 LR |
346 | struct ath_hw *ah = sc->sc_ah; |
347 | struct ath_common *common = ath9k_hw_common(ah); | |
f078f209 LR |
348 | struct sk_buff *skb; |
349 | struct ath_buf *bf; | |
350 | ||
b5c80475 FF |
351 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
352 | ath_rx_edma_cleanup(sc); | |
353 | return; | |
354 | } else { | |
355 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { | |
356 | skb = bf->bf_mpdu; | |
357 | if (skb) { | |
358 | dma_unmap_single(sc->dev, bf->bf_buf_addr, | |
359 | common->rx_bufsize, | |
360 | DMA_FROM_DEVICE); | |
361 | dev_kfree_skb(skb); | |
6cf9e995 BG |
362 | bf->bf_buf_addr = 0; |
363 | bf->bf_mpdu = NULL; | |
b5c80475 | 364 | } |
051b9191 | 365 | } |
f078f209 | 366 | |
b5c80475 FF |
367 | if (sc->rx.rxdma.dd_desc_len != 0) |
368 | ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf); | |
369 | } | |
f078f209 LR |
370 | } |
371 | ||
372 | /* | |
373 | * Calculate the receive filter according to the | |
374 | * operating mode and state: | |
375 | * | |
376 | * o always accept unicast, broadcast, and multicast traffic | |
377 | * o maintain current state of phy error reception (the hal | |
378 | * may enable phy error frames for noise immunity work) | |
379 | * o probe request frames are accepted only when operating in | |
380 | * hostap, adhoc, or monitor modes | |
381 | * o enable promiscuous mode according to the interface state | |
382 | * o accept beacons: | |
383 | * - when operating in adhoc mode so the 802.11 layer creates | |
384 | * node table entries for peers, | |
385 | * - when operating in station mode for collecting rssi data when | |
386 | * the station is otherwise quiet, or | |
387 | * - when operating as a repeater so we see repeater-sta beacons | |
388 | * - when scanning | |
389 | */ | |
390 | ||
391 | u32 ath_calcrxfilter(struct ath_softc *sc) | |
392 | { | |
f078f209 LR |
393 | u32 rfilt; |
394 | ||
ac06697c | 395 | rfilt = ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST |
f078f209 LR |
396 | | ATH9K_RX_FILTER_MCAST; |
397 | ||
9c1d8e4a | 398 | if (sc->rx.rxfilter & FIF_PROBE_REQ) |
f078f209 LR |
399 | rfilt |= ATH9K_RX_FILTER_PROBEREQ; |
400 | ||
217ba9da JM |
401 | /* |
402 | * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station | |
403 | * mode interface or when in monitor mode. AP mode does not need this | |
404 | * since it receives all in-BSS frames anyway. | |
405 | */ | |
2e286947 | 406 | if (sc->sc_ah->is_monitoring) |
f078f209 | 407 | rfilt |= ATH9K_RX_FILTER_PROM; |
f078f209 | 408 | |
d42c6b71 S |
409 | if (sc->rx.rxfilter & FIF_CONTROL) |
410 | rfilt |= ATH9K_RX_FILTER_CONTROL; | |
411 | ||
dbaaa147 | 412 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) && |
cfda6695 | 413 | (sc->nvifs <= 1) && |
dbaaa147 VT |
414 | !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)) |
415 | rfilt |= ATH9K_RX_FILTER_MYBEACON; | |
416 | else | |
f078f209 LR |
417 | rfilt |= ATH9K_RX_FILTER_BEACON; |
418 | ||
264bbec8 | 419 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) || |
66afad01 | 420 | (sc->rx.rxfilter & FIF_PSPOLL)) |
dbaaa147 | 421 | rfilt |= ATH9K_RX_FILTER_PSPOLL; |
be0418ad | 422 | |
7ea310be S |
423 | if (conf_is_ht(&sc->hw->conf)) |
424 | rfilt |= ATH9K_RX_FILTER_COMP_BAR; | |
425 | ||
7545daf4 | 426 | if (sc->nvifs > 1 || (sc->rx.rxfilter & FIF_OTHER_BSS)) { |
5eb6ba83 JC |
427 | /* The following may also be needed for other older chips */ |
428 | if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160) | |
429 | rfilt |= ATH9K_RX_FILTER_PROM; | |
b93bce2a JM |
430 | rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL; |
431 | } | |
432 | ||
b3d7aa43 GJ |
433 | if (AR_SREV_9550(sc->sc_ah)) |
434 | rfilt |= ATH9K_RX_FILTER_4ADDRESS; | |
435 | ||
f078f209 | 436 | return rfilt; |
7dcfdcd9 | 437 | |
f078f209 LR |
438 | } |
439 | ||
f078f209 LR |
440 | int ath_startrecv(struct ath_softc *sc) |
441 | { | |
cbe61d8a | 442 | struct ath_hw *ah = sc->sc_ah; |
f078f209 LR |
443 | struct ath_buf *bf, *tbf; |
444 | ||
b5c80475 FF |
445 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
446 | ath_edma_start_recv(sc); | |
447 | return 0; | |
448 | } | |
449 | ||
b77f483f S |
450 | spin_lock_bh(&sc->rx.rxbuflock); |
451 | if (list_empty(&sc->rx.rxbuf)) | |
f078f209 LR |
452 | goto start_recv; |
453 | ||
b77f483f S |
454 | sc->rx.rxlink = NULL; |
455 | list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) { | |
f078f209 LR |
456 | ath_rx_buf_link(sc, bf); |
457 | } | |
458 | ||
459 | /* We could have deleted elements so the list may be empty now */ | |
b77f483f | 460 | if (list_empty(&sc->rx.rxbuf)) |
f078f209 LR |
461 | goto start_recv; |
462 | ||
b77f483f | 463 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); |
f078f209 | 464 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); |
be0418ad | 465 | ath9k_hw_rxena(ah); |
f078f209 LR |
466 | |
467 | start_recv: | |
be0418ad | 468 | ath_opmode_init(sc); |
4cb54fa3 | 469 | ath9k_hw_startpcureceive(ah, !!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)); |
be0418ad | 470 | |
7583c550 LR |
471 | spin_unlock_bh(&sc->rx.rxbuflock); |
472 | ||
f078f209 LR |
473 | return 0; |
474 | } | |
475 | ||
f078f209 LR |
476 | bool ath_stoprecv(struct ath_softc *sc) |
477 | { | |
cbe61d8a | 478 | struct ath_hw *ah = sc->sc_ah; |
5882da02 | 479 | bool stopped, reset = false; |
f078f209 | 480 | |
1e450285 | 481 | spin_lock_bh(&sc->rx.rxbuflock); |
d47844a0 | 482 | ath9k_hw_abortpcurecv(ah); |
be0418ad | 483 | ath9k_hw_setrxfilter(ah, 0); |
5882da02 | 484 | stopped = ath9k_hw_stopdmarecv(ah, &reset); |
b5c80475 FF |
485 | |
486 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
487 | ath_edma_stop_recv(sc); | |
488 | else | |
489 | sc->rx.rxlink = NULL; | |
1e450285 | 490 | spin_unlock_bh(&sc->rx.rxbuflock); |
be0418ad | 491 | |
d584747b RM |
492 | if (!(ah->ah_flags & AH_UNPLUGGED) && |
493 | unlikely(!stopped)) { | |
d7fd1b50 BG |
494 | ath_err(ath9k_hw_common(sc->sc_ah), |
495 | "Could not stop RX, we could be " | |
496 | "confusing the DMA engine when we start RX up\n"); | |
497 | ATH_DBG_WARN_ON_ONCE(!stopped); | |
498 | } | |
2232d31b | 499 | return stopped && !reset; |
f078f209 LR |
500 | } |
501 | ||
f078f209 LR |
502 | void ath_flushrecv(struct ath_softc *sc) |
503 | { | |
781b14a3 | 504 | set_bit(SC_OP_RXFLUSH, &sc->sc_flags); |
b5c80475 FF |
505 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
506 | ath_rx_tasklet(sc, 1, true); | |
507 | ath_rx_tasklet(sc, 1, false); | |
781b14a3 | 508 | clear_bit(SC_OP_RXFLUSH, &sc->sc_flags); |
f078f209 LR |
509 | } |
510 | ||
cc65965c JM |
511 | static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb) |
512 | { | |
513 | /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */ | |
514 | struct ieee80211_mgmt *mgmt; | |
515 | u8 *pos, *end, id, elen; | |
516 | struct ieee80211_tim_ie *tim; | |
517 | ||
518 | mgmt = (struct ieee80211_mgmt *)skb->data; | |
519 | pos = mgmt->u.beacon.variable; | |
520 | end = skb->data + skb->len; | |
521 | ||
522 | while (pos + 2 < end) { | |
523 | id = *pos++; | |
524 | elen = *pos++; | |
525 | if (pos + elen > end) | |
526 | break; | |
527 | ||
528 | if (id == WLAN_EID_TIM) { | |
529 | if (elen < sizeof(*tim)) | |
530 | break; | |
531 | tim = (struct ieee80211_tim_ie *) pos; | |
532 | if (tim->dtim_count != 0) | |
533 | break; | |
534 | return tim->bitmap_ctrl & 0x01; | |
535 | } | |
536 | ||
537 | pos += elen; | |
538 | } | |
539 | ||
540 | return false; | |
541 | } | |
542 | ||
cc65965c JM |
543 | static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb) |
544 | { | |
1510718d | 545 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
cc65965c JM |
546 | |
547 | if (skb->len < 24 + 8 + 2 + 2) | |
548 | return; | |
549 | ||
1b04b930 | 550 | sc->ps_flags &= ~PS_WAIT_FOR_BEACON; |
293dc5df | 551 | |
1b04b930 S |
552 | if (sc->ps_flags & PS_BEACON_SYNC) { |
553 | sc->ps_flags &= ~PS_BEACON_SYNC; | |
d2182b69 | 554 | ath_dbg(common, PS, |
226afe68 | 555 | "Reconfigure Beacon timers based on timestamp from the AP\n"); |
ef4ad633 | 556 | ath9k_set_beacon(sc); |
ccdfeab6 JM |
557 | } |
558 | ||
cc65965c JM |
559 | if (ath_beacon_dtim_pending_cab(skb)) { |
560 | /* | |
561 | * Remain awake waiting for buffered broadcast/multicast | |
58f5fffd GJ |
562 | * frames. If the last broadcast/multicast frame is not |
563 | * received properly, the next beacon frame will work as | |
564 | * a backup trigger for returning into NETWORK SLEEP state, | |
565 | * so we are waiting for it as well. | |
cc65965c | 566 | */ |
d2182b69 | 567 | ath_dbg(common, PS, |
226afe68 | 568 | "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n"); |
1b04b930 | 569 | sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON; |
cc65965c JM |
570 | return; |
571 | } | |
572 | ||
1b04b930 | 573 | if (sc->ps_flags & PS_WAIT_FOR_CAB) { |
cc65965c JM |
574 | /* |
575 | * This can happen if a broadcast frame is dropped or the AP | |
576 | * fails to send a frame indicating that all CAB frames have | |
577 | * been delivered. | |
578 | */ | |
1b04b930 | 579 | sc->ps_flags &= ~PS_WAIT_FOR_CAB; |
d2182b69 | 580 | ath_dbg(common, PS, "PS wait for CAB frames timed out\n"); |
cc65965c | 581 | } |
cc65965c JM |
582 | } |
583 | ||
f73c604c | 584 | static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb, bool mybeacon) |
cc65965c JM |
585 | { |
586 | struct ieee80211_hdr *hdr; | |
c46917bb | 587 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
cc65965c JM |
588 | |
589 | hdr = (struct ieee80211_hdr *)skb->data; | |
590 | ||
591 | /* Process Beacon and CAB receive in PS state */ | |
ededf1f8 | 592 | if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc)) |
07c15a3f | 593 | && mybeacon) { |
cc65965c | 594 | ath_rx_ps_beacon(sc, skb); |
07c15a3f SM |
595 | } else if ((sc->ps_flags & PS_WAIT_FOR_CAB) && |
596 | (ieee80211_is_data(hdr->frame_control) || | |
597 | ieee80211_is_action(hdr->frame_control)) && | |
598 | is_multicast_ether_addr(hdr->addr1) && | |
599 | !ieee80211_has_moredata(hdr->frame_control)) { | |
cc65965c JM |
600 | /* |
601 | * No more broadcast/multicast frames to be received at this | |
602 | * point. | |
603 | */ | |
3fac6dfd | 604 | sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON); |
d2182b69 | 605 | ath_dbg(common, PS, |
226afe68 | 606 | "All PS CAB frames received, back to sleep\n"); |
1b04b930 | 607 | } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) && |
9a23f9ca JM |
608 | !is_multicast_ether_addr(hdr->addr1) && |
609 | !ieee80211_has_morefrags(hdr->frame_control)) { | |
1b04b930 | 610 | sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA; |
d2182b69 | 611 | ath_dbg(common, PS, |
226afe68 | 612 | "Going back to sleep after having received PS-Poll data (0x%lx)\n", |
1b04b930 S |
613 | sc->ps_flags & (PS_WAIT_FOR_BEACON | |
614 | PS_WAIT_FOR_CAB | | |
615 | PS_WAIT_FOR_PSPOLL_DATA | | |
616 | PS_WAIT_FOR_TX_ACK)); | |
cc65965c JM |
617 | } |
618 | } | |
619 | ||
b5c80475 | 620 | static bool ath_edma_get_buffers(struct ath_softc *sc, |
3a2923e8 FF |
621 | enum ath9k_rx_qtype qtype, |
622 | struct ath_rx_status *rs, | |
623 | struct ath_buf **dest) | |
f078f209 | 624 | { |
b5c80475 FF |
625 | struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype]; |
626 | struct ath_hw *ah = sc->sc_ah; | |
627 | struct ath_common *common = ath9k_hw_common(ah); | |
628 | struct sk_buff *skb; | |
629 | struct ath_buf *bf; | |
630 | int ret; | |
631 | ||
632 | skb = skb_peek(&rx_edma->rx_fifo); | |
633 | if (!skb) | |
634 | return false; | |
635 | ||
636 | bf = SKB_CB_ATHBUF(skb); | |
637 | BUG_ON(!bf); | |
638 | ||
ce9426d1 | 639 | dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr, |
b5c80475 FF |
640 | common->rx_bufsize, DMA_FROM_DEVICE); |
641 | ||
3a2923e8 | 642 | ret = ath9k_hw_process_rxdesc_edma(ah, rs, skb->data); |
ce9426d1 ML |
643 | if (ret == -EINPROGRESS) { |
644 | /*let device gain the buffer again*/ | |
645 | dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, | |
646 | common->rx_bufsize, DMA_FROM_DEVICE); | |
b5c80475 | 647 | return false; |
ce9426d1 | 648 | } |
b5c80475 FF |
649 | |
650 | __skb_unlink(skb, &rx_edma->rx_fifo); | |
651 | if (ret == -EINVAL) { | |
652 | /* corrupt descriptor, skip this one and the following one */ | |
653 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
654 | ath_rx_edma_buf_link(sc, qtype); | |
b5c80475 | 655 | |
3a2923e8 FF |
656 | skb = skb_peek(&rx_edma->rx_fifo); |
657 | if (skb) { | |
658 | bf = SKB_CB_ATHBUF(skb); | |
659 | BUG_ON(!bf); | |
660 | ||
661 | __skb_unlink(skb, &rx_edma->rx_fifo); | |
662 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
663 | ath_rx_edma_buf_link(sc, qtype); | |
3a2923e8 | 664 | } |
6bb51c70 TH |
665 | |
666 | bf = NULL; | |
b5c80475 | 667 | } |
b5c80475 | 668 | |
3a2923e8 | 669 | *dest = bf; |
b5c80475 FF |
670 | return true; |
671 | } | |
f078f209 | 672 | |
b5c80475 FF |
673 | static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc, |
674 | struct ath_rx_status *rs, | |
675 | enum ath9k_rx_qtype qtype) | |
676 | { | |
3a2923e8 | 677 | struct ath_buf *bf = NULL; |
b5c80475 | 678 | |
3a2923e8 FF |
679 | while (ath_edma_get_buffers(sc, qtype, rs, &bf)) { |
680 | if (!bf) | |
681 | continue; | |
b5c80475 | 682 | |
3a2923e8 FF |
683 | return bf; |
684 | } | |
685 | return NULL; | |
b5c80475 FF |
686 | } |
687 | ||
688 | static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc, | |
689 | struct ath_rx_status *rs) | |
690 | { | |
691 | struct ath_hw *ah = sc->sc_ah; | |
692 | struct ath_common *common = ath9k_hw_common(ah); | |
f078f209 | 693 | struct ath_desc *ds; |
b5c80475 FF |
694 | struct ath_buf *bf; |
695 | int ret; | |
696 | ||
697 | if (list_empty(&sc->rx.rxbuf)) { | |
698 | sc->rx.rxlink = NULL; | |
699 | return NULL; | |
700 | } | |
701 | ||
702 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); | |
703 | ds = bf->bf_desc; | |
704 | ||
705 | /* | |
706 | * Must provide the virtual address of the current | |
707 | * descriptor, the physical address, and the virtual | |
708 | * address of the next descriptor in the h/w chain. | |
709 | * This allows the HAL to look ahead to see if the | |
710 | * hardware is done with a descriptor by checking the | |
711 | * done bit in the following descriptor and the address | |
712 | * of the current descriptor the DMA engine is working | |
713 | * on. All this is necessary because of our use of | |
714 | * a self-linked list to avoid rx overruns. | |
715 | */ | |
3de21116 | 716 | ret = ath9k_hw_rxprocdesc(ah, ds, rs); |
b5c80475 FF |
717 | if (ret == -EINPROGRESS) { |
718 | struct ath_rx_status trs; | |
719 | struct ath_buf *tbf; | |
720 | struct ath_desc *tds; | |
721 | ||
722 | memset(&trs, 0, sizeof(trs)); | |
723 | if (list_is_last(&bf->list, &sc->rx.rxbuf)) { | |
724 | sc->rx.rxlink = NULL; | |
725 | return NULL; | |
726 | } | |
727 | ||
728 | tbf = list_entry(bf->list.next, struct ath_buf, list); | |
729 | ||
730 | /* | |
731 | * On some hardware the descriptor status words could | |
732 | * get corrupted, including the done bit. Because of | |
733 | * this, check if the next descriptor's done bit is | |
734 | * set or not. | |
735 | * | |
736 | * If the next descriptor's done bit is set, the current | |
737 | * descriptor has been corrupted. Force s/w to discard | |
738 | * this descriptor and continue... | |
739 | */ | |
740 | ||
741 | tds = tbf->bf_desc; | |
3de21116 | 742 | ret = ath9k_hw_rxprocdesc(ah, tds, &trs); |
b5c80475 FF |
743 | if (ret == -EINPROGRESS) |
744 | return NULL; | |
745 | } | |
746 | ||
747 | if (!bf->bf_mpdu) | |
748 | return bf; | |
749 | ||
750 | /* | |
751 | * Synchronize the DMA transfer with CPU before | |
752 | * 1. accessing the frame | |
753 | * 2. requeueing the same buffer to h/w | |
754 | */ | |
ce9426d1 | 755 | dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr, |
b5c80475 FF |
756 | common->rx_bufsize, |
757 | DMA_FROM_DEVICE); | |
758 | ||
759 | return bf; | |
760 | } | |
761 | ||
d435700f S |
762 | /* Assumes you've already done the endian to CPU conversion */ |
763 | static bool ath9k_rx_accept(struct ath_common *common, | |
9f167f64 | 764 | struct ieee80211_hdr *hdr, |
d435700f S |
765 | struct ieee80211_rx_status *rxs, |
766 | struct ath_rx_status *rx_stats, | |
767 | bool *decrypt_error) | |
768 | { | |
ec205999 | 769 | struct ath_softc *sc = (struct ath_softc *) common->priv; |
66760eac | 770 | bool is_mc, is_valid_tkip, strip_mic, mic_error; |
d435700f | 771 | struct ath_hw *ah = common->ah; |
d435700f | 772 | __le16 fc; |
b7b1b512 | 773 | u8 rx_status_len = ah->caps.rx_status_len; |
d435700f | 774 | |
d435700f S |
775 | fc = hdr->frame_control; |
776 | ||
66760eac FF |
777 | is_mc = !!is_multicast_ether_addr(hdr->addr1); |
778 | is_valid_tkip = rx_stats->rs_keyix != ATH9K_RXKEYIX_INVALID && | |
779 | test_bit(rx_stats->rs_keyix, common->tkip_keymap); | |
152e585d | 780 | strip_mic = is_valid_tkip && ieee80211_is_data(fc) && |
2a5783b8 | 781 | ieee80211_has_protected(fc) && |
152e585d | 782 | !(rx_stats->rs_status & |
846d9363 FF |
783 | (ATH9K_RXERR_DECRYPT | ATH9K_RXERR_CRC | ATH9K_RXERR_MIC | |
784 | ATH9K_RXERR_KEYMISS)); | |
66760eac | 785 | |
f88373fa FF |
786 | /* |
787 | * Key miss events are only relevant for pairwise keys where the | |
788 | * descriptor does contain a valid key index. This has been observed | |
789 | * mostly with CCMP encryption. | |
790 | */ | |
bed3d9c0 FF |
791 | if (rx_stats->rs_keyix == ATH9K_RXKEYIX_INVALID || |
792 | !test_bit(rx_stats->rs_keyix, common->ccmp_keymap)) | |
f88373fa FF |
793 | rx_stats->rs_status &= ~ATH9K_RXERR_KEYMISS; |
794 | ||
15072189 BG |
795 | if (!rx_stats->rs_datalen) { |
796 | RX_STAT_INC(rx_len_err); | |
d435700f | 797 | return false; |
15072189 BG |
798 | } |
799 | ||
d435700f S |
800 | /* |
801 | * rs_status follows rs_datalen so if rs_datalen is too large | |
802 | * we can take a hint that hardware corrupted it, so ignore | |
803 | * those frames. | |
804 | */ | |
15072189 BG |
805 | if (rx_stats->rs_datalen > (common->rx_bufsize - rx_status_len)) { |
806 | RX_STAT_INC(rx_len_err); | |
d435700f | 807 | return false; |
15072189 | 808 | } |
d435700f | 809 | |
0d95521e | 810 | /* Only use error bits from the last fragment */ |
d435700f | 811 | if (rx_stats->rs_more) |
0d95521e | 812 | return true; |
d435700f | 813 | |
66760eac FF |
814 | mic_error = is_valid_tkip && !ieee80211_is_ctl(fc) && |
815 | !ieee80211_has_morefrags(fc) && | |
816 | !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) && | |
817 | (rx_stats->rs_status & ATH9K_RXERR_MIC); | |
818 | ||
d435700f S |
819 | /* |
820 | * The rx_stats->rs_status will not be set until the end of the | |
821 | * chained descriptors so it can be ignored if rs_more is set. The | |
822 | * rs_more will be false at the last element of the chained | |
823 | * descriptors. | |
824 | */ | |
825 | if (rx_stats->rs_status != 0) { | |
846d9363 FF |
826 | u8 status_mask; |
827 | ||
66760eac | 828 | if (rx_stats->rs_status & ATH9K_RXERR_CRC) { |
d435700f | 829 | rxs->flag |= RX_FLAG_FAILED_FCS_CRC; |
66760eac FF |
830 | mic_error = false; |
831 | } | |
d435700f S |
832 | if (rx_stats->rs_status & ATH9K_RXERR_PHY) |
833 | return false; | |
834 | ||
846d9363 FF |
835 | if ((rx_stats->rs_status & ATH9K_RXERR_DECRYPT) || |
836 | (!is_mc && (rx_stats->rs_status & ATH9K_RXERR_KEYMISS))) { | |
d435700f | 837 | *decrypt_error = true; |
66760eac | 838 | mic_error = false; |
d435700f | 839 | } |
66760eac | 840 | |
d435700f S |
841 | /* |
842 | * Reject error frames with the exception of | |
843 | * decryption and MIC failures. For monitor mode, | |
844 | * we also ignore the CRC error. | |
845 | */ | |
846d9363 FF |
846 | status_mask = ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC | |
847 | ATH9K_RXERR_KEYMISS; | |
848 | ||
ec205999 | 849 | if (ah->is_monitoring && (sc->rx.rxfilter & FIF_FCSFAIL)) |
846d9363 FF |
850 | status_mask |= ATH9K_RXERR_CRC; |
851 | ||
852 | if (rx_stats->rs_status & ~status_mask) | |
853 | return false; | |
d435700f | 854 | } |
66760eac FF |
855 | |
856 | /* | |
857 | * For unicast frames the MIC error bit can have false positives, | |
858 | * so all MIC error reports need to be validated in software. | |
859 | * False negatives are not common, so skip software verification | |
860 | * if the hardware considers the MIC valid. | |
861 | */ | |
862 | if (strip_mic) | |
863 | rxs->flag |= RX_FLAG_MMIC_STRIPPED; | |
864 | else if (is_mc && mic_error) | |
865 | rxs->flag |= RX_FLAG_MMIC_ERROR; | |
866 | ||
d435700f S |
867 | return true; |
868 | } | |
869 | ||
870 | static int ath9k_process_rate(struct ath_common *common, | |
871 | struct ieee80211_hw *hw, | |
872 | struct ath_rx_status *rx_stats, | |
9f167f64 | 873 | struct ieee80211_rx_status *rxs) |
d435700f S |
874 | { |
875 | struct ieee80211_supported_band *sband; | |
876 | enum ieee80211_band band; | |
877 | unsigned int i = 0; | |
990e08a0 | 878 | struct ath_softc __maybe_unused *sc = common->priv; |
d435700f S |
879 | |
880 | band = hw->conf.channel->band; | |
881 | sband = hw->wiphy->bands[band]; | |
882 | ||
883 | if (rx_stats->rs_rate & 0x80) { | |
884 | /* HT rate */ | |
885 | rxs->flag |= RX_FLAG_HT; | |
886 | if (rx_stats->rs_flags & ATH9K_RX_2040) | |
887 | rxs->flag |= RX_FLAG_40MHZ; | |
888 | if (rx_stats->rs_flags & ATH9K_RX_GI) | |
889 | rxs->flag |= RX_FLAG_SHORT_GI; | |
890 | rxs->rate_idx = rx_stats->rs_rate & 0x7f; | |
891 | return 0; | |
892 | } | |
893 | ||
894 | for (i = 0; i < sband->n_bitrates; i++) { | |
895 | if (sband->bitrates[i].hw_value == rx_stats->rs_rate) { | |
896 | rxs->rate_idx = i; | |
897 | return 0; | |
898 | } | |
899 | if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) { | |
900 | rxs->flag |= RX_FLAG_SHORTPRE; | |
901 | rxs->rate_idx = i; | |
902 | return 0; | |
903 | } | |
904 | } | |
905 | ||
906 | /* | |
907 | * No valid hardware bitrate found -- we should not get here | |
908 | * because hardware has already validated this frame as OK. | |
909 | */ | |
d2182b69 | 910 | ath_dbg(common, ANY, |
226afe68 JP |
911 | "unsupported hw bitrate detected 0x%02x using 1 Mbit\n", |
912 | rx_stats->rs_rate); | |
15072189 | 913 | RX_STAT_INC(rx_rate_err); |
d435700f S |
914 | return -EINVAL; |
915 | } | |
916 | ||
917 | static void ath9k_process_rssi(struct ath_common *common, | |
918 | struct ieee80211_hw *hw, | |
9f167f64 | 919 | struct ieee80211_hdr *hdr, |
d435700f S |
920 | struct ath_rx_status *rx_stats) |
921 | { | |
9ac58615 | 922 | struct ath_softc *sc = hw->priv; |
d435700f | 923 | struct ath_hw *ah = common->ah; |
9fa23e17 | 924 | int last_rssi; |
2ef16755 | 925 | int rssi = rx_stats->rs_rssi; |
d435700f | 926 | |
cf3af748 RM |
927 | if (!rx_stats->is_mybeacon || |
928 | ((ah->opmode != NL80211_IFTYPE_STATION) && | |
929 | (ah->opmode != NL80211_IFTYPE_ADHOC))) | |
9fa23e17 FF |
930 | return; |
931 | ||
9fa23e17 | 932 | if (rx_stats->rs_rssi != ATH9K_RSSI_BAD && !rx_stats->rs_moreaggr) |
9ac58615 | 933 | ATH_RSSI_LPF(sc->last_rssi, rx_stats->rs_rssi); |
d435700f | 934 | |
9ac58615 | 935 | last_rssi = sc->last_rssi; |
d435700f | 936 | if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER)) |
2ef16755 FF |
937 | rssi = ATH_EP_RND(last_rssi, ATH_RSSI_EP_MULTIPLIER); |
938 | if (rssi < 0) | |
939 | rssi = 0; | |
d435700f S |
940 | |
941 | /* Update Beacon RSSI, this is used by ANI. */ | |
2ef16755 | 942 | ah->stats.avgbrssi = rssi; |
d435700f S |
943 | } |
944 | ||
945 | /* | |
946 | * For Decrypt or Demic errors, we only mark packet status here and always push | |
947 | * up the frame up to let mac80211 handle the actual error case, be it no | |
948 | * decryption key or real decryption error. This let us keep statistics there. | |
949 | */ | |
950 | static int ath9k_rx_skb_preprocess(struct ath_common *common, | |
951 | struct ieee80211_hw *hw, | |
9f167f64 | 952 | struct ieee80211_hdr *hdr, |
d435700f S |
953 | struct ath_rx_status *rx_stats, |
954 | struct ieee80211_rx_status *rx_status, | |
955 | bool *decrypt_error) | |
956 | { | |
f749b946 FF |
957 | struct ath_hw *ah = common->ah; |
958 | ||
d435700f S |
959 | /* |
960 | * everything but the rate is checked here, the rate check is done | |
961 | * separately to avoid doing two lookups for a rate for each frame. | |
962 | */ | |
9f167f64 | 963 | if (!ath9k_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error)) |
d435700f S |
964 | return -EINVAL; |
965 | ||
0d95521e FF |
966 | /* Only use status info from the last fragment */ |
967 | if (rx_stats->rs_more) | |
968 | return 0; | |
969 | ||
9f167f64 | 970 | ath9k_process_rssi(common, hw, hdr, rx_stats); |
d435700f | 971 | |
9f167f64 | 972 | if (ath9k_process_rate(common, hw, rx_stats, rx_status)) |
d435700f S |
973 | return -EINVAL; |
974 | ||
d435700f S |
975 | rx_status->band = hw->conf.channel->band; |
976 | rx_status->freq = hw->conf.channel->center_freq; | |
f749b946 | 977 | rx_status->signal = ah->noise + rx_stats->rs_rssi; |
d435700f | 978 | rx_status->antenna = rx_stats->rs_antenna; |
6ebacbb7 | 979 | rx_status->flag |= RX_FLAG_MACTIME_MPDU; |
2ef16755 FF |
980 | if (rx_stats->rs_moreaggr) |
981 | rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; | |
d435700f S |
982 | |
983 | return 0; | |
984 | } | |
985 | ||
986 | static void ath9k_rx_skb_postprocess(struct ath_common *common, | |
987 | struct sk_buff *skb, | |
988 | struct ath_rx_status *rx_stats, | |
989 | struct ieee80211_rx_status *rxs, | |
990 | bool decrypt_error) | |
991 | { | |
992 | struct ath_hw *ah = common->ah; | |
993 | struct ieee80211_hdr *hdr; | |
994 | int hdrlen, padpos, padsize; | |
995 | u8 keyix; | |
996 | __le16 fc; | |
997 | ||
998 | /* see if any padding is done by the hw and remove it */ | |
999 | hdr = (struct ieee80211_hdr *) skb->data; | |
1000 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); | |
1001 | fc = hdr->frame_control; | |
1002 | padpos = ath9k_cmn_padpos(hdr->frame_control); | |
1003 | ||
1004 | /* The MAC header is padded to have 32-bit boundary if the | |
1005 | * packet payload is non-zero. The general calculation for | |
1006 | * padsize would take into account odd header lengths: | |
1007 | * padsize = (4 - padpos % 4) % 4; However, since only | |
1008 | * even-length headers are used, padding can only be 0 or 2 | |
1009 | * bytes and we can optimize this a bit. In addition, we must | |
1010 | * not try to remove padding from short control frames that do | |
1011 | * not have payload. */ | |
1012 | padsize = padpos & 3; | |
1013 | if (padsize && skb->len>=padpos+padsize+FCS_LEN) { | |
1014 | memmove(skb->data + padsize, skb->data, padpos); | |
1015 | skb_pull(skb, padsize); | |
1016 | } | |
1017 | ||
1018 | keyix = rx_stats->rs_keyix; | |
1019 | ||
1020 | if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error && | |
1021 | ieee80211_has_protected(fc)) { | |
1022 | rxs->flag |= RX_FLAG_DECRYPTED; | |
1023 | } else if (ieee80211_has_protected(fc) | |
1024 | && !decrypt_error && skb->len >= hdrlen + 4) { | |
1025 | keyix = skb->data[hdrlen + 3] >> 6; | |
1026 | ||
1027 | if (test_bit(keyix, common->keymap)) | |
1028 | rxs->flag |= RX_FLAG_DECRYPTED; | |
1029 | } | |
1030 | if (ah->sw_mgmt_crypto && | |
1031 | (rxs->flag & RX_FLAG_DECRYPTED) && | |
1032 | ieee80211_is_mgmt(fc)) | |
1033 | /* Use software decrypt for management frames. */ | |
1034 | rxs->flag &= ~RX_FLAG_DECRYPTED; | |
1035 | } | |
b5c80475 FF |
1036 | |
1037 | int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp) | |
1038 | { | |
1039 | struct ath_buf *bf; | |
0d95521e | 1040 | struct sk_buff *skb = NULL, *requeue_skb, *hdr_skb; |
5ca42627 | 1041 | struct ieee80211_rx_status *rxs; |
cbe61d8a | 1042 | struct ath_hw *ah = sc->sc_ah; |
27c51f1a | 1043 | struct ath_common *common = ath9k_hw_common(ah); |
7545daf4 | 1044 | struct ieee80211_hw *hw = sc->hw; |
be0418ad | 1045 | struct ieee80211_hdr *hdr; |
c9b14170 | 1046 | int retval; |
29bffa96 | 1047 | struct ath_rx_status rs; |
b5c80475 FF |
1048 | enum ath9k_rx_qtype qtype; |
1049 | bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); | |
1050 | int dma_type; | |
5c6dd921 | 1051 | u8 rx_status_len = ah->caps.rx_status_len; |
a6d2055b FF |
1052 | u64 tsf = 0; |
1053 | u32 tsf_lower = 0; | |
8ab2cd09 | 1054 | unsigned long flags; |
be0418ad | 1055 | |
b5c80475 | 1056 | if (edma) |
b5c80475 | 1057 | dma_type = DMA_BIDIRECTIONAL; |
56824223 ML |
1058 | else |
1059 | dma_type = DMA_FROM_DEVICE; | |
b5c80475 FF |
1060 | |
1061 | qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP; | |
b77f483f | 1062 | spin_lock_bh(&sc->rx.rxbuflock); |
f078f209 | 1063 | |
a6d2055b FF |
1064 | tsf = ath9k_hw_gettsf64(ah); |
1065 | tsf_lower = tsf & 0xffffffff; | |
1066 | ||
f078f209 | 1067 | do { |
e1352fde | 1068 | bool decrypt_error = false; |
f078f209 | 1069 | /* If handling rx interrupt and flush is in progress => exit */ |
781b14a3 | 1070 | if (test_bit(SC_OP_RXFLUSH, &sc->sc_flags) && (flush == 0)) |
f078f209 LR |
1071 | break; |
1072 | ||
29bffa96 | 1073 | memset(&rs, 0, sizeof(rs)); |
b5c80475 FF |
1074 | if (edma) |
1075 | bf = ath_edma_get_next_rx_buf(sc, &rs, qtype); | |
1076 | else | |
1077 | bf = ath_get_next_rx_buf(sc, &rs); | |
f078f209 | 1078 | |
b5c80475 FF |
1079 | if (!bf) |
1080 | break; | |
f078f209 | 1081 | |
f078f209 | 1082 | skb = bf->bf_mpdu; |
be0418ad | 1083 | if (!skb) |
f078f209 | 1084 | continue; |
f078f209 | 1085 | |
0d95521e FF |
1086 | /* |
1087 | * Take frame header from the first fragment and RX status from | |
1088 | * the last one. | |
1089 | */ | |
1090 | if (sc->rx.frag) | |
1091 | hdr_skb = sc->rx.frag; | |
1092 | else | |
1093 | hdr_skb = skb; | |
1094 | ||
1095 | hdr = (struct ieee80211_hdr *) (hdr_skb->data + rx_status_len); | |
1096 | rxs = IEEE80211_SKB_RXCB(hdr_skb); | |
15072189 BG |
1097 | if (ieee80211_is_beacon(hdr->frame_control)) { |
1098 | RX_STAT_INC(rx_beacons); | |
1099 | if (!is_zero_ether_addr(common->curbssid) && | |
2e42e474 | 1100 | ether_addr_equal(hdr->addr3, common->curbssid)) |
15072189 BG |
1101 | rs.is_mybeacon = true; |
1102 | else | |
1103 | rs.is_mybeacon = false; | |
1104 | } | |
cf3af748 RM |
1105 | else |
1106 | rs.is_mybeacon = false; | |
5ca42627 | 1107 | |
6995fb80 | 1108 | sc->rx.num_pkts++; |
29bffa96 | 1109 | ath_debug_stat_rx(sc, &rs); |
1395d3f0 | 1110 | |
f078f209 | 1111 | /* |
be0418ad S |
1112 | * If we're asked to flush receive queue, directly |
1113 | * chain it back at the queue without processing it. | |
f078f209 | 1114 | */ |
781b14a3 | 1115 | if (test_bit(SC_OP_RXFLUSH, &sc->sc_flags)) { |
15072189 | 1116 | RX_STAT_INC(rx_drop_rxflush); |
0d95521e | 1117 | goto requeue_drop_frag; |
15072189 | 1118 | } |
f078f209 | 1119 | |
ffb1c56a AN |
1120 | memset(rxs, 0, sizeof(struct ieee80211_rx_status)); |
1121 | ||
a6d2055b FF |
1122 | rxs->mactime = (tsf & ~0xffffffffULL) | rs.rs_tstamp; |
1123 | if (rs.rs_tstamp > tsf_lower && | |
1124 | unlikely(rs.rs_tstamp - tsf_lower > 0x10000000)) | |
1125 | rxs->mactime -= 0x100000000ULL; | |
1126 | ||
1127 | if (rs.rs_tstamp < tsf_lower && | |
1128 | unlikely(tsf_lower - rs.rs_tstamp > 0x10000000)) | |
1129 | rxs->mactime += 0x100000000ULL; | |
1130 | ||
83c76570 ZK |
1131 | retval = ath9k_rx_skb_preprocess(common, hw, hdr, &rs, |
1132 | rxs, &decrypt_error); | |
1133 | if (retval) | |
1134 | goto requeue_drop_frag; | |
1135 | ||
01e18918 RM |
1136 | if (rs.is_mybeacon) { |
1137 | sc->hw_busy_count = 0; | |
1138 | ath_start_rx_poll(sc, 3); | |
1139 | } | |
cb71d9ba LR |
1140 | /* Ensure we always have an skb to requeue once we are done |
1141 | * processing the current buffer's skb */ | |
cc861f74 | 1142 | requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC); |
cb71d9ba LR |
1143 | |
1144 | /* If there is no memory we ignore the current RX'd frame, | |
1145 | * tell hardware it can give us a new frame using the old | |
b77f483f | 1146 | * skb and put it at the tail of the sc->rx.rxbuf list for |
cb71d9ba | 1147 | * processing. */ |
15072189 BG |
1148 | if (!requeue_skb) { |
1149 | RX_STAT_INC(rx_oom_err); | |
0d95521e | 1150 | goto requeue_drop_frag; |
15072189 | 1151 | } |
f078f209 | 1152 | |
9bf9fca8 | 1153 | /* Unmap the frame */ |
7da3c55c | 1154 | dma_unmap_single(sc->dev, bf->bf_buf_addr, |
cc861f74 | 1155 | common->rx_bufsize, |
b5c80475 | 1156 | dma_type); |
f078f209 | 1157 | |
b5c80475 FF |
1158 | skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len); |
1159 | if (ah->caps.rx_status_len) | |
1160 | skb_pull(skb, ah->caps.rx_status_len); | |
be0418ad | 1161 | |
0d95521e FF |
1162 | if (!rs.rs_more) |
1163 | ath9k_rx_skb_postprocess(common, hdr_skb, &rs, | |
1164 | rxs, decrypt_error); | |
be0418ad | 1165 | |
cb71d9ba LR |
1166 | /* We will now give hardware our shiny new allocated skb */ |
1167 | bf->bf_mpdu = requeue_skb; | |
7da3c55c | 1168 | bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data, |
cc861f74 | 1169 | common->rx_bufsize, |
b5c80475 | 1170 | dma_type); |
7da3c55c | 1171 | if (unlikely(dma_mapping_error(sc->dev, |
f8316df1 LR |
1172 | bf->bf_buf_addr))) { |
1173 | dev_kfree_skb_any(requeue_skb); | |
1174 | bf->bf_mpdu = NULL; | |
6cf9e995 | 1175 | bf->bf_buf_addr = 0; |
3800276a | 1176 | ath_err(common, "dma_mapping_error() on RX\n"); |
7545daf4 | 1177 | ieee80211_rx(hw, skb); |
f8316df1 LR |
1178 | break; |
1179 | } | |
f078f209 | 1180 | |
0d95521e | 1181 | if (rs.rs_more) { |
15072189 | 1182 | RX_STAT_INC(rx_frags); |
0d95521e FF |
1183 | /* |
1184 | * rs_more indicates chained descriptors which can be | |
1185 | * used to link buffers together for a sort of | |
1186 | * scatter-gather operation. | |
1187 | */ | |
1188 | if (sc->rx.frag) { | |
1189 | /* too many fragments - cannot handle frame */ | |
1190 | dev_kfree_skb_any(sc->rx.frag); | |
1191 | dev_kfree_skb_any(skb); | |
15072189 | 1192 | RX_STAT_INC(rx_too_many_frags_err); |
0d95521e FF |
1193 | skb = NULL; |
1194 | } | |
1195 | sc->rx.frag = skb; | |
1196 | goto requeue; | |
1197 | } | |
1198 | ||
1199 | if (sc->rx.frag) { | |
1200 | int space = skb->len - skb_tailroom(hdr_skb); | |
1201 | ||
0d95521e FF |
1202 | if (pskb_expand_head(hdr_skb, 0, space, GFP_ATOMIC) < 0) { |
1203 | dev_kfree_skb(skb); | |
15072189 | 1204 | RX_STAT_INC(rx_oom_err); |
0d95521e FF |
1205 | goto requeue_drop_frag; |
1206 | } | |
1207 | ||
b5447ff9 ED |
1208 | sc->rx.frag = NULL; |
1209 | ||
0d95521e FF |
1210 | skb_copy_from_linear_data(skb, skb_put(hdr_skb, skb->len), |
1211 | skb->len); | |
1212 | dev_kfree_skb_any(skb); | |
1213 | skb = hdr_skb; | |
1214 | } | |
1215 | ||
eb840a80 MSS |
1216 | |
1217 | if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) { | |
1218 | ||
1219 | /* | |
1220 | * change the default rx antenna if rx diversity | |
1221 | * chooses the other antenna 3 times in a row. | |
1222 | */ | |
1223 | if (sc->rx.defant != rs.rs_antenna) { | |
1224 | if (++sc->rx.rxotherant >= 3) | |
1225 | ath_setdefantenna(sc, rs.rs_antenna); | |
1226 | } else { | |
1227 | sc->rx.rxotherant = 0; | |
1228 | } | |
1229 | ||
f078f209 | 1230 | } |
3cbb5dd7 | 1231 | |
66760eac FF |
1232 | if (rxs->flag & RX_FLAG_MMIC_STRIPPED) |
1233 | skb_trim(skb, skb->len - 8); | |
1234 | ||
8ab2cd09 | 1235 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
aaef24b4 | 1236 | if ((sc->ps_flags & (PS_WAIT_FOR_BEACON | |
f73c604c RM |
1237 | PS_WAIT_FOR_CAB | |
1238 | PS_WAIT_FOR_PSPOLL_DATA)) || | |
1239 | ath9k_check_auto_sleep(sc)) | |
1240 | ath_rx_ps(sc, skb, rs.is_mybeacon); | |
8ab2cd09 | 1241 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
cc65965c | 1242 | |
43c35284 | 1243 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx == 3) |
102885a5 VT |
1244 | ath_ant_comb_scan(sc, &rs); |
1245 | ||
7545daf4 | 1246 | ieee80211_rx(hw, skb); |
cc65965c | 1247 | |
0d95521e FF |
1248 | requeue_drop_frag: |
1249 | if (sc->rx.frag) { | |
1250 | dev_kfree_skb_any(sc->rx.frag); | |
1251 | sc->rx.frag = NULL; | |
1252 | } | |
cb71d9ba | 1253 | requeue: |
b5c80475 FF |
1254 | if (edma) { |
1255 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
1256 | ath_rx_edma_buf_link(sc, qtype); | |
1257 | } else { | |
1258 | list_move_tail(&bf->list, &sc->rx.rxbuf); | |
1259 | ath_rx_buf_link(sc, bf); | |
3483288c FF |
1260 | if (!flush) |
1261 | ath9k_hw_rxena(ah); | |
b5c80475 | 1262 | } |
be0418ad S |
1263 | } while (1); |
1264 | ||
b77f483f | 1265 | spin_unlock_bh(&sc->rx.rxbuflock); |
f078f209 | 1266 | |
29ab0b36 RM |
1267 | if (!(ah->imask & ATH9K_INT_RXEOL)) { |
1268 | ah->imask |= (ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
72d874c6 | 1269 | ath9k_hw_set_interrupts(ah); |
29ab0b36 RM |
1270 | } |
1271 | ||
f078f209 | 1272 | return 0; |
f078f209 | 1273 | } |