Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
b7f080cf | 17 | #include <linux/dma-mapping.h> |
e93d083f | 18 | #include <linux/relay.h> |
394cf0a1 | 19 | #include "ath9k.h" |
b622a720 | 20 | #include "ar9003_mac.h" |
f078f209 | 21 | |
b5c80475 FF |
22 | #define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb)) |
23 | ||
ededf1f8 VT |
24 | static inline bool ath9k_check_auto_sleep(struct ath_softc *sc) |
25 | { | |
26 | return sc->ps_enabled && | |
27 | (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP); | |
28 | } | |
29 | ||
f078f209 LR |
30 | /* |
31 | * Setup and link descriptors. | |
32 | * | |
33 | * 11N: we can no longer afford to self link the last descriptor. | |
34 | * MAC acknowledges BA status as long as it copies frames to host | |
35 | * buffer (or rx fifo). This can incorrectly acknowledge packets | |
36 | * to a sender if last desc is self-linked. | |
f078f209 | 37 | */ |
f078f209 LR |
38 | static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf) |
39 | { | |
cbe61d8a | 40 | struct ath_hw *ah = sc->sc_ah; |
cc861f74 | 41 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 LR |
42 | struct ath_desc *ds; |
43 | struct sk_buff *skb; | |
44 | ||
f078f209 | 45 | ds = bf->bf_desc; |
be0418ad | 46 | ds->ds_link = 0; /* link to null */ |
f078f209 LR |
47 | ds->ds_data = bf->bf_buf_addr; |
48 | ||
be0418ad | 49 | /* virtual addr of the beginning of the buffer. */ |
f078f209 | 50 | skb = bf->bf_mpdu; |
9680e8a3 | 51 | BUG_ON(skb == NULL); |
f078f209 LR |
52 | ds->ds_vdata = skb->data; |
53 | ||
cc861f74 LR |
54 | /* |
55 | * setup rx descriptors. The rx_bufsize here tells the hardware | |
b4b6cda2 | 56 | * how much data it can DMA to us and that we are prepared |
cc861f74 LR |
57 | * to process |
58 | */ | |
b77f483f | 59 | ath9k_hw_setuprxdesc(ah, ds, |
cc861f74 | 60 | common->rx_bufsize, |
f078f209 LR |
61 | 0); |
62 | ||
b77f483f | 63 | if (sc->rx.rxlink == NULL) |
f078f209 LR |
64 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); |
65 | else | |
b77f483f | 66 | *sc->rx.rxlink = bf->bf_daddr; |
f078f209 | 67 | |
b77f483f | 68 | sc->rx.rxlink = &ds->ds_link; |
f078f209 LR |
69 | } |
70 | ||
e96542e5 FF |
71 | static void ath_rx_buf_relink(struct ath_softc *sc, struct ath_buf *bf) |
72 | { | |
73 | if (sc->rx.buf_hold) | |
74 | ath_rx_buf_link(sc, sc->rx.buf_hold); | |
75 | ||
76 | sc->rx.buf_hold = bf; | |
77 | } | |
78 | ||
ff37e337 S |
79 | static void ath_setdefantenna(struct ath_softc *sc, u32 antenna) |
80 | { | |
81 | /* XXX block beacon interrupts */ | |
82 | ath9k_hw_setantenna(sc->sc_ah, antenna); | |
b77f483f S |
83 | sc->rx.defant = antenna; |
84 | sc->rx.rxotherant = 0; | |
ff37e337 S |
85 | } |
86 | ||
f078f209 LR |
87 | static void ath_opmode_init(struct ath_softc *sc) |
88 | { | |
cbe61d8a | 89 | struct ath_hw *ah = sc->sc_ah; |
1510718d LR |
90 | struct ath_common *common = ath9k_hw_common(ah); |
91 | ||
f078f209 LR |
92 | u32 rfilt, mfilt[2]; |
93 | ||
94 | /* configure rx filter */ | |
95 | rfilt = ath_calcrxfilter(sc); | |
96 | ath9k_hw_setrxfilter(ah, rfilt); | |
97 | ||
98 | /* configure bssid mask */ | |
364734fa | 99 | ath_hw_setbssidmask(common); |
f078f209 LR |
100 | |
101 | /* configure operational mode */ | |
102 | ath9k_hw_setopmode(ah); | |
103 | ||
f078f209 LR |
104 | /* calculate and install multicast filter */ |
105 | mfilt[0] = mfilt[1] = ~0; | |
f078f209 | 106 | ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]); |
f078f209 LR |
107 | } |
108 | ||
b5c80475 FF |
109 | static bool ath_rx_edma_buf_link(struct ath_softc *sc, |
110 | enum ath9k_rx_qtype qtype) | |
f078f209 | 111 | { |
b5c80475 FF |
112 | struct ath_hw *ah = sc->sc_ah; |
113 | struct ath_rx_edma *rx_edma; | |
f078f209 LR |
114 | struct sk_buff *skb; |
115 | struct ath_buf *bf; | |
f078f209 | 116 | |
b5c80475 FF |
117 | rx_edma = &sc->rx.rx_edma[qtype]; |
118 | if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize) | |
119 | return false; | |
f078f209 | 120 | |
b5c80475 FF |
121 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); |
122 | list_del_init(&bf->list); | |
f078f209 | 123 | |
b5c80475 FF |
124 | skb = bf->bf_mpdu; |
125 | ||
b5c80475 FF |
126 | memset(skb->data, 0, ah->caps.rx_status_len); |
127 | dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, | |
128 | ah->caps.rx_status_len, DMA_TO_DEVICE); | |
f078f209 | 129 | |
b5c80475 FF |
130 | SKB_CB_ATHBUF(skb) = bf; |
131 | ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype); | |
07236bf3 | 132 | __skb_queue_tail(&rx_edma->rx_fifo, skb); |
f078f209 | 133 | |
b5c80475 FF |
134 | return true; |
135 | } | |
136 | ||
137 | static void ath_rx_addbuffer_edma(struct ath_softc *sc, | |
7a897203 | 138 | enum ath9k_rx_qtype qtype) |
b5c80475 | 139 | { |
b5c80475 | 140 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
6a01f0c0 | 141 | struct ath_buf *bf, *tbf; |
b5c80475 | 142 | |
b5c80475 | 143 | if (list_empty(&sc->rx.rxbuf)) { |
d2182b69 | 144 | ath_dbg(common, QUEUE, "No free rx buf available\n"); |
b5c80475 | 145 | return; |
797fe5cb | 146 | } |
f078f209 | 147 | |
6a01f0c0 | 148 | list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) |
b5c80475 FF |
149 | if (!ath_rx_edma_buf_link(sc, qtype)) |
150 | break; | |
151 | ||
b5c80475 FF |
152 | } |
153 | ||
154 | static void ath_rx_remove_buffer(struct ath_softc *sc, | |
155 | enum ath9k_rx_qtype qtype) | |
156 | { | |
157 | struct ath_buf *bf; | |
158 | struct ath_rx_edma *rx_edma; | |
159 | struct sk_buff *skb; | |
160 | ||
161 | rx_edma = &sc->rx.rx_edma[qtype]; | |
162 | ||
07236bf3 | 163 | while ((skb = __skb_dequeue(&rx_edma->rx_fifo)) != NULL) { |
b5c80475 FF |
164 | bf = SKB_CB_ATHBUF(skb); |
165 | BUG_ON(!bf); | |
166 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
167 | } | |
168 | } | |
169 | ||
170 | static void ath_rx_edma_cleanup(struct ath_softc *sc) | |
171 | { | |
ba542385 MSS |
172 | struct ath_hw *ah = sc->sc_ah; |
173 | struct ath_common *common = ath9k_hw_common(ah); | |
b5c80475 FF |
174 | struct ath_buf *bf; |
175 | ||
176 | ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP); | |
177 | ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP); | |
178 | ||
797fe5cb | 179 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { |
ba542385 MSS |
180 | if (bf->bf_mpdu) { |
181 | dma_unmap_single(sc->dev, bf->bf_buf_addr, | |
182 | common->rx_bufsize, | |
183 | DMA_BIDIRECTIONAL); | |
b5c80475 | 184 | dev_kfree_skb_any(bf->bf_mpdu); |
ba542385 MSS |
185 | bf->bf_buf_addr = 0; |
186 | bf->bf_mpdu = NULL; | |
187 | } | |
b5c80475 | 188 | } |
b5c80475 FF |
189 | } |
190 | ||
191 | static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size) | |
192 | { | |
193 | skb_queue_head_init(&rx_edma->rx_fifo); | |
b5c80475 FF |
194 | rx_edma->rx_fifo_hwsize = size; |
195 | } | |
196 | ||
197 | static int ath_rx_edma_init(struct ath_softc *sc, int nbufs) | |
198 | { | |
199 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
200 | struct ath_hw *ah = sc->sc_ah; | |
201 | struct sk_buff *skb; | |
202 | struct ath_buf *bf; | |
203 | int error = 0, i; | |
204 | u32 size; | |
205 | ||
b5c80475 FF |
206 | ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - |
207 | ah->caps.rx_status_len); | |
208 | ||
209 | ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP], | |
210 | ah->caps.rx_lp_qdepth); | |
211 | ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP], | |
212 | ah->caps.rx_hp_qdepth); | |
213 | ||
214 | size = sizeof(struct ath_buf) * nbufs; | |
b81950b1 | 215 | bf = devm_kzalloc(sc->dev, size, GFP_KERNEL); |
b5c80475 FF |
216 | if (!bf) |
217 | return -ENOMEM; | |
218 | ||
219 | INIT_LIST_HEAD(&sc->rx.rxbuf); | |
b5c80475 FF |
220 | |
221 | for (i = 0; i < nbufs; i++, bf++) { | |
cc861f74 | 222 | skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL); |
b5c80475 | 223 | if (!skb) { |
797fe5cb | 224 | error = -ENOMEM; |
b5c80475 | 225 | goto rx_init_fail; |
f078f209 | 226 | } |
f078f209 | 227 | |
b5c80475 | 228 | memset(skb->data, 0, common->rx_bufsize); |
797fe5cb | 229 | bf->bf_mpdu = skb; |
b5c80475 | 230 | |
797fe5cb | 231 | bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, |
cc861f74 | 232 | common->rx_bufsize, |
b5c80475 | 233 | DMA_BIDIRECTIONAL); |
797fe5cb | 234 | if (unlikely(dma_mapping_error(sc->dev, |
b5c80475 FF |
235 | bf->bf_buf_addr))) { |
236 | dev_kfree_skb_any(skb); | |
237 | bf->bf_mpdu = NULL; | |
6cf9e995 | 238 | bf->bf_buf_addr = 0; |
3800276a | 239 | ath_err(common, |
b5c80475 FF |
240 | "dma_mapping_error() on RX init\n"); |
241 | error = -ENOMEM; | |
242 | goto rx_init_fail; | |
243 | } | |
244 | ||
245 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
246 | } | |
247 | ||
248 | return 0; | |
249 | ||
250 | rx_init_fail: | |
251 | ath_rx_edma_cleanup(sc); | |
252 | return error; | |
253 | } | |
254 | ||
255 | static void ath_edma_start_recv(struct ath_softc *sc) | |
256 | { | |
b5c80475 | 257 | ath9k_hw_rxena(sc->sc_ah); |
7a897203 SM |
258 | ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP); |
259 | ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP); | |
b5c80475 | 260 | ath_opmode_init(sc); |
4cb54fa3 | 261 | ath9k_hw_startpcureceive(sc->sc_ah, !!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)); |
b5c80475 FF |
262 | } |
263 | ||
264 | static void ath_edma_stop_recv(struct ath_softc *sc) | |
265 | { | |
b5c80475 FF |
266 | ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP); |
267 | ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP); | |
b5c80475 FF |
268 | } |
269 | ||
270 | int ath_rx_init(struct ath_softc *sc, int nbufs) | |
271 | { | |
272 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
273 | struct sk_buff *skb; | |
274 | struct ath_buf *bf; | |
275 | int error = 0; | |
276 | ||
4bdd1e97 | 277 | spin_lock_init(&sc->sc_pcu_lock); |
b5c80475 | 278 | |
0d95521e FF |
279 | common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 + |
280 | sc->sc_ah->caps.rx_status_len; | |
281 | ||
e87f3d53 | 282 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
b5c80475 | 283 | return ath_rx_edma_init(sc, nbufs); |
b5c80475 | 284 | |
e87f3d53 SM |
285 | ath_dbg(common, CONFIG, "cachelsz %u rxbufsize %u\n", |
286 | common->cachelsz, common->rx_bufsize); | |
b5c80475 | 287 | |
e87f3d53 SM |
288 | /* Initialize rx descriptors */ |
289 | ||
290 | error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf, | |
291 | "rx", nbufs, 1, 0); | |
292 | if (error != 0) { | |
293 | ath_err(common, | |
294 | "failed to allocate rx descriptors: %d\n", | |
295 | error); | |
296 | goto err; | |
297 | } | |
298 | ||
299 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { | |
300 | skb = ath_rxbuf_alloc(common, common->rx_bufsize, | |
301 | GFP_KERNEL); | |
302 | if (skb == NULL) { | |
303 | error = -ENOMEM; | |
797fe5cb S |
304 | goto err; |
305 | } | |
b5c80475 | 306 | |
e87f3d53 SM |
307 | bf->bf_mpdu = skb; |
308 | bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, | |
309 | common->rx_bufsize, | |
310 | DMA_FROM_DEVICE); | |
311 | if (unlikely(dma_mapping_error(sc->dev, | |
312 | bf->bf_buf_addr))) { | |
313 | dev_kfree_skb_any(skb); | |
314 | bf->bf_mpdu = NULL; | |
315 | bf->bf_buf_addr = 0; | |
316 | ath_err(common, | |
317 | "dma_mapping_error() on RX init\n"); | |
318 | error = -ENOMEM; | |
319 | goto err; | |
b5c80475 | 320 | } |
797fe5cb | 321 | } |
e87f3d53 | 322 | sc->rx.rxlink = NULL; |
797fe5cb | 323 | err: |
f078f209 LR |
324 | if (error) |
325 | ath_rx_cleanup(sc); | |
326 | ||
327 | return error; | |
328 | } | |
329 | ||
f078f209 LR |
330 | void ath_rx_cleanup(struct ath_softc *sc) |
331 | { | |
cc861f74 LR |
332 | struct ath_hw *ah = sc->sc_ah; |
333 | struct ath_common *common = ath9k_hw_common(ah); | |
f078f209 LR |
334 | struct sk_buff *skb; |
335 | struct ath_buf *bf; | |
336 | ||
b5c80475 FF |
337 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
338 | ath_rx_edma_cleanup(sc); | |
339 | return; | |
e87f3d53 SM |
340 | } |
341 | ||
342 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { | |
343 | skb = bf->bf_mpdu; | |
344 | if (skb) { | |
345 | dma_unmap_single(sc->dev, bf->bf_buf_addr, | |
346 | common->rx_bufsize, | |
347 | DMA_FROM_DEVICE); | |
348 | dev_kfree_skb(skb); | |
349 | bf->bf_buf_addr = 0; | |
350 | bf->bf_mpdu = NULL; | |
051b9191 | 351 | } |
b5c80475 | 352 | } |
f078f209 LR |
353 | } |
354 | ||
355 | /* | |
356 | * Calculate the receive filter according to the | |
357 | * operating mode and state: | |
358 | * | |
359 | * o always accept unicast, broadcast, and multicast traffic | |
360 | * o maintain current state of phy error reception (the hal | |
361 | * may enable phy error frames for noise immunity work) | |
362 | * o probe request frames are accepted only when operating in | |
363 | * hostap, adhoc, or monitor modes | |
364 | * o enable promiscuous mode according to the interface state | |
365 | * o accept beacons: | |
366 | * - when operating in adhoc mode so the 802.11 layer creates | |
367 | * node table entries for peers, | |
368 | * - when operating in station mode for collecting rssi data when | |
369 | * the station is otherwise quiet, or | |
370 | * - when operating as a repeater so we see repeater-sta beacons | |
371 | * - when scanning | |
372 | */ | |
373 | ||
374 | u32 ath_calcrxfilter(struct ath_softc *sc) | |
375 | { | |
f078f209 LR |
376 | u32 rfilt; |
377 | ||
ac06697c | 378 | rfilt = ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST |
f078f209 LR |
379 | | ATH9K_RX_FILTER_MCAST; |
380 | ||
73e4937d ZK |
381 | /* if operating on a DFS channel, enable radar pulse detection */ |
382 | if (sc->hw->conf.radar_enabled) | |
383 | rfilt |= ATH9K_RX_FILTER_PHYRADAR | ATH9K_RX_FILTER_PHYERR; | |
384 | ||
9c1d8e4a | 385 | if (sc->rx.rxfilter & FIF_PROBE_REQ) |
f078f209 LR |
386 | rfilt |= ATH9K_RX_FILTER_PROBEREQ; |
387 | ||
217ba9da JM |
388 | /* |
389 | * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station | |
390 | * mode interface or when in monitor mode. AP mode does not need this | |
391 | * since it receives all in-BSS frames anyway. | |
392 | */ | |
2e286947 | 393 | if (sc->sc_ah->is_monitoring) |
f078f209 | 394 | rfilt |= ATH9K_RX_FILTER_PROM; |
f078f209 | 395 | |
d42c6b71 S |
396 | if (sc->rx.rxfilter & FIF_CONTROL) |
397 | rfilt |= ATH9K_RX_FILTER_CONTROL; | |
398 | ||
dbaaa147 | 399 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) && |
cfda6695 | 400 | (sc->nvifs <= 1) && |
dbaaa147 VT |
401 | !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)) |
402 | rfilt |= ATH9K_RX_FILTER_MYBEACON; | |
403 | else | |
f078f209 LR |
404 | rfilt |= ATH9K_RX_FILTER_BEACON; |
405 | ||
264bbec8 | 406 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) || |
66afad01 | 407 | (sc->rx.rxfilter & FIF_PSPOLL)) |
dbaaa147 | 408 | rfilt |= ATH9K_RX_FILTER_PSPOLL; |
be0418ad | 409 | |
7ea310be S |
410 | if (conf_is_ht(&sc->hw->conf)) |
411 | rfilt |= ATH9K_RX_FILTER_COMP_BAR; | |
412 | ||
7545daf4 | 413 | if (sc->nvifs > 1 || (sc->rx.rxfilter & FIF_OTHER_BSS)) { |
a549459c TW |
414 | /* This is needed for older chips */ |
415 | if (sc->sc_ah->hw_version.macVersion <= AR_SREV_VERSION_9160) | |
5eb6ba83 | 416 | rfilt |= ATH9K_RX_FILTER_PROM; |
b93bce2a JM |
417 | rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL; |
418 | } | |
419 | ||
b3d7aa43 GJ |
420 | if (AR_SREV_9550(sc->sc_ah)) |
421 | rfilt |= ATH9K_RX_FILTER_4ADDRESS; | |
422 | ||
f078f209 | 423 | return rfilt; |
7dcfdcd9 | 424 | |
f078f209 LR |
425 | } |
426 | ||
f078f209 LR |
427 | int ath_startrecv(struct ath_softc *sc) |
428 | { | |
cbe61d8a | 429 | struct ath_hw *ah = sc->sc_ah; |
f078f209 LR |
430 | struct ath_buf *bf, *tbf; |
431 | ||
b5c80475 FF |
432 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
433 | ath_edma_start_recv(sc); | |
434 | return 0; | |
435 | } | |
436 | ||
b77f483f | 437 | if (list_empty(&sc->rx.rxbuf)) |
f078f209 LR |
438 | goto start_recv; |
439 | ||
e96542e5 | 440 | sc->rx.buf_hold = NULL; |
b77f483f S |
441 | sc->rx.rxlink = NULL; |
442 | list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) { | |
f078f209 LR |
443 | ath_rx_buf_link(sc, bf); |
444 | } | |
445 | ||
446 | /* We could have deleted elements so the list may be empty now */ | |
b77f483f | 447 | if (list_empty(&sc->rx.rxbuf)) |
f078f209 LR |
448 | goto start_recv; |
449 | ||
b77f483f | 450 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); |
f078f209 | 451 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); |
be0418ad | 452 | ath9k_hw_rxena(ah); |
f078f209 LR |
453 | |
454 | start_recv: | |
be0418ad | 455 | ath_opmode_init(sc); |
4cb54fa3 | 456 | ath9k_hw_startpcureceive(ah, !!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)); |
be0418ad | 457 | |
f078f209 LR |
458 | return 0; |
459 | } | |
460 | ||
4b883f02 FF |
461 | static void ath_flushrecv(struct ath_softc *sc) |
462 | { | |
463 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
464 | ath_rx_tasklet(sc, 1, true); | |
465 | ath_rx_tasklet(sc, 1, false); | |
466 | } | |
467 | ||
f078f209 LR |
468 | bool ath_stoprecv(struct ath_softc *sc) |
469 | { | |
cbe61d8a | 470 | struct ath_hw *ah = sc->sc_ah; |
5882da02 | 471 | bool stopped, reset = false; |
f078f209 | 472 | |
d47844a0 | 473 | ath9k_hw_abortpcurecv(ah); |
be0418ad | 474 | ath9k_hw_setrxfilter(ah, 0); |
5882da02 | 475 | stopped = ath9k_hw_stopdmarecv(ah, &reset); |
b5c80475 | 476 | |
4b883f02 FF |
477 | ath_flushrecv(sc); |
478 | ||
b5c80475 FF |
479 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
480 | ath_edma_stop_recv(sc); | |
481 | else | |
482 | sc->rx.rxlink = NULL; | |
be0418ad | 483 | |
d584747b RM |
484 | if (!(ah->ah_flags & AH_UNPLUGGED) && |
485 | unlikely(!stopped)) { | |
d7fd1b50 BG |
486 | ath_err(ath9k_hw_common(sc->sc_ah), |
487 | "Could not stop RX, we could be " | |
488 | "confusing the DMA engine when we start RX up\n"); | |
489 | ATH_DBG_WARN_ON_ONCE(!stopped); | |
490 | } | |
2232d31b | 491 | return stopped && !reset; |
f078f209 LR |
492 | } |
493 | ||
cc65965c JM |
494 | static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb) |
495 | { | |
496 | /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */ | |
497 | struct ieee80211_mgmt *mgmt; | |
498 | u8 *pos, *end, id, elen; | |
499 | struct ieee80211_tim_ie *tim; | |
500 | ||
501 | mgmt = (struct ieee80211_mgmt *)skb->data; | |
502 | pos = mgmt->u.beacon.variable; | |
503 | end = skb->data + skb->len; | |
504 | ||
505 | while (pos + 2 < end) { | |
506 | id = *pos++; | |
507 | elen = *pos++; | |
508 | if (pos + elen > end) | |
509 | break; | |
510 | ||
511 | if (id == WLAN_EID_TIM) { | |
512 | if (elen < sizeof(*tim)) | |
513 | break; | |
514 | tim = (struct ieee80211_tim_ie *) pos; | |
515 | if (tim->dtim_count != 0) | |
516 | break; | |
517 | return tim->bitmap_ctrl & 0x01; | |
518 | } | |
519 | ||
520 | pos += elen; | |
521 | } | |
522 | ||
523 | return false; | |
524 | } | |
525 | ||
cc65965c JM |
526 | static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb) |
527 | { | |
1510718d | 528 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
cc65965c JM |
529 | |
530 | if (skb->len < 24 + 8 + 2 + 2) | |
531 | return; | |
532 | ||
1b04b930 | 533 | sc->ps_flags &= ~PS_WAIT_FOR_BEACON; |
293dc5df | 534 | |
1b04b930 S |
535 | if (sc->ps_flags & PS_BEACON_SYNC) { |
536 | sc->ps_flags &= ~PS_BEACON_SYNC; | |
d2182b69 | 537 | ath_dbg(common, PS, |
1a6404a1 | 538 | "Reconfigure beacon timers based on synchronized timestamp\n"); |
ef4ad633 | 539 | ath9k_set_beacon(sc); |
ccdfeab6 JM |
540 | } |
541 | ||
cc65965c JM |
542 | if (ath_beacon_dtim_pending_cab(skb)) { |
543 | /* | |
544 | * Remain awake waiting for buffered broadcast/multicast | |
58f5fffd GJ |
545 | * frames. If the last broadcast/multicast frame is not |
546 | * received properly, the next beacon frame will work as | |
547 | * a backup trigger for returning into NETWORK SLEEP state, | |
548 | * so we are waiting for it as well. | |
cc65965c | 549 | */ |
d2182b69 | 550 | ath_dbg(common, PS, |
226afe68 | 551 | "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n"); |
1b04b930 | 552 | sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON; |
cc65965c JM |
553 | return; |
554 | } | |
555 | ||
1b04b930 | 556 | if (sc->ps_flags & PS_WAIT_FOR_CAB) { |
cc65965c JM |
557 | /* |
558 | * This can happen if a broadcast frame is dropped or the AP | |
559 | * fails to send a frame indicating that all CAB frames have | |
560 | * been delivered. | |
561 | */ | |
1b04b930 | 562 | sc->ps_flags &= ~PS_WAIT_FOR_CAB; |
d2182b69 | 563 | ath_dbg(common, PS, "PS wait for CAB frames timed out\n"); |
cc65965c | 564 | } |
cc65965c JM |
565 | } |
566 | ||
f73c604c | 567 | static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb, bool mybeacon) |
cc65965c JM |
568 | { |
569 | struct ieee80211_hdr *hdr; | |
c46917bb | 570 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
cc65965c JM |
571 | |
572 | hdr = (struct ieee80211_hdr *)skb->data; | |
573 | ||
574 | /* Process Beacon and CAB receive in PS state */ | |
ededf1f8 | 575 | if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc)) |
07c15a3f | 576 | && mybeacon) { |
cc65965c | 577 | ath_rx_ps_beacon(sc, skb); |
07c15a3f SM |
578 | } else if ((sc->ps_flags & PS_WAIT_FOR_CAB) && |
579 | (ieee80211_is_data(hdr->frame_control) || | |
580 | ieee80211_is_action(hdr->frame_control)) && | |
581 | is_multicast_ether_addr(hdr->addr1) && | |
582 | !ieee80211_has_moredata(hdr->frame_control)) { | |
cc65965c JM |
583 | /* |
584 | * No more broadcast/multicast frames to be received at this | |
585 | * point. | |
586 | */ | |
3fac6dfd | 587 | sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON); |
d2182b69 | 588 | ath_dbg(common, PS, |
226afe68 | 589 | "All PS CAB frames received, back to sleep\n"); |
1b04b930 | 590 | } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) && |
9a23f9ca JM |
591 | !is_multicast_ether_addr(hdr->addr1) && |
592 | !ieee80211_has_morefrags(hdr->frame_control)) { | |
1b04b930 | 593 | sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA; |
d2182b69 | 594 | ath_dbg(common, PS, |
226afe68 | 595 | "Going back to sleep after having received PS-Poll data (0x%lx)\n", |
1b04b930 S |
596 | sc->ps_flags & (PS_WAIT_FOR_BEACON | |
597 | PS_WAIT_FOR_CAB | | |
598 | PS_WAIT_FOR_PSPOLL_DATA | | |
599 | PS_WAIT_FOR_TX_ACK)); | |
cc65965c JM |
600 | } |
601 | } | |
602 | ||
b5c80475 | 603 | static bool ath_edma_get_buffers(struct ath_softc *sc, |
3a2923e8 FF |
604 | enum ath9k_rx_qtype qtype, |
605 | struct ath_rx_status *rs, | |
606 | struct ath_buf **dest) | |
f078f209 | 607 | { |
b5c80475 FF |
608 | struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype]; |
609 | struct ath_hw *ah = sc->sc_ah; | |
610 | struct ath_common *common = ath9k_hw_common(ah); | |
611 | struct sk_buff *skb; | |
612 | struct ath_buf *bf; | |
613 | int ret; | |
614 | ||
615 | skb = skb_peek(&rx_edma->rx_fifo); | |
616 | if (!skb) | |
617 | return false; | |
618 | ||
619 | bf = SKB_CB_ATHBUF(skb); | |
620 | BUG_ON(!bf); | |
621 | ||
ce9426d1 | 622 | dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr, |
b5c80475 FF |
623 | common->rx_bufsize, DMA_FROM_DEVICE); |
624 | ||
3a2923e8 | 625 | ret = ath9k_hw_process_rxdesc_edma(ah, rs, skb->data); |
ce9426d1 ML |
626 | if (ret == -EINPROGRESS) { |
627 | /*let device gain the buffer again*/ | |
628 | dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, | |
629 | common->rx_bufsize, DMA_FROM_DEVICE); | |
b5c80475 | 630 | return false; |
ce9426d1 | 631 | } |
b5c80475 FF |
632 | |
633 | __skb_unlink(skb, &rx_edma->rx_fifo); | |
634 | if (ret == -EINVAL) { | |
635 | /* corrupt descriptor, skip this one and the following one */ | |
636 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
637 | ath_rx_edma_buf_link(sc, qtype); | |
b5c80475 | 638 | |
3a2923e8 FF |
639 | skb = skb_peek(&rx_edma->rx_fifo); |
640 | if (skb) { | |
641 | bf = SKB_CB_ATHBUF(skb); | |
642 | BUG_ON(!bf); | |
643 | ||
644 | __skb_unlink(skb, &rx_edma->rx_fifo); | |
645 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
646 | ath_rx_edma_buf_link(sc, qtype); | |
3a2923e8 | 647 | } |
6bb51c70 TH |
648 | |
649 | bf = NULL; | |
b5c80475 | 650 | } |
b5c80475 | 651 | |
3a2923e8 | 652 | *dest = bf; |
b5c80475 FF |
653 | return true; |
654 | } | |
f078f209 | 655 | |
b5c80475 FF |
656 | static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc, |
657 | struct ath_rx_status *rs, | |
658 | enum ath9k_rx_qtype qtype) | |
659 | { | |
3a2923e8 | 660 | struct ath_buf *bf = NULL; |
b5c80475 | 661 | |
3a2923e8 FF |
662 | while (ath_edma_get_buffers(sc, qtype, rs, &bf)) { |
663 | if (!bf) | |
664 | continue; | |
b5c80475 | 665 | |
3a2923e8 FF |
666 | return bf; |
667 | } | |
668 | return NULL; | |
b5c80475 FF |
669 | } |
670 | ||
671 | static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc, | |
672 | struct ath_rx_status *rs) | |
673 | { | |
674 | struct ath_hw *ah = sc->sc_ah; | |
675 | struct ath_common *common = ath9k_hw_common(ah); | |
f078f209 | 676 | struct ath_desc *ds; |
b5c80475 FF |
677 | struct ath_buf *bf; |
678 | int ret; | |
679 | ||
680 | if (list_empty(&sc->rx.rxbuf)) { | |
681 | sc->rx.rxlink = NULL; | |
682 | return NULL; | |
683 | } | |
684 | ||
685 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); | |
e96542e5 FF |
686 | if (bf == sc->rx.buf_hold) |
687 | return NULL; | |
688 | ||
b5c80475 FF |
689 | ds = bf->bf_desc; |
690 | ||
691 | /* | |
692 | * Must provide the virtual address of the current | |
693 | * descriptor, the physical address, and the virtual | |
694 | * address of the next descriptor in the h/w chain. | |
695 | * This allows the HAL to look ahead to see if the | |
696 | * hardware is done with a descriptor by checking the | |
697 | * done bit in the following descriptor and the address | |
698 | * of the current descriptor the DMA engine is working | |
699 | * on. All this is necessary because of our use of | |
700 | * a self-linked list to avoid rx overruns. | |
701 | */ | |
3de21116 | 702 | ret = ath9k_hw_rxprocdesc(ah, ds, rs); |
b5c80475 FF |
703 | if (ret == -EINPROGRESS) { |
704 | struct ath_rx_status trs; | |
705 | struct ath_buf *tbf; | |
706 | struct ath_desc *tds; | |
707 | ||
708 | memset(&trs, 0, sizeof(trs)); | |
709 | if (list_is_last(&bf->list, &sc->rx.rxbuf)) { | |
710 | sc->rx.rxlink = NULL; | |
711 | return NULL; | |
712 | } | |
713 | ||
714 | tbf = list_entry(bf->list.next, struct ath_buf, list); | |
715 | ||
716 | /* | |
717 | * On some hardware the descriptor status words could | |
718 | * get corrupted, including the done bit. Because of | |
719 | * this, check if the next descriptor's done bit is | |
720 | * set or not. | |
721 | * | |
722 | * If the next descriptor's done bit is set, the current | |
723 | * descriptor has been corrupted. Force s/w to discard | |
724 | * this descriptor and continue... | |
725 | */ | |
726 | ||
727 | tds = tbf->bf_desc; | |
3de21116 | 728 | ret = ath9k_hw_rxprocdesc(ah, tds, &trs); |
b5c80475 FF |
729 | if (ret == -EINPROGRESS) |
730 | return NULL; | |
723e7113 FF |
731 | |
732 | /* | |
733 | * mark descriptor as zero-length and set the 'more' | |
734 | * flag to ensure that both buffers get discarded | |
735 | */ | |
736 | rs->rs_datalen = 0; | |
737 | rs->rs_more = true; | |
b5c80475 FF |
738 | } |
739 | ||
a3dc48e8 | 740 | list_del(&bf->list); |
b5c80475 FF |
741 | if (!bf->bf_mpdu) |
742 | return bf; | |
743 | ||
744 | /* | |
745 | * Synchronize the DMA transfer with CPU before | |
746 | * 1. accessing the frame | |
747 | * 2. requeueing the same buffer to h/w | |
748 | */ | |
ce9426d1 | 749 | dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr, |
b5c80475 FF |
750 | common->rx_bufsize, |
751 | DMA_FROM_DEVICE); | |
752 | ||
753 | return bf; | |
754 | } | |
755 | ||
d435700f S |
756 | /* Assumes you've already done the endian to CPU conversion */ |
757 | static bool ath9k_rx_accept(struct ath_common *common, | |
9f167f64 | 758 | struct ieee80211_hdr *hdr, |
d435700f S |
759 | struct ieee80211_rx_status *rxs, |
760 | struct ath_rx_status *rx_stats, | |
761 | bool *decrypt_error) | |
762 | { | |
ec205999 | 763 | struct ath_softc *sc = (struct ath_softc *) common->priv; |
66760eac | 764 | bool is_mc, is_valid_tkip, strip_mic, mic_error; |
d435700f | 765 | struct ath_hw *ah = common->ah; |
d435700f S |
766 | __le16 fc; |
767 | ||
d435700f S |
768 | fc = hdr->frame_control; |
769 | ||
66760eac FF |
770 | is_mc = !!is_multicast_ether_addr(hdr->addr1); |
771 | is_valid_tkip = rx_stats->rs_keyix != ATH9K_RXKEYIX_INVALID && | |
772 | test_bit(rx_stats->rs_keyix, common->tkip_keymap); | |
152e585d | 773 | strip_mic = is_valid_tkip && ieee80211_is_data(fc) && |
2a5783b8 | 774 | ieee80211_has_protected(fc) && |
152e585d | 775 | !(rx_stats->rs_status & |
846d9363 FF |
776 | (ATH9K_RXERR_DECRYPT | ATH9K_RXERR_CRC | ATH9K_RXERR_MIC | |
777 | ATH9K_RXERR_KEYMISS)); | |
66760eac | 778 | |
f88373fa FF |
779 | /* |
780 | * Key miss events are only relevant for pairwise keys where the | |
781 | * descriptor does contain a valid key index. This has been observed | |
782 | * mostly with CCMP encryption. | |
783 | */ | |
bed3d9c0 FF |
784 | if (rx_stats->rs_keyix == ATH9K_RXKEYIX_INVALID || |
785 | !test_bit(rx_stats->rs_keyix, common->ccmp_keymap)) | |
f88373fa FF |
786 | rx_stats->rs_status &= ~ATH9K_RXERR_KEYMISS; |
787 | ||
66760eac FF |
788 | mic_error = is_valid_tkip && !ieee80211_is_ctl(fc) && |
789 | !ieee80211_has_morefrags(fc) && | |
790 | !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) && | |
791 | (rx_stats->rs_status & ATH9K_RXERR_MIC); | |
792 | ||
d435700f S |
793 | /* |
794 | * The rx_stats->rs_status will not be set until the end of the | |
795 | * chained descriptors so it can be ignored if rs_more is set. The | |
796 | * rs_more will be false at the last element of the chained | |
797 | * descriptors. | |
798 | */ | |
799 | if (rx_stats->rs_status != 0) { | |
846d9363 FF |
800 | u8 status_mask; |
801 | ||
66760eac | 802 | if (rx_stats->rs_status & ATH9K_RXERR_CRC) { |
d435700f | 803 | rxs->flag |= RX_FLAG_FAILED_FCS_CRC; |
66760eac FF |
804 | mic_error = false; |
805 | } | |
d435700f | 806 | |
846d9363 FF |
807 | if ((rx_stats->rs_status & ATH9K_RXERR_DECRYPT) || |
808 | (!is_mc && (rx_stats->rs_status & ATH9K_RXERR_KEYMISS))) { | |
d435700f | 809 | *decrypt_error = true; |
66760eac | 810 | mic_error = false; |
d435700f | 811 | } |
66760eac | 812 | |
d435700f S |
813 | /* |
814 | * Reject error frames with the exception of | |
815 | * decryption and MIC failures. For monitor mode, | |
816 | * we also ignore the CRC error. | |
817 | */ | |
846d9363 FF |
818 | status_mask = ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC | |
819 | ATH9K_RXERR_KEYMISS; | |
820 | ||
ec205999 | 821 | if (ah->is_monitoring && (sc->rx.rxfilter & FIF_FCSFAIL)) |
846d9363 FF |
822 | status_mask |= ATH9K_RXERR_CRC; |
823 | ||
824 | if (rx_stats->rs_status & ~status_mask) | |
825 | return false; | |
d435700f | 826 | } |
66760eac FF |
827 | |
828 | /* | |
829 | * For unicast frames the MIC error bit can have false positives, | |
830 | * so all MIC error reports need to be validated in software. | |
831 | * False negatives are not common, so skip software verification | |
832 | * if the hardware considers the MIC valid. | |
833 | */ | |
834 | if (strip_mic) | |
835 | rxs->flag |= RX_FLAG_MMIC_STRIPPED; | |
836 | else if (is_mc && mic_error) | |
837 | rxs->flag |= RX_FLAG_MMIC_ERROR; | |
838 | ||
d435700f S |
839 | return true; |
840 | } | |
841 | ||
842 | static int ath9k_process_rate(struct ath_common *common, | |
843 | struct ieee80211_hw *hw, | |
844 | struct ath_rx_status *rx_stats, | |
9f167f64 | 845 | struct ieee80211_rx_status *rxs) |
d435700f S |
846 | { |
847 | struct ieee80211_supported_band *sband; | |
848 | enum ieee80211_band band; | |
849 | unsigned int i = 0; | |
990e08a0 | 850 | struct ath_softc __maybe_unused *sc = common->priv; |
d435700f | 851 | |
675a0b04 | 852 | band = hw->conf.chandef.chan->band; |
d435700f S |
853 | sband = hw->wiphy->bands[band]; |
854 | ||
855 | if (rx_stats->rs_rate & 0x80) { | |
856 | /* HT rate */ | |
857 | rxs->flag |= RX_FLAG_HT; | |
ab276103 | 858 | rxs->flag |= rx_stats->flag; |
d435700f S |
859 | rxs->rate_idx = rx_stats->rs_rate & 0x7f; |
860 | return 0; | |
861 | } | |
862 | ||
863 | for (i = 0; i < sband->n_bitrates; i++) { | |
864 | if (sband->bitrates[i].hw_value == rx_stats->rs_rate) { | |
865 | rxs->rate_idx = i; | |
866 | return 0; | |
867 | } | |
868 | if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) { | |
869 | rxs->flag |= RX_FLAG_SHORTPRE; | |
870 | rxs->rate_idx = i; | |
871 | return 0; | |
872 | } | |
873 | } | |
874 | ||
875 | /* | |
876 | * No valid hardware bitrate found -- we should not get here | |
877 | * because hardware has already validated this frame as OK. | |
878 | */ | |
d2182b69 | 879 | ath_dbg(common, ANY, |
226afe68 JP |
880 | "unsupported hw bitrate detected 0x%02x using 1 Mbit\n", |
881 | rx_stats->rs_rate); | |
15072189 | 882 | RX_STAT_INC(rx_rate_err); |
d435700f S |
883 | return -EINVAL; |
884 | } | |
885 | ||
886 | static void ath9k_process_rssi(struct ath_common *common, | |
887 | struct ieee80211_hw *hw, | |
9f167f64 | 888 | struct ieee80211_hdr *hdr, |
d435700f S |
889 | struct ath_rx_status *rx_stats) |
890 | { | |
9ac58615 | 891 | struct ath_softc *sc = hw->priv; |
d435700f | 892 | struct ath_hw *ah = common->ah; |
9fa23e17 | 893 | int last_rssi; |
2ef16755 | 894 | int rssi = rx_stats->rs_rssi; |
d435700f | 895 | |
cf3af748 RM |
896 | if (!rx_stats->is_mybeacon || |
897 | ((ah->opmode != NL80211_IFTYPE_STATION) && | |
898 | (ah->opmode != NL80211_IFTYPE_ADHOC))) | |
9fa23e17 FF |
899 | return; |
900 | ||
9fa23e17 | 901 | if (rx_stats->rs_rssi != ATH9K_RSSI_BAD && !rx_stats->rs_moreaggr) |
9ac58615 | 902 | ATH_RSSI_LPF(sc->last_rssi, rx_stats->rs_rssi); |
d435700f | 903 | |
9ac58615 | 904 | last_rssi = sc->last_rssi; |
d435700f | 905 | if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER)) |
2ef16755 FF |
906 | rssi = ATH_EP_RND(last_rssi, ATH_RSSI_EP_MULTIPLIER); |
907 | if (rssi < 0) | |
908 | rssi = 0; | |
d435700f S |
909 | |
910 | /* Update Beacon RSSI, this is used by ANI. */ | |
2ef16755 | 911 | ah->stats.avgbrssi = rssi; |
d435700f S |
912 | } |
913 | ||
e0dd1a96 SM |
914 | static void ath9k_process_tsf(struct ath_rx_status *rs, |
915 | struct ieee80211_rx_status *rxs, | |
916 | u64 tsf) | |
917 | { | |
918 | u32 tsf_lower = tsf & 0xffffffff; | |
919 | ||
920 | rxs->mactime = (tsf & ~0xffffffffULL) | rs->rs_tstamp; | |
921 | if (rs->rs_tstamp > tsf_lower && | |
922 | unlikely(rs->rs_tstamp - tsf_lower > 0x10000000)) | |
923 | rxs->mactime -= 0x100000000ULL; | |
924 | ||
925 | if (rs->rs_tstamp < tsf_lower && | |
926 | unlikely(tsf_lower - rs->rs_tstamp > 0x10000000)) | |
927 | rxs->mactime += 0x100000000ULL; | |
928 | } | |
929 | ||
3105b672 SM |
930 | #ifdef CONFIG_ATH9K_DEBUGFS |
931 | static s8 fix_rssi_inv_only(u8 rssi_val) | |
932 | { | |
933 | if (rssi_val == 128) | |
934 | rssi_val = 0; | |
935 | return (s8) rssi_val; | |
936 | } | |
937 | #endif | |
938 | ||
939 | /* returns 1 if this was a spectral frame, even if not handled. */ | |
940 | static int ath_process_fft(struct ath_softc *sc, struct ieee80211_hdr *hdr, | |
941 | struct ath_rx_status *rs, u64 tsf) | |
942 | { | |
943 | #ifdef CONFIG_ATH9K_DEBUGFS | |
944 | struct ath_hw *ah = sc->sc_ah; | |
945 | u8 bins[SPECTRAL_HT20_NUM_BINS]; | |
946 | u8 *vdata = (u8 *)hdr; | |
947 | struct fft_sample_ht20 fft_sample; | |
948 | struct ath_radar_info *radar_info; | |
949 | struct ath_ht20_mag_info *mag_info; | |
950 | int len = rs->rs_datalen; | |
951 | int dc_pos; | |
952 | u16 length, max_magnitude; | |
953 | ||
954 | /* AR9280 and before report via ATH9K_PHYERR_RADAR, AR93xx and newer | |
955 | * via ATH9K_PHYERR_SPECTRAL. Haven't seen ATH9K_PHYERR_FALSE_RADAR_EXT | |
956 | * yet, but this is supposed to be possible as well. | |
957 | */ | |
958 | if (rs->rs_phyerr != ATH9K_PHYERR_RADAR && | |
959 | rs->rs_phyerr != ATH9K_PHYERR_FALSE_RADAR_EXT && | |
960 | rs->rs_phyerr != ATH9K_PHYERR_SPECTRAL) | |
961 | return 0; | |
962 | ||
963 | /* check if spectral scan bit is set. This does not have to be checked | |
964 | * if received through a SPECTRAL phy error, but shouldn't hurt. | |
965 | */ | |
966 | radar_info = ((struct ath_radar_info *)&vdata[len]) - 1; | |
967 | if (!(radar_info->pulse_bw_info & SPECTRAL_SCAN_BITMASK)) | |
968 | return 0; | |
969 | ||
970 | /* Variation in the data length is possible and will be fixed later. | |
971 | * Note that we only support HT20 for now. | |
972 | * | |
973 | * TODO: add HT20_40 support as well. | |
974 | */ | |
975 | if ((len > SPECTRAL_HT20_TOTAL_DATA_LEN + 2) || | |
976 | (len < SPECTRAL_HT20_TOTAL_DATA_LEN - 1)) | |
977 | return 1; | |
978 | ||
979 | fft_sample.tlv.type = ATH_FFT_SAMPLE_HT20; | |
980 | length = sizeof(fft_sample) - sizeof(fft_sample.tlv); | |
981 | fft_sample.tlv.length = __cpu_to_be16(length); | |
982 | ||
983 | fft_sample.freq = __cpu_to_be16(ah->curchan->chan->center_freq); | |
984 | fft_sample.rssi = fix_rssi_inv_only(rs->rs_rssi_ctl0); | |
985 | fft_sample.noise = ah->noise; | |
986 | ||
987 | switch (len - SPECTRAL_HT20_TOTAL_DATA_LEN) { | |
988 | case 0: | |
989 | /* length correct, nothing to do. */ | |
990 | memcpy(bins, vdata, SPECTRAL_HT20_NUM_BINS); | |
991 | break; | |
992 | case -1: | |
993 | /* first byte missing, duplicate it. */ | |
994 | memcpy(&bins[1], vdata, SPECTRAL_HT20_NUM_BINS - 1); | |
995 | bins[0] = vdata[0]; | |
996 | break; | |
997 | case 2: | |
998 | /* MAC added 2 extra bytes at bin 30 and 32, remove them. */ | |
999 | memcpy(bins, vdata, 30); | |
1000 | bins[30] = vdata[31]; | |
1001 | memcpy(&bins[31], &vdata[33], SPECTRAL_HT20_NUM_BINS - 31); | |
1002 | break; | |
1003 | case 1: | |
1004 | /* MAC added 2 extra bytes AND first byte is missing. */ | |
1005 | bins[0] = vdata[0]; | |
1006 | memcpy(&bins[0], vdata, 30); | |
1007 | bins[31] = vdata[31]; | |
1008 | memcpy(&bins[32], &vdata[33], SPECTRAL_HT20_NUM_BINS - 32); | |
1009 | break; | |
1010 | default: | |
1011 | return 1; | |
1012 | } | |
1013 | ||
1014 | /* DC value (value in the middle) is the blind spot of the spectral | |
1015 | * sample and invalid, interpolate it. | |
1016 | */ | |
1017 | dc_pos = SPECTRAL_HT20_NUM_BINS / 2; | |
1018 | bins[dc_pos] = (bins[dc_pos + 1] + bins[dc_pos - 1]) / 2; | |
1019 | ||
1020 | /* mag data is at the end of the frame, in front of radar_info */ | |
1021 | mag_info = ((struct ath_ht20_mag_info *)radar_info) - 1; | |
1022 | ||
1023 | /* copy raw bins without scaling them */ | |
1024 | memcpy(fft_sample.data, bins, SPECTRAL_HT20_NUM_BINS); | |
1025 | fft_sample.max_exp = mag_info->max_exp & 0xf; | |
1026 | ||
1027 | max_magnitude = spectral_max_magnitude(mag_info->all_bins); | |
1028 | fft_sample.max_magnitude = __cpu_to_be16(max_magnitude); | |
1029 | fft_sample.max_index = spectral_max_index(mag_info->all_bins); | |
1030 | fft_sample.bitmap_weight = spectral_bitmap_weight(mag_info->all_bins); | |
1031 | fft_sample.tsf = __cpu_to_be64(tsf); | |
1032 | ||
1033 | ath_debug_send_fft_sample(sc, &fft_sample.tlv); | |
1034 | return 1; | |
1035 | #else | |
1036 | return 0; | |
1037 | #endif | |
1038 | } | |
1039 | ||
d435700f S |
1040 | /* |
1041 | * For Decrypt or Demic errors, we only mark packet status here and always push | |
1042 | * up the frame up to let mac80211 handle the actual error case, be it no | |
1043 | * decryption key or real decryption error. This let us keep statistics there. | |
1044 | */ | |
723e7113 | 1045 | static int ath9k_rx_skb_preprocess(struct ath_softc *sc, |
9f167f64 | 1046 | struct ieee80211_hdr *hdr, |
d435700f S |
1047 | struct ath_rx_status *rx_stats, |
1048 | struct ieee80211_rx_status *rx_status, | |
e0dd1a96 | 1049 | bool *decrypt_error, u64 tsf) |
d435700f | 1050 | { |
723e7113 FF |
1051 | struct ieee80211_hw *hw = sc->hw; |
1052 | struct ath_hw *ah = sc->sc_ah; | |
1053 | struct ath_common *common = ath9k_hw_common(ah); | |
1054 | bool discard_current = sc->rx.discard_next; | |
1055 | ||
5871d2d7 SM |
1056 | /* |
1057 | * Discard corrupt descriptors which are marked in | |
1058 | * ath_get_next_rx_buf(). | |
1059 | */ | |
723e7113 FF |
1060 | sc->rx.discard_next = rx_stats->rs_more; |
1061 | if (discard_current) | |
1062 | return -EINVAL; | |
f749b946 | 1063 | |
5871d2d7 SM |
1064 | /* |
1065 | * Discard zero-length packets. | |
1066 | */ | |
1067 | if (!rx_stats->rs_datalen) { | |
1068 | RX_STAT_INC(rx_len_err); | |
1069 | return -EINVAL; | |
1070 | } | |
1071 | ||
1072 | /* | |
1073 | * rs_status follows rs_datalen so if rs_datalen is too large | |
1074 | * we can take a hint that hardware corrupted it, so ignore | |
1075 | * those frames. | |
1076 | */ | |
1077 | if (rx_stats->rs_datalen > (common->rx_bufsize - ah->caps.rx_status_len)) { | |
1078 | RX_STAT_INC(rx_len_err); | |
1079 | return -EINVAL; | |
1080 | } | |
1081 | ||
4a470647 SM |
1082 | /* Only use status info from the last fragment */ |
1083 | if (rx_stats->rs_more) | |
1084 | return 0; | |
1085 | ||
e0dd1a96 SM |
1086 | ath9k_process_tsf(rx_stats, rx_status, tsf); |
1087 | ||
6b87d71c SM |
1088 | /* |
1089 | * Process PHY errors and return so that the packet | |
1090 | * can be dropped. | |
1091 | */ | |
1092 | if (rx_stats->rs_status & ATH9K_RXERR_PHY) { | |
1093 | ath9k_dfs_process_phyerr(sc, hdr, rx_stats, rx_status->mactime); | |
1094 | if (ath_process_fft(sc, hdr, rx_stats, rx_status->mactime)) | |
1095 | RX_STAT_INC(rx_spectral); | |
1096 | ||
1097 | return -EINVAL; | |
1098 | } | |
1099 | ||
d435700f S |
1100 | /* |
1101 | * everything but the rate is checked here, the rate check is done | |
1102 | * separately to avoid doing two lookups for a rate for each frame. | |
1103 | */ | |
9f167f64 | 1104 | if (!ath9k_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error)) |
d435700f S |
1105 | return -EINVAL; |
1106 | ||
9f167f64 | 1107 | if (ath9k_process_rate(common, hw, rx_stats, rx_status)) |
d435700f S |
1108 | return -EINVAL; |
1109 | ||
74a97755 SM |
1110 | ath9k_process_rssi(common, hw, hdr, rx_stats); |
1111 | ||
675a0b04 KB |
1112 | rx_status->band = hw->conf.chandef.chan->band; |
1113 | rx_status->freq = hw->conf.chandef.chan->center_freq; | |
f749b946 | 1114 | rx_status->signal = ah->noise + rx_stats->rs_rssi; |
d435700f | 1115 | rx_status->antenna = rx_stats->rs_antenna; |
96d21371 | 1116 | rx_status->flag |= RX_FLAG_MACTIME_END; |
2ef16755 FF |
1117 | if (rx_stats->rs_moreaggr) |
1118 | rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; | |
d435700f | 1119 | |
723e7113 | 1120 | sc->rx.discard_next = false; |
d435700f S |
1121 | return 0; |
1122 | } | |
1123 | ||
1124 | static void ath9k_rx_skb_postprocess(struct ath_common *common, | |
1125 | struct sk_buff *skb, | |
1126 | struct ath_rx_status *rx_stats, | |
1127 | struct ieee80211_rx_status *rxs, | |
1128 | bool decrypt_error) | |
1129 | { | |
1130 | struct ath_hw *ah = common->ah; | |
1131 | struct ieee80211_hdr *hdr; | |
1132 | int hdrlen, padpos, padsize; | |
1133 | u8 keyix; | |
1134 | __le16 fc; | |
1135 | ||
1136 | /* see if any padding is done by the hw and remove it */ | |
1137 | hdr = (struct ieee80211_hdr *) skb->data; | |
1138 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); | |
1139 | fc = hdr->frame_control; | |
c60c9929 | 1140 | padpos = ieee80211_hdrlen(fc); |
d435700f S |
1141 | |
1142 | /* The MAC header is padded to have 32-bit boundary if the | |
1143 | * packet payload is non-zero. The general calculation for | |
1144 | * padsize would take into account odd header lengths: | |
1145 | * padsize = (4 - padpos % 4) % 4; However, since only | |
1146 | * even-length headers are used, padding can only be 0 or 2 | |
1147 | * bytes and we can optimize this a bit. In addition, we must | |
1148 | * not try to remove padding from short control frames that do | |
1149 | * not have payload. */ | |
1150 | padsize = padpos & 3; | |
1151 | if (padsize && skb->len>=padpos+padsize+FCS_LEN) { | |
1152 | memmove(skb->data + padsize, skb->data, padpos); | |
1153 | skb_pull(skb, padsize); | |
1154 | } | |
1155 | ||
1156 | keyix = rx_stats->rs_keyix; | |
1157 | ||
1158 | if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error && | |
1159 | ieee80211_has_protected(fc)) { | |
1160 | rxs->flag |= RX_FLAG_DECRYPTED; | |
1161 | } else if (ieee80211_has_protected(fc) | |
1162 | && !decrypt_error && skb->len >= hdrlen + 4) { | |
1163 | keyix = skb->data[hdrlen + 3] >> 6; | |
1164 | ||
1165 | if (test_bit(keyix, common->keymap)) | |
1166 | rxs->flag |= RX_FLAG_DECRYPTED; | |
1167 | } | |
1168 | if (ah->sw_mgmt_crypto && | |
1169 | (rxs->flag & RX_FLAG_DECRYPTED) && | |
1170 | ieee80211_is_mgmt(fc)) | |
1171 | /* Use software decrypt for management frames. */ | |
1172 | rxs->flag &= ~RX_FLAG_DECRYPTED; | |
1173 | } | |
b5c80475 | 1174 | |
21fbbca3 CL |
1175 | static void ath9k_apply_ampdu_details(struct ath_softc *sc, |
1176 | struct ath_rx_status *rs, struct ieee80211_rx_status *rxs) | |
1177 | { | |
1178 | if (rs->rs_isaggr) { | |
1179 | rxs->flag |= RX_FLAG_AMPDU_DETAILS | RX_FLAG_AMPDU_LAST_KNOWN; | |
1180 | ||
1181 | rxs->ampdu_reference = sc->rx.ampdu_ref; | |
1182 | ||
1183 | if (!rs->rs_moreaggr) { | |
1184 | rxs->flag |= RX_FLAG_AMPDU_IS_LAST; | |
1185 | sc->rx.ampdu_ref++; | |
1186 | } | |
1187 | ||
1188 | if (rs->rs_flags & ATH9K_RX_DELIM_CRC_PRE) | |
1189 | rxs->flag |= RX_FLAG_AMPDU_DELIM_CRC_ERROR; | |
1190 | } | |
1191 | } | |
1192 | ||
f6307dda SM |
1193 | static bool ath9k_is_mybeacon(struct ath_softc *sc, struct sk_buff *skb) |
1194 | { | |
1195 | struct ath_hw *ah = sc->sc_ah; | |
1196 | struct ath_common *common = ath9k_hw_common(ah); | |
1197 | struct ieee80211_hdr *hdr; | |
1198 | ||
1199 | hdr = (struct ieee80211_hdr *) (skb->data + ah->caps.rx_status_len); | |
1200 | ||
1201 | if (ieee80211_is_beacon(hdr->frame_control)) { | |
1202 | RX_STAT_INC(rx_beacons); | |
1203 | if (!is_zero_ether_addr(common->curbssid) && | |
1204 | ether_addr_equal(hdr->addr3, common->curbssid)) | |
1205 | return true; | |
1206 | } | |
1207 | ||
1208 | return false; | |
1209 | } | |
1210 | ||
b5c80475 FF |
1211 | int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp) |
1212 | { | |
1213 | struct ath_buf *bf; | |
0d95521e | 1214 | struct sk_buff *skb = NULL, *requeue_skb, *hdr_skb; |
5ca42627 | 1215 | struct ieee80211_rx_status *rxs; |
cbe61d8a | 1216 | struct ath_hw *ah = sc->sc_ah; |
16fe28e9 | 1217 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
27c51f1a | 1218 | struct ath_common *common = ath9k_hw_common(ah); |
7545daf4 | 1219 | struct ieee80211_hw *hw = sc->hw; |
be0418ad | 1220 | struct ieee80211_hdr *hdr; |
c9b14170 | 1221 | int retval; |
29bffa96 | 1222 | struct ath_rx_status rs; |
b5c80475 FF |
1223 | enum ath9k_rx_qtype qtype; |
1224 | bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); | |
1225 | int dma_type; | |
a6d2055b | 1226 | u64 tsf = 0; |
8ab2cd09 | 1227 | unsigned long flags; |
2e1cd495 | 1228 | dma_addr_t new_buf_addr; |
be0418ad | 1229 | |
b5c80475 | 1230 | if (edma) |
b5c80475 | 1231 | dma_type = DMA_BIDIRECTIONAL; |
56824223 ML |
1232 | else |
1233 | dma_type = DMA_FROM_DEVICE; | |
b5c80475 FF |
1234 | |
1235 | qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP; | |
f078f209 | 1236 | |
a6d2055b | 1237 | tsf = ath9k_hw_gettsf64(ah); |
a6d2055b | 1238 | |
f078f209 | 1239 | do { |
e1352fde | 1240 | bool decrypt_error = false; |
f078f209 | 1241 | |
29bffa96 | 1242 | memset(&rs, 0, sizeof(rs)); |
b5c80475 FF |
1243 | if (edma) |
1244 | bf = ath_edma_get_next_rx_buf(sc, &rs, qtype); | |
1245 | else | |
1246 | bf = ath_get_next_rx_buf(sc, &rs); | |
f078f209 | 1247 | |
b5c80475 FF |
1248 | if (!bf) |
1249 | break; | |
f078f209 | 1250 | |
f078f209 | 1251 | skb = bf->bf_mpdu; |
be0418ad | 1252 | if (!skb) |
f078f209 | 1253 | continue; |
f078f209 | 1254 | |
0d95521e FF |
1255 | /* |
1256 | * Take frame header from the first fragment and RX status from | |
1257 | * the last one. | |
1258 | */ | |
1259 | if (sc->rx.frag) | |
1260 | hdr_skb = sc->rx.frag; | |
1261 | else | |
1262 | hdr_skb = skb; | |
1263 | ||
f6307dda SM |
1264 | rs.is_mybeacon = ath9k_is_mybeacon(sc, hdr_skb); |
1265 | ||
1266 | hdr = (struct ieee80211_hdr *) (hdr_skb->data + | |
1267 | ah->caps.rx_status_len); | |
5ca42627 | 1268 | |
be41b052 MSS |
1269 | if (ieee80211_is_data_present(hdr->frame_control) && |
1270 | !ieee80211_is_qos_nullfunc(hdr->frame_control)) | |
1271 | sc->rx.num_pkts++; | |
1272 | ||
29bffa96 | 1273 | ath_debug_stat_rx(sc, &rs); |
1395d3f0 | 1274 | |
f6307dda | 1275 | rxs = IEEE80211_SKB_RXCB(hdr_skb); |
ffb1c56a AN |
1276 | memset(rxs, 0, sizeof(struct ieee80211_rx_status)); |
1277 | ||
723e7113 | 1278 | retval = ath9k_rx_skb_preprocess(sc, hdr, &rs, rxs, |
e0dd1a96 | 1279 | &decrypt_error, tsf); |
83c76570 ZK |
1280 | if (retval) |
1281 | goto requeue_drop_frag; | |
1282 | ||
01e18918 RM |
1283 | if (rs.is_mybeacon) { |
1284 | sc->hw_busy_count = 0; | |
1285 | ath_start_rx_poll(sc, 3); | |
1286 | } | |
cb71d9ba LR |
1287 | /* Ensure we always have an skb to requeue once we are done |
1288 | * processing the current buffer's skb */ | |
cc861f74 | 1289 | requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC); |
cb71d9ba LR |
1290 | |
1291 | /* If there is no memory we ignore the current RX'd frame, | |
1292 | * tell hardware it can give us a new frame using the old | |
b77f483f | 1293 | * skb and put it at the tail of the sc->rx.rxbuf list for |
cb71d9ba | 1294 | * processing. */ |
15072189 BG |
1295 | if (!requeue_skb) { |
1296 | RX_STAT_INC(rx_oom_err); | |
0d95521e | 1297 | goto requeue_drop_frag; |
15072189 | 1298 | } |
f078f209 | 1299 | |
2e1cd495 FF |
1300 | /* We will now give hardware our shiny new allocated skb */ |
1301 | new_buf_addr = dma_map_single(sc->dev, requeue_skb->data, | |
1302 | common->rx_bufsize, dma_type); | |
1303 | if (unlikely(dma_mapping_error(sc->dev, new_buf_addr))) { | |
1304 | dev_kfree_skb_any(requeue_skb); | |
1305 | goto requeue_drop_frag; | |
1306 | } | |
1307 | ||
9bf9fca8 | 1308 | /* Unmap the frame */ |
7da3c55c | 1309 | dma_unmap_single(sc->dev, bf->bf_buf_addr, |
2e1cd495 | 1310 | common->rx_bufsize, dma_type); |
f078f209 | 1311 | |
176f0e84 SM |
1312 | bf->bf_mpdu = requeue_skb; |
1313 | bf->bf_buf_addr = new_buf_addr; | |
1314 | ||
b5c80475 FF |
1315 | skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len); |
1316 | if (ah->caps.rx_status_len) | |
1317 | skb_pull(skb, ah->caps.rx_status_len); | |
be0418ad | 1318 | |
0d95521e FF |
1319 | if (!rs.rs_more) |
1320 | ath9k_rx_skb_postprocess(common, hdr_skb, &rs, | |
1321 | rxs, decrypt_error); | |
be0418ad | 1322 | |
0d95521e | 1323 | if (rs.rs_more) { |
15072189 | 1324 | RX_STAT_INC(rx_frags); |
0d95521e FF |
1325 | /* |
1326 | * rs_more indicates chained descriptors which can be | |
1327 | * used to link buffers together for a sort of | |
1328 | * scatter-gather operation. | |
1329 | */ | |
1330 | if (sc->rx.frag) { | |
1331 | /* too many fragments - cannot handle frame */ | |
1332 | dev_kfree_skb_any(sc->rx.frag); | |
1333 | dev_kfree_skb_any(skb); | |
15072189 | 1334 | RX_STAT_INC(rx_too_many_frags_err); |
0d95521e FF |
1335 | skb = NULL; |
1336 | } | |
1337 | sc->rx.frag = skb; | |
1338 | goto requeue; | |
1339 | } | |
3747c3ee FF |
1340 | if (rs.rs_status & ATH9K_RXERR_CORRUPT_DESC) |
1341 | goto requeue_drop_frag; | |
0d95521e FF |
1342 | |
1343 | if (sc->rx.frag) { | |
1344 | int space = skb->len - skb_tailroom(hdr_skb); | |
1345 | ||
0d95521e FF |
1346 | if (pskb_expand_head(hdr_skb, 0, space, GFP_ATOMIC) < 0) { |
1347 | dev_kfree_skb(skb); | |
15072189 | 1348 | RX_STAT_INC(rx_oom_err); |
0d95521e FF |
1349 | goto requeue_drop_frag; |
1350 | } | |
1351 | ||
b5447ff9 ED |
1352 | sc->rx.frag = NULL; |
1353 | ||
0d95521e FF |
1354 | skb_copy_from_linear_data(skb, skb_put(hdr_skb, skb->len), |
1355 | skb->len); | |
1356 | dev_kfree_skb_any(skb); | |
1357 | skb = hdr_skb; | |
1358 | } | |
1359 | ||
16fe28e9 SM |
1360 | if (rxs->flag & RX_FLAG_MMIC_STRIPPED) |
1361 | skb_trim(skb, skb->len - 8); | |
eb840a80 | 1362 | |
16fe28e9 SM |
1363 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
1364 | if ((sc->ps_flags & (PS_WAIT_FOR_BEACON | | |
1365 | PS_WAIT_FOR_CAB | | |
1366 | PS_WAIT_FOR_PSPOLL_DATA)) || | |
1367 | ath9k_check_auto_sleep(sc)) | |
1368 | ath_rx_ps(sc, skb, rs.is_mybeacon); | |
1369 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
eb840a80 | 1370 | |
16fe28e9 SM |
1371 | /* |
1372 | * Run the LNA combining algorithm only in these cases: | |
1373 | * | |
1374 | * Standalone WLAN cards with both LNA/Antenna diversity | |
1375 | * enabled in the EEPROM. | |
1376 | * | |
1377 | * WLAN+BT cards which are in the supported card list | |
1378 | * in ath_pci_id_table and the user has loaded the | |
1379 | * driver with "bt_ant_diversity" set to true. | |
1380 | */ | |
1381 | if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) { | |
eb840a80 | 1382 | /* |
16fe28e9 | 1383 | * Change the default rx antenna if rx diversity |
eb840a80 MSS |
1384 | * chooses the other antenna 3 times in a row. |
1385 | */ | |
1386 | if (sc->rx.defant != rs.rs_antenna) { | |
1387 | if (++sc->rx.rxotherant >= 3) | |
1388 | ath_setdefantenna(sc, rs.rs_antenna); | |
1389 | } else { | |
1390 | sc->rx.rxotherant = 0; | |
1391 | } | |
1392 | ||
16fe28e9 SM |
1393 | if (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV) { |
1394 | if (common->bt_ant_diversity) | |
1395 | ath_ant_comb_scan(sc, &rs); | |
1396 | } else { | |
1397 | ath_ant_comb_scan(sc, &rs); | |
1398 | } | |
f078f209 | 1399 | } |
3cbb5dd7 | 1400 | |
21fbbca3 CL |
1401 | ath9k_apply_ampdu_details(sc, &rs, rxs); |
1402 | ||
7545daf4 | 1403 | ieee80211_rx(hw, skb); |
cc65965c | 1404 | |
0d95521e FF |
1405 | requeue_drop_frag: |
1406 | if (sc->rx.frag) { | |
1407 | dev_kfree_skb_any(sc->rx.frag); | |
1408 | sc->rx.frag = NULL; | |
1409 | } | |
cb71d9ba | 1410 | requeue: |
a3dc48e8 FF |
1411 | list_add_tail(&bf->list, &sc->rx.rxbuf); |
1412 | if (flush) | |
1413 | continue; | |
1414 | ||
b5c80475 | 1415 | if (edma) { |
b5c80475 FF |
1416 | ath_rx_edma_buf_link(sc, qtype); |
1417 | } else { | |
e96542e5 | 1418 | ath_rx_buf_relink(sc, bf); |
a3dc48e8 | 1419 | ath9k_hw_rxena(ah); |
b5c80475 | 1420 | } |
be0418ad S |
1421 | } while (1); |
1422 | ||
29ab0b36 RM |
1423 | if (!(ah->imask & ATH9K_INT_RXEOL)) { |
1424 | ah->imask |= (ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
72d874c6 | 1425 | ath9k_hw_set_interrupts(ah); |
29ab0b36 RM |
1426 | } |
1427 | ||
f078f209 | 1428 | return 0; |
f078f209 | 1429 | } |