Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
394cf0a1 | 17 | #include "ath9k.h" |
b622a720 | 18 | #include "ar9003_mac.h" |
f078f209 | 19 | |
b5c80475 FF |
20 | #define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb)) |
21 | ||
102885a5 VT |
22 | static inline bool ath_is_alt_ant_ratio_better(int alt_ratio, int maxdelta, |
23 | int mindelta, int main_rssi_avg, | |
24 | int alt_rssi_avg, int pkt_count) | |
25 | { | |
26 | return (((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) && | |
27 | (alt_rssi_avg > main_rssi_avg + maxdelta)) || | |
28 | (alt_rssi_avg > main_rssi_avg + mindelta)) && (pkt_count > 50); | |
29 | } | |
30 | ||
ededf1f8 VT |
31 | static inline bool ath9k_check_auto_sleep(struct ath_softc *sc) |
32 | { | |
33 | return sc->ps_enabled && | |
34 | (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP); | |
35 | } | |
36 | ||
f078f209 LR |
37 | /* |
38 | * Setup and link descriptors. | |
39 | * | |
40 | * 11N: we can no longer afford to self link the last descriptor. | |
41 | * MAC acknowledges BA status as long as it copies frames to host | |
42 | * buffer (or rx fifo). This can incorrectly acknowledge packets | |
43 | * to a sender if last desc is self-linked. | |
f078f209 | 44 | */ |
f078f209 LR |
45 | static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf) |
46 | { | |
cbe61d8a | 47 | struct ath_hw *ah = sc->sc_ah; |
cc861f74 | 48 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 LR |
49 | struct ath_desc *ds; |
50 | struct sk_buff *skb; | |
51 | ||
52 | ATH_RXBUF_RESET(bf); | |
53 | ||
54 | ds = bf->bf_desc; | |
be0418ad | 55 | ds->ds_link = 0; /* link to null */ |
f078f209 LR |
56 | ds->ds_data = bf->bf_buf_addr; |
57 | ||
be0418ad | 58 | /* virtual addr of the beginning of the buffer. */ |
f078f209 | 59 | skb = bf->bf_mpdu; |
9680e8a3 | 60 | BUG_ON(skb == NULL); |
f078f209 LR |
61 | ds->ds_vdata = skb->data; |
62 | ||
cc861f74 LR |
63 | /* |
64 | * setup rx descriptors. The rx_bufsize here tells the hardware | |
b4b6cda2 | 65 | * how much data it can DMA to us and that we are prepared |
cc861f74 LR |
66 | * to process |
67 | */ | |
b77f483f | 68 | ath9k_hw_setuprxdesc(ah, ds, |
cc861f74 | 69 | common->rx_bufsize, |
f078f209 LR |
70 | 0); |
71 | ||
b77f483f | 72 | if (sc->rx.rxlink == NULL) |
f078f209 LR |
73 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); |
74 | else | |
b77f483f | 75 | *sc->rx.rxlink = bf->bf_daddr; |
f078f209 | 76 | |
b77f483f | 77 | sc->rx.rxlink = &ds->ds_link; |
f078f209 LR |
78 | ath9k_hw_rxena(ah); |
79 | } | |
80 | ||
ff37e337 S |
81 | static void ath_setdefantenna(struct ath_softc *sc, u32 antenna) |
82 | { | |
83 | /* XXX block beacon interrupts */ | |
84 | ath9k_hw_setantenna(sc->sc_ah, antenna); | |
b77f483f S |
85 | sc->rx.defant = antenna; |
86 | sc->rx.rxotherant = 0; | |
ff37e337 S |
87 | } |
88 | ||
f078f209 LR |
89 | static void ath_opmode_init(struct ath_softc *sc) |
90 | { | |
cbe61d8a | 91 | struct ath_hw *ah = sc->sc_ah; |
1510718d LR |
92 | struct ath_common *common = ath9k_hw_common(ah); |
93 | ||
f078f209 LR |
94 | u32 rfilt, mfilt[2]; |
95 | ||
96 | /* configure rx filter */ | |
97 | rfilt = ath_calcrxfilter(sc); | |
98 | ath9k_hw_setrxfilter(ah, rfilt); | |
99 | ||
100 | /* configure bssid mask */ | |
364734fa | 101 | ath_hw_setbssidmask(common); |
f078f209 LR |
102 | |
103 | /* configure operational mode */ | |
104 | ath9k_hw_setopmode(ah); | |
105 | ||
f078f209 LR |
106 | /* calculate and install multicast filter */ |
107 | mfilt[0] = mfilt[1] = ~0; | |
f078f209 | 108 | ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]); |
f078f209 LR |
109 | } |
110 | ||
b5c80475 FF |
111 | static bool ath_rx_edma_buf_link(struct ath_softc *sc, |
112 | enum ath9k_rx_qtype qtype) | |
f078f209 | 113 | { |
b5c80475 FF |
114 | struct ath_hw *ah = sc->sc_ah; |
115 | struct ath_rx_edma *rx_edma; | |
f078f209 LR |
116 | struct sk_buff *skb; |
117 | struct ath_buf *bf; | |
f078f209 | 118 | |
b5c80475 FF |
119 | rx_edma = &sc->rx.rx_edma[qtype]; |
120 | if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize) | |
121 | return false; | |
f078f209 | 122 | |
b5c80475 FF |
123 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); |
124 | list_del_init(&bf->list); | |
f078f209 | 125 | |
b5c80475 FF |
126 | skb = bf->bf_mpdu; |
127 | ||
128 | ATH_RXBUF_RESET(bf); | |
129 | memset(skb->data, 0, ah->caps.rx_status_len); | |
130 | dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, | |
131 | ah->caps.rx_status_len, DMA_TO_DEVICE); | |
f078f209 | 132 | |
b5c80475 FF |
133 | SKB_CB_ATHBUF(skb) = bf; |
134 | ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype); | |
135 | skb_queue_tail(&rx_edma->rx_fifo, skb); | |
f078f209 | 136 | |
b5c80475 FF |
137 | return true; |
138 | } | |
139 | ||
140 | static void ath_rx_addbuffer_edma(struct ath_softc *sc, | |
141 | enum ath9k_rx_qtype qtype, int size) | |
142 | { | |
b5c80475 FF |
143 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
144 | u32 nbuf = 0; | |
145 | ||
b5c80475 | 146 | if (list_empty(&sc->rx.rxbuf)) { |
226afe68 | 147 | ath_dbg(common, ATH_DBG_QUEUE, "No free rx buf available\n"); |
b5c80475 | 148 | return; |
797fe5cb | 149 | } |
f078f209 | 150 | |
b5c80475 FF |
151 | while (!list_empty(&sc->rx.rxbuf)) { |
152 | nbuf++; | |
153 | ||
154 | if (!ath_rx_edma_buf_link(sc, qtype)) | |
155 | break; | |
156 | ||
157 | if (nbuf >= size) | |
158 | break; | |
159 | } | |
160 | } | |
161 | ||
162 | static void ath_rx_remove_buffer(struct ath_softc *sc, | |
163 | enum ath9k_rx_qtype qtype) | |
164 | { | |
165 | struct ath_buf *bf; | |
166 | struct ath_rx_edma *rx_edma; | |
167 | struct sk_buff *skb; | |
168 | ||
169 | rx_edma = &sc->rx.rx_edma[qtype]; | |
170 | ||
171 | while ((skb = skb_dequeue(&rx_edma->rx_fifo)) != NULL) { | |
172 | bf = SKB_CB_ATHBUF(skb); | |
173 | BUG_ON(!bf); | |
174 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
175 | } | |
176 | } | |
177 | ||
178 | static void ath_rx_edma_cleanup(struct ath_softc *sc) | |
179 | { | |
180 | struct ath_buf *bf; | |
181 | ||
182 | ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP); | |
183 | ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP); | |
184 | ||
797fe5cb | 185 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { |
b5c80475 FF |
186 | if (bf->bf_mpdu) |
187 | dev_kfree_skb_any(bf->bf_mpdu); | |
188 | } | |
189 | ||
190 | INIT_LIST_HEAD(&sc->rx.rxbuf); | |
191 | ||
192 | kfree(sc->rx.rx_bufptr); | |
193 | sc->rx.rx_bufptr = NULL; | |
194 | } | |
195 | ||
196 | static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size) | |
197 | { | |
198 | skb_queue_head_init(&rx_edma->rx_fifo); | |
199 | skb_queue_head_init(&rx_edma->rx_buffers); | |
200 | rx_edma->rx_fifo_hwsize = size; | |
201 | } | |
202 | ||
203 | static int ath_rx_edma_init(struct ath_softc *sc, int nbufs) | |
204 | { | |
205 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
206 | struct ath_hw *ah = sc->sc_ah; | |
207 | struct sk_buff *skb; | |
208 | struct ath_buf *bf; | |
209 | int error = 0, i; | |
210 | u32 size; | |
211 | ||
212 | ||
213 | common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN + | |
214 | ah->caps.rx_status_len, | |
215 | min(common->cachelsz, (u16)64)); | |
216 | ||
217 | ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - | |
218 | ah->caps.rx_status_len); | |
219 | ||
220 | ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP], | |
221 | ah->caps.rx_lp_qdepth); | |
222 | ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP], | |
223 | ah->caps.rx_hp_qdepth); | |
224 | ||
225 | size = sizeof(struct ath_buf) * nbufs; | |
226 | bf = kzalloc(size, GFP_KERNEL); | |
227 | if (!bf) | |
228 | return -ENOMEM; | |
229 | ||
230 | INIT_LIST_HEAD(&sc->rx.rxbuf); | |
231 | sc->rx.rx_bufptr = bf; | |
232 | ||
233 | for (i = 0; i < nbufs; i++, bf++) { | |
cc861f74 | 234 | skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL); |
b5c80475 | 235 | if (!skb) { |
797fe5cb | 236 | error = -ENOMEM; |
b5c80475 | 237 | goto rx_init_fail; |
f078f209 | 238 | } |
f078f209 | 239 | |
b5c80475 | 240 | memset(skb->data, 0, common->rx_bufsize); |
797fe5cb | 241 | bf->bf_mpdu = skb; |
b5c80475 | 242 | |
797fe5cb | 243 | bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, |
cc861f74 | 244 | common->rx_bufsize, |
b5c80475 | 245 | DMA_BIDIRECTIONAL); |
797fe5cb | 246 | if (unlikely(dma_mapping_error(sc->dev, |
b5c80475 FF |
247 | bf->bf_buf_addr))) { |
248 | dev_kfree_skb_any(skb); | |
249 | bf->bf_mpdu = NULL; | |
6cf9e995 | 250 | bf->bf_buf_addr = 0; |
3800276a | 251 | ath_err(common, |
b5c80475 FF |
252 | "dma_mapping_error() on RX init\n"); |
253 | error = -ENOMEM; | |
254 | goto rx_init_fail; | |
255 | } | |
256 | ||
257 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
258 | } | |
259 | ||
260 | return 0; | |
261 | ||
262 | rx_init_fail: | |
263 | ath_rx_edma_cleanup(sc); | |
264 | return error; | |
265 | } | |
266 | ||
267 | static void ath_edma_start_recv(struct ath_softc *sc) | |
268 | { | |
269 | spin_lock_bh(&sc->rx.rxbuflock); | |
270 | ||
271 | ath9k_hw_rxena(sc->sc_ah); | |
272 | ||
273 | ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP, | |
274 | sc->rx.rx_edma[ATH9K_RX_QUEUE_HP].rx_fifo_hwsize); | |
275 | ||
276 | ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP, | |
277 | sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize); | |
278 | ||
b5c80475 FF |
279 | ath_opmode_init(sc); |
280 | ||
48a6a468 | 281 | ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_OFFCHANNEL)); |
7583c550 LR |
282 | |
283 | spin_unlock_bh(&sc->rx.rxbuflock); | |
b5c80475 FF |
284 | } |
285 | ||
286 | static void ath_edma_stop_recv(struct ath_softc *sc) | |
287 | { | |
b5c80475 FF |
288 | ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP); |
289 | ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP); | |
b5c80475 FF |
290 | } |
291 | ||
292 | int ath_rx_init(struct ath_softc *sc, int nbufs) | |
293 | { | |
294 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
295 | struct sk_buff *skb; | |
296 | struct ath_buf *bf; | |
297 | int error = 0; | |
298 | ||
4bdd1e97 | 299 | spin_lock_init(&sc->sc_pcu_lock); |
b5c80475 FF |
300 | sc->sc_flags &= ~SC_OP_RXFLUSH; |
301 | spin_lock_init(&sc->rx.rxbuflock); | |
302 | ||
303 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { | |
304 | return ath_rx_edma_init(sc, nbufs); | |
305 | } else { | |
306 | common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN, | |
307 | min(common->cachelsz, (u16)64)); | |
308 | ||
226afe68 JP |
309 | ath_dbg(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n", |
310 | common->cachelsz, common->rx_bufsize); | |
b5c80475 FF |
311 | |
312 | /* Initialize rx descriptors */ | |
313 | ||
314 | error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf, | |
4adfcded | 315 | "rx", nbufs, 1, 0); |
b5c80475 | 316 | if (error != 0) { |
3800276a JP |
317 | ath_err(common, |
318 | "failed to allocate rx descriptors: %d\n", | |
319 | error); | |
797fe5cb S |
320 | goto err; |
321 | } | |
b5c80475 FF |
322 | |
323 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { | |
324 | skb = ath_rxbuf_alloc(common, common->rx_bufsize, | |
325 | GFP_KERNEL); | |
326 | if (skb == NULL) { | |
327 | error = -ENOMEM; | |
328 | goto err; | |
329 | } | |
330 | ||
331 | bf->bf_mpdu = skb; | |
332 | bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, | |
333 | common->rx_bufsize, | |
334 | DMA_FROM_DEVICE); | |
335 | if (unlikely(dma_mapping_error(sc->dev, | |
336 | bf->bf_buf_addr))) { | |
337 | dev_kfree_skb_any(skb); | |
338 | bf->bf_mpdu = NULL; | |
6cf9e995 | 339 | bf->bf_buf_addr = 0; |
3800276a JP |
340 | ath_err(common, |
341 | "dma_mapping_error() on RX init\n"); | |
b5c80475 FF |
342 | error = -ENOMEM; |
343 | goto err; | |
344 | } | |
b5c80475 FF |
345 | } |
346 | sc->rx.rxlink = NULL; | |
797fe5cb | 347 | } |
f078f209 | 348 | |
797fe5cb | 349 | err: |
f078f209 LR |
350 | if (error) |
351 | ath_rx_cleanup(sc); | |
352 | ||
353 | return error; | |
354 | } | |
355 | ||
f078f209 LR |
356 | void ath_rx_cleanup(struct ath_softc *sc) |
357 | { | |
cc861f74 LR |
358 | struct ath_hw *ah = sc->sc_ah; |
359 | struct ath_common *common = ath9k_hw_common(ah); | |
f078f209 LR |
360 | struct sk_buff *skb; |
361 | struct ath_buf *bf; | |
362 | ||
b5c80475 FF |
363 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
364 | ath_rx_edma_cleanup(sc); | |
365 | return; | |
366 | } else { | |
367 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { | |
368 | skb = bf->bf_mpdu; | |
369 | if (skb) { | |
370 | dma_unmap_single(sc->dev, bf->bf_buf_addr, | |
371 | common->rx_bufsize, | |
372 | DMA_FROM_DEVICE); | |
373 | dev_kfree_skb(skb); | |
6cf9e995 BG |
374 | bf->bf_buf_addr = 0; |
375 | bf->bf_mpdu = NULL; | |
b5c80475 | 376 | } |
051b9191 | 377 | } |
f078f209 | 378 | |
b5c80475 FF |
379 | if (sc->rx.rxdma.dd_desc_len != 0) |
380 | ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf); | |
381 | } | |
f078f209 LR |
382 | } |
383 | ||
384 | /* | |
385 | * Calculate the receive filter according to the | |
386 | * operating mode and state: | |
387 | * | |
388 | * o always accept unicast, broadcast, and multicast traffic | |
389 | * o maintain current state of phy error reception (the hal | |
390 | * may enable phy error frames for noise immunity work) | |
391 | * o probe request frames are accepted only when operating in | |
392 | * hostap, adhoc, or monitor modes | |
393 | * o enable promiscuous mode according to the interface state | |
394 | * o accept beacons: | |
395 | * - when operating in adhoc mode so the 802.11 layer creates | |
396 | * node table entries for peers, | |
397 | * - when operating in station mode for collecting rssi data when | |
398 | * the station is otherwise quiet, or | |
399 | * - when operating as a repeater so we see repeater-sta beacons | |
400 | * - when scanning | |
401 | */ | |
402 | ||
403 | u32 ath_calcrxfilter(struct ath_softc *sc) | |
404 | { | |
405 | #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR) | |
7dcfdcd9 | 406 | |
f078f209 LR |
407 | u32 rfilt; |
408 | ||
409 | rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE) | |
410 | | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST | |
411 | | ATH9K_RX_FILTER_MCAST; | |
412 | ||
9c1d8e4a | 413 | if (sc->rx.rxfilter & FIF_PROBE_REQ) |
f078f209 LR |
414 | rfilt |= ATH9K_RX_FILTER_PROBEREQ; |
415 | ||
217ba9da JM |
416 | /* |
417 | * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station | |
418 | * mode interface or when in monitor mode. AP mode does not need this | |
419 | * since it receives all in-BSS frames anyway. | |
420 | */ | |
2660b81a | 421 | if (((sc->sc_ah->opmode != NL80211_IFTYPE_AP) && |
b77f483f | 422 | (sc->rx.rxfilter & FIF_PROMISC_IN_BSS)) || |
5f841b41 | 423 | (sc->sc_ah->is_monitoring)) |
f078f209 | 424 | rfilt |= ATH9K_RX_FILTER_PROM; |
f078f209 | 425 | |
d42c6b71 S |
426 | if (sc->rx.rxfilter & FIF_CONTROL) |
427 | rfilt |= ATH9K_RX_FILTER_CONTROL; | |
428 | ||
dbaaa147 | 429 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) && |
cfda6695 | 430 | (sc->nvifs <= 1) && |
dbaaa147 VT |
431 | !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)) |
432 | rfilt |= ATH9K_RX_FILTER_MYBEACON; | |
433 | else | |
f078f209 LR |
434 | rfilt |= ATH9K_RX_FILTER_BEACON; |
435 | ||
7a37081e | 436 | if ((AR_SREV_9280_20_OR_LATER(sc->sc_ah) || |
e17f83ea | 437 | AR_SREV_9285_12_OR_LATER(sc->sc_ah)) && |
66afad01 SB |
438 | (sc->sc_ah->opmode == NL80211_IFTYPE_AP) && |
439 | (sc->rx.rxfilter & FIF_PSPOLL)) | |
dbaaa147 | 440 | rfilt |= ATH9K_RX_FILTER_PSPOLL; |
be0418ad | 441 | |
7ea310be S |
442 | if (conf_is_ht(&sc->hw->conf)) |
443 | rfilt |= ATH9K_RX_FILTER_COMP_BAR; | |
444 | ||
7545daf4 | 445 | if (sc->nvifs > 1 || (sc->rx.rxfilter & FIF_OTHER_BSS)) { |
5eb6ba83 JC |
446 | /* The following may also be needed for other older chips */ |
447 | if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160) | |
448 | rfilt |= ATH9K_RX_FILTER_PROM; | |
b93bce2a JM |
449 | rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL; |
450 | } | |
451 | ||
f078f209 | 452 | return rfilt; |
7dcfdcd9 | 453 | |
f078f209 LR |
454 | #undef RX_FILTER_PRESERVE |
455 | } | |
456 | ||
f078f209 LR |
457 | int ath_startrecv(struct ath_softc *sc) |
458 | { | |
cbe61d8a | 459 | struct ath_hw *ah = sc->sc_ah; |
f078f209 LR |
460 | struct ath_buf *bf, *tbf; |
461 | ||
b5c80475 FF |
462 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
463 | ath_edma_start_recv(sc); | |
464 | return 0; | |
465 | } | |
466 | ||
b77f483f S |
467 | spin_lock_bh(&sc->rx.rxbuflock); |
468 | if (list_empty(&sc->rx.rxbuf)) | |
f078f209 LR |
469 | goto start_recv; |
470 | ||
b77f483f S |
471 | sc->rx.rxlink = NULL; |
472 | list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) { | |
f078f209 LR |
473 | ath_rx_buf_link(sc, bf); |
474 | } | |
475 | ||
476 | /* We could have deleted elements so the list may be empty now */ | |
b77f483f | 477 | if (list_empty(&sc->rx.rxbuf)) |
f078f209 LR |
478 | goto start_recv; |
479 | ||
b77f483f | 480 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); |
f078f209 | 481 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); |
be0418ad | 482 | ath9k_hw_rxena(ah); |
f078f209 LR |
483 | |
484 | start_recv: | |
be0418ad | 485 | ath_opmode_init(sc); |
48a6a468 | 486 | ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_OFFCHANNEL)); |
be0418ad | 487 | |
7583c550 LR |
488 | spin_unlock_bh(&sc->rx.rxbuflock); |
489 | ||
f078f209 LR |
490 | return 0; |
491 | } | |
492 | ||
f078f209 LR |
493 | bool ath_stoprecv(struct ath_softc *sc) |
494 | { | |
cbe61d8a | 495 | struct ath_hw *ah = sc->sc_ah; |
f078f209 LR |
496 | bool stopped; |
497 | ||
1e450285 | 498 | spin_lock_bh(&sc->rx.rxbuflock); |
d47844a0 | 499 | ath9k_hw_abortpcurecv(ah); |
be0418ad S |
500 | ath9k_hw_setrxfilter(ah, 0); |
501 | stopped = ath9k_hw_stopdmarecv(ah); | |
b5c80475 FF |
502 | |
503 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
504 | ath_edma_stop_recv(sc); | |
505 | else | |
506 | sc->rx.rxlink = NULL; | |
1e450285 | 507 | spin_unlock_bh(&sc->rx.rxbuflock); |
be0418ad | 508 | |
d584747b RM |
509 | if (!(ah->ah_flags & AH_UNPLUGGED) && |
510 | unlikely(!stopped)) { | |
d7fd1b50 BG |
511 | ath_err(ath9k_hw_common(sc->sc_ah), |
512 | "Could not stop RX, we could be " | |
513 | "confusing the DMA engine when we start RX up\n"); | |
514 | ATH_DBG_WARN_ON_ONCE(!stopped); | |
515 | } | |
f078f209 LR |
516 | return stopped; |
517 | } | |
518 | ||
f078f209 LR |
519 | void ath_flushrecv(struct ath_softc *sc) |
520 | { | |
98deeea0 | 521 | sc->sc_flags |= SC_OP_RXFLUSH; |
b5c80475 FF |
522 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
523 | ath_rx_tasklet(sc, 1, true); | |
524 | ath_rx_tasklet(sc, 1, false); | |
98deeea0 | 525 | sc->sc_flags &= ~SC_OP_RXFLUSH; |
f078f209 LR |
526 | } |
527 | ||
cc65965c JM |
528 | static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb) |
529 | { | |
530 | /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */ | |
531 | struct ieee80211_mgmt *mgmt; | |
532 | u8 *pos, *end, id, elen; | |
533 | struct ieee80211_tim_ie *tim; | |
534 | ||
535 | mgmt = (struct ieee80211_mgmt *)skb->data; | |
536 | pos = mgmt->u.beacon.variable; | |
537 | end = skb->data + skb->len; | |
538 | ||
539 | while (pos + 2 < end) { | |
540 | id = *pos++; | |
541 | elen = *pos++; | |
542 | if (pos + elen > end) | |
543 | break; | |
544 | ||
545 | if (id == WLAN_EID_TIM) { | |
546 | if (elen < sizeof(*tim)) | |
547 | break; | |
548 | tim = (struct ieee80211_tim_ie *) pos; | |
549 | if (tim->dtim_count != 0) | |
550 | break; | |
551 | return tim->bitmap_ctrl & 0x01; | |
552 | } | |
553 | ||
554 | pos += elen; | |
555 | } | |
556 | ||
557 | return false; | |
558 | } | |
559 | ||
cc65965c JM |
560 | static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb) |
561 | { | |
562 | struct ieee80211_mgmt *mgmt; | |
1510718d | 563 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
cc65965c JM |
564 | |
565 | if (skb->len < 24 + 8 + 2 + 2) | |
566 | return; | |
567 | ||
568 | mgmt = (struct ieee80211_mgmt *)skb->data; | |
4801416c BG |
569 | if (memcmp(common->curbssid, mgmt->bssid, ETH_ALEN) != 0) { |
570 | /* TODO: This doesn't work well if you have stations | |
571 | * associated to two different APs because curbssid | |
572 | * is just the last AP that any of the stations associated | |
573 | * with. | |
574 | */ | |
cc65965c | 575 | return; /* not from our current AP */ |
4801416c | 576 | } |
cc65965c | 577 | |
1b04b930 | 578 | sc->ps_flags &= ~PS_WAIT_FOR_BEACON; |
293dc5df | 579 | |
1b04b930 S |
580 | if (sc->ps_flags & PS_BEACON_SYNC) { |
581 | sc->ps_flags &= ~PS_BEACON_SYNC; | |
226afe68 JP |
582 | ath_dbg(common, ATH_DBG_PS, |
583 | "Reconfigure Beacon timers based on timestamp from the AP\n"); | |
ccdfeab6 JM |
584 | ath_beacon_config(sc, NULL); |
585 | } | |
586 | ||
cc65965c JM |
587 | if (ath_beacon_dtim_pending_cab(skb)) { |
588 | /* | |
589 | * Remain awake waiting for buffered broadcast/multicast | |
58f5fffd GJ |
590 | * frames. If the last broadcast/multicast frame is not |
591 | * received properly, the next beacon frame will work as | |
592 | * a backup trigger for returning into NETWORK SLEEP state, | |
593 | * so we are waiting for it as well. | |
cc65965c | 594 | */ |
226afe68 JP |
595 | ath_dbg(common, ATH_DBG_PS, |
596 | "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n"); | |
1b04b930 | 597 | sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON; |
cc65965c JM |
598 | return; |
599 | } | |
600 | ||
1b04b930 | 601 | if (sc->ps_flags & PS_WAIT_FOR_CAB) { |
cc65965c JM |
602 | /* |
603 | * This can happen if a broadcast frame is dropped or the AP | |
604 | * fails to send a frame indicating that all CAB frames have | |
605 | * been delivered. | |
606 | */ | |
1b04b930 | 607 | sc->ps_flags &= ~PS_WAIT_FOR_CAB; |
226afe68 JP |
608 | ath_dbg(common, ATH_DBG_PS, |
609 | "PS wait for CAB frames timed out\n"); | |
cc65965c | 610 | } |
cc65965c JM |
611 | } |
612 | ||
613 | static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb) | |
614 | { | |
615 | struct ieee80211_hdr *hdr; | |
c46917bb | 616 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
cc65965c JM |
617 | |
618 | hdr = (struct ieee80211_hdr *)skb->data; | |
619 | ||
620 | /* Process Beacon and CAB receive in PS state */ | |
ededf1f8 VT |
621 | if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc)) |
622 | && ieee80211_is_beacon(hdr->frame_control)) | |
cc65965c | 623 | ath_rx_ps_beacon(sc, skb); |
1b04b930 | 624 | else if ((sc->ps_flags & PS_WAIT_FOR_CAB) && |
cc65965c JM |
625 | (ieee80211_is_data(hdr->frame_control) || |
626 | ieee80211_is_action(hdr->frame_control)) && | |
627 | is_multicast_ether_addr(hdr->addr1) && | |
628 | !ieee80211_has_moredata(hdr->frame_control)) { | |
cc65965c JM |
629 | /* |
630 | * No more broadcast/multicast frames to be received at this | |
631 | * point. | |
632 | */ | |
3fac6dfd | 633 | sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON); |
226afe68 JP |
634 | ath_dbg(common, ATH_DBG_PS, |
635 | "All PS CAB frames received, back to sleep\n"); | |
1b04b930 | 636 | } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) && |
9a23f9ca JM |
637 | !is_multicast_ether_addr(hdr->addr1) && |
638 | !ieee80211_has_morefrags(hdr->frame_control)) { | |
1b04b930 | 639 | sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA; |
226afe68 JP |
640 | ath_dbg(common, ATH_DBG_PS, |
641 | "Going back to sleep after having received PS-Poll data (0x%lx)\n", | |
1b04b930 S |
642 | sc->ps_flags & (PS_WAIT_FOR_BEACON | |
643 | PS_WAIT_FOR_CAB | | |
644 | PS_WAIT_FOR_PSPOLL_DATA | | |
645 | PS_WAIT_FOR_TX_ACK)); | |
cc65965c JM |
646 | } |
647 | } | |
648 | ||
b5c80475 FF |
649 | static bool ath_edma_get_buffers(struct ath_softc *sc, |
650 | enum ath9k_rx_qtype qtype) | |
f078f209 | 651 | { |
b5c80475 FF |
652 | struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype]; |
653 | struct ath_hw *ah = sc->sc_ah; | |
654 | struct ath_common *common = ath9k_hw_common(ah); | |
655 | struct sk_buff *skb; | |
656 | struct ath_buf *bf; | |
657 | int ret; | |
658 | ||
659 | skb = skb_peek(&rx_edma->rx_fifo); | |
660 | if (!skb) | |
661 | return false; | |
662 | ||
663 | bf = SKB_CB_ATHBUF(skb); | |
664 | BUG_ON(!bf); | |
665 | ||
ce9426d1 | 666 | dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr, |
b5c80475 FF |
667 | common->rx_bufsize, DMA_FROM_DEVICE); |
668 | ||
669 | ret = ath9k_hw_process_rxdesc_edma(ah, NULL, skb->data); | |
ce9426d1 ML |
670 | if (ret == -EINPROGRESS) { |
671 | /*let device gain the buffer again*/ | |
672 | dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, | |
673 | common->rx_bufsize, DMA_FROM_DEVICE); | |
b5c80475 | 674 | return false; |
ce9426d1 | 675 | } |
b5c80475 FF |
676 | |
677 | __skb_unlink(skb, &rx_edma->rx_fifo); | |
678 | if (ret == -EINVAL) { | |
679 | /* corrupt descriptor, skip this one and the following one */ | |
680 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
681 | ath_rx_edma_buf_link(sc, qtype); | |
682 | skb = skb_peek(&rx_edma->rx_fifo); | |
683 | if (!skb) | |
684 | return true; | |
685 | ||
686 | bf = SKB_CB_ATHBUF(skb); | |
687 | BUG_ON(!bf); | |
688 | ||
689 | __skb_unlink(skb, &rx_edma->rx_fifo); | |
690 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
691 | ath_rx_edma_buf_link(sc, qtype); | |
083e3e8d | 692 | return true; |
b5c80475 FF |
693 | } |
694 | skb_queue_tail(&rx_edma->rx_buffers, skb); | |
695 | ||
696 | return true; | |
697 | } | |
f078f209 | 698 | |
b5c80475 FF |
699 | static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc, |
700 | struct ath_rx_status *rs, | |
701 | enum ath9k_rx_qtype qtype) | |
702 | { | |
703 | struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype]; | |
704 | struct sk_buff *skb; | |
be0418ad | 705 | struct ath_buf *bf; |
b5c80475 FF |
706 | |
707 | while (ath_edma_get_buffers(sc, qtype)); | |
708 | skb = __skb_dequeue(&rx_edma->rx_buffers); | |
709 | if (!skb) | |
710 | return NULL; | |
711 | ||
712 | bf = SKB_CB_ATHBUF(skb); | |
713 | ath9k_hw_process_rxdesc_edma(sc->sc_ah, rs, skb->data); | |
714 | return bf; | |
715 | } | |
716 | ||
717 | static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc, | |
718 | struct ath_rx_status *rs) | |
719 | { | |
720 | struct ath_hw *ah = sc->sc_ah; | |
721 | struct ath_common *common = ath9k_hw_common(ah); | |
f078f209 | 722 | struct ath_desc *ds; |
b5c80475 FF |
723 | struct ath_buf *bf; |
724 | int ret; | |
725 | ||
726 | if (list_empty(&sc->rx.rxbuf)) { | |
727 | sc->rx.rxlink = NULL; | |
728 | return NULL; | |
729 | } | |
730 | ||
731 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); | |
732 | ds = bf->bf_desc; | |
733 | ||
734 | /* | |
735 | * Must provide the virtual address of the current | |
736 | * descriptor, the physical address, and the virtual | |
737 | * address of the next descriptor in the h/w chain. | |
738 | * This allows the HAL to look ahead to see if the | |
739 | * hardware is done with a descriptor by checking the | |
740 | * done bit in the following descriptor and the address | |
741 | * of the current descriptor the DMA engine is working | |
742 | * on. All this is necessary because of our use of | |
743 | * a self-linked list to avoid rx overruns. | |
744 | */ | |
745 | ret = ath9k_hw_rxprocdesc(ah, ds, rs, 0); | |
746 | if (ret == -EINPROGRESS) { | |
747 | struct ath_rx_status trs; | |
748 | struct ath_buf *tbf; | |
749 | struct ath_desc *tds; | |
750 | ||
751 | memset(&trs, 0, sizeof(trs)); | |
752 | if (list_is_last(&bf->list, &sc->rx.rxbuf)) { | |
753 | sc->rx.rxlink = NULL; | |
754 | return NULL; | |
755 | } | |
756 | ||
757 | tbf = list_entry(bf->list.next, struct ath_buf, list); | |
758 | ||
759 | /* | |
760 | * On some hardware the descriptor status words could | |
761 | * get corrupted, including the done bit. Because of | |
762 | * this, check if the next descriptor's done bit is | |
763 | * set or not. | |
764 | * | |
765 | * If the next descriptor's done bit is set, the current | |
766 | * descriptor has been corrupted. Force s/w to discard | |
767 | * this descriptor and continue... | |
768 | */ | |
769 | ||
770 | tds = tbf->bf_desc; | |
771 | ret = ath9k_hw_rxprocdesc(ah, tds, &trs, 0); | |
772 | if (ret == -EINPROGRESS) | |
773 | return NULL; | |
774 | } | |
775 | ||
776 | if (!bf->bf_mpdu) | |
777 | return bf; | |
778 | ||
779 | /* | |
780 | * Synchronize the DMA transfer with CPU before | |
781 | * 1. accessing the frame | |
782 | * 2. requeueing the same buffer to h/w | |
783 | */ | |
ce9426d1 | 784 | dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr, |
b5c80475 FF |
785 | common->rx_bufsize, |
786 | DMA_FROM_DEVICE); | |
787 | ||
788 | return bf; | |
789 | } | |
790 | ||
d435700f S |
791 | /* Assumes you've already done the endian to CPU conversion */ |
792 | static bool ath9k_rx_accept(struct ath_common *common, | |
9f167f64 | 793 | struct ieee80211_hdr *hdr, |
d435700f S |
794 | struct ieee80211_rx_status *rxs, |
795 | struct ath_rx_status *rx_stats, | |
796 | bool *decrypt_error) | |
797 | { | |
38852b20 SB |
798 | #define is_mc_or_valid_tkip_keyix ((is_mc || \ |
799 | (rx_stats->rs_keyix != ATH9K_RXKEYIX_INVALID && \ | |
800 | test_bit(rx_stats->rs_keyix, common->tkip_keymap)))) | |
801 | ||
d435700f | 802 | struct ath_hw *ah = common->ah; |
d435700f | 803 | __le16 fc; |
b7b1b512 | 804 | u8 rx_status_len = ah->caps.rx_status_len; |
d435700f | 805 | |
d435700f S |
806 | fc = hdr->frame_control; |
807 | ||
808 | if (!rx_stats->rs_datalen) | |
809 | return false; | |
810 | /* | |
811 | * rs_status follows rs_datalen so if rs_datalen is too large | |
812 | * we can take a hint that hardware corrupted it, so ignore | |
813 | * those frames. | |
814 | */ | |
b7b1b512 | 815 | if (rx_stats->rs_datalen > (common->rx_bufsize - rx_status_len)) |
d435700f S |
816 | return false; |
817 | ||
818 | /* | |
819 | * rs_more indicates chained descriptors which can be used | |
820 | * to link buffers together for a sort of scatter-gather | |
821 | * operation. | |
822 | * reject the frame, we don't support scatter-gather yet and | |
823 | * the frame is probably corrupt anyway | |
824 | */ | |
825 | if (rx_stats->rs_more) | |
826 | return false; | |
827 | ||
828 | /* | |
829 | * The rx_stats->rs_status will not be set until the end of the | |
830 | * chained descriptors so it can be ignored if rs_more is set. The | |
831 | * rs_more will be false at the last element of the chained | |
832 | * descriptors. | |
833 | */ | |
834 | if (rx_stats->rs_status != 0) { | |
835 | if (rx_stats->rs_status & ATH9K_RXERR_CRC) | |
836 | rxs->flag |= RX_FLAG_FAILED_FCS_CRC; | |
837 | if (rx_stats->rs_status & ATH9K_RXERR_PHY) | |
838 | return false; | |
839 | ||
840 | if (rx_stats->rs_status & ATH9K_RXERR_DECRYPT) { | |
841 | *decrypt_error = true; | |
842 | } else if (rx_stats->rs_status & ATH9K_RXERR_MIC) { | |
38852b20 | 843 | bool is_mc; |
56363dde FF |
844 | /* |
845 | * The MIC error bit is only valid if the frame | |
846 | * is not a control frame or fragment, and it was | |
847 | * decrypted using a valid TKIP key. | |
848 | */ | |
38852b20 SB |
849 | is_mc = !!is_multicast_ether_addr(hdr->addr1); |
850 | ||
56363dde FF |
851 | if (!ieee80211_is_ctl(fc) && |
852 | !ieee80211_has_morefrags(fc) && | |
853 | !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) && | |
38852b20 | 854 | is_mc_or_valid_tkip_keyix) |
d435700f | 855 | rxs->flag |= RX_FLAG_MMIC_ERROR; |
56363dde FF |
856 | else |
857 | rx_stats->rs_status &= ~ATH9K_RXERR_MIC; | |
d435700f S |
858 | } |
859 | /* | |
860 | * Reject error frames with the exception of | |
861 | * decryption and MIC failures. For monitor mode, | |
862 | * we also ignore the CRC error. | |
863 | */ | |
5f841b41 | 864 | if (ah->is_monitoring) { |
d435700f S |
865 | if (rx_stats->rs_status & |
866 | ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC | | |
867 | ATH9K_RXERR_CRC)) | |
868 | return false; | |
869 | } else { | |
870 | if (rx_stats->rs_status & | |
871 | ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) { | |
872 | return false; | |
873 | } | |
874 | } | |
875 | } | |
876 | return true; | |
877 | } | |
878 | ||
879 | static int ath9k_process_rate(struct ath_common *common, | |
880 | struct ieee80211_hw *hw, | |
881 | struct ath_rx_status *rx_stats, | |
9f167f64 | 882 | struct ieee80211_rx_status *rxs) |
d435700f S |
883 | { |
884 | struct ieee80211_supported_band *sband; | |
885 | enum ieee80211_band band; | |
886 | unsigned int i = 0; | |
887 | ||
888 | band = hw->conf.channel->band; | |
889 | sband = hw->wiphy->bands[band]; | |
890 | ||
891 | if (rx_stats->rs_rate & 0x80) { | |
892 | /* HT rate */ | |
893 | rxs->flag |= RX_FLAG_HT; | |
894 | if (rx_stats->rs_flags & ATH9K_RX_2040) | |
895 | rxs->flag |= RX_FLAG_40MHZ; | |
896 | if (rx_stats->rs_flags & ATH9K_RX_GI) | |
897 | rxs->flag |= RX_FLAG_SHORT_GI; | |
898 | rxs->rate_idx = rx_stats->rs_rate & 0x7f; | |
899 | return 0; | |
900 | } | |
901 | ||
902 | for (i = 0; i < sband->n_bitrates; i++) { | |
903 | if (sband->bitrates[i].hw_value == rx_stats->rs_rate) { | |
904 | rxs->rate_idx = i; | |
905 | return 0; | |
906 | } | |
907 | if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) { | |
908 | rxs->flag |= RX_FLAG_SHORTPRE; | |
909 | rxs->rate_idx = i; | |
910 | return 0; | |
911 | } | |
912 | } | |
913 | ||
914 | /* | |
915 | * No valid hardware bitrate found -- we should not get here | |
916 | * because hardware has already validated this frame as OK. | |
917 | */ | |
226afe68 JP |
918 | ath_dbg(common, ATH_DBG_XMIT, |
919 | "unsupported hw bitrate detected 0x%02x using 1 Mbit\n", | |
920 | rx_stats->rs_rate); | |
d435700f S |
921 | |
922 | return -EINVAL; | |
923 | } | |
924 | ||
925 | static void ath9k_process_rssi(struct ath_common *common, | |
926 | struct ieee80211_hw *hw, | |
9f167f64 | 927 | struct ieee80211_hdr *hdr, |
d435700f S |
928 | struct ath_rx_status *rx_stats) |
929 | { | |
9fa23e17 | 930 | struct ath_wiphy *aphy = hw->priv; |
d435700f | 931 | struct ath_hw *ah = common->ah; |
9fa23e17 | 932 | int last_rssi; |
d435700f S |
933 | __le16 fc; |
934 | ||
9fa23e17 FF |
935 | if (ah->opmode != NL80211_IFTYPE_STATION) |
936 | return; | |
937 | ||
d435700f | 938 | fc = hdr->frame_control; |
9fa23e17 | 939 | if (!ieee80211_is_beacon(fc) || |
4801416c BG |
940 | compare_ether_addr(hdr->addr3, common->curbssid)) { |
941 | /* TODO: This doesn't work well if you have stations | |
942 | * associated to two different APs because curbssid | |
943 | * is just the last AP that any of the stations associated | |
944 | * with. | |
945 | */ | |
9fa23e17 | 946 | return; |
4801416c | 947 | } |
d435700f | 948 | |
9fa23e17 FF |
949 | if (rx_stats->rs_rssi != ATH9K_RSSI_BAD && !rx_stats->rs_moreaggr) |
950 | ATH_RSSI_LPF(aphy->last_rssi, rx_stats->rs_rssi); | |
d435700f | 951 | |
9fa23e17 | 952 | last_rssi = aphy->last_rssi; |
d435700f S |
953 | if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER)) |
954 | rx_stats->rs_rssi = ATH_EP_RND(last_rssi, | |
955 | ATH_RSSI_EP_MULTIPLIER); | |
956 | if (rx_stats->rs_rssi < 0) | |
957 | rx_stats->rs_rssi = 0; | |
958 | ||
959 | /* Update Beacon RSSI, this is used by ANI. */ | |
9fa23e17 | 960 | ah->stats.avgbrssi = rx_stats->rs_rssi; |
d435700f S |
961 | } |
962 | ||
963 | /* | |
964 | * For Decrypt or Demic errors, we only mark packet status here and always push | |
965 | * up the frame up to let mac80211 handle the actual error case, be it no | |
966 | * decryption key or real decryption error. This let us keep statistics there. | |
967 | */ | |
968 | static int ath9k_rx_skb_preprocess(struct ath_common *common, | |
969 | struct ieee80211_hw *hw, | |
9f167f64 | 970 | struct ieee80211_hdr *hdr, |
d435700f S |
971 | struct ath_rx_status *rx_stats, |
972 | struct ieee80211_rx_status *rx_status, | |
973 | bool *decrypt_error) | |
974 | { | |
d435700f S |
975 | memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); |
976 | ||
977 | /* | |
978 | * everything but the rate is checked here, the rate check is done | |
979 | * separately to avoid doing two lookups for a rate for each frame. | |
980 | */ | |
9f167f64 | 981 | if (!ath9k_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error)) |
d435700f S |
982 | return -EINVAL; |
983 | ||
9f167f64 | 984 | ath9k_process_rssi(common, hw, hdr, rx_stats); |
d435700f | 985 | |
9f167f64 | 986 | if (ath9k_process_rate(common, hw, rx_stats, rx_status)) |
d435700f S |
987 | return -EINVAL; |
988 | ||
d435700f S |
989 | rx_status->band = hw->conf.channel->band; |
990 | rx_status->freq = hw->conf.channel->center_freq; | |
991 | rx_status->signal = ATH_DEFAULT_NOISE_FLOOR + rx_stats->rs_rssi; | |
992 | rx_status->antenna = rx_stats->rs_antenna; | |
993 | rx_status->flag |= RX_FLAG_TSFT; | |
994 | ||
995 | return 0; | |
996 | } | |
997 | ||
998 | static void ath9k_rx_skb_postprocess(struct ath_common *common, | |
999 | struct sk_buff *skb, | |
1000 | struct ath_rx_status *rx_stats, | |
1001 | struct ieee80211_rx_status *rxs, | |
1002 | bool decrypt_error) | |
1003 | { | |
1004 | struct ath_hw *ah = common->ah; | |
1005 | struct ieee80211_hdr *hdr; | |
1006 | int hdrlen, padpos, padsize; | |
1007 | u8 keyix; | |
1008 | __le16 fc; | |
1009 | ||
1010 | /* see if any padding is done by the hw and remove it */ | |
1011 | hdr = (struct ieee80211_hdr *) skb->data; | |
1012 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); | |
1013 | fc = hdr->frame_control; | |
1014 | padpos = ath9k_cmn_padpos(hdr->frame_control); | |
1015 | ||
1016 | /* The MAC header is padded to have 32-bit boundary if the | |
1017 | * packet payload is non-zero. The general calculation for | |
1018 | * padsize would take into account odd header lengths: | |
1019 | * padsize = (4 - padpos % 4) % 4; However, since only | |
1020 | * even-length headers are used, padding can only be 0 or 2 | |
1021 | * bytes and we can optimize this a bit. In addition, we must | |
1022 | * not try to remove padding from short control frames that do | |
1023 | * not have payload. */ | |
1024 | padsize = padpos & 3; | |
1025 | if (padsize && skb->len>=padpos+padsize+FCS_LEN) { | |
1026 | memmove(skb->data + padsize, skb->data, padpos); | |
1027 | skb_pull(skb, padsize); | |
1028 | } | |
1029 | ||
1030 | keyix = rx_stats->rs_keyix; | |
1031 | ||
1032 | if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error && | |
1033 | ieee80211_has_protected(fc)) { | |
1034 | rxs->flag |= RX_FLAG_DECRYPTED; | |
1035 | } else if (ieee80211_has_protected(fc) | |
1036 | && !decrypt_error && skb->len >= hdrlen + 4) { | |
1037 | keyix = skb->data[hdrlen + 3] >> 6; | |
1038 | ||
1039 | if (test_bit(keyix, common->keymap)) | |
1040 | rxs->flag |= RX_FLAG_DECRYPTED; | |
1041 | } | |
1042 | if (ah->sw_mgmt_crypto && | |
1043 | (rxs->flag & RX_FLAG_DECRYPTED) && | |
1044 | ieee80211_is_mgmt(fc)) | |
1045 | /* Use software decrypt for management frames. */ | |
1046 | rxs->flag &= ~RX_FLAG_DECRYPTED; | |
1047 | } | |
b5c80475 | 1048 | |
102885a5 VT |
1049 | static void ath_lnaconf_alt_good_scan(struct ath_ant_comb *antcomb, |
1050 | struct ath_hw_antcomb_conf ant_conf, | |
1051 | int main_rssi_avg) | |
1052 | { | |
1053 | antcomb->quick_scan_cnt = 0; | |
1054 | ||
1055 | if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA2) | |
1056 | antcomb->rssi_lna2 = main_rssi_avg; | |
1057 | else if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA1) | |
1058 | antcomb->rssi_lna1 = main_rssi_avg; | |
1059 | ||
1060 | switch ((ant_conf.main_lna_conf << 4) | ant_conf.alt_lna_conf) { | |
1061 | case (0x10): /* LNA2 A-B */ | |
1062 | antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; | |
1063 | antcomb->first_quick_scan_conf = | |
1064 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; | |
1065 | antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1; | |
1066 | break; | |
1067 | case (0x20): /* LNA1 A-B */ | |
1068 | antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; | |
1069 | antcomb->first_quick_scan_conf = | |
1070 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; | |
1071 | antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2; | |
1072 | break; | |
1073 | case (0x21): /* LNA1 LNA2 */ | |
1074 | antcomb->main_conf = ATH_ANT_DIV_COMB_LNA2; | |
1075 | antcomb->first_quick_scan_conf = | |
1076 | ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; | |
1077 | antcomb->second_quick_scan_conf = | |
1078 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; | |
1079 | break; | |
1080 | case (0x12): /* LNA2 LNA1 */ | |
1081 | antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1; | |
1082 | antcomb->first_quick_scan_conf = | |
1083 | ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; | |
1084 | antcomb->second_quick_scan_conf = | |
1085 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; | |
1086 | break; | |
1087 | case (0x13): /* LNA2 A+B */ | |
1088 | antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; | |
1089 | antcomb->first_quick_scan_conf = | |
1090 | ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; | |
1091 | antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1; | |
1092 | break; | |
1093 | case (0x23): /* LNA1 A+B */ | |
1094 | antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; | |
1095 | antcomb->first_quick_scan_conf = | |
1096 | ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; | |
1097 | antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2; | |
1098 | break; | |
1099 | default: | |
1100 | break; | |
1101 | } | |
1102 | } | |
1103 | ||
1104 | static void ath_select_ant_div_from_quick_scan(struct ath_ant_comb *antcomb, | |
1105 | struct ath_hw_antcomb_conf *div_ant_conf, | |
1106 | int main_rssi_avg, int alt_rssi_avg, | |
1107 | int alt_ratio) | |
1108 | { | |
1109 | /* alt_good */ | |
1110 | switch (antcomb->quick_scan_cnt) { | |
1111 | case 0: | |
1112 | /* set alt to main, and alt to first conf */ | |
1113 | div_ant_conf->main_lna_conf = antcomb->main_conf; | |
1114 | div_ant_conf->alt_lna_conf = antcomb->first_quick_scan_conf; | |
1115 | break; | |
1116 | case 1: | |
1117 | /* set alt to main, and alt to first conf */ | |
1118 | div_ant_conf->main_lna_conf = antcomb->main_conf; | |
1119 | div_ant_conf->alt_lna_conf = antcomb->second_quick_scan_conf; | |
1120 | antcomb->rssi_first = main_rssi_avg; | |
1121 | antcomb->rssi_second = alt_rssi_avg; | |
1122 | ||
1123 | if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) { | |
1124 | /* main is LNA1 */ | |
1125 | if (ath_is_alt_ant_ratio_better(alt_ratio, | |
1126 | ATH_ANT_DIV_COMB_LNA1_DELTA_HI, | |
1127 | ATH_ANT_DIV_COMB_LNA1_DELTA_LOW, | |
1128 | main_rssi_avg, alt_rssi_avg, | |
1129 | antcomb->total_pkt_count)) | |
1130 | antcomb->first_ratio = true; | |
1131 | else | |
1132 | antcomb->first_ratio = false; | |
1133 | } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) { | |
1134 | if (ath_is_alt_ant_ratio_better(alt_ratio, | |
1135 | ATH_ANT_DIV_COMB_LNA1_DELTA_MID, | |
1136 | ATH_ANT_DIV_COMB_LNA1_DELTA_LOW, | |
1137 | main_rssi_avg, alt_rssi_avg, | |
1138 | antcomb->total_pkt_count)) | |
1139 | antcomb->first_ratio = true; | |
1140 | else | |
1141 | antcomb->first_ratio = false; | |
1142 | } else { | |
1143 | if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) && | |
1144 | (alt_rssi_avg > main_rssi_avg + | |
1145 | ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) || | |
1146 | (alt_rssi_avg > main_rssi_avg)) && | |
1147 | (antcomb->total_pkt_count > 50)) | |
1148 | antcomb->first_ratio = true; | |
1149 | else | |
1150 | antcomb->first_ratio = false; | |
1151 | } | |
1152 | break; | |
1153 | case 2: | |
1154 | antcomb->alt_good = false; | |
1155 | antcomb->scan_not_start = false; | |
1156 | antcomb->scan = false; | |
1157 | antcomb->rssi_first = main_rssi_avg; | |
1158 | antcomb->rssi_third = alt_rssi_avg; | |
1159 | ||
1160 | if (antcomb->second_quick_scan_conf == ATH_ANT_DIV_COMB_LNA1) | |
1161 | antcomb->rssi_lna1 = alt_rssi_avg; | |
1162 | else if (antcomb->second_quick_scan_conf == | |
1163 | ATH_ANT_DIV_COMB_LNA2) | |
1164 | antcomb->rssi_lna2 = alt_rssi_avg; | |
1165 | else if (antcomb->second_quick_scan_conf == | |
1166 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2) { | |
1167 | if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) | |
1168 | antcomb->rssi_lna2 = main_rssi_avg; | |
1169 | else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) | |
1170 | antcomb->rssi_lna1 = main_rssi_avg; | |
1171 | } | |
1172 | ||
1173 | if (antcomb->rssi_lna2 > antcomb->rssi_lna1 + | |
1174 | ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA) | |
1175 | div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA2; | |
1176 | else | |
1177 | div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA1; | |
1178 | ||
1179 | if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) { | |
1180 | if (ath_is_alt_ant_ratio_better(alt_ratio, | |
1181 | ATH_ANT_DIV_COMB_LNA1_DELTA_HI, | |
1182 | ATH_ANT_DIV_COMB_LNA1_DELTA_LOW, | |
1183 | main_rssi_avg, alt_rssi_avg, | |
1184 | antcomb->total_pkt_count)) | |
1185 | antcomb->second_ratio = true; | |
1186 | else | |
1187 | antcomb->second_ratio = false; | |
1188 | } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) { | |
1189 | if (ath_is_alt_ant_ratio_better(alt_ratio, | |
1190 | ATH_ANT_DIV_COMB_LNA1_DELTA_MID, | |
1191 | ATH_ANT_DIV_COMB_LNA1_DELTA_LOW, | |
1192 | main_rssi_avg, alt_rssi_avg, | |
1193 | antcomb->total_pkt_count)) | |
1194 | antcomb->second_ratio = true; | |
1195 | else | |
1196 | antcomb->second_ratio = false; | |
1197 | } else { | |
1198 | if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) && | |
1199 | (alt_rssi_avg > main_rssi_avg + | |
1200 | ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) || | |
1201 | (alt_rssi_avg > main_rssi_avg)) && | |
1202 | (antcomb->total_pkt_count > 50)) | |
1203 | antcomb->second_ratio = true; | |
1204 | else | |
1205 | antcomb->second_ratio = false; | |
1206 | } | |
1207 | ||
1208 | /* set alt to the conf with maximun ratio */ | |
1209 | if (antcomb->first_ratio && antcomb->second_ratio) { | |
1210 | if (antcomb->rssi_second > antcomb->rssi_third) { | |
1211 | /* first alt*/ | |
1212 | if ((antcomb->first_quick_scan_conf == | |
1213 | ATH_ANT_DIV_COMB_LNA1) || | |
1214 | (antcomb->first_quick_scan_conf == | |
1215 | ATH_ANT_DIV_COMB_LNA2)) | |
1216 | /* Set alt LNA1 or LNA2*/ | |
1217 | if (div_ant_conf->main_lna_conf == | |
1218 | ATH_ANT_DIV_COMB_LNA2) | |
1219 | div_ant_conf->alt_lna_conf = | |
1220 | ATH_ANT_DIV_COMB_LNA1; | |
1221 | else | |
1222 | div_ant_conf->alt_lna_conf = | |
1223 | ATH_ANT_DIV_COMB_LNA2; | |
1224 | else | |
1225 | /* Set alt to A+B or A-B */ | |
1226 | div_ant_conf->alt_lna_conf = | |
1227 | antcomb->first_quick_scan_conf; | |
1228 | } else if ((antcomb->second_quick_scan_conf == | |
1229 | ATH_ANT_DIV_COMB_LNA1) || | |
1230 | (antcomb->second_quick_scan_conf == | |
1231 | ATH_ANT_DIV_COMB_LNA2)) { | |
1232 | /* Set alt LNA1 or LNA2 */ | |
1233 | if (div_ant_conf->main_lna_conf == | |
1234 | ATH_ANT_DIV_COMB_LNA2) | |
1235 | div_ant_conf->alt_lna_conf = | |
1236 | ATH_ANT_DIV_COMB_LNA1; | |
1237 | else | |
1238 | div_ant_conf->alt_lna_conf = | |
1239 | ATH_ANT_DIV_COMB_LNA2; | |
1240 | } else { | |
1241 | /* Set alt to A+B or A-B */ | |
1242 | div_ant_conf->alt_lna_conf = | |
1243 | antcomb->second_quick_scan_conf; | |
1244 | } | |
1245 | } else if (antcomb->first_ratio) { | |
1246 | /* first alt */ | |
1247 | if ((antcomb->first_quick_scan_conf == | |
1248 | ATH_ANT_DIV_COMB_LNA1) || | |
1249 | (antcomb->first_quick_scan_conf == | |
1250 | ATH_ANT_DIV_COMB_LNA2)) | |
1251 | /* Set alt LNA1 or LNA2 */ | |
1252 | if (div_ant_conf->main_lna_conf == | |
1253 | ATH_ANT_DIV_COMB_LNA2) | |
1254 | div_ant_conf->alt_lna_conf = | |
1255 | ATH_ANT_DIV_COMB_LNA1; | |
1256 | else | |
1257 | div_ant_conf->alt_lna_conf = | |
1258 | ATH_ANT_DIV_COMB_LNA2; | |
1259 | else | |
1260 | /* Set alt to A+B or A-B */ | |
1261 | div_ant_conf->alt_lna_conf = | |
1262 | antcomb->first_quick_scan_conf; | |
1263 | } else if (antcomb->second_ratio) { | |
1264 | /* second alt */ | |
1265 | if ((antcomb->second_quick_scan_conf == | |
1266 | ATH_ANT_DIV_COMB_LNA1) || | |
1267 | (antcomb->second_quick_scan_conf == | |
1268 | ATH_ANT_DIV_COMB_LNA2)) | |
1269 | /* Set alt LNA1 or LNA2 */ | |
1270 | if (div_ant_conf->main_lna_conf == | |
1271 | ATH_ANT_DIV_COMB_LNA2) | |
1272 | div_ant_conf->alt_lna_conf = | |
1273 | ATH_ANT_DIV_COMB_LNA1; | |
1274 | else | |
1275 | div_ant_conf->alt_lna_conf = | |
1276 | ATH_ANT_DIV_COMB_LNA2; | |
1277 | else | |
1278 | /* Set alt to A+B or A-B */ | |
1279 | div_ant_conf->alt_lna_conf = | |
1280 | antcomb->second_quick_scan_conf; | |
1281 | } else { | |
1282 | /* main is largest */ | |
1283 | if ((antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) || | |
1284 | (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2)) | |
1285 | /* Set alt LNA1 or LNA2 */ | |
1286 | if (div_ant_conf->main_lna_conf == | |
1287 | ATH_ANT_DIV_COMB_LNA2) | |
1288 | div_ant_conf->alt_lna_conf = | |
1289 | ATH_ANT_DIV_COMB_LNA1; | |
1290 | else | |
1291 | div_ant_conf->alt_lna_conf = | |
1292 | ATH_ANT_DIV_COMB_LNA2; | |
1293 | else | |
1294 | /* Set alt to A+B or A-B */ | |
1295 | div_ant_conf->alt_lna_conf = antcomb->main_conf; | |
1296 | } | |
1297 | break; | |
1298 | default: | |
1299 | break; | |
1300 | } | |
1301 | } | |
1302 | ||
9bad82b8 | 1303 | static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf) |
102885a5 VT |
1304 | { |
1305 | /* Adjust the fast_div_bias based on main and alt lna conf */ | |
1306 | switch ((ant_conf->main_lna_conf << 4) | ant_conf->alt_lna_conf) { | |
1307 | case (0x01): /* A-B LNA2 */ | |
1308 | ant_conf->fast_div_bias = 0x3b; | |
1309 | break; | |
1310 | case (0x02): /* A-B LNA1 */ | |
1311 | ant_conf->fast_div_bias = 0x3d; | |
1312 | break; | |
1313 | case (0x03): /* A-B A+B */ | |
1314 | ant_conf->fast_div_bias = 0x1; | |
1315 | break; | |
1316 | case (0x10): /* LNA2 A-B */ | |
1317 | ant_conf->fast_div_bias = 0x7; | |
1318 | break; | |
1319 | case (0x12): /* LNA2 LNA1 */ | |
1320 | ant_conf->fast_div_bias = 0x2; | |
1321 | break; | |
1322 | case (0x13): /* LNA2 A+B */ | |
1323 | ant_conf->fast_div_bias = 0x7; | |
1324 | break; | |
1325 | case (0x20): /* LNA1 A-B */ | |
1326 | ant_conf->fast_div_bias = 0x6; | |
1327 | break; | |
1328 | case (0x21): /* LNA1 LNA2 */ | |
1329 | ant_conf->fast_div_bias = 0x0; | |
1330 | break; | |
1331 | case (0x23): /* LNA1 A+B */ | |
1332 | ant_conf->fast_div_bias = 0x6; | |
1333 | break; | |
1334 | case (0x30): /* A+B A-B */ | |
1335 | ant_conf->fast_div_bias = 0x1; | |
1336 | break; | |
1337 | case (0x31): /* A+B LNA2 */ | |
1338 | ant_conf->fast_div_bias = 0x3b; | |
1339 | break; | |
1340 | case (0x32): /* A+B LNA1 */ | |
1341 | ant_conf->fast_div_bias = 0x3d; | |
1342 | break; | |
1343 | default: | |
1344 | break; | |
1345 | } | |
1346 | } | |
1347 | ||
1348 | /* Antenna diversity and combining */ | |
1349 | static void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs) | |
1350 | { | |
1351 | struct ath_hw_antcomb_conf div_ant_conf; | |
1352 | struct ath_ant_comb *antcomb = &sc->ant_comb; | |
1353 | int alt_ratio = 0, alt_rssi_avg = 0, main_rssi_avg = 0, curr_alt_set; | |
1354 | int curr_main_set, curr_bias; | |
1355 | int main_rssi = rs->rs_rssi_ctl0; | |
1356 | int alt_rssi = rs->rs_rssi_ctl1; | |
1357 | int rx_ant_conf, main_ant_conf; | |
1358 | bool short_scan = false; | |
1359 | ||
1360 | rx_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_CURRENT_SHIFT) & | |
1361 | ATH_ANT_RX_MASK; | |
1362 | main_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_MAIN_SHIFT) & | |
1363 | ATH_ANT_RX_MASK; | |
1364 | ||
1365 | /* Record packet only when alt_rssi is positive */ | |
1366 | if (alt_rssi > 0) { | |
1367 | antcomb->total_pkt_count++; | |
1368 | antcomb->main_total_rssi += main_rssi; | |
1369 | antcomb->alt_total_rssi += alt_rssi; | |
1370 | if (main_ant_conf == rx_ant_conf) | |
1371 | antcomb->main_recv_cnt++; | |
1372 | else | |
1373 | antcomb->alt_recv_cnt++; | |
1374 | } | |
1375 | ||
1376 | /* Short scan check */ | |
1377 | if (antcomb->scan && antcomb->alt_good) { | |
1378 | if (time_after(jiffies, antcomb->scan_start_time + | |
1379 | msecs_to_jiffies(ATH_ANT_DIV_COMB_SHORT_SCAN_INTR))) | |
1380 | short_scan = true; | |
1381 | else | |
1382 | if (antcomb->total_pkt_count == | |
1383 | ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT) { | |
1384 | alt_ratio = ((antcomb->alt_recv_cnt * 100) / | |
1385 | antcomb->total_pkt_count); | |
1386 | if (alt_ratio < ATH_ANT_DIV_COMB_ALT_ANT_RATIO) | |
1387 | short_scan = true; | |
1388 | } | |
1389 | } | |
1390 | ||
1391 | if (((antcomb->total_pkt_count < ATH_ANT_DIV_COMB_MAX_PKTCOUNT) || | |
1392 | rs->rs_moreaggr) && !short_scan) | |
1393 | return; | |
1394 | ||
1395 | if (antcomb->total_pkt_count) { | |
1396 | alt_ratio = ((antcomb->alt_recv_cnt * 100) / | |
1397 | antcomb->total_pkt_count); | |
1398 | main_rssi_avg = (antcomb->main_total_rssi / | |
1399 | antcomb->total_pkt_count); | |
1400 | alt_rssi_avg = (antcomb->alt_total_rssi / | |
1401 | antcomb->total_pkt_count); | |
1402 | } | |
1403 | ||
1404 | ||
1405 | ath9k_hw_antdiv_comb_conf_get(sc->sc_ah, &div_ant_conf); | |
1406 | curr_alt_set = div_ant_conf.alt_lna_conf; | |
1407 | curr_main_set = div_ant_conf.main_lna_conf; | |
1408 | curr_bias = div_ant_conf.fast_div_bias; | |
1409 | ||
1410 | antcomb->count++; | |
1411 | ||
1412 | if (antcomb->count == ATH_ANT_DIV_COMB_MAX_COUNT) { | |
1413 | if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) { | |
1414 | ath_lnaconf_alt_good_scan(antcomb, div_ant_conf, | |
1415 | main_rssi_avg); | |
1416 | antcomb->alt_good = true; | |
1417 | } else { | |
1418 | antcomb->alt_good = false; | |
1419 | } | |
1420 | ||
1421 | antcomb->count = 0; | |
1422 | antcomb->scan = true; | |
1423 | antcomb->scan_not_start = true; | |
1424 | } | |
1425 | ||
1426 | if (!antcomb->scan) { | |
1427 | if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) { | |
1428 | if (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) { | |
1429 | /* Switch main and alt LNA */ | |
1430 | div_ant_conf.main_lna_conf = | |
1431 | ATH_ANT_DIV_COMB_LNA2; | |
1432 | div_ant_conf.alt_lna_conf = | |
1433 | ATH_ANT_DIV_COMB_LNA1; | |
1434 | } else if (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) { | |
1435 | div_ant_conf.main_lna_conf = | |
1436 | ATH_ANT_DIV_COMB_LNA1; | |
1437 | div_ant_conf.alt_lna_conf = | |
1438 | ATH_ANT_DIV_COMB_LNA2; | |
1439 | } | |
1440 | ||
1441 | goto div_comb_done; | |
1442 | } else if ((curr_alt_set != ATH_ANT_DIV_COMB_LNA1) && | |
1443 | (curr_alt_set != ATH_ANT_DIV_COMB_LNA2)) { | |
1444 | /* Set alt to another LNA */ | |
1445 | if (curr_main_set == ATH_ANT_DIV_COMB_LNA2) | |
1446 | div_ant_conf.alt_lna_conf = | |
1447 | ATH_ANT_DIV_COMB_LNA1; | |
1448 | else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1) | |
1449 | div_ant_conf.alt_lna_conf = | |
1450 | ATH_ANT_DIV_COMB_LNA2; | |
1451 | ||
1452 | goto div_comb_done; | |
1453 | } | |
1454 | ||
1455 | if ((alt_rssi_avg < (main_rssi_avg + | |
1456 | ATH_ANT_DIV_COMB_LNA1_LNA2_DELTA))) | |
1457 | goto div_comb_done; | |
1458 | } | |
1459 | ||
1460 | if (!antcomb->scan_not_start) { | |
1461 | switch (curr_alt_set) { | |
1462 | case ATH_ANT_DIV_COMB_LNA2: | |
1463 | antcomb->rssi_lna2 = alt_rssi_avg; | |
1464 | antcomb->rssi_lna1 = main_rssi_avg; | |
1465 | antcomb->scan = true; | |
1466 | /* set to A+B */ | |
1467 | div_ant_conf.main_lna_conf = | |
1468 | ATH_ANT_DIV_COMB_LNA1; | |
1469 | div_ant_conf.alt_lna_conf = | |
1470 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; | |
1471 | break; | |
1472 | case ATH_ANT_DIV_COMB_LNA1: | |
1473 | antcomb->rssi_lna1 = alt_rssi_avg; | |
1474 | antcomb->rssi_lna2 = main_rssi_avg; | |
1475 | antcomb->scan = true; | |
1476 | /* set to A+B */ | |
1477 | div_ant_conf.main_lna_conf = ATH_ANT_DIV_COMB_LNA2; | |
1478 | div_ant_conf.alt_lna_conf = | |
1479 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; | |
1480 | break; | |
1481 | case ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2: | |
1482 | antcomb->rssi_add = alt_rssi_avg; | |
1483 | antcomb->scan = true; | |
1484 | /* set to A-B */ | |
1485 | div_ant_conf.alt_lna_conf = | |
1486 | ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; | |
1487 | break; | |
1488 | case ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2: | |
1489 | antcomb->rssi_sub = alt_rssi_avg; | |
1490 | antcomb->scan = false; | |
1491 | if (antcomb->rssi_lna2 > | |
1492 | (antcomb->rssi_lna1 + | |
1493 | ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)) { | |
1494 | /* use LNA2 as main LNA */ | |
1495 | if ((antcomb->rssi_add > antcomb->rssi_lna1) && | |
1496 | (antcomb->rssi_add > antcomb->rssi_sub)) { | |
1497 | /* set to A+B */ | |
1498 | div_ant_conf.main_lna_conf = | |
1499 | ATH_ANT_DIV_COMB_LNA2; | |
1500 | div_ant_conf.alt_lna_conf = | |
1501 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; | |
1502 | } else if (antcomb->rssi_sub > | |
1503 | antcomb->rssi_lna1) { | |
1504 | /* set to A-B */ | |
1505 | div_ant_conf.main_lna_conf = | |
1506 | ATH_ANT_DIV_COMB_LNA2; | |
1507 | div_ant_conf.alt_lna_conf = | |
1508 | ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; | |
1509 | } else { | |
1510 | /* set to LNA1 */ | |
1511 | div_ant_conf.main_lna_conf = | |
1512 | ATH_ANT_DIV_COMB_LNA2; | |
1513 | div_ant_conf.alt_lna_conf = | |
1514 | ATH_ANT_DIV_COMB_LNA1; | |
1515 | } | |
1516 | } else { | |
1517 | /* use LNA1 as main LNA */ | |
1518 | if ((antcomb->rssi_add > antcomb->rssi_lna2) && | |
1519 | (antcomb->rssi_add > antcomb->rssi_sub)) { | |
1520 | /* set to A+B */ | |
1521 | div_ant_conf.main_lna_conf = | |
1522 | ATH_ANT_DIV_COMB_LNA1; | |
1523 | div_ant_conf.alt_lna_conf = | |
1524 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; | |
1525 | } else if (antcomb->rssi_sub > | |
1526 | antcomb->rssi_lna1) { | |
1527 | /* set to A-B */ | |
1528 | div_ant_conf.main_lna_conf = | |
1529 | ATH_ANT_DIV_COMB_LNA1; | |
1530 | div_ant_conf.alt_lna_conf = | |
1531 | ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; | |
1532 | } else { | |
1533 | /* set to LNA2 */ | |
1534 | div_ant_conf.main_lna_conf = | |
1535 | ATH_ANT_DIV_COMB_LNA1; | |
1536 | div_ant_conf.alt_lna_conf = | |
1537 | ATH_ANT_DIV_COMB_LNA2; | |
1538 | } | |
1539 | } | |
1540 | break; | |
1541 | default: | |
1542 | break; | |
1543 | } | |
1544 | } else { | |
1545 | if (!antcomb->alt_good) { | |
1546 | antcomb->scan_not_start = false; | |
1547 | /* Set alt to another LNA */ | |
1548 | if (curr_main_set == ATH_ANT_DIV_COMB_LNA2) { | |
1549 | div_ant_conf.main_lna_conf = | |
1550 | ATH_ANT_DIV_COMB_LNA2; | |
1551 | div_ant_conf.alt_lna_conf = | |
1552 | ATH_ANT_DIV_COMB_LNA1; | |
1553 | } else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1) { | |
1554 | div_ant_conf.main_lna_conf = | |
1555 | ATH_ANT_DIV_COMB_LNA1; | |
1556 | div_ant_conf.alt_lna_conf = | |
1557 | ATH_ANT_DIV_COMB_LNA2; | |
1558 | } | |
1559 | goto div_comb_done; | |
1560 | } | |
1561 | } | |
1562 | ||
1563 | ath_select_ant_div_from_quick_scan(antcomb, &div_ant_conf, | |
1564 | main_rssi_avg, alt_rssi_avg, | |
1565 | alt_ratio); | |
1566 | ||
1567 | antcomb->quick_scan_cnt++; | |
1568 | ||
1569 | div_comb_done: | |
1570 | ath_ant_div_conf_fast_divbias(&div_ant_conf); | |
1571 | ||
1572 | ath9k_hw_antdiv_comb_conf_set(sc->sc_ah, &div_ant_conf); | |
1573 | ||
1574 | antcomb->scan_start_time = jiffies; | |
1575 | antcomb->total_pkt_count = 0; | |
1576 | antcomb->main_total_rssi = 0; | |
1577 | antcomb->alt_total_rssi = 0; | |
1578 | antcomb->main_recv_cnt = 0; | |
1579 | antcomb->alt_recv_cnt = 0; | |
1580 | } | |
1581 | ||
b5c80475 FF |
1582 | int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp) |
1583 | { | |
1584 | struct ath_buf *bf; | |
cb71d9ba | 1585 | struct sk_buff *skb = NULL, *requeue_skb; |
5ca42627 | 1586 | struct ieee80211_rx_status *rxs; |
cbe61d8a | 1587 | struct ath_hw *ah = sc->sc_ah; |
27c51f1a | 1588 | struct ath_common *common = ath9k_hw_common(ah); |
b4afffc0 | 1589 | /* |
cae6b74d | 1590 | * The hw can technically differ from common->hw when using ath9k |
b4afffc0 LR |
1591 | * virtual wiphy so to account for that we iterate over the active |
1592 | * wiphys and find the appropriate wiphy and therefore hw. | |
1593 | */ | |
7545daf4 | 1594 | struct ieee80211_hw *hw = sc->hw; |
be0418ad | 1595 | struct ieee80211_hdr *hdr; |
c9b14170 | 1596 | int retval; |
be0418ad | 1597 | bool decrypt_error = false; |
29bffa96 | 1598 | struct ath_rx_status rs; |
b5c80475 FF |
1599 | enum ath9k_rx_qtype qtype; |
1600 | bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); | |
1601 | int dma_type; | |
5c6dd921 | 1602 | u8 rx_status_len = ah->caps.rx_status_len; |
a6d2055b FF |
1603 | u64 tsf = 0; |
1604 | u32 tsf_lower = 0; | |
8ab2cd09 | 1605 | unsigned long flags; |
be0418ad | 1606 | |
b5c80475 | 1607 | if (edma) |
b5c80475 | 1608 | dma_type = DMA_BIDIRECTIONAL; |
56824223 ML |
1609 | else |
1610 | dma_type = DMA_FROM_DEVICE; | |
b5c80475 FF |
1611 | |
1612 | qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP; | |
b77f483f | 1613 | spin_lock_bh(&sc->rx.rxbuflock); |
f078f209 | 1614 | |
a6d2055b FF |
1615 | tsf = ath9k_hw_gettsf64(ah); |
1616 | tsf_lower = tsf & 0xffffffff; | |
1617 | ||
f078f209 LR |
1618 | do { |
1619 | /* If handling rx interrupt and flush is in progress => exit */ | |
98deeea0 | 1620 | if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0)) |
f078f209 LR |
1621 | break; |
1622 | ||
29bffa96 | 1623 | memset(&rs, 0, sizeof(rs)); |
b5c80475 FF |
1624 | if (edma) |
1625 | bf = ath_edma_get_next_rx_buf(sc, &rs, qtype); | |
1626 | else | |
1627 | bf = ath_get_next_rx_buf(sc, &rs); | |
f078f209 | 1628 | |
b5c80475 FF |
1629 | if (!bf) |
1630 | break; | |
f078f209 | 1631 | |
f078f209 | 1632 | skb = bf->bf_mpdu; |
be0418ad | 1633 | if (!skb) |
f078f209 | 1634 | continue; |
f078f209 | 1635 | |
5c6dd921 | 1636 | hdr = (struct ieee80211_hdr *) (skb->data + rx_status_len); |
5ca42627 LR |
1637 | rxs = IEEE80211_SKB_RXCB(skb); |
1638 | ||
29bffa96 | 1639 | ath_debug_stat_rx(sc, &rs); |
1395d3f0 | 1640 | |
f078f209 | 1641 | /* |
be0418ad S |
1642 | * If we're asked to flush receive queue, directly |
1643 | * chain it back at the queue without processing it. | |
f078f209 | 1644 | */ |
be0418ad | 1645 | if (flush) |
cb71d9ba | 1646 | goto requeue; |
f078f209 | 1647 | |
c8f3b721 JF |
1648 | retval = ath9k_rx_skb_preprocess(common, hw, hdr, &rs, |
1649 | rxs, &decrypt_error); | |
1650 | if (retval) | |
1651 | goto requeue; | |
1652 | ||
a6d2055b FF |
1653 | rxs->mactime = (tsf & ~0xffffffffULL) | rs.rs_tstamp; |
1654 | if (rs.rs_tstamp > tsf_lower && | |
1655 | unlikely(rs.rs_tstamp - tsf_lower > 0x10000000)) | |
1656 | rxs->mactime -= 0x100000000ULL; | |
1657 | ||
1658 | if (rs.rs_tstamp < tsf_lower && | |
1659 | unlikely(tsf_lower - rs.rs_tstamp > 0x10000000)) | |
1660 | rxs->mactime += 0x100000000ULL; | |
1661 | ||
cb71d9ba LR |
1662 | /* Ensure we always have an skb to requeue once we are done |
1663 | * processing the current buffer's skb */ | |
cc861f74 | 1664 | requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC); |
cb71d9ba LR |
1665 | |
1666 | /* If there is no memory we ignore the current RX'd frame, | |
1667 | * tell hardware it can give us a new frame using the old | |
b77f483f | 1668 | * skb and put it at the tail of the sc->rx.rxbuf list for |
cb71d9ba LR |
1669 | * processing. */ |
1670 | if (!requeue_skb) | |
1671 | goto requeue; | |
f078f209 | 1672 | |
9bf9fca8 | 1673 | /* Unmap the frame */ |
7da3c55c | 1674 | dma_unmap_single(sc->dev, bf->bf_buf_addr, |
cc861f74 | 1675 | common->rx_bufsize, |
b5c80475 | 1676 | dma_type); |
f078f209 | 1677 | |
b5c80475 FF |
1678 | skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len); |
1679 | if (ah->caps.rx_status_len) | |
1680 | skb_pull(skb, ah->caps.rx_status_len); | |
be0418ad | 1681 | |
d435700f S |
1682 | ath9k_rx_skb_postprocess(common, skb, &rs, |
1683 | rxs, decrypt_error); | |
be0418ad | 1684 | |
cb71d9ba LR |
1685 | /* We will now give hardware our shiny new allocated skb */ |
1686 | bf->bf_mpdu = requeue_skb; | |
7da3c55c | 1687 | bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data, |
cc861f74 | 1688 | common->rx_bufsize, |
b5c80475 | 1689 | dma_type); |
7da3c55c | 1690 | if (unlikely(dma_mapping_error(sc->dev, |
f8316df1 LR |
1691 | bf->bf_buf_addr))) { |
1692 | dev_kfree_skb_any(requeue_skb); | |
1693 | bf->bf_mpdu = NULL; | |
6cf9e995 | 1694 | bf->bf_buf_addr = 0; |
3800276a | 1695 | ath_err(common, "dma_mapping_error() on RX\n"); |
7545daf4 | 1696 | ieee80211_rx(hw, skb); |
f8316df1 LR |
1697 | break; |
1698 | } | |
f078f209 LR |
1699 | |
1700 | /* | |
1701 | * change the default rx antenna if rx diversity chooses the | |
1702 | * other antenna 3 times in a row. | |
1703 | */ | |
29bffa96 | 1704 | if (sc->rx.defant != rs.rs_antenna) { |
b77f483f | 1705 | if (++sc->rx.rxotherant >= 3) |
29bffa96 | 1706 | ath_setdefantenna(sc, rs.rs_antenna); |
f078f209 | 1707 | } else { |
b77f483f | 1708 | sc->rx.rxotherant = 0; |
f078f209 | 1709 | } |
3cbb5dd7 | 1710 | |
8ab2cd09 | 1711 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
aaef24b4 MSS |
1712 | |
1713 | if ((sc->ps_flags & (PS_WAIT_FOR_BEACON | | |
ededf1f8 | 1714 | PS_WAIT_FOR_CAB | |
aaef24b4 MSS |
1715 | PS_WAIT_FOR_PSPOLL_DATA)) || |
1716 | unlikely(ath9k_check_auto_sleep(sc))) | |
cc65965c | 1717 | ath_rx_ps(sc, skb); |
8ab2cd09 | 1718 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
cc65965c | 1719 | |
102885a5 VT |
1720 | if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) |
1721 | ath_ant_comb_scan(sc, &rs); | |
1722 | ||
7545daf4 | 1723 | ieee80211_rx(hw, skb); |
cc65965c | 1724 | |
cb71d9ba | 1725 | requeue: |
b5c80475 FF |
1726 | if (edma) { |
1727 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
1728 | ath_rx_edma_buf_link(sc, qtype); | |
1729 | } else { | |
1730 | list_move_tail(&bf->list, &sc->rx.rxbuf); | |
1731 | ath_rx_buf_link(sc, bf); | |
1732 | } | |
be0418ad S |
1733 | } while (1); |
1734 | ||
b77f483f | 1735 | spin_unlock_bh(&sc->rx.rxbuflock); |
f078f209 LR |
1736 | |
1737 | return 0; | |
f078f209 | 1738 | } |