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Merge tag 'v3.5-rc6' into irqdomain/next
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / recv.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
b7f080cf 17#include <linux/dma-mapping.h>
394cf0a1 18#include "ath9k.h"
b622a720 19#include "ar9003_mac.h"
f078f209 20
b5c80475
FF		 21#define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb))
22
102885a5
VT		 23static inline bool ath_is_alt_ant_ratio_better(int alt_ratio, int maxdelta,
24 int mindelta, int main_rssi_avg,
25 int alt_rssi_avg, int pkt_count)
26{
27 return (((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
28 (alt_rssi_avg > main_rssi_avg + maxdelta)) ||
29 (alt_rssi_avg > main_rssi_avg + mindelta)) && (pkt_count > 50);
30}
31
b85c5734
MSS		 32static inline bool ath_ant_div_comb_alt_check(u8 div_group, int alt_ratio,
33 int curr_main_set, int curr_alt_set,
34 int alt_rssi_avg, int main_rssi_avg)
35{
36 bool result = false;
37 switch (div_group) {
38 case 0:
39 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
40 result = true;
41 break;
42 case 1:
66ce235a 43 case 2:
b85c5734
MSS		 44 if ((((curr_main_set == ATH_ANT_DIV_COMB_LNA2) &&
45 (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) &&
46 (alt_rssi_avg >= (main_rssi_avg - 5))) ||
47 ((curr_main_set == ATH_ANT_DIV_COMB_LNA1) &&
48 (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) &&
49 (alt_rssi_avg >= (main_rssi_avg - 2)))) &&
50 (alt_rssi_avg >= 4))
51 result = true;
52 else
53 result = false;
54 break;
55 }
56
57 return result;
58}
59
ededf1f8
VT		 60static inline bool ath9k_check_auto_sleep(struct ath_softc *sc)
61{
62 return sc->ps_enabled &&
63 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP);
64}
65
f078f209
LR		 66/*
67 * Setup and link descriptors.
68 *
69 * 11N: we can no longer afford to self link the last descriptor.
70 * MAC acknowledges BA status as long as it copies frames to host
71 * buffer (or rx fifo). This can incorrectly acknowledge packets
72 * to a sender if last desc is self-linked.
f078f209 73 */
f078f209
LR		 74static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
75{
cbe61d8a 76 struct ath_hw *ah = sc->sc_ah;
cc861f74 77 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 78 struct ath_desc *ds;
79 struct sk_buff *skb;
80
81 ATH_RXBUF_RESET(bf);
82
83 ds = bf->bf_desc;
be0418ad 84 ds->ds_link = 0; /* link to null */
f078f209
LR		 85 ds->ds_data = bf->bf_buf_addr;
86
be0418ad 87 /* virtual addr of the beginning of the buffer. */
f078f209 88 skb = bf->bf_mpdu;
9680e8a3 89 BUG_ON(skb == NULL);
f078f209
LR		 90 ds->ds_vdata = skb->data;
91
cc861f74
LR		 92 /*
93 * setup rx descriptors. The rx_bufsize here tells the hardware
b4b6cda2 94 * how much data it can DMA to us and that we are prepared
cc861f74
LR		 95 * to process
96 */
b77f483f 97 ath9k_hw_setuprxdesc(ah, ds,
cc861f74 98 common->rx_bufsize,
f078f209
LR		 99 0);
100
b77f483f 101 if (sc->rx.rxlink == NULL)
f078f209
LR		 102 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
103 else
b77f483f 104 *sc->rx.rxlink = bf->bf_daddr;
f078f209 105
b77f483f 106 sc->rx.rxlink = &ds->ds_link;
f078f209
LR		 107}
108
ff37e337
S		 109static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
110{
111 /* XXX block beacon interrupts */
112 ath9k_hw_setantenna(sc->sc_ah, antenna);
b77f483f
S		 113 sc->rx.defant = antenna;
114 sc->rx.rxotherant = 0;
ff37e337
S		 115}
116
f078f209
LR		 117static void ath_opmode_init(struct ath_softc *sc)
118{
cbe61d8a 119 struct ath_hw *ah = sc->sc_ah;
1510718d
LR		 120 struct ath_common *common = ath9k_hw_common(ah);
121
f078f209
LR		 122 u32 rfilt, mfilt[2];
123
124 /* configure rx filter */
125 rfilt = ath_calcrxfilter(sc);
126 ath9k_hw_setrxfilter(ah, rfilt);
127
128 /* configure bssid mask */
364734fa 129 ath_hw_setbssidmask(common);
f078f209
LR		 130
131 /* configure operational mode */
132 ath9k_hw_setopmode(ah);
133
f078f209
LR		 134 /* calculate and install multicast filter */
135 mfilt[0] = mfilt[1] = ~0;
f078f209 136 ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
f078f209
LR		 137}
138
b5c80475
FF		 139static bool ath_rx_edma_buf_link(struct ath_softc *sc,
140 enum ath9k_rx_qtype qtype)
f078f209 141{
b5c80475
FF		 142 struct ath_hw *ah = sc->sc_ah;
143 struct ath_rx_edma *rx_edma;
f078f209
LR		 144 struct sk_buff *skb;
145 struct ath_buf *bf;
f078f209 146
b5c80475
FF		 147 rx_edma = &sc->rx.rx_edma[qtype];
148 if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize)
149 return false;
f078f209 150
b5c80475
FF		 151 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
152 list_del_init(&bf->list);
f078f209 153
b5c80475
FF		 154 skb = bf->bf_mpdu;
155
156 ATH_RXBUF_RESET(bf);
157 memset(skb->data, 0, ah->caps.rx_status_len);
158 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
159 ah->caps.rx_status_len, DMA_TO_DEVICE);
f078f209 160
b5c80475
FF		 161 SKB_CB_ATHBUF(skb) = bf;
162 ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype);
163 skb_queue_tail(&rx_edma->rx_fifo, skb);
f078f209 164
b5c80475
FF		 165 return true;
166}
167
168static void ath_rx_addbuffer_edma(struct ath_softc *sc,
169 enum ath9k_rx_qtype qtype, int size)
170{
b5c80475 171 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
6a01f0c0 172 struct ath_buf *bf, *tbf;
b5c80475 173
b5c80475 174 if (list_empty(&sc->rx.rxbuf)) {
d2182b69 175 ath_dbg(common, QUEUE, "No free rx buf available\n");
b5c80475 176 return;
797fe5cb 177 }
f078f209 178
6a01f0c0 179 list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list)
b5c80475
FF		 180 if (!ath_rx_edma_buf_link(sc, qtype))
181 break;
182
b5c80475
FF		 183}
184
185static void ath_rx_remove_buffer(struct ath_softc *sc,
186 enum ath9k_rx_qtype qtype)
187{
188 struct ath_buf *bf;
189 struct ath_rx_edma *rx_edma;
190 struct sk_buff *skb;
191
192 rx_edma = &sc->rx.rx_edma[qtype];
193
194 while ((skb = skb_dequeue(&rx_edma->rx_fifo)) != NULL) {
195 bf = SKB_CB_ATHBUF(skb);
196 BUG_ON(!bf);
197 list_add_tail(&bf->list, &sc->rx.rxbuf);
198 }
199}
200
201static void ath_rx_edma_cleanup(struct ath_softc *sc)
202{
ba542385
MSS		 203 struct ath_hw *ah = sc->sc_ah;
204 struct ath_common *common = ath9k_hw_common(ah);
b5c80475
FF		 205 struct ath_buf *bf;
206
207 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
208 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
209
797fe5cb 210 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
ba542385
MSS		 211 if (bf->bf_mpdu) {
212 dma_unmap_single(sc->dev, bf->bf_buf_addr,
213 common->rx_bufsize,
214 DMA_BIDIRECTIONAL);
b5c80475 215 dev_kfree_skb_any(bf->bf_mpdu);
ba542385
MSS		 216 bf->bf_buf_addr = 0;
217 bf->bf_mpdu = NULL;
218 }
b5c80475
FF		 219 }
220
221 INIT_LIST_HEAD(&sc->rx.rxbuf);
222
223 kfree(sc->rx.rx_bufptr);
224 sc->rx.rx_bufptr = NULL;
225}
226
227static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size)
228{
229 skb_queue_head_init(&rx_edma->rx_fifo);
b5c80475
FF		 230 rx_edma->rx_fifo_hwsize = size;
231}
232
233static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
234{
235 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
236 struct ath_hw *ah = sc->sc_ah;
237 struct sk_buff *skb;
238 struct ath_buf *bf;
239 int error = 0, i;
240 u32 size;
241
b5c80475
FF		 242 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
243 ah->caps.rx_status_len);
244
245 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP],
246 ah->caps.rx_lp_qdepth);
247 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP],
248 ah->caps.rx_hp_qdepth);
249
250 size = sizeof(struct ath_buf) * nbufs;
251 bf = kzalloc(size, GFP_KERNEL);
252 if (!bf)
253 return -ENOMEM;
254
255 INIT_LIST_HEAD(&sc->rx.rxbuf);
256 sc->rx.rx_bufptr = bf;
257
258 for (i = 0; i < nbufs; i++, bf++) {
cc861f74 259 skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
b5c80475 260 if (!skb) {
797fe5cb 261 error = -ENOMEM;
b5c80475 262 goto rx_init_fail;
f078f209 263 }
f078f209 264
b5c80475 265 memset(skb->data, 0, common->rx_bufsize);
797fe5cb 266 bf->bf_mpdu = skb;
b5c80475 267
797fe5cb 268 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
cc861f74 269 common->rx_bufsize,
b5c80475 270 DMA_BIDIRECTIONAL);
797fe5cb 271 if (unlikely(dma_mapping_error(sc->dev,
b5c80475
FF		 272 bf->bf_buf_addr))) {
273 dev_kfree_skb_any(skb);
274 bf->bf_mpdu = NULL;
6cf9e995 275 bf->bf_buf_addr = 0;
3800276a 276 ath_err(common,
b5c80475
FF		 277 "dma_mapping_error() on RX init\n");
278 error = -ENOMEM;
279 goto rx_init_fail;
280 }
281
282 list_add_tail(&bf->list, &sc->rx.rxbuf);
283 }
284
285 return 0;
286
287rx_init_fail:
288 ath_rx_edma_cleanup(sc);
289 return error;
290}
291
292static void ath_edma_start_recv(struct ath_softc *sc)
293{
294 spin_lock_bh(&sc->rx.rxbuflock);
295
296 ath9k_hw_rxena(sc->sc_ah);
297
298 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP,
299 sc->rx.rx_edma[ATH9K_RX_QUEUE_HP].rx_fifo_hwsize);
300
301 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP,
302 sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize);
303
b5c80475
FF		 304 ath_opmode_init(sc);
305
48a6a468 306 ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
7583c550
LR		 307
308 spin_unlock_bh(&sc->rx.rxbuflock);
b5c80475
FF		 309}
310
311static void ath_edma_stop_recv(struct ath_softc *sc)
312{
b5c80475
FF		 313 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
314 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
b5c80475
FF		 315}
316
317int ath_rx_init(struct ath_softc *sc, int nbufs)
318{
319 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
320 struct sk_buff *skb;
321 struct ath_buf *bf;
322 int error = 0;
323
4bdd1e97 324 spin_lock_init(&sc->sc_pcu_lock);
b5c80475
FF		 325 sc->sc_flags &= ~SC_OP_RXFLUSH;
326 spin_lock_init(&sc->rx.rxbuflock);
327
0d95521e
FF		 328 common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 +
329 sc->sc_ah->caps.rx_status_len;
330
b5c80475
FF		 331 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
332 return ath_rx_edma_init(sc, nbufs);
333 } else {
d2182b69 334 ath_dbg(common, CONFIG, "cachelsz %u rxbufsize %u\n",
226afe68 335 common->cachelsz, common->rx_bufsize);
b5c80475
FF		 336
337 /* Initialize rx descriptors */
338
339 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
4adfcded 340 "rx", nbufs, 1, 0);
b5c80475 341 if (error != 0) {
3800276a
JP		 342 ath_err(common,
343 "failed to allocate rx descriptors: %d\n",
344 error);
797fe5cb
S		 345 goto err;
346 }
b5c80475
FF		 347
348 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
349 skb = ath_rxbuf_alloc(common, common->rx_bufsize,
350 GFP_KERNEL);
351 if (skb == NULL) {
352 error = -ENOMEM;
353 goto err;
354 }
355
356 bf->bf_mpdu = skb;
357 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
358 common->rx_bufsize,
359 DMA_FROM_DEVICE);
360 if (unlikely(dma_mapping_error(sc->dev,
361 bf->bf_buf_addr))) {
362 dev_kfree_skb_any(skb);
363 bf->bf_mpdu = NULL;
6cf9e995 364 bf->bf_buf_addr = 0;
3800276a
JP		 365 ath_err(common,
366 "dma_mapping_error() on RX init\n");
b5c80475
FF		 367 error = -ENOMEM;
368 goto err;
369 }
b5c80475
FF		 370 }
371 sc->rx.rxlink = NULL;
797fe5cb 372 }
f078f209 373
797fe5cb 374err:
f078f209
LR		 375 if (error)
376 ath_rx_cleanup(sc);
377
378 return error;
379}
380
f078f209
LR		 381void ath_rx_cleanup(struct ath_softc *sc)
382{
cc861f74
LR		 383 struct ath_hw *ah = sc->sc_ah;
384 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 385 struct sk_buff *skb;
386 struct ath_buf *bf;
387
b5c80475
FF		 388 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
389 ath_rx_edma_cleanup(sc);
390 return;
391 } else {
392 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
393 skb = bf->bf_mpdu;
394 if (skb) {
395 dma_unmap_single(sc->dev, bf->bf_buf_addr,
396 common->rx_bufsize,
397 DMA_FROM_DEVICE);
398 dev_kfree_skb(skb);
6cf9e995
BG		 399 bf->bf_buf_addr = 0;
400 bf->bf_mpdu = NULL;
b5c80475 401 }
051b9191 402 }
f078f209 403
b5c80475
FF		 404 if (sc->rx.rxdma.dd_desc_len != 0)
405 ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
406 }
f078f209
LR		 407}
408
409/*
410 * Calculate the receive filter according to the
411 * operating mode and state:
412 *
413 * o always accept unicast, broadcast, and multicast traffic
414 * o maintain current state of phy error reception (the hal
415 * may enable phy error frames for noise immunity work)
416 * o probe request frames are accepted only when operating in
417 * hostap, adhoc, or monitor modes
418 * o enable promiscuous mode according to the interface state
419 * o accept beacons:
420 * - when operating in adhoc mode so the 802.11 layer creates
421 * node table entries for peers,
422 * - when operating in station mode for collecting rssi data when
423 * the station is otherwise quiet, or
424 * - when operating as a repeater so we see repeater-sta beacons
425 * - when scanning
426 */
427
428u32 ath_calcrxfilter(struct ath_softc *sc)
429{
f078f209
LR		 430 u32 rfilt;
431
ac06697c 432 rfilt = ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
f078f209
LR		 433 | ATH9K_RX_FILTER_MCAST;
434
9c1d8e4a 435 if (sc->rx.rxfilter & FIF_PROBE_REQ)
f078f209
LR		 436 rfilt |= ATH9K_RX_FILTER_PROBEREQ;
437
217ba9da
JM		 438 /*
439 * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station
440 * mode interface or when in monitor mode. AP mode does not need this
441 * since it receives all in-BSS frames anyway.
442 */
2e286947 443 if (sc->sc_ah->is_monitoring)
f078f209 444 rfilt |= ATH9K_RX_FILTER_PROM;
f078f209 445
d42c6b71
S		 446 if (sc->rx.rxfilter & FIF_CONTROL)
447 rfilt |= ATH9K_RX_FILTER_CONTROL;
448
dbaaa147 449 if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
cfda6695 450 (sc->nvifs <= 1) &&
dbaaa147
VT		 451 !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC))
452 rfilt |= ATH9K_RX_FILTER_MYBEACON;
453 else
f078f209
LR		 454 rfilt |= ATH9K_RX_FILTER_BEACON;
455
264bbec8 456 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
66afad01 457 (sc->rx.rxfilter & FIF_PSPOLL))
dbaaa147 458 rfilt |= ATH9K_RX_FILTER_PSPOLL;
be0418ad 459
7ea310be
S		 460 if (conf_is_ht(&sc->hw->conf))
461 rfilt |= ATH9K_RX_FILTER_COMP_BAR;
462
7545daf4 463 if (sc->nvifs > 1 || (sc->rx.rxfilter & FIF_OTHER_BSS)) {
5eb6ba83
JC		 464 /* The following may also be needed for other older chips */
465 if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160)
466 rfilt |= ATH9K_RX_FILTER_PROM;
b93bce2a
JM		 467 rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
468 }
469
f078f209 470 return rfilt;
7dcfdcd9 471
f078f209
LR		 472}
473
f078f209
LR		 474int ath_startrecv(struct ath_softc *sc)
475{
cbe61d8a 476 struct ath_hw *ah = sc->sc_ah;
f078f209
LR		 477 struct ath_buf *bf, *tbf;
478
b5c80475
FF		 479 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
480 ath_edma_start_recv(sc);
481 return 0;
482 }
483
b77f483f
S		 484 spin_lock_bh(&sc->rx.rxbuflock);
485 if (list_empty(&sc->rx.rxbuf))
f078f209
LR		 486 goto start_recv;
487
b77f483f
S		 488 sc->rx.rxlink = NULL;
489 list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
f078f209
LR		 490 ath_rx_buf_link(sc, bf);
491 }
492
493 /* We could have deleted elements so the list may be empty now */
b77f483f 494 if (list_empty(&sc->rx.rxbuf))
f078f209
LR		 495 goto start_recv;
496
b77f483f 497 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
f078f209 498 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
be0418ad 499 ath9k_hw_rxena(ah);
f078f209
LR		 500
501start_recv:
be0418ad 502 ath_opmode_init(sc);
48a6a468 503 ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
be0418ad 504
7583c550
LR		 505 spin_unlock_bh(&sc->rx.rxbuflock);
506
f078f209
LR		 507 return 0;
508}
509
f078f209
LR		 510bool ath_stoprecv(struct ath_softc *sc)
511{
cbe61d8a 512 struct ath_hw *ah = sc->sc_ah;
5882da02 513 bool stopped, reset = false;
f078f209 514
1e450285 515 spin_lock_bh(&sc->rx.rxbuflock);
d47844a0 516 ath9k_hw_abortpcurecv(ah);
be0418ad 517 ath9k_hw_setrxfilter(ah, 0);
5882da02 518 stopped = ath9k_hw_stopdmarecv(ah, &reset);
b5c80475
FF		 519
520 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
521 ath_edma_stop_recv(sc);
522 else
523 sc->rx.rxlink = NULL;
1e450285 524 spin_unlock_bh(&sc->rx.rxbuflock);
be0418ad 525
d584747b
RM		 526 if (!(ah->ah_flags & AH_UNPLUGGED) &&
527 unlikely(!stopped)) {
d7fd1b50
BG		 528 ath_err(ath9k_hw_common(sc->sc_ah),
529 "Could not stop RX, we could be "
530 "confusing the DMA engine when we start RX up\n");
531 ATH_DBG_WARN_ON_ONCE(!stopped);
532 }
2232d31b 533 return stopped && !reset;
f078f209
LR		 534}
535
f078f209
LR		 536void ath_flushrecv(struct ath_softc *sc)
537{
98deeea0 538 sc->sc_flags |= SC_OP_RXFLUSH;
b5c80475
FF		 539 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
540 ath_rx_tasklet(sc, 1, true);
541 ath_rx_tasklet(sc, 1, false);
98deeea0 542 sc->sc_flags &= ~SC_OP_RXFLUSH;
f078f209
LR		 543}
544
cc65965c
JM		 545static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
546{
547 /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
548 struct ieee80211_mgmt *mgmt;
549 u8 *pos, *end, id, elen;
550 struct ieee80211_tim_ie *tim;
551
552 mgmt = (struct ieee80211_mgmt *)skb->data;
553 pos = mgmt->u.beacon.variable;
554 end = skb->data + skb->len;
555
556 while (pos + 2 < end) {
557 id = *pos++;
558 elen = *pos++;
559 if (pos + elen > end)
560 break;
561
562 if (id == WLAN_EID_TIM) {
563 if (elen < sizeof(*tim))
564 break;
565 tim = (struct ieee80211_tim_ie *) pos;
566 if (tim->dtim_count != 0)
567 break;
568 return tim->bitmap_ctrl & 0x01;
569 }
570
571 pos += elen;
572 }
573
574 return false;
575}
576
cc65965c
JM		 577static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
578{
1510718d 579 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
cc65965c
JM		 580
581 if (skb->len < 24 + 8 + 2 + 2)
582 return;
583
1b04b930 584 sc->ps_flags &= ~PS_WAIT_FOR_BEACON;
293dc5df 585
1b04b930
S		 586 if (sc->ps_flags & PS_BEACON_SYNC) {
587 sc->ps_flags &= ~PS_BEACON_SYNC;
d2182b69 588 ath_dbg(common, PS,
226afe68 589 "Reconfigure Beacon timers based on timestamp from the AP\n");
99e4d43a 590 ath_set_beacon(sc);
ccdfeab6
JM		 591 }
592
cc65965c
JM		 593 if (ath_beacon_dtim_pending_cab(skb)) {
594 /*
595 * Remain awake waiting for buffered broadcast/multicast
58f5fffd
GJ		 596 * frames. If the last broadcast/multicast frame is not
597 * received properly, the next beacon frame will work as
598 * a backup trigger for returning into NETWORK SLEEP state,
599 * so we are waiting for it as well.
cc65965c 600 */
d2182b69 601 ath_dbg(common, PS,
226afe68 602 "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n");
1b04b930 603 sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
cc65965c
JM		 604 return;
605 }
606
1b04b930 607 if (sc->ps_flags & PS_WAIT_FOR_CAB) {
cc65965c
JM		 608 /*
609 * This can happen if a broadcast frame is dropped or the AP
610 * fails to send a frame indicating that all CAB frames have
611 * been delivered.
612 */
1b04b930 613 sc->ps_flags &= ~PS_WAIT_FOR_CAB;
d2182b69 614 ath_dbg(common, PS, "PS wait for CAB frames timed out\n");
cc65965c 615 }
cc65965c
JM		 616}
617
f73c604c 618static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb, bool mybeacon)
cc65965c
JM		 619{
620 struct ieee80211_hdr *hdr;
c46917bb 621 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
cc65965c
JM		 622
623 hdr = (struct ieee80211_hdr *)skb->data;
624
625 /* Process Beacon and CAB receive in PS state */
ededf1f8 626 if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc))
f73c604c 627 && mybeacon)
cc65965c 628 ath_rx_ps_beacon(sc, skb);
1b04b930 629 else if ((sc->ps_flags & PS_WAIT_FOR_CAB) &&
cc65965c
JM		 630 (ieee80211_is_data(hdr->frame_control) ||
631 ieee80211_is_action(hdr->frame_control)) &&
632 is_multicast_ether_addr(hdr->addr1) &&
633 !ieee80211_has_moredata(hdr->frame_control)) {
cc65965c
JM		 634 /*
635 * No more broadcast/multicast frames to be received at this
636 * point.
637 */
3fac6dfd 638 sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON);
d2182b69 639 ath_dbg(common, PS,
226afe68 640 "All PS CAB frames received, back to sleep\n");
1b04b930 641 } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
9a23f9ca
JM		 642 !is_multicast_ether_addr(hdr->addr1) &&
643 !ieee80211_has_morefrags(hdr->frame_control)) {
1b04b930 644 sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
d2182b69 645 ath_dbg(common, PS,
226afe68 646 "Going back to sleep after having received PS-Poll data (0x%lx)\n",
1b04b930
S		 647 sc->ps_flags & (PS_WAIT_FOR_BEACON |
648 PS_WAIT_FOR_CAB |
649 PS_WAIT_FOR_PSPOLL_DATA |
650 PS_WAIT_FOR_TX_ACK));
cc65965c
JM		 651 }
652}
653
b5c80475 654static bool ath_edma_get_buffers(struct ath_softc *sc,
3a2923e8
FF		 655 enum ath9k_rx_qtype qtype,
656 struct ath_rx_status *rs,
657 struct ath_buf **dest)
f078f209 658{
b5c80475
FF		 659 struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
660 struct ath_hw *ah = sc->sc_ah;
661 struct ath_common *common = ath9k_hw_common(ah);
662 struct sk_buff *skb;
663 struct ath_buf *bf;
664 int ret;
665
666 skb = skb_peek(&rx_edma->rx_fifo);
667 if (!skb)
668 return false;
669
670 bf = SKB_CB_ATHBUF(skb);
671 BUG_ON(!bf);
672
ce9426d1 673 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
b5c80475
FF		 674 common->rx_bufsize, DMA_FROM_DEVICE);
675
3a2923e8 676 ret = ath9k_hw_process_rxdesc_edma(ah, rs, skb->data);
ce9426d1
ML		 677 if (ret == -EINPROGRESS) {
678 /*let device gain the buffer again*/
679 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
680 common->rx_bufsize, DMA_FROM_DEVICE);
b5c80475 681 return false;
ce9426d1 682 }
b5c80475
FF		 683
684 __skb_unlink(skb, &rx_edma->rx_fifo);
685 if (ret == -EINVAL) {
686 /* corrupt descriptor, skip this one and the following one */
687 list_add_tail(&bf->list, &sc->rx.rxbuf);
688 ath_rx_edma_buf_link(sc, qtype);
b5c80475 689
3a2923e8
FF		 690 skb = skb_peek(&rx_edma->rx_fifo);
691 if (skb) {
692 bf = SKB_CB_ATHBUF(skb);
693 BUG_ON(!bf);
694
695 __skb_unlink(skb, &rx_edma->rx_fifo);
696 list_add_tail(&bf->list, &sc->rx.rxbuf);
697 ath_rx_edma_buf_link(sc, qtype);
3a2923e8 698 }
6bb51c70
TH		 699
700 bf = NULL;
b5c80475 701 }
b5c80475 702
3a2923e8 703 *dest = bf;
b5c80475
FF		 704 return true;
705}
f078f209 706
b5c80475
FF		 707static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc,
708 struct ath_rx_status *rs,
709 enum ath9k_rx_qtype qtype)
710{
3a2923e8 711 struct ath_buf *bf = NULL;
b5c80475 712
3a2923e8
FF		 713 while (ath_edma_get_buffers(sc, qtype, rs, &bf)) {
714 if (!bf)
715 continue;
b5c80475 716
3a2923e8
FF		 717 return bf;
718 }
719 return NULL;
b5c80475
FF		 720}
721
722static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc,
723 struct ath_rx_status *rs)
724{
725 struct ath_hw *ah = sc->sc_ah;
726 struct ath_common *common = ath9k_hw_common(ah);
f078f209 727 struct ath_desc *ds;
b5c80475
FF		 728 struct ath_buf *bf;
729 int ret;
730
731 if (list_empty(&sc->rx.rxbuf)) {
732 sc->rx.rxlink = NULL;
733 return NULL;
734 }
735
736 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
737 ds = bf->bf_desc;
738
739 /*
740 * Must provide the virtual address of the current
741 * descriptor, the physical address, and the virtual
742 * address of the next descriptor in the h/w chain.
743 * This allows the HAL to look ahead to see if the
744 * hardware is done with a descriptor by checking the
745 * done bit in the following descriptor and the address
746 * of the current descriptor the DMA engine is working
747 * on. All this is necessary because of our use of
748 * a self-linked list to avoid rx overruns.
749 */
3de21116 750 ret = ath9k_hw_rxprocdesc(ah, ds, rs);
b5c80475
FF		 751 if (ret == -EINPROGRESS) {
752 struct ath_rx_status trs;
753 struct ath_buf *tbf;
754 struct ath_desc *tds;
755
756 memset(&trs, 0, sizeof(trs));
757 if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
758 sc->rx.rxlink = NULL;
759 return NULL;
760 }
761
762 tbf = list_entry(bf->list.next, struct ath_buf, list);
763
764 /*
765 * On some hardware the descriptor status words could
766 * get corrupted, including the done bit. Because of
767 * this, check if the next descriptor's done bit is
768 * set or not.
769 *
770 * If the next descriptor's done bit is set, the current
771 * descriptor has been corrupted. Force s/w to discard
772 * this descriptor and continue...
773 */
774
775 tds = tbf->bf_desc;
3de21116 776 ret = ath9k_hw_rxprocdesc(ah, tds, &trs);
b5c80475
FF		 777 if (ret == -EINPROGRESS)
778 return NULL;
779 }
780
781 if (!bf->bf_mpdu)
782 return bf;
783
784 /*
785 * Synchronize the DMA transfer with CPU before
786 * 1. accessing the frame
787 * 2. requeueing the same buffer to h/w
788 */
ce9426d1 789 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
b5c80475
FF		 790 common->rx_bufsize,
791 DMA_FROM_DEVICE);
792
793 return bf;
794}
795
d435700f
S		 796/* Assumes you've already done the endian to CPU conversion */
797static bool ath9k_rx_accept(struct ath_common *common,
9f167f64 798 struct ieee80211_hdr *hdr,
d435700f
S		 799 struct ieee80211_rx_status *rxs,
800 struct ath_rx_status *rx_stats,
801 bool *decrypt_error)
802{
ec205999 803 struct ath_softc *sc = (struct ath_softc *) common->priv;
66760eac 804 bool is_mc, is_valid_tkip, strip_mic, mic_error;
d435700f 805 struct ath_hw *ah = common->ah;
d435700f 806 __le16 fc;
b7b1b512 807 u8 rx_status_len = ah->caps.rx_status_len;
d435700f 808
d435700f
S		 809 fc = hdr->frame_control;
810
66760eac
FF		 811 is_mc = !!is_multicast_ether_addr(hdr->addr1);
812 is_valid_tkip = rx_stats->rs_keyix != ATH9K_RXKEYIX_INVALID &&
813 test_bit(rx_stats->rs_keyix, common->tkip_keymap);
152e585d 814 strip_mic = is_valid_tkip && ieee80211_is_data(fc) &&
2a5783b8 815 ieee80211_has_protected(fc) &&
152e585d 816 !(rx_stats->rs_status &
846d9363
FF		 817 (ATH9K_RXERR_DECRYPT | ATH9K_RXERR_CRC | ATH9K_RXERR_MIC |
818 ATH9K_RXERR_KEYMISS));
66760eac 819
f88373fa
FF		 820 /*
821 * Key miss events are only relevant for pairwise keys where the
822 * descriptor does contain a valid key index. This has been observed
823 * mostly with CCMP encryption.
824 */
bed3d9c0
FF		 825 if (rx_stats->rs_keyix == ATH9K_RXKEYIX_INVALID ||
826 !test_bit(rx_stats->rs_keyix, common->ccmp_keymap))
f88373fa
FF		 827 rx_stats->rs_status &= ~ATH9K_RXERR_KEYMISS;
828
15072189
BG		 829 if (!rx_stats->rs_datalen) {
830 RX_STAT_INC(rx_len_err);
d435700f 831 return false;
15072189
BG		 832 }
833
d435700f
S		 834 /*
835 * rs_status follows rs_datalen so if rs_datalen is too large
836 * we can take a hint that hardware corrupted it, so ignore
837 * those frames.
838 */
15072189
BG		 839 if (rx_stats->rs_datalen > (common->rx_bufsize - rx_status_len)) {
840 RX_STAT_INC(rx_len_err);
d435700f 841 return false;
15072189 842 }
d435700f 843
0d95521e 844 /* Only use error bits from the last fragment */
d435700f 845 if (rx_stats->rs_more)
0d95521e 846 return true;
d435700f 847
66760eac
FF		 848 mic_error = is_valid_tkip && !ieee80211_is_ctl(fc) &&
849 !ieee80211_has_morefrags(fc) &&
850 !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) &&
851 (rx_stats->rs_status & ATH9K_RXERR_MIC);
852
d435700f
S		 853 /*
854 * The rx_stats->rs_status will not be set until the end of the
855 * chained descriptors so it can be ignored if rs_more is set. The
856 * rs_more will be false at the last element of the chained
857 * descriptors.
858 */
859 if (rx_stats->rs_status != 0) {
846d9363
FF		 860 u8 status_mask;
861
66760eac 862 if (rx_stats->rs_status & ATH9K_RXERR_CRC) {
d435700f 863 rxs->flag |= RX_FLAG_FAILED_FCS_CRC;
66760eac
FF		 864 mic_error = false;
865 }
d435700f
S		 866 if (rx_stats->rs_status & ATH9K_RXERR_PHY)
867 return false;
868
846d9363
FF		 869 if ((rx_stats->rs_status & ATH9K_RXERR_DECRYPT) ||
870 (!is_mc && (rx_stats->rs_status & ATH9K_RXERR_KEYMISS))) {
d435700f 871 *decrypt_error = true;
66760eac 872 mic_error = false;
d435700f 873 }
66760eac 874
d435700f
S		 875 /*
876 * Reject error frames with the exception of
877 * decryption and MIC failures. For monitor mode,
878 * we also ignore the CRC error.
879 */
846d9363
FF		 880 status_mask = ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
881 ATH9K_RXERR_KEYMISS;
882
ec205999 883 if (ah->is_monitoring && (sc->rx.rxfilter & FIF_FCSFAIL))
846d9363
FF		 884 status_mask |= ATH9K_RXERR_CRC;
885
886 if (rx_stats->rs_status & ~status_mask)
887 return false;
d435700f 888 }
66760eac
FF		 889
890 /*
891 * For unicast frames the MIC error bit can have false positives,
892 * so all MIC error reports need to be validated in software.
893 * False negatives are not common, so skip software verification
894 * if the hardware considers the MIC valid.
895 */
896 if (strip_mic)
897 rxs->flag |= RX_FLAG_MMIC_STRIPPED;
898 else if (is_mc && mic_error)
899 rxs->flag |= RX_FLAG_MMIC_ERROR;
900
d435700f
S		 901 return true;
902}
903
904static int ath9k_process_rate(struct ath_common *common,
905 struct ieee80211_hw *hw,
906 struct ath_rx_status *rx_stats,
9f167f64 907 struct ieee80211_rx_status *rxs)
d435700f
S		 908{
909 struct ieee80211_supported_band *sband;
910 enum ieee80211_band band;
911 unsigned int i = 0;
990e08a0 912 struct ath_softc __maybe_unused *sc = common->priv;
d435700f
S		 913
914 band = hw->conf.channel->band;
915 sband = hw->wiphy->bands[band];
916
917 if (rx_stats->rs_rate & 0x80) {
918 /* HT rate */
919 rxs->flag |= RX_FLAG_HT;
920 if (rx_stats->rs_flags & ATH9K_RX_2040)
921 rxs->flag |= RX_FLAG_40MHZ;
922 if (rx_stats->rs_flags & ATH9K_RX_GI)
923 rxs->flag |= RX_FLAG_SHORT_GI;
924 rxs->rate_idx = rx_stats->rs_rate & 0x7f;
925 return 0;
926 }
927
928 for (i = 0; i < sband->n_bitrates; i++) {
929 if (sband->bitrates[i].hw_value == rx_stats->rs_rate) {
930 rxs->rate_idx = i;
931 return 0;
932 }
933 if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) {
934 rxs->flag |= RX_FLAG_SHORTPRE;
935 rxs->rate_idx = i;
936 return 0;
937 }
938 }
939
940 /*
941 * No valid hardware bitrate found -- we should not get here
942 * because hardware has already validated this frame as OK.
943 */
d2182b69 944 ath_dbg(common, ANY,
226afe68
JP		 945 "unsupported hw bitrate detected 0x%02x using 1 Mbit\n",
946 rx_stats->rs_rate);
15072189 947 RX_STAT_INC(rx_rate_err);
d435700f
S		 948 return -EINVAL;
949}
950
951static void ath9k_process_rssi(struct ath_common *common,
952 struct ieee80211_hw *hw,
9f167f64 953 struct ieee80211_hdr *hdr,
d435700f
S		 954 struct ath_rx_status *rx_stats)
955{
9ac58615 956 struct ath_softc *sc = hw->priv;
d435700f 957 struct ath_hw *ah = common->ah;
9fa23e17 958 int last_rssi;
2ef16755 959 int rssi = rx_stats->rs_rssi;
d435700f 960
cf3af748
RM		 961 if (!rx_stats->is_mybeacon ||
962 ((ah->opmode != NL80211_IFTYPE_STATION) &&
963 (ah->opmode != NL80211_IFTYPE_ADHOC)))
9fa23e17
FF		 964 return;
965
9fa23e17 966 if (rx_stats->rs_rssi != ATH9K_RSSI_BAD && !rx_stats->rs_moreaggr)
9ac58615 967 ATH_RSSI_LPF(sc->last_rssi, rx_stats->rs_rssi);
d435700f 968
9ac58615 969 last_rssi = sc->last_rssi;
d435700f 970 if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
2ef16755
FF		 971 rssi = ATH_EP_RND(last_rssi, ATH_RSSI_EP_MULTIPLIER);
972 if (rssi < 0)
973 rssi = 0;
d435700f
S		 974
975 /* Update Beacon RSSI, this is used by ANI. */
2ef16755 976 ah->stats.avgbrssi = rssi;
d435700f
S		 977}
978
979/*
980 * For Decrypt or Demic errors, we only mark packet status here and always push
981 * up the frame up to let mac80211 handle the actual error case, be it no
982 * decryption key or real decryption error. This let us keep statistics there.
983 */
984static int ath9k_rx_skb_preprocess(struct ath_common *common,
985 struct ieee80211_hw *hw,
9f167f64 986 struct ieee80211_hdr *hdr,
d435700f
S		 987 struct ath_rx_status *rx_stats,
988 struct ieee80211_rx_status *rx_status,
989 bool *decrypt_error)
990{
f749b946
FF		 991 struct ath_hw *ah = common->ah;
992
d435700f
S		 993 /*
994 * everything but the rate is checked here, the rate check is done
995 * separately to avoid doing two lookups for a rate for each frame.
996 */
9f167f64 997 if (!ath9k_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error))
d435700f
S		 998 return -EINVAL;
999
0d95521e
FF		 1000 /* Only use status info from the last fragment */
1001 if (rx_stats->rs_more)
1002 return 0;
1003
9f167f64 1004 ath9k_process_rssi(common, hw, hdr, rx_stats);
d435700f 1005
9f167f64 1006 if (ath9k_process_rate(common, hw, rx_stats, rx_status))
d435700f
S		 1007 return -EINVAL;
1008
d435700f
S		 1009 rx_status->band = hw->conf.channel->band;
1010 rx_status->freq = hw->conf.channel->center_freq;
f749b946 1011 rx_status->signal = ah->noise + rx_stats->rs_rssi;
d435700f 1012 rx_status->antenna = rx_stats->rs_antenna;
6ebacbb7 1013 rx_status->flag |= RX_FLAG_MACTIME_MPDU;
2ef16755
FF		 1014 if (rx_stats->rs_moreaggr)
1015 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
d435700f
S		 1016
1017 return 0;
1018}
1019
1020static void ath9k_rx_skb_postprocess(struct ath_common *common,
1021 struct sk_buff *skb,
1022 struct ath_rx_status *rx_stats,
1023 struct ieee80211_rx_status *rxs,
1024 bool decrypt_error)
1025{
1026 struct ath_hw *ah = common->ah;
1027 struct ieee80211_hdr *hdr;
1028 int hdrlen, padpos, padsize;
1029 u8 keyix;
1030 __le16 fc;
1031
1032 /* see if any padding is done by the hw and remove it */
1033 hdr = (struct ieee80211_hdr *) skb->data;
1034 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1035 fc = hdr->frame_control;
1036 padpos = ath9k_cmn_padpos(hdr->frame_control);
1037
1038 /* The MAC header is padded to have 32-bit boundary if the
1039 * packet payload is non-zero. The general calculation for
1040 * padsize would take into account odd header lengths:
1041 * padsize = (4 - padpos % 4) % 4; However, since only
1042 * even-length headers are used, padding can only be 0 or 2
1043 * bytes and we can optimize this a bit. In addition, we must
1044 * not try to remove padding from short control frames that do
1045 * not have payload. */
1046 padsize = padpos & 3;
1047 if (padsize && skb->len>=padpos+padsize+FCS_LEN) {
1048 memmove(skb->data + padsize, skb->data, padpos);
1049 skb_pull(skb, padsize);
1050 }
1051
1052 keyix = rx_stats->rs_keyix;
1053
1054 if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error &&
1055 ieee80211_has_protected(fc)) {
1056 rxs->flag |= RX_FLAG_DECRYPTED;
1057 } else if (ieee80211_has_protected(fc)
1058 && !decrypt_error && skb->len >= hdrlen + 4) {
1059 keyix = skb->data[hdrlen + 3] >> 6;
1060
1061 if (test_bit(keyix, common->keymap))
1062 rxs->flag |= RX_FLAG_DECRYPTED;
1063 }
1064 if (ah->sw_mgmt_crypto &&
1065 (rxs->flag & RX_FLAG_DECRYPTED) &&
1066 ieee80211_is_mgmt(fc))
1067 /* Use software decrypt for management frames. */
1068 rxs->flag &= ~RX_FLAG_DECRYPTED;
1069}
b5c80475 1070
102885a5
VT		 1071static void ath_lnaconf_alt_good_scan(struct ath_ant_comb *antcomb,
1072 struct ath_hw_antcomb_conf ant_conf,
1073 int main_rssi_avg)
1074{
1075 antcomb->quick_scan_cnt = 0;
1076
1077 if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA2)
1078 antcomb->rssi_lna2 = main_rssi_avg;
1079 else if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA1)
1080 antcomb->rssi_lna1 = main_rssi_avg;
1081
1082 switch ((ant_conf.main_lna_conf << 4) | ant_conf.alt_lna_conf) {
223c5a87 1083 case 0x10: /* LNA2 A-B */
102885a5
VT		 1084 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1085 antcomb->first_quick_scan_conf =
1086 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1087 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1088 break;
223c5a87 1089 case 0x20: /* LNA1 A-B */
102885a5
VT		 1090 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1091 antcomb->first_quick_scan_conf =
1092 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1093 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
1094 break;
223c5a87 1095 case 0x21: /* LNA1 LNA2 */
102885a5
VT		 1096 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA2;
1097 antcomb->first_quick_scan_conf =
1098 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1099 antcomb->second_quick_scan_conf =
1100 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1101 break;
223c5a87 1102 case 0x12: /* LNA2 LNA1 */
102885a5
VT		 1103 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1;
1104 antcomb->first_quick_scan_conf =
1105 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1106 antcomb->second_quick_scan_conf =
1107 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1108 break;
223c5a87 1109 case 0x13: /* LNA2 A+B */
102885a5
VT		 1110 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1111 antcomb->first_quick_scan_conf =
1112 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1113 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1114 break;
223c5a87 1115 case 0x23: /* LNA1 A+B */
102885a5
VT		 1116 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1117 antcomb->first_quick_scan_conf =
1118 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1119 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
1120 break;
1121 default:
1122 break;
1123 }
1124}
1125
1126static void ath_select_ant_div_from_quick_scan(struct ath_ant_comb *antcomb,
1127 struct ath_hw_antcomb_conf *div_ant_conf,
1128 int main_rssi_avg, int alt_rssi_avg,
1129 int alt_ratio)
1130{
1131 /* alt_good */
1132 switch (antcomb->quick_scan_cnt) {
1133 case 0:
1134 /* set alt to main, and alt to first conf */
1135 div_ant_conf->main_lna_conf = antcomb->main_conf;
1136 div_ant_conf->alt_lna_conf = antcomb->first_quick_scan_conf;
1137 break;
1138 case 1:
1139 /* set alt to main, and alt to first conf */
1140 div_ant_conf->main_lna_conf = antcomb->main_conf;
1141 div_ant_conf->alt_lna_conf = antcomb->second_quick_scan_conf;
1142 antcomb->rssi_first = main_rssi_avg;
1143 antcomb->rssi_second = alt_rssi_avg;
1144
1145 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
1146 /* main is LNA1 */
1147 if (ath_is_alt_ant_ratio_better(alt_ratio,
1148 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
1149 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1150 main_rssi_avg, alt_rssi_avg,
1151 antcomb->total_pkt_count))
1152 antcomb->first_ratio = true;
1153 else
1154 antcomb->first_ratio = false;
1155 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
1156 if (ath_is_alt_ant_ratio_better(alt_ratio,
1157 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
1158 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1159 main_rssi_avg, alt_rssi_avg,
1160 antcomb->total_pkt_count))
1161 antcomb->first_ratio = true;
1162 else
1163 antcomb->first_ratio = false;
1164 } else {
1165 if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
1166 (alt_rssi_avg > main_rssi_avg +
1167 ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
1168 (alt_rssi_avg > main_rssi_avg)) &&
1169 (antcomb->total_pkt_count > 50))
1170 antcomb->first_ratio = true;
1171 else
1172 antcomb->first_ratio = false;
1173 }
1174 break;
1175 case 2:
1176 antcomb->alt_good = false;
1177 antcomb->scan_not_start = false;
1178 antcomb->scan = false;
1179 antcomb->rssi_first = main_rssi_avg;
1180 antcomb->rssi_third = alt_rssi_avg;
1181
1182 if (antcomb->second_quick_scan_conf == ATH_ANT_DIV_COMB_LNA1)
1183 antcomb->rssi_lna1 = alt_rssi_avg;
1184 else if (antcomb->second_quick_scan_conf ==
1185 ATH_ANT_DIV_COMB_LNA2)
1186 antcomb->rssi_lna2 = alt_rssi_avg;
1187 else if (antcomb->second_quick_scan_conf ==
1188 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2) {
1189 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2)
1190 antcomb->rssi_lna2 = main_rssi_avg;
1191 else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1)
1192 antcomb->rssi_lna1 = main_rssi_avg;
1193 }
1194
1195 if (antcomb->rssi_lna2 > antcomb->rssi_lna1 +
1196 ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)
1197 div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
1198 else
1199 div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA1;
1200
1201 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
1202 if (ath_is_alt_ant_ratio_better(alt_ratio,
1203 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
1204 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1205 main_rssi_avg, alt_rssi_avg,
1206 antcomb->total_pkt_count))
1207 antcomb->second_ratio = true;
1208 else
1209 antcomb->second_ratio = false;
1210 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
1211 if (ath_is_alt_ant_ratio_better(alt_ratio,
1212 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
1213 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1214 main_rssi_avg, alt_rssi_avg,
1215 antcomb->total_pkt_count))
1216 antcomb->second_ratio = true;
1217 else
1218 antcomb->second_ratio = false;
1219 } else {
1220 if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
1221 (alt_rssi_avg > main_rssi_avg +
1222 ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
1223 (alt_rssi_avg > main_rssi_avg)) &&
1224 (antcomb->total_pkt_count > 50))
1225 antcomb->second_ratio = true;
1226 else
1227 antcomb->second_ratio = false;
1228 }
1229
1230 /* set alt to the conf with maximun ratio */
1231 if (antcomb->first_ratio && antcomb->second_ratio) {
1232 if (antcomb->rssi_second > antcomb->rssi_third) {
1233 /* first alt*/
1234 if ((antcomb->first_quick_scan_conf ==
1235 ATH_ANT_DIV_COMB_LNA1) ||
1236 (antcomb->first_quick_scan_conf ==
1237 ATH_ANT_DIV_COMB_LNA2))
1238 /* Set alt LNA1 or LNA2*/
1239 if (div_ant_conf->main_lna_conf ==
1240 ATH_ANT_DIV_COMB_LNA2)
1241 div_ant_conf->alt_lna_conf =
1242 ATH_ANT_DIV_COMB_LNA1;
1243 else
1244 div_ant_conf->alt_lna_conf =
1245 ATH_ANT_DIV_COMB_LNA2;
1246 else
1247 /* Set alt to A+B or A-B */
1248 div_ant_conf->alt_lna_conf =
1249 antcomb->first_quick_scan_conf;
1250 } else if ((antcomb->second_quick_scan_conf ==
1251 ATH_ANT_DIV_COMB_LNA1) ||
1252 (antcomb->second_quick_scan_conf ==
1253 ATH_ANT_DIV_COMB_LNA2)) {
1254 /* Set alt LNA1 or LNA2 */
1255 if (div_ant_conf->main_lna_conf ==
1256 ATH_ANT_DIV_COMB_LNA2)
1257 div_ant_conf->alt_lna_conf =
1258 ATH_ANT_DIV_COMB_LNA1;
1259 else
1260 div_ant_conf->alt_lna_conf =
1261 ATH_ANT_DIV_COMB_LNA2;
1262 } else {
1263 /* Set alt to A+B or A-B */
1264 div_ant_conf->alt_lna_conf =
1265 antcomb->second_quick_scan_conf;
1266 }
1267 } else if (antcomb->first_ratio) {
1268 /* first alt */
1269 if ((antcomb->first_quick_scan_conf ==
1270 ATH_ANT_DIV_COMB_LNA1) ||
1271 (antcomb->first_quick_scan_conf ==
1272 ATH_ANT_DIV_COMB_LNA2))
1273 /* Set alt LNA1 or LNA2 */
1274 if (div_ant_conf->main_lna_conf ==
1275 ATH_ANT_DIV_COMB_LNA2)
1276 div_ant_conf->alt_lna_conf =
1277 ATH_ANT_DIV_COMB_LNA1;
1278 else
1279 div_ant_conf->alt_lna_conf =
1280 ATH_ANT_DIV_COMB_LNA2;
1281 else
1282 /* Set alt to A+B or A-B */
1283 div_ant_conf->alt_lna_conf =
1284 antcomb->first_quick_scan_conf;
1285 } else if (antcomb->second_ratio) {
1286 /* second alt */
1287 if ((antcomb->second_quick_scan_conf ==
1288 ATH_ANT_DIV_COMB_LNA1) ||
1289 (antcomb->second_quick_scan_conf ==
1290 ATH_ANT_DIV_COMB_LNA2))
1291 /* Set alt LNA1 or LNA2 */
1292 if (div_ant_conf->main_lna_conf ==
1293 ATH_ANT_DIV_COMB_LNA2)
1294 div_ant_conf->alt_lna_conf =
1295 ATH_ANT_DIV_COMB_LNA1;
1296 else
1297 div_ant_conf->alt_lna_conf =
1298 ATH_ANT_DIV_COMB_LNA2;
1299 else
1300 /* Set alt to A+B or A-B */
1301 div_ant_conf->alt_lna_conf =
1302 antcomb->second_quick_scan_conf;
1303 } else {
1304 /* main is largest */
1305 if ((antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) ||
1306 (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2))
1307 /* Set alt LNA1 or LNA2 */
1308 if (div_ant_conf->main_lna_conf ==
1309 ATH_ANT_DIV_COMB_LNA2)
1310 div_ant_conf->alt_lna_conf =
1311 ATH_ANT_DIV_COMB_LNA1;
1312 else
1313 div_ant_conf->alt_lna_conf =
1314 ATH_ANT_DIV_COMB_LNA2;
1315 else
1316 /* Set alt to A+B or A-B */
1317 div_ant_conf->alt_lna_conf = antcomb->main_conf;
1318 }
1319 break;
1320 default:
1321 break;
1322 }
1323}
1324
3e9a212a
MSS		 1325static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf,
1326 struct ath_ant_comb *antcomb, int alt_ratio)
102885a5 1327{
3e9a212a
MSS		 1328 if (ant_conf->div_group == 0) {
1329 /* Adjust the fast_div_bias based on main and alt lna conf */
1330 switch ((ant_conf->main_lna_conf << 4) |
1331 ant_conf->alt_lna_conf) {
223c5a87 1332 case 0x01: /* A-B LNA2 */
3e9a212a
MSS		 1333 ant_conf->fast_div_bias = 0x3b;
1334 break;
223c5a87 1335 case 0x02: /* A-B LNA1 */
3e9a212a
MSS		 1336 ant_conf->fast_div_bias = 0x3d;
1337 break;
223c5a87 1338 case 0x03: /* A-B A+B */
3e9a212a
MSS		 1339 ant_conf->fast_div_bias = 0x1;
1340 break;
223c5a87 1341 case 0x10: /* LNA2 A-B */
3e9a212a
MSS		 1342 ant_conf->fast_div_bias = 0x7;
1343 break;
223c5a87 1344 case 0x12: /* LNA2 LNA1 */
3e9a212a
MSS		 1345 ant_conf->fast_div_bias = 0x2;
1346 break;
223c5a87 1347 case 0x13: /* LNA2 A+B */
3e9a212a
MSS		 1348 ant_conf->fast_div_bias = 0x7;
1349 break;
223c5a87 1350 case 0x20: /* LNA1 A-B */
3e9a212a
MSS		 1351 ant_conf->fast_div_bias = 0x6;
1352 break;
223c5a87 1353 case 0x21: /* LNA1 LNA2 */
3e9a212a
MSS		 1354 ant_conf->fast_div_bias = 0x0;
1355 break;
223c5a87 1356 case 0x23: /* LNA1 A+B */
3e9a212a
MSS		 1357 ant_conf->fast_div_bias = 0x6;
1358 break;
223c5a87 1359 case 0x30: /* A+B A-B */
3e9a212a
MSS		 1360 ant_conf->fast_div_bias = 0x1;
1361 break;
223c5a87 1362 case 0x31: /* A+B LNA2 */
3e9a212a
MSS		 1363 ant_conf->fast_div_bias = 0x3b;
1364 break;
223c5a87 1365 case 0x32: /* A+B LNA1 */
3e9a212a
MSS		 1366 ant_conf->fast_div_bias = 0x3d;
1367 break;
1368 default:
1369 break;
1370 }
e7ef5bc0
GJ		 1371 } else if (ant_conf->div_group == 1) {
1372 /* Adjust the fast_div_bias based on main and alt_lna_conf */
1373 switch ((ant_conf->main_lna_conf << 4) |
1374 ant_conf->alt_lna_conf) {
1375 case 0x01: /* A-B LNA2 */
1376 ant_conf->fast_div_bias = 0x1;
1377 ant_conf->main_gaintb = 0;
1378 ant_conf->alt_gaintb = 0;
1379 break;
1380 case 0x02: /* A-B LNA1 */
1381 ant_conf->fast_div_bias = 0x1;
1382 ant_conf->main_gaintb = 0;
1383 ant_conf->alt_gaintb = 0;
1384 break;
1385 case 0x03: /* A-B A+B */
1386 ant_conf->fast_div_bias = 0x1;
1387 ant_conf->main_gaintb = 0;
1388 ant_conf->alt_gaintb = 0;
1389 break;
1390 case 0x10: /* LNA2 A-B */
1391 if (!(antcomb->scan) &&
1392 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1393 ant_conf->fast_div_bias = 0x3f;
1394 else
1395 ant_conf->fast_div_bias = 0x1;
1396 ant_conf->main_gaintb = 0;
1397 ant_conf->alt_gaintb = 0;
1398 break;
1399 case 0x12: /* LNA2 LNA1 */
1400 ant_conf->fast_div_bias = 0x1;
1401 ant_conf->main_gaintb = 0;
1402 ant_conf->alt_gaintb = 0;
1403 break;
1404 case 0x13: /* LNA2 A+B */
1405 if (!(antcomb->scan) &&
1406 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1407 ant_conf->fast_div_bias = 0x3f;
1408 else
1409 ant_conf->fast_div_bias = 0x1;
1410 ant_conf->main_gaintb = 0;
1411 ant_conf->alt_gaintb = 0;
1412 break;
1413 case 0x20: /* LNA1 A-B */
1414 if (!(antcomb->scan) &&
1415 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1416 ant_conf->fast_div_bias = 0x3f;
1417 else
1418 ant_conf->fast_div_bias = 0x1;
1419 ant_conf->main_gaintb = 0;
1420 ant_conf->alt_gaintb = 0;
1421 break;
1422 case 0x21: /* LNA1 LNA2 */
1423 ant_conf->fast_div_bias = 0x1;
1424 ant_conf->main_gaintb = 0;
1425 ant_conf->alt_gaintb = 0;
1426 break;
1427 case 0x23: /* LNA1 A+B */
1428 if (!(antcomb->scan) &&
1429 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1430 ant_conf->fast_div_bias = 0x3f;
1431 else
1432 ant_conf->fast_div_bias = 0x1;
1433 ant_conf->main_gaintb = 0;
1434 ant_conf->alt_gaintb = 0;
1435 break;
1436 case 0x30: /* A+B A-B */
1437 ant_conf->fast_div_bias = 0x1;
1438 ant_conf->main_gaintb = 0;
1439 ant_conf->alt_gaintb = 0;
1440 break;
1441 case 0x31: /* A+B LNA2 */
1442 ant_conf->fast_div_bias = 0x1;
1443 ant_conf->main_gaintb = 0;
1444 ant_conf->alt_gaintb = 0;
1445 break;
1446 case 0x32: /* A+B LNA1 */
1447 ant_conf->fast_div_bias = 0x1;
1448 ant_conf->main_gaintb = 0;
1449 ant_conf->alt_gaintb = 0;
1450 break;
1451 default:
1452 break;
1453 }
3e9a212a
MSS		 1454 } else if (ant_conf->div_group == 2) {
1455 /* Adjust the fast_div_bias based on main and alt_lna_conf */
1456 switch ((ant_conf->main_lna_conf << 4) |
1457 ant_conf->alt_lna_conf) {
223c5a87 1458 case 0x01: /* A-B LNA2 */
3e9a212a
MSS		 1459 ant_conf->fast_div_bias = 0x1;
1460 ant_conf->main_gaintb = 0;
1461 ant_conf->alt_gaintb = 0;
1462 break;
223c5a87 1463 case 0x02: /* A-B LNA1 */
3e9a212a
MSS		 1464 ant_conf->fast_div_bias = 0x1;
1465 ant_conf->main_gaintb = 0;
1466 ant_conf->alt_gaintb = 0;
1467 break;
223c5a87 1468 case 0x03: /* A-B A+B */
3e9a212a
MSS		 1469 ant_conf->fast_div_bias = 0x1;
1470 ant_conf->main_gaintb = 0;
1471 ant_conf->alt_gaintb = 0;
1472 break;
223c5a87 1473 case 0x10: /* LNA2 A-B */
3e9a212a
MSS		 1474 if (!(antcomb->scan) &&
1475 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1476 ant_conf->fast_div_bias = 0x1;
1477 else
1478 ant_conf->fast_div_bias = 0x2;
1479 ant_conf->main_gaintb = 0;
1480 ant_conf->alt_gaintb = 0;
1481 break;
223c5a87 1482 case 0x12: /* LNA2 LNA1 */
3e9a212a
MSS		 1483 ant_conf->fast_div_bias = 0x1;
1484 ant_conf->main_gaintb = 0;
1485 ant_conf->alt_gaintb = 0;
1486 break;
223c5a87 1487 case 0x13: /* LNA2 A+B */
3e9a212a
MSS		 1488 if (!(antcomb->scan) &&
1489 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1490 ant_conf->fast_div_bias = 0x1;
1491 else
1492 ant_conf->fast_div_bias = 0x2;
1493 ant_conf->main_gaintb = 0;
1494 ant_conf->alt_gaintb = 0;
1495 break;
223c5a87 1496 case 0x20: /* LNA1 A-B */
3e9a212a
MSS		 1497 if (!(antcomb->scan) &&
1498 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1499 ant_conf->fast_div_bias = 0x1;
1500 else
1501 ant_conf->fast_div_bias = 0x2;
1502 ant_conf->main_gaintb = 0;
1503 ant_conf->alt_gaintb = 0;
1504 break;
223c5a87 1505 case 0x21: /* LNA1 LNA2 */
3e9a212a
MSS		 1506 ant_conf->fast_div_bias = 0x1;
1507 ant_conf->main_gaintb = 0;
1508 ant_conf->alt_gaintb = 0;
1509 break;
223c5a87 1510 case 0x23: /* LNA1 A+B */
3e9a212a
MSS		 1511 if (!(antcomb->scan) &&
1512 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1513 ant_conf->fast_div_bias = 0x1;
1514 else
1515 ant_conf->fast_div_bias = 0x2;
1516 ant_conf->main_gaintb = 0;
1517 ant_conf->alt_gaintb = 0;
1518 break;
223c5a87 1519 case 0x30: /* A+B A-B */
3e9a212a
MSS		 1520 ant_conf->fast_div_bias = 0x1;
1521 ant_conf->main_gaintb = 0;
1522 ant_conf->alt_gaintb = 0;
1523 break;
223c5a87 1524 case 0x31: /* A+B LNA2 */
3e9a212a
MSS		 1525 ant_conf->fast_div_bias = 0x1;
1526 ant_conf->main_gaintb = 0;
1527 ant_conf->alt_gaintb = 0;
1528 break;
223c5a87 1529 case 0x32: /* A+B LNA1 */
3e9a212a
MSS		 1530 ant_conf->fast_div_bias = 0x1;
1531 ant_conf->main_gaintb = 0;
1532 ant_conf->alt_gaintb = 0;
1533 break;
1534 default:
1535 break;
1536 }
102885a5
VT		 1537 }
1538}
1539
1540/* Antenna diversity and combining */
1541static void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs)
1542{
1543 struct ath_hw_antcomb_conf div_ant_conf;
1544 struct ath_ant_comb *antcomb = &sc->ant_comb;
1545 int alt_ratio = 0, alt_rssi_avg = 0, main_rssi_avg = 0, curr_alt_set;
0ff2b5c0 1546 int curr_main_set;
102885a5
VT		 1547 int main_rssi = rs->rs_rssi_ctl0;
1548 int alt_rssi = rs->rs_rssi_ctl1;
1549 int rx_ant_conf, main_ant_conf;
1550 bool short_scan = false;
1551
1552 rx_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_CURRENT_SHIFT) &
1553 ATH_ANT_RX_MASK;
1554 main_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_MAIN_SHIFT) &
1555 ATH_ANT_RX_MASK;
1556
21e8ee6d
MSS		 1557 /* Record packet only when both main_rssi and alt_rssi is positive */
1558 if (main_rssi > 0 && alt_rssi > 0) {
102885a5
VT		 1559 antcomb->total_pkt_count++;
1560 antcomb->main_total_rssi += main_rssi;
1561 antcomb->alt_total_rssi += alt_rssi;
1562 if (main_ant_conf == rx_ant_conf)
1563 antcomb->main_recv_cnt++;
1564 else
1565 antcomb->alt_recv_cnt++;
1566 }
1567
1568 /* Short scan check */
1569 if (antcomb->scan && antcomb->alt_good) {
1570 if (time_after(jiffies, antcomb->scan_start_time +
1571 msecs_to_jiffies(ATH_ANT_DIV_COMB_SHORT_SCAN_INTR)))
1572 short_scan = true;
1573 else
1574 if (antcomb->total_pkt_count ==
1575 ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT) {
1576 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
1577 antcomb->total_pkt_count);
1578 if (alt_ratio < ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
1579 short_scan = true;
1580 }
1581 }
1582
1583 if (((antcomb->total_pkt_count < ATH_ANT_DIV_COMB_MAX_PKTCOUNT) ||
1584 rs->rs_moreaggr) && !short_scan)
1585 return;
1586
1587 if (antcomb->total_pkt_count) {
1588 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
1589 antcomb->total_pkt_count);
1590 main_rssi_avg = (antcomb->main_total_rssi /
1591 antcomb->total_pkt_count);
1592 alt_rssi_avg = (antcomb->alt_total_rssi /
1593 antcomb->total_pkt_count);
1594 }
1595
1596
1597 ath9k_hw_antdiv_comb_conf_get(sc->sc_ah, &div_ant_conf);
1598 curr_alt_set = div_ant_conf.alt_lna_conf;
1599 curr_main_set = div_ant_conf.main_lna_conf;
102885a5
VT		 1600
1601 antcomb->count++;
1602
1603 if (antcomb->count == ATH_ANT_DIV_COMB_MAX_COUNT) {
1604 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) {
1605 ath_lnaconf_alt_good_scan(antcomb, div_ant_conf,
1606 main_rssi_avg);
1607 antcomb->alt_good = true;
1608 } else {
1609 antcomb->alt_good = false;
1610 }
1611
1612 antcomb->count = 0;
1613 antcomb->scan = true;
1614 antcomb->scan_not_start = true;
1615 }
1616
1617 if (!antcomb->scan) {
b85c5734
MSS		 1618 if (ath_ant_div_comb_alt_check(div_ant_conf.div_group,
1619 alt_ratio, curr_main_set, curr_alt_set,
1620 alt_rssi_avg, main_rssi_avg)) {
102885a5
VT		 1621 if (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) {
1622 /* Switch main and alt LNA */
1623 div_ant_conf.main_lna_conf =
1624 ATH_ANT_DIV_COMB_LNA2;
1625 div_ant_conf.alt_lna_conf =
1626 ATH_ANT_DIV_COMB_LNA1;
1627 } else if (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) {
1628 div_ant_conf.main_lna_conf =
1629 ATH_ANT_DIV_COMB_LNA1;
1630 div_ant_conf.alt_lna_conf =
1631 ATH_ANT_DIV_COMB_LNA2;
1632 }
1633
1634 goto div_comb_done;
1635 } else if ((curr_alt_set != ATH_ANT_DIV_COMB_LNA1) &&
1636 (curr_alt_set != ATH_ANT_DIV_COMB_LNA2)) {
1637 /* Set alt to another LNA */
1638 if (curr_main_set == ATH_ANT_DIV_COMB_LNA2)
1639 div_ant_conf.alt_lna_conf =
1640 ATH_ANT_DIV_COMB_LNA1;
1641 else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1)
1642 div_ant_conf.alt_lna_conf =
1643 ATH_ANT_DIV_COMB_LNA2;
1644
1645 goto div_comb_done;
1646 }
1647
1648 if ((alt_rssi_avg < (main_rssi_avg +
8afbcc8b 1649 div_ant_conf.lna1_lna2_delta)))
102885a5
VT		 1650 goto div_comb_done;
1651 }
1652
1653 if (!antcomb->scan_not_start) {
1654 switch (curr_alt_set) {
1655 case ATH_ANT_DIV_COMB_LNA2:
1656 antcomb->rssi_lna2 = alt_rssi_avg;
1657 antcomb->rssi_lna1 = main_rssi_avg;
1658 antcomb->scan = true;
1659 /* set to A+B */
1660 div_ant_conf.main_lna_conf =
1661 ATH_ANT_DIV_COMB_LNA1;
1662 div_ant_conf.alt_lna_conf =
1663 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1664 break;
1665 case ATH_ANT_DIV_COMB_LNA1:
1666 antcomb->rssi_lna1 = alt_rssi_avg;
1667 antcomb->rssi_lna2 = main_rssi_avg;
1668 antcomb->scan = true;
1669 /* set to A+B */
1670 div_ant_conf.main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
1671 div_ant_conf.alt_lna_conf =
1672 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1673 break;
1674 case ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2:
1675 antcomb->rssi_add = alt_rssi_avg;
1676 antcomb->scan = true;
1677 /* set to A-B */
1678 div_ant_conf.alt_lna_conf =
1679 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1680 break;
1681 case ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2:
1682 antcomb->rssi_sub = alt_rssi_avg;
1683 antcomb->scan = false;
1684 if (antcomb->rssi_lna2 >
1685 (antcomb->rssi_lna1 +
1686 ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)) {
1687 /* use LNA2 as main LNA */
1688 if ((antcomb->rssi_add > antcomb->rssi_lna1) &&
1689 (antcomb->rssi_add > antcomb->rssi_sub)) {
1690 /* set to A+B */
1691 div_ant_conf.main_lna_conf =
1692 ATH_ANT_DIV_COMB_LNA2;
1693 div_ant_conf.alt_lna_conf =
1694 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1695 } else if (antcomb->rssi_sub >
1696 antcomb->rssi_lna1) {
1697 /* set to A-B */
1698 div_ant_conf.main_lna_conf =
1699 ATH_ANT_DIV_COMB_LNA2;
1700 div_ant_conf.alt_lna_conf =
1701 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1702 } else {
1703 /* set to LNA1 */
1704 div_ant_conf.main_lna_conf =
1705 ATH_ANT_DIV_COMB_LNA2;
1706 div_ant_conf.alt_lna_conf =
1707 ATH_ANT_DIV_COMB_LNA1;
1708 }
1709 } else {
1710 /* use LNA1 as main LNA */
1711 if ((antcomb->rssi_add > antcomb->rssi_lna2) &&
1712 (antcomb->rssi_add > antcomb->rssi_sub)) {
1713 /* set to A+B */
1714 div_ant_conf.main_lna_conf =
1715 ATH_ANT_DIV_COMB_LNA1;
1716 div_ant_conf.alt_lna_conf =
1717 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1718 } else if (antcomb->rssi_sub >
1719 antcomb->rssi_lna1) {
1720 /* set to A-B */
1721 div_ant_conf.main_lna_conf =
1722 ATH_ANT_DIV_COMB_LNA1;
1723 div_ant_conf.alt_lna_conf =
1724 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1725 } else {
1726 /* set to LNA2 */
1727 div_ant_conf.main_lna_conf =
1728 ATH_ANT_DIV_COMB_LNA1;
1729 div_ant_conf.alt_lna_conf =
1730 ATH_ANT_DIV_COMB_LNA2;
1731 }
1732 }
1733 break;
1734 default:
1735 break;
1736 }
1737 } else {
1738 if (!antcomb->alt_good) {
1739 antcomb->scan_not_start = false;
1740 /* Set alt to another LNA */
1741 if (curr_main_set == ATH_ANT_DIV_COMB_LNA2) {
1742 div_ant_conf.main_lna_conf =
1743 ATH_ANT_DIV_COMB_LNA2;
1744 div_ant_conf.alt_lna_conf =
1745 ATH_ANT_DIV_COMB_LNA1;
1746 } else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1) {
1747 div_ant_conf.main_lna_conf =
1748 ATH_ANT_DIV_COMB_LNA1;
1749 div_ant_conf.alt_lna_conf =
1750 ATH_ANT_DIV_COMB_LNA2;
1751 }
1752 goto div_comb_done;
1753 }
1754 }
1755
1756 ath_select_ant_div_from_quick_scan(antcomb, &div_ant_conf,
1757 main_rssi_avg, alt_rssi_avg,
1758 alt_ratio);
1759
1760 antcomb->quick_scan_cnt++;
1761
1762div_comb_done:
3e9a212a 1763 ath_ant_div_conf_fast_divbias(&div_ant_conf, antcomb, alt_ratio);
102885a5
VT		 1764 ath9k_hw_antdiv_comb_conf_set(sc->sc_ah, &div_ant_conf);
1765
1766 antcomb->scan_start_time = jiffies;
1767 antcomb->total_pkt_count = 0;
1768 antcomb->main_total_rssi = 0;
1769 antcomb->alt_total_rssi = 0;
1770 antcomb->main_recv_cnt = 0;
1771 antcomb->alt_recv_cnt = 0;
1772}
1773
b5c80475
FF		 1774int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
1775{
1776 struct ath_buf *bf;
0d95521e 1777 struct sk_buff *skb = NULL, *requeue_skb, *hdr_skb;
5ca42627 1778 struct ieee80211_rx_status *rxs;
cbe61d8a 1779 struct ath_hw *ah = sc->sc_ah;
27c51f1a 1780 struct ath_common *common = ath9k_hw_common(ah);
7545daf4 1781 struct ieee80211_hw *hw = sc->hw;
be0418ad 1782 struct ieee80211_hdr *hdr;
c9b14170 1783 int retval;
be0418ad 1784 bool decrypt_error = false;
29bffa96 1785 struct ath_rx_status rs;
b5c80475
FF		 1786 enum ath9k_rx_qtype qtype;
1787 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1788 int dma_type;
5c6dd921 1789 u8 rx_status_len = ah->caps.rx_status_len;
a6d2055b
FF		 1790 u64 tsf = 0;
1791 u32 tsf_lower = 0;
8ab2cd09 1792 unsigned long flags;
be0418ad 1793
b5c80475 1794 if (edma)
b5c80475 1795 dma_type = DMA_BIDIRECTIONAL;
56824223
ML		 1796 else
1797 dma_type = DMA_FROM_DEVICE;
b5c80475
FF		 1798
1799 qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
b77f483f 1800 spin_lock_bh(&sc->rx.rxbuflock);
f078f209 1801
a6d2055b
FF		 1802 tsf = ath9k_hw_gettsf64(ah);
1803 tsf_lower = tsf & 0xffffffff;
1804
f078f209
LR		 1805 do {
1806 /* If handling rx interrupt and flush is in progress => exit */
98deeea0 1807 if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
f078f209
LR		 1808 break;
1809
29bffa96 1810 memset(&rs, 0, sizeof(rs));
b5c80475
FF		 1811 if (edma)
1812 bf = ath_edma_get_next_rx_buf(sc, &rs, qtype);
1813 else
1814 bf = ath_get_next_rx_buf(sc, &rs);
f078f209 1815
b5c80475
FF		 1816 if (!bf)
1817 break;
f078f209 1818
f078f209 1819 skb = bf->bf_mpdu;
be0418ad 1820 if (!skb)
f078f209 1821 continue;
f078f209 1822
0d95521e
FF		 1823 /*
1824 * Take frame header from the first fragment and RX status from
1825 * the last one.
1826 */
1827 if (sc->rx.frag)
1828 hdr_skb = sc->rx.frag;
1829 else
1830 hdr_skb = skb;
1831
1832 hdr = (struct ieee80211_hdr *) (hdr_skb->data + rx_status_len);
1833 rxs = IEEE80211_SKB_RXCB(hdr_skb);
15072189
BG		 1834 if (ieee80211_is_beacon(hdr->frame_control)) {
1835 RX_STAT_INC(rx_beacons);
1836 if (!is_zero_ether_addr(common->curbssid) &&
2e42e474 1837 ether_addr_equal(hdr->addr3, common->curbssid))
15072189
BG		 1838 rs.is_mybeacon = true;
1839 else
1840 rs.is_mybeacon = false;
1841 }
cf3af748
RM		 1842 else
1843 rs.is_mybeacon = false;
5ca42627 1844
29bffa96 1845 ath_debug_stat_rx(sc, &rs);
1395d3f0 1846
f078f209 1847 /*
be0418ad
S		 1848 * If we're asked to flush receive queue, directly
1849 * chain it back at the queue without processing it.
f078f209 1850 */
15072189
BG		 1851 if (sc->sc_flags & SC_OP_RXFLUSH) {
1852 RX_STAT_INC(rx_drop_rxflush);
0d95521e 1853 goto requeue_drop_frag;
15072189 1854 }
f078f209 1855
ffb1c56a
AN		 1856 memset(rxs, 0, sizeof(struct ieee80211_rx_status));
1857
a6d2055b
FF		 1858 rxs->mactime = (tsf & ~0xffffffffULL) | rs.rs_tstamp;
1859 if (rs.rs_tstamp > tsf_lower &&
1860 unlikely(rs.rs_tstamp - tsf_lower > 0x10000000))
1861 rxs->mactime -= 0x100000000ULL;
1862
1863 if (rs.rs_tstamp < tsf_lower &&
1864 unlikely(tsf_lower - rs.rs_tstamp > 0x10000000))
1865 rxs->mactime += 0x100000000ULL;
1866
83c76570
ZK		 1867 retval = ath9k_rx_skb_preprocess(common, hw, hdr, &rs,
1868 rxs, &decrypt_error);
1869 if (retval)
1870 goto requeue_drop_frag;
1871
01e18918
RM		 1872 if (rs.is_mybeacon) {
1873 sc->hw_busy_count = 0;
1874 ath_start_rx_poll(sc, 3);
1875 }
cb71d9ba
LR		 1876 /* Ensure we always have an skb to requeue once we are done
1877 * processing the current buffer's skb */
cc861f74 1878 requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC);
cb71d9ba
LR		 1879
1880 /* If there is no memory we ignore the current RX'd frame,
1881 * tell hardware it can give us a new frame using the old
b77f483f 1882 * skb and put it at the tail of the sc->rx.rxbuf list for
cb71d9ba 1883 * processing. */
15072189
BG		 1884 if (!requeue_skb) {
1885 RX_STAT_INC(rx_oom_err);
0d95521e 1886 goto requeue_drop_frag;
15072189 1887 }
f078f209 1888
9bf9fca8 1889 /* Unmap the frame */
7da3c55c 1890 dma_unmap_single(sc->dev, bf->bf_buf_addr,
cc861f74 1891 common->rx_bufsize,
b5c80475 1892 dma_type);
f078f209 1893
b5c80475
FF		 1894 skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len);
1895 if (ah->caps.rx_status_len)
1896 skb_pull(skb, ah->caps.rx_status_len);
be0418ad 1897
0d95521e
FF		 1898 if (!rs.rs_more)
1899 ath9k_rx_skb_postprocess(common, hdr_skb, &rs,
1900 rxs, decrypt_error);
be0418ad 1901
cb71d9ba
LR		 1902 /* We will now give hardware our shiny new allocated skb */
1903 bf->bf_mpdu = requeue_skb;
7da3c55c 1904 bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
cc861f74 1905 common->rx_bufsize,
b5c80475 1906 dma_type);
7da3c55c 1907 if (unlikely(dma_mapping_error(sc->dev,
f8316df1
LR		 1908 bf->bf_buf_addr))) {
1909 dev_kfree_skb_any(requeue_skb);
1910 bf->bf_mpdu = NULL;
6cf9e995 1911 bf->bf_buf_addr = 0;
3800276a 1912 ath_err(common, "dma_mapping_error() on RX\n");
7545daf4 1913 ieee80211_rx(hw, skb);
f8316df1
LR		 1914 break;
1915 }
f078f209 1916
0d95521e 1917 if (rs.rs_more) {
15072189 1918 RX_STAT_INC(rx_frags);
0d95521e
FF		 1919 /*
1920 * rs_more indicates chained descriptors which can be
1921 * used to link buffers together for a sort of
1922 * scatter-gather operation.
1923 */
1924 if (sc->rx.frag) {
1925 /* too many fragments - cannot handle frame */
1926 dev_kfree_skb_any(sc->rx.frag);
1927 dev_kfree_skb_any(skb);
15072189 1928 RX_STAT_INC(rx_too_many_frags_err);
0d95521e
FF		 1929 skb = NULL;
1930 }
1931 sc->rx.frag = skb;
1932 goto requeue;
1933 }
1934
1935 if (sc->rx.frag) {
1936 int space = skb->len - skb_tailroom(hdr_skb);
1937
0d95521e
FF		 1938 if (pskb_expand_head(hdr_skb, 0, space, GFP_ATOMIC) < 0) {
1939 dev_kfree_skb(skb);
15072189 1940 RX_STAT_INC(rx_oom_err);
0d95521e
FF		 1941 goto requeue_drop_frag;
1942 }
1943
b5447ff9
ED		 1944 sc->rx.frag = NULL;
1945
0d95521e
FF		 1946 skb_copy_from_linear_data(skb, skb_put(hdr_skb, skb->len),
1947 skb->len);
1948 dev_kfree_skb_any(skb);
1949 skb = hdr_skb;
1950 }
1951
eb840a80
MSS		 1952
1953 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {
1954
1955 /*
1956 * change the default rx antenna if rx diversity
1957 * chooses the other antenna 3 times in a row.
1958 */
1959 if (sc->rx.defant != rs.rs_antenna) {
1960 if (++sc->rx.rxotherant >= 3)
1961 ath_setdefantenna(sc, rs.rs_antenna);
1962 } else {
1963 sc->rx.rxotherant = 0;
1964 }
1965
f078f209 1966 }
3cbb5dd7 1967
66760eac
FF		 1968 if (rxs->flag & RX_FLAG_MMIC_STRIPPED)
1969 skb_trim(skb, skb->len - 8);
1970
8ab2cd09 1971 spin_lock_irqsave(&sc->sc_pm_lock, flags);
aaef24b4
MSS		 1972
1973 if ((sc->ps_flags & (PS_WAIT_FOR_BEACON |
f73c604c
RM		 1974 PS_WAIT_FOR_CAB |
1975 PS_WAIT_FOR_PSPOLL_DATA)) ||
1976 ath9k_check_auto_sleep(sc))
1977 ath_rx_ps(sc, skb, rs.is_mybeacon);
8ab2cd09 1978 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
cc65965c 1979
43c35284 1980 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx == 3)
102885a5
VT		 1981 ath_ant_comb_scan(sc, &rs);
1982
7545daf4 1983 ieee80211_rx(hw, skb);
cc65965c 1984
0d95521e
FF		 1985requeue_drop_frag:
1986 if (sc->rx.frag) {
1987 dev_kfree_skb_any(sc->rx.frag);
1988 sc->rx.frag = NULL;
1989 }
cb71d9ba 1990requeue:
b5c80475
FF		 1991 if (edma) {
1992 list_add_tail(&bf->list, &sc->rx.rxbuf);
1993 ath_rx_edma_buf_link(sc, qtype);
1994 } else {
1995 list_move_tail(&bf->list, &sc->rx.rxbuf);
1996 ath_rx_buf_link(sc, bf);
3483288c
FF		 1997 if (!flush)
1998 ath9k_hw_rxena(ah);
b5c80475 1999 }
be0418ad
S		 2000 } while (1);
2001
b77f483f 2002 spin_unlock_bh(&sc->rx.rxbuflock);
f078f209 2003
29ab0b36
RM		 2004 if (!(ah->imask & ATH9K_INT_RXEOL)) {
2005 ah->imask |= (ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
72d874c6 2006 ath9k_hw_set_interrupts(ah);
29ab0b36
RM		 2007 }
2008
f078f209 2009 return 0;
f078f209 2010}
Linux kernel - Deliverables
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