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ath9k: make beacon timer initialization more reliable
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / recv.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
b7f080cf 17#include <linux/dma-mapping.h>
394cf0a1 18#include "ath9k.h"
b622a720 19#include "ar9003_mac.h"
f078f209 20
b5c80475
FF		 21#define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb))
22
102885a5
VT		 23static inline bool ath_is_alt_ant_ratio_better(int alt_ratio, int maxdelta,
24 int mindelta, int main_rssi_avg,
25 int alt_rssi_avg, int pkt_count)
26{
27 return (((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
28 (alt_rssi_avg > main_rssi_avg + maxdelta)) ||
29 (alt_rssi_avg > main_rssi_avg + mindelta)) && (pkt_count > 50);
30}
31
b85c5734
MSS		 32static inline bool ath_ant_div_comb_alt_check(u8 div_group, int alt_ratio,
33 int curr_main_set, int curr_alt_set,
34 int alt_rssi_avg, int main_rssi_avg)
35{
36 bool result = false;
37 switch (div_group) {
38 case 0:
39 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
40 result = true;
41 break;
42 case 1:
66ce235a 43 case 2:
b85c5734
MSS		 44 if ((((curr_main_set == ATH_ANT_DIV_COMB_LNA2) &&
45 (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) &&
46 (alt_rssi_avg >= (main_rssi_avg - 5))) ||
47 ((curr_main_set == ATH_ANT_DIV_COMB_LNA1) &&
48 (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) &&
49 (alt_rssi_avg >= (main_rssi_avg - 2)))) &&
50 (alt_rssi_avg >= 4))
51 result = true;
52 else
53 result = false;
54 break;
55 }
56
57 return result;
58}
59
ededf1f8
VT		 60static inline bool ath9k_check_auto_sleep(struct ath_softc *sc)
61{
62 return sc->ps_enabled &&
63 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP);
64}
65
f078f209
LR		 66/*
67 * Setup and link descriptors.
68 *
69 * 11N: we can no longer afford to self link the last descriptor.
70 * MAC acknowledges BA status as long as it copies frames to host
71 * buffer (or rx fifo). This can incorrectly acknowledge packets
72 * to a sender if last desc is self-linked.
f078f209 73 */
f078f209
LR		 74static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
75{
cbe61d8a 76 struct ath_hw *ah = sc->sc_ah;
cc861f74 77 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 78 struct ath_desc *ds;
79 struct sk_buff *skb;
80
81 ATH_RXBUF_RESET(bf);
82
83 ds = bf->bf_desc;
be0418ad 84 ds->ds_link = 0; /* link to null */
f078f209
LR		 85 ds->ds_data = bf->bf_buf_addr;
86
be0418ad 87 /* virtual addr of the beginning of the buffer. */
f078f209 88 skb = bf->bf_mpdu;
9680e8a3 89 BUG_ON(skb == NULL);
f078f209
LR		 90 ds->ds_vdata = skb->data;
91
cc861f74
LR		 92 /*
93 * setup rx descriptors. The rx_bufsize here tells the hardware
b4b6cda2 94 * how much data it can DMA to us and that we are prepared
cc861f74
LR		 95 * to process
96 */
b77f483f 97 ath9k_hw_setuprxdesc(ah, ds,
cc861f74 98 common->rx_bufsize,
f078f209
LR		 99 0);
100
b77f483f 101 if (sc->rx.rxlink == NULL)
f078f209
LR		 102 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
103 else
b77f483f 104 *sc->rx.rxlink = bf->bf_daddr;
f078f209 105
b77f483f 106 sc->rx.rxlink = &ds->ds_link;
f078f209
LR		 107}
108
ff37e337
S		 109static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
110{
111 /* XXX block beacon interrupts */
112 ath9k_hw_setantenna(sc->sc_ah, antenna);
b77f483f
S		 113 sc->rx.defant = antenna;
114 sc->rx.rxotherant = 0;
ff37e337
S		 115}
116
f078f209
LR		 117static void ath_opmode_init(struct ath_softc *sc)
118{
cbe61d8a 119 struct ath_hw *ah = sc->sc_ah;
1510718d
LR		 120 struct ath_common *common = ath9k_hw_common(ah);
121
f078f209
LR		 122 u32 rfilt, mfilt[2];
123
124 /* configure rx filter */
125 rfilt = ath_calcrxfilter(sc);
126 ath9k_hw_setrxfilter(ah, rfilt);
127
128 /* configure bssid mask */
364734fa 129 ath_hw_setbssidmask(common);
f078f209
LR		 130
131 /* configure operational mode */
132 ath9k_hw_setopmode(ah);
133
f078f209
LR		 134 /* calculate and install multicast filter */
135 mfilt[0] = mfilt[1] = ~0;
f078f209 136 ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
f078f209
LR		 137}
138
b5c80475
FF		 139static bool ath_rx_edma_buf_link(struct ath_softc *sc,
140 enum ath9k_rx_qtype qtype)
f078f209 141{
b5c80475
FF		 142 struct ath_hw *ah = sc->sc_ah;
143 struct ath_rx_edma *rx_edma;
f078f209
LR		 144 struct sk_buff *skb;
145 struct ath_buf *bf;
f078f209 146
b5c80475
FF		 147 rx_edma = &sc->rx.rx_edma[qtype];
148 if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize)
149 return false;
f078f209 150
b5c80475
FF		 151 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
152 list_del_init(&bf->list);
f078f209 153
b5c80475
FF		 154 skb = bf->bf_mpdu;
155
156 ATH_RXBUF_RESET(bf);
157 memset(skb->data, 0, ah->caps.rx_status_len);
158 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
159 ah->caps.rx_status_len, DMA_TO_DEVICE);
f078f209 160
b5c80475
FF		 161 SKB_CB_ATHBUF(skb) = bf;
162 ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype);
163 skb_queue_tail(&rx_edma->rx_fifo, skb);
f078f209 164
b5c80475
FF		 165 return true;
166}
167
168static void ath_rx_addbuffer_edma(struct ath_softc *sc,
169 enum ath9k_rx_qtype qtype, int size)
170{
b5c80475
FF		 171 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
172 u32 nbuf = 0;
173
b5c80475 174 if (list_empty(&sc->rx.rxbuf)) {
226afe68 175 ath_dbg(common, ATH_DBG_QUEUE, "No free rx buf available\n");
b5c80475 176 return;
797fe5cb 177 }
f078f209 178
b5c80475
FF		 179 while (!list_empty(&sc->rx.rxbuf)) {
180 nbuf++;
181
182 if (!ath_rx_edma_buf_link(sc, qtype))
183 break;
184
185 if (nbuf >= size)
186 break;
187 }
188}
189
190static void ath_rx_remove_buffer(struct ath_softc *sc,
191 enum ath9k_rx_qtype qtype)
192{
193 struct ath_buf *bf;
194 struct ath_rx_edma *rx_edma;
195 struct sk_buff *skb;
196
197 rx_edma = &sc->rx.rx_edma[qtype];
198
199 while ((skb = skb_dequeue(&rx_edma->rx_fifo)) != NULL) {
200 bf = SKB_CB_ATHBUF(skb);
201 BUG_ON(!bf);
202 list_add_tail(&bf->list, &sc->rx.rxbuf);
203 }
204}
205
206static void ath_rx_edma_cleanup(struct ath_softc *sc)
207{
208 struct ath_buf *bf;
209
210 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
211 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
212
797fe5cb 213 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
b5c80475
FF		 214 if (bf->bf_mpdu)
215 dev_kfree_skb_any(bf->bf_mpdu);
216 }
217
218 INIT_LIST_HEAD(&sc->rx.rxbuf);
219
220 kfree(sc->rx.rx_bufptr);
221 sc->rx.rx_bufptr = NULL;
222}
223
224static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size)
225{
226 skb_queue_head_init(&rx_edma->rx_fifo);
227 skb_queue_head_init(&rx_edma->rx_buffers);
228 rx_edma->rx_fifo_hwsize = size;
229}
230
231static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
232{
233 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
234 struct ath_hw *ah = sc->sc_ah;
235 struct sk_buff *skb;
236 struct ath_buf *bf;
237 int error = 0, i;
238 u32 size;
239
b5c80475
FF		 240 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
241 ah->caps.rx_status_len);
242
243 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP],
244 ah->caps.rx_lp_qdepth);
245 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP],
246 ah->caps.rx_hp_qdepth);
247
248 size = sizeof(struct ath_buf) * nbufs;
249 bf = kzalloc(size, GFP_KERNEL);
250 if (!bf)
251 return -ENOMEM;
252
253 INIT_LIST_HEAD(&sc->rx.rxbuf);
254 sc->rx.rx_bufptr = bf;
255
256 for (i = 0; i < nbufs; i++, bf++) {
cc861f74 257 skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
b5c80475 258 if (!skb) {
797fe5cb 259 error = -ENOMEM;
b5c80475 260 goto rx_init_fail;
f078f209 261 }
f078f209 262
b5c80475 263 memset(skb->data, 0, common->rx_bufsize);
797fe5cb 264 bf->bf_mpdu = skb;
b5c80475 265
797fe5cb 266 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
cc861f74 267 common->rx_bufsize,
b5c80475 268 DMA_BIDIRECTIONAL);
797fe5cb 269 if (unlikely(dma_mapping_error(sc->dev,
b5c80475
FF		 270 bf->bf_buf_addr))) {
271 dev_kfree_skb_any(skb);
272 bf->bf_mpdu = NULL;
6cf9e995 273 bf->bf_buf_addr = 0;
3800276a 274 ath_err(common,
b5c80475
FF		 275 "dma_mapping_error() on RX init\n");
276 error = -ENOMEM;
277 goto rx_init_fail;
278 }
279
280 list_add_tail(&bf->list, &sc->rx.rxbuf);
281 }
282
283 return 0;
284
285rx_init_fail:
286 ath_rx_edma_cleanup(sc);
287 return error;
288}
289
290static void ath_edma_start_recv(struct ath_softc *sc)
291{
292 spin_lock_bh(&sc->rx.rxbuflock);
293
294 ath9k_hw_rxena(sc->sc_ah);
295
296 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP,
297 sc->rx.rx_edma[ATH9K_RX_QUEUE_HP].rx_fifo_hwsize);
298
299 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP,
300 sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize);
301
b5c80475
FF		 302 ath_opmode_init(sc);
303
48a6a468 304 ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
7583c550
LR		 305
306 spin_unlock_bh(&sc->rx.rxbuflock);
b5c80475
FF		 307}
308
309static void ath_edma_stop_recv(struct ath_softc *sc)
310{
b5c80475
FF		 311 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
312 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
b5c80475
FF		 313}
314
315int ath_rx_init(struct ath_softc *sc, int nbufs)
316{
317 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
318 struct sk_buff *skb;
319 struct ath_buf *bf;
320 int error = 0;
321
4bdd1e97 322 spin_lock_init(&sc->sc_pcu_lock);
b5c80475
FF		 323 sc->sc_flags &= ~SC_OP_RXFLUSH;
324 spin_lock_init(&sc->rx.rxbuflock);
325
0d95521e
FF		 326 common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 +
327 sc->sc_ah->caps.rx_status_len;
328
b5c80475
FF		 329 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
330 return ath_rx_edma_init(sc, nbufs);
331 } else {
226afe68
JP		 332 ath_dbg(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
333 common->cachelsz, common->rx_bufsize);
b5c80475
FF		 334
335 /* Initialize rx descriptors */
336
337 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
4adfcded 338 "rx", nbufs, 1, 0);
b5c80475 339 if (error != 0) {
3800276a
JP		 340 ath_err(common,
341 "failed to allocate rx descriptors: %d\n",
342 error);
797fe5cb
S		 343 goto err;
344 }
b5c80475
FF		 345
346 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
347 skb = ath_rxbuf_alloc(common, common->rx_bufsize,
348 GFP_KERNEL);
349 if (skb == NULL) {
350 error = -ENOMEM;
351 goto err;
352 }
353
354 bf->bf_mpdu = skb;
355 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
356 common->rx_bufsize,
357 DMA_FROM_DEVICE);
358 if (unlikely(dma_mapping_error(sc->dev,
359 bf->bf_buf_addr))) {
360 dev_kfree_skb_any(skb);
361 bf->bf_mpdu = NULL;
6cf9e995 362 bf->bf_buf_addr = 0;
3800276a
JP		 363 ath_err(common,
364 "dma_mapping_error() on RX init\n");
b5c80475
FF		 365 error = -ENOMEM;
366 goto err;
367 }
b5c80475
FF		 368 }
369 sc->rx.rxlink = NULL;
797fe5cb 370 }
f078f209 371
797fe5cb 372err:
f078f209
LR		 373 if (error)
374 ath_rx_cleanup(sc);
375
376 return error;
377}
378
f078f209
LR		 379void ath_rx_cleanup(struct ath_softc *sc)
380{
cc861f74
LR		 381 struct ath_hw *ah = sc->sc_ah;
382 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 383 struct sk_buff *skb;
384 struct ath_buf *bf;
385
b5c80475
FF		 386 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
387 ath_rx_edma_cleanup(sc);
388 return;
389 } else {
390 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
391 skb = bf->bf_mpdu;
392 if (skb) {
393 dma_unmap_single(sc->dev, bf->bf_buf_addr,
394 common->rx_bufsize,
395 DMA_FROM_DEVICE);
396 dev_kfree_skb(skb);
6cf9e995
BG		 397 bf->bf_buf_addr = 0;
398 bf->bf_mpdu = NULL;
b5c80475 399 }
051b9191 400 }
f078f209 401
b5c80475
FF		 402 if (sc->rx.rxdma.dd_desc_len != 0)
403 ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
404 }
f078f209
LR		 405}
406
407/*
408 * Calculate the receive filter according to the
409 * operating mode and state:
410 *
411 * o always accept unicast, broadcast, and multicast traffic
412 * o maintain current state of phy error reception (the hal
413 * may enable phy error frames for noise immunity work)
414 * o probe request frames are accepted only when operating in
415 * hostap, adhoc, or monitor modes
416 * o enable promiscuous mode according to the interface state
417 * o accept beacons:
418 * - when operating in adhoc mode so the 802.11 layer creates
419 * node table entries for peers,
420 * - when operating in station mode for collecting rssi data when
421 * the station is otherwise quiet, or
422 * - when operating as a repeater so we see repeater-sta beacons
423 * - when scanning
424 */
425
426u32 ath_calcrxfilter(struct ath_softc *sc)
427{
428#define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR)
7dcfdcd9 429
f078f209
LR		 430 u32 rfilt;
431
432 rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE)
433 | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
434 | ATH9K_RX_FILTER_MCAST;
435
9c1d8e4a 436 if (sc->rx.rxfilter & FIF_PROBE_REQ)
f078f209
LR		 437 rfilt |= ATH9K_RX_FILTER_PROBEREQ;
438
217ba9da
JM		 439 /*
440 * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station
441 * mode interface or when in monitor mode. AP mode does not need this
442 * since it receives all in-BSS frames anyway.
443 */
2e286947 444 if (sc->sc_ah->is_monitoring)
f078f209 445 rfilt |= ATH9K_RX_FILTER_PROM;
f078f209 446
d42c6b71
S		 447 if (sc->rx.rxfilter & FIF_CONTROL)
448 rfilt |= ATH9K_RX_FILTER_CONTROL;
449
dbaaa147 450 if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
cfda6695 451 (sc->nvifs <= 1) &&
dbaaa147
VT		 452 !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC))
453 rfilt |= ATH9K_RX_FILTER_MYBEACON;
454 else
f078f209
LR		 455 rfilt |= ATH9K_RX_FILTER_BEACON;
456
264bbec8 457 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
66afad01 458 (sc->rx.rxfilter & FIF_PSPOLL))
dbaaa147 459 rfilt |= ATH9K_RX_FILTER_PSPOLL;
be0418ad 460
7ea310be
S		 461 if (conf_is_ht(&sc->hw->conf))
462 rfilt |= ATH9K_RX_FILTER_COMP_BAR;
463
7545daf4 464 if (sc->nvifs > 1 || (sc->rx.rxfilter & FIF_OTHER_BSS)) {
5eb6ba83
JC		 465 /* The following may also be needed for other older chips */
466 if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160)
467 rfilt |= ATH9K_RX_FILTER_PROM;
b93bce2a
JM		 468 rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
469 }
470
f078f209 471 return rfilt;
7dcfdcd9 472
f078f209
LR		 473#undef RX_FILTER_PRESERVE
474}
475
f078f209
LR		 476int ath_startrecv(struct ath_softc *sc)
477{
cbe61d8a 478 struct ath_hw *ah = sc->sc_ah;
f078f209
LR		 479 struct ath_buf *bf, *tbf;
480
b5c80475
FF		 481 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
482 ath_edma_start_recv(sc);
483 return 0;
484 }
485
b77f483f
S		 486 spin_lock_bh(&sc->rx.rxbuflock);
487 if (list_empty(&sc->rx.rxbuf))
f078f209
LR		 488 goto start_recv;
489
b77f483f
S		 490 sc->rx.rxlink = NULL;
491 list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
f078f209
LR		 492 ath_rx_buf_link(sc, bf);
493 }
494
495 /* We could have deleted elements so the list may be empty now */
b77f483f 496 if (list_empty(&sc->rx.rxbuf))
f078f209
LR		 497 goto start_recv;
498
b77f483f 499 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
f078f209 500 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
be0418ad 501 ath9k_hw_rxena(ah);
f078f209
LR		 502
503start_recv:
be0418ad 504 ath_opmode_init(sc);
48a6a468 505 ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
be0418ad 506
7583c550
LR		 507 spin_unlock_bh(&sc->rx.rxbuflock);
508
f078f209
LR		 509 return 0;
510}
511
f078f209
LR		 512bool ath_stoprecv(struct ath_softc *sc)
513{
cbe61d8a 514 struct ath_hw *ah = sc->sc_ah;
5882da02 515 bool stopped, reset = false;
f078f209 516
1e450285 517 spin_lock_bh(&sc->rx.rxbuflock);
d47844a0 518 ath9k_hw_abortpcurecv(ah);
be0418ad 519 ath9k_hw_setrxfilter(ah, 0);
5882da02 520 stopped = ath9k_hw_stopdmarecv(ah, &reset);
b5c80475
FF		 521
522 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
523 ath_edma_stop_recv(sc);
524 else
525 sc->rx.rxlink = NULL;
1e450285 526 spin_unlock_bh(&sc->rx.rxbuflock);
be0418ad 527
d584747b
RM		 528 if (!(ah->ah_flags & AH_UNPLUGGED) &&
529 unlikely(!stopped)) {
d7fd1b50
BG		 530 ath_err(ath9k_hw_common(sc->sc_ah),
531 "Could not stop RX, we could be "
532 "confusing the DMA engine when we start RX up\n");
533 ATH_DBG_WARN_ON_ONCE(!stopped);
534 }
2232d31b 535 return stopped && !reset;
f078f209
LR		 536}
537
f078f209
LR		 538void ath_flushrecv(struct ath_softc *sc)
539{
98deeea0 540 sc->sc_flags |= SC_OP_RXFLUSH;
b5c80475
FF		 541 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
542 ath_rx_tasklet(sc, 1, true);
543 ath_rx_tasklet(sc, 1, false);
98deeea0 544 sc->sc_flags &= ~SC_OP_RXFLUSH;
f078f209
LR		 545}
546
cc65965c
JM		 547static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
548{
549 /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
550 struct ieee80211_mgmt *mgmt;
551 u8 *pos, *end, id, elen;
552 struct ieee80211_tim_ie *tim;
553
554 mgmt = (struct ieee80211_mgmt *)skb->data;
555 pos = mgmt->u.beacon.variable;
556 end = skb->data + skb->len;
557
558 while (pos + 2 < end) {
559 id = *pos++;
560 elen = *pos++;
561 if (pos + elen > end)
562 break;
563
564 if (id == WLAN_EID_TIM) {
565 if (elen < sizeof(*tim))
566 break;
567 tim = (struct ieee80211_tim_ie *) pos;
568 if (tim->dtim_count != 0)
569 break;
570 return tim->bitmap_ctrl & 0x01;
571 }
572
573 pos += elen;
574 }
575
576 return false;
577}
578
cc65965c
JM		 579static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
580{
581 struct ieee80211_mgmt *mgmt;
1510718d 582 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
cc65965c
JM		 583
584 if (skb->len < 24 + 8 + 2 + 2)
585 return;
586
587 mgmt = (struct ieee80211_mgmt *)skb->data;
4801416c
BG		 588 if (memcmp(common->curbssid, mgmt->bssid, ETH_ALEN) != 0) {
589 /* TODO: This doesn't work well if you have stations
590 * associated to two different APs because curbssid
591 * is just the last AP that any of the stations associated
592 * with.
593 */
cc65965c 594 return; /* not from our current AP */
4801416c 595 }
cc65965c 596
1b04b930 597 sc->ps_flags &= ~PS_WAIT_FOR_BEACON;
293dc5df 598
1b04b930
S		 599 if (sc->ps_flags & PS_BEACON_SYNC) {
600 sc->ps_flags &= ~PS_BEACON_SYNC;
226afe68
JP		 601 ath_dbg(common, ATH_DBG_PS,
602 "Reconfigure Beacon timers based on timestamp from the AP\n");
99e4d43a 603 ath_set_beacon(sc);
ccdfeab6
JM		 604 }
605
cc65965c
JM		 606 if (ath_beacon_dtim_pending_cab(skb)) {
607 /*
608 * Remain awake waiting for buffered broadcast/multicast
58f5fffd
GJ		 609 * frames. If the last broadcast/multicast frame is not
610 * received properly, the next beacon frame will work as
611 * a backup trigger for returning into NETWORK SLEEP state,
612 * so we are waiting for it as well.
cc65965c 613 */
226afe68
JP		 614 ath_dbg(common, ATH_DBG_PS,
615 "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n");
1b04b930 616 sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
cc65965c
JM		 617 return;
618 }
619
1b04b930 620 if (sc->ps_flags & PS_WAIT_FOR_CAB) {
cc65965c
JM		 621 /*
622 * This can happen if a broadcast frame is dropped or the AP
623 * fails to send a frame indicating that all CAB frames have
624 * been delivered.
625 */
1b04b930 626 sc->ps_flags &= ~PS_WAIT_FOR_CAB;
226afe68
JP		 627 ath_dbg(common, ATH_DBG_PS,
628 "PS wait for CAB frames timed out\n");
cc65965c 629 }
cc65965c
JM		 630}
631
632static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
633{
634 struct ieee80211_hdr *hdr;
c46917bb 635 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
cc65965c
JM		 636
637 hdr = (struct ieee80211_hdr *)skb->data;
638
639 /* Process Beacon and CAB receive in PS state */
ededf1f8
VT		 640 if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc))
641 && ieee80211_is_beacon(hdr->frame_control))
cc65965c 642 ath_rx_ps_beacon(sc, skb);
1b04b930 643 else if ((sc->ps_flags & PS_WAIT_FOR_CAB) &&
cc65965c
JM		 644 (ieee80211_is_data(hdr->frame_control) ||
645 ieee80211_is_action(hdr->frame_control)) &&
646 is_multicast_ether_addr(hdr->addr1) &&
647 !ieee80211_has_moredata(hdr->frame_control)) {
cc65965c
JM		 648 /*
649 * No more broadcast/multicast frames to be received at this
650 * point.
651 */
3fac6dfd 652 sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON);
226afe68
JP		 653 ath_dbg(common, ATH_DBG_PS,
654 "All PS CAB frames received, back to sleep\n");
1b04b930 655 } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
9a23f9ca
JM		 656 !is_multicast_ether_addr(hdr->addr1) &&
657 !ieee80211_has_morefrags(hdr->frame_control)) {
1b04b930 658 sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
226afe68
JP		 659 ath_dbg(common, ATH_DBG_PS,
660 "Going back to sleep after having received PS-Poll data (0x%lx)\n",
1b04b930
S		 661 sc->ps_flags & (PS_WAIT_FOR_BEACON |
662 PS_WAIT_FOR_CAB |
663 PS_WAIT_FOR_PSPOLL_DATA |
664 PS_WAIT_FOR_TX_ACK));
cc65965c
JM		 665 }
666}
667
b5c80475
FF		 668static bool ath_edma_get_buffers(struct ath_softc *sc,
669 enum ath9k_rx_qtype qtype)
f078f209 670{
b5c80475
FF		 671 struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
672 struct ath_hw *ah = sc->sc_ah;
673 struct ath_common *common = ath9k_hw_common(ah);
674 struct sk_buff *skb;
675 struct ath_buf *bf;
676 int ret;
677
678 skb = skb_peek(&rx_edma->rx_fifo);
679 if (!skb)
680 return false;
681
682 bf = SKB_CB_ATHBUF(skb);
683 BUG_ON(!bf);
684
ce9426d1 685 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
b5c80475
FF		 686 common->rx_bufsize, DMA_FROM_DEVICE);
687
688 ret = ath9k_hw_process_rxdesc_edma(ah, NULL, skb->data);
ce9426d1
ML		 689 if (ret == -EINPROGRESS) {
690 /*let device gain the buffer again*/
691 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
692 common->rx_bufsize, DMA_FROM_DEVICE);
b5c80475 693 return false;
ce9426d1 694 }
b5c80475
FF		 695
696 __skb_unlink(skb, &rx_edma->rx_fifo);
697 if (ret == -EINVAL) {
698 /* corrupt descriptor, skip this one and the following one */
699 list_add_tail(&bf->list, &sc->rx.rxbuf);
700 ath_rx_edma_buf_link(sc, qtype);
701 skb = skb_peek(&rx_edma->rx_fifo);
702 if (!skb)
703 return true;
704
705 bf = SKB_CB_ATHBUF(skb);
706 BUG_ON(!bf);
707
708 __skb_unlink(skb, &rx_edma->rx_fifo);
709 list_add_tail(&bf->list, &sc->rx.rxbuf);
710 ath_rx_edma_buf_link(sc, qtype);
083e3e8d 711 return true;
b5c80475
FF		 712 }
713 skb_queue_tail(&rx_edma->rx_buffers, skb);
714
715 return true;
716}
f078f209 717
b5c80475
FF		 718static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc,
719 struct ath_rx_status *rs,
720 enum ath9k_rx_qtype qtype)
721{
722 struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
723 struct sk_buff *skb;
be0418ad 724 struct ath_buf *bf;
b5c80475
FF		 725
726 while (ath_edma_get_buffers(sc, qtype));
727 skb = __skb_dequeue(&rx_edma->rx_buffers);
728 if (!skb)
729 return NULL;
730
731 bf = SKB_CB_ATHBUF(skb);
732 ath9k_hw_process_rxdesc_edma(sc->sc_ah, rs, skb->data);
733 return bf;
734}
735
736static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc,
737 struct ath_rx_status *rs)
738{
739 struct ath_hw *ah = sc->sc_ah;
740 struct ath_common *common = ath9k_hw_common(ah);
f078f209 741 struct ath_desc *ds;
b5c80475
FF		 742 struct ath_buf *bf;
743 int ret;
744
745 if (list_empty(&sc->rx.rxbuf)) {
746 sc->rx.rxlink = NULL;
747 return NULL;
748 }
749
750 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
751 ds = bf->bf_desc;
752
753 /*
754 * Must provide the virtual address of the current
755 * descriptor, the physical address, and the virtual
756 * address of the next descriptor in the h/w chain.
757 * This allows the HAL to look ahead to see if the
758 * hardware is done with a descriptor by checking the
759 * done bit in the following descriptor and the address
760 * of the current descriptor the DMA engine is working
761 * on. All this is necessary because of our use of
762 * a self-linked list to avoid rx overruns.
763 */
3de21116 764 ret = ath9k_hw_rxprocdesc(ah, ds, rs);
b5c80475
FF		 765 if (ret == -EINPROGRESS) {
766 struct ath_rx_status trs;
767 struct ath_buf *tbf;
768 struct ath_desc *tds;
769
770 memset(&trs, 0, sizeof(trs));
771 if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
772 sc->rx.rxlink = NULL;
773 return NULL;
774 }
775
776 tbf = list_entry(bf->list.next, struct ath_buf, list);
777
778 /*
779 * On some hardware the descriptor status words could
780 * get corrupted, including the done bit. Because of
781 * this, check if the next descriptor's done bit is
782 * set or not.
783 *
784 * If the next descriptor's done bit is set, the current
785 * descriptor has been corrupted. Force s/w to discard
786 * this descriptor and continue...
787 */
788
789 tds = tbf->bf_desc;
3de21116 790 ret = ath9k_hw_rxprocdesc(ah, tds, &trs);
b5c80475
FF		 791 if (ret == -EINPROGRESS)
792 return NULL;
793 }
794
795 if (!bf->bf_mpdu)
796 return bf;
797
798 /*
799 * Synchronize the DMA transfer with CPU before
800 * 1. accessing the frame
801 * 2. requeueing the same buffer to h/w
802 */
ce9426d1 803 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
b5c80475
FF		 804 common->rx_bufsize,
805 DMA_FROM_DEVICE);
806
807 return bf;
808}
809
d435700f
S		 810/* Assumes you've already done the endian to CPU conversion */
811static bool ath9k_rx_accept(struct ath_common *common,
9f167f64 812 struct ieee80211_hdr *hdr,
d435700f
S		 813 struct ieee80211_rx_status *rxs,
814 struct ath_rx_status *rx_stats,
815 bool *decrypt_error)
816{
66760eac 817 bool is_mc, is_valid_tkip, strip_mic, mic_error;
d435700f 818 struct ath_hw *ah = common->ah;
d435700f 819 __le16 fc;
b7b1b512 820 u8 rx_status_len = ah->caps.rx_status_len;
d435700f 821
d435700f
S		 822 fc = hdr->frame_control;
823
66760eac
FF		 824 is_mc = !!is_multicast_ether_addr(hdr->addr1);
825 is_valid_tkip = rx_stats->rs_keyix != ATH9K_RXKEYIX_INVALID &&
826 test_bit(rx_stats->rs_keyix, common->tkip_keymap);
152e585d
BJ		 827 strip_mic = is_valid_tkip && ieee80211_is_data(fc) &&
828 !(rx_stats->rs_status &
66760eac
FF		 829 (ATH9K_RXERR_DECRYPT | ATH9K_RXERR_CRC | ATH9K_RXERR_MIC));
830
d435700f
S		 831 if (!rx_stats->rs_datalen)
832 return false;
833 /*
834 * rs_status follows rs_datalen so if rs_datalen is too large
835 * we can take a hint that hardware corrupted it, so ignore
836 * those frames.
837 */
b7b1b512 838 if (rx_stats->rs_datalen > (common->rx_bufsize - rx_status_len))
d435700f
S		 839 return false;
840
0d95521e 841 /* Only use error bits from the last fragment */
d435700f 842 if (rx_stats->rs_more)
0d95521e 843 return true;
d435700f 844
66760eac
FF		 845 mic_error = is_valid_tkip && !ieee80211_is_ctl(fc) &&
846 !ieee80211_has_morefrags(fc) &&
847 !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) &&
848 (rx_stats->rs_status & ATH9K_RXERR_MIC);
849
d435700f
S		 850 /*
851 * The rx_stats->rs_status will not be set until the end of the
852 * chained descriptors so it can be ignored if rs_more is set. The
853 * rs_more will be false at the last element of the chained
854 * descriptors.
855 */
856 if (rx_stats->rs_status != 0) {
66760eac 857 if (rx_stats->rs_status & ATH9K_RXERR_CRC) {
d435700f 858 rxs->flag |= RX_FLAG_FAILED_FCS_CRC;
66760eac
FF		 859 mic_error = false;
860 }
d435700f
S		 861 if (rx_stats->rs_status & ATH9K_RXERR_PHY)
862 return false;
863
864 if (rx_stats->rs_status & ATH9K_RXERR_DECRYPT) {
865 *decrypt_error = true;
66760eac 866 mic_error = false;
d435700f 867 }
66760eac 868
d435700f
S		 869 /*
870 * Reject error frames with the exception of
871 * decryption and MIC failures. For monitor mode,
872 * we also ignore the CRC error.
873 */
5f841b41 874 if (ah->is_monitoring) {
d435700f
S		 875 if (rx_stats->rs_status &
876 ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
877 ATH9K_RXERR_CRC))
878 return false;
879 } else {
880 if (rx_stats->rs_status &
881 ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) {
882 return false;
883 }
884 }
885 }
66760eac
FF		 886
887 /*
888 * For unicast frames the MIC error bit can have false positives,
889 * so all MIC error reports need to be validated in software.
890 * False negatives are not common, so skip software verification
891 * if the hardware considers the MIC valid.
892 */
893 if (strip_mic)
894 rxs->flag |= RX_FLAG_MMIC_STRIPPED;
895 else if (is_mc && mic_error)
896 rxs->flag |= RX_FLAG_MMIC_ERROR;
897
d435700f
S		 898 return true;
899}
900
901static int ath9k_process_rate(struct ath_common *common,
902 struct ieee80211_hw *hw,
903 struct ath_rx_status *rx_stats,
9f167f64 904 struct ieee80211_rx_status *rxs)
d435700f
S		 905{
906 struct ieee80211_supported_band *sband;
907 enum ieee80211_band band;
908 unsigned int i = 0;
909
910 band = hw->conf.channel->band;
911 sband = hw->wiphy->bands[band];
912
913 if (rx_stats->rs_rate & 0x80) {
914 /* HT rate */
915 rxs->flag |= RX_FLAG_HT;
916 if (rx_stats->rs_flags & ATH9K_RX_2040)
917 rxs->flag |= RX_FLAG_40MHZ;
918 if (rx_stats->rs_flags & ATH9K_RX_GI)
919 rxs->flag |= RX_FLAG_SHORT_GI;
920 rxs->rate_idx = rx_stats->rs_rate & 0x7f;
921 return 0;
922 }
923
924 for (i = 0; i < sband->n_bitrates; i++) {
925 if (sband->bitrates[i].hw_value == rx_stats->rs_rate) {
926 rxs->rate_idx = i;
927 return 0;
928 }
929 if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) {
930 rxs->flag |= RX_FLAG_SHORTPRE;
931 rxs->rate_idx = i;
932 return 0;
933 }
934 }
935
936 /*
937 * No valid hardware bitrate found -- we should not get here
938 * because hardware has already validated this frame as OK.
939 */
9976f62e 940 ath_dbg(common, ATH_DBG_ANY,
226afe68
JP		 941 "unsupported hw bitrate detected 0x%02x using 1 Mbit\n",
942 rx_stats->rs_rate);
d435700f
S		 943
944 return -EINVAL;
945}
946
947static void ath9k_process_rssi(struct ath_common *common,
948 struct ieee80211_hw *hw,
9f167f64 949 struct ieee80211_hdr *hdr,
d435700f
S		 950 struct ath_rx_status *rx_stats)
951{
9ac58615 952 struct ath_softc *sc = hw->priv;
d435700f 953 struct ath_hw *ah = common->ah;
9fa23e17 954 int last_rssi;
d435700f 955
cf3af748
RM		 956 if (!rx_stats->is_mybeacon ||
957 ((ah->opmode != NL80211_IFTYPE_STATION) &&
958 (ah->opmode != NL80211_IFTYPE_ADHOC)))
9fa23e17
FF		 959 return;
960
9fa23e17 961 if (rx_stats->rs_rssi != ATH9K_RSSI_BAD && !rx_stats->rs_moreaggr)
9ac58615 962 ATH_RSSI_LPF(sc->last_rssi, rx_stats->rs_rssi);
d435700f 963
9ac58615 964 last_rssi = sc->last_rssi;
d435700f
S		 965 if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
966 rx_stats->rs_rssi = ATH_EP_RND(last_rssi,
967 ATH_RSSI_EP_MULTIPLIER);
968 if (rx_stats->rs_rssi < 0)
969 rx_stats->rs_rssi = 0;
970
971 /* Update Beacon RSSI, this is used by ANI. */
9fa23e17 972 ah->stats.avgbrssi = rx_stats->rs_rssi;
d435700f
S		 973}
974
975/*
976 * For Decrypt or Demic errors, we only mark packet status here and always push
977 * up the frame up to let mac80211 handle the actual error case, be it no
978 * decryption key or real decryption error. This let us keep statistics there.
979 */
980static int ath9k_rx_skb_preprocess(struct ath_common *common,
981 struct ieee80211_hw *hw,
9f167f64 982 struct ieee80211_hdr *hdr,
d435700f
S		 983 struct ath_rx_status *rx_stats,
984 struct ieee80211_rx_status *rx_status,
985 bool *decrypt_error)
986{
f749b946
FF		 987 struct ath_hw *ah = common->ah;
988
d435700f
S		 989 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
990
991 /*
992 * everything but the rate is checked here, the rate check is done
993 * separately to avoid doing two lookups for a rate for each frame.
994 */
9f167f64 995 if (!ath9k_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error))
d435700f
S		 996 return -EINVAL;
997
0d95521e
FF		 998 /* Only use status info from the last fragment */
999 if (rx_stats->rs_more)
1000 return 0;
1001
9f167f64 1002 ath9k_process_rssi(common, hw, hdr, rx_stats);
d435700f 1003
9f167f64 1004 if (ath9k_process_rate(common, hw, rx_stats, rx_status))
d435700f
S		 1005 return -EINVAL;
1006
d435700f
S		 1007 rx_status->band = hw->conf.channel->band;
1008 rx_status->freq = hw->conf.channel->center_freq;
f749b946 1009 rx_status->signal = ah->noise + rx_stats->rs_rssi;
d435700f 1010 rx_status->antenna = rx_stats->rs_antenna;
6ebacbb7 1011 rx_status->flag |= RX_FLAG_MACTIME_MPDU;
d435700f
S		 1012
1013 return 0;
1014}
1015
1016static void ath9k_rx_skb_postprocess(struct ath_common *common,
1017 struct sk_buff *skb,
1018 struct ath_rx_status *rx_stats,
1019 struct ieee80211_rx_status *rxs,
1020 bool decrypt_error)
1021{
1022 struct ath_hw *ah = common->ah;
1023 struct ieee80211_hdr *hdr;
1024 int hdrlen, padpos, padsize;
1025 u8 keyix;
1026 __le16 fc;
1027
1028 /* see if any padding is done by the hw and remove it */
1029 hdr = (struct ieee80211_hdr *) skb->data;
1030 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1031 fc = hdr->frame_control;
1032 padpos = ath9k_cmn_padpos(hdr->frame_control);
1033
1034 /* The MAC header is padded to have 32-bit boundary if the
1035 * packet payload is non-zero. The general calculation for
1036 * padsize would take into account odd header lengths:
1037 * padsize = (4 - padpos % 4) % 4; However, since only
1038 * even-length headers are used, padding can only be 0 or 2
1039 * bytes and we can optimize this a bit. In addition, we must
1040 * not try to remove padding from short control frames that do
1041 * not have payload. */
1042 padsize = padpos & 3;
1043 if (padsize && skb->len>=padpos+padsize+FCS_LEN) {
1044 memmove(skb->data + padsize, skb->data, padpos);
1045 skb_pull(skb, padsize);
1046 }
1047
1048 keyix = rx_stats->rs_keyix;
1049
1050 if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error &&
1051 ieee80211_has_protected(fc)) {
1052 rxs->flag |= RX_FLAG_DECRYPTED;
1053 } else if (ieee80211_has_protected(fc)
1054 && !decrypt_error && skb->len >= hdrlen + 4) {
1055 keyix = skb->data[hdrlen + 3] >> 6;
1056
1057 if (test_bit(keyix, common->keymap))
1058 rxs->flag |= RX_FLAG_DECRYPTED;
1059 }
1060 if (ah->sw_mgmt_crypto &&
1061 (rxs->flag & RX_FLAG_DECRYPTED) &&
1062 ieee80211_is_mgmt(fc))
1063 /* Use software decrypt for management frames. */
1064 rxs->flag &= ~RX_FLAG_DECRYPTED;
1065}
b5c80475 1066
102885a5
VT		 1067static void ath_lnaconf_alt_good_scan(struct ath_ant_comb *antcomb,
1068 struct ath_hw_antcomb_conf ant_conf,
1069 int main_rssi_avg)
1070{
1071 antcomb->quick_scan_cnt = 0;
1072
1073 if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA2)
1074 antcomb->rssi_lna2 = main_rssi_avg;
1075 else if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA1)
1076 antcomb->rssi_lna1 = main_rssi_avg;
1077
1078 switch ((ant_conf.main_lna_conf << 4) | ant_conf.alt_lna_conf) {
223c5a87 1079 case 0x10: /* LNA2 A-B */
102885a5
VT		 1080 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1081 antcomb->first_quick_scan_conf =
1082 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1083 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1084 break;
223c5a87 1085 case 0x20: /* LNA1 A-B */
102885a5
VT		 1086 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1087 antcomb->first_quick_scan_conf =
1088 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1089 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
1090 break;
223c5a87 1091 case 0x21: /* LNA1 LNA2 */
102885a5
VT		 1092 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA2;
1093 antcomb->first_quick_scan_conf =
1094 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1095 antcomb->second_quick_scan_conf =
1096 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1097 break;
223c5a87 1098 case 0x12: /* LNA2 LNA1 */
102885a5
VT		 1099 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1;
1100 antcomb->first_quick_scan_conf =
1101 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1102 antcomb->second_quick_scan_conf =
1103 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1104 break;
223c5a87 1105 case 0x13: /* LNA2 A+B */
102885a5
VT		 1106 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1107 antcomb->first_quick_scan_conf =
1108 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1109 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1110 break;
223c5a87 1111 case 0x23: /* LNA1 A+B */
102885a5
VT		 1112 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1113 antcomb->first_quick_scan_conf =
1114 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1115 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
1116 break;
1117 default:
1118 break;
1119 }
1120}
1121
1122static void ath_select_ant_div_from_quick_scan(struct ath_ant_comb *antcomb,
1123 struct ath_hw_antcomb_conf *div_ant_conf,
1124 int main_rssi_avg, int alt_rssi_avg,
1125 int alt_ratio)
1126{
1127 /* alt_good */
1128 switch (antcomb->quick_scan_cnt) {
1129 case 0:
1130 /* set alt to main, and alt to first conf */
1131 div_ant_conf->main_lna_conf = antcomb->main_conf;
1132 div_ant_conf->alt_lna_conf = antcomb->first_quick_scan_conf;
1133 break;
1134 case 1:
1135 /* set alt to main, and alt to first conf */
1136 div_ant_conf->main_lna_conf = antcomb->main_conf;
1137 div_ant_conf->alt_lna_conf = antcomb->second_quick_scan_conf;
1138 antcomb->rssi_first = main_rssi_avg;
1139 antcomb->rssi_second = alt_rssi_avg;
1140
1141 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
1142 /* main is LNA1 */
1143 if (ath_is_alt_ant_ratio_better(alt_ratio,
1144 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
1145 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1146 main_rssi_avg, alt_rssi_avg,
1147 antcomb->total_pkt_count))
1148 antcomb->first_ratio = true;
1149 else
1150 antcomb->first_ratio = false;
1151 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
1152 if (ath_is_alt_ant_ratio_better(alt_ratio,
1153 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
1154 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1155 main_rssi_avg, alt_rssi_avg,
1156 antcomb->total_pkt_count))
1157 antcomb->first_ratio = true;
1158 else
1159 antcomb->first_ratio = false;
1160 } else {
1161 if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
1162 (alt_rssi_avg > main_rssi_avg +
1163 ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
1164 (alt_rssi_avg > main_rssi_avg)) &&
1165 (antcomb->total_pkt_count > 50))
1166 antcomb->first_ratio = true;
1167 else
1168 antcomb->first_ratio = false;
1169 }
1170 break;
1171 case 2:
1172 antcomb->alt_good = false;
1173 antcomb->scan_not_start = false;
1174 antcomb->scan = false;
1175 antcomb->rssi_first = main_rssi_avg;
1176 antcomb->rssi_third = alt_rssi_avg;
1177
1178 if (antcomb->second_quick_scan_conf == ATH_ANT_DIV_COMB_LNA1)
1179 antcomb->rssi_lna1 = alt_rssi_avg;
1180 else if (antcomb->second_quick_scan_conf ==
1181 ATH_ANT_DIV_COMB_LNA2)
1182 antcomb->rssi_lna2 = alt_rssi_avg;
1183 else if (antcomb->second_quick_scan_conf ==
1184 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2) {
1185 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2)
1186 antcomb->rssi_lna2 = main_rssi_avg;
1187 else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1)
1188 antcomb->rssi_lna1 = main_rssi_avg;
1189 }
1190
1191 if (antcomb->rssi_lna2 > antcomb->rssi_lna1 +
1192 ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)
1193 div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
1194 else
1195 div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA1;
1196
1197 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
1198 if (ath_is_alt_ant_ratio_better(alt_ratio,
1199 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
1200 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1201 main_rssi_avg, alt_rssi_avg,
1202 antcomb->total_pkt_count))
1203 antcomb->second_ratio = true;
1204 else
1205 antcomb->second_ratio = false;
1206 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
1207 if (ath_is_alt_ant_ratio_better(alt_ratio,
1208 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
1209 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1210 main_rssi_avg, alt_rssi_avg,
1211 antcomb->total_pkt_count))
1212 antcomb->second_ratio = true;
1213 else
1214 antcomb->second_ratio = false;
1215 } else {
1216 if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
1217 (alt_rssi_avg > main_rssi_avg +
1218 ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
1219 (alt_rssi_avg > main_rssi_avg)) &&
1220 (antcomb->total_pkt_count > 50))
1221 antcomb->second_ratio = true;
1222 else
1223 antcomb->second_ratio = false;
1224 }
1225
1226 /* set alt to the conf with maximun ratio */
1227 if (antcomb->first_ratio && antcomb->second_ratio) {
1228 if (antcomb->rssi_second > antcomb->rssi_third) {
1229 /* first alt*/
1230 if ((antcomb->first_quick_scan_conf ==
1231 ATH_ANT_DIV_COMB_LNA1) ||
1232 (antcomb->first_quick_scan_conf ==
1233 ATH_ANT_DIV_COMB_LNA2))
1234 /* Set alt LNA1 or LNA2*/
1235 if (div_ant_conf->main_lna_conf ==
1236 ATH_ANT_DIV_COMB_LNA2)
1237 div_ant_conf->alt_lna_conf =
1238 ATH_ANT_DIV_COMB_LNA1;
1239 else
1240 div_ant_conf->alt_lna_conf =
1241 ATH_ANT_DIV_COMB_LNA2;
1242 else
1243 /* Set alt to A+B or A-B */
1244 div_ant_conf->alt_lna_conf =
1245 antcomb->first_quick_scan_conf;
1246 } else if ((antcomb->second_quick_scan_conf ==
1247 ATH_ANT_DIV_COMB_LNA1) ||
1248 (antcomb->second_quick_scan_conf ==
1249 ATH_ANT_DIV_COMB_LNA2)) {
1250 /* Set alt LNA1 or LNA2 */
1251 if (div_ant_conf->main_lna_conf ==
1252 ATH_ANT_DIV_COMB_LNA2)
1253 div_ant_conf->alt_lna_conf =
1254 ATH_ANT_DIV_COMB_LNA1;
1255 else
1256 div_ant_conf->alt_lna_conf =
1257 ATH_ANT_DIV_COMB_LNA2;
1258 } else {
1259 /* Set alt to A+B or A-B */
1260 div_ant_conf->alt_lna_conf =
1261 antcomb->second_quick_scan_conf;
1262 }
1263 } else if (antcomb->first_ratio) {
1264 /* first alt */
1265 if ((antcomb->first_quick_scan_conf ==
1266 ATH_ANT_DIV_COMB_LNA1) ||
1267 (antcomb->first_quick_scan_conf ==
1268 ATH_ANT_DIV_COMB_LNA2))
1269 /* Set alt LNA1 or LNA2 */
1270 if (div_ant_conf->main_lna_conf ==
1271 ATH_ANT_DIV_COMB_LNA2)
1272 div_ant_conf->alt_lna_conf =
1273 ATH_ANT_DIV_COMB_LNA1;
1274 else
1275 div_ant_conf->alt_lna_conf =
1276 ATH_ANT_DIV_COMB_LNA2;
1277 else
1278 /* Set alt to A+B or A-B */
1279 div_ant_conf->alt_lna_conf =
1280 antcomb->first_quick_scan_conf;
1281 } else if (antcomb->second_ratio) {
1282 /* second alt */
1283 if ((antcomb->second_quick_scan_conf ==
1284 ATH_ANT_DIV_COMB_LNA1) ||
1285 (antcomb->second_quick_scan_conf ==
1286 ATH_ANT_DIV_COMB_LNA2))
1287 /* Set alt LNA1 or LNA2 */
1288 if (div_ant_conf->main_lna_conf ==
1289 ATH_ANT_DIV_COMB_LNA2)
1290 div_ant_conf->alt_lna_conf =
1291 ATH_ANT_DIV_COMB_LNA1;
1292 else
1293 div_ant_conf->alt_lna_conf =
1294 ATH_ANT_DIV_COMB_LNA2;
1295 else
1296 /* Set alt to A+B or A-B */
1297 div_ant_conf->alt_lna_conf =
1298 antcomb->second_quick_scan_conf;
1299 } else {
1300 /* main is largest */
1301 if ((antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) ||
1302 (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2))
1303 /* Set alt LNA1 or LNA2 */
1304 if (div_ant_conf->main_lna_conf ==
1305 ATH_ANT_DIV_COMB_LNA2)
1306 div_ant_conf->alt_lna_conf =
1307 ATH_ANT_DIV_COMB_LNA1;
1308 else
1309 div_ant_conf->alt_lna_conf =
1310 ATH_ANT_DIV_COMB_LNA2;
1311 else
1312 /* Set alt to A+B or A-B */
1313 div_ant_conf->alt_lna_conf = antcomb->main_conf;
1314 }
1315 break;
1316 default:
1317 break;
1318 }
1319}
1320
3e9a212a
MSS		 1321static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf,
1322 struct ath_ant_comb *antcomb, int alt_ratio)
102885a5 1323{
3e9a212a
MSS		 1324 if (ant_conf->div_group == 0) {
1325 /* Adjust the fast_div_bias based on main and alt lna conf */
1326 switch ((ant_conf->main_lna_conf << 4) |
1327 ant_conf->alt_lna_conf) {
223c5a87 1328 case 0x01: /* A-B LNA2 */
3e9a212a
MSS		 1329 ant_conf->fast_div_bias = 0x3b;
1330 break;
223c5a87 1331 case 0x02: /* A-B LNA1 */
3e9a212a
MSS		 1332 ant_conf->fast_div_bias = 0x3d;
1333 break;
223c5a87 1334 case 0x03: /* A-B A+B */
3e9a212a
MSS		 1335 ant_conf->fast_div_bias = 0x1;
1336 break;
223c5a87 1337 case 0x10: /* LNA2 A-B */
3e9a212a
MSS		 1338 ant_conf->fast_div_bias = 0x7;
1339 break;
223c5a87 1340 case 0x12: /* LNA2 LNA1 */
3e9a212a
MSS		 1341 ant_conf->fast_div_bias = 0x2;
1342 break;
223c5a87 1343 case 0x13: /* LNA2 A+B */
3e9a212a
MSS		 1344 ant_conf->fast_div_bias = 0x7;
1345 break;
223c5a87 1346 case 0x20: /* LNA1 A-B */
3e9a212a
MSS		 1347 ant_conf->fast_div_bias = 0x6;
1348 break;
223c5a87 1349 case 0x21: /* LNA1 LNA2 */
3e9a212a
MSS		 1350 ant_conf->fast_div_bias = 0x0;
1351 break;
223c5a87 1352 case 0x23: /* LNA1 A+B */
3e9a212a
MSS		 1353 ant_conf->fast_div_bias = 0x6;
1354 break;
223c5a87 1355 case 0x30: /* A+B A-B */
3e9a212a
MSS		 1356 ant_conf->fast_div_bias = 0x1;
1357 break;
223c5a87 1358 case 0x31: /* A+B LNA2 */
3e9a212a
MSS		 1359 ant_conf->fast_div_bias = 0x3b;
1360 break;
223c5a87 1361 case 0x32: /* A+B LNA1 */
3e9a212a
MSS		 1362 ant_conf->fast_div_bias = 0x3d;
1363 break;
1364 default:
1365 break;
1366 }
e7ef5bc0
GJ		 1367 } else if (ant_conf->div_group == 1) {
1368 /* Adjust the fast_div_bias based on main and alt_lna_conf */
1369 switch ((ant_conf->main_lna_conf << 4) |
1370 ant_conf->alt_lna_conf) {
1371 case 0x01: /* A-B LNA2 */
1372 ant_conf->fast_div_bias = 0x1;
1373 ant_conf->main_gaintb = 0;
1374 ant_conf->alt_gaintb = 0;
1375 break;
1376 case 0x02: /* A-B LNA1 */
1377 ant_conf->fast_div_bias = 0x1;
1378 ant_conf->main_gaintb = 0;
1379 ant_conf->alt_gaintb = 0;
1380 break;
1381 case 0x03: /* A-B A+B */
1382 ant_conf->fast_div_bias = 0x1;
1383 ant_conf->main_gaintb = 0;
1384 ant_conf->alt_gaintb = 0;
1385 break;
1386 case 0x10: /* LNA2 A-B */
1387 if (!(antcomb->scan) &&
1388 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1389 ant_conf->fast_div_bias = 0x3f;
1390 else
1391 ant_conf->fast_div_bias = 0x1;
1392 ant_conf->main_gaintb = 0;
1393 ant_conf->alt_gaintb = 0;
1394 break;
1395 case 0x12: /* LNA2 LNA1 */
1396 ant_conf->fast_div_bias = 0x1;
1397 ant_conf->main_gaintb = 0;
1398 ant_conf->alt_gaintb = 0;
1399 break;
1400 case 0x13: /* LNA2 A+B */
1401 if (!(antcomb->scan) &&
1402 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1403 ant_conf->fast_div_bias = 0x3f;
1404 else
1405 ant_conf->fast_div_bias = 0x1;
1406 ant_conf->main_gaintb = 0;
1407 ant_conf->alt_gaintb = 0;
1408 break;
1409 case 0x20: /* LNA1 A-B */
1410 if (!(antcomb->scan) &&
1411 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1412 ant_conf->fast_div_bias = 0x3f;
1413 else
1414 ant_conf->fast_div_bias = 0x1;
1415 ant_conf->main_gaintb = 0;
1416 ant_conf->alt_gaintb = 0;
1417 break;
1418 case 0x21: /* LNA1 LNA2 */
1419 ant_conf->fast_div_bias = 0x1;
1420 ant_conf->main_gaintb = 0;
1421 ant_conf->alt_gaintb = 0;
1422 break;
1423 case 0x23: /* LNA1 A+B */
1424 if (!(antcomb->scan) &&
1425 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1426 ant_conf->fast_div_bias = 0x3f;
1427 else
1428 ant_conf->fast_div_bias = 0x1;
1429 ant_conf->main_gaintb = 0;
1430 ant_conf->alt_gaintb = 0;
1431 break;
1432 case 0x30: /* A+B A-B */
1433 ant_conf->fast_div_bias = 0x1;
1434 ant_conf->main_gaintb = 0;
1435 ant_conf->alt_gaintb = 0;
1436 break;
1437 case 0x31: /* A+B LNA2 */
1438 ant_conf->fast_div_bias = 0x1;
1439 ant_conf->main_gaintb = 0;
1440 ant_conf->alt_gaintb = 0;
1441 break;
1442 case 0x32: /* A+B LNA1 */
1443 ant_conf->fast_div_bias = 0x1;
1444 ant_conf->main_gaintb = 0;
1445 ant_conf->alt_gaintb = 0;
1446 break;
1447 default:
1448 break;
1449 }
3e9a212a
MSS		 1450 } else if (ant_conf->div_group == 2) {
1451 /* Adjust the fast_div_bias based on main and alt_lna_conf */
1452 switch ((ant_conf->main_lna_conf << 4) |
1453 ant_conf->alt_lna_conf) {
223c5a87 1454 case 0x01: /* A-B LNA2 */
3e9a212a
MSS		 1455 ant_conf->fast_div_bias = 0x1;
1456 ant_conf->main_gaintb = 0;
1457 ant_conf->alt_gaintb = 0;
1458 break;
223c5a87 1459 case 0x02: /* A-B LNA1 */
3e9a212a
MSS		 1460 ant_conf->fast_div_bias = 0x1;
1461 ant_conf->main_gaintb = 0;
1462 ant_conf->alt_gaintb = 0;
1463 break;
223c5a87 1464 case 0x03: /* A-B A+B */
3e9a212a
MSS		 1465 ant_conf->fast_div_bias = 0x1;
1466 ant_conf->main_gaintb = 0;
1467 ant_conf->alt_gaintb = 0;
1468 break;
223c5a87 1469 case 0x10: /* LNA2 A-B */
3e9a212a
MSS		 1470 if (!(antcomb->scan) &&
1471 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1472 ant_conf->fast_div_bias = 0x1;
1473 else
1474 ant_conf->fast_div_bias = 0x2;
1475 ant_conf->main_gaintb = 0;
1476 ant_conf->alt_gaintb = 0;
1477 break;
223c5a87 1478 case 0x12: /* LNA2 LNA1 */
3e9a212a
MSS		 1479 ant_conf->fast_div_bias = 0x1;
1480 ant_conf->main_gaintb = 0;
1481 ant_conf->alt_gaintb = 0;
1482 break;
223c5a87 1483 case 0x13: /* LNA2 A+B */
3e9a212a
MSS		 1484 if (!(antcomb->scan) &&
1485 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1486 ant_conf->fast_div_bias = 0x1;
1487 else
1488 ant_conf->fast_div_bias = 0x2;
1489 ant_conf->main_gaintb = 0;
1490 ant_conf->alt_gaintb = 0;
1491 break;
223c5a87 1492 case 0x20: /* LNA1 A-B */
3e9a212a
MSS		 1493 if (!(antcomb->scan) &&
1494 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1495 ant_conf->fast_div_bias = 0x1;
1496 else
1497 ant_conf->fast_div_bias = 0x2;
1498 ant_conf->main_gaintb = 0;
1499 ant_conf->alt_gaintb = 0;
1500 break;
223c5a87 1501 case 0x21: /* LNA1 LNA2 */
3e9a212a
MSS		 1502 ant_conf->fast_div_bias = 0x1;
1503 ant_conf->main_gaintb = 0;
1504 ant_conf->alt_gaintb = 0;
1505 break;
223c5a87 1506 case 0x23: /* LNA1 A+B */
3e9a212a
MSS		 1507 if (!(antcomb->scan) &&
1508 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1509 ant_conf->fast_div_bias = 0x1;
1510 else
1511 ant_conf->fast_div_bias = 0x2;
1512 ant_conf->main_gaintb = 0;
1513 ant_conf->alt_gaintb = 0;
1514 break;
223c5a87 1515 case 0x30: /* A+B A-B */
3e9a212a
MSS		 1516 ant_conf->fast_div_bias = 0x1;
1517 ant_conf->main_gaintb = 0;
1518 ant_conf->alt_gaintb = 0;
1519 break;
223c5a87 1520 case 0x31: /* A+B LNA2 */
3e9a212a
MSS		 1521 ant_conf->fast_div_bias = 0x1;
1522 ant_conf->main_gaintb = 0;
1523 ant_conf->alt_gaintb = 0;
1524 break;
223c5a87 1525 case 0x32: /* A+B LNA1 */
3e9a212a
MSS		 1526 ant_conf->fast_div_bias = 0x1;
1527 ant_conf->main_gaintb = 0;
1528 ant_conf->alt_gaintb = 0;
1529 break;
1530 default:
1531 break;
1532 }
102885a5
VT		 1533 }
1534}
1535
1536/* Antenna diversity and combining */
1537static void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs)
1538{
1539 struct ath_hw_antcomb_conf div_ant_conf;
1540 struct ath_ant_comb *antcomb = &sc->ant_comb;
1541 int alt_ratio = 0, alt_rssi_avg = 0, main_rssi_avg = 0, curr_alt_set;
0ff2b5c0 1542 int curr_main_set;
102885a5
VT		 1543 int main_rssi = rs->rs_rssi_ctl0;
1544 int alt_rssi = rs->rs_rssi_ctl1;
1545 int rx_ant_conf, main_ant_conf;
1546 bool short_scan = false;
1547
1548 rx_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_CURRENT_SHIFT) &
1549 ATH_ANT_RX_MASK;
1550 main_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_MAIN_SHIFT) &
1551 ATH_ANT_RX_MASK;
1552
21e8ee6d
MSS		 1553 /* Record packet only when both main_rssi and alt_rssi is positive */
1554 if (main_rssi > 0 && alt_rssi > 0) {
102885a5
VT		 1555 antcomb->total_pkt_count++;
1556 antcomb->main_total_rssi += main_rssi;
1557 antcomb->alt_total_rssi += alt_rssi;
1558 if (main_ant_conf == rx_ant_conf)
1559 antcomb->main_recv_cnt++;
1560 else
1561 antcomb->alt_recv_cnt++;
1562 }
1563
1564 /* Short scan check */
1565 if (antcomb->scan && antcomb->alt_good) {
1566 if (time_after(jiffies, antcomb->scan_start_time +
1567 msecs_to_jiffies(ATH_ANT_DIV_COMB_SHORT_SCAN_INTR)))
1568 short_scan = true;
1569 else
1570 if (antcomb->total_pkt_count ==
1571 ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT) {
1572 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
1573 antcomb->total_pkt_count);
1574 if (alt_ratio < ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
1575 short_scan = true;
1576 }
1577 }
1578
1579 if (((antcomb->total_pkt_count < ATH_ANT_DIV_COMB_MAX_PKTCOUNT) ||
1580 rs->rs_moreaggr) && !short_scan)
1581 return;
1582
1583 if (antcomb->total_pkt_count) {
1584 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
1585 antcomb->total_pkt_count);
1586 main_rssi_avg = (antcomb->main_total_rssi /
1587 antcomb->total_pkt_count);
1588 alt_rssi_avg = (antcomb->alt_total_rssi /
1589 antcomb->total_pkt_count);
1590 }
1591
1592
1593 ath9k_hw_antdiv_comb_conf_get(sc->sc_ah, &div_ant_conf);
1594 curr_alt_set = div_ant_conf.alt_lna_conf;
1595 curr_main_set = div_ant_conf.main_lna_conf;
102885a5
VT		 1596
1597 antcomb->count++;
1598
1599 if (antcomb->count == ATH_ANT_DIV_COMB_MAX_COUNT) {
1600 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) {
1601 ath_lnaconf_alt_good_scan(antcomb, div_ant_conf,
1602 main_rssi_avg);
1603 antcomb->alt_good = true;
1604 } else {
1605 antcomb->alt_good = false;
1606 }
1607
1608 antcomb->count = 0;
1609 antcomb->scan = true;
1610 antcomb->scan_not_start = true;
1611 }
1612
1613 if (!antcomb->scan) {
b85c5734
MSS		 1614 if (ath_ant_div_comb_alt_check(div_ant_conf.div_group,
1615 alt_ratio, curr_main_set, curr_alt_set,
1616 alt_rssi_avg, main_rssi_avg)) {
102885a5
VT		 1617 if (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) {
1618 /* Switch main and alt LNA */
1619 div_ant_conf.main_lna_conf =
1620 ATH_ANT_DIV_COMB_LNA2;
1621 div_ant_conf.alt_lna_conf =
1622 ATH_ANT_DIV_COMB_LNA1;
1623 } else if (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) {
1624 div_ant_conf.main_lna_conf =
1625 ATH_ANT_DIV_COMB_LNA1;
1626 div_ant_conf.alt_lna_conf =
1627 ATH_ANT_DIV_COMB_LNA2;
1628 }
1629
1630 goto div_comb_done;
1631 } else if ((curr_alt_set != ATH_ANT_DIV_COMB_LNA1) &&
1632 (curr_alt_set != ATH_ANT_DIV_COMB_LNA2)) {
1633 /* Set alt to another LNA */
1634 if (curr_main_set == ATH_ANT_DIV_COMB_LNA2)
1635 div_ant_conf.alt_lna_conf =
1636 ATH_ANT_DIV_COMB_LNA1;
1637 else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1)
1638 div_ant_conf.alt_lna_conf =
1639 ATH_ANT_DIV_COMB_LNA2;
1640
1641 goto div_comb_done;
1642 }
1643
1644 if ((alt_rssi_avg < (main_rssi_avg +
8afbcc8b 1645 div_ant_conf.lna1_lna2_delta)))
102885a5
VT		 1646 goto div_comb_done;
1647 }
1648
1649 if (!antcomb->scan_not_start) {
1650 switch (curr_alt_set) {
1651 case ATH_ANT_DIV_COMB_LNA2:
1652 antcomb->rssi_lna2 = alt_rssi_avg;
1653 antcomb->rssi_lna1 = main_rssi_avg;
1654 antcomb->scan = true;
1655 /* set to A+B */
1656 div_ant_conf.main_lna_conf =
1657 ATH_ANT_DIV_COMB_LNA1;
1658 div_ant_conf.alt_lna_conf =
1659 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1660 break;
1661 case ATH_ANT_DIV_COMB_LNA1:
1662 antcomb->rssi_lna1 = alt_rssi_avg;
1663 antcomb->rssi_lna2 = main_rssi_avg;
1664 antcomb->scan = true;
1665 /* set to A+B */
1666 div_ant_conf.main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
1667 div_ant_conf.alt_lna_conf =
1668 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1669 break;
1670 case ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2:
1671 antcomb->rssi_add = alt_rssi_avg;
1672 antcomb->scan = true;
1673 /* set to A-B */
1674 div_ant_conf.alt_lna_conf =
1675 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1676 break;
1677 case ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2:
1678 antcomb->rssi_sub = alt_rssi_avg;
1679 antcomb->scan = false;
1680 if (antcomb->rssi_lna2 >
1681 (antcomb->rssi_lna1 +
1682 ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)) {
1683 /* use LNA2 as main LNA */
1684 if ((antcomb->rssi_add > antcomb->rssi_lna1) &&
1685 (antcomb->rssi_add > antcomb->rssi_sub)) {
1686 /* set to A+B */
1687 div_ant_conf.main_lna_conf =
1688 ATH_ANT_DIV_COMB_LNA2;
1689 div_ant_conf.alt_lna_conf =
1690 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1691 } else if (antcomb->rssi_sub >
1692 antcomb->rssi_lna1) {
1693 /* set to A-B */
1694 div_ant_conf.main_lna_conf =
1695 ATH_ANT_DIV_COMB_LNA2;
1696 div_ant_conf.alt_lna_conf =
1697 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1698 } else {
1699 /* set to LNA1 */
1700 div_ant_conf.main_lna_conf =
1701 ATH_ANT_DIV_COMB_LNA2;
1702 div_ant_conf.alt_lna_conf =
1703 ATH_ANT_DIV_COMB_LNA1;
1704 }
1705 } else {
1706 /* use LNA1 as main LNA */
1707 if ((antcomb->rssi_add > antcomb->rssi_lna2) &&
1708 (antcomb->rssi_add > antcomb->rssi_sub)) {
1709 /* set to A+B */
1710 div_ant_conf.main_lna_conf =
1711 ATH_ANT_DIV_COMB_LNA1;
1712 div_ant_conf.alt_lna_conf =
1713 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1714 } else if (antcomb->rssi_sub >
1715 antcomb->rssi_lna1) {
1716 /* set to A-B */
1717 div_ant_conf.main_lna_conf =
1718 ATH_ANT_DIV_COMB_LNA1;
1719 div_ant_conf.alt_lna_conf =
1720 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1721 } else {
1722 /* set to LNA2 */
1723 div_ant_conf.main_lna_conf =
1724 ATH_ANT_DIV_COMB_LNA1;
1725 div_ant_conf.alt_lna_conf =
1726 ATH_ANT_DIV_COMB_LNA2;
1727 }
1728 }
1729 break;
1730 default:
1731 break;
1732 }
1733 } else {
1734 if (!antcomb->alt_good) {
1735 antcomb->scan_not_start = false;
1736 /* Set alt to another LNA */
1737 if (curr_main_set == ATH_ANT_DIV_COMB_LNA2) {
1738 div_ant_conf.main_lna_conf =
1739 ATH_ANT_DIV_COMB_LNA2;
1740 div_ant_conf.alt_lna_conf =
1741 ATH_ANT_DIV_COMB_LNA1;
1742 } else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1) {
1743 div_ant_conf.main_lna_conf =
1744 ATH_ANT_DIV_COMB_LNA1;
1745 div_ant_conf.alt_lna_conf =
1746 ATH_ANT_DIV_COMB_LNA2;
1747 }
1748 goto div_comb_done;
1749 }
1750 }
1751
1752 ath_select_ant_div_from_quick_scan(antcomb, &div_ant_conf,
1753 main_rssi_avg, alt_rssi_avg,
1754 alt_ratio);
1755
1756 antcomb->quick_scan_cnt++;
1757
1758div_comb_done:
3e9a212a 1759 ath_ant_div_conf_fast_divbias(&div_ant_conf, antcomb, alt_ratio);
102885a5
VT		 1760 ath9k_hw_antdiv_comb_conf_set(sc->sc_ah, &div_ant_conf);
1761
1762 antcomb->scan_start_time = jiffies;
1763 antcomb->total_pkt_count = 0;
1764 antcomb->main_total_rssi = 0;
1765 antcomb->alt_total_rssi = 0;
1766 antcomb->main_recv_cnt = 0;
1767 antcomb->alt_recv_cnt = 0;
1768}
1769
b5c80475
FF		 1770int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
1771{
1772 struct ath_buf *bf;
0d95521e 1773 struct sk_buff *skb = NULL, *requeue_skb, *hdr_skb;
5ca42627 1774 struct ieee80211_rx_status *rxs;
cbe61d8a 1775 struct ath_hw *ah = sc->sc_ah;
27c51f1a 1776 struct ath_common *common = ath9k_hw_common(ah);
7545daf4 1777 struct ieee80211_hw *hw = sc->hw;
be0418ad 1778 struct ieee80211_hdr *hdr;
c9b14170 1779 int retval;
be0418ad 1780 bool decrypt_error = false;
29bffa96 1781 struct ath_rx_status rs;
b5c80475
FF		 1782 enum ath9k_rx_qtype qtype;
1783 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1784 int dma_type;
5c6dd921 1785 u8 rx_status_len = ah->caps.rx_status_len;
a6d2055b
FF		 1786 u64 tsf = 0;
1787 u32 tsf_lower = 0;
8ab2cd09 1788 unsigned long flags;
be0418ad 1789
b5c80475 1790 if (edma)
b5c80475 1791 dma_type = DMA_BIDIRECTIONAL;
56824223
ML		 1792 else
1793 dma_type = DMA_FROM_DEVICE;
b5c80475
FF		 1794
1795 qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
b77f483f 1796 spin_lock_bh(&sc->rx.rxbuflock);
f078f209 1797
a6d2055b
FF		 1798 tsf = ath9k_hw_gettsf64(ah);
1799 tsf_lower = tsf & 0xffffffff;
1800
f078f209
LR		 1801 do {
1802 /* If handling rx interrupt and flush is in progress => exit */
98deeea0 1803 if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
f078f209
LR		 1804 break;
1805
29bffa96 1806 memset(&rs, 0, sizeof(rs));
b5c80475
FF		 1807 if (edma)
1808 bf = ath_edma_get_next_rx_buf(sc, &rs, qtype);
1809 else
1810 bf = ath_get_next_rx_buf(sc, &rs);
f078f209 1811
b5c80475
FF		 1812 if (!bf)
1813 break;
f078f209 1814
f078f209 1815 skb = bf->bf_mpdu;
be0418ad 1816 if (!skb)
f078f209 1817 continue;
f078f209 1818
0d95521e
FF		 1819 /*
1820 * Take frame header from the first fragment and RX status from
1821 * the last one.
1822 */
1823 if (sc->rx.frag)
1824 hdr_skb = sc->rx.frag;
1825 else
1826 hdr_skb = skb;
1827
1828 hdr = (struct ieee80211_hdr *) (hdr_skb->data + rx_status_len);
1829 rxs = IEEE80211_SKB_RXCB(hdr_skb);
cf3af748
RM		 1830 if (ieee80211_is_beacon(hdr->frame_control) &&
1831 !compare_ether_addr(hdr->addr3, common->curbssid))
1832 rs.is_mybeacon = true;
1833 else
1834 rs.is_mybeacon = false;
5ca42627 1835
29bffa96 1836 ath_debug_stat_rx(sc, &rs);
1395d3f0 1837
f078f209 1838 /*
be0418ad
S		 1839 * If we're asked to flush receive queue, directly
1840 * chain it back at the queue without processing it.
f078f209 1841 */
be0418ad 1842 if (flush)
0d95521e 1843 goto requeue_drop_frag;
f078f209 1844
c8f3b721
JF		 1845 retval = ath9k_rx_skb_preprocess(common, hw, hdr, &rs,
1846 rxs, &decrypt_error);
1847 if (retval)
0d95521e 1848 goto requeue_drop_frag;
c8f3b721 1849
a6d2055b
FF		 1850 rxs->mactime = (tsf & ~0xffffffffULL) | rs.rs_tstamp;
1851 if (rs.rs_tstamp > tsf_lower &&
1852 unlikely(rs.rs_tstamp - tsf_lower > 0x10000000))
1853 rxs->mactime -= 0x100000000ULL;
1854
1855 if (rs.rs_tstamp < tsf_lower &&
1856 unlikely(tsf_lower - rs.rs_tstamp > 0x10000000))
1857 rxs->mactime += 0x100000000ULL;
1858
cb71d9ba
LR		 1859 /* Ensure we always have an skb to requeue once we are done
1860 * processing the current buffer's skb */
cc861f74 1861 requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC);
cb71d9ba
LR		 1862
1863 /* If there is no memory we ignore the current RX'd frame,
1864 * tell hardware it can give us a new frame using the old
b77f483f 1865 * skb and put it at the tail of the sc->rx.rxbuf list for
cb71d9ba
LR		 1866 * processing. */
1867 if (!requeue_skb)
0d95521e 1868 goto requeue_drop_frag;
f078f209 1869
9bf9fca8 1870 /* Unmap the frame */
7da3c55c 1871 dma_unmap_single(sc->dev, bf->bf_buf_addr,
cc861f74 1872 common->rx_bufsize,
b5c80475 1873 dma_type);
f078f209 1874
b5c80475
FF		 1875 skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len);
1876 if (ah->caps.rx_status_len)
1877 skb_pull(skb, ah->caps.rx_status_len);
be0418ad 1878
0d95521e
FF		 1879 if (!rs.rs_more)
1880 ath9k_rx_skb_postprocess(common, hdr_skb, &rs,
1881 rxs, decrypt_error);
be0418ad 1882
cb71d9ba
LR		 1883 /* We will now give hardware our shiny new allocated skb */
1884 bf->bf_mpdu = requeue_skb;
7da3c55c 1885 bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
cc861f74 1886 common->rx_bufsize,
b5c80475 1887 dma_type);
7da3c55c 1888 if (unlikely(dma_mapping_error(sc->dev,
f8316df1
LR		 1889 bf->bf_buf_addr))) {
1890 dev_kfree_skb_any(requeue_skb);
1891 bf->bf_mpdu = NULL;
6cf9e995 1892 bf->bf_buf_addr = 0;
3800276a 1893 ath_err(common, "dma_mapping_error() on RX\n");
7545daf4 1894 ieee80211_rx(hw, skb);
f8316df1
LR		 1895 break;
1896 }
f078f209 1897
0d95521e
FF		 1898 if (rs.rs_more) {
1899 /*
1900 * rs_more indicates chained descriptors which can be
1901 * used to link buffers together for a sort of
1902 * scatter-gather operation.
1903 */
1904 if (sc->rx.frag) {
1905 /* too many fragments - cannot handle frame */
1906 dev_kfree_skb_any(sc->rx.frag);
1907 dev_kfree_skb_any(skb);
1908 skb = NULL;
1909 }
1910 sc->rx.frag = skb;
1911 goto requeue;
1912 }
1913
1914 if (sc->rx.frag) {
1915 int space = skb->len - skb_tailroom(hdr_skb);
1916
1917 sc->rx.frag = NULL;
1918
1919 if (pskb_expand_head(hdr_skb, 0, space, GFP_ATOMIC) < 0) {
1920 dev_kfree_skb(skb);
1921 goto requeue_drop_frag;
1922 }
1923
1924 skb_copy_from_linear_data(skb, skb_put(hdr_skb, skb->len),
1925 skb->len);
1926 dev_kfree_skb_any(skb);
1927 skb = hdr_skb;
1928 }
1929
f078f209
LR		 1930 /*
1931 * change the default rx antenna if rx diversity chooses the
1932 * other antenna 3 times in a row.
1933 */
29bffa96 1934 if (sc->rx.defant != rs.rs_antenna) {
b77f483f 1935 if (++sc->rx.rxotherant >= 3)
29bffa96 1936 ath_setdefantenna(sc, rs.rs_antenna);
f078f209 1937 } else {
b77f483f 1938 sc->rx.rxotherant = 0;
f078f209 1939 }
3cbb5dd7 1940
66760eac
FF		 1941 if (rxs->flag & RX_FLAG_MMIC_STRIPPED)
1942 skb_trim(skb, skb->len - 8);
1943
8ab2cd09 1944 spin_lock_irqsave(&sc->sc_pm_lock, flags);
aaef24b4
MSS		 1945
1946 if ((sc->ps_flags & (PS_WAIT_FOR_BEACON |
ededf1f8 1947 PS_WAIT_FOR_CAB |
aaef24b4 1948 PS_WAIT_FOR_PSPOLL_DATA)) ||
cedc7e3d 1949 ath9k_check_auto_sleep(sc))
cc65965c 1950 ath_rx_ps(sc, skb);
8ab2cd09 1951 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
cc65965c 1952
43c35284 1953 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx == 3)
102885a5
VT		 1954 ath_ant_comb_scan(sc, &rs);
1955
7545daf4 1956 ieee80211_rx(hw, skb);
cc65965c 1957
0d95521e
FF		 1958requeue_drop_frag:
1959 if (sc->rx.frag) {
1960 dev_kfree_skb_any(sc->rx.frag);
1961 sc->rx.frag = NULL;
1962 }
cb71d9ba 1963requeue:
b5c80475
FF		 1964 if (edma) {
1965 list_add_tail(&bf->list, &sc->rx.rxbuf);
1966 ath_rx_edma_buf_link(sc, qtype);
1967 } else {
1968 list_move_tail(&bf->list, &sc->rx.rxbuf);
1969 ath_rx_buf_link(sc, bf);
95294973 1970 ath9k_hw_rxena(ah);
b5c80475 1971 }
be0418ad
S		 1972 } while (1);
1973
b77f483f 1974 spin_unlock_bh(&sc->rx.rxbuflock);
f078f209 1975
29ab0b36
RM		 1976 if (!(ah->imask & ATH9K_INT_RXEOL)) {
1977 ah->imask |= (ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
1978 ath9k_hw_set_interrupts(ah, ah->imask);
1979 }
1980
f078f209 1981 return 0;
f078f209 1982}
Linux kernel - Deliverables
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