Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
394cf0a1 | 17 | #include "ath9k.h" |
f078f209 | 18 | |
bce048d7 JM |
19 | static struct ieee80211_hw * ath_get_virt_hw(struct ath_softc *sc, |
20 | struct ieee80211_hdr *hdr) | |
21 | { | |
c52f33d0 JM |
22 | struct ieee80211_hw *hw = sc->pri_wiphy->hw; |
23 | int i; | |
24 | ||
25 | spin_lock_bh(&sc->wiphy_lock); | |
26 | for (i = 0; i < sc->num_sec_wiphy; i++) { | |
27 | struct ath_wiphy *aphy = sc->sec_wiphy[i]; | |
28 | if (aphy == NULL) | |
29 | continue; | |
30 | if (compare_ether_addr(hdr->addr1, aphy->hw->wiphy->perm_addr) | |
31 | == 0) { | |
32 | hw = aphy->hw; | |
33 | break; | |
34 | } | |
35 | } | |
36 | spin_unlock_bh(&sc->wiphy_lock); | |
37 | return hw; | |
bce048d7 JM |
38 | } |
39 | ||
f078f209 LR |
40 | /* |
41 | * Setup and link descriptors. | |
42 | * | |
43 | * 11N: we can no longer afford to self link the last descriptor. | |
44 | * MAC acknowledges BA status as long as it copies frames to host | |
45 | * buffer (or rx fifo). This can incorrectly acknowledge packets | |
46 | * to a sender if last desc is self-linked. | |
f078f209 | 47 | */ |
f078f209 LR |
48 | static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf) |
49 | { | |
cbe61d8a | 50 | struct ath_hw *ah = sc->sc_ah; |
f078f209 LR |
51 | struct ath_desc *ds; |
52 | struct sk_buff *skb; | |
53 | ||
54 | ATH_RXBUF_RESET(bf); | |
55 | ||
56 | ds = bf->bf_desc; | |
be0418ad | 57 | ds->ds_link = 0; /* link to null */ |
f078f209 LR |
58 | ds->ds_data = bf->bf_buf_addr; |
59 | ||
be0418ad | 60 | /* virtual addr of the beginning of the buffer. */ |
f078f209 | 61 | skb = bf->bf_mpdu; |
9680e8a3 | 62 | BUG_ON(skb == NULL); |
f078f209 LR |
63 | ds->ds_vdata = skb->data; |
64 | ||
b77f483f | 65 | /* setup rx descriptors. The rx.bufsize here tells the harware |
b4b6cda2 LR |
66 | * how much data it can DMA to us and that we are prepared |
67 | * to process */ | |
b77f483f S |
68 | ath9k_hw_setuprxdesc(ah, ds, |
69 | sc->rx.bufsize, | |
f078f209 LR |
70 | 0); |
71 | ||
b77f483f | 72 | if (sc->rx.rxlink == NULL) |
f078f209 LR |
73 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); |
74 | else | |
b77f483f | 75 | *sc->rx.rxlink = bf->bf_daddr; |
f078f209 | 76 | |
b77f483f | 77 | sc->rx.rxlink = &ds->ds_link; |
f078f209 LR |
78 | ath9k_hw_rxena(ah); |
79 | } | |
80 | ||
ff37e337 S |
81 | static void ath_setdefantenna(struct ath_softc *sc, u32 antenna) |
82 | { | |
83 | /* XXX block beacon interrupts */ | |
84 | ath9k_hw_setantenna(sc->sc_ah, antenna); | |
b77f483f S |
85 | sc->rx.defant = antenna; |
86 | sc->rx.rxotherant = 0; | |
ff37e337 S |
87 | } |
88 | ||
207e9685 LR |
89 | /* Assumes you've already done the endian to CPU conversion */ |
90 | static bool ath9k_rx_accept(struct ath_common *common, | |
91 | struct sk_buff *skb, | |
92 | struct ieee80211_rx_status *rxs, | |
93 | struct ath_rx_status *rx_stats, | |
94 | bool *decrypt_error) | |
f078f209 | 95 | { |
712c13a8 | 96 | struct ath_hw *ah = common->ah; |
be0418ad | 97 | struct ieee80211_hdr *hdr; |
be0418ad | 98 | __le16 fc; |
a59b5a5e | 99 | |
207e9685 | 100 | hdr = (struct ieee80211_hdr *) skb->data; |
be0418ad | 101 | fc = hdr->frame_control; |
be0418ad | 102 | |
26ab2645 | 103 | if (rx_stats->rs_more) { |
be0418ad S |
104 | /* |
105 | * Frame spans multiple descriptors; this cannot happen yet | |
106 | * as we don't support jumbograms. If not in monitor mode, | |
107 | * discard the frame. Enable this if you want to see | |
108 | * error frames in Monitor mode. | |
109 | */ | |
712c13a8 | 110 | if (ah->opmode != NL80211_IFTYPE_MONITOR) |
207e9685 | 111 | return false; |
26ab2645 LR |
112 | } else if (rx_stats->rs_status != 0) { |
113 | if (rx_stats->rs_status & ATH9K_RXERR_CRC) | |
207e9685 | 114 | rxs->flag |= RX_FLAG_FAILED_FCS_CRC; |
26ab2645 | 115 | if (rx_stats->rs_status & ATH9K_RXERR_PHY) |
207e9685 | 116 | return false; |
f078f209 | 117 | |
26ab2645 | 118 | if (rx_stats->rs_status & ATH9K_RXERR_DECRYPT) { |
be0418ad | 119 | *decrypt_error = true; |
26ab2645 | 120 | } else if (rx_stats->rs_status & ATH9K_RXERR_MIC) { |
be0418ad S |
121 | if (ieee80211_is_ctl(fc)) |
122 | /* | |
123 | * Sometimes, we get invalid | |
124 | * MIC failures on valid control frames. | |
125 | * Remove these mic errors. | |
126 | */ | |
26ab2645 | 127 | rx_stats->rs_status &= ~ATH9K_RXERR_MIC; |
be0418ad | 128 | else |
207e9685 | 129 | rxs->flag |= RX_FLAG_MMIC_ERROR; |
be0418ad S |
130 | } |
131 | /* | |
132 | * Reject error frames with the exception of | |
133 | * decryption and MIC failures. For monitor mode, | |
134 | * we also ignore the CRC error. | |
135 | */ | |
712c13a8 | 136 | if (ah->opmode == NL80211_IFTYPE_MONITOR) { |
26ab2645 | 137 | if (rx_stats->rs_status & |
be0418ad S |
138 | ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC | |
139 | ATH9K_RXERR_CRC)) | |
207e9685 | 140 | return false; |
be0418ad | 141 | } else { |
26ab2645 | 142 | if (rx_stats->rs_status & |
be0418ad | 143 | ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) { |
207e9685 | 144 | return false; |
be0418ad S |
145 | } |
146 | } | |
f078f209 | 147 | } |
207e9685 LR |
148 | return true; |
149 | } | |
150 | ||
9878841e LR |
151 | static u8 ath9k_process_rate(struct ath_common *common, |
152 | struct ieee80211_hw *hw, | |
153 | struct ath_rx_status *rx_stats, | |
154 | struct ieee80211_rx_status *rxs, | |
155 | struct sk_buff *skb) | |
156 | { | |
157 | struct ieee80211_supported_band *sband; | |
158 | enum ieee80211_band band; | |
159 | unsigned int i = 0; | |
160 | ||
161 | band = hw->conf.channel->band; | |
162 | sband = hw->wiphy->bands[band]; | |
163 | ||
164 | if (rx_stats->rs_rate & 0x80) { | |
165 | /* HT rate */ | |
166 | rxs->flag |= RX_FLAG_HT; | |
167 | if (rx_stats->rs_flags & ATH9K_RX_2040) | |
168 | rxs->flag |= RX_FLAG_40MHZ; | |
169 | if (rx_stats->rs_flags & ATH9K_RX_GI) | |
170 | rxs->flag |= RX_FLAG_SHORT_GI; | |
171 | return rx_stats->rs_rate & 0x7f; | |
172 | } | |
173 | ||
174 | for (i = 0; i < sband->n_bitrates; i++) { | |
175 | if (sband->bitrates[i].hw_value == rx_stats->rs_rate) | |
176 | return i; | |
177 | if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) { | |
178 | rxs->flag |= RX_FLAG_SHORTPRE; | |
179 | return i; | |
180 | } | |
181 | } | |
182 | ||
183 | /* No valid hardware bitrate found -- we should not get here */ | |
184 | ath_print(common, ATH_DBG_XMIT, "unsupported hw bitrate detected " | |
185 | "0x%02x using 1 Mbit\n", rx_stats->rs_rate); | |
186 | if ((common->debug_mask & ATH_DBG_XMIT)) | |
187 | print_hex_dump_bytes("", DUMP_PREFIX_NONE, skb->data, skb->len); | |
188 | ||
189 | return 0; | |
190 | } | |
191 | ||
21b22738 LR |
192 | /* |
193 | * Theory for reporting quality: | |
194 | * | |
195 | * At a hardware RSSI of 45 you will be able to use MCS 7 reliably. | |
196 | * At a hardware RSSI of 45 you will be able to use MCS 15 reliably. | |
197 | * At a hardware RSSI of 35 you should be able use 54 Mbps reliably. | |
198 | * | |
199 | * MCS 7 is the highets MCS index usable by a 1-stream device. | |
200 | * MCS 15 is the highest MCS index usable by a 2-stream device. | |
201 | * | |
202 | * All ath9k devices are either 1-stream or 2-stream. | |
203 | * | |
204 | * How many bars you see is derived from the qual reporting. | |
205 | * | |
206 | * A more elaborate scheme can be used here but it requires tables | |
207 | * of SNR/throughput for each possible mode used. For the MCS table | |
208 | * you can refer to the wireless wiki: | |
209 | * | |
210 | * http://wireless.kernel.org/en/developers/Documentation/ieee80211/802.11n | |
211 | * | |
212 | */ | |
213 | static int ath9k_compute_qual(struct ieee80211_hw *hw, | |
214 | struct ath_rx_status *rx_stats) | |
215 | { | |
216 | int qual; | |
217 | ||
218 | if (conf_is_ht(&hw->conf)) | |
219 | qual = rx_stats->rs_rssi * 100 / 45; | |
220 | else | |
221 | qual = rx_stats->rs_rssi * 100 / 35; | |
222 | ||
223 | /* | |
224 | * rssi can be more than 45 though, anything above that | |
225 | * should be considered at 100% | |
226 | */ | |
227 | if (qual > 100) | |
228 | qual = 100; | |
229 | ||
230 | return qual; | |
231 | } | |
232 | ||
dbfc22df LR |
233 | static void ath9k_process_rssi(struct ath_common *common, |
234 | struct ieee80211_hw *hw, | |
235 | struct sk_buff *skb, | |
236 | struct ath_rx_status *rx_stats) | |
207e9685 LR |
237 | { |
238 | struct ath_hw *ah = common->ah; | |
207e9685 | 239 | struct ieee80211_sta *sta; |
dbfc22df | 240 | struct ieee80211_hdr *hdr; |
207e9685 LR |
241 | struct ath_node *an; |
242 | int last_rssi = ATH_RSSI_DUMMY_MARKER; | |
dbfc22df | 243 | __le16 fc; |
207e9685 LR |
244 | |
245 | hdr = (struct ieee80211_hdr *)skb->data; | |
246 | fc = hdr->frame_control; | |
be0418ad | 247 | |
a59b5a5e | 248 | rcu_read_lock(); |
5ed176e1 | 249 | /* XXX: use ieee80211_find_sta! */ |
cee71d6c | 250 | sta = ieee80211_find_sta_by_hw(hw, hdr->addr2); |
a59b5a5e SB |
251 | if (sta) { |
252 | an = (struct ath_node *) sta->drv_priv; | |
26ab2645 LR |
253 | if (rx_stats->rs_rssi != ATH9K_RSSI_BAD && |
254 | !rx_stats->rs_moreaggr) | |
255 | ATH_RSSI_LPF(an->last_rssi, rx_stats->rs_rssi); | |
a59b5a5e SB |
256 | last_rssi = an->last_rssi; |
257 | } | |
258 | rcu_read_unlock(); | |
259 | ||
260 | if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER)) | |
26ab2645 LR |
261 | rx_stats->rs_rssi = ATH_EP_RND(last_rssi, |
262 | ATH_RSSI_EP_MULTIPLIER); | |
263 | if (rx_stats->rs_rssi < 0) | |
264 | rx_stats->rs_rssi = 0; | |
265 | else if (rx_stats->rs_rssi > 127) | |
266 | rx_stats->rs_rssi = 127; | |
a59b5a5e | 267 | |
5e32b1ed S |
268 | /* Update Beacon RSSI, this is used by ANI. */ |
269 | if (ieee80211_is_beacon(fc)) | |
712c13a8 | 270 | ah->stats.avgbrssi = rx_stats->rs_rssi; |
dbfc22df LR |
271 | } |
272 | ||
273 | /* | |
274 | * For Decrypt or Demic errors, we only mark packet status here and always push | |
275 | * up the frame up to let mac80211 handle the actual error case, be it no | |
276 | * decryption key or real decryption error. This let us keep statistics there. | |
277 | */ | |
278 | static int ath_rx_prepare(struct ath_common *common, | |
279 | struct ieee80211_hw *hw, | |
280 | struct sk_buff *skb, struct ath_rx_status *rx_stats, | |
281 | struct ieee80211_rx_status *rx_status, | |
282 | bool *decrypt_error) | |
283 | { | |
284 | struct ath_hw *ah = common->ah; | |
285 | ||
286 | memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); | |
287 | ||
288 | if (!ath9k_rx_accept(common, skb, rx_status, rx_stats, decrypt_error)) | |
289 | goto rx_next; | |
290 | ||
291 | ath9k_process_rssi(common, hw, skb, rx_stats); | |
5e32b1ed | 292 | |
9878841e LR |
293 | rx_status->rate_idx = ath9k_process_rate(common, hw, |
294 | rx_stats, rx_status, skb); | |
712c13a8 | 295 | rx_status->mactime = ath9k_hw_extend_tsf(ah, rx_stats->rs_tstamp); |
bce048d7 JM |
296 | rx_status->band = hw->conf.channel->band; |
297 | rx_status->freq = hw->conf.channel->center_freq; | |
3d536acf | 298 | rx_status->noise = common->ani.noise_floor; |
26ab2645 LR |
299 | rx_status->signal = ATH_DEFAULT_NOISE_FLOOR + rx_stats->rs_rssi; |
300 | rx_status->antenna = rx_stats->rs_antenna; | |
21b22738 | 301 | rx_status->qual = ath9k_compute_qual(hw, rx_stats); |
be0418ad S |
302 | rx_status->flag |= RX_FLAG_TSFT; |
303 | ||
304 | return 1; | |
305 | rx_next: | |
306 | return 0; | |
f078f209 LR |
307 | } |
308 | ||
309 | static void ath_opmode_init(struct ath_softc *sc) | |
310 | { | |
cbe61d8a | 311 | struct ath_hw *ah = sc->sc_ah; |
1510718d LR |
312 | struct ath_common *common = ath9k_hw_common(ah); |
313 | ||
f078f209 LR |
314 | u32 rfilt, mfilt[2]; |
315 | ||
316 | /* configure rx filter */ | |
317 | rfilt = ath_calcrxfilter(sc); | |
318 | ath9k_hw_setrxfilter(ah, rfilt); | |
319 | ||
320 | /* configure bssid mask */ | |
2660b81a | 321 | if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) |
13b81559 | 322 | ath_hw_setbssidmask(common); |
f078f209 LR |
323 | |
324 | /* configure operational mode */ | |
325 | ath9k_hw_setopmode(ah); | |
326 | ||
327 | /* Handle any link-level address change. */ | |
1510718d | 328 | ath9k_hw_setmac(ah, common->macaddr); |
f078f209 LR |
329 | |
330 | /* calculate and install multicast filter */ | |
331 | mfilt[0] = mfilt[1] = ~0; | |
f078f209 | 332 | ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]); |
f078f209 LR |
333 | } |
334 | ||
335 | int ath_rx_init(struct ath_softc *sc, int nbufs) | |
336 | { | |
27c51f1a | 337 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
f078f209 LR |
338 | struct sk_buff *skb; |
339 | struct ath_buf *bf; | |
340 | int error = 0; | |
341 | ||
797fe5cb S |
342 | spin_lock_init(&sc->rx.rxflushlock); |
343 | sc->sc_flags &= ~SC_OP_RXFLUSH; | |
344 | spin_lock_init(&sc->rx.rxbuflock); | |
f078f209 | 345 | |
797fe5cb | 346 | sc->rx.bufsize = roundup(IEEE80211_MAX_MPDU_LEN, |
27c51f1a | 347 | min(common->cachelsz, (u16)64)); |
f078f209 | 348 | |
c46917bb LR |
349 | ath_print(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n", |
350 | common->cachelsz, sc->rx.bufsize); | |
f078f209 | 351 | |
797fe5cb | 352 | /* Initialize rx descriptors */ |
f078f209 | 353 | |
797fe5cb S |
354 | error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf, |
355 | "rx", nbufs, 1); | |
356 | if (error != 0) { | |
c46917bb LR |
357 | ath_print(common, ATH_DBG_FATAL, |
358 | "failed to allocate rx descriptors: %d\n", error); | |
797fe5cb S |
359 | goto err; |
360 | } | |
f078f209 | 361 | |
797fe5cb | 362 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { |
27c51f1a | 363 | skb = ath_rxbuf_alloc(common, sc->rx.bufsize, GFP_KERNEL); |
797fe5cb S |
364 | if (skb == NULL) { |
365 | error = -ENOMEM; | |
366 | goto err; | |
f078f209 | 367 | } |
f078f209 | 368 | |
797fe5cb S |
369 | bf->bf_mpdu = skb; |
370 | bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, | |
371 | sc->rx.bufsize, | |
372 | DMA_FROM_DEVICE); | |
373 | if (unlikely(dma_mapping_error(sc->dev, | |
374 | bf->bf_buf_addr))) { | |
375 | dev_kfree_skb_any(skb); | |
376 | bf->bf_mpdu = NULL; | |
c46917bb LR |
377 | ath_print(common, ATH_DBG_FATAL, |
378 | "dma_mapping_error() on RX init\n"); | |
797fe5cb S |
379 | error = -ENOMEM; |
380 | goto err; | |
381 | } | |
382 | bf->bf_dmacontext = bf->bf_buf_addr; | |
383 | } | |
384 | sc->rx.rxlink = NULL; | |
f078f209 | 385 | |
797fe5cb | 386 | err: |
f078f209 LR |
387 | if (error) |
388 | ath_rx_cleanup(sc); | |
389 | ||
390 | return error; | |
391 | } | |
392 | ||
f078f209 LR |
393 | void ath_rx_cleanup(struct ath_softc *sc) |
394 | { | |
395 | struct sk_buff *skb; | |
396 | struct ath_buf *bf; | |
397 | ||
b77f483f | 398 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { |
f078f209 | 399 | skb = bf->bf_mpdu; |
051b9191 | 400 | if (skb) { |
797fe5cb S |
401 | dma_unmap_single(sc->dev, bf->bf_buf_addr, |
402 | sc->rx.bufsize, DMA_FROM_DEVICE); | |
f078f209 | 403 | dev_kfree_skb(skb); |
051b9191 | 404 | } |
f078f209 LR |
405 | } |
406 | ||
b77f483f S |
407 | if (sc->rx.rxdma.dd_desc_len != 0) |
408 | ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf); | |
f078f209 LR |
409 | } |
410 | ||
411 | /* | |
412 | * Calculate the receive filter according to the | |
413 | * operating mode and state: | |
414 | * | |
415 | * o always accept unicast, broadcast, and multicast traffic | |
416 | * o maintain current state of phy error reception (the hal | |
417 | * may enable phy error frames for noise immunity work) | |
418 | * o probe request frames are accepted only when operating in | |
419 | * hostap, adhoc, or monitor modes | |
420 | * o enable promiscuous mode according to the interface state | |
421 | * o accept beacons: | |
422 | * - when operating in adhoc mode so the 802.11 layer creates | |
423 | * node table entries for peers, | |
424 | * - when operating in station mode for collecting rssi data when | |
425 | * the station is otherwise quiet, or | |
426 | * - when operating as a repeater so we see repeater-sta beacons | |
427 | * - when scanning | |
428 | */ | |
429 | ||
430 | u32 ath_calcrxfilter(struct ath_softc *sc) | |
431 | { | |
432 | #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR) | |
7dcfdcd9 | 433 | |
f078f209 LR |
434 | u32 rfilt; |
435 | ||
436 | rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE) | |
437 | | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST | |
438 | | ATH9K_RX_FILTER_MCAST; | |
439 | ||
440 | /* If not a STA, enable processing of Probe Requests */ | |
2660b81a | 441 | if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) |
f078f209 LR |
442 | rfilt |= ATH9K_RX_FILTER_PROBEREQ; |
443 | ||
217ba9da JM |
444 | /* |
445 | * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station | |
446 | * mode interface or when in monitor mode. AP mode does not need this | |
447 | * since it receives all in-BSS frames anyway. | |
448 | */ | |
2660b81a | 449 | if (((sc->sc_ah->opmode != NL80211_IFTYPE_AP) && |
b77f483f | 450 | (sc->rx.rxfilter & FIF_PROMISC_IN_BSS)) || |
217ba9da | 451 | (sc->sc_ah->opmode == NL80211_IFTYPE_MONITOR)) |
f078f209 | 452 | rfilt |= ATH9K_RX_FILTER_PROM; |
f078f209 | 453 | |
d42c6b71 S |
454 | if (sc->rx.rxfilter & FIF_CONTROL) |
455 | rfilt |= ATH9K_RX_FILTER_CONTROL; | |
456 | ||
dbaaa147 VT |
457 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) && |
458 | !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)) | |
459 | rfilt |= ATH9K_RX_FILTER_MYBEACON; | |
460 | else | |
f078f209 LR |
461 | rfilt |= ATH9K_RX_FILTER_BEACON; |
462 | ||
66afad01 SB |
463 | if ((AR_SREV_9280_10_OR_LATER(sc->sc_ah) || |
464 | AR_SREV_9285_10_OR_LATER(sc->sc_ah)) && | |
465 | (sc->sc_ah->opmode == NL80211_IFTYPE_AP) && | |
466 | (sc->rx.rxfilter & FIF_PSPOLL)) | |
dbaaa147 | 467 | rfilt |= ATH9K_RX_FILTER_PSPOLL; |
be0418ad | 468 | |
7ea310be S |
469 | if (conf_is_ht(&sc->hw->conf)) |
470 | rfilt |= ATH9K_RX_FILTER_COMP_BAR; | |
471 | ||
5eb6ba83 | 472 | if (sc->sec_wiphy || (sc->rx.rxfilter & FIF_OTHER_BSS)) { |
b93bce2a JM |
473 | /* TODO: only needed if more than one BSSID is in use in |
474 | * station/adhoc mode */ | |
5eb6ba83 JC |
475 | /* The following may also be needed for other older chips */ |
476 | if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160) | |
477 | rfilt |= ATH9K_RX_FILTER_PROM; | |
b93bce2a JM |
478 | rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL; |
479 | } | |
480 | ||
f078f209 | 481 | return rfilt; |
7dcfdcd9 | 482 | |
f078f209 LR |
483 | #undef RX_FILTER_PRESERVE |
484 | } | |
485 | ||
f078f209 LR |
486 | int ath_startrecv(struct ath_softc *sc) |
487 | { | |
cbe61d8a | 488 | struct ath_hw *ah = sc->sc_ah; |
f078f209 LR |
489 | struct ath_buf *bf, *tbf; |
490 | ||
b77f483f S |
491 | spin_lock_bh(&sc->rx.rxbuflock); |
492 | if (list_empty(&sc->rx.rxbuf)) | |
f078f209 LR |
493 | goto start_recv; |
494 | ||
b77f483f S |
495 | sc->rx.rxlink = NULL; |
496 | list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) { | |
f078f209 LR |
497 | ath_rx_buf_link(sc, bf); |
498 | } | |
499 | ||
500 | /* We could have deleted elements so the list may be empty now */ | |
b77f483f | 501 | if (list_empty(&sc->rx.rxbuf)) |
f078f209 LR |
502 | goto start_recv; |
503 | ||
b77f483f | 504 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); |
f078f209 | 505 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); |
be0418ad | 506 | ath9k_hw_rxena(ah); |
f078f209 LR |
507 | |
508 | start_recv: | |
b77f483f | 509 | spin_unlock_bh(&sc->rx.rxbuflock); |
be0418ad S |
510 | ath_opmode_init(sc); |
511 | ath9k_hw_startpcureceive(ah); | |
512 | ||
f078f209 LR |
513 | return 0; |
514 | } | |
515 | ||
f078f209 LR |
516 | bool ath_stoprecv(struct ath_softc *sc) |
517 | { | |
cbe61d8a | 518 | struct ath_hw *ah = sc->sc_ah; |
f078f209 LR |
519 | bool stopped; |
520 | ||
be0418ad S |
521 | ath9k_hw_stoppcurecv(ah); |
522 | ath9k_hw_setrxfilter(ah, 0); | |
523 | stopped = ath9k_hw_stopdmarecv(ah); | |
b77f483f | 524 | sc->rx.rxlink = NULL; |
be0418ad | 525 | |
f078f209 LR |
526 | return stopped; |
527 | } | |
528 | ||
f078f209 LR |
529 | void ath_flushrecv(struct ath_softc *sc) |
530 | { | |
b77f483f | 531 | spin_lock_bh(&sc->rx.rxflushlock); |
98deeea0 | 532 | sc->sc_flags |= SC_OP_RXFLUSH; |
f078f209 | 533 | ath_rx_tasklet(sc, 1); |
98deeea0 | 534 | sc->sc_flags &= ~SC_OP_RXFLUSH; |
b77f483f | 535 | spin_unlock_bh(&sc->rx.rxflushlock); |
f078f209 LR |
536 | } |
537 | ||
cc65965c JM |
538 | static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb) |
539 | { | |
540 | /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */ | |
541 | struct ieee80211_mgmt *mgmt; | |
542 | u8 *pos, *end, id, elen; | |
543 | struct ieee80211_tim_ie *tim; | |
544 | ||
545 | mgmt = (struct ieee80211_mgmt *)skb->data; | |
546 | pos = mgmt->u.beacon.variable; | |
547 | end = skb->data + skb->len; | |
548 | ||
549 | while (pos + 2 < end) { | |
550 | id = *pos++; | |
551 | elen = *pos++; | |
552 | if (pos + elen > end) | |
553 | break; | |
554 | ||
555 | if (id == WLAN_EID_TIM) { | |
556 | if (elen < sizeof(*tim)) | |
557 | break; | |
558 | tim = (struct ieee80211_tim_ie *) pos; | |
559 | if (tim->dtim_count != 0) | |
560 | break; | |
561 | return tim->bitmap_ctrl & 0x01; | |
562 | } | |
563 | ||
564 | pos += elen; | |
565 | } | |
566 | ||
567 | return false; | |
568 | } | |
569 | ||
cc65965c JM |
570 | static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb) |
571 | { | |
572 | struct ieee80211_mgmt *mgmt; | |
1510718d | 573 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
cc65965c JM |
574 | |
575 | if (skb->len < 24 + 8 + 2 + 2) | |
576 | return; | |
577 | ||
578 | mgmt = (struct ieee80211_mgmt *)skb->data; | |
1510718d | 579 | if (memcmp(common->curbssid, mgmt->bssid, ETH_ALEN) != 0) |
cc65965c JM |
580 | return; /* not from our current AP */ |
581 | ||
293dc5df GJ |
582 | sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON; |
583 | ||
ccdfeab6 JM |
584 | if (sc->sc_flags & SC_OP_BEACON_SYNC) { |
585 | sc->sc_flags &= ~SC_OP_BEACON_SYNC; | |
c46917bb LR |
586 | ath_print(common, ATH_DBG_PS, |
587 | "Reconfigure Beacon timers based on " | |
588 | "timestamp from the AP\n"); | |
ccdfeab6 JM |
589 | ath_beacon_config(sc, NULL); |
590 | } | |
591 | ||
cc65965c JM |
592 | if (ath_beacon_dtim_pending_cab(skb)) { |
593 | /* | |
594 | * Remain awake waiting for buffered broadcast/multicast | |
58f5fffd GJ |
595 | * frames. If the last broadcast/multicast frame is not |
596 | * received properly, the next beacon frame will work as | |
597 | * a backup trigger for returning into NETWORK SLEEP state, | |
598 | * so we are waiting for it as well. | |
cc65965c | 599 | */ |
c46917bb LR |
600 | ath_print(common, ATH_DBG_PS, "Received DTIM beacon indicating " |
601 | "buffered broadcast/multicast frame(s)\n"); | |
58f5fffd | 602 | sc->sc_flags |= SC_OP_WAIT_FOR_CAB | SC_OP_WAIT_FOR_BEACON; |
cc65965c JM |
603 | return; |
604 | } | |
605 | ||
606 | if (sc->sc_flags & SC_OP_WAIT_FOR_CAB) { | |
607 | /* | |
608 | * This can happen if a broadcast frame is dropped or the AP | |
609 | * fails to send a frame indicating that all CAB frames have | |
610 | * been delivered. | |
611 | */ | |
293dc5df | 612 | sc->sc_flags &= ~SC_OP_WAIT_FOR_CAB; |
c46917bb LR |
613 | ath_print(common, ATH_DBG_PS, |
614 | "PS wait for CAB frames timed out\n"); | |
cc65965c | 615 | } |
cc65965c JM |
616 | } |
617 | ||
618 | static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb) | |
619 | { | |
620 | struct ieee80211_hdr *hdr; | |
c46917bb | 621 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
cc65965c JM |
622 | |
623 | hdr = (struct ieee80211_hdr *)skb->data; | |
624 | ||
625 | /* Process Beacon and CAB receive in PS state */ | |
9a23f9ca JM |
626 | if ((sc->sc_flags & SC_OP_WAIT_FOR_BEACON) && |
627 | ieee80211_is_beacon(hdr->frame_control)) | |
cc65965c JM |
628 | ath_rx_ps_beacon(sc, skb); |
629 | else if ((sc->sc_flags & SC_OP_WAIT_FOR_CAB) && | |
630 | (ieee80211_is_data(hdr->frame_control) || | |
631 | ieee80211_is_action(hdr->frame_control)) && | |
632 | is_multicast_ether_addr(hdr->addr1) && | |
633 | !ieee80211_has_moredata(hdr->frame_control)) { | |
cc65965c JM |
634 | /* |
635 | * No more broadcast/multicast frames to be received at this | |
636 | * point. | |
637 | */ | |
293dc5df | 638 | sc->sc_flags &= ~SC_OP_WAIT_FOR_CAB; |
c46917bb LR |
639 | ath_print(common, ATH_DBG_PS, |
640 | "All PS CAB frames received, back to sleep\n"); | |
9a23f9ca JM |
641 | } else if ((sc->sc_flags & SC_OP_WAIT_FOR_PSPOLL_DATA) && |
642 | !is_multicast_ether_addr(hdr->addr1) && | |
643 | !ieee80211_has_morefrags(hdr->frame_control)) { | |
644 | sc->sc_flags &= ~SC_OP_WAIT_FOR_PSPOLL_DATA; | |
c46917bb LR |
645 | ath_print(common, ATH_DBG_PS, |
646 | "Going back to sleep after having received " | |
647 | "PS-Poll data (0x%x)\n", | |
9a23f9ca JM |
648 | sc->sc_flags & (SC_OP_WAIT_FOR_BEACON | |
649 | SC_OP_WAIT_FOR_CAB | | |
650 | SC_OP_WAIT_FOR_PSPOLL_DATA | | |
651 | SC_OP_WAIT_FOR_TX_ACK)); | |
cc65965c JM |
652 | } |
653 | } | |
654 | ||
b4afffc0 LR |
655 | static void ath_rx_send_to_mac80211(struct ieee80211_hw *hw, |
656 | struct ath_softc *sc, struct sk_buff *skb, | |
9d64a3cf JM |
657 | struct ieee80211_rx_status *rx_status) |
658 | { | |
659 | struct ieee80211_hdr *hdr; | |
660 | ||
661 | hdr = (struct ieee80211_hdr *)skb->data; | |
662 | ||
663 | /* Send the frame to mac80211 */ | |
664 | if (is_multicast_ether_addr(hdr->addr1)) { | |
665 | int i; | |
666 | /* | |
667 | * Deliver broadcast/multicast frames to all suitable | |
668 | * virtual wiphys. | |
669 | */ | |
670 | /* TODO: filter based on channel configuration */ | |
671 | for (i = 0; i < sc->num_sec_wiphy; i++) { | |
672 | struct ath_wiphy *aphy = sc->sec_wiphy[i]; | |
673 | struct sk_buff *nskb; | |
674 | if (aphy == NULL) | |
675 | continue; | |
676 | nskb = skb_copy(skb, GFP_ATOMIC); | |
f1d58c25 JB |
677 | if (nskb) { |
678 | memcpy(IEEE80211_SKB_RXCB(nskb), rx_status, | |
679 | sizeof(*rx_status)); | |
680 | ieee80211_rx(aphy->hw, nskb); | |
681 | } | |
9d64a3cf | 682 | } |
f1d58c25 JB |
683 | memcpy(IEEE80211_SKB_RXCB(skb), rx_status, sizeof(*rx_status)); |
684 | ieee80211_rx(sc->hw, skb); | |
9d64a3cf JM |
685 | } else { |
686 | /* Deliver unicast frames based on receiver address */ | |
f1d58c25 | 687 | memcpy(IEEE80211_SKB_RXCB(skb), rx_status, sizeof(*rx_status)); |
b4afffc0 | 688 | ieee80211_rx(hw, skb); |
9d64a3cf JM |
689 | } |
690 | } | |
691 | ||
f078f209 LR |
692 | int ath_rx_tasklet(struct ath_softc *sc, int flush) |
693 | { | |
694 | #define PA2DESC(_sc, _pa) \ | |
b77f483f S |
695 | ((struct ath_desc *)((caddr_t)(_sc)->rx.rxdma.dd_desc + \ |
696 | ((_pa) - (_sc)->rx.rxdma.dd_desc_paddr))) | |
f078f209 | 697 | |
be0418ad | 698 | struct ath_buf *bf; |
f078f209 | 699 | struct ath_desc *ds; |
26ab2645 | 700 | struct ath_rx_status *rx_stats; |
cb71d9ba | 701 | struct sk_buff *skb = NULL, *requeue_skb; |
be0418ad | 702 | struct ieee80211_rx_status rx_status; |
cbe61d8a | 703 | struct ath_hw *ah = sc->sc_ah; |
27c51f1a | 704 | struct ath_common *common = ath9k_hw_common(ah); |
b4afffc0 LR |
705 | /* |
706 | * The hw can techncically differ from common->hw when using ath9k | |
707 | * virtual wiphy so to account for that we iterate over the active | |
708 | * wiphys and find the appropriate wiphy and therefore hw. | |
709 | */ | |
710 | struct ieee80211_hw *hw = NULL; | |
be0418ad S |
711 | struct ieee80211_hdr *hdr; |
712 | int hdrlen, padsize, retval; | |
713 | bool decrypt_error = false; | |
714 | u8 keyix; | |
853da11b | 715 | __le16 fc; |
be0418ad | 716 | |
b77f483f | 717 | spin_lock_bh(&sc->rx.rxbuflock); |
f078f209 LR |
718 | |
719 | do { | |
720 | /* If handling rx interrupt and flush is in progress => exit */ | |
98deeea0 | 721 | if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0)) |
f078f209 LR |
722 | break; |
723 | ||
b77f483f S |
724 | if (list_empty(&sc->rx.rxbuf)) { |
725 | sc->rx.rxlink = NULL; | |
f078f209 LR |
726 | break; |
727 | } | |
728 | ||
b77f483f | 729 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); |
f078f209 | 730 | ds = bf->bf_desc; |
f078f209 LR |
731 | |
732 | /* | |
733 | * Must provide the virtual address of the current | |
734 | * descriptor, the physical address, and the virtual | |
735 | * address of the next descriptor in the h/w chain. | |
736 | * This allows the HAL to look ahead to see if the | |
737 | * hardware is done with a descriptor by checking the | |
738 | * done bit in the following descriptor and the address | |
739 | * of the current descriptor the DMA engine is working | |
740 | * on. All this is necessary because of our use of | |
741 | * a self-linked list to avoid rx overruns. | |
742 | */ | |
be0418ad | 743 | retval = ath9k_hw_rxprocdesc(ah, ds, |
f078f209 LR |
744 | bf->bf_daddr, |
745 | PA2DESC(sc, ds->ds_link), | |
746 | 0); | |
747 | if (retval == -EINPROGRESS) { | |
748 | struct ath_buf *tbf; | |
749 | struct ath_desc *tds; | |
750 | ||
b77f483f S |
751 | if (list_is_last(&bf->list, &sc->rx.rxbuf)) { |
752 | sc->rx.rxlink = NULL; | |
f078f209 LR |
753 | break; |
754 | } | |
755 | ||
756 | tbf = list_entry(bf->list.next, struct ath_buf, list); | |
757 | ||
758 | /* | |
759 | * On some hardware the descriptor status words could | |
760 | * get corrupted, including the done bit. Because of | |
761 | * this, check if the next descriptor's done bit is | |
762 | * set or not. | |
763 | * | |
764 | * If the next descriptor's done bit is set, the current | |
765 | * descriptor has been corrupted. Force s/w to discard | |
766 | * this descriptor and continue... | |
767 | */ | |
768 | ||
769 | tds = tbf->bf_desc; | |
be0418ad S |
770 | retval = ath9k_hw_rxprocdesc(ah, tds, tbf->bf_daddr, |
771 | PA2DESC(sc, tds->ds_link), 0); | |
f078f209 | 772 | if (retval == -EINPROGRESS) { |
f078f209 LR |
773 | break; |
774 | } | |
775 | } | |
776 | ||
f078f209 | 777 | skb = bf->bf_mpdu; |
be0418ad | 778 | if (!skb) |
f078f209 | 779 | continue; |
f078f209 | 780 | |
9bf9fca8 VT |
781 | /* |
782 | * Synchronize the DMA transfer with CPU before | |
783 | * 1. accessing the frame | |
784 | * 2. requeueing the same buffer to h/w | |
785 | */ | |
7da3c55c | 786 | dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr, |
9bf9fca8 | 787 | sc->rx.bufsize, |
7da3c55c | 788 | DMA_FROM_DEVICE); |
9bf9fca8 | 789 | |
b4afffc0 LR |
790 | hdr = (struct ieee80211_hdr *) skb->data; |
791 | hw = ath_get_virt_hw(sc, hdr); | |
26ab2645 | 792 | rx_stats = &ds->ds_rxstat; |
b4afffc0 | 793 | |
f078f209 | 794 | /* |
be0418ad S |
795 | * If we're asked to flush receive queue, directly |
796 | * chain it back at the queue without processing it. | |
f078f209 | 797 | */ |
be0418ad | 798 | if (flush) |
cb71d9ba | 799 | goto requeue; |
f078f209 | 800 | |
26ab2645 | 801 | if (!rx_stats->rs_datalen) |
cb71d9ba | 802 | goto requeue; |
f078f209 | 803 | |
be0418ad | 804 | /* The status portion of the descriptor could get corrupted. */ |
26ab2645 | 805 | if (sc->rx.bufsize < rx_stats->rs_datalen) |
cb71d9ba | 806 | goto requeue; |
f078f209 | 807 | |
712c13a8 LR |
808 | if (!ath_rx_prepare(common, hw, skb, rx_stats, |
809 | &rx_status, &decrypt_error)) | |
cb71d9ba LR |
810 | goto requeue; |
811 | ||
812 | /* Ensure we always have an skb to requeue once we are done | |
813 | * processing the current buffer's skb */ | |
27c51f1a | 814 | requeue_skb = ath_rxbuf_alloc(common, sc->rx.bufsize, GFP_ATOMIC); |
cb71d9ba LR |
815 | |
816 | /* If there is no memory we ignore the current RX'd frame, | |
817 | * tell hardware it can give us a new frame using the old | |
b77f483f | 818 | * skb and put it at the tail of the sc->rx.rxbuf list for |
cb71d9ba LR |
819 | * processing. */ |
820 | if (!requeue_skb) | |
821 | goto requeue; | |
f078f209 | 822 | |
9bf9fca8 | 823 | /* Unmap the frame */ |
7da3c55c | 824 | dma_unmap_single(sc->dev, bf->bf_buf_addr, |
b77f483f | 825 | sc->rx.bufsize, |
7da3c55c | 826 | DMA_FROM_DEVICE); |
f078f209 | 827 | |
26ab2645 | 828 | skb_put(skb, rx_stats->rs_datalen); |
be0418ad S |
829 | |
830 | /* see if any padding is done by the hw and remove it */ | |
be0418ad | 831 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); |
853da11b | 832 | fc = hdr->frame_control; |
be0418ad | 833 | |
9c5f89b3 JM |
834 | /* The MAC header is padded to have 32-bit boundary if the |
835 | * packet payload is non-zero. The general calculation for | |
836 | * padsize would take into account odd header lengths: | |
837 | * padsize = (4 - hdrlen % 4) % 4; However, since only | |
838 | * even-length headers are used, padding can only be 0 or 2 | |
839 | * bytes and we can optimize this a bit. In addition, we must | |
840 | * not try to remove padding from short control frames that do | |
841 | * not have payload. */ | |
842 | padsize = hdrlen & 3; | |
843 | if (padsize && hdrlen >= 24) { | |
be0418ad S |
844 | memmove(skb->data + padsize, skb->data, hdrlen); |
845 | skb_pull(skb, padsize); | |
f078f209 LR |
846 | } |
847 | ||
26ab2645 | 848 | keyix = rx_stats->rs_keyix; |
f078f209 | 849 | |
be0418ad S |
850 | if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error) { |
851 | rx_status.flag |= RX_FLAG_DECRYPTED; | |
9d64a3cf | 852 | } else if (ieee80211_has_protected(fc) |
be0418ad S |
853 | && !decrypt_error && skb->len >= hdrlen + 4) { |
854 | keyix = skb->data[hdrlen + 3] >> 6; | |
855 | ||
17d7904d | 856 | if (test_bit(keyix, sc->keymap)) |
be0418ad S |
857 | rx_status.flag |= RX_FLAG_DECRYPTED; |
858 | } | |
0ced0e17 JM |
859 | if (ah->sw_mgmt_crypto && |
860 | (rx_status.flag & RX_FLAG_DECRYPTED) && | |
9d64a3cf | 861 | ieee80211_is_mgmt(fc)) { |
0ced0e17 JM |
862 | /* Use software decrypt for management frames. */ |
863 | rx_status.flag &= ~RX_FLAG_DECRYPTED; | |
864 | } | |
be0418ad | 865 | |
cb71d9ba LR |
866 | /* We will now give hardware our shiny new allocated skb */ |
867 | bf->bf_mpdu = requeue_skb; | |
7da3c55c | 868 | bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data, |
b77f483f | 869 | sc->rx.bufsize, |
7da3c55c GJ |
870 | DMA_FROM_DEVICE); |
871 | if (unlikely(dma_mapping_error(sc->dev, | |
f8316df1 LR |
872 | bf->bf_buf_addr))) { |
873 | dev_kfree_skb_any(requeue_skb); | |
874 | bf->bf_mpdu = NULL; | |
c46917bb LR |
875 | ath_print(common, ATH_DBG_FATAL, |
876 | "dma_mapping_error() on RX\n"); | |
b4afffc0 | 877 | ath_rx_send_to_mac80211(hw, sc, skb, &rx_status); |
f8316df1 LR |
878 | break; |
879 | } | |
cb71d9ba | 880 | bf->bf_dmacontext = bf->bf_buf_addr; |
f078f209 LR |
881 | |
882 | /* | |
883 | * change the default rx antenna if rx diversity chooses the | |
884 | * other antenna 3 times in a row. | |
885 | */ | |
b77f483f S |
886 | if (sc->rx.defant != ds->ds_rxstat.rs_antenna) { |
887 | if (++sc->rx.rxotherant >= 3) | |
26ab2645 | 888 | ath_setdefantenna(sc, rx_stats->rs_antenna); |
f078f209 | 889 | } else { |
b77f483f | 890 | sc->rx.rxotherant = 0; |
f078f209 | 891 | } |
3cbb5dd7 | 892 | |
9a23f9ca | 893 | if (unlikely(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON | |
f0e9a860 | 894 | SC_OP_WAIT_FOR_CAB | |
9a23f9ca | 895 | SC_OP_WAIT_FOR_PSPOLL_DATA))) |
cc65965c JM |
896 | ath_rx_ps(sc, skb); |
897 | ||
b4afffc0 | 898 | ath_rx_send_to_mac80211(hw, sc, skb, &rx_status); |
cc65965c | 899 | |
cb71d9ba | 900 | requeue: |
b77f483f | 901 | list_move_tail(&bf->list, &sc->rx.rxbuf); |
cb71d9ba | 902 | ath_rx_buf_link(sc, bf); |
be0418ad S |
903 | } while (1); |
904 | ||
b77f483f | 905 | spin_unlock_bh(&sc->rx.rxbuflock); |
f078f209 LR |
906 | |
907 | return 0; | |
908 | #undef PA2DESC | |
909 | } |