Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
394cf0a1 | 17 | #include "ath9k.h" |
f078f209 | 18 | |
bce048d7 JM |
19 | static struct ieee80211_hw * ath_get_virt_hw(struct ath_softc *sc, |
20 | struct ieee80211_hdr *hdr) | |
21 | { | |
c52f33d0 JM |
22 | struct ieee80211_hw *hw = sc->pri_wiphy->hw; |
23 | int i; | |
24 | ||
25 | spin_lock_bh(&sc->wiphy_lock); | |
26 | for (i = 0; i < sc->num_sec_wiphy; i++) { | |
27 | struct ath_wiphy *aphy = sc->sec_wiphy[i]; | |
28 | if (aphy == NULL) | |
29 | continue; | |
30 | if (compare_ether_addr(hdr->addr1, aphy->hw->wiphy->perm_addr) | |
31 | == 0) { | |
32 | hw = aphy->hw; | |
33 | break; | |
34 | } | |
35 | } | |
36 | spin_unlock_bh(&sc->wiphy_lock); | |
37 | return hw; | |
bce048d7 JM |
38 | } |
39 | ||
f078f209 LR |
40 | /* |
41 | * Setup and link descriptors. | |
42 | * | |
43 | * 11N: we can no longer afford to self link the last descriptor. | |
44 | * MAC acknowledges BA status as long as it copies frames to host | |
45 | * buffer (or rx fifo). This can incorrectly acknowledge packets | |
46 | * to a sender if last desc is self-linked. | |
f078f209 | 47 | */ |
f078f209 LR |
48 | static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf) |
49 | { | |
cbe61d8a | 50 | struct ath_hw *ah = sc->sc_ah; |
cc861f74 | 51 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 LR |
52 | struct ath_desc *ds; |
53 | struct sk_buff *skb; | |
54 | ||
55 | ATH_RXBUF_RESET(bf); | |
56 | ||
57 | ds = bf->bf_desc; | |
be0418ad | 58 | ds->ds_link = 0; /* link to null */ |
f078f209 LR |
59 | ds->ds_data = bf->bf_buf_addr; |
60 | ||
be0418ad | 61 | /* virtual addr of the beginning of the buffer. */ |
f078f209 | 62 | skb = bf->bf_mpdu; |
9680e8a3 | 63 | BUG_ON(skb == NULL); |
f078f209 LR |
64 | ds->ds_vdata = skb->data; |
65 | ||
cc861f74 LR |
66 | /* |
67 | * setup rx descriptors. The rx_bufsize here tells the hardware | |
b4b6cda2 | 68 | * how much data it can DMA to us and that we are prepared |
cc861f74 LR |
69 | * to process |
70 | */ | |
b77f483f | 71 | ath9k_hw_setuprxdesc(ah, ds, |
cc861f74 | 72 | common->rx_bufsize, |
f078f209 LR |
73 | 0); |
74 | ||
b77f483f | 75 | if (sc->rx.rxlink == NULL) |
f078f209 LR |
76 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); |
77 | else | |
b77f483f | 78 | *sc->rx.rxlink = bf->bf_daddr; |
f078f209 | 79 | |
b77f483f | 80 | sc->rx.rxlink = &ds->ds_link; |
f078f209 LR |
81 | ath9k_hw_rxena(ah); |
82 | } | |
83 | ||
ff37e337 S |
84 | static void ath_setdefantenna(struct ath_softc *sc, u32 antenna) |
85 | { | |
86 | /* XXX block beacon interrupts */ | |
87 | ath9k_hw_setantenna(sc->sc_ah, antenna); | |
b77f483f S |
88 | sc->rx.defant = antenna; |
89 | sc->rx.rxotherant = 0; | |
ff37e337 S |
90 | } |
91 | ||
207e9685 LR |
92 | /* Assumes you've already done the endian to CPU conversion */ |
93 | static bool ath9k_rx_accept(struct ath_common *common, | |
94 | struct sk_buff *skb, | |
95 | struct ieee80211_rx_status *rxs, | |
96 | struct ath_rx_status *rx_stats, | |
97 | bool *decrypt_error) | |
f078f209 | 98 | { |
712c13a8 | 99 | struct ath_hw *ah = common->ah; |
be0418ad | 100 | struct ieee80211_hdr *hdr; |
be0418ad | 101 | __le16 fc; |
a59b5a5e | 102 | |
207e9685 | 103 | hdr = (struct ieee80211_hdr *) skb->data; |
be0418ad | 104 | fc = hdr->frame_control; |
be0418ad | 105 | |
0a45da76 LR |
106 | if (!rx_stats->rs_datalen) |
107 | return false; | |
2c74aa4d LR |
108 | /* |
109 | * rs_status follows rs_datalen so if rs_datalen is too large | |
110 | * we can take a hint that hardware corrupted it, so ignore | |
111 | * those frames. | |
112 | */ | |
113 | if (rx_stats->rs_datalen > common->rx_bufsize) | |
114 | return false; | |
0a45da76 | 115 | |
26ab2645 | 116 | if (rx_stats->rs_more) { |
be0418ad S |
117 | /* |
118 | * Frame spans multiple descriptors; this cannot happen yet | |
119 | * as we don't support jumbograms. If not in monitor mode, | |
120 | * discard the frame. Enable this if you want to see | |
121 | * error frames in Monitor mode. | |
122 | */ | |
712c13a8 | 123 | if (ah->opmode != NL80211_IFTYPE_MONITOR) |
207e9685 | 124 | return false; |
26ab2645 LR |
125 | } else if (rx_stats->rs_status != 0) { |
126 | if (rx_stats->rs_status & ATH9K_RXERR_CRC) | |
207e9685 | 127 | rxs->flag |= RX_FLAG_FAILED_FCS_CRC; |
26ab2645 | 128 | if (rx_stats->rs_status & ATH9K_RXERR_PHY) |
207e9685 | 129 | return false; |
f078f209 | 130 | |
26ab2645 | 131 | if (rx_stats->rs_status & ATH9K_RXERR_DECRYPT) { |
be0418ad | 132 | *decrypt_error = true; |
26ab2645 | 133 | } else if (rx_stats->rs_status & ATH9K_RXERR_MIC) { |
be0418ad S |
134 | if (ieee80211_is_ctl(fc)) |
135 | /* | |
136 | * Sometimes, we get invalid | |
137 | * MIC failures on valid control frames. | |
138 | * Remove these mic errors. | |
139 | */ | |
26ab2645 | 140 | rx_stats->rs_status &= ~ATH9K_RXERR_MIC; |
be0418ad | 141 | else |
207e9685 | 142 | rxs->flag |= RX_FLAG_MMIC_ERROR; |
be0418ad S |
143 | } |
144 | /* | |
145 | * Reject error frames with the exception of | |
146 | * decryption and MIC failures. For monitor mode, | |
147 | * we also ignore the CRC error. | |
148 | */ | |
712c13a8 | 149 | if (ah->opmode == NL80211_IFTYPE_MONITOR) { |
26ab2645 | 150 | if (rx_stats->rs_status & |
be0418ad S |
151 | ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC | |
152 | ATH9K_RXERR_CRC)) | |
207e9685 | 153 | return false; |
be0418ad | 154 | } else { |
26ab2645 | 155 | if (rx_stats->rs_status & |
be0418ad | 156 | ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) { |
207e9685 | 157 | return false; |
be0418ad S |
158 | } |
159 | } | |
f078f209 | 160 | } |
207e9685 LR |
161 | return true; |
162 | } | |
163 | ||
9878841e LR |
164 | static u8 ath9k_process_rate(struct ath_common *common, |
165 | struct ieee80211_hw *hw, | |
166 | struct ath_rx_status *rx_stats, | |
167 | struct ieee80211_rx_status *rxs, | |
168 | struct sk_buff *skb) | |
169 | { | |
170 | struct ieee80211_supported_band *sband; | |
171 | enum ieee80211_band band; | |
172 | unsigned int i = 0; | |
173 | ||
174 | band = hw->conf.channel->band; | |
175 | sband = hw->wiphy->bands[band]; | |
176 | ||
177 | if (rx_stats->rs_rate & 0x80) { | |
178 | /* HT rate */ | |
179 | rxs->flag |= RX_FLAG_HT; | |
180 | if (rx_stats->rs_flags & ATH9K_RX_2040) | |
181 | rxs->flag |= RX_FLAG_40MHZ; | |
182 | if (rx_stats->rs_flags & ATH9K_RX_GI) | |
183 | rxs->flag |= RX_FLAG_SHORT_GI; | |
184 | return rx_stats->rs_rate & 0x7f; | |
185 | } | |
186 | ||
187 | for (i = 0; i < sband->n_bitrates; i++) { | |
188 | if (sband->bitrates[i].hw_value == rx_stats->rs_rate) | |
189 | return i; | |
190 | if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) { | |
191 | rxs->flag |= RX_FLAG_SHORTPRE; | |
192 | return i; | |
193 | } | |
194 | } | |
195 | ||
196 | /* No valid hardware bitrate found -- we should not get here */ | |
197 | ath_print(common, ATH_DBG_XMIT, "unsupported hw bitrate detected " | |
198 | "0x%02x using 1 Mbit\n", rx_stats->rs_rate); | |
199 | if ((common->debug_mask & ATH_DBG_XMIT)) | |
200 | print_hex_dump_bytes("", DUMP_PREFIX_NONE, skb->data, skb->len); | |
201 | ||
202 | return 0; | |
203 | } | |
204 | ||
21b22738 LR |
205 | /* |
206 | * Theory for reporting quality: | |
207 | * | |
208 | * At a hardware RSSI of 45 you will be able to use MCS 7 reliably. | |
209 | * At a hardware RSSI of 45 you will be able to use MCS 15 reliably. | |
210 | * At a hardware RSSI of 35 you should be able use 54 Mbps reliably. | |
211 | * | |
212 | * MCS 7 is the highets MCS index usable by a 1-stream device. | |
213 | * MCS 15 is the highest MCS index usable by a 2-stream device. | |
214 | * | |
215 | * All ath9k devices are either 1-stream or 2-stream. | |
216 | * | |
217 | * How many bars you see is derived from the qual reporting. | |
218 | * | |
219 | * A more elaborate scheme can be used here but it requires tables | |
220 | * of SNR/throughput for each possible mode used. For the MCS table | |
221 | * you can refer to the wireless wiki: | |
222 | * | |
223 | * http://wireless.kernel.org/en/developers/Documentation/ieee80211/802.11n | |
224 | * | |
225 | */ | |
226 | static int ath9k_compute_qual(struct ieee80211_hw *hw, | |
227 | struct ath_rx_status *rx_stats) | |
228 | { | |
229 | int qual; | |
230 | ||
231 | if (conf_is_ht(&hw->conf)) | |
232 | qual = rx_stats->rs_rssi * 100 / 45; | |
233 | else | |
234 | qual = rx_stats->rs_rssi * 100 / 35; | |
235 | ||
236 | /* | |
237 | * rssi can be more than 45 though, anything above that | |
238 | * should be considered at 100% | |
239 | */ | |
240 | if (qual > 100) | |
241 | qual = 100; | |
242 | ||
243 | return qual; | |
244 | } | |
245 | ||
dbfc22df LR |
246 | static void ath9k_process_rssi(struct ath_common *common, |
247 | struct ieee80211_hw *hw, | |
248 | struct sk_buff *skb, | |
249 | struct ath_rx_status *rx_stats) | |
207e9685 LR |
250 | { |
251 | struct ath_hw *ah = common->ah; | |
207e9685 | 252 | struct ieee80211_sta *sta; |
dbfc22df | 253 | struct ieee80211_hdr *hdr; |
207e9685 LR |
254 | struct ath_node *an; |
255 | int last_rssi = ATH_RSSI_DUMMY_MARKER; | |
dbfc22df | 256 | __le16 fc; |
207e9685 LR |
257 | |
258 | hdr = (struct ieee80211_hdr *)skb->data; | |
259 | fc = hdr->frame_control; | |
be0418ad | 260 | |
a59b5a5e | 261 | rcu_read_lock(); |
5ed176e1 | 262 | /* XXX: use ieee80211_find_sta! */ |
cee71d6c | 263 | sta = ieee80211_find_sta_by_hw(hw, hdr->addr2); |
a59b5a5e SB |
264 | if (sta) { |
265 | an = (struct ath_node *) sta->drv_priv; | |
26ab2645 LR |
266 | if (rx_stats->rs_rssi != ATH9K_RSSI_BAD && |
267 | !rx_stats->rs_moreaggr) | |
268 | ATH_RSSI_LPF(an->last_rssi, rx_stats->rs_rssi); | |
a59b5a5e SB |
269 | last_rssi = an->last_rssi; |
270 | } | |
271 | rcu_read_unlock(); | |
272 | ||
273 | if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER)) | |
26ab2645 LR |
274 | rx_stats->rs_rssi = ATH_EP_RND(last_rssi, |
275 | ATH_RSSI_EP_MULTIPLIER); | |
276 | if (rx_stats->rs_rssi < 0) | |
277 | rx_stats->rs_rssi = 0; | |
278 | else if (rx_stats->rs_rssi > 127) | |
279 | rx_stats->rs_rssi = 127; | |
a59b5a5e | 280 | |
5e32b1ed S |
281 | /* Update Beacon RSSI, this is used by ANI. */ |
282 | if (ieee80211_is_beacon(fc)) | |
712c13a8 | 283 | ah->stats.avgbrssi = rx_stats->rs_rssi; |
dbfc22df LR |
284 | } |
285 | ||
286 | /* | |
287 | * For Decrypt or Demic errors, we only mark packet status here and always push | |
288 | * up the frame up to let mac80211 handle the actual error case, be it no | |
289 | * decryption key or real decryption error. This let us keep statistics there. | |
290 | */ | |
1e875e9f LR |
291 | static int ath9k_rx_skb_preprocess(struct ath_common *common, |
292 | struct ieee80211_hw *hw, | |
293 | struct sk_buff *skb, | |
294 | struct ath_rx_status *rx_stats, | |
295 | struct ieee80211_rx_status *rx_status, | |
296 | bool *decrypt_error) | |
dbfc22df LR |
297 | { |
298 | struct ath_hw *ah = common->ah; | |
299 | ||
dbfc22df | 300 | if (!ath9k_rx_accept(common, skb, rx_status, rx_stats, decrypt_error)) |
1e875e9f | 301 | return -EINVAL; |
dbfc22df LR |
302 | |
303 | ath9k_process_rssi(common, hw, skb, rx_stats); | |
5e32b1ed | 304 | |
9878841e LR |
305 | rx_status->rate_idx = ath9k_process_rate(common, hw, |
306 | rx_stats, rx_status, skb); | |
712c13a8 | 307 | rx_status->mactime = ath9k_hw_extend_tsf(ah, rx_stats->rs_tstamp); |
bce048d7 JM |
308 | rx_status->band = hw->conf.channel->band; |
309 | rx_status->freq = hw->conf.channel->center_freq; | |
3d536acf | 310 | rx_status->noise = common->ani.noise_floor; |
26ab2645 LR |
311 | rx_status->signal = ATH_DEFAULT_NOISE_FLOOR + rx_stats->rs_rssi; |
312 | rx_status->antenna = rx_stats->rs_antenna; | |
21b22738 | 313 | rx_status->qual = ath9k_compute_qual(hw, rx_stats); |
be0418ad S |
314 | rx_status->flag |= RX_FLAG_TSFT; |
315 | ||
be0418ad | 316 | return 0; |
f078f209 LR |
317 | } |
318 | ||
319 | static void ath_opmode_init(struct ath_softc *sc) | |
320 | { | |
cbe61d8a | 321 | struct ath_hw *ah = sc->sc_ah; |
1510718d LR |
322 | struct ath_common *common = ath9k_hw_common(ah); |
323 | ||
f078f209 LR |
324 | u32 rfilt, mfilt[2]; |
325 | ||
326 | /* configure rx filter */ | |
327 | rfilt = ath_calcrxfilter(sc); | |
328 | ath9k_hw_setrxfilter(ah, rfilt); | |
329 | ||
330 | /* configure bssid mask */ | |
2660b81a | 331 | if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) |
13b81559 | 332 | ath_hw_setbssidmask(common); |
f078f209 LR |
333 | |
334 | /* configure operational mode */ | |
335 | ath9k_hw_setopmode(ah); | |
336 | ||
337 | /* Handle any link-level address change. */ | |
1510718d | 338 | ath9k_hw_setmac(ah, common->macaddr); |
f078f209 LR |
339 | |
340 | /* calculate and install multicast filter */ | |
341 | mfilt[0] = mfilt[1] = ~0; | |
f078f209 | 342 | ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]); |
f078f209 LR |
343 | } |
344 | ||
345 | int ath_rx_init(struct ath_softc *sc, int nbufs) | |
346 | { | |
27c51f1a | 347 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
f078f209 LR |
348 | struct sk_buff *skb; |
349 | struct ath_buf *bf; | |
350 | int error = 0; | |
351 | ||
797fe5cb S |
352 | spin_lock_init(&sc->rx.rxflushlock); |
353 | sc->sc_flags &= ~SC_OP_RXFLUSH; | |
354 | spin_lock_init(&sc->rx.rxbuflock); | |
f078f209 | 355 | |
cc861f74 LR |
356 | common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN, |
357 | min(common->cachelsz, (u16)64)); | |
f078f209 | 358 | |
c46917bb | 359 | ath_print(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n", |
cc861f74 | 360 | common->cachelsz, common->rx_bufsize); |
f078f209 | 361 | |
797fe5cb | 362 | /* Initialize rx descriptors */ |
f078f209 | 363 | |
797fe5cb S |
364 | error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf, |
365 | "rx", nbufs, 1); | |
366 | if (error != 0) { | |
c46917bb LR |
367 | ath_print(common, ATH_DBG_FATAL, |
368 | "failed to allocate rx descriptors: %d\n", error); | |
797fe5cb S |
369 | goto err; |
370 | } | |
f078f209 | 371 | |
797fe5cb | 372 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { |
cc861f74 | 373 | skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL); |
797fe5cb S |
374 | if (skb == NULL) { |
375 | error = -ENOMEM; | |
376 | goto err; | |
f078f209 | 377 | } |
f078f209 | 378 | |
797fe5cb S |
379 | bf->bf_mpdu = skb; |
380 | bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, | |
cc861f74 | 381 | common->rx_bufsize, |
797fe5cb S |
382 | DMA_FROM_DEVICE); |
383 | if (unlikely(dma_mapping_error(sc->dev, | |
384 | bf->bf_buf_addr))) { | |
385 | dev_kfree_skb_any(skb); | |
386 | bf->bf_mpdu = NULL; | |
c46917bb LR |
387 | ath_print(common, ATH_DBG_FATAL, |
388 | "dma_mapping_error() on RX init\n"); | |
797fe5cb S |
389 | error = -ENOMEM; |
390 | goto err; | |
391 | } | |
392 | bf->bf_dmacontext = bf->bf_buf_addr; | |
393 | } | |
394 | sc->rx.rxlink = NULL; | |
f078f209 | 395 | |
797fe5cb | 396 | err: |
f078f209 LR |
397 | if (error) |
398 | ath_rx_cleanup(sc); | |
399 | ||
400 | return error; | |
401 | } | |
402 | ||
f078f209 LR |
403 | void ath_rx_cleanup(struct ath_softc *sc) |
404 | { | |
cc861f74 LR |
405 | struct ath_hw *ah = sc->sc_ah; |
406 | struct ath_common *common = ath9k_hw_common(ah); | |
f078f209 LR |
407 | struct sk_buff *skb; |
408 | struct ath_buf *bf; | |
409 | ||
b77f483f | 410 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { |
f078f209 | 411 | skb = bf->bf_mpdu; |
051b9191 | 412 | if (skb) { |
797fe5cb | 413 | dma_unmap_single(sc->dev, bf->bf_buf_addr, |
cc861f74 | 414 | common->rx_bufsize, DMA_FROM_DEVICE); |
f078f209 | 415 | dev_kfree_skb(skb); |
051b9191 | 416 | } |
f078f209 LR |
417 | } |
418 | ||
b77f483f S |
419 | if (sc->rx.rxdma.dd_desc_len != 0) |
420 | ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf); | |
f078f209 LR |
421 | } |
422 | ||
423 | /* | |
424 | * Calculate the receive filter according to the | |
425 | * operating mode and state: | |
426 | * | |
427 | * o always accept unicast, broadcast, and multicast traffic | |
428 | * o maintain current state of phy error reception (the hal | |
429 | * may enable phy error frames for noise immunity work) | |
430 | * o probe request frames are accepted only when operating in | |
431 | * hostap, adhoc, or monitor modes | |
432 | * o enable promiscuous mode according to the interface state | |
433 | * o accept beacons: | |
434 | * - when operating in adhoc mode so the 802.11 layer creates | |
435 | * node table entries for peers, | |
436 | * - when operating in station mode for collecting rssi data when | |
437 | * the station is otherwise quiet, or | |
438 | * - when operating as a repeater so we see repeater-sta beacons | |
439 | * - when scanning | |
440 | */ | |
441 | ||
442 | u32 ath_calcrxfilter(struct ath_softc *sc) | |
443 | { | |
444 | #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR) | |
7dcfdcd9 | 445 | |
f078f209 LR |
446 | u32 rfilt; |
447 | ||
448 | rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE) | |
449 | | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST | |
450 | | ATH9K_RX_FILTER_MCAST; | |
451 | ||
452 | /* If not a STA, enable processing of Probe Requests */ | |
2660b81a | 453 | if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) |
f078f209 LR |
454 | rfilt |= ATH9K_RX_FILTER_PROBEREQ; |
455 | ||
217ba9da JM |
456 | /* |
457 | * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station | |
458 | * mode interface or when in monitor mode. AP mode does not need this | |
459 | * since it receives all in-BSS frames anyway. | |
460 | */ | |
2660b81a | 461 | if (((sc->sc_ah->opmode != NL80211_IFTYPE_AP) && |
b77f483f | 462 | (sc->rx.rxfilter & FIF_PROMISC_IN_BSS)) || |
217ba9da | 463 | (sc->sc_ah->opmode == NL80211_IFTYPE_MONITOR)) |
f078f209 | 464 | rfilt |= ATH9K_RX_FILTER_PROM; |
f078f209 | 465 | |
d42c6b71 S |
466 | if (sc->rx.rxfilter & FIF_CONTROL) |
467 | rfilt |= ATH9K_RX_FILTER_CONTROL; | |
468 | ||
dbaaa147 VT |
469 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) && |
470 | !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)) | |
471 | rfilt |= ATH9K_RX_FILTER_MYBEACON; | |
472 | else | |
f078f209 LR |
473 | rfilt |= ATH9K_RX_FILTER_BEACON; |
474 | ||
66afad01 SB |
475 | if ((AR_SREV_9280_10_OR_LATER(sc->sc_ah) || |
476 | AR_SREV_9285_10_OR_LATER(sc->sc_ah)) && | |
477 | (sc->sc_ah->opmode == NL80211_IFTYPE_AP) && | |
478 | (sc->rx.rxfilter & FIF_PSPOLL)) | |
dbaaa147 | 479 | rfilt |= ATH9K_RX_FILTER_PSPOLL; |
be0418ad | 480 | |
7ea310be S |
481 | if (conf_is_ht(&sc->hw->conf)) |
482 | rfilt |= ATH9K_RX_FILTER_COMP_BAR; | |
483 | ||
5eb6ba83 | 484 | if (sc->sec_wiphy || (sc->rx.rxfilter & FIF_OTHER_BSS)) { |
b93bce2a JM |
485 | /* TODO: only needed if more than one BSSID is in use in |
486 | * station/adhoc mode */ | |
5eb6ba83 JC |
487 | /* The following may also be needed for other older chips */ |
488 | if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160) | |
489 | rfilt |= ATH9K_RX_FILTER_PROM; | |
b93bce2a JM |
490 | rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL; |
491 | } | |
492 | ||
f078f209 | 493 | return rfilt; |
7dcfdcd9 | 494 | |
f078f209 LR |
495 | #undef RX_FILTER_PRESERVE |
496 | } | |
497 | ||
f078f209 LR |
498 | int ath_startrecv(struct ath_softc *sc) |
499 | { | |
cbe61d8a | 500 | struct ath_hw *ah = sc->sc_ah; |
f078f209 LR |
501 | struct ath_buf *bf, *tbf; |
502 | ||
b77f483f S |
503 | spin_lock_bh(&sc->rx.rxbuflock); |
504 | if (list_empty(&sc->rx.rxbuf)) | |
f078f209 LR |
505 | goto start_recv; |
506 | ||
b77f483f S |
507 | sc->rx.rxlink = NULL; |
508 | list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) { | |
f078f209 LR |
509 | ath_rx_buf_link(sc, bf); |
510 | } | |
511 | ||
512 | /* We could have deleted elements so the list may be empty now */ | |
b77f483f | 513 | if (list_empty(&sc->rx.rxbuf)) |
f078f209 LR |
514 | goto start_recv; |
515 | ||
b77f483f | 516 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); |
f078f209 | 517 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); |
be0418ad | 518 | ath9k_hw_rxena(ah); |
f078f209 LR |
519 | |
520 | start_recv: | |
b77f483f | 521 | spin_unlock_bh(&sc->rx.rxbuflock); |
be0418ad S |
522 | ath_opmode_init(sc); |
523 | ath9k_hw_startpcureceive(ah); | |
524 | ||
f078f209 LR |
525 | return 0; |
526 | } | |
527 | ||
f078f209 LR |
528 | bool ath_stoprecv(struct ath_softc *sc) |
529 | { | |
cbe61d8a | 530 | struct ath_hw *ah = sc->sc_ah; |
f078f209 LR |
531 | bool stopped; |
532 | ||
be0418ad S |
533 | ath9k_hw_stoppcurecv(ah); |
534 | ath9k_hw_setrxfilter(ah, 0); | |
535 | stopped = ath9k_hw_stopdmarecv(ah); | |
b77f483f | 536 | sc->rx.rxlink = NULL; |
be0418ad | 537 | |
f078f209 LR |
538 | return stopped; |
539 | } | |
540 | ||
f078f209 LR |
541 | void ath_flushrecv(struct ath_softc *sc) |
542 | { | |
b77f483f | 543 | spin_lock_bh(&sc->rx.rxflushlock); |
98deeea0 | 544 | sc->sc_flags |= SC_OP_RXFLUSH; |
f078f209 | 545 | ath_rx_tasklet(sc, 1); |
98deeea0 | 546 | sc->sc_flags &= ~SC_OP_RXFLUSH; |
b77f483f | 547 | spin_unlock_bh(&sc->rx.rxflushlock); |
f078f209 LR |
548 | } |
549 | ||
cc65965c JM |
550 | static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb) |
551 | { | |
552 | /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */ | |
553 | struct ieee80211_mgmt *mgmt; | |
554 | u8 *pos, *end, id, elen; | |
555 | struct ieee80211_tim_ie *tim; | |
556 | ||
557 | mgmt = (struct ieee80211_mgmt *)skb->data; | |
558 | pos = mgmt->u.beacon.variable; | |
559 | end = skb->data + skb->len; | |
560 | ||
561 | while (pos + 2 < end) { | |
562 | id = *pos++; | |
563 | elen = *pos++; | |
564 | if (pos + elen > end) | |
565 | break; | |
566 | ||
567 | if (id == WLAN_EID_TIM) { | |
568 | if (elen < sizeof(*tim)) | |
569 | break; | |
570 | tim = (struct ieee80211_tim_ie *) pos; | |
571 | if (tim->dtim_count != 0) | |
572 | break; | |
573 | return tim->bitmap_ctrl & 0x01; | |
574 | } | |
575 | ||
576 | pos += elen; | |
577 | } | |
578 | ||
579 | return false; | |
580 | } | |
581 | ||
cc65965c JM |
582 | static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb) |
583 | { | |
584 | struct ieee80211_mgmt *mgmt; | |
1510718d | 585 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
cc65965c JM |
586 | |
587 | if (skb->len < 24 + 8 + 2 + 2) | |
588 | return; | |
589 | ||
590 | mgmt = (struct ieee80211_mgmt *)skb->data; | |
1510718d | 591 | if (memcmp(common->curbssid, mgmt->bssid, ETH_ALEN) != 0) |
cc65965c JM |
592 | return; /* not from our current AP */ |
593 | ||
293dc5df GJ |
594 | sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON; |
595 | ||
ccdfeab6 JM |
596 | if (sc->sc_flags & SC_OP_BEACON_SYNC) { |
597 | sc->sc_flags &= ~SC_OP_BEACON_SYNC; | |
c46917bb LR |
598 | ath_print(common, ATH_DBG_PS, |
599 | "Reconfigure Beacon timers based on " | |
600 | "timestamp from the AP\n"); | |
ccdfeab6 JM |
601 | ath_beacon_config(sc, NULL); |
602 | } | |
603 | ||
cc65965c JM |
604 | if (ath_beacon_dtim_pending_cab(skb)) { |
605 | /* | |
606 | * Remain awake waiting for buffered broadcast/multicast | |
58f5fffd GJ |
607 | * frames. If the last broadcast/multicast frame is not |
608 | * received properly, the next beacon frame will work as | |
609 | * a backup trigger for returning into NETWORK SLEEP state, | |
610 | * so we are waiting for it as well. | |
cc65965c | 611 | */ |
c46917bb LR |
612 | ath_print(common, ATH_DBG_PS, "Received DTIM beacon indicating " |
613 | "buffered broadcast/multicast frame(s)\n"); | |
58f5fffd | 614 | sc->sc_flags |= SC_OP_WAIT_FOR_CAB | SC_OP_WAIT_FOR_BEACON; |
cc65965c JM |
615 | return; |
616 | } | |
617 | ||
618 | if (sc->sc_flags & SC_OP_WAIT_FOR_CAB) { | |
619 | /* | |
620 | * This can happen if a broadcast frame is dropped or the AP | |
621 | * fails to send a frame indicating that all CAB frames have | |
622 | * been delivered. | |
623 | */ | |
293dc5df | 624 | sc->sc_flags &= ~SC_OP_WAIT_FOR_CAB; |
c46917bb LR |
625 | ath_print(common, ATH_DBG_PS, |
626 | "PS wait for CAB frames timed out\n"); | |
cc65965c | 627 | } |
cc65965c JM |
628 | } |
629 | ||
630 | static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb) | |
631 | { | |
632 | struct ieee80211_hdr *hdr; | |
c46917bb | 633 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
cc65965c JM |
634 | |
635 | hdr = (struct ieee80211_hdr *)skb->data; | |
636 | ||
637 | /* Process Beacon and CAB receive in PS state */ | |
9a23f9ca JM |
638 | if ((sc->sc_flags & SC_OP_WAIT_FOR_BEACON) && |
639 | ieee80211_is_beacon(hdr->frame_control)) | |
cc65965c JM |
640 | ath_rx_ps_beacon(sc, skb); |
641 | else if ((sc->sc_flags & SC_OP_WAIT_FOR_CAB) && | |
642 | (ieee80211_is_data(hdr->frame_control) || | |
643 | ieee80211_is_action(hdr->frame_control)) && | |
644 | is_multicast_ether_addr(hdr->addr1) && | |
645 | !ieee80211_has_moredata(hdr->frame_control)) { | |
cc65965c JM |
646 | /* |
647 | * No more broadcast/multicast frames to be received at this | |
648 | * point. | |
649 | */ | |
293dc5df | 650 | sc->sc_flags &= ~SC_OP_WAIT_FOR_CAB; |
c46917bb LR |
651 | ath_print(common, ATH_DBG_PS, |
652 | "All PS CAB frames received, back to sleep\n"); | |
9a23f9ca JM |
653 | } else if ((sc->sc_flags & SC_OP_WAIT_FOR_PSPOLL_DATA) && |
654 | !is_multicast_ether_addr(hdr->addr1) && | |
655 | !ieee80211_has_morefrags(hdr->frame_control)) { | |
656 | sc->sc_flags &= ~SC_OP_WAIT_FOR_PSPOLL_DATA; | |
c46917bb LR |
657 | ath_print(common, ATH_DBG_PS, |
658 | "Going back to sleep after having received " | |
659 | "PS-Poll data (0x%x)\n", | |
9a23f9ca JM |
660 | sc->sc_flags & (SC_OP_WAIT_FOR_BEACON | |
661 | SC_OP_WAIT_FOR_CAB | | |
662 | SC_OP_WAIT_FOR_PSPOLL_DATA | | |
663 | SC_OP_WAIT_FOR_TX_ACK)); | |
cc65965c JM |
664 | } |
665 | } | |
666 | ||
b4afffc0 LR |
667 | static void ath_rx_send_to_mac80211(struct ieee80211_hw *hw, |
668 | struct ath_softc *sc, struct sk_buff *skb, | |
5ca42627 | 669 | struct ieee80211_rx_status *rxs) |
9d64a3cf JM |
670 | { |
671 | struct ieee80211_hdr *hdr; | |
672 | ||
673 | hdr = (struct ieee80211_hdr *)skb->data; | |
674 | ||
675 | /* Send the frame to mac80211 */ | |
676 | if (is_multicast_ether_addr(hdr->addr1)) { | |
677 | int i; | |
678 | /* | |
679 | * Deliver broadcast/multicast frames to all suitable | |
680 | * virtual wiphys. | |
681 | */ | |
682 | /* TODO: filter based on channel configuration */ | |
683 | for (i = 0; i < sc->num_sec_wiphy; i++) { | |
684 | struct ath_wiphy *aphy = sc->sec_wiphy[i]; | |
685 | struct sk_buff *nskb; | |
686 | if (aphy == NULL) | |
687 | continue; | |
688 | nskb = skb_copy(skb, GFP_ATOMIC); | |
5ca42627 LR |
689 | if (!nskb) |
690 | continue; | |
691 | ieee80211_rx(aphy->hw, nskb); | |
9d64a3cf | 692 | } |
f1d58c25 | 693 | ieee80211_rx(sc->hw, skb); |
5ca42627 | 694 | } else |
9d64a3cf | 695 | /* Deliver unicast frames based on receiver address */ |
b4afffc0 | 696 | ieee80211_rx(hw, skb); |
9d64a3cf JM |
697 | } |
698 | ||
f078f209 LR |
699 | int ath_rx_tasklet(struct ath_softc *sc, int flush) |
700 | { | |
701 | #define PA2DESC(_sc, _pa) \ | |
b77f483f S |
702 | ((struct ath_desc *)((caddr_t)(_sc)->rx.rxdma.dd_desc + \ |
703 | ((_pa) - (_sc)->rx.rxdma.dd_desc_paddr))) | |
f078f209 | 704 | |
be0418ad | 705 | struct ath_buf *bf; |
f078f209 | 706 | struct ath_desc *ds; |
26ab2645 | 707 | struct ath_rx_status *rx_stats; |
cb71d9ba | 708 | struct sk_buff *skb = NULL, *requeue_skb; |
5ca42627 | 709 | struct ieee80211_rx_status *rxs; |
cbe61d8a | 710 | struct ath_hw *ah = sc->sc_ah; |
27c51f1a | 711 | struct ath_common *common = ath9k_hw_common(ah); |
b4afffc0 LR |
712 | /* |
713 | * The hw can techncically differ from common->hw when using ath9k | |
714 | * virtual wiphy so to account for that we iterate over the active | |
715 | * wiphys and find the appropriate wiphy and therefore hw. | |
716 | */ | |
717 | struct ieee80211_hw *hw = NULL; | |
be0418ad S |
718 | struct ieee80211_hdr *hdr; |
719 | int hdrlen, padsize, retval; | |
720 | bool decrypt_error = false; | |
721 | u8 keyix; | |
853da11b | 722 | __le16 fc; |
be0418ad | 723 | |
b77f483f | 724 | spin_lock_bh(&sc->rx.rxbuflock); |
f078f209 LR |
725 | |
726 | do { | |
727 | /* If handling rx interrupt and flush is in progress => exit */ | |
98deeea0 | 728 | if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0)) |
f078f209 LR |
729 | break; |
730 | ||
b77f483f S |
731 | if (list_empty(&sc->rx.rxbuf)) { |
732 | sc->rx.rxlink = NULL; | |
f078f209 LR |
733 | break; |
734 | } | |
735 | ||
b77f483f | 736 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); |
f078f209 | 737 | ds = bf->bf_desc; |
f078f209 LR |
738 | |
739 | /* | |
740 | * Must provide the virtual address of the current | |
741 | * descriptor, the physical address, and the virtual | |
742 | * address of the next descriptor in the h/w chain. | |
743 | * This allows the HAL to look ahead to see if the | |
744 | * hardware is done with a descriptor by checking the | |
745 | * done bit in the following descriptor and the address | |
746 | * of the current descriptor the DMA engine is working | |
747 | * on. All this is necessary because of our use of | |
748 | * a self-linked list to avoid rx overruns. | |
749 | */ | |
be0418ad | 750 | retval = ath9k_hw_rxprocdesc(ah, ds, |
f078f209 LR |
751 | bf->bf_daddr, |
752 | PA2DESC(sc, ds->ds_link), | |
753 | 0); | |
754 | if (retval == -EINPROGRESS) { | |
755 | struct ath_buf *tbf; | |
756 | struct ath_desc *tds; | |
757 | ||
b77f483f S |
758 | if (list_is_last(&bf->list, &sc->rx.rxbuf)) { |
759 | sc->rx.rxlink = NULL; | |
f078f209 LR |
760 | break; |
761 | } | |
762 | ||
763 | tbf = list_entry(bf->list.next, struct ath_buf, list); | |
764 | ||
765 | /* | |
766 | * On some hardware the descriptor status words could | |
767 | * get corrupted, including the done bit. Because of | |
768 | * this, check if the next descriptor's done bit is | |
769 | * set or not. | |
770 | * | |
771 | * If the next descriptor's done bit is set, the current | |
772 | * descriptor has been corrupted. Force s/w to discard | |
773 | * this descriptor and continue... | |
774 | */ | |
775 | ||
776 | tds = tbf->bf_desc; | |
be0418ad S |
777 | retval = ath9k_hw_rxprocdesc(ah, tds, tbf->bf_daddr, |
778 | PA2DESC(sc, tds->ds_link), 0); | |
f078f209 | 779 | if (retval == -EINPROGRESS) { |
f078f209 LR |
780 | break; |
781 | } | |
782 | } | |
783 | ||
f078f209 | 784 | skb = bf->bf_mpdu; |
be0418ad | 785 | if (!skb) |
f078f209 | 786 | continue; |
f078f209 | 787 | |
9bf9fca8 VT |
788 | /* |
789 | * Synchronize the DMA transfer with CPU before | |
790 | * 1. accessing the frame | |
791 | * 2. requeueing the same buffer to h/w | |
792 | */ | |
7da3c55c | 793 | dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr, |
cc861f74 | 794 | common->rx_bufsize, |
7da3c55c | 795 | DMA_FROM_DEVICE); |
9bf9fca8 | 796 | |
b4afffc0 | 797 | hdr = (struct ieee80211_hdr *) skb->data; |
5ca42627 LR |
798 | rxs = IEEE80211_SKB_RXCB(skb); |
799 | ||
b4afffc0 | 800 | hw = ath_get_virt_hw(sc, hdr); |
26ab2645 | 801 | rx_stats = &ds->ds_rxstat; |
b4afffc0 | 802 | |
f078f209 | 803 | /* |
be0418ad S |
804 | * If we're asked to flush receive queue, directly |
805 | * chain it back at the queue without processing it. | |
f078f209 | 806 | */ |
be0418ad | 807 | if (flush) |
cb71d9ba | 808 | goto requeue; |
f078f209 | 809 | |
1e875e9f LR |
810 | retval = ath9k_rx_skb_preprocess(common, hw, skb, rx_stats, |
811 | rxs, &decrypt_error); | |
812 | if (retval) | |
cb71d9ba LR |
813 | goto requeue; |
814 | ||
815 | /* Ensure we always have an skb to requeue once we are done | |
816 | * processing the current buffer's skb */ | |
cc861f74 | 817 | requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC); |
cb71d9ba LR |
818 | |
819 | /* If there is no memory we ignore the current RX'd frame, | |
820 | * tell hardware it can give us a new frame using the old | |
b77f483f | 821 | * skb and put it at the tail of the sc->rx.rxbuf list for |
cb71d9ba LR |
822 | * processing. */ |
823 | if (!requeue_skb) | |
824 | goto requeue; | |
f078f209 | 825 | |
9bf9fca8 | 826 | /* Unmap the frame */ |
7da3c55c | 827 | dma_unmap_single(sc->dev, bf->bf_buf_addr, |
cc861f74 | 828 | common->rx_bufsize, |
7da3c55c | 829 | DMA_FROM_DEVICE); |
f078f209 | 830 | |
26ab2645 | 831 | skb_put(skb, rx_stats->rs_datalen); |
be0418ad S |
832 | |
833 | /* see if any padding is done by the hw and remove it */ | |
be0418ad | 834 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); |
853da11b | 835 | fc = hdr->frame_control; |
be0418ad | 836 | |
9c5f89b3 JM |
837 | /* The MAC header is padded to have 32-bit boundary if the |
838 | * packet payload is non-zero. The general calculation for | |
839 | * padsize would take into account odd header lengths: | |
840 | * padsize = (4 - hdrlen % 4) % 4; However, since only | |
841 | * even-length headers are used, padding can only be 0 or 2 | |
842 | * bytes and we can optimize this a bit. In addition, we must | |
843 | * not try to remove padding from short control frames that do | |
844 | * not have payload. */ | |
845 | padsize = hdrlen & 3; | |
846 | if (padsize && hdrlen >= 24) { | |
be0418ad S |
847 | memmove(skb->data + padsize, skb->data, hdrlen); |
848 | skb_pull(skb, padsize); | |
f078f209 LR |
849 | } |
850 | ||
26ab2645 | 851 | keyix = rx_stats->rs_keyix; |
f078f209 | 852 | |
be0418ad | 853 | if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error) { |
5ca42627 | 854 | rxs->flag |= RX_FLAG_DECRYPTED; |
9d64a3cf | 855 | } else if (ieee80211_has_protected(fc) |
be0418ad S |
856 | && !decrypt_error && skb->len >= hdrlen + 4) { |
857 | keyix = skb->data[hdrlen + 3] >> 6; | |
858 | ||
7e86c104 | 859 | if (test_bit(keyix, common->keymap)) |
5ca42627 | 860 | rxs->flag |= RX_FLAG_DECRYPTED; |
be0418ad | 861 | } |
0ced0e17 | 862 | if (ah->sw_mgmt_crypto && |
5ca42627 LR |
863 | (rxs->flag & RX_FLAG_DECRYPTED) && |
864 | ieee80211_is_mgmt(fc)) | |
0ced0e17 | 865 | /* Use software decrypt for management frames. */ |
5ca42627 | 866 | rxs->flag &= ~RX_FLAG_DECRYPTED; |
be0418ad | 867 | |
cb71d9ba LR |
868 | /* We will now give hardware our shiny new allocated skb */ |
869 | bf->bf_mpdu = requeue_skb; | |
7da3c55c | 870 | bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data, |
cc861f74 LR |
871 | common->rx_bufsize, |
872 | DMA_FROM_DEVICE); | |
7da3c55c | 873 | if (unlikely(dma_mapping_error(sc->dev, |
f8316df1 LR |
874 | bf->bf_buf_addr))) { |
875 | dev_kfree_skb_any(requeue_skb); | |
876 | bf->bf_mpdu = NULL; | |
c46917bb LR |
877 | ath_print(common, ATH_DBG_FATAL, |
878 | "dma_mapping_error() on RX\n"); | |
5ca42627 | 879 | ath_rx_send_to_mac80211(hw, sc, skb, rxs); |
f8316df1 LR |
880 | break; |
881 | } | |
cb71d9ba | 882 | bf->bf_dmacontext = bf->bf_buf_addr; |
f078f209 LR |
883 | |
884 | /* | |
885 | * change the default rx antenna if rx diversity chooses the | |
886 | * other antenna 3 times in a row. | |
887 | */ | |
b77f483f S |
888 | if (sc->rx.defant != ds->ds_rxstat.rs_antenna) { |
889 | if (++sc->rx.rxotherant >= 3) | |
26ab2645 | 890 | ath_setdefantenna(sc, rx_stats->rs_antenna); |
f078f209 | 891 | } else { |
b77f483f | 892 | sc->rx.rxotherant = 0; |
f078f209 | 893 | } |
3cbb5dd7 | 894 | |
9a23f9ca | 895 | if (unlikely(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON | |
f0e9a860 | 896 | SC_OP_WAIT_FOR_CAB | |
9a23f9ca | 897 | SC_OP_WAIT_FOR_PSPOLL_DATA))) |
cc65965c JM |
898 | ath_rx_ps(sc, skb); |
899 | ||
5ca42627 | 900 | ath_rx_send_to_mac80211(hw, sc, skb, rxs); |
cc65965c | 901 | |
cb71d9ba | 902 | requeue: |
b77f483f | 903 | list_move_tail(&bf->list, &sc->rx.rxbuf); |
cb71d9ba | 904 | ath_rx_buf_link(sc, bf); |
be0418ad S |
905 | } while (1); |
906 | ||
b77f483f | 907 | spin_unlock_bh(&sc->rx.rxbuflock); |
f078f209 LR |
908 | |
909 | return 0; | |
910 | #undef PA2DESC | |
911 | } |