[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / wmi.h

/*
 * Copyright (c) 2010-2011 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef WMI_H
#define WMI_H

struct wmi_event_txrate {
	__be32 txrate;
	struct {
		u8 rssi_thresh;
		u8 per;
	} rc_stats;
} __packed;

struct wmi_cmd_hdr {
	__be16 command_id;
	__be16 seq_no;
} __packed;

struct wmi_fw_version {
	__be16 major;
	__be16 minor;

} __packed;

struct wmi_event_swba {
	__be64 tsf;
	u8 beacon_pending;
};

/*
 * 64 - HTC header - WMI header - 1 / txstatus
 * And some other hdr. space is also accounted for.
 * 12 seems to be the magic number.
 */
#define HTC_MAX_TX_STATUS 12

#define ATH9K_HTC_TXSTAT_ACK        BIT(0)
#define ATH9K_HTC_TXSTAT_FILT       BIT(1)
#define ATH9K_HTC_TXSTAT_RTC_CTS    BIT(2)
#define ATH9K_HTC_TXSTAT_MCS        BIT(3)
#define ATH9K_HTC_TXSTAT_CW40       BIT(4)
#define ATH9K_HTC_TXSTAT_SGI        BIT(5)

/*
 * Legacy rates are indicated as indices.
 * HT rates are indicated as dot11 numbers.
 * This allows us to resrict the rate field
 * to 4 bits.
 */
#define ATH9K_HTC_TXSTAT_RATE       0x0f
#define ATH9K_HTC_TXSTAT_RATE_S     0

#define ATH9K_HTC_TXSTAT_EPID       0xf0
#define ATH9K_HTC_TXSTAT_EPID_S     4

struct __wmi_event_txstatus {
	u8 cookie;
	u8 ts_rate; /* Also holds EP ID */
	u8 ts_flags;
};

struct wmi_event_txstatus {
	u8 cnt;
	struct __wmi_event_txstatus txstatus[HTC_MAX_TX_STATUS];
} __packed;

enum wmi_cmd_id {
	WMI_ECHO_CMDID = 0x0001,
	WMI_ACCESS_MEMORY_CMDID,

	/* Commands to Target */
	WMI_GET_FW_VERSION,
	WMI_DISABLE_INTR_CMDID,
	WMI_ENABLE_INTR_CMDID,
	WMI_ATH_INIT_CMDID,
	WMI_ABORT_TXQ_CMDID,
	WMI_STOP_TX_DMA_CMDID,
	WMI_ABORT_TX_DMA_CMDID,
	WMI_DRAIN_TXQ_CMDID,
	WMI_DRAIN_TXQ_ALL_CMDID,
	WMI_START_RECV_CMDID,
	WMI_STOP_RECV_CMDID,
	WMI_FLUSH_RECV_CMDID,
	WMI_SET_MODE_CMDID,
	WMI_NODE_CREATE_CMDID,
	WMI_NODE_REMOVE_CMDID,
	WMI_VAP_REMOVE_CMDID,
	WMI_VAP_CREATE_CMDID,
	WMI_REG_READ_CMDID,
	WMI_REG_WRITE_CMDID,
	WMI_RC_STATE_CHANGE_CMDID,
	WMI_RC_RATE_UPDATE_CMDID,
	WMI_TARGET_IC_UPDATE_CMDID,
	WMI_TX_AGGR_ENABLE_CMDID,
	WMI_TGT_DETACH_CMDID,
	WMI_NODE_UPDATE_CMDID,
	WMI_INT_STATS_CMDID,
	WMI_TX_STATS_CMDID,
	WMI_RX_STATS_CMDID,
	WMI_BITRATE_MASK_CMDID,
};

enum wmi_event_id {
	WMI_TGT_RDY_EVENTID = 0x1001,
	WMI_SWBA_EVENTID,
	WMI_FATAL_EVENTID,
	WMI_TXTO_EVENTID,
	WMI_BMISS_EVENTID,
	WMI_DELBA_EVENTID,
	WMI_TXSTATUS_EVENTID,
};

#define MAX_CMD_NUMBER 62

struct register_write {
	__be32 reg;
	__be32 val;
};

struct ath9k_htc_tx_event {
	int count;
	struct __wmi_event_txstatus txs;
	struct list_head list;
};

struct wmi {
	struct ath9k_htc_priv *drv_priv;
	struct htc_target *htc;
	enum htc_endpoint_id ctrl_epid;
	struct mutex op_mutex;
	struct completion cmd_wait;
	enum wmi_cmd_id last_cmd_id;
	struct sk_buff_head wmi_event_queue;
	struct tasklet_struct wmi_event_tasklet;
	u16 tx_seq_id;
	u8 *cmd_rsp_buf;
	u32 cmd_rsp_len;
	bool stopped;

	struct list_head pending_tx_events;
	spinlock_t event_lock;

	spinlock_t wmi_lock;

	atomic_t mwrite_cnt;
	struct register_write multi_write[MAX_CMD_NUMBER];
	u32 multi_write_idx;
	struct mutex multi_write_mutex;
};

struct wmi *ath9k_init_wmi(struct ath9k_htc_priv *priv);
void ath9k_deinit_wmi(struct ath9k_htc_priv *priv);
int ath9k_wmi_connect(struct htc_target *htc, struct wmi *wmi,
		      enum htc_endpoint_id *wmi_ctrl_epid);
int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id,
		  u8 *cmd_buf, u32 cmd_len,
		  u8 *rsp_buf, u32 rsp_len,
		  u32 timeout);
void ath9k_wmi_event_tasklet(unsigned long data);
void ath9k_fatal_work(struct work_struct *work);
void ath9k_wmi_event_drain(struct ath9k_htc_priv *priv);

#define WMI_CMD(_wmi_cmd)						\
	do {								\
		ret = ath9k_wmi_cmd(priv->wmi, _wmi_cmd, NULL, 0,	\
				    (u8 *) &cmd_rsp,			\
				    sizeof(cmd_rsp), HZ*2);		\
	} while (0)

#define WMI_CMD_BUF(_wmi_cmd, _buf)					\
	do {								\
		ret = ath9k_wmi_cmd(priv->wmi, _wmi_cmd,		\
				    (u8 *) _buf, sizeof(*_buf),		\
				    &cmd_rsp, sizeof(cmd_rsp), HZ*2);	\
	} while (0)

#endif /* WMI_H */
Commit	Line	Data
fb9987d0	1	/*
5b68138e	2	* Copyright (c) 2010-2011 Atheros Communications Inc.
fb9987d0 S	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#ifndef WMI_H
	18	#define WMI_H
	19
fb9987d0	20	struct wmi_event_txrate {
7f1f5a00	21	__be32 txrate;
fb9987d0 S	22	struct {
	23	u8 rssi_thresh;
	24	u8 per;
	25	} rc_stats;
	26	} __packed;
	27
	28	struct wmi_cmd_hdr {
7f1f5a00 S	29	__be16 command_id;
7f1f5a00 S	30	__be16 seq_no;
fb9987d0 S	31	} __packed;
fb9987d0 S	32
29bbfb24 SM	33	struct wmi_fw_version {
	34	__be16 major;
	35	__be16 minor;
	36
	37	} __packed;
1c165c97 SM	38
	39	struct wmi_event_swba {
	40	__be64 tsf;
	41	u8 beacon_pending;
	42	};
16c56ae8 SM	43
	44	/*
	45	* 64 - HTC header - WMI header - 1 / txstatus
	46	* And some other hdr. space is also accounted for.
27876a29	47	* 12 seems to be the magic number.
16c56ae8	48	*/
27876a29	49	#define HTC_MAX_TX_STATUS 12
16c56ae8 SM	50
	51	#define ATH9K_HTC_TXSTAT_ACK BIT(0)
	52	#define ATH9K_HTC_TXSTAT_FILT BIT(1)
	53	#define ATH9K_HTC_TXSTAT_RTC_CTS BIT(2)
	54	#define ATH9K_HTC_TXSTAT_MCS BIT(3)
	55	#define ATH9K_HTC_TXSTAT_CW40 BIT(4)
	56	#define ATH9K_HTC_TXSTAT_SGI BIT(5)
	57
	58	/*
	59	* Legacy rates are indicated as indices.
	60	* HT rates are indicated as dot11 numbers.
	61	* This allows us to resrict the rate field
	62	* to 4 bits.
	63	*/
	64	#define ATH9K_HTC_TXSTAT_RATE 0x0f
	65	#define ATH9K_HTC_TXSTAT_RATE_S 0
	66
	67	#define ATH9K_HTC_TXSTAT_EPID 0xf0
	68	#define ATH9K_HTC_TXSTAT_EPID_S 4
	69
	70	struct __wmi_event_txstatus {
	71	u8 cookie;
	72	u8 ts_rate; /* Also holds EP ID */
	73	u8 ts_flags;
	74	};
	75
	76	struct wmi_event_txstatus {
	77	u8 cnt;
	78	struct __wmi_event_txstatus txstatus[HTC_MAX_TX_STATUS];
	79	} __packed;
	80
fb9987d0 S	81	enum wmi_cmd_id {
	82	WMI_ECHO_CMDID = 0x0001,
	83	WMI_ACCESS_MEMORY_CMDID,
	84
	85	/* Commands to Target */
29bbfb24	86	WMI_GET_FW_VERSION,
fb9987d0 S	87	WMI_DISABLE_INTR_CMDID,
fb9987d0 S	88	WMI_ENABLE_INTR_CMDID,
fb9987d0 S	89	WMI_ATH_INIT_CMDID,
	90	WMI_ABORT_TXQ_CMDID,
	91	WMI_STOP_TX_DMA_CMDID,
fb9987d0 S	92	WMI_ABORT_TX_DMA_CMDID,
	93	WMI_DRAIN_TXQ_CMDID,
	94	WMI_DRAIN_TXQ_ALL_CMDID,
	95	WMI_START_RECV_CMDID,
	96	WMI_STOP_RECV_CMDID,
	97	WMI_FLUSH_RECV_CMDID,
	98	WMI_SET_MODE_CMDID,
fb9987d0 S	99	WMI_NODE_CREATE_CMDID,
	100	WMI_NODE_REMOVE_CMDID,
	101	WMI_VAP_REMOVE_CMDID,
	102	WMI_VAP_CREATE_CMDID,
fb9987d0 S	103	WMI_REG_READ_CMDID,
	104	WMI_REG_WRITE_CMDID,
	105	WMI_RC_STATE_CHANGE_CMDID,
	106	WMI_RC_RATE_UPDATE_CMDID,
fb9987d0	107	WMI_TARGET_IC_UPDATE_CMDID,
fb9987d0 S	108	WMI_TX_AGGR_ENABLE_CMDID,
fb9987d0 S	109	WMI_TGT_DETACH_CMDID,
fbc29d6c SM	110	WMI_NODE_UPDATE_CMDID,
	111	WMI_INT_STATS_CMDID,
	112	WMI_TX_STATS_CMDID,
	113	WMI_RX_STATS_CMDID,
a55bb94a	114	WMI_BITRATE_MASK_CMDID,
fb9987d0 S	115	};
	116
	117	enum wmi_event_id {
	118	WMI_TGT_RDY_EVENTID = 0x1001,
	119	WMI_SWBA_EVENTID,
	120	WMI_FATAL_EVENTID,
	121	WMI_TXTO_EVENTID,
	122	WMI_BMISS_EVENTID,
fb9987d0	123	WMI_DELBA_EVENTID,
16c56ae8	124	WMI_TXSTATUS_EVENTID,
fb9987d0 S	125	};
fb9987d0 S	126
4a22fe10 S	127	#define MAX_CMD_NUMBER 62
	128
	129	struct register_write {
7f1f5a00 S	130	__be32 reg;
7f1f5a00 S	131	__be32 val;
4a22fe10 S	132	};
4a22fe10 S	133
859c3ca1 SM	134	struct ath9k_htc_tx_event {
	135	int count;
	136	struct __wmi_event_txstatus txs;
	137	struct list_head list;
	138	};
	139
fb9987d0 S	140	struct wmi {
	141	struct ath9k_htc_priv *drv_priv;
	142	struct htc_target *htc;
	143	enum htc_endpoint_id ctrl_epid;
	144	struct mutex op_mutex;
	145	struct completion cmd_wait;
6ce34ec1	146	enum wmi_cmd_id last_cmd_id;
f4c88991 SM	147	struct sk_buff_head wmi_event_queue;
f4c88991 SM	148	struct tasklet_struct wmi_event_tasklet;
fb9987d0 S	149	u16 tx_seq_id;
	150	u8 *cmd_rsp_buf;
	151	u32 cmd_rsp_len;
	152	bool stopped;
	153
859c3ca1 SM	154	struct list_head pending_tx_events;
	155	spinlock_t event_lock;
	156
fb9987d0	157	spinlock_t wmi_lock;
4a22fe10 S	158
	159	atomic_t mwrite_cnt;
	160	struct register_write multi_write[MAX_CMD_NUMBER];
	161	u32 multi_write_idx;
	162	struct mutex multi_write_mutex;
fb9987d0 S	163	};
	164
	165	struct wmi ath9k_init_wmi(struct ath9k_htc_priv priv);
	166	void ath9k_deinit_wmi(struct ath9k_htc_priv *priv);
	167	int ath9k_wmi_connect(struct htc_target htc, struct wmi wmi,
	168	enum htc_endpoint_id *wmi_ctrl_epid);
	169	int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id,
	170	u8 *cmd_buf, u32 cmd_len,
	171	u8 *rsp_buf, u32 rsp_len,
	172	u32 timeout);
f4c88991	173	void ath9k_wmi_event_tasklet(unsigned long data);
73908674	174	void ath9k_fatal_work(struct work_struct *work);
f4c88991	175	void ath9k_wmi_event_drain(struct ath9k_htc_priv *priv);
fb9987d0 S	176
	177	#define WMI_CMD(_wmi_cmd) \
	178	do { \
	179	ret = ath9k_wmi_cmd(priv->wmi, _wmi_cmd, NULL, 0, \
	180	(u8 *) &cmd_rsp, \
ba443701	181	sizeof(cmd_rsp), HZ*2); \
fb9987d0 S	182	} while (0)
	183
	184	#define WMI_CMD_BUF(_wmi_cmd, _buf) \
	185	do { \
	186	ret = ath9k_wmi_cmd(priv->wmi, _wmi_cmd, \
	187	(u8 ) _buf, sizeof(_buf), \
ba443701	188	&cmd_rsp, sizeof(cmd_rsp), HZ*2); \
fb9987d0 S	189	} while (0)
	190
	191	#endif /* WMI_H */