Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
b7f080cf | 17 | #include <linux/dma-mapping.h> |
394cf0a1 | 18 | #include "ath9k.h" |
b622a720 | 19 | #include "ar9003_mac.h" |
f078f209 LR |
20 | |
21 | #define BITS_PER_BYTE 8 | |
22 | #define OFDM_PLCP_BITS 22 | |
f078f209 LR |
23 | #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) |
24 | #define L_STF 8 | |
25 | #define L_LTF 8 | |
26 | #define L_SIG 4 | |
27 | #define HT_SIG 8 | |
28 | #define HT_STF 4 | |
29 | #define HT_LTF(_ns) (4 * (_ns)) | |
30 | #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */ | |
31 | #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */ | |
aa5955c3 FF |
32 | #define TIME_SYMBOLS(t) ((t) >> 2) |
33 | #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18) | |
f078f209 LR |
34 | #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) |
35 | #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) | |
36 | ||
f078f209 | 37 | |
c6663876 | 38 | static u16 bits_per_symbol[][2] = { |
f078f209 LR |
39 | /* 20MHz 40MHz */ |
40 | { 26, 54 }, /* 0: BPSK */ | |
41 | { 52, 108 }, /* 1: QPSK 1/2 */ | |
42 | { 78, 162 }, /* 2: QPSK 3/4 */ | |
43 | { 104, 216 }, /* 3: 16-QAM 1/2 */ | |
44 | { 156, 324 }, /* 4: 16-QAM 3/4 */ | |
45 | { 208, 432 }, /* 5: 64-QAM 2/3 */ | |
46 | { 234, 486 }, /* 6: 64-QAM 3/4 */ | |
47 | { 260, 540 }, /* 7: 64-QAM 5/6 */ | |
f078f209 LR |
48 | }; |
49 | ||
50 | #define IS_HT_RATE(_rate) ((_rate) & 0x80) | |
51 | ||
82b873af | 52 | static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, |
44f1d26c FF |
53 | struct ath_atx_tid *tid, struct sk_buff *skb); |
54 | static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, | |
55 | int tx_flags, struct ath_txq *txq); | |
e8324357 | 56 | static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, |
db1a052b | 57 | struct ath_txq *txq, struct list_head *bf_q, |
156369fa | 58 | struct ath_tx_status *ts, int txok); |
102e0572 | 59 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, |
fce041be | 60 | struct list_head *head, bool internal); |
0cdd5c60 FF |
61 | static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, |
62 | struct ath_tx_status *ts, int nframes, int nbad, | |
3afd21e7 | 63 | int txok); |
90fa539c FF |
64 | static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
65 | int seqno); | |
44f1d26c FF |
66 | static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, |
67 | struct ath_txq *txq, | |
68 | struct ath_atx_tid *tid, | |
249ee722 | 69 | struct sk_buff *skb); |
c4288390 | 70 | |
545750d3 | 71 | enum { |
0e668cde FF |
72 | MCS_HT20, |
73 | MCS_HT20_SGI, | |
545750d3 FF |
74 | MCS_HT40, |
75 | MCS_HT40_SGI, | |
76 | }; | |
77 | ||
e8324357 S |
78 | /*********************/ |
79 | /* Aggregation logic */ | |
80 | /*********************/ | |
f078f209 | 81 | |
ef1b6cd9 | 82 | void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq) |
1512a486 | 83 | __acquires(&txq->axq_lock) |
23de5dc9 FF |
84 | { |
85 | spin_lock_bh(&txq->axq_lock); | |
86 | } | |
87 | ||
ef1b6cd9 | 88 | void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq) |
1512a486 | 89 | __releases(&txq->axq_lock) |
23de5dc9 FF |
90 | { |
91 | spin_unlock_bh(&txq->axq_lock); | |
92 | } | |
93 | ||
ef1b6cd9 | 94 | void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq) |
1512a486 | 95 | __releases(&txq->axq_lock) |
23de5dc9 FF |
96 | { |
97 | struct sk_buff_head q; | |
98 | struct sk_buff *skb; | |
99 | ||
100 | __skb_queue_head_init(&q); | |
101 | skb_queue_splice_init(&txq->complete_q, &q); | |
102 | spin_unlock_bh(&txq->axq_lock); | |
103 | ||
104 | while ((skb = __skb_dequeue(&q))) | |
105 | ieee80211_tx_status(sc->hw, skb); | |
106 | } | |
107 | ||
e8324357 | 108 | static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid) |
ff37e337 | 109 | { |
e8324357 | 110 | struct ath_atx_ac *ac = tid->ac; |
ff37e337 | 111 | |
e8324357 S |
112 | if (tid->paused) |
113 | return; | |
ff37e337 | 114 | |
e8324357 S |
115 | if (tid->sched) |
116 | return; | |
ff37e337 | 117 | |
e8324357 S |
118 | tid->sched = true; |
119 | list_add_tail(&tid->list, &ac->tid_q); | |
528f0c6b | 120 | |
e8324357 S |
121 | if (ac->sched) |
122 | return; | |
f078f209 | 123 | |
e8324357 S |
124 | ac->sched = true; |
125 | list_add_tail(&ac->list, &txq->axq_acq); | |
126 | } | |
f078f209 | 127 | |
e8324357 | 128 | static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
f078f209 | 129 | { |
066dae93 | 130 | struct ath_txq *txq = tid->ac->txq; |
e6a9854b | 131 | |
75401849 | 132 | WARN_ON(!tid->paused); |
f078f209 | 133 | |
23de5dc9 | 134 | ath_txq_lock(sc, txq); |
75401849 | 135 | tid->paused = false; |
f078f209 | 136 | |
56dc6336 | 137 | if (skb_queue_empty(&tid->buf_q)) |
e8324357 | 138 | goto unlock; |
f078f209 | 139 | |
e8324357 S |
140 | ath_tx_queue_tid(txq, tid); |
141 | ath_txq_schedule(sc, txq); | |
142 | unlock: | |
23de5dc9 | 143 | ath_txq_unlock_complete(sc, txq); |
528f0c6b | 144 | } |
f078f209 | 145 | |
2d42efc4 | 146 | static struct ath_frame_info *get_frame_info(struct sk_buff *skb) |
76e45221 FF |
147 | { |
148 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
2d42efc4 FF |
149 | BUILD_BUG_ON(sizeof(struct ath_frame_info) > |
150 | sizeof(tx_info->rate_driver_data)); | |
151 | return (struct ath_frame_info *) &tx_info->rate_driver_data[0]; | |
76e45221 FF |
152 | } |
153 | ||
156369fa FF |
154 | static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno) |
155 | { | |
156 | ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno, | |
157 | seqno << IEEE80211_SEQ_SEQ_SHIFT); | |
158 | } | |
159 | ||
79acac07 FF |
160 | static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta, |
161 | struct ath_buf *bf) | |
162 | { | |
163 | ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates, | |
164 | ARRAY_SIZE(bf->rates)); | |
165 | } | |
166 | ||
16e23428 FF |
167 | static void ath_tx_clear_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
168 | { | |
169 | tid->state &= ~AGGR_ADDBA_COMPLETE; | |
170 | tid->state &= ~AGGR_CLEANUP; | |
171 | if (!tid->stop_cb) | |
172 | return; | |
173 | ||
174 | ieee80211_start_tx_ba_cb_irqsafe(tid->an->vif, tid->an->sta->addr, | |
175 | tid->tidno); | |
176 | tid->stop_cb = false; | |
177 | } | |
178 | ||
179 | static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid, | |
180 | bool flush_packets) | |
528f0c6b | 181 | { |
066dae93 | 182 | struct ath_txq *txq = tid->ac->txq; |
56dc6336 | 183 | struct sk_buff *skb; |
e8324357 S |
184 | struct ath_buf *bf; |
185 | struct list_head bf_head; | |
90fa539c | 186 | struct ath_tx_status ts; |
2d42efc4 | 187 | struct ath_frame_info *fi; |
156369fa | 188 | bool sendbar = false; |
f078f209 | 189 | |
90fa539c | 190 | INIT_LIST_HEAD(&bf_head); |
e6a9854b | 191 | |
90fa539c | 192 | memset(&ts, 0, sizeof(ts)); |
f078f209 | 193 | |
56dc6336 FF |
194 | while ((skb = __skb_dequeue(&tid->buf_q))) { |
195 | fi = get_frame_info(skb); | |
196 | bf = fi->bf; | |
16e23428 FF |
197 | if (!bf && !flush_packets) |
198 | bf = ath_tx_setup_buffer(sc, txq, tid, skb); | |
56dc6336 | 199 | |
249ee722 | 200 | if (!bf) { |
16e23428 FF |
201 | ieee80211_free_txskb(sc->hw, skb); |
202 | continue; | |
249ee722 FF |
203 | } |
204 | ||
16e23428 | 205 | if (fi->retries || flush_packets) { |
44f1d26c | 206 | list_add_tail(&bf->list, &bf_head); |
6a0ddaef | 207 | ath_tx_update_baw(sc, tid, bf->bf_state.seqno); |
156369fa FF |
208 | ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0); |
209 | sendbar = true; | |
90fa539c | 210 | } else { |
79acac07 | 211 | ath_set_rates(tid->an->vif, tid->an->sta, bf); |
44f1d26c | 212 | ath_tx_send_normal(sc, txq, NULL, skb); |
90fa539c | 213 | } |
528f0c6b | 214 | } |
f078f209 | 215 | |
16e23428 FF |
216 | if (tid->baw_head == tid->baw_tail) |
217 | ath_tx_clear_tid(sc, tid); | |
4eb287a4 | 218 | |
16e23428 | 219 | if (sendbar && !flush_packets) { |
23de5dc9 | 220 | ath_txq_unlock(sc, txq); |
156369fa | 221 | ath_send_bar(tid, tid->seq_start); |
23de5dc9 FF |
222 | ath_txq_lock(sc, txq); |
223 | } | |
528f0c6b | 224 | } |
f078f209 | 225 | |
e8324357 S |
226 | static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
227 | int seqno) | |
528f0c6b | 228 | { |
e8324357 | 229 | int index, cindex; |
f078f209 | 230 | |
e8324357 S |
231 | index = ATH_BA_INDEX(tid->seq_start, seqno); |
232 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | |
f078f209 | 233 | |
81ee13ba | 234 | __clear_bit(cindex, tid->tx_buf); |
528f0c6b | 235 | |
81ee13ba | 236 | while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) { |
e8324357 S |
237 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); |
238 | INCR(tid->baw_head, ATH_TID_MAX_BUFS); | |
f9437543 FF |
239 | if (tid->bar_index >= 0) |
240 | tid->bar_index--; | |
e8324357 | 241 | } |
528f0c6b | 242 | } |
f078f209 | 243 | |
e8324357 | 244 | static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
2d3bcba0 | 245 | u16 seqno) |
528f0c6b | 246 | { |
e8324357 | 247 | int index, cindex; |
528f0c6b | 248 | |
2d3bcba0 | 249 | index = ATH_BA_INDEX(tid->seq_start, seqno); |
e8324357 | 250 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); |
81ee13ba | 251 | __set_bit(cindex, tid->tx_buf); |
f078f209 | 252 | |
e8324357 S |
253 | if (index >= ((tid->baw_tail - tid->baw_head) & |
254 | (ATH_TID_MAX_BUFS - 1))) { | |
255 | tid->baw_tail = cindex; | |
256 | INCR(tid->baw_tail, ATH_TID_MAX_BUFS); | |
f078f209 | 257 | } |
f078f209 LR |
258 | } |
259 | ||
260 | /* | |
e8324357 S |
261 | * TODO: For frame(s) that are in the retry state, we will reuse the |
262 | * sequence number(s) without setting the retry bit. The | |
263 | * alternative is to give up on these and BAR the receiver's window | |
264 | * forward. | |
f078f209 | 265 | */ |
e8324357 S |
266 | static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq, |
267 | struct ath_atx_tid *tid) | |
f078f209 | 268 | |
f078f209 | 269 | { |
56dc6336 | 270 | struct sk_buff *skb; |
e8324357 S |
271 | struct ath_buf *bf; |
272 | struct list_head bf_head; | |
db1a052b | 273 | struct ath_tx_status ts; |
2d42efc4 | 274 | struct ath_frame_info *fi; |
db1a052b FF |
275 | |
276 | memset(&ts, 0, sizeof(ts)); | |
e8324357 | 277 | INIT_LIST_HEAD(&bf_head); |
f078f209 | 278 | |
56dc6336 FF |
279 | while ((skb = __skb_dequeue(&tid->buf_q))) { |
280 | fi = get_frame_info(skb); | |
281 | bf = fi->bf; | |
f078f209 | 282 | |
44f1d26c | 283 | if (!bf) { |
44f1d26c | 284 | ath_tx_complete(sc, skb, ATH_TX_ERROR, txq); |
44f1d26c FF |
285 | continue; |
286 | } | |
287 | ||
56dc6336 | 288 | list_add_tail(&bf->list, &bf_head); |
f078f209 | 289 | |
2d42efc4 | 290 | if (fi->retries) |
6a0ddaef | 291 | ath_tx_update_baw(sc, tid, bf->bf_state.seqno); |
f078f209 | 292 | |
156369fa | 293 | ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0); |
e8324357 | 294 | } |
f078f209 | 295 | |
e8324357 S |
296 | tid->seq_next = tid->seq_start; |
297 | tid->baw_tail = tid->baw_head; | |
f9437543 | 298 | tid->bar_index = -1; |
f078f209 LR |
299 | } |
300 | ||
fec247c0 | 301 | static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq, |
da647626 | 302 | struct sk_buff *skb, int count) |
f078f209 | 303 | { |
8b7f8532 | 304 | struct ath_frame_info *fi = get_frame_info(skb); |
f11cc949 | 305 | struct ath_buf *bf = fi->bf; |
e8324357 | 306 | struct ieee80211_hdr *hdr; |
da647626 | 307 | int prev = fi->retries; |
f078f209 | 308 | |
fec247c0 | 309 | TX_STAT_INC(txq->axq_qnum, a_retries); |
da647626 FF |
310 | fi->retries += count; |
311 | ||
312 | if (prev > 0) | |
2d42efc4 | 313 | return; |
f078f209 | 314 | |
e8324357 S |
315 | hdr = (struct ieee80211_hdr *)skb->data; |
316 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); | |
f11cc949 FF |
317 | dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, |
318 | sizeof(*hdr), DMA_TO_DEVICE); | |
f078f209 LR |
319 | } |
320 | ||
0a8cea84 | 321 | static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc) |
d43f3015 | 322 | { |
0a8cea84 | 323 | struct ath_buf *bf = NULL; |
d43f3015 S |
324 | |
325 | spin_lock_bh(&sc->tx.txbuflock); | |
0a8cea84 FF |
326 | |
327 | if (unlikely(list_empty(&sc->tx.txbuf))) { | |
8a46097a VT |
328 | spin_unlock_bh(&sc->tx.txbuflock); |
329 | return NULL; | |
330 | } | |
0a8cea84 FF |
331 | |
332 | bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); | |
333 | list_del(&bf->list); | |
334 | ||
d43f3015 S |
335 | spin_unlock_bh(&sc->tx.txbuflock); |
336 | ||
0a8cea84 FF |
337 | return bf; |
338 | } | |
339 | ||
340 | static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf) | |
341 | { | |
342 | spin_lock_bh(&sc->tx.txbuflock); | |
343 | list_add_tail(&bf->list, &sc->tx.txbuf); | |
344 | spin_unlock_bh(&sc->tx.txbuflock); | |
345 | } | |
346 | ||
347 | static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf) | |
348 | { | |
349 | struct ath_buf *tbf; | |
350 | ||
351 | tbf = ath_tx_get_buffer(sc); | |
352 | if (WARN_ON(!tbf)) | |
353 | return NULL; | |
354 | ||
d43f3015 S |
355 | ATH_TXBUF_RESET(tbf); |
356 | ||
357 | tbf->bf_mpdu = bf->bf_mpdu; | |
358 | tbf->bf_buf_addr = bf->bf_buf_addr; | |
d826c832 | 359 | memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len); |
d43f3015 | 360 | tbf->bf_state = bf->bf_state; |
d43f3015 S |
361 | |
362 | return tbf; | |
363 | } | |
364 | ||
b572d033 FF |
365 | static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf, |
366 | struct ath_tx_status *ts, int txok, | |
367 | int *nframes, int *nbad) | |
368 | { | |
2d42efc4 | 369 | struct ath_frame_info *fi; |
b572d033 FF |
370 | u16 seq_st = 0; |
371 | u32 ba[WME_BA_BMP_SIZE >> 5]; | |
372 | int ba_index; | |
373 | int isaggr = 0; | |
374 | ||
375 | *nbad = 0; | |
376 | *nframes = 0; | |
377 | ||
b572d033 FF |
378 | isaggr = bf_isaggr(bf); |
379 | if (isaggr) { | |
380 | seq_st = ts->ts_seqnum; | |
381 | memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); | |
382 | } | |
383 | ||
384 | while (bf) { | |
2d42efc4 | 385 | fi = get_frame_info(bf->bf_mpdu); |
6a0ddaef | 386 | ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno); |
b572d033 FF |
387 | |
388 | (*nframes)++; | |
389 | if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index))) | |
390 | (*nbad)++; | |
391 | ||
392 | bf = bf->bf_next; | |
393 | } | |
394 | } | |
395 | ||
396 | ||
d43f3015 S |
397 | static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, |
398 | struct ath_buf *bf, struct list_head *bf_q, | |
1381559b | 399 | struct ath_tx_status *ts, int txok) |
f078f209 | 400 | { |
e8324357 S |
401 | struct ath_node *an = NULL; |
402 | struct sk_buff *skb; | |
1286ec6d | 403 | struct ieee80211_sta *sta; |
0cdd5c60 | 404 | struct ieee80211_hw *hw = sc->hw; |
1286ec6d | 405 | struct ieee80211_hdr *hdr; |
76d5a9e8 | 406 | struct ieee80211_tx_info *tx_info; |
e8324357 | 407 | struct ath_atx_tid *tid = NULL; |
d43f3015 | 408 | struct ath_buf *bf_next, *bf_last = bf->bf_lastbf; |
56dc6336 FF |
409 | struct list_head bf_head; |
410 | struct sk_buff_head bf_pending; | |
156369fa | 411 | u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first; |
f078f209 | 412 | u32 ba[WME_BA_BMP_SIZE >> 5]; |
0934af23 | 413 | int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0; |
6fe7cc71 | 414 | bool rc_update = true, isba; |
78c4653a | 415 | struct ieee80211_tx_rate rates[4]; |
2d42efc4 | 416 | struct ath_frame_info *fi; |
ebd02287 | 417 | int nframes; |
5daefbd0 | 418 | u8 tidno; |
daa5c408 | 419 | bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH); |
da647626 | 420 | int i, retries; |
156369fa | 421 | int bar_index = -1; |
f078f209 | 422 | |
a22be22a | 423 | skb = bf->bf_mpdu; |
1286ec6d S |
424 | hdr = (struct ieee80211_hdr *)skb->data; |
425 | ||
76d5a9e8 | 426 | tx_info = IEEE80211_SKB_CB(skb); |
76d5a9e8 | 427 | |
79acac07 | 428 | memcpy(rates, bf->rates, sizeof(rates)); |
78c4653a | 429 | |
da647626 FF |
430 | retries = ts->ts_longretry + 1; |
431 | for (i = 0; i < ts->ts_rateindex; i++) | |
432 | retries += rates[i].count; | |
433 | ||
1286ec6d | 434 | rcu_read_lock(); |
f078f209 | 435 | |
686b9cb9 | 436 | sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2); |
1286ec6d S |
437 | if (!sta) { |
438 | rcu_read_unlock(); | |
73e19463 | 439 | |
31e79a59 FF |
440 | INIT_LIST_HEAD(&bf_head); |
441 | while (bf) { | |
442 | bf_next = bf->bf_next; | |
443 | ||
fce041be | 444 | if (!bf->bf_stale || bf_next != NULL) |
31e79a59 FF |
445 | list_move_tail(&bf->list, &bf_head); |
446 | ||
156369fa | 447 | ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0); |
31e79a59 FF |
448 | |
449 | bf = bf_next; | |
450 | } | |
1286ec6d | 451 | return; |
f078f209 LR |
452 | } |
453 | ||
1286ec6d | 454 | an = (struct ath_node *)sta->drv_priv; |
5daefbd0 FF |
455 | tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK; |
456 | tid = ATH_AN_2_TID(an, tidno); | |
156369fa | 457 | seq_first = tid->seq_start; |
6fe7cc71 | 458 | isba = ts->ts_flags & ATH9K_TX_BA; |
1286ec6d | 459 | |
b11b160d FF |
460 | /* |
461 | * The hardware occasionally sends a tx status for the wrong TID. | |
462 | * In this case, the BA status cannot be considered valid and all | |
463 | * subframes need to be retransmitted | |
6fe7cc71 SE |
464 | * |
465 | * Only BlockAcks have a TID and therefore normal Acks cannot be | |
466 | * checked | |
b11b160d | 467 | */ |
6fe7cc71 | 468 | if (isba && tidno != ts->tid) |
b11b160d FF |
469 | txok = false; |
470 | ||
e8324357 | 471 | isaggr = bf_isaggr(bf); |
d43f3015 | 472 | memset(ba, 0, WME_BA_BMP_SIZE >> 3); |
f078f209 | 473 | |
d43f3015 | 474 | if (isaggr && txok) { |
db1a052b FF |
475 | if (ts->ts_flags & ATH9K_TX_BA) { |
476 | seq_st = ts->ts_seqnum; | |
477 | memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); | |
e8324357 | 478 | } else { |
d43f3015 S |
479 | /* |
480 | * AR5416 can become deaf/mute when BA | |
481 | * issue happens. Chip needs to be reset. | |
482 | * But AP code may have sychronization issues | |
483 | * when perform internal reset in this routine. | |
484 | * Only enable reset in STA mode for now. | |
485 | */ | |
2660b81a | 486 | if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) |
d43f3015 | 487 | needreset = 1; |
e8324357 | 488 | } |
f078f209 LR |
489 | } |
490 | ||
56dc6336 | 491 | __skb_queue_head_init(&bf_pending); |
f078f209 | 492 | |
b572d033 | 493 | ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad); |
e8324357 | 494 | while (bf) { |
6a0ddaef FF |
495 | u16 seqno = bf->bf_state.seqno; |
496 | ||
f0b8220c | 497 | txfail = txpending = sendbar = 0; |
e8324357 | 498 | bf_next = bf->bf_next; |
f078f209 | 499 | |
78c4653a FF |
500 | skb = bf->bf_mpdu; |
501 | tx_info = IEEE80211_SKB_CB(skb); | |
2d42efc4 | 502 | fi = get_frame_info(skb); |
78c4653a | 503 | |
6a0ddaef | 504 | if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) { |
e8324357 S |
505 | /* transmit completion, subframe is |
506 | * acked by block ack */ | |
0934af23 | 507 | acked_cnt++; |
e8324357 S |
508 | } else if (!isaggr && txok) { |
509 | /* transmit completion */ | |
0934af23 | 510 | acked_cnt++; |
1381559b | 511 | } else if (tid->state & AGGR_CLEANUP) { |
b0477013 FF |
512 | /* |
513 | * cleanup in progress, just fail | |
514 | * the un-acked sub-frames | |
515 | */ | |
516 | txfail = 1; | |
517 | } else if (flush) { | |
518 | txpending = 1; | |
519 | } else if (fi->retries < ATH_MAX_SW_RETRIES) { | |
520 | if (txok || !an->sleeping) | |
521 | ath_tx_set_retry(sc, txq, bf->bf_mpdu, | |
522 | retries); | |
523 | ||
524 | txpending = 1; | |
e8324357 | 525 | } else { |
b0477013 FF |
526 | txfail = 1; |
527 | txfail_cnt++; | |
528 | bar_index = max_t(int, bar_index, | |
529 | ATH_BA_INDEX(seq_first, seqno)); | |
e8324357 | 530 | } |
f078f209 | 531 | |
fce041be FF |
532 | /* |
533 | * Make sure the last desc is reclaimed if it | |
534 | * not a holding desc. | |
535 | */ | |
56dc6336 | 536 | INIT_LIST_HEAD(&bf_head); |
99ba6a46 | 537 | if (bf_next != NULL || !bf_last->bf_stale) |
d43f3015 | 538 | list_move_tail(&bf->list, &bf_head); |
f078f209 | 539 | |
90fa539c | 540 | if (!txpending || (tid->state & AGGR_CLEANUP)) { |
e8324357 S |
541 | /* |
542 | * complete the acked-ones/xretried ones; update | |
543 | * block-ack window | |
544 | */ | |
6a0ddaef | 545 | ath_tx_update_baw(sc, tid, seqno); |
f078f209 | 546 | |
8a92e2ee | 547 | if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) { |
78c4653a | 548 | memcpy(tx_info->control.rates, rates, sizeof(rates)); |
3afd21e7 | 549 | ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok); |
8a92e2ee | 550 | rc_update = false; |
8a92e2ee VT |
551 | } |
552 | ||
db1a052b | 553 | ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, |
156369fa | 554 | !txfail); |
e8324357 | 555 | } else { |
d43f3015 | 556 | /* retry the un-acked ones */ |
99ba6a46 | 557 | if (bf->bf_next == NULL && bf_last->bf_stale) { |
b0477013 FF |
558 | struct ath_buf *tbf; |
559 | ||
560 | tbf = ath_clone_txbuf(sc, bf_last); | |
561 | /* | |
562 | * Update tx baw and complete the | |
563 | * frame with failed status if we | |
564 | * run out of tx buf. | |
565 | */ | |
566 | if (!tbf) { | |
b0477013 | 567 | ath_tx_update_baw(sc, tid, seqno); |
b0477013 FF |
568 | |
569 | ath_tx_complete_buf(sc, bf, txq, | |
570 | &bf_head, ts, 0); | |
571 | bar_index = max_t(int, bar_index, | |
572 | ATH_BA_INDEX(seq_first, seqno)); | |
573 | break; | |
c41d92dc | 574 | } |
b0477013 FF |
575 | |
576 | fi->bf = tbf; | |
e8324357 S |
577 | } |
578 | ||
579 | /* | |
580 | * Put this buffer to the temporary pending | |
581 | * queue to retain ordering | |
582 | */ | |
56dc6336 | 583 | __skb_queue_tail(&bf_pending, skb); |
e8324357 S |
584 | } |
585 | ||
586 | bf = bf_next; | |
f078f209 | 587 | } |
f078f209 | 588 | |
4cee7861 | 589 | /* prepend un-acked frames to the beginning of the pending frame queue */ |
56dc6336 | 590 | if (!skb_queue_empty(&bf_pending)) { |
5519541d | 591 | if (an->sleeping) |
042ec453 | 592 | ieee80211_sta_set_buffered(sta, tid->tidno, true); |
5519541d | 593 | |
56dc6336 | 594 | skb_queue_splice(&bf_pending, &tid->buf_q); |
26a64259 | 595 | if (!an->sleeping) { |
9af73cf7 | 596 | ath_tx_queue_tid(txq, tid); |
26a64259 | 597 | |
adfbda62 | 598 | if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY)) |
26a64259 FF |
599 | tid->ac->clear_ps_filter = true; |
600 | } | |
4cee7861 FF |
601 | } |
602 | ||
23de5dc9 FF |
603 | if (bar_index >= 0) { |
604 | u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index); | |
605 | ||
606 | if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq)) | |
607 | tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq); | |
608 | ||
609 | ath_txq_unlock(sc, txq); | |
610 | ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1)); | |
611 | ath_txq_lock(sc, txq); | |
612 | } | |
613 | ||
4eb287a4 | 614 | if (tid->state & AGGR_CLEANUP) |
16e23428 | 615 | ath_tx_flush_tid(sc, tid, false); |
90fa539c | 616 | |
1286ec6d S |
617 | rcu_read_unlock(); |
618 | ||
124b979b RM |
619 | if (needreset) |
620 | ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR); | |
e8324357 | 621 | } |
f078f209 | 622 | |
81b51950 FF |
623 | static bool bf_is_ampdu_not_probing(struct ath_buf *bf) |
624 | { | |
625 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu); | |
626 | return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE); | |
627 | } | |
628 | ||
629 | static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq, | |
630 | struct ath_tx_status *ts, struct ath_buf *bf, | |
631 | struct list_head *bf_head) | |
632 | { | |
633 | bool txok, flush; | |
634 | ||
635 | txok = !(ts->ts_status & ATH9K_TXERR_MASK); | |
636 | flush = !!(ts->ts_status & ATH9K_TX_FLUSH); | |
637 | txq->axq_tx_inprogress = false; | |
638 | ||
639 | txq->axq_depth--; | |
640 | if (bf_is_ampdu_not_probing(bf)) | |
641 | txq->axq_ampdu_depth--; | |
642 | ||
643 | if (!bf_isampdu(bf)) { | |
644 | if (!flush) | |
645 | ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok); | |
646 | ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok); | |
647 | } else | |
648 | ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok); | |
649 | ||
650 | if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) && !flush) | |
651 | ath_txq_schedule(sc, txq); | |
652 | } | |
653 | ||
1a6e9d0f RM |
654 | static bool ath_lookup_legacy(struct ath_buf *bf) |
655 | { | |
656 | struct sk_buff *skb; | |
657 | struct ieee80211_tx_info *tx_info; | |
658 | struct ieee80211_tx_rate *rates; | |
659 | int i; | |
660 | ||
661 | skb = bf->bf_mpdu; | |
662 | tx_info = IEEE80211_SKB_CB(skb); | |
663 | rates = tx_info->control.rates; | |
664 | ||
059ee09b FF |
665 | for (i = 0; i < 4; i++) { |
666 | if (!rates[i].count || rates[i].idx < 0) | |
667 | break; | |
668 | ||
1a6e9d0f RM |
669 | if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) |
670 | return true; | |
671 | } | |
672 | ||
673 | return false; | |
674 | } | |
675 | ||
e8324357 S |
676 | static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf, |
677 | struct ath_atx_tid *tid) | |
f078f209 | 678 | { |
528f0c6b S |
679 | struct sk_buff *skb; |
680 | struct ieee80211_tx_info *tx_info; | |
a8efee4f | 681 | struct ieee80211_tx_rate *rates; |
d43f3015 | 682 | u32 max_4ms_framelen, frmlen; |
c0ac53fa | 683 | u16 aggr_limit, bt_aggr_limit, legacy = 0; |
aa5955c3 | 684 | int q = tid->ac->txq->mac80211_qnum; |
e8324357 | 685 | int i; |
528f0c6b | 686 | |
a22be22a | 687 | skb = bf->bf_mpdu; |
528f0c6b | 688 | tx_info = IEEE80211_SKB_CB(skb); |
e63835b0 | 689 | rates = tx_info->control.rates; |
528f0c6b | 690 | |
e8324357 S |
691 | /* |
692 | * Find the lowest frame length among the rate series that will have a | |
aa5955c3 | 693 | * 4ms (or TXOP limited) transmit duration. |
e8324357 S |
694 | */ |
695 | max_4ms_framelen = ATH_AMPDU_LIMIT_MAX; | |
e63835b0 | 696 | |
e8324357 | 697 | for (i = 0; i < 4; i++) { |
b0477013 | 698 | int modeidx; |
e8324357 | 699 | |
b0477013 FF |
700 | if (!rates[i].count) |
701 | continue; | |
545750d3 | 702 | |
b0477013 FF |
703 | if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) { |
704 | legacy = 1; | |
705 | break; | |
f078f209 | 706 | } |
b0477013 FF |
707 | |
708 | if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) | |
709 | modeidx = MCS_HT40; | |
710 | else | |
711 | modeidx = MCS_HT20; | |
712 | ||
713 | if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) | |
714 | modeidx++; | |
715 | ||
aa5955c3 | 716 | frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx]; |
b0477013 | 717 | max_4ms_framelen = min(max_4ms_framelen, frmlen); |
f078f209 | 718 | } |
e63835b0 | 719 | |
f078f209 | 720 | /* |
e8324357 S |
721 | * limit aggregate size by the minimum rate if rate selected is |
722 | * not a probe rate, if rate selected is a probe rate then | |
723 | * avoid aggregation of this packet. | |
f078f209 | 724 | */ |
e8324357 S |
725 | if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy) |
726 | return 0; | |
f078f209 | 727 | |
c0ac53fa SM |
728 | aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX); |
729 | ||
730 | /* | |
731 | * Override the default aggregation limit for BTCOEX. | |
732 | */ | |
733 | bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen); | |
734 | if (bt_aggr_limit) | |
735 | aggr_limit = bt_aggr_limit; | |
f078f209 | 736 | |
e8324357 | 737 | /* |
25985edc LDM |
738 | * h/w can accept aggregates up to 16 bit lengths (65535). |
739 | * The IE, however can hold up to 65536, which shows up here | |
e8324357 | 740 | * as zero. Ignore 65536 since we are constrained by hw. |
f078f209 | 741 | */ |
4ef70841 S |
742 | if (tid->an->maxampdu) |
743 | aggr_limit = min(aggr_limit, tid->an->maxampdu); | |
f078f209 | 744 | |
e8324357 S |
745 | return aggr_limit; |
746 | } | |
f078f209 | 747 | |
e8324357 | 748 | /* |
d43f3015 | 749 | * Returns the number of delimiters to be added to |
e8324357 | 750 | * meet the minimum required mpdudensity. |
e8324357 S |
751 | */ |
752 | static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid, | |
7a12dfdb RM |
753 | struct ath_buf *bf, u16 frmlen, |
754 | bool first_subfrm) | |
e8324357 | 755 | { |
7a12dfdb | 756 | #define FIRST_DESC_NDELIMS 60 |
4ef70841 | 757 | u32 nsymbits, nsymbols; |
e8324357 | 758 | u16 minlen; |
545750d3 | 759 | u8 flags, rix; |
c6663876 | 760 | int width, streams, half_gi, ndelim, mindelim; |
2d42efc4 | 761 | struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); |
e8324357 S |
762 | |
763 | /* Select standard number of delimiters based on frame length alone */ | |
764 | ndelim = ATH_AGGR_GET_NDELIM(frmlen); | |
f078f209 LR |
765 | |
766 | /* | |
e8324357 S |
767 | * If encryption enabled, hardware requires some more padding between |
768 | * subframes. | |
769 | * TODO - this could be improved to be dependent on the rate. | |
770 | * The hardware can keep up at lower rates, but not higher rates | |
f078f209 | 771 | */ |
4f6760b0 RM |
772 | if ((fi->keyix != ATH9K_TXKEYIX_INVALID) && |
773 | !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) | |
e8324357 | 774 | ndelim += ATH_AGGR_ENCRYPTDELIM; |
f078f209 | 775 | |
7a12dfdb RM |
776 | /* |
777 | * Add delimiter when using RTS/CTS with aggregation | |
778 | * and non enterprise AR9003 card | |
779 | */ | |
3459731a FF |
780 | if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) && |
781 | (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE)) | |
7a12dfdb RM |
782 | ndelim = max(ndelim, FIRST_DESC_NDELIMS); |
783 | ||
e8324357 S |
784 | /* |
785 | * Convert desired mpdu density from microeconds to bytes based | |
786 | * on highest rate in rate series (i.e. first rate) to determine | |
787 | * required minimum length for subframe. Take into account | |
788 | * whether high rate is 20 or 40Mhz and half or full GI. | |
4ef70841 | 789 | * |
e8324357 S |
790 | * If there is no mpdu density restriction, no further calculation |
791 | * is needed. | |
792 | */ | |
4ef70841 S |
793 | |
794 | if (tid->an->mpdudensity == 0) | |
e8324357 | 795 | return ndelim; |
f078f209 | 796 | |
79acac07 FF |
797 | rix = bf->rates[0].idx; |
798 | flags = bf->rates[0].flags; | |
e8324357 S |
799 | width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0; |
800 | half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0; | |
f078f209 | 801 | |
e8324357 | 802 | if (half_gi) |
4ef70841 | 803 | nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity); |
e8324357 | 804 | else |
4ef70841 | 805 | nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity); |
f078f209 | 806 | |
e8324357 S |
807 | if (nsymbols == 0) |
808 | nsymbols = 1; | |
f078f209 | 809 | |
c6663876 FF |
810 | streams = HT_RC_2_STREAMS(rix); |
811 | nsymbits = bits_per_symbol[rix % 8][width] * streams; | |
e8324357 | 812 | minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; |
f078f209 | 813 | |
e8324357 | 814 | if (frmlen < minlen) { |
e8324357 S |
815 | mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ; |
816 | ndelim = max(mindelim, ndelim); | |
f078f209 LR |
817 | } |
818 | ||
e8324357 | 819 | return ndelim; |
f078f209 LR |
820 | } |
821 | ||
e8324357 | 822 | static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc, |
fec247c0 | 823 | struct ath_txq *txq, |
d43f3015 | 824 | struct ath_atx_tid *tid, |
269c44bc FF |
825 | struct list_head *bf_q, |
826 | int *aggr_len) | |
f078f209 | 827 | { |
e8324357 | 828 | #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) |
56dc6336 | 829 | struct ath_buf *bf, *bf_first = NULL, *bf_prev = NULL; |
d43f3015 | 830 | int rl = 0, nframes = 0, ndelim, prev_al = 0; |
e8324357 S |
831 | u16 aggr_limit = 0, al = 0, bpad = 0, |
832 | al_delta, h_baw = tid->baw_size / 2; | |
833 | enum ATH_AGGR_STATUS status = ATH_AGGR_DONE; | |
0299a50a | 834 | struct ieee80211_tx_info *tx_info; |
2d42efc4 | 835 | struct ath_frame_info *fi; |
56dc6336 | 836 | struct sk_buff *skb; |
6a0ddaef | 837 | u16 seqno; |
f078f209 | 838 | |
e8324357 | 839 | do { |
56dc6336 FF |
840 | skb = skb_peek(&tid->buf_q); |
841 | fi = get_frame_info(skb); | |
842 | bf = fi->bf; | |
44f1d26c | 843 | if (!fi->bf) |
249ee722 | 844 | bf = ath_tx_setup_buffer(sc, txq, tid, skb); |
56dc6336 | 845 | |
249ee722 FF |
846 | if (!bf) { |
847 | __skb_unlink(skb, &tid->buf_q); | |
848 | ieee80211_free_txskb(sc->hw, skb); | |
44f1d26c | 849 | continue; |
249ee722 | 850 | } |
44f1d26c | 851 | |
399c6489 | 852 | bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR; |
44f1d26c | 853 | seqno = bf->bf_state.seqno; |
f078f209 | 854 | |
d43f3015 | 855 | /* do not step over block-ack window */ |
6a0ddaef | 856 | if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) { |
e8324357 S |
857 | status = ATH_AGGR_BAW_CLOSED; |
858 | break; | |
859 | } | |
f078f209 | 860 | |
f9437543 FF |
861 | if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) { |
862 | struct ath_tx_status ts = {}; | |
863 | struct list_head bf_head; | |
864 | ||
865 | INIT_LIST_HEAD(&bf_head); | |
866 | list_add(&bf->list, &bf_head); | |
867 | __skb_unlink(skb, &tid->buf_q); | |
868 | ath_tx_update_baw(sc, tid, seqno); | |
869 | ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0); | |
870 | continue; | |
871 | } | |
872 | ||
873 | if (!bf_first) | |
874 | bf_first = bf; | |
875 | ||
e8324357 | 876 | if (!rl) { |
79acac07 | 877 | ath_set_rates(tid->an->vif, tid->an->sta, bf); |
e8324357 S |
878 | aggr_limit = ath_lookup_rate(sc, bf, tid); |
879 | rl = 1; | |
880 | } | |
f078f209 | 881 | |
d43f3015 | 882 | /* do not exceed aggregation limit */ |
2d42efc4 | 883 | al_delta = ATH_AGGR_DELIM_SZ + fi->framelen; |
f078f209 | 884 | |
d43f3015 | 885 | if (nframes && |
1a6e9d0f RM |
886 | ((aggr_limit < (al + bpad + al_delta + prev_al)) || |
887 | ath_lookup_legacy(bf))) { | |
e8324357 S |
888 | status = ATH_AGGR_LIMITED; |
889 | break; | |
890 | } | |
f078f209 | 891 | |
0299a50a | 892 | tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); |
bdf2dbfb | 893 | if (nframes && (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) |
0299a50a FF |
894 | break; |
895 | ||
d43f3015 S |
896 | /* do not exceed subframe limit */ |
897 | if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) { | |
e8324357 S |
898 | status = ATH_AGGR_LIMITED; |
899 | break; | |
900 | } | |
f078f209 | 901 | |
d43f3015 | 902 | /* add padding for previous frame to aggregation length */ |
e8324357 | 903 | al += bpad + al_delta; |
f078f209 | 904 | |
e8324357 S |
905 | /* |
906 | * Get the delimiters needed to meet the MPDU | |
907 | * density for this node. | |
908 | */ | |
7a12dfdb RM |
909 | ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen, |
910 | !nframes); | |
e8324357 | 911 | bpad = PADBYTES(al_delta) + (ndelim << 2); |
f078f209 | 912 | |
7a12dfdb | 913 | nframes++; |
e8324357 | 914 | bf->bf_next = NULL; |
f078f209 | 915 | |
d43f3015 | 916 | /* link buffers of this frame to the aggregate */ |
2d42efc4 | 917 | if (!fi->retries) |
6a0ddaef | 918 | ath_tx_addto_baw(sc, tid, seqno); |
399c6489 | 919 | bf->bf_state.ndelim = ndelim; |
56dc6336 FF |
920 | |
921 | __skb_unlink(skb, &tid->buf_q); | |
922 | list_add_tail(&bf->list, bf_q); | |
399c6489 | 923 | if (bf_prev) |
e8324357 | 924 | bf_prev->bf_next = bf; |
399c6489 | 925 | |
e8324357 | 926 | bf_prev = bf; |
fec247c0 | 927 | |
56dc6336 | 928 | } while (!skb_queue_empty(&tid->buf_q)); |
f078f209 | 929 | |
269c44bc | 930 | *aggr_len = al; |
d43f3015 | 931 | |
e8324357 S |
932 | return status; |
933 | #undef PADBYTES | |
934 | } | |
f078f209 | 935 | |
38dad7ba FF |
936 | /* |
937 | * rix - rate index | |
938 | * pktlen - total bytes (delims + data + fcs + pads + pad delims) | |
939 | * width - 0 for 20 MHz, 1 for 40 MHz | |
940 | * half_gi - to use 4us v/s 3.6 us for symbol time | |
941 | */ | |
942 | static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen, | |
943 | int width, int half_gi, bool shortPreamble) | |
944 | { | |
945 | u32 nbits, nsymbits, duration, nsymbols; | |
946 | int streams; | |
947 | ||
948 | /* find number of symbols: PLCP + data */ | |
949 | streams = HT_RC_2_STREAMS(rix); | |
950 | nbits = (pktlen << 3) + OFDM_PLCP_BITS; | |
951 | nsymbits = bits_per_symbol[rix % 8][width] * streams; | |
952 | nsymbols = (nbits + nsymbits - 1) / nsymbits; | |
953 | ||
954 | if (!half_gi) | |
955 | duration = SYMBOL_TIME(nsymbols); | |
956 | else | |
957 | duration = SYMBOL_TIME_HALFGI(nsymbols); | |
958 | ||
959 | /* addup duration for legacy/ht training and signal fields */ | |
960 | duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); | |
961 | ||
962 | return duration; | |
963 | } | |
964 | ||
aa5955c3 FF |
965 | static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi) |
966 | { | |
967 | int streams = HT_RC_2_STREAMS(mcs); | |
968 | int symbols, bits; | |
969 | int bytes = 0; | |
970 | ||
971 | symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec); | |
972 | bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams; | |
973 | bits -= OFDM_PLCP_BITS; | |
974 | bytes = bits / 8; | |
975 | bytes -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); | |
976 | if (bytes > 65532) | |
977 | bytes = 65532; | |
978 | ||
979 | return bytes; | |
980 | } | |
981 | ||
982 | void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop) | |
983 | { | |
984 | u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi; | |
985 | int mcs; | |
986 | ||
987 | /* 4ms is the default (and maximum) duration */ | |
988 | if (!txop || txop > 4096) | |
989 | txop = 4096; | |
990 | ||
991 | cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20]; | |
992 | cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI]; | |
993 | cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40]; | |
994 | cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI]; | |
995 | for (mcs = 0; mcs < 32; mcs++) { | |
996 | cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false); | |
997 | cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true); | |
998 | cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false); | |
999 | cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true); | |
1000 | } | |
1001 | } | |
1002 | ||
493cf04f FF |
1003 | static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, |
1004 | struct ath_tx_info *info, int len) | |
38dad7ba FF |
1005 | { |
1006 | struct ath_hw *ah = sc->sc_ah; | |
38dad7ba FF |
1007 | struct sk_buff *skb; |
1008 | struct ieee80211_tx_info *tx_info; | |
1009 | struct ieee80211_tx_rate *rates; | |
1010 | const struct ieee80211_rate *rate; | |
1011 | struct ieee80211_hdr *hdr; | |
80b08a8d | 1012 | struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); |
493cf04f FF |
1013 | int i; |
1014 | u8 rix = 0; | |
38dad7ba FF |
1015 | |
1016 | skb = bf->bf_mpdu; | |
1017 | tx_info = IEEE80211_SKB_CB(skb); | |
79acac07 | 1018 | rates = bf->rates; |
38dad7ba | 1019 | hdr = (struct ieee80211_hdr *)skb->data; |
493cf04f FF |
1020 | |
1021 | /* set dur_update_en for l-sig computation except for PS-Poll frames */ | |
1022 | info->dur_update = !ieee80211_is_pspoll(hdr->frame_control); | |
80b08a8d | 1023 | info->rtscts_rate = fi->rtscts_rate; |
38dad7ba | 1024 | |
79acac07 | 1025 | for (i = 0; i < ARRAY_SIZE(bf->rates); i++) { |
38dad7ba FF |
1026 | bool is_40, is_sgi, is_sp; |
1027 | int phy; | |
1028 | ||
1029 | if (!rates[i].count || (rates[i].idx < 0)) | |
1030 | continue; | |
1031 | ||
1032 | rix = rates[i].idx; | |
493cf04f | 1033 | info->rates[i].Tries = rates[i].count; |
38dad7ba FF |
1034 | |
1035 | if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) { | |
493cf04f FF |
1036 | info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; |
1037 | info->flags |= ATH9K_TXDESC_RTSENA; | |
38dad7ba | 1038 | } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { |
493cf04f FF |
1039 | info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; |
1040 | info->flags |= ATH9K_TXDESC_CTSENA; | |
38dad7ba FF |
1041 | } |
1042 | ||
1043 | if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) | |
493cf04f | 1044 | info->rates[i].RateFlags |= ATH9K_RATESERIES_2040; |
38dad7ba | 1045 | if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) |
493cf04f | 1046 | info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI; |
38dad7ba FF |
1047 | |
1048 | is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI); | |
1049 | is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH); | |
1050 | is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE); | |
1051 | ||
1052 | if (rates[i].flags & IEEE80211_TX_RC_MCS) { | |
1053 | /* MCS rates */ | |
493cf04f FF |
1054 | info->rates[i].Rate = rix | 0x80; |
1055 | info->rates[i].ChSel = ath_txchainmask_reduction(sc, | |
1056 | ah->txchainmask, info->rates[i].Rate); | |
1057 | info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len, | |
38dad7ba FF |
1058 | is_40, is_sgi, is_sp); |
1059 | if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC)) | |
493cf04f | 1060 | info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC; |
38dad7ba FF |
1061 | continue; |
1062 | } | |
1063 | ||
1064 | /* legacy rates */ | |
76591bea | 1065 | rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx]; |
38dad7ba FF |
1066 | if ((tx_info->band == IEEE80211_BAND_2GHZ) && |
1067 | !(rate->flags & IEEE80211_RATE_ERP_G)) | |
1068 | phy = WLAN_RC_PHY_CCK; | |
1069 | else | |
1070 | phy = WLAN_RC_PHY_OFDM; | |
1071 | ||
493cf04f | 1072 | info->rates[i].Rate = rate->hw_value; |
38dad7ba FF |
1073 | if (rate->hw_value_short) { |
1074 | if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) | |
493cf04f | 1075 | info->rates[i].Rate |= rate->hw_value_short; |
38dad7ba FF |
1076 | } else { |
1077 | is_sp = false; | |
1078 | } | |
1079 | ||
1080 | if (bf->bf_state.bfs_paprd) | |
493cf04f | 1081 | info->rates[i].ChSel = ah->txchainmask; |
38dad7ba | 1082 | else |
493cf04f FF |
1083 | info->rates[i].ChSel = ath_txchainmask_reduction(sc, |
1084 | ah->txchainmask, info->rates[i].Rate); | |
38dad7ba | 1085 | |
493cf04f | 1086 | info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah, |
38dad7ba FF |
1087 | phy, rate->bitrate * 100, len, rix, is_sp); |
1088 | } | |
1089 | ||
1090 | /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ | |
1091 | if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit)) | |
493cf04f | 1092 | info->flags &= ~ATH9K_TXDESC_RTSENA; |
38dad7ba FF |
1093 | |
1094 | /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */ | |
493cf04f FF |
1095 | if (info->flags & ATH9K_TXDESC_RTSENA) |
1096 | info->flags &= ~ATH9K_TXDESC_CTSENA; | |
1097 | } | |
38dad7ba | 1098 | |
493cf04f FF |
1099 | static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb) |
1100 | { | |
1101 | struct ieee80211_hdr *hdr; | |
1102 | enum ath9k_pkt_type htype; | |
1103 | __le16 fc; | |
1104 | ||
1105 | hdr = (struct ieee80211_hdr *)skb->data; | |
1106 | fc = hdr->frame_control; | |
38dad7ba | 1107 | |
493cf04f FF |
1108 | if (ieee80211_is_beacon(fc)) |
1109 | htype = ATH9K_PKT_TYPE_BEACON; | |
1110 | else if (ieee80211_is_probe_resp(fc)) | |
1111 | htype = ATH9K_PKT_TYPE_PROBE_RESP; | |
1112 | else if (ieee80211_is_atim(fc)) | |
1113 | htype = ATH9K_PKT_TYPE_ATIM; | |
1114 | else if (ieee80211_is_pspoll(fc)) | |
1115 | htype = ATH9K_PKT_TYPE_PSPOLL; | |
1116 | else | |
1117 | htype = ATH9K_PKT_TYPE_NORMAL; | |
1118 | ||
1119 | return htype; | |
38dad7ba FF |
1120 | } |
1121 | ||
493cf04f FF |
1122 | static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf, |
1123 | struct ath_txq *txq, int len) | |
399c6489 FF |
1124 | { |
1125 | struct ath_hw *ah = sc->sc_ah; | |
1126 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); | |
1127 | struct ath_buf *bf_first = bf; | |
493cf04f | 1128 | struct ath_tx_info info; |
399c6489 | 1129 | bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR); |
399c6489 | 1130 | |
493cf04f FF |
1131 | memset(&info, 0, sizeof(info)); |
1132 | info.is_first = true; | |
1133 | info.is_last = true; | |
1134 | info.txpower = MAX_RATE_POWER; | |
1135 | info.qcu = txq->axq_qnum; | |
1136 | ||
1137 | info.flags = ATH9K_TXDESC_INTREQ; | |
1138 | if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) | |
1139 | info.flags |= ATH9K_TXDESC_NOACK; | |
1140 | if (tx_info->flags & IEEE80211_TX_CTL_LDPC) | |
1141 | info.flags |= ATH9K_TXDESC_LDPC; | |
1142 | ||
1143 | ath_buf_set_rate(sc, bf, &info, len); | |
1144 | ||
1145 | if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) | |
1146 | info.flags |= ATH9K_TXDESC_CLRDMASK; | |
1147 | ||
1148 | if (bf->bf_state.bfs_paprd) | |
1149 | info.flags |= (u32) bf->bf_state.bfs_paprd << ATH9K_TXDESC_PAPRD_S; | |
399c6489 | 1150 | |
399c6489 FF |
1151 | |
1152 | while (bf) { | |
493cf04f FF |
1153 | struct sk_buff *skb = bf->bf_mpdu; |
1154 | struct ath_frame_info *fi = get_frame_info(skb); | |
1155 | ||
1156 | info.type = get_hw_packet_type(skb); | |
399c6489 | 1157 | if (bf->bf_next) |
493cf04f | 1158 | info.link = bf->bf_next->bf_daddr; |
399c6489 | 1159 | else |
493cf04f FF |
1160 | info.link = 0; |
1161 | ||
42cecc34 JL |
1162 | info.buf_addr[0] = bf->bf_buf_addr; |
1163 | info.buf_len[0] = skb->len; | |
493cf04f FF |
1164 | info.pkt_len = fi->framelen; |
1165 | info.keyix = fi->keyix; | |
1166 | info.keytype = fi->keytype; | |
1167 | ||
1168 | if (aggr) { | |
399c6489 | 1169 | if (bf == bf_first) |
493cf04f FF |
1170 | info.aggr = AGGR_BUF_FIRST; |
1171 | else if (!bf->bf_next) | |
1172 | info.aggr = AGGR_BUF_LAST; | |
1173 | else | |
1174 | info.aggr = AGGR_BUF_MIDDLE; | |
399c6489 | 1175 | |
493cf04f FF |
1176 | info.ndelim = bf->bf_state.ndelim; |
1177 | info.aggr_len = len; | |
399c6489 FF |
1178 | } |
1179 | ||
493cf04f | 1180 | ath9k_hw_set_txdesc(ah, bf->bf_desc, &info); |
399c6489 FF |
1181 | bf = bf->bf_next; |
1182 | } | |
1183 | } | |
1184 | ||
e8324357 S |
1185 | static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq, |
1186 | struct ath_atx_tid *tid) | |
1187 | { | |
d43f3015 | 1188 | struct ath_buf *bf; |
e8324357 | 1189 | enum ATH_AGGR_STATUS status; |
399c6489 | 1190 | struct ieee80211_tx_info *tx_info; |
e8324357 | 1191 | struct list_head bf_q; |
269c44bc | 1192 | int aggr_len; |
f078f209 | 1193 | |
e8324357 | 1194 | do { |
56dc6336 | 1195 | if (skb_queue_empty(&tid->buf_q)) |
e8324357 | 1196 | return; |
f078f209 | 1197 | |
e8324357 S |
1198 | INIT_LIST_HEAD(&bf_q); |
1199 | ||
269c44bc | 1200 | status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len); |
f078f209 | 1201 | |
f078f209 | 1202 | /* |
d43f3015 S |
1203 | * no frames picked up to be aggregated; |
1204 | * block-ack window is not open. | |
f078f209 | 1205 | */ |
e8324357 S |
1206 | if (list_empty(&bf_q)) |
1207 | break; | |
f078f209 | 1208 | |
e8324357 | 1209 | bf = list_first_entry(&bf_q, struct ath_buf, list); |
d43f3015 | 1210 | bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list); |
399c6489 | 1211 | tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); |
f078f209 | 1212 | |
5519541d FF |
1213 | if (tid->ac->clear_ps_filter) { |
1214 | tid->ac->clear_ps_filter = false; | |
399c6489 FF |
1215 | tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT; |
1216 | } else { | |
1217 | tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT; | |
5519541d FF |
1218 | } |
1219 | ||
d43f3015 | 1220 | /* if only one frame, send as non-aggregate */ |
b572d033 | 1221 | if (bf == bf->bf_lastbf) { |
399c6489 FF |
1222 | aggr_len = get_frame_info(bf->bf_mpdu)->framelen; |
1223 | bf->bf_state.bf_type = BUF_AMPDU; | |
1224 | } else { | |
1225 | TX_STAT_INC(txq->axq_qnum, a_aggr); | |
e8324357 | 1226 | } |
f078f209 | 1227 | |
493cf04f | 1228 | ath_tx_fill_desc(sc, bf, txq, aggr_len); |
fce041be | 1229 | ath_tx_txqaddbuf(sc, txq, &bf_q, false); |
4b3ba66a | 1230 | } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH && |
e8324357 S |
1231 | status != ATH_AGGR_BAW_CLOSED); |
1232 | } | |
1233 | ||
231c3a1f FF |
1234 | int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, |
1235 | u16 tid, u16 *ssn) | |
e8324357 S |
1236 | { |
1237 | struct ath_atx_tid *txtid; | |
1238 | struct ath_node *an; | |
313eb87f | 1239 | u8 density; |
e8324357 S |
1240 | |
1241 | an = (struct ath_node *)sta->drv_priv; | |
f83da965 | 1242 | txtid = ATH_AN_2_TID(an, tid); |
231c3a1f FF |
1243 | |
1244 | if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE)) | |
1245 | return -EAGAIN; | |
1246 | ||
313eb87f SE |
1247 | /* update ampdu factor/density, they may have changed. This may happen |
1248 | * in HT IBSS when a beacon with HT-info is received after the station | |
1249 | * has already been added. | |
1250 | */ | |
dd5ee59b | 1251 | if (sta->ht_cap.ht_supported) { |
313eb87f SE |
1252 | an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + |
1253 | sta->ht_cap.ampdu_factor); | |
1254 | density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density); | |
1255 | an->mpdudensity = density; | |
1256 | } | |
1257 | ||
f83da965 | 1258 | txtid->state |= AGGR_ADDBA_PROGRESS; |
75401849 | 1259 | txtid->paused = true; |
49447f2f | 1260 | *ssn = txtid->seq_start = txtid->seq_next; |
f9437543 | 1261 | txtid->bar_index = -1; |
231c3a1f | 1262 | |
2ed72229 FF |
1263 | memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf)); |
1264 | txtid->baw_head = txtid->baw_tail = 0; | |
1265 | ||
231c3a1f | 1266 | return 0; |
e8324357 | 1267 | } |
f078f209 | 1268 | |
16e23428 FF |
1269 | bool ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid, |
1270 | bool flush) | |
e8324357 S |
1271 | { |
1272 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
1273 | struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid); | |
066dae93 | 1274 | struct ath_txq *txq = txtid->ac->txq; |
16e23428 FF |
1275 | bool ret = !flush; |
1276 | ||
1277 | if (flush) | |
1278 | txtid->stop_cb = false; | |
f078f209 | 1279 | |
e8324357 | 1280 | if (txtid->state & AGGR_CLEANUP) |
16e23428 | 1281 | return false; |
f078f209 | 1282 | |
e8324357 | 1283 | if (!(txtid->state & AGGR_ADDBA_COMPLETE)) { |
5eae6592 | 1284 | txtid->state &= ~AGGR_ADDBA_PROGRESS; |
16e23428 | 1285 | return ret; |
e8324357 | 1286 | } |
f078f209 | 1287 | |
23de5dc9 | 1288 | ath_txq_lock(sc, txq); |
75401849 | 1289 | txtid->paused = true; |
f078f209 | 1290 | |
90fa539c FF |
1291 | /* |
1292 | * If frames are still being transmitted for this TID, they will be | |
1293 | * cleaned up during tx completion. To prevent race conditions, this | |
1294 | * TID can only be reused after all in-progress subframes have been | |
1295 | * completed. | |
1296 | */ | |
16e23428 | 1297 | if (txtid->baw_head != txtid->baw_tail) { |
e8324357 | 1298 | txtid->state |= AGGR_CLEANUP; |
16e23428 FF |
1299 | ret = false; |
1300 | txtid->stop_cb = !flush; | |
1301 | } else { | |
e8324357 | 1302 | txtid->state &= ~AGGR_ADDBA_COMPLETE; |
16e23428 | 1303 | } |
90fa539c | 1304 | |
16e23428 | 1305 | ath_tx_flush_tid(sc, txtid, flush); |
23de5dc9 | 1306 | ath_txq_unlock_complete(sc, txq); |
16e23428 | 1307 | return ret; |
e8324357 | 1308 | } |
f078f209 | 1309 | |
042ec453 JB |
1310 | void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc, |
1311 | struct ath_node *an) | |
5519541d FF |
1312 | { |
1313 | struct ath_atx_tid *tid; | |
1314 | struct ath_atx_ac *ac; | |
1315 | struct ath_txq *txq; | |
042ec453 | 1316 | bool buffered; |
5519541d FF |
1317 | int tidno; |
1318 | ||
1319 | for (tidno = 0, tid = &an->tid[tidno]; | |
de7b7604 | 1320 | tidno < IEEE80211_NUM_TIDS; tidno++, tid++) { |
5519541d FF |
1321 | |
1322 | if (!tid->sched) | |
1323 | continue; | |
1324 | ||
1325 | ac = tid->ac; | |
1326 | txq = ac->txq; | |
1327 | ||
23de5dc9 | 1328 | ath_txq_lock(sc, txq); |
5519541d | 1329 | |
042ec453 | 1330 | buffered = !skb_queue_empty(&tid->buf_q); |
5519541d FF |
1331 | |
1332 | tid->sched = false; | |
1333 | list_del(&tid->list); | |
1334 | ||
1335 | if (ac->sched) { | |
1336 | ac->sched = false; | |
1337 | list_del(&ac->list); | |
1338 | } | |
1339 | ||
23de5dc9 | 1340 | ath_txq_unlock(sc, txq); |
5519541d | 1341 | |
042ec453 JB |
1342 | ieee80211_sta_set_buffered(sta, tidno, buffered); |
1343 | } | |
5519541d FF |
1344 | } |
1345 | ||
1346 | void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an) | |
1347 | { | |
1348 | struct ath_atx_tid *tid; | |
1349 | struct ath_atx_ac *ac; | |
1350 | struct ath_txq *txq; | |
1351 | int tidno; | |
1352 | ||
1353 | for (tidno = 0, tid = &an->tid[tidno]; | |
de7b7604 | 1354 | tidno < IEEE80211_NUM_TIDS; tidno++, tid++) { |
5519541d FF |
1355 | |
1356 | ac = tid->ac; | |
1357 | txq = ac->txq; | |
1358 | ||
23de5dc9 | 1359 | ath_txq_lock(sc, txq); |
5519541d FF |
1360 | ac->clear_ps_filter = true; |
1361 | ||
56dc6336 | 1362 | if (!skb_queue_empty(&tid->buf_q) && !tid->paused) { |
5519541d FF |
1363 | ath_tx_queue_tid(txq, tid); |
1364 | ath_txq_schedule(sc, txq); | |
1365 | } | |
1366 | ||
23de5dc9 | 1367 | ath_txq_unlock_complete(sc, txq); |
5519541d FF |
1368 | } |
1369 | } | |
1370 | ||
e8324357 S |
1371 | void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) |
1372 | { | |
1373 | struct ath_atx_tid *txtid; | |
1374 | struct ath_node *an; | |
1375 | ||
1376 | an = (struct ath_node *)sta->drv_priv; | |
1377 | ||
3d4e20f2 SM |
1378 | txtid = ATH_AN_2_TID(an, tid); |
1379 | txtid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor; | |
1380 | txtid->state |= AGGR_ADDBA_COMPLETE; | |
1381 | txtid->state &= ~AGGR_ADDBA_PROGRESS; | |
1382 | ath_tx_resume_tid(sc, txtid); | |
f078f209 LR |
1383 | } |
1384 | ||
e8324357 S |
1385 | /********************/ |
1386 | /* Queue Management */ | |
1387 | /********************/ | |
f078f209 | 1388 | |
e8324357 | 1389 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) |
f078f209 | 1390 | { |
cbe61d8a | 1391 | struct ath_hw *ah = sc->sc_ah; |
e8324357 | 1392 | struct ath9k_tx_queue_info qi; |
066dae93 | 1393 | static const int subtype_txq_to_hwq[] = { |
bea843c7 SM |
1394 | [IEEE80211_AC_BE] = ATH_TXQ_AC_BE, |
1395 | [IEEE80211_AC_BK] = ATH_TXQ_AC_BK, | |
1396 | [IEEE80211_AC_VI] = ATH_TXQ_AC_VI, | |
1397 | [IEEE80211_AC_VO] = ATH_TXQ_AC_VO, | |
066dae93 | 1398 | }; |
60f2d1d5 | 1399 | int axq_qnum, i; |
f078f209 | 1400 | |
e8324357 | 1401 | memset(&qi, 0, sizeof(qi)); |
066dae93 | 1402 | qi.tqi_subtype = subtype_txq_to_hwq[subtype]; |
e8324357 S |
1403 | qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT; |
1404 | qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT; | |
1405 | qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT; | |
1406 | qi.tqi_physCompBuf = 0; | |
f078f209 LR |
1407 | |
1408 | /* | |
e8324357 S |
1409 | * Enable interrupts only for EOL and DESC conditions. |
1410 | * We mark tx descriptors to receive a DESC interrupt | |
1411 | * when a tx queue gets deep; otherwise waiting for the | |
1412 | * EOL to reap descriptors. Note that this is done to | |
1413 | * reduce interrupt load and this only defers reaping | |
1414 | * descriptors, never transmitting frames. Aside from | |
1415 | * reducing interrupts this also permits more concurrency. | |
1416 | * The only potential downside is if the tx queue backs | |
1417 | * up in which case the top half of the kernel may backup | |
1418 | * due to a lack of tx descriptors. | |
1419 | * | |
1420 | * The UAPSD queue is an exception, since we take a desc- | |
1421 | * based intr on the EOSP frames. | |
f078f209 | 1422 | */ |
afe754d6 | 1423 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
ce8fdf6e | 1424 | qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE; |
afe754d6 VT |
1425 | } else { |
1426 | if (qtype == ATH9K_TX_QUEUE_UAPSD) | |
1427 | qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; | |
1428 | else | |
1429 | qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | | |
1430 | TXQ_FLAG_TXDESCINT_ENABLE; | |
1431 | } | |
60f2d1d5 BG |
1432 | axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); |
1433 | if (axq_qnum == -1) { | |
f078f209 | 1434 | /* |
e8324357 S |
1435 | * NB: don't print a message, this happens |
1436 | * normally on parts with too few tx queues | |
f078f209 | 1437 | */ |
e8324357 | 1438 | return NULL; |
f078f209 | 1439 | } |
60f2d1d5 BG |
1440 | if (!ATH_TXQ_SETUP(sc, axq_qnum)) { |
1441 | struct ath_txq *txq = &sc->tx.txq[axq_qnum]; | |
f078f209 | 1442 | |
60f2d1d5 BG |
1443 | txq->axq_qnum = axq_qnum; |
1444 | txq->mac80211_qnum = -1; | |
e8324357 | 1445 | txq->axq_link = NULL; |
23de5dc9 | 1446 | __skb_queue_head_init(&txq->complete_q); |
e8324357 S |
1447 | INIT_LIST_HEAD(&txq->axq_q); |
1448 | INIT_LIST_HEAD(&txq->axq_acq); | |
1449 | spin_lock_init(&txq->axq_lock); | |
1450 | txq->axq_depth = 0; | |
4b3ba66a | 1451 | txq->axq_ampdu_depth = 0; |
164ace38 | 1452 | txq->axq_tx_inprogress = false; |
60f2d1d5 | 1453 | sc->tx.txqsetup |= 1<<axq_qnum; |
e5003249 VT |
1454 | |
1455 | txq->txq_headidx = txq->txq_tailidx = 0; | |
1456 | for (i = 0; i < ATH_TXFIFO_DEPTH; i++) | |
1457 | INIT_LIST_HEAD(&txq->txq_fifo[i]); | |
e8324357 | 1458 | } |
60f2d1d5 | 1459 | return &sc->tx.txq[axq_qnum]; |
f078f209 LR |
1460 | } |
1461 | ||
e8324357 S |
1462 | int ath_txq_update(struct ath_softc *sc, int qnum, |
1463 | struct ath9k_tx_queue_info *qinfo) | |
1464 | { | |
cbe61d8a | 1465 | struct ath_hw *ah = sc->sc_ah; |
e8324357 S |
1466 | int error = 0; |
1467 | struct ath9k_tx_queue_info qi; | |
1468 | ||
9680e8a3 | 1469 | BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum); |
e8324357 S |
1470 | |
1471 | ath9k_hw_get_txq_props(ah, qnum, &qi); | |
1472 | qi.tqi_aifs = qinfo->tqi_aifs; | |
1473 | qi.tqi_cwmin = qinfo->tqi_cwmin; | |
1474 | qi.tqi_cwmax = qinfo->tqi_cwmax; | |
1475 | qi.tqi_burstTime = qinfo->tqi_burstTime; | |
1476 | qi.tqi_readyTime = qinfo->tqi_readyTime; | |
1477 | ||
1478 | if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { | |
3800276a JP |
1479 | ath_err(ath9k_hw_common(sc->sc_ah), |
1480 | "Unable to update hardware queue %u!\n", qnum); | |
e8324357 S |
1481 | error = -EIO; |
1482 | } else { | |
1483 | ath9k_hw_resettxqueue(ah, qnum); | |
1484 | } | |
1485 | ||
1486 | return error; | |
1487 | } | |
1488 | ||
1489 | int ath_cabq_update(struct ath_softc *sc) | |
1490 | { | |
1491 | struct ath9k_tx_queue_info qi; | |
9814f6b3 | 1492 | struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf; |
e8324357 | 1493 | int qnum = sc->beacon.cabq->axq_qnum; |
f078f209 | 1494 | |
e8324357 | 1495 | ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi); |
f078f209 | 1496 | /* |
e8324357 | 1497 | * Ensure the readytime % is within the bounds. |
f078f209 | 1498 | */ |
17d7904d S |
1499 | if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND) |
1500 | sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND; | |
1501 | else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND) | |
1502 | sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND; | |
f078f209 | 1503 | |
9814f6b3 | 1504 | qi.tqi_readyTime = (cur_conf->beacon_interval * |
fdbf7335 | 1505 | sc->config.cabqReadytime) / 100; |
e8324357 S |
1506 | ath_txq_update(sc, qnum, &qi); |
1507 | ||
1508 | return 0; | |
f078f209 LR |
1509 | } |
1510 | ||
fce041be | 1511 | static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq, |
1381559b | 1512 | struct list_head *list) |
f078f209 | 1513 | { |
e8324357 S |
1514 | struct ath_buf *bf, *lastbf; |
1515 | struct list_head bf_head; | |
db1a052b FF |
1516 | struct ath_tx_status ts; |
1517 | ||
1518 | memset(&ts, 0, sizeof(ts)); | |
daa5c408 | 1519 | ts.ts_status = ATH9K_TX_FLUSH; |
e8324357 | 1520 | INIT_LIST_HEAD(&bf_head); |
f078f209 | 1521 | |
fce041be FF |
1522 | while (!list_empty(list)) { |
1523 | bf = list_first_entry(list, struct ath_buf, list); | |
f078f209 | 1524 | |
fce041be FF |
1525 | if (bf->bf_stale) { |
1526 | list_del(&bf->list); | |
f078f209 | 1527 | |
fce041be FF |
1528 | ath_tx_return_buffer(sc, bf); |
1529 | continue; | |
e8324357 | 1530 | } |
f078f209 | 1531 | |
e8324357 | 1532 | lastbf = bf->bf_lastbf; |
fce041be | 1533 | list_cut_position(&bf_head, list, &lastbf->list); |
81b51950 | 1534 | ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); |
f078f209 | 1535 | } |
fce041be | 1536 | } |
f078f209 | 1537 | |
fce041be FF |
1538 | /* |
1539 | * Drain a given TX queue (could be Beacon or Data) | |
1540 | * | |
1541 | * This assumes output has been stopped and | |
1542 | * we do not need to block ath_tx_tasklet. | |
1543 | */ | |
1381559b | 1544 | void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq) |
fce041be | 1545 | { |
23de5dc9 FF |
1546 | ath_txq_lock(sc, txq); |
1547 | ||
e5003249 | 1548 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
fce041be | 1549 | int idx = txq->txq_tailidx; |
e5003249 | 1550 | |
fce041be | 1551 | while (!list_empty(&txq->txq_fifo[idx])) { |
1381559b | 1552 | ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]); |
fce041be FF |
1553 | |
1554 | INCR(idx, ATH_TXFIFO_DEPTH); | |
e5003249 | 1555 | } |
fce041be | 1556 | txq->txq_tailidx = idx; |
e5003249 | 1557 | } |
e609e2ea | 1558 | |
fce041be FF |
1559 | txq->axq_link = NULL; |
1560 | txq->axq_tx_inprogress = false; | |
1381559b | 1561 | ath_drain_txq_list(sc, txq, &txq->axq_q); |
fce041be | 1562 | |
23de5dc9 | 1563 | ath_txq_unlock_complete(sc, txq); |
f078f209 LR |
1564 | } |
1565 | ||
1381559b | 1566 | bool ath_drain_all_txq(struct ath_softc *sc) |
f078f209 | 1567 | { |
cbe61d8a | 1568 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1569 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
043a0405 | 1570 | struct ath_txq *txq; |
34d25810 FF |
1571 | int i; |
1572 | u32 npend = 0; | |
043a0405 | 1573 | |
781b14a3 | 1574 | if (test_bit(SC_OP_INVALID, &sc->sc_flags)) |
080e1a25 | 1575 | return true; |
043a0405 | 1576 | |
0d51cccc | 1577 | ath9k_hw_abort_tx_dma(ah); |
043a0405 | 1578 | |
0d51cccc | 1579 | /* Check if any queue remains active */ |
043a0405 | 1580 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
0d51cccc FF |
1581 | if (!ATH_TXQ_SETUP(sc, i)) |
1582 | continue; | |
1583 | ||
34d25810 FF |
1584 | if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum)) |
1585 | npend |= BIT(i); | |
043a0405 S |
1586 | } |
1587 | ||
080e1a25 | 1588 | if (npend) |
34d25810 | 1589 | ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend); |
043a0405 S |
1590 | |
1591 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
92460412 FF |
1592 | if (!ATH_TXQ_SETUP(sc, i)) |
1593 | continue; | |
1594 | ||
1595 | /* | |
1596 | * The caller will resume queues with ieee80211_wake_queues. | |
1597 | * Mark the queue as not stopped to prevent ath_tx_complete | |
1598 | * from waking the queue too early. | |
1599 | */ | |
1600 | txq = &sc->tx.txq[i]; | |
1601 | txq->stopped = false; | |
1381559b | 1602 | ath_draintxq(sc, txq); |
043a0405 | 1603 | } |
080e1a25 FF |
1604 | |
1605 | return !npend; | |
e8324357 | 1606 | } |
f078f209 | 1607 | |
043a0405 | 1608 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) |
e8324357 | 1609 | { |
043a0405 S |
1610 | ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum); |
1611 | sc->tx.txqsetup &= ~(1<<txq->axq_qnum); | |
e8324357 | 1612 | } |
f078f209 | 1613 | |
7755bad9 BG |
1614 | /* For each axq_acq entry, for each tid, try to schedule packets |
1615 | * for transmit until ampdu_depth has reached min Q depth. | |
1616 | */ | |
e8324357 S |
1617 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) |
1618 | { | |
7755bad9 BG |
1619 | struct ath_atx_ac *ac, *ac_tmp, *last_ac; |
1620 | struct ath_atx_tid *tid, *last_tid; | |
f078f209 | 1621 | |
124b979b RM |
1622 | if (test_bit(SC_OP_HW_RESET, &sc->sc_flags) || |
1623 | list_empty(&txq->axq_acq) || | |
21f28e6f | 1624 | txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) |
e8324357 | 1625 | return; |
f078f209 | 1626 | |
e8324357 | 1627 | ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list); |
7755bad9 | 1628 | last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list); |
f078f209 | 1629 | |
7755bad9 BG |
1630 | list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) { |
1631 | last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list); | |
1632 | list_del(&ac->list); | |
1633 | ac->sched = false; | |
f078f209 | 1634 | |
7755bad9 BG |
1635 | while (!list_empty(&ac->tid_q)) { |
1636 | tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, | |
1637 | list); | |
1638 | list_del(&tid->list); | |
1639 | tid->sched = false; | |
f078f209 | 1640 | |
7755bad9 BG |
1641 | if (tid->paused) |
1642 | continue; | |
f078f209 | 1643 | |
7755bad9 | 1644 | ath_tx_sched_aggr(sc, txq, tid); |
f078f209 | 1645 | |
7755bad9 BG |
1646 | /* |
1647 | * add tid to round-robin queue if more frames | |
1648 | * are pending for the tid | |
1649 | */ | |
56dc6336 | 1650 | if (!skb_queue_empty(&tid->buf_q)) |
7755bad9 | 1651 | ath_tx_queue_tid(txq, tid); |
f078f209 | 1652 | |
7755bad9 BG |
1653 | if (tid == last_tid || |
1654 | txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) | |
1655 | break; | |
1656 | } | |
f078f209 | 1657 | |
b0477013 FF |
1658 | if (!list_empty(&ac->tid_q) && !ac->sched) { |
1659 | ac->sched = true; | |
1660 | list_add_tail(&ac->list, &txq->axq_acq); | |
f078f209 | 1661 | } |
7755bad9 BG |
1662 | |
1663 | if (ac == last_ac || | |
1664 | txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) | |
1665 | return; | |
e8324357 S |
1666 | } |
1667 | } | |
f078f209 | 1668 | |
e8324357 S |
1669 | /***********/ |
1670 | /* TX, DMA */ | |
1671 | /***********/ | |
1672 | ||
f078f209 | 1673 | /* |
e8324357 S |
1674 | * Insert a chain of ath_buf (descriptors) on a txq and |
1675 | * assume the descriptors are already chained together by caller. | |
f078f209 | 1676 | */ |
e8324357 | 1677 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, |
fce041be | 1678 | struct list_head *head, bool internal) |
f078f209 | 1679 | { |
cbe61d8a | 1680 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1681 | struct ath_common *common = ath9k_hw_common(ah); |
fce041be FF |
1682 | struct ath_buf *bf, *bf_last; |
1683 | bool puttxbuf = false; | |
1684 | bool edma; | |
f078f209 | 1685 | |
e8324357 S |
1686 | /* |
1687 | * Insert the frame on the outbound list and | |
1688 | * pass it on to the hardware. | |
1689 | */ | |
f078f209 | 1690 | |
e8324357 S |
1691 | if (list_empty(head)) |
1692 | return; | |
f078f209 | 1693 | |
fce041be | 1694 | edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); |
e8324357 | 1695 | bf = list_first_entry(head, struct ath_buf, list); |
fce041be | 1696 | bf_last = list_entry(head->prev, struct ath_buf, list); |
f078f209 | 1697 | |
d2182b69 JP |
1698 | ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n", |
1699 | txq->axq_qnum, txq->axq_depth); | |
f078f209 | 1700 | |
fce041be FF |
1701 | if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) { |
1702 | list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]); | |
e5003249 | 1703 | INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH); |
fce041be | 1704 | puttxbuf = true; |
e8324357 | 1705 | } else { |
e5003249 VT |
1706 | list_splice_tail_init(head, &txq->axq_q); |
1707 | ||
fce041be FF |
1708 | if (txq->axq_link) { |
1709 | ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr); | |
d2182b69 | 1710 | ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n", |
226afe68 JP |
1711 | txq->axq_qnum, txq->axq_link, |
1712 | ito64(bf->bf_daddr), bf->bf_desc); | |
fce041be FF |
1713 | } else if (!edma) |
1714 | puttxbuf = true; | |
1715 | ||
1716 | txq->axq_link = bf_last->bf_desc; | |
1717 | } | |
1718 | ||
1719 | if (puttxbuf) { | |
1720 | TX_STAT_INC(txq->axq_qnum, puttxbuf); | |
1721 | ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); | |
d2182b69 | 1722 | ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n", |
fce041be FF |
1723 | txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); |
1724 | } | |
1725 | ||
1726 | if (!edma) { | |
8d8d3fdc | 1727 | TX_STAT_INC(txq->axq_qnum, txstart); |
e5003249 | 1728 | ath9k_hw_txstart(ah, txq->axq_qnum); |
e8324357 | 1729 | } |
fce041be FF |
1730 | |
1731 | if (!internal) { | |
1732 | txq->axq_depth++; | |
1733 | if (bf_is_ampdu_not_probing(bf)) | |
1734 | txq->axq_ampdu_depth++; | |
1735 | } | |
e8324357 | 1736 | } |
f078f209 | 1737 | |
e8324357 | 1738 | static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid, |
44f1d26c | 1739 | struct sk_buff *skb, struct ath_tx_control *txctl) |
f078f209 | 1740 | { |
44f1d26c | 1741 | struct ath_frame_info *fi = get_frame_info(skb); |
04caf863 | 1742 | struct list_head bf_head; |
44f1d26c | 1743 | struct ath_buf *bf; |
f078f209 | 1744 | |
e8324357 S |
1745 | /* |
1746 | * Do not queue to h/w when any of the following conditions is true: | |
1747 | * - there are pending frames in software queue | |
1748 | * - the TID is currently paused for ADDBA/BAR request | |
1749 | * - seqno is not within block-ack window | |
1750 | * - h/w queue depth exceeds low water mark | |
1751 | */ | |
56dc6336 | 1752 | if (!skb_queue_empty(&tid->buf_q) || tid->paused || |
44f1d26c | 1753 | !BAW_WITHIN(tid->seq_start, tid->baw_size, tid->seq_next) || |
4b3ba66a | 1754 | txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) { |
f078f209 | 1755 | /* |
e8324357 S |
1756 | * Add this frame to software queue for scheduling later |
1757 | * for aggregation. | |
f078f209 | 1758 | */ |
bda8adda | 1759 | TX_STAT_INC(txctl->txq->axq_qnum, a_queued_sw); |
44f1d26c | 1760 | __skb_queue_tail(&tid->buf_q, skb); |
9af73cf7 FF |
1761 | if (!txctl->an || !txctl->an->sleeping) |
1762 | ath_tx_queue_tid(txctl->txq, tid); | |
e8324357 S |
1763 | return; |
1764 | } | |
1765 | ||
249ee722 FF |
1766 | bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb); |
1767 | if (!bf) { | |
1768 | ieee80211_free_txskb(sc->hw, skb); | |
44f1d26c | 1769 | return; |
249ee722 | 1770 | } |
44f1d26c | 1771 | |
79acac07 | 1772 | ath_set_rates(tid->an->vif, tid->an->sta, bf); |
399c6489 | 1773 | bf->bf_state.bf_type = BUF_AMPDU; |
04caf863 FF |
1774 | INIT_LIST_HEAD(&bf_head); |
1775 | list_add(&bf->list, &bf_head); | |
1776 | ||
e8324357 | 1777 | /* Add sub-frame to BAW */ |
44f1d26c | 1778 | ath_tx_addto_baw(sc, tid, bf->bf_state.seqno); |
e8324357 S |
1779 | |
1780 | /* Queue to h/w without aggregation */ | |
bda8adda | 1781 | TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw); |
d43f3015 | 1782 | bf->bf_lastbf = bf; |
493cf04f | 1783 | ath_tx_fill_desc(sc, bf, txctl->txq, fi->framelen); |
fce041be | 1784 | ath_tx_txqaddbuf(sc, txctl->txq, &bf_head, false); |
e8324357 S |
1785 | } |
1786 | ||
82b873af | 1787 | static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, |
44f1d26c | 1788 | struct ath_atx_tid *tid, struct sk_buff *skb) |
e8324357 | 1789 | { |
44f1d26c FF |
1790 | struct ath_frame_info *fi = get_frame_info(skb); |
1791 | struct list_head bf_head; | |
e8324357 S |
1792 | struct ath_buf *bf; |
1793 | ||
44f1d26c | 1794 | bf = fi->bf; |
44f1d26c FF |
1795 | |
1796 | INIT_LIST_HEAD(&bf_head); | |
1797 | list_add_tail(&bf->list, &bf_head); | |
399c6489 | 1798 | bf->bf_state.bf_type = 0; |
e8324357 | 1799 | |
8c6e3093 | 1800 | bf->bf_next = NULL; |
d43f3015 | 1801 | bf->bf_lastbf = bf; |
493cf04f | 1802 | ath_tx_fill_desc(sc, bf, txq, fi->framelen); |
44f1d26c | 1803 | ath_tx_txqaddbuf(sc, txq, &bf_head, false); |
fec247c0 | 1804 | TX_STAT_INC(txq->axq_qnum, queued); |
e8324357 S |
1805 | } |
1806 | ||
36323f81 TH |
1807 | static void setup_frame_info(struct ieee80211_hw *hw, |
1808 | struct ieee80211_sta *sta, | |
1809 | struct sk_buff *skb, | |
2d42efc4 | 1810 | int framelen) |
e8324357 S |
1811 | { |
1812 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
2d42efc4 | 1813 | struct ieee80211_key_conf *hw_key = tx_info->control.hw_key; |
6a0ddaef | 1814 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
80b08a8d | 1815 | const struct ieee80211_rate *rate; |
2d42efc4 | 1816 | struct ath_frame_info *fi = get_frame_info(skb); |
93ae2dd2 | 1817 | struct ath_node *an = NULL; |
2d42efc4 | 1818 | enum ath9k_key_type keytype; |
80b08a8d FF |
1819 | bool short_preamble = false; |
1820 | ||
1821 | /* | |
1822 | * We check if Short Preamble is needed for the CTS rate by | |
1823 | * checking the BSS's global flag. | |
1824 | * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used. | |
1825 | */ | |
1826 | if (tx_info->control.vif && | |
1827 | tx_info->control.vif->bss_conf.use_short_preamble) | |
1828 | short_preamble = true; | |
e8324357 | 1829 | |
80b08a8d | 1830 | rate = ieee80211_get_rts_cts_rate(hw, tx_info); |
2d42efc4 | 1831 | keytype = ath9k_cmn_get_hw_crypto_keytype(skb); |
e8324357 | 1832 | |
93ae2dd2 FF |
1833 | if (sta) |
1834 | an = (struct ath_node *) sta->drv_priv; | |
1835 | ||
2d42efc4 FF |
1836 | memset(fi, 0, sizeof(*fi)); |
1837 | if (hw_key) | |
1838 | fi->keyix = hw_key->hw_key_idx; | |
93ae2dd2 FF |
1839 | else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0) |
1840 | fi->keyix = an->ps_key; | |
2d42efc4 FF |
1841 | else |
1842 | fi->keyix = ATH9K_TXKEYIX_INVALID; | |
1843 | fi->keytype = keytype; | |
1844 | fi->framelen = framelen; | |
80b08a8d FF |
1845 | fi->rtscts_rate = rate->hw_value; |
1846 | if (short_preamble) | |
1847 | fi->rtscts_rate |= rate->hw_value_short; | |
e8324357 S |
1848 | } |
1849 | ||
ea066d5a MSS |
1850 | u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate) |
1851 | { | |
1852 | struct ath_hw *ah = sc->sc_ah; | |
1853 | struct ath9k_channel *curchan = ah->curchan; | |
365d2ebc | 1854 | |
d77bf3eb RM |
1855 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && |
1856 | (curchan->channelFlags & CHANNEL_5GHZ) && | |
1857 | (chainmask == 0x7) && (rate < 0x90)) | |
ea066d5a | 1858 | return 0x3; |
365d2ebc SM |
1859 | else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) && |
1860 | IS_CCK_RATE(rate)) | |
1861 | return 0x2; | |
ea066d5a MSS |
1862 | else |
1863 | return chainmask; | |
1864 | } | |
1865 | ||
44f1d26c FF |
1866 | /* |
1867 | * Assign a descriptor (and sequence number if necessary, | |
1868 | * and map buffer for DMA. Frees skb on error | |
1869 | */ | |
fa05f87a | 1870 | static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, |
04caf863 | 1871 | struct ath_txq *txq, |
fa05f87a | 1872 | struct ath_atx_tid *tid, |
249ee722 | 1873 | struct sk_buff *skb) |
f078f209 | 1874 | { |
82b873af | 1875 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
2d42efc4 | 1876 | struct ath_frame_info *fi = get_frame_info(skb); |
fa05f87a | 1877 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
82b873af | 1878 | struct ath_buf *bf; |
fd09c85f | 1879 | int fragno; |
fa05f87a | 1880 | u16 seqno; |
82b873af FF |
1881 | |
1882 | bf = ath_tx_get_buffer(sc); | |
1883 | if (!bf) { | |
d2182b69 | 1884 | ath_dbg(common, XMIT, "TX buffers are full\n"); |
249ee722 | 1885 | return NULL; |
82b873af | 1886 | } |
e022edbd | 1887 | |
528f0c6b | 1888 | ATH_TXBUF_RESET(bf); |
f078f209 | 1889 | |
fa05f87a | 1890 | if (tid) { |
fd09c85f | 1891 | fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG; |
fa05f87a FF |
1892 | seqno = tid->seq_next; |
1893 | hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT); | |
fd09c85f SM |
1894 | |
1895 | if (fragno) | |
1896 | hdr->seq_ctrl |= cpu_to_le16(fragno); | |
1897 | ||
1898 | if (!ieee80211_has_morefrags(hdr->frame_control)) | |
1899 | INCR(tid->seq_next, IEEE80211_SEQ_MAX); | |
1900 | ||
fa05f87a FF |
1901 | bf->bf_state.seqno = seqno; |
1902 | } | |
1903 | ||
f078f209 | 1904 | bf->bf_mpdu = skb; |
f8316df1 | 1905 | |
c1739eb3 BG |
1906 | bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, |
1907 | skb->len, DMA_TO_DEVICE); | |
1908 | if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) { | |
f8316df1 | 1909 | bf->bf_mpdu = NULL; |
6cf9e995 | 1910 | bf->bf_buf_addr = 0; |
3800276a JP |
1911 | ath_err(ath9k_hw_common(sc->sc_ah), |
1912 | "dma_mapping_error() on TX\n"); | |
82b873af | 1913 | ath_tx_return_buffer(sc, bf); |
249ee722 | 1914 | return NULL; |
f8316df1 LR |
1915 | } |
1916 | ||
56dc6336 | 1917 | fi->bf = bf; |
04caf863 FF |
1918 | |
1919 | return bf; | |
1920 | } | |
1921 | ||
f8316df1 | 1922 | /* Upon failure caller should free skb */ |
c52f33d0 | 1923 | int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, |
528f0c6b | 1924 | struct ath_tx_control *txctl) |
f078f209 | 1925 | { |
28d16708 FF |
1926 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; |
1927 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
36323f81 | 1928 | struct ieee80211_sta *sta = txctl->sta; |
f59a59fe | 1929 | struct ieee80211_vif *vif = info->control.vif; |
9ac58615 | 1930 | struct ath_softc *sc = hw->priv; |
84642d6b | 1931 | struct ath_txq *txq = txctl->txq; |
bdc21457 FF |
1932 | struct ath_atx_tid *tid = NULL; |
1933 | struct ath_buf *bf; | |
4d91f9f3 | 1934 | int padpos, padsize; |
04caf863 | 1935 | int frmlen = skb->len + FCS_LEN; |
bdc21457 | 1936 | u8 tidno; |
28d16708 | 1937 | int q; |
f078f209 | 1938 | |
a9927ba3 BG |
1939 | /* NOTE: sta can be NULL according to net/mac80211.h */ |
1940 | if (sta) | |
1941 | txctl->an = (struct ath_node *)sta->drv_priv; | |
1942 | ||
04caf863 FF |
1943 | if (info->control.hw_key) |
1944 | frmlen += info->control.hw_key->icv_len; | |
1945 | ||
f078f209 | 1946 | /* |
e8324357 S |
1947 | * As a temporary workaround, assign seq# here; this will likely need |
1948 | * to be cleaned up to work better with Beacon transmission and virtual | |
1949 | * BSSes. | |
f078f209 | 1950 | */ |
e8324357 | 1951 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { |
e8324357 S |
1952 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) |
1953 | sc->tx.seq_no += 0x10; | |
1954 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); | |
1955 | hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); | |
f078f209 | 1956 | } |
f078f209 | 1957 | |
42cecc34 | 1958 | /* Add the padding after the header if this is not already done */ |
c60c9929 | 1959 | padpos = ieee80211_hdrlen(hdr->frame_control); |
42cecc34 JL |
1960 | padsize = padpos & 3; |
1961 | if (padsize && skb->len > padpos) { | |
1962 | if (skb_headroom(skb) < padsize) | |
1963 | return -ENOMEM; | |
28d16708 | 1964 | |
42cecc34 JL |
1965 | skb_push(skb, padsize); |
1966 | memmove(skb->data, skb->data + padsize, padpos); | |
6e82bc4a | 1967 | hdr = (struct ieee80211_hdr *) skb->data; |
f078f209 | 1968 | } |
f078f209 | 1969 | |
f59a59fe FF |
1970 | if ((vif && vif->type != NL80211_IFTYPE_AP && |
1971 | vif->type != NL80211_IFTYPE_AP_VLAN) || | |
1972 | !ieee80211_is_data(hdr->frame_control)) | |
1973 | info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT; | |
1974 | ||
36323f81 | 1975 | setup_frame_info(hw, sta, skb, frmlen); |
2d42efc4 FF |
1976 | |
1977 | /* | |
1978 | * At this point, the vif, hw_key and sta pointers in the tx control | |
1979 | * info are no longer valid (overwritten by the ath_frame_info data. | |
1980 | */ | |
1981 | ||
28d16708 | 1982 | q = skb_get_queue_mapping(skb); |
23de5dc9 FF |
1983 | |
1984 | ath_txq_lock(sc, txq); | |
28d16708 | 1985 | if (txq == sc->tx.txq_map[q] && |
7702e788 FF |
1986 | ++txq->pending_frames > sc->tx.txq_max_pending[q] && |
1987 | !txq->stopped) { | |
7545daf4 | 1988 | ieee80211_stop_queue(sc->hw, q); |
3db1cd5c | 1989 | txq->stopped = true; |
f078f209 | 1990 | } |
f078f209 | 1991 | |
bdc21457 FF |
1992 | if (txctl->an && ieee80211_is_data_qos(hdr->frame_control)) { |
1993 | tidno = ieee80211_get_qos_ctl(hdr)[0] & | |
1994 | IEEE80211_QOS_CTL_TID_MASK; | |
1995 | tid = ATH_AN_2_TID(txctl->an, tidno); | |
1996 | ||
1997 | WARN_ON(tid->ac->txq != txctl->txq); | |
1998 | } | |
1999 | ||
2000 | if ((info->flags & IEEE80211_TX_CTL_AMPDU) && tid) { | |
2001 | /* | |
2002 | * Try aggregation if it's a unicast data frame | |
2003 | * and the destination is HT capable. | |
2004 | */ | |
2005 | ath_tx_send_ampdu(sc, tid, skb, txctl); | |
2006 | goto out; | |
2007 | } | |
2008 | ||
2009 | bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb); | |
2010 | if (!bf) { | |
2011 | if (txctl->paprd) | |
2012 | dev_kfree_skb_any(skb); | |
2013 | else | |
2014 | ieee80211_free_txskb(sc->hw, skb); | |
2015 | goto out; | |
2016 | } | |
2017 | ||
2018 | bf->bf_state.bfs_paprd = txctl->paprd; | |
2019 | ||
2020 | if (txctl->paprd) | |
2021 | bf->bf_state.bfs_paprd_timestamp = jiffies; | |
2022 | ||
79acac07 | 2023 | ath_set_rates(vif, sta, bf); |
bdc21457 | 2024 | ath_tx_send_normal(sc, txctl->txq, tid, skb); |
3ad29529 | 2025 | |
bdc21457 | 2026 | out: |
23de5dc9 | 2027 | ath_txq_unlock(sc, txq); |
3ad29529 | 2028 | |
44f1d26c | 2029 | return 0; |
f078f209 LR |
2030 | } |
2031 | ||
e8324357 S |
2032 | /*****************/ |
2033 | /* TX Completion */ | |
2034 | /*****************/ | |
528f0c6b | 2035 | |
e8324357 | 2036 | static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, |
0f9dc298 | 2037 | int tx_flags, struct ath_txq *txq) |
528f0c6b | 2038 | { |
e8324357 | 2039 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
c46917bb | 2040 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
4d91f9f3 | 2041 | struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data; |
97923b14 | 2042 | int q, padpos, padsize; |
07c15a3f | 2043 | unsigned long flags; |
528f0c6b | 2044 | |
d2182b69 | 2045 | ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb); |
528f0c6b | 2046 | |
51dea9be FF |
2047 | if (sc->sc_ah->caldata) |
2048 | sc->sc_ah->caldata->paprd_packet_sent = true; | |
2049 | ||
55797b1a | 2050 | if (!(tx_flags & ATH_TX_ERROR)) |
e8324357 S |
2051 | /* Frame was ACKed */ |
2052 | tx_info->flags |= IEEE80211_TX_STAT_ACK; | |
528f0c6b | 2053 | |
c60c9929 | 2054 | padpos = ieee80211_hdrlen(hdr->frame_control); |
42cecc34 JL |
2055 | padsize = padpos & 3; |
2056 | if (padsize && skb->len>padpos+padsize) { | |
2057 | /* | |
2058 | * Remove MAC header padding before giving the frame back to | |
2059 | * mac80211. | |
2060 | */ | |
2061 | memmove(skb->data + padsize, skb->data, padpos); | |
2062 | skb_pull(skb, padsize); | |
e8324357 | 2063 | } |
528f0c6b | 2064 | |
07c15a3f | 2065 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
c8e8868e | 2066 | if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) { |
1b04b930 | 2067 | sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK; |
d2182b69 | 2068 | ath_dbg(common, PS, |
226afe68 | 2069 | "Going back to sleep after having received TX status (0x%lx)\n", |
1b04b930 S |
2070 | sc->ps_flags & (PS_WAIT_FOR_BEACON | |
2071 | PS_WAIT_FOR_CAB | | |
2072 | PS_WAIT_FOR_PSPOLL_DATA | | |
2073 | PS_WAIT_FOR_TX_ACK)); | |
9a23f9ca | 2074 | } |
07c15a3f | 2075 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
9a23f9ca | 2076 | |
7545daf4 FF |
2077 | q = skb_get_queue_mapping(skb); |
2078 | if (txq == sc->tx.txq_map[q]) { | |
7545daf4 FF |
2079 | if (WARN_ON(--txq->pending_frames < 0)) |
2080 | txq->pending_frames = 0; | |
92460412 | 2081 | |
7702e788 FF |
2082 | if (txq->stopped && |
2083 | txq->pending_frames < sc->tx.txq_max_pending[q]) { | |
7545daf4 | 2084 | ieee80211_wake_queue(sc->hw, q); |
3db1cd5c | 2085 | txq->stopped = false; |
066dae93 | 2086 | } |
97923b14 | 2087 | } |
7545daf4 | 2088 | |
23de5dc9 | 2089 | __skb_queue_tail(&txq->complete_q, skb); |
e8324357 | 2090 | } |
f078f209 | 2091 | |
e8324357 | 2092 | static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, |
db1a052b | 2093 | struct ath_txq *txq, struct list_head *bf_q, |
156369fa | 2094 | struct ath_tx_status *ts, int txok) |
f078f209 | 2095 | { |
e8324357 | 2096 | struct sk_buff *skb = bf->bf_mpdu; |
3afd21e7 | 2097 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
e8324357 | 2098 | unsigned long flags; |
6b2c4032 | 2099 | int tx_flags = 0; |
f078f209 | 2100 | |
55797b1a | 2101 | if (!txok) |
6b2c4032 | 2102 | tx_flags |= ATH_TX_ERROR; |
f078f209 | 2103 | |
3afd21e7 FF |
2104 | if (ts->ts_status & ATH9K_TXERR_FILT) |
2105 | tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; | |
2106 | ||
c1739eb3 | 2107 | dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE); |
6cf9e995 | 2108 | bf->bf_buf_addr = 0; |
9f42c2b6 FF |
2109 | |
2110 | if (bf->bf_state.bfs_paprd) { | |
9cf04dcc MSS |
2111 | if (time_after(jiffies, |
2112 | bf->bf_state.bfs_paprd_timestamp + | |
2113 | msecs_to_jiffies(ATH_PAPRD_TIMEOUT))) | |
ca369eb4 | 2114 | dev_kfree_skb_any(skb); |
78a18172 | 2115 | else |
ca369eb4 | 2116 | complete(&sc->paprd_complete); |
9f42c2b6 | 2117 | } else { |
55797b1a | 2118 | ath_debug_stat_tx(sc, bf, ts, txq, tx_flags); |
0f9dc298 | 2119 | ath_tx_complete(sc, skb, tx_flags, txq); |
9f42c2b6 | 2120 | } |
6cf9e995 BG |
2121 | /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't |
2122 | * accidentally reference it later. | |
2123 | */ | |
2124 | bf->bf_mpdu = NULL; | |
e8324357 S |
2125 | |
2126 | /* | |
2127 | * Return the list of ath_buf of this mpdu to free queue | |
2128 | */ | |
2129 | spin_lock_irqsave(&sc->tx.txbuflock, flags); | |
2130 | list_splice_tail_init(bf_q, &sc->tx.txbuf); | |
2131 | spin_unlock_irqrestore(&sc->tx.txbuflock, flags); | |
f078f209 LR |
2132 | } |
2133 | ||
0cdd5c60 FF |
2134 | static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, |
2135 | struct ath_tx_status *ts, int nframes, int nbad, | |
3afd21e7 | 2136 | int txok) |
f078f209 | 2137 | { |
a22be22a | 2138 | struct sk_buff *skb = bf->bf_mpdu; |
254ad0ff | 2139 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
e8324357 | 2140 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
0cdd5c60 | 2141 | struct ieee80211_hw *hw = sc->hw; |
f0c255a0 | 2142 | struct ath_hw *ah = sc->sc_ah; |
8a92e2ee | 2143 | u8 i, tx_rateindex; |
f078f209 | 2144 | |
95e4acb7 | 2145 | if (txok) |
db1a052b | 2146 | tx_info->status.ack_signal = ts->ts_rssi; |
95e4acb7 | 2147 | |
db1a052b | 2148 | tx_rateindex = ts->ts_rateindex; |
8a92e2ee VT |
2149 | WARN_ON(tx_rateindex >= hw->max_rates); |
2150 | ||
3afd21e7 | 2151 | if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { |
d969847c | 2152 | tx_info->flags |= IEEE80211_TX_STAT_AMPDU; |
f078f209 | 2153 | |
b572d033 | 2154 | BUG_ON(nbad > nframes); |
ebd02287 | 2155 | } |
185d1589 RM |
2156 | tx_info->status.ampdu_len = nframes; |
2157 | tx_info->status.ampdu_ack_len = nframes - nbad; | |
ebd02287 | 2158 | |
db1a052b | 2159 | if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 && |
3afd21e7 | 2160 | (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) { |
f0c255a0 FF |
2161 | /* |
2162 | * If an underrun error is seen assume it as an excessive | |
2163 | * retry only if max frame trigger level has been reached | |
2164 | * (2 KB for single stream, and 4 KB for dual stream). | |
2165 | * Adjust the long retry as if the frame was tried | |
2166 | * hw->max_rate_tries times to affect how rate control updates | |
2167 | * PER for the failed rate. | |
2168 | * In case of congestion on the bus penalizing this type of | |
2169 | * underruns should help hardware actually transmit new frames | |
2170 | * successfully by eventually preferring slower rates. | |
2171 | * This itself should also alleviate congestion on the bus. | |
2172 | */ | |
3afd21e7 FF |
2173 | if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN | |
2174 | ATH9K_TX_DELIM_UNDERRUN)) && | |
2175 | ieee80211_is_data(hdr->frame_control) && | |
83860c59 | 2176 | ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level) |
f0c255a0 FF |
2177 | tx_info->status.rates[tx_rateindex].count = |
2178 | hw->max_rate_tries; | |
f078f209 | 2179 | } |
8a92e2ee | 2180 | |
545750d3 | 2181 | for (i = tx_rateindex + 1; i < hw->max_rates; i++) { |
8a92e2ee | 2182 | tx_info->status.rates[i].count = 0; |
545750d3 FF |
2183 | tx_info->status.rates[i].idx = -1; |
2184 | } | |
8a92e2ee | 2185 | |
78c4653a | 2186 | tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1; |
f078f209 LR |
2187 | } |
2188 | ||
e8324357 | 2189 | static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) |
f078f209 | 2190 | { |
cbe61d8a | 2191 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 2192 | struct ath_common *common = ath9k_hw_common(ah); |
e8324357 | 2193 | struct ath_buf *bf, *lastbf, *bf_held = NULL; |
f078f209 | 2194 | struct list_head bf_head; |
e8324357 | 2195 | struct ath_desc *ds; |
29bffa96 | 2196 | struct ath_tx_status ts; |
e8324357 | 2197 | int status; |
f078f209 | 2198 | |
d2182b69 | 2199 | ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n", |
226afe68 JP |
2200 | txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), |
2201 | txq->axq_link); | |
f078f209 | 2202 | |
23de5dc9 | 2203 | ath_txq_lock(sc, txq); |
f078f209 | 2204 | for (;;) { |
124b979b | 2205 | if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) |
236de514 FF |
2206 | break; |
2207 | ||
f078f209 LR |
2208 | if (list_empty(&txq->axq_q)) { |
2209 | txq->axq_link = NULL; | |
3d4e20f2 | 2210 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
082f6536 | 2211 | ath_txq_schedule(sc, txq); |
f078f209 LR |
2212 | break; |
2213 | } | |
f078f209 LR |
2214 | bf = list_first_entry(&txq->axq_q, struct ath_buf, list); |
2215 | ||
e8324357 S |
2216 | /* |
2217 | * There is a race condition that a BH gets scheduled | |
2218 | * after sw writes TxE and before hw re-load the last | |
2219 | * descriptor to get the newly chained one. | |
2220 | * Software must keep the last DONE descriptor as a | |
2221 | * holding descriptor - software does so by marking | |
2222 | * it with the STALE flag. | |
2223 | */ | |
2224 | bf_held = NULL; | |
a119cc49 | 2225 | if (bf->bf_stale) { |
e8324357 | 2226 | bf_held = bf; |
fce041be | 2227 | if (list_is_last(&bf_held->list, &txq->axq_q)) |
e8324357 | 2228 | break; |
fce041be FF |
2229 | |
2230 | bf = list_entry(bf_held->list.next, struct ath_buf, | |
2231 | list); | |
f078f209 LR |
2232 | } |
2233 | ||
2234 | lastbf = bf->bf_lastbf; | |
e8324357 | 2235 | ds = lastbf->bf_desc; |
f078f209 | 2236 | |
29bffa96 FF |
2237 | memset(&ts, 0, sizeof(ts)); |
2238 | status = ath9k_hw_txprocdesc(ah, ds, &ts); | |
fce041be | 2239 | if (status == -EINPROGRESS) |
e8324357 | 2240 | break; |
fce041be | 2241 | |
2dac4fb9 | 2242 | TX_STAT_INC(txq->axq_qnum, txprocdesc); |
f078f209 | 2243 | |
e8324357 S |
2244 | /* |
2245 | * Remove ath_buf's of the same transmit unit from txq, | |
2246 | * however leave the last descriptor back as the holding | |
2247 | * descriptor for hw. | |
2248 | */ | |
a119cc49 | 2249 | lastbf->bf_stale = true; |
e8324357 | 2250 | INIT_LIST_HEAD(&bf_head); |
e8324357 S |
2251 | if (!list_is_singular(&lastbf->list)) |
2252 | list_cut_position(&bf_head, | |
2253 | &txq->axq_q, lastbf->list.prev); | |
f078f209 | 2254 | |
fce041be | 2255 | if (bf_held) { |
0a8cea84 | 2256 | list_del(&bf_held->list); |
0a8cea84 | 2257 | ath_tx_return_buffer(sc, bf_held); |
e8324357 | 2258 | } |
f078f209 | 2259 | |
fce041be | 2260 | ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); |
8469cdef | 2261 | } |
23de5dc9 | 2262 | ath_txq_unlock_complete(sc, txq); |
8469cdef S |
2263 | } |
2264 | ||
e8324357 | 2265 | void ath_tx_tasklet(struct ath_softc *sc) |
f078f209 | 2266 | { |
239c795d FF |
2267 | struct ath_hw *ah = sc->sc_ah; |
2268 | u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs; | |
e8324357 | 2269 | int i; |
f078f209 | 2270 | |
e8324357 S |
2271 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
2272 | if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i))) | |
2273 | ath_tx_processq(sc, &sc->tx.txq[i]); | |
f078f209 LR |
2274 | } |
2275 | } | |
2276 | ||
e5003249 VT |
2277 | void ath_tx_edma_tasklet(struct ath_softc *sc) |
2278 | { | |
fce041be | 2279 | struct ath_tx_status ts; |
e5003249 VT |
2280 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
2281 | struct ath_hw *ah = sc->sc_ah; | |
2282 | struct ath_txq *txq; | |
2283 | struct ath_buf *bf, *lastbf; | |
2284 | struct list_head bf_head; | |
99ba6a46 | 2285 | struct list_head *fifo_list; |
e5003249 | 2286 | int status; |
e5003249 VT |
2287 | |
2288 | for (;;) { | |
124b979b | 2289 | if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) |
236de514 FF |
2290 | break; |
2291 | ||
fce041be | 2292 | status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts); |
e5003249 VT |
2293 | if (status == -EINPROGRESS) |
2294 | break; | |
2295 | if (status == -EIO) { | |
d2182b69 | 2296 | ath_dbg(common, XMIT, "Error processing tx status\n"); |
e5003249 VT |
2297 | break; |
2298 | } | |
2299 | ||
4e0ad259 FF |
2300 | /* Process beacon completions separately */ |
2301 | if (ts.qid == sc->beacon.beaconq) { | |
2302 | sc->beacon.tx_processed = true; | |
2303 | sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); | |
e5003249 | 2304 | continue; |
4e0ad259 | 2305 | } |
e5003249 | 2306 | |
fce041be | 2307 | txq = &sc->tx.txq[ts.qid]; |
e5003249 | 2308 | |
23de5dc9 | 2309 | ath_txq_lock(sc, txq); |
fce041be | 2310 | |
78ef731c SM |
2311 | TX_STAT_INC(txq->axq_qnum, txprocdesc); |
2312 | ||
99ba6a46 FF |
2313 | fifo_list = &txq->txq_fifo[txq->txq_tailidx]; |
2314 | if (list_empty(fifo_list)) { | |
23de5dc9 | 2315 | ath_txq_unlock(sc, txq); |
e5003249 VT |
2316 | return; |
2317 | } | |
2318 | ||
99ba6a46 FF |
2319 | bf = list_first_entry(fifo_list, struct ath_buf, list); |
2320 | if (bf->bf_stale) { | |
2321 | list_del(&bf->list); | |
2322 | ath_tx_return_buffer(sc, bf); | |
2323 | bf = list_first_entry(fifo_list, struct ath_buf, list); | |
2324 | } | |
2325 | ||
e5003249 VT |
2326 | lastbf = bf->bf_lastbf; |
2327 | ||
2328 | INIT_LIST_HEAD(&bf_head); | |
99ba6a46 FF |
2329 | if (list_is_last(&lastbf->list, fifo_list)) { |
2330 | list_splice_tail_init(fifo_list, &bf_head); | |
fce041be | 2331 | INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH); |
e5003249 | 2332 | |
fce041be FF |
2333 | if (!list_empty(&txq->axq_q)) { |
2334 | struct list_head bf_q; | |
60f2d1d5 | 2335 | |
fce041be FF |
2336 | INIT_LIST_HEAD(&bf_q); |
2337 | txq->axq_link = NULL; | |
2338 | list_splice_tail_init(&txq->axq_q, &bf_q); | |
2339 | ath_tx_txqaddbuf(sc, txq, &bf_q, true); | |
2340 | } | |
99ba6a46 FF |
2341 | } else { |
2342 | lastbf->bf_stale = true; | |
2343 | if (bf != lastbf) | |
2344 | list_cut_position(&bf_head, fifo_list, | |
2345 | lastbf->list.prev); | |
fce041be | 2346 | } |
86271e46 | 2347 | |
fce041be | 2348 | ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); |
23de5dc9 | 2349 | ath_txq_unlock_complete(sc, txq); |
e5003249 VT |
2350 | } |
2351 | } | |
2352 | ||
e8324357 S |
2353 | /*****************/ |
2354 | /* Init, Cleanup */ | |
2355 | /*****************/ | |
f078f209 | 2356 | |
5088c2f1 VT |
2357 | static int ath_txstatus_setup(struct ath_softc *sc, int size) |
2358 | { | |
2359 | struct ath_descdma *dd = &sc->txsdma; | |
2360 | u8 txs_len = sc->sc_ah->caps.txs_len; | |
2361 | ||
2362 | dd->dd_desc_len = size * txs_len; | |
b81950b1 FF |
2363 | dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len, |
2364 | &dd->dd_desc_paddr, GFP_KERNEL); | |
5088c2f1 VT |
2365 | if (!dd->dd_desc) |
2366 | return -ENOMEM; | |
2367 | ||
2368 | return 0; | |
2369 | } | |
2370 | ||
2371 | static int ath_tx_edma_init(struct ath_softc *sc) | |
2372 | { | |
2373 | int err; | |
2374 | ||
2375 | err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE); | |
2376 | if (!err) | |
2377 | ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc, | |
2378 | sc->txsdma.dd_desc_paddr, | |
2379 | ATH_TXSTATUS_RING_SIZE); | |
2380 | ||
2381 | return err; | |
2382 | } | |
2383 | ||
e8324357 | 2384 | int ath_tx_init(struct ath_softc *sc, int nbufs) |
f078f209 | 2385 | { |
c46917bb | 2386 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
e8324357 | 2387 | int error = 0; |
f078f209 | 2388 | |
797fe5cb | 2389 | spin_lock_init(&sc->tx.txbuflock); |
f078f209 | 2390 | |
797fe5cb | 2391 | error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, |
4adfcded | 2392 | "tx", nbufs, 1, 1); |
797fe5cb | 2393 | if (error != 0) { |
3800276a JP |
2394 | ath_err(common, |
2395 | "Failed to allocate tx descriptors: %d\n", error); | |
b81950b1 | 2396 | return error; |
797fe5cb | 2397 | } |
f078f209 | 2398 | |
797fe5cb | 2399 | error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, |
5088c2f1 | 2400 | "beacon", ATH_BCBUF, 1, 1); |
797fe5cb | 2401 | if (error != 0) { |
3800276a JP |
2402 | ath_err(common, |
2403 | "Failed to allocate beacon descriptors: %d\n", error); | |
b81950b1 | 2404 | return error; |
797fe5cb | 2405 | } |
f078f209 | 2406 | |
164ace38 SB |
2407 | INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work); |
2408 | ||
b81950b1 | 2409 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
5088c2f1 | 2410 | error = ath_tx_edma_init(sc); |
f078f209 | 2411 | |
e8324357 | 2412 | return error; |
f078f209 LR |
2413 | } |
2414 | ||
f078f209 LR |
2415 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an) |
2416 | { | |
c5170163 S |
2417 | struct ath_atx_tid *tid; |
2418 | struct ath_atx_ac *ac; | |
2419 | int tidno, acno; | |
f078f209 | 2420 | |
8ee5afbc | 2421 | for (tidno = 0, tid = &an->tid[tidno]; |
de7b7604 | 2422 | tidno < IEEE80211_NUM_TIDS; |
c5170163 S |
2423 | tidno++, tid++) { |
2424 | tid->an = an; | |
2425 | tid->tidno = tidno; | |
2426 | tid->seq_start = tid->seq_next = 0; | |
2427 | tid->baw_size = WME_MAX_BA; | |
2428 | tid->baw_head = tid->baw_tail = 0; | |
2429 | tid->sched = false; | |
e8324357 | 2430 | tid->paused = false; |
a37c2c79 | 2431 | tid->state &= ~AGGR_CLEANUP; |
56dc6336 | 2432 | __skb_queue_head_init(&tid->buf_q); |
c5170163 | 2433 | acno = TID_TO_WME_AC(tidno); |
8ee5afbc | 2434 | tid->ac = &an->ac[acno]; |
a37c2c79 S |
2435 | tid->state &= ~AGGR_ADDBA_COMPLETE; |
2436 | tid->state &= ~AGGR_ADDBA_PROGRESS; | |
16e23428 | 2437 | tid->stop_cb = false; |
c5170163 | 2438 | } |
f078f209 | 2439 | |
8ee5afbc | 2440 | for (acno = 0, ac = &an->ac[acno]; |
bea843c7 | 2441 | acno < IEEE80211_NUM_ACS; acno++, ac++) { |
c5170163 | 2442 | ac->sched = false; |
066dae93 | 2443 | ac->txq = sc->tx.txq_map[acno]; |
c5170163 | 2444 | INIT_LIST_HEAD(&ac->tid_q); |
f078f209 LR |
2445 | } |
2446 | } | |
2447 | ||
b5aa9bf9 | 2448 | void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an) |
f078f209 | 2449 | { |
2b40994c FF |
2450 | struct ath_atx_ac *ac; |
2451 | struct ath_atx_tid *tid; | |
f078f209 | 2452 | struct ath_txq *txq; |
066dae93 | 2453 | int tidno; |
e8324357 | 2454 | |
2b40994c | 2455 | for (tidno = 0, tid = &an->tid[tidno]; |
de7b7604 | 2456 | tidno < IEEE80211_NUM_TIDS; tidno++, tid++) { |
f078f209 | 2457 | |
2b40994c | 2458 | ac = tid->ac; |
066dae93 | 2459 | txq = ac->txq; |
f078f209 | 2460 | |
23de5dc9 | 2461 | ath_txq_lock(sc, txq); |
2b40994c FF |
2462 | |
2463 | if (tid->sched) { | |
2464 | list_del(&tid->list); | |
2465 | tid->sched = false; | |
2466 | } | |
2467 | ||
2468 | if (ac->sched) { | |
2469 | list_del(&ac->list); | |
2470 | tid->ac->sched = false; | |
f078f209 | 2471 | } |
2b40994c FF |
2472 | |
2473 | ath_tid_drain(sc, txq, tid); | |
16e23428 | 2474 | ath_tx_clear_tid(sc, tid); |
2b40994c | 2475 | |
23de5dc9 | 2476 | ath_txq_unlock(sc, txq); |
f078f209 LR |
2477 | } |
2478 | } |