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ath9k: move channel change code to ath_set_channel
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / xmit.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
b7f080cf 17#include <linux/dma-mapping.h>
394cf0a1 18#include "ath9k.h"
b622a720 19#include "ar9003_mac.h"
f078f209
LR		 20
21#define BITS_PER_BYTE 8
22#define OFDM_PLCP_BITS 22
f078f209
LR		 23#define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
24#define L_STF 8
25#define L_LTF 8
26#define L_SIG 4
27#define HT_SIG 8
28#define HT_STF 4
29#define HT_LTF(_ns) (4 * (_ns))
30#define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31#define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
aa5955c3
FF		 32#define TIME_SYMBOLS(t) ((t) >> 2)
33#define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
f078f209
LR		 34#define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35#define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
36
f078f209 37
c6663876 38static u16 bits_per_symbol[][2] = {
f078f209
LR		 39 /* 20MHz 40MHz */
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
f078f209
LR		 48};
49
50#define IS_HT_RATE(_rate) ((_rate) & 0x80)
51
82b873af 52static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
44f1d26c
FF		 53 struct ath_atx_tid *tid, struct sk_buff *skb);
54static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
55 int tx_flags, struct ath_txq *txq);
e8324357 56static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
db1a052b 57 struct ath_txq *txq, struct list_head *bf_q,
156369fa 58 struct ath_tx_status *ts, int txok);
102e0572 59static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
fce041be 60 struct list_head *head, bool internal);
0cdd5c60
FF		 61static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
62 struct ath_tx_status *ts, int nframes, int nbad,
3afd21e7 63 int txok);
90fa539c
FF		 64static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
65 int seqno);
44f1d26c
FF		 66static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
67 struct ath_txq *txq,
68 struct ath_atx_tid *tid,
249ee722 69 struct sk_buff *skb);
c4288390 70
545750d3 71enum {
0e668cde
FF		 72 MCS_HT20,
73 MCS_HT20_SGI,
545750d3
FF		 74 MCS_HT40,
75 MCS_HT40_SGI,
76};
77
e8324357
S		 78/*********************/
79/* Aggregation logic */
80/*********************/
f078f209 81
ef1b6cd9 82void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq)
1512a486 83 __acquires(&txq->axq_lock)
23de5dc9
FF		 84{
85 spin_lock_bh(&txq->axq_lock);
86}
87
ef1b6cd9 88void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq)
1512a486 89 __releases(&txq->axq_lock)
23de5dc9
FF		 90{
91 spin_unlock_bh(&txq->axq_lock);
92}
93
ef1b6cd9 94void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
1512a486 95 __releases(&txq->axq_lock)
23de5dc9
FF		 96{
97 struct sk_buff_head q;
98 struct sk_buff *skb;
99
100 __skb_queue_head_init(&q);
101 skb_queue_splice_init(&txq->complete_q, &q);
102 spin_unlock_bh(&txq->axq_lock);
103
104 while ((skb = __skb_dequeue(&q)))
105 ieee80211_tx_status(sc->hw, skb);
106}
107
e8324357 108static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
ff37e337 109{
e8324357 110 struct ath_atx_ac *ac = tid->ac;
ff37e337 111
e8324357
S		 112 if (tid->paused)
113 return;
ff37e337 114
e8324357
S		 115 if (tid->sched)
116 return;
ff37e337 117
e8324357
S		 118 tid->sched = true;
119 list_add_tail(&tid->list, &ac->tid_q);
528f0c6b 120
e8324357
S		 121 if (ac->sched)
122 return;
f078f209 123
e8324357
S		 124 ac->sched = true;
125 list_add_tail(&ac->list, &txq->axq_acq);
126}
f078f209 127
2d42efc4 128static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
76e45221
FF		 129{
130 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2d42efc4
FF		 131 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
132 sizeof(tx_info->rate_driver_data));
133 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
76e45221
FF		 134}
135
156369fa
FF		 136static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
137{
f89d1bc4
FF		 138 if (!tid->an->sta)
139 return;
140
156369fa
FF		 141 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
142 seqno << IEEE80211_SEQ_SEQ_SHIFT);
143}
144
79acac07
FF		 145static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
146 struct ath_buf *bf)
147{
148 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
149 ARRAY_SIZE(bf->rates));
150}
151
a4943ccb
FF		 152static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
153 struct sk_buff *skb)
154{
155 int q;
156
157 q = skb_get_queue_mapping(skb);
158 if (txq == sc->tx.uapsdq)
159 txq = sc->tx.txq_map[q];
160
161 if (txq != sc->tx.txq_map[q])
162 return;
163
164 if (WARN_ON(--txq->pending_frames < 0))
165 txq->pending_frames = 0;
166
167 if (txq->stopped &&
168 txq->pending_frames < sc->tx.txq_max_pending[q]) {
169 ieee80211_wake_queue(sc->hw, q);
170 txq->stopped = false;
171 }
172}
173
1803d02d
FF		 174static struct ath_atx_tid *
175ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
176{
177 struct ieee80211_hdr *hdr;
178 u8 tidno = 0;
179
180 hdr = (struct ieee80211_hdr *) skb->data;
181 if (ieee80211_is_data_qos(hdr->frame_control))
182 tidno = ieee80211_get_qos_ctl(hdr)[0];
183
184 tidno &= IEEE80211_QOS_CTL_TID_MASK;
185 return ATH_AN_2_TID(an, tidno);
186}
187
a7586ee4
FF		 188static bool ath_tid_has_buffered(struct ath_atx_tid *tid)
189{
bb195ff6 190 return !skb_queue_empty(&tid->buf_q) || !skb_queue_empty(&tid->retry_q);
a7586ee4
FF		 191}
192
193static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid)
194{
bb195ff6
FF		 195 struct sk_buff *skb;
196
197 skb = __skb_dequeue(&tid->retry_q);
198 if (!skb)
199 skb = __skb_dequeue(&tid->buf_q);
200
201 return skb;
a7586ee4
FF		 202}
203
2800e82b
FF		 204/*
205 * ath_tx_tid_change_state:
206 * - clears a-mpdu flag of previous session
207 * - force sequence number allocation to fix next BlockAck Window
208 */
209static void
210ath_tx_tid_change_state(struct ath_softc *sc, struct ath_atx_tid *tid)
211{
212 struct ath_txq *txq = tid->ac->txq;
213 struct ieee80211_tx_info *tx_info;
214 struct sk_buff *skb, *tskb;
215 struct ath_buf *bf;
216 struct ath_frame_info *fi;
217
218 skb_queue_walk_safe(&tid->buf_q, skb, tskb) {
219 fi = get_frame_info(skb);
220 bf = fi->bf;
221
222 tx_info = IEEE80211_SKB_CB(skb);
223 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
224
225 if (bf)
226 continue;
227
228 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
229 if (!bf) {
230 __skb_unlink(skb, &tid->buf_q);
231 ath_txq_skb_done(sc, txq, skb);
232 ieee80211_free_txskb(sc->hw, skb);
233 continue;
234 }
235 }
236
237}
238
08c96abd 239static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
528f0c6b 240{
066dae93 241 struct ath_txq *txq = tid->ac->txq;
56dc6336 242 struct sk_buff *skb;
e8324357
S		 243 struct ath_buf *bf;
244 struct list_head bf_head;
90fa539c 245 struct ath_tx_status ts;
2d42efc4 246 struct ath_frame_info *fi;
156369fa 247 bool sendbar = false;
f078f209 248
90fa539c 249 INIT_LIST_HEAD(&bf_head);
e6a9854b 250
90fa539c 251 memset(&ts, 0, sizeof(ts));
f078f209 252
2800e82b 253 while ((skb = __skb_dequeue(&tid->retry_q))) {
56dc6336
FF		 254 fi = get_frame_info(skb);
255 bf = fi->bf;
249ee722 256 if (!bf) {
2800e82b
FF		 257 ath_txq_skb_done(sc, txq, skb);
258 ieee80211_free_txskb(sc->hw, skb);
259 continue;
249ee722
FF		 260 }
261
8fed1408 262 if (fi->baw_tracked) {
6a0ddaef 263 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
156369fa 264 sendbar = true;
90fa539c 265 }
2800e82b
FF		 266
267 list_add_tail(&bf->list, &bf_head);
268 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
528f0c6b 269 }
f078f209 270
08c96abd 271 if (sendbar) {
23de5dc9 272 ath_txq_unlock(sc, txq);
156369fa 273 ath_send_bar(tid, tid->seq_start);
23de5dc9
FF		 274 ath_txq_lock(sc, txq);
275 }
528f0c6b 276}
f078f209 277
e8324357
S		 278static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
279 int seqno)
528f0c6b 280{
e8324357 281 int index, cindex;
f078f209 282
e8324357
S		 283 index = ATH_BA_INDEX(tid->seq_start, seqno);
284 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
f078f209 285
81ee13ba 286 __clear_bit(cindex, tid->tx_buf);
528f0c6b 287
81ee13ba 288 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
e8324357
S		 289 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
290 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
f9437543
FF		 291 if (tid->bar_index >= 0)
292 tid->bar_index--;
e8324357 293 }
528f0c6b 294}
f078f209 295
e8324357 296static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
8fed1408 297 struct ath_buf *bf)
528f0c6b 298{
8fed1408
FF		 299 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
300 u16 seqno = bf->bf_state.seqno;
e8324357 301 int index, cindex;
528f0c6b 302
2d3bcba0 303 index = ATH_BA_INDEX(tid->seq_start, seqno);
e8324357 304 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
81ee13ba 305 __set_bit(cindex, tid->tx_buf);
8fed1408 306 fi->baw_tracked = 1;
f078f209 307
e8324357
S		 308 if (index >= ((tid->baw_tail - tid->baw_head) &
309 (ATH_TID_MAX_BUFS - 1))) {
310 tid->baw_tail = cindex;
311 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
f078f209 312 }
f078f209
LR		 313}
314
e8324357
S		 315static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
316 struct ath_atx_tid *tid)
f078f209 317
f078f209 318{
56dc6336 319 struct sk_buff *skb;
e8324357
S		 320 struct ath_buf *bf;
321 struct list_head bf_head;
db1a052b 322 struct ath_tx_status ts;
2d42efc4 323 struct ath_frame_info *fi;
db1a052b
FF		 324
325 memset(&ts, 0, sizeof(ts));
e8324357 326 INIT_LIST_HEAD(&bf_head);
f078f209 327
a7586ee4 328 while ((skb = ath_tid_dequeue(tid))) {
56dc6336
FF		 329 fi = get_frame_info(skb);
330 bf = fi->bf;
f078f209 331
44f1d26c 332 if (!bf) {
44f1d26c 333 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
44f1d26c
FF		 334 continue;
335 }
336
56dc6336 337 list_add_tail(&bf->list, &bf_head);
156369fa 338 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
e8324357 339 }
f078f209
LR		 340}
341
fec247c0 342static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
da647626 343 struct sk_buff *skb, int count)
f078f209 344{
8b7f8532 345 struct ath_frame_info *fi = get_frame_info(skb);
f11cc949 346 struct ath_buf *bf = fi->bf;
e8324357 347 struct ieee80211_hdr *hdr;
da647626 348 int prev = fi->retries;
f078f209 349
fec247c0 350 TX_STAT_INC(txq->axq_qnum, a_retries);
da647626
FF		 351 fi->retries += count;
352
353 if (prev > 0)
2d42efc4 354 return;
f078f209 355
e8324357
S		 356 hdr = (struct ieee80211_hdr *)skb->data;
357 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
f11cc949
FF		 358 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
359 sizeof(*hdr), DMA_TO_DEVICE);
f078f209
LR		 360}
361
0a8cea84 362static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
d43f3015 363{
0a8cea84 364 struct ath_buf *bf = NULL;
d43f3015
S		 365
366 spin_lock_bh(&sc->tx.txbuflock);
0a8cea84
FF		 367
368 if (unlikely(list_empty(&sc->tx.txbuf))) {
8a46097a
VT		 369 spin_unlock_bh(&sc->tx.txbuflock);
370 return NULL;
371 }
0a8cea84
FF		 372
373 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
374 list_del(&bf->list);
375
d43f3015
S		 376 spin_unlock_bh(&sc->tx.txbuflock);
377
0a8cea84
FF		 378 return bf;
379}
380
381static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
382{
383 spin_lock_bh(&sc->tx.txbuflock);
384 list_add_tail(&bf->list, &sc->tx.txbuf);
385 spin_unlock_bh(&sc->tx.txbuflock);
386}
387
388static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
389{
390 struct ath_buf *tbf;
391
392 tbf = ath_tx_get_buffer(sc);
393 if (WARN_ON(!tbf))
394 return NULL;
395
d43f3015
S		 396 ATH_TXBUF_RESET(tbf);
397
398 tbf->bf_mpdu = bf->bf_mpdu;
399 tbf->bf_buf_addr = bf->bf_buf_addr;
d826c832 400 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
d43f3015 401 tbf->bf_state = bf->bf_state;
d43f3015
S		 402
403 return tbf;
404}
405
b572d033
FF		 406static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
407 struct ath_tx_status *ts, int txok,
408 int *nframes, int *nbad)
409{
2d42efc4 410 struct ath_frame_info *fi;
b572d033
FF		 411 u16 seq_st = 0;
412 u32 ba[WME_BA_BMP_SIZE >> 5];
413 int ba_index;
414 int isaggr = 0;
415
416 *nbad = 0;
417 *nframes = 0;
418
b572d033
FF		 419 isaggr = bf_isaggr(bf);
420 if (isaggr) {
421 seq_st = ts->ts_seqnum;
422 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
423 }
424
425 while (bf) {
2d42efc4 426 fi = get_frame_info(bf->bf_mpdu);
6a0ddaef 427 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
b572d033
FF		 428
429 (*nframes)++;
430 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
431 (*nbad)++;
432
433 bf = bf->bf_next;
434 }
435}
436
437
d43f3015
S		 438static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
439 struct ath_buf *bf, struct list_head *bf_q,
1381559b 440 struct ath_tx_status *ts, int txok)
f078f209 441{
e8324357
S		 442 struct ath_node *an = NULL;
443 struct sk_buff *skb;
1286ec6d 444 struct ieee80211_sta *sta;
0cdd5c60 445 struct ieee80211_hw *hw = sc->hw;
1286ec6d 446 struct ieee80211_hdr *hdr;
76d5a9e8 447 struct ieee80211_tx_info *tx_info;
e8324357 448 struct ath_atx_tid *tid = NULL;
d43f3015 449 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
56dc6336
FF		 450 struct list_head bf_head;
451 struct sk_buff_head bf_pending;
156369fa 452 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
f078f209 453 u32 ba[WME_BA_BMP_SIZE >> 5];
0934af23 454 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
6fe7cc71 455 bool rc_update = true, isba;
78c4653a 456 struct ieee80211_tx_rate rates[4];
2d42efc4 457 struct ath_frame_info *fi;
ebd02287 458 int nframes;
daa5c408 459 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
da647626 460 int i, retries;
156369fa 461 int bar_index = -1;
f078f209 462
a22be22a 463 skb = bf->bf_mpdu;
1286ec6d
S		 464 hdr = (struct ieee80211_hdr *)skb->data;
465
76d5a9e8 466 tx_info = IEEE80211_SKB_CB(skb);
76d5a9e8 467
79acac07 468 memcpy(rates, bf->rates, sizeof(rates));
78c4653a 469
da647626
FF		 470 retries = ts->ts_longretry + 1;
471 for (i = 0; i < ts->ts_rateindex; i++)
472 retries += rates[i].count;
473
1286ec6d 474 rcu_read_lock();
f078f209 475
686b9cb9 476 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
1286ec6d
S		 477 if (!sta) {
478 rcu_read_unlock();
73e19463 479
31e79a59
FF		 480 INIT_LIST_HEAD(&bf_head);
481 while (bf) {
482 bf_next = bf->bf_next;
483
50676b81 484 if (!bf->bf_state.stale || bf_next != NULL)
31e79a59
FF		 485 list_move_tail(&bf->list, &bf_head);
486
156369fa 487 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
31e79a59
FF		 488
489 bf = bf_next;
490 }
1286ec6d 491 return;
f078f209
LR		 492 }
493
1286ec6d 494 an = (struct ath_node *)sta->drv_priv;
1803d02d 495 tid = ath_get_skb_tid(sc, an, skb);
156369fa 496 seq_first = tid->seq_start;
6fe7cc71 497 isba = ts->ts_flags & ATH9K_TX_BA;
1286ec6d 498
b11b160d
FF		 499 /*
500 * The hardware occasionally sends a tx status for the wrong TID.
501 * In this case, the BA status cannot be considered valid and all
502 * subframes need to be retransmitted
6fe7cc71
SE		 503 *
504 * Only BlockAcks have a TID and therefore normal Acks cannot be
505 * checked
b11b160d 506 */
1803d02d 507 if (isba && tid->tidno != ts->tid)
b11b160d
FF		 508 txok = false;
509
e8324357 510 isaggr = bf_isaggr(bf);
d43f3015 511 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
f078f209 512
d43f3015 513 if (isaggr && txok) {
db1a052b
FF		 514 if (ts->ts_flags & ATH9K_TX_BA) {
515 seq_st = ts->ts_seqnum;
516 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
e8324357 517 } else {
d43f3015
S		 518 /*
519 * AR5416 can become deaf/mute when BA
520 * issue happens. Chip needs to be reset.
521 * But AP code may have sychronization issues
522 * when perform internal reset in this routine.
523 * Only enable reset in STA mode for now.
524 */
2660b81a 525 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
d43f3015 526 needreset = 1;
e8324357 527 }
f078f209
LR		 528 }
529
56dc6336 530 __skb_queue_head_init(&bf_pending);
f078f209 531
b572d033 532 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
e8324357 533 while (bf) {
6a0ddaef
FF		 534 u16 seqno = bf->bf_state.seqno;
535
f0b8220c 536 txfail = txpending = sendbar = 0;
e8324357 537 bf_next = bf->bf_next;
f078f209 538
78c4653a
FF		 539 skb = bf->bf_mpdu;
540 tx_info = IEEE80211_SKB_CB(skb);
2d42efc4 541 fi = get_frame_info(skb);
78c4653a 542
897d7fd9
FF		 543 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
544 !tid->active) {
08c96abd
FF		 545 /*
546 * Outside of the current BlockAck window,
547 * maybe part of a previous session
548 */
549 txfail = 1;
550 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
e8324357
S		 551 /* transmit completion, subframe is
552 * acked by block ack */
0934af23 553 acked_cnt++;
e8324357
S		 554 } else if (!isaggr && txok) {
555 /* transmit completion */
0934af23 556 acked_cnt++;
b0477013
FF		 557 } else if (flush) {
558 txpending = 1;
559 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
560 if (txok || !an->sleeping)
561 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
562 retries);
563
564 txpending = 1;
e8324357 565 } else {
b0477013
FF		 566 txfail = 1;
567 txfail_cnt++;
568 bar_index = max_t(int, bar_index,
569 ATH_BA_INDEX(seq_first, seqno));
e8324357 570 }
f078f209 571
fce041be
FF		 572 /*
573 * Make sure the last desc is reclaimed if it
574 * not a holding desc.
575 */
56dc6336 576 INIT_LIST_HEAD(&bf_head);
50676b81 577 if (bf_next != NULL || !bf_last->bf_state.stale)
d43f3015 578 list_move_tail(&bf->list, &bf_head);
f078f209 579
08c96abd 580 if (!txpending) {
e8324357
S		 581 /*
582 * complete the acked-ones/xretried ones; update
583 * block-ack window
584 */
6a0ddaef 585 ath_tx_update_baw(sc, tid, seqno);
f078f209 586
8a92e2ee 587 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
78c4653a 588 memcpy(tx_info->control.rates, rates, sizeof(rates));
3afd21e7 589 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
8a92e2ee 590 rc_update = false;
8a92e2ee
VT		 591 }
592
db1a052b 593 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
156369fa 594 !txfail);
e8324357 595 } else {
86a22acf
FF		 596 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
597 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
598 ieee80211_sta_eosp(sta);
599 }
d43f3015 600 /* retry the un-acked ones */
50676b81 601 if (bf->bf_next == NULL && bf_last->bf_state.stale) {
b0477013
FF		 602 struct ath_buf *tbf;
603
604 tbf = ath_clone_txbuf(sc, bf_last);
605 /*
606 * Update tx baw and complete the
607 * frame with failed status if we
608 * run out of tx buf.
609 */
610 if (!tbf) {
b0477013 611 ath_tx_update_baw(sc, tid, seqno);
b0477013
FF		 612
613 ath_tx_complete_buf(sc, bf, txq,
614 &bf_head, ts, 0);
615 bar_index = max_t(int, bar_index,
616 ATH_BA_INDEX(seq_first, seqno));
617 break;
c41d92dc 618 }
b0477013
FF		 619
620 fi->bf = tbf;
e8324357
S		 621 }
622
623 /*
624 * Put this buffer to the temporary pending
625 * queue to retain ordering
626 */
56dc6336 627 __skb_queue_tail(&bf_pending, skb);
e8324357
S		 628 }
629
630 bf = bf_next;
f078f209 631 }
f078f209 632
4cee7861 633 /* prepend un-acked frames to the beginning of the pending frame queue */
56dc6336 634 if (!skb_queue_empty(&bf_pending)) {
5519541d 635 if (an->sleeping)
042ec453 636 ieee80211_sta_set_buffered(sta, tid->tidno, true);
5519541d 637
bb195ff6 638 skb_queue_splice_tail(&bf_pending, &tid->retry_q);
26a64259 639 if (!an->sleeping) {
9af73cf7 640 ath_tx_queue_tid(txq, tid);
26a64259 641
adfbda62 642 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
26a64259
FF		 643 tid->ac->clear_ps_filter = true;
644 }
4cee7861
FF		 645 }
646
23de5dc9
FF		 647 if (bar_index >= 0) {
648 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
649
650 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
651 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
652
653 ath_txq_unlock(sc, txq);
654 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
655 ath_txq_lock(sc, txq);
656 }
657
1286ec6d
S		 658 rcu_read_unlock();
659
124b979b
RM		 660 if (needreset)
661 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
e8324357 662}
f078f209 663
81b51950
FF		 664static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
665{
666 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
667 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
668}
669
670static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
671 struct ath_tx_status *ts, struct ath_buf *bf,
672 struct list_head *bf_head)
673{
0c585dda 674 struct ieee80211_tx_info *info;
81b51950
FF		 675 bool txok, flush;
676
677 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
678 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
679 txq->axq_tx_inprogress = false;
680
681 txq->axq_depth--;
682 if (bf_is_ampdu_not_probing(bf))
683 txq->axq_ampdu_depth--;
684
685 if (!bf_isampdu(bf)) {
0c585dda
FF		 686 if (!flush) {
687 info = IEEE80211_SKB_CB(bf->bf_mpdu);
688 memcpy(info->control.rates, bf->rates,
689 sizeof(info->control.rates));
81b51950 690 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
0c585dda 691 }
81b51950
FF		 692 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
693 } else
694 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok);
695
73364b0c 696 if (!flush)
81b51950
FF		 697 ath_txq_schedule(sc, txq);
698}
699
1a6e9d0f
RM		 700static bool ath_lookup_legacy(struct ath_buf *bf)
701{
702 struct sk_buff *skb;
703 struct ieee80211_tx_info *tx_info;
704 struct ieee80211_tx_rate *rates;
705 int i;
706
707 skb = bf->bf_mpdu;
708 tx_info = IEEE80211_SKB_CB(skb);
709 rates = tx_info->control.rates;
710
059ee09b
FF		 711 for (i = 0; i < 4; i++) {
712 if (!rates[i].count || rates[i].idx < 0)
713 break;
714
1a6e9d0f
RM		 715 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
716 return true;
717 }
718
719 return false;
720}
721
e8324357
S		 722static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
723 struct ath_atx_tid *tid)
f078f209 724{
528f0c6b
S		 725 struct sk_buff *skb;
726 struct ieee80211_tx_info *tx_info;
a8efee4f 727 struct ieee80211_tx_rate *rates;
d43f3015 728 u32 max_4ms_framelen, frmlen;
c0ac53fa 729 u16 aggr_limit, bt_aggr_limit, legacy = 0;
aa5955c3 730 int q = tid->ac->txq->mac80211_qnum;
e8324357 731 int i;
528f0c6b 732
a22be22a 733 skb = bf->bf_mpdu;
528f0c6b 734 tx_info = IEEE80211_SKB_CB(skb);
0c585dda 735 rates = bf->rates;
528f0c6b 736
e8324357
S		 737 /*
738 * Find the lowest frame length among the rate series that will have a
aa5955c3 739 * 4ms (or TXOP limited) transmit duration.
e8324357
S		 740 */
741 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
e63835b0 742
e8324357 743 for (i = 0; i < 4; i++) {
b0477013 744 int modeidx;
e8324357 745
b0477013
FF		 746 if (!rates[i].count)
747 continue;
545750d3 748
b0477013
FF		 749 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
750 legacy = 1;
751 break;
f078f209 752 }
b0477013
FF		 753
754 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
755 modeidx = MCS_HT40;
756 else
757 modeidx = MCS_HT20;
758
759 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
760 modeidx++;
761
aa5955c3 762 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
b0477013 763 max_4ms_framelen = min(max_4ms_framelen, frmlen);
f078f209 764 }
e63835b0 765
f078f209 766 /*
e8324357
S		 767 * limit aggregate size by the minimum rate if rate selected is
768 * not a probe rate, if rate selected is a probe rate then
769 * avoid aggregation of this packet.
f078f209 770 */
e8324357
S		 771 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
772 return 0;
f078f209 773
c0ac53fa
SM		 774 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
775
776 /*
777 * Override the default aggregation limit for BTCOEX.
778 */
779 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
780 if (bt_aggr_limit)
781 aggr_limit = bt_aggr_limit;
f078f209 782
e8324357 783 /*
25985edc
LDM		 784 * h/w can accept aggregates up to 16 bit lengths (65535).
785 * The IE, however can hold up to 65536, which shows up here
e8324357 786 * as zero. Ignore 65536 since we are constrained by hw.
f078f209 787 */
4ef70841
S		 788 if (tid->an->maxampdu)
789 aggr_limit = min(aggr_limit, tid->an->maxampdu);
f078f209 790
e8324357
S		 791 return aggr_limit;
792}
f078f209 793
e8324357 794/*
d43f3015 795 * Returns the number of delimiters to be added to
e8324357 796 * meet the minimum required mpdudensity.
e8324357
S		 797 */
798static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
7a12dfdb
RM		 799 struct ath_buf *bf, u16 frmlen,
800 bool first_subfrm)
e8324357 801{
7a12dfdb 802#define FIRST_DESC_NDELIMS 60
4ef70841 803 u32 nsymbits, nsymbols;
e8324357 804 u16 minlen;
545750d3 805 u8 flags, rix;
c6663876 806 int width, streams, half_gi, ndelim, mindelim;
2d42efc4 807 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
e8324357
S		 808
809 /* Select standard number of delimiters based on frame length alone */
810 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
f078f209
LR		 811
812 /*
e8324357
S		 813 * If encryption enabled, hardware requires some more padding between
814 * subframes.
815 * TODO - this could be improved to be dependent on the rate.
816 * The hardware can keep up at lower rates, but not higher rates
f078f209 817 */
4f6760b0
RM		 818 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
819 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
e8324357 820 ndelim += ATH_AGGR_ENCRYPTDELIM;
f078f209 821
7a12dfdb
RM		 822 /*
823 * Add delimiter when using RTS/CTS with aggregation
824 * and non enterprise AR9003 card
825 */
3459731a
FF		 826 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
827 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
7a12dfdb
RM		 828 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
829
e8324357
S		 830 /*
831 * Convert desired mpdu density from microeconds to bytes based
832 * on highest rate in rate series (i.e. first rate) to determine
833 * required minimum length for subframe. Take into account
834 * whether high rate is 20 or 40Mhz and half or full GI.
4ef70841 835 *
e8324357
S		 836 * If there is no mpdu density restriction, no further calculation
837 * is needed.
838 */
4ef70841
S		 839
840 if (tid->an->mpdudensity == 0)
e8324357 841 return ndelim;
f078f209 842
79acac07
FF		 843 rix = bf->rates[0].idx;
844 flags = bf->rates[0].flags;
e8324357
S		 845 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
846 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
f078f209 847
e8324357 848 if (half_gi)
4ef70841 849 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
e8324357 850 else
4ef70841 851 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
f078f209 852
e8324357
S		 853 if (nsymbols == 0)
854 nsymbols = 1;
f078f209 855
c6663876
FF		 856 streams = HT_RC_2_STREAMS(rix);
857 nsymbits = bits_per_symbol[rix % 8][width] * streams;
e8324357 858 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
f078f209 859
e8324357 860 if (frmlen < minlen) {
e8324357
S		 861 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
862 ndelim = max(mindelim, ndelim);
f078f209
LR		 863 }
864
e8324357 865 return ndelim;
f078f209
LR		 866}
867
86a22acf
FF		 868static struct ath_buf *
869ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
a7586ee4 870 struct ath_atx_tid *tid, struct sk_buff_head **q)
f078f209 871{
73364b0c 872 struct ieee80211_tx_info *tx_info;
2d42efc4 873 struct ath_frame_info *fi;
56dc6336 874 struct sk_buff *skb;
86a22acf 875 struct ath_buf *bf;
6a0ddaef 876 u16 seqno;
f078f209 877
86a22acf 878 while (1) {
bb195ff6
FF		 879 *q = &tid->retry_q;
880 if (skb_queue_empty(*q))
881 *q = &tid->buf_q;
882
a7586ee4 883 skb = skb_peek(*q);
86a22acf
FF		 884 if (!skb)
885 break;
886
56dc6336
FF		 887 fi = get_frame_info(skb);
888 bf = fi->bf;
44f1d26c 889 if (!fi->bf)
249ee722 890 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
563299d8
FF		 891 else
892 bf->bf_state.stale = false;
56dc6336 893
249ee722 894 if (!bf) {
a7586ee4 895 __skb_unlink(skb, *q);
a4943ccb 896 ath_txq_skb_done(sc, txq, skb);
249ee722 897 ieee80211_free_txskb(sc->hw, skb);
44f1d26c 898 continue;
249ee722 899 }
44f1d26c 900
73364b0c
FF		 901 bf->bf_next = NULL;
902 bf->bf_lastbf = bf;
903
904 tx_info = IEEE80211_SKB_CB(skb);
905 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
906 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
907 bf->bf_state.bf_type = 0;
908 return bf;
909 }
910
399c6489 911 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
44f1d26c 912 seqno = bf->bf_state.seqno;
f078f209 913
d43f3015 914 /* do not step over block-ack window */
86a22acf 915 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno))
e8324357 916 break;
f078f209 917
f9437543
FF		 918 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
919 struct ath_tx_status ts = {};
920 struct list_head bf_head;
921
922 INIT_LIST_HEAD(&bf_head);
923 list_add(&bf->list, &bf_head);
a7586ee4 924 __skb_unlink(skb, *q);
f9437543
FF		 925 ath_tx_update_baw(sc, tid, seqno);
926 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
927 continue;
928 }
929
86a22acf
FF		 930 return bf;
931 }
932
933 return NULL;
934}
935
2800e82b
FF		 936static bool
937ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq,
938 struct ath_atx_tid *tid, struct list_head *bf_q,
939 struct ath_buf *bf_first, struct sk_buff_head *tid_q,
940 int *aggr_len)
86a22acf
FF		 941{
942#define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
2800e82b 943 struct ath_buf *bf = bf_first, *bf_prev = NULL;
a1cd94d3 944 int nframes = 0, ndelim;
86a22acf 945 u16 aggr_limit = 0, al = 0, bpad = 0,
a1cd94d3 946 al_delta, h_baw = tid->baw_size / 2;
86a22acf
FF		 947 struct ieee80211_tx_info *tx_info;
948 struct ath_frame_info *fi;
949 struct sk_buff *skb;
2800e82b 950 bool closed = false;
86a22acf 951
2800e82b
FF		 952 bf = bf_first;
953 aggr_limit = ath_lookup_rate(sc, bf, tid);
86a22acf 954
2800e82b 955 do {
86a22acf
FF		 956 skb = bf->bf_mpdu;
957 fi = get_frame_info(skb);
958
d43f3015 959 /* do not exceed aggregation limit */
2d42efc4 960 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
a1cd94d3
FF		 961 if (nframes) {
962 if (aggr_limit < al + bpad + al_delta ||
2800e82b 963 ath_lookup_legacy(bf) || nframes >= h_baw)
a1cd94d3 964 break;
f078f209 965
a1cd94d3 966 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
2800e82b
FF		 967 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
968 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU))
a1cd94d3 969 break;
e8324357 970 }
f078f209 971
d43f3015 972 /* add padding for previous frame to aggregation length */
e8324357 973 al += bpad + al_delta;
f078f209 974
e8324357
S		 975 /*
976 * Get the delimiters needed to meet the MPDU
977 * density for this node.
978 */
7a12dfdb
RM		 979 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
980 !nframes);
e8324357 981 bpad = PADBYTES(al_delta) + (ndelim << 2);
f078f209 982
7a12dfdb 983 nframes++;
e8324357 984 bf->bf_next = NULL;
f078f209 985
d43f3015 986 /* link buffers of this frame to the aggregate */
8fed1408
FF		 987 if (!fi->baw_tracked)
988 ath_tx_addto_baw(sc, tid, bf);
399c6489 989 bf->bf_state.ndelim = ndelim;
56dc6336 990
a7586ee4 991 __skb_unlink(skb, tid_q);
56dc6336 992 list_add_tail(&bf->list, bf_q);
399c6489 993 if (bf_prev)
e8324357 994 bf_prev->bf_next = bf;
399c6489 995
e8324357 996 bf_prev = bf;
fec247c0 997
2800e82b
FF		 998 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
999 if (!bf) {
1000 closed = true;
1001 break;
1002 }
a7586ee4 1003 } while (ath_tid_has_buffered(tid));
f078f209 1004
2800e82b
FF		 1005 bf = bf_first;
1006 bf->bf_lastbf = bf_prev;
1007
1008 if (bf == bf_prev) {
1009 al = get_frame_info(bf->bf_mpdu)->framelen;
1010 bf->bf_state.bf_type = BUF_AMPDU;
1011 } else {
1012 TX_STAT_INC(txq->axq_qnum, a_aggr);
1013 }
1014
269c44bc 1015 *aggr_len = al;
d43f3015 1016
2800e82b 1017 return closed;
e8324357
S		 1018#undef PADBYTES
1019}
f078f209 1020
38dad7ba
FF		 1021/*
1022 * rix - rate index
1023 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1024 * width - 0 for 20 MHz, 1 for 40 MHz
1025 * half_gi - to use 4us v/s 3.6 us for symbol time
1026 */
1027static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1028 int width, int half_gi, bool shortPreamble)
1029{
1030 u32 nbits, nsymbits, duration, nsymbols;
1031 int streams;
1032
1033 /* find number of symbols: PLCP + data */
1034 streams = HT_RC_2_STREAMS(rix);
1035 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1036 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1037 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1038
1039 if (!half_gi)
1040 duration = SYMBOL_TIME(nsymbols);
1041 else
1042 duration = SYMBOL_TIME_HALFGI(nsymbols);
1043
1044 /* addup duration for legacy/ht training and signal fields */
1045 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1046
1047 return duration;
1048}
1049
aa5955c3
FF		 1050static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1051{
1052 int streams = HT_RC_2_STREAMS(mcs);
1053 int symbols, bits;
1054 int bytes = 0;
1055
1056 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1057 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1058 bits -= OFDM_PLCP_BITS;
1059 bytes = bits / 8;
1060 bytes -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1061 if (bytes > 65532)
1062 bytes = 65532;
1063
1064 return bytes;
1065}
1066
1067void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1068{
1069 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1070 int mcs;
1071
1072 /* 4ms is the default (and maximum) duration */
1073 if (!txop || txop > 4096)
1074 txop = 4096;
1075
1076 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1077 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1078 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1079 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1080 for (mcs = 0; mcs < 32; mcs++) {
1081 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1082 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1083 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1084 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1085 }
1086}
1087
493cf04f 1088static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
a3835e9f 1089 struct ath_tx_info *info, int len, bool rts)
38dad7ba
FF		 1090{
1091 struct ath_hw *ah = sc->sc_ah;
38dad7ba
FF		 1092 struct sk_buff *skb;
1093 struct ieee80211_tx_info *tx_info;
1094 struct ieee80211_tx_rate *rates;
1095 const struct ieee80211_rate *rate;
1096 struct ieee80211_hdr *hdr;
80b08a8d 1097 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
a3835e9f 1098 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
493cf04f
FF		 1099 int i;
1100 u8 rix = 0;
38dad7ba
FF		 1101
1102 skb = bf->bf_mpdu;
1103 tx_info = IEEE80211_SKB_CB(skb);
79acac07 1104 rates = bf->rates;
38dad7ba 1105 hdr = (struct ieee80211_hdr *)skb->data;
493cf04f
FF		 1106
1107 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1108 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
80b08a8d 1109 info->rtscts_rate = fi->rtscts_rate;
38dad7ba 1110
79acac07 1111 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
38dad7ba
FF		 1112 bool is_40, is_sgi, is_sp;
1113 int phy;
1114
1115 if (!rates[i].count || (rates[i].idx < 0))
1116 continue;
1117
1118 rix = rates[i].idx;
493cf04f 1119 info->rates[i].Tries = rates[i].count;
38dad7ba 1120
a3835e9f
SM		 1121 /*
1122 * Handle RTS threshold for unaggregated HT frames.
1123 */
1124 if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1125 (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1126 unlikely(rts_thresh != (u32) -1)) {
1127 if (!rts_thresh || (len > rts_thresh))
1128 rts = true;
1129 }
1130
1131 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
493cf04f
FF		 1132 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1133 info->flags |= ATH9K_TXDESC_RTSENA;
38dad7ba 1134 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
493cf04f
FF		 1135 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1136 info->flags |= ATH9K_TXDESC_CTSENA;
38dad7ba
FF		 1137 }
1138
1139 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
493cf04f 1140 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
38dad7ba 1141 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
493cf04f 1142 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
38dad7ba
FF		 1143
1144 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1145 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1146 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1147
1148 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1149 /* MCS rates */
493cf04f
FF		 1150 info->rates[i].Rate = rix | 0x80;
1151 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1152 ah->txchainmask, info->rates[i].Rate);
1153 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
38dad7ba
FF		 1154 is_40, is_sgi, is_sp);
1155 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
493cf04f 1156 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
38dad7ba
FF		 1157 continue;
1158 }
1159
1160 /* legacy rates */
76591bea 1161 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
38dad7ba
FF		 1162 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1163 !(rate->flags & IEEE80211_RATE_ERP_G))
1164 phy = WLAN_RC_PHY_CCK;
1165 else
1166 phy = WLAN_RC_PHY_OFDM;
1167
493cf04f 1168 info->rates[i].Rate = rate->hw_value;
38dad7ba
FF		 1169 if (rate->hw_value_short) {
1170 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
493cf04f 1171 info->rates[i].Rate |= rate->hw_value_short;
38dad7ba
FF		 1172 } else {
1173 is_sp = false;
1174 }
1175
1176 if (bf->bf_state.bfs_paprd)
493cf04f 1177 info->rates[i].ChSel = ah->txchainmask;
38dad7ba 1178 else
493cf04f
FF		 1179 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1180 ah->txchainmask, info->rates[i].Rate);
38dad7ba 1181
493cf04f 1182 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
38dad7ba
FF		 1183 phy, rate->bitrate * 100, len, rix, is_sp);
1184 }
1185
1186 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1187 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
493cf04f 1188 info->flags &= ~ATH9K_TXDESC_RTSENA;
38dad7ba
FF		 1189
1190 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
493cf04f
FF		 1191 if (info->flags & ATH9K_TXDESC_RTSENA)
1192 info->flags &= ~ATH9K_TXDESC_CTSENA;
1193}
38dad7ba 1194
493cf04f
FF		 1195static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1196{
1197 struct ieee80211_hdr *hdr;
1198 enum ath9k_pkt_type htype;
1199 __le16 fc;
1200
1201 hdr = (struct ieee80211_hdr *)skb->data;
1202 fc = hdr->frame_control;
38dad7ba 1203
493cf04f
FF		 1204 if (ieee80211_is_beacon(fc))
1205 htype = ATH9K_PKT_TYPE_BEACON;
1206 else if (ieee80211_is_probe_resp(fc))
1207 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1208 else if (ieee80211_is_atim(fc))
1209 htype = ATH9K_PKT_TYPE_ATIM;
1210 else if (ieee80211_is_pspoll(fc))
1211 htype = ATH9K_PKT_TYPE_PSPOLL;
1212 else
1213 htype = ATH9K_PKT_TYPE_NORMAL;
1214
1215 return htype;
38dad7ba
FF		 1216}
1217
493cf04f
FF		 1218static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1219 struct ath_txq *txq, int len)
399c6489
FF		 1220{
1221 struct ath_hw *ah = sc->sc_ah;
86a22acf 1222 struct ath_buf *bf_first = NULL;
493cf04f 1223 struct ath_tx_info info;
a3835e9f
SM		 1224 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1225 bool rts = false;
399c6489 1226
493cf04f
FF		 1227 memset(&info, 0, sizeof(info));
1228 info.is_first = true;
1229 info.is_last = true;
1230 info.txpower = MAX_RATE_POWER;
1231 info.qcu = txq->axq_qnum;
1232
399c6489 1233 while (bf) {
493cf04f 1234 struct sk_buff *skb = bf->bf_mpdu;
86a22acf 1235 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
493cf04f 1236 struct ath_frame_info *fi = get_frame_info(skb);
86a22acf 1237 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
493cf04f
FF		 1238
1239 info.type = get_hw_packet_type(skb);
399c6489 1240 if (bf->bf_next)
493cf04f 1241 info.link = bf->bf_next->bf_daddr;
399c6489 1242 else
493cf04f
FF		 1243 info.link = 0;
1244
86a22acf
FF		 1245 if (!bf_first) {
1246 bf_first = bf;
1247
1248 info.flags = ATH9K_TXDESC_INTREQ;
1249 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1250 txq == sc->tx.uapsdq)
1251 info.flags |= ATH9K_TXDESC_CLRDMASK;
1252
1253 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1254 info.flags |= ATH9K_TXDESC_NOACK;
1255 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1256 info.flags |= ATH9K_TXDESC_LDPC;
1257
1258 if (bf->bf_state.bfs_paprd)
1259 info.flags |= (u32) bf->bf_state.bfs_paprd <<
1260 ATH9K_TXDESC_PAPRD_S;
1261
a3835e9f
SM		 1262 /*
1263 * mac80211 doesn't handle RTS threshold for HT because
1264 * the decision has to be taken based on AMPDU length
1265 * and aggregation is done entirely inside ath9k.
1266 * Set the RTS/CTS flag for the first subframe based
1267 * on the threshold.
1268 */
1269 if (aggr && (bf == bf_first) &&
1270 unlikely(rts_thresh != (u32) -1)) {
1271 /*
1272 * "len" is the size of the entire AMPDU.
1273 */
1274 if (!rts_thresh || (len > rts_thresh))
1275 rts = true;
1276 }
1277 ath_buf_set_rate(sc, bf, &info, len, rts);
86a22acf
FF		 1278 }
1279
42cecc34
JL		 1280 info.buf_addr[0] = bf->bf_buf_addr;
1281 info.buf_len[0] = skb->len;
493cf04f
FF		 1282 info.pkt_len = fi->framelen;
1283 info.keyix = fi->keyix;
1284 info.keytype = fi->keytype;
1285
1286 if (aggr) {
399c6489 1287 if (bf == bf_first)
493cf04f 1288 info.aggr = AGGR_BUF_FIRST;
86a22acf 1289 else if (bf == bf_first->bf_lastbf)
493cf04f
FF		 1290 info.aggr = AGGR_BUF_LAST;
1291 else
1292 info.aggr = AGGR_BUF_MIDDLE;
399c6489 1293
493cf04f
FF		 1294 info.ndelim = bf->bf_state.ndelim;
1295 info.aggr_len = len;
399c6489
FF		 1296 }
1297
86a22acf
FF		 1298 if (bf == bf_first->bf_lastbf)
1299 bf_first = NULL;
1300
493cf04f 1301 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
399c6489
FF		 1302 bf = bf->bf_next;
1303 }
1304}
1305
2800e82b
FF		 1306static void
1307ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq,
1308 struct ath_atx_tid *tid, struct list_head *bf_q,
1309 struct ath_buf *bf_first, struct sk_buff_head *tid_q)
1310{
1311 struct ath_buf *bf = bf_first, *bf_prev = NULL;
1312 struct sk_buff *skb;
1313 int nframes = 0;
1314
1315 do {
1316 struct ieee80211_tx_info *tx_info;
1317 skb = bf->bf_mpdu;
1318
1319 nframes++;
1320 __skb_unlink(skb, tid_q);
1321 list_add_tail(&bf->list, bf_q);
1322 if (bf_prev)
1323 bf_prev->bf_next = bf;
1324 bf_prev = bf;
1325
1326 if (nframes >= 2)
1327 break;
1328
1329 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1330 if (!bf)
1331 break;
1332
1333 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1334 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1335 break;
1336
1337 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1338 } while (1);
1339}
1340
020f20f6
FF		 1341static bool ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1342 struct ath_atx_tid *tid, bool *stop)
e8324357 1343{
d43f3015 1344 struct ath_buf *bf;
399c6489 1345 struct ieee80211_tx_info *tx_info;
2800e82b 1346 struct sk_buff_head *tid_q;
e8324357 1347 struct list_head bf_q;
2800e82b
FF		 1348 int aggr_len = 0;
1349 bool aggr, last = true;
f078f209 1350
020f20f6
FF		 1351 if (!ath_tid_has_buffered(tid))
1352 return false;
f078f209 1353
020f20f6 1354 INIT_LIST_HEAD(&bf_q);
e8324357 1355
020f20f6
FF		 1356 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1357 if (!bf)
1358 return false;
f078f209 1359
020f20f6
FF		 1360 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1361 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1362 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) ||
1363 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) {
1364 *stop = true;
1365 return false;
1366 }
2800e82b 1367
020f20f6
FF		 1368 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1369 if (aggr)
1370 last = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf,
1371 tid_q, &aggr_len);
1372 else
1373 ath_tx_form_burst(sc, txq, tid, &bf_q, bf, tid_q);
2800e82b 1374
020f20f6
FF		 1375 if (list_empty(&bf_q))
1376 return false;
f078f209 1377
f89d1bc4 1378 if (tid->ac->clear_ps_filter || tid->an->no_ps_filter) {
020f20f6
FF		 1379 tid->ac->clear_ps_filter = false;
1380 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1381 }
f078f209 1382
020f20f6
FF		 1383 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1384 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1385 return true;
e8324357
S		 1386}
1387
231c3a1f
FF		 1388int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1389 u16 tid, u16 *ssn)
e8324357
S		 1390{
1391 struct ath_atx_tid *txtid;
1392 struct ath_node *an;
313eb87f 1393 u8 density;
e8324357
S		 1394
1395 an = (struct ath_node *)sta->drv_priv;
f83da965 1396 txtid = ATH_AN_2_TID(an, tid);
231c3a1f 1397
313eb87f
SE		 1398 /* update ampdu factor/density, they may have changed. This may happen
1399 * in HT IBSS when a beacon with HT-info is received after the station
1400 * has already been added.
1401 */
dd5ee59b 1402 if (sta->ht_cap.ht_supported) {
313eb87f
SE		 1403 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1404 sta->ht_cap.ampdu_factor);
1405 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1406 an->mpdudensity = density;
1407 }
1408
2800e82b
FF		 1409 /* force sequence number allocation for pending frames */
1410 ath_tx_tid_change_state(sc, txtid);
1411
08c96abd 1412 txtid->active = true;
75401849 1413 txtid->paused = true;
49447f2f 1414 *ssn = txtid->seq_start = txtid->seq_next;
f9437543 1415 txtid->bar_index = -1;
231c3a1f 1416
2ed72229
FF		 1417 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1418 txtid->baw_head = txtid->baw_tail = 0;
1419
231c3a1f 1420 return 0;
e8324357 1421}
f078f209 1422
08c96abd 1423void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
e8324357
S		 1424{
1425 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1426 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
066dae93 1427 struct ath_txq *txq = txtid->ac->txq;
f078f209 1428
23de5dc9 1429 ath_txq_lock(sc, txq);
08c96abd 1430 txtid->active = false;
73364b0c 1431 txtid->paused = false;
08c96abd 1432 ath_tx_flush_tid(sc, txtid);
2800e82b 1433 ath_tx_tid_change_state(sc, txtid);
23de5dc9 1434 ath_txq_unlock_complete(sc, txq);
e8324357 1435}
f078f209 1436
042ec453
JB		 1437void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1438 struct ath_node *an)
5519541d
FF		 1439{
1440 struct ath_atx_tid *tid;
1441 struct ath_atx_ac *ac;
1442 struct ath_txq *txq;
042ec453 1443 bool buffered;
5519541d
FF		 1444 int tidno;
1445
1446 for (tidno = 0, tid = &an->tid[tidno];
de7b7604 1447 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
5519541d
FF		 1448
1449 if (!tid->sched)
1450 continue;
1451
1452 ac = tid->ac;
1453 txq = ac->txq;
1454
23de5dc9 1455 ath_txq_lock(sc, txq);
5519541d 1456
a7586ee4 1457 buffered = ath_tid_has_buffered(tid);
5519541d
FF		 1458
1459 tid->sched = false;
1460 list_del(&tid->list);
1461
1462 if (ac->sched) {
1463 ac->sched = false;
1464 list_del(&ac->list);
1465 }
1466
23de5dc9 1467 ath_txq_unlock(sc, txq);
5519541d 1468
042ec453
JB		 1469 ieee80211_sta_set_buffered(sta, tidno, buffered);
1470 }
5519541d
FF		 1471}
1472
1473void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1474{
1475 struct ath_atx_tid *tid;
1476 struct ath_atx_ac *ac;
1477 struct ath_txq *txq;
1478 int tidno;
1479
1480 for (tidno = 0, tid = &an->tid[tidno];
de7b7604 1481 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
5519541d
FF		 1482
1483 ac = tid->ac;
1484 txq = ac->txq;
1485
23de5dc9 1486 ath_txq_lock(sc, txq);
5519541d
FF		 1487 ac->clear_ps_filter = true;
1488
a7586ee4 1489 if (!tid->paused && ath_tid_has_buffered(tid)) {
5519541d
FF		 1490 ath_tx_queue_tid(txq, tid);
1491 ath_txq_schedule(sc, txq);
1492 }
1493
23de5dc9 1494 ath_txq_unlock_complete(sc, txq);
5519541d
FF		 1495 }
1496}
1497
08c96abd
FF		 1498void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta,
1499 u16 tidno)
e8324357 1500{
08c96abd 1501 struct ath_atx_tid *tid;
e8324357 1502 struct ath_node *an;
08c96abd 1503 struct ath_txq *txq;
e8324357
S		 1504
1505 an = (struct ath_node *)sta->drv_priv;
08c96abd
FF		 1506 tid = ATH_AN_2_TID(an, tidno);
1507 txq = tid->ac->txq;
e8324357 1508
08c96abd
FF		 1509 ath_txq_lock(sc, txq);
1510
1511 tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1512 tid->paused = false;
1513
a7586ee4 1514 if (ath_tid_has_buffered(tid)) {
08c96abd
FF		 1515 ath_tx_queue_tid(txq, tid);
1516 ath_txq_schedule(sc, txq);
1517 }
1518
1519 ath_txq_unlock_complete(sc, txq);
f078f209
LR		 1520}
1521
86a22acf
FF		 1522void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1523 struct ieee80211_sta *sta,
1524 u16 tids, int nframes,
1525 enum ieee80211_frame_release_type reason,
1526 bool more_data)
1527{
1528 struct ath_softc *sc = hw->priv;
1529 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1530 struct ath_txq *txq = sc->tx.uapsdq;
1531 struct ieee80211_tx_info *info;
1532 struct list_head bf_q;
1533 struct ath_buf *bf_tail = NULL, *bf;
a7586ee4 1534 struct sk_buff_head *tid_q;
86a22acf
FF		 1535 int sent = 0;
1536 int i;
1537
1538 INIT_LIST_HEAD(&bf_q);
1539 for (i = 0; tids && nframes; i++, tids >>= 1) {
1540 struct ath_atx_tid *tid;
1541
1542 if (!(tids & 1))
1543 continue;
1544
1545 tid = ATH_AN_2_TID(an, i);
1546 if (tid->paused)
1547 continue;
1548
1549 ath_txq_lock(sc, tid->ac->txq);
a7586ee4
FF		 1550 while (nframes > 0) {
1551 bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid, &tid_q);
86a22acf
FF		 1552 if (!bf)
1553 break;
1554
a7586ee4 1555 __skb_unlink(bf->bf_mpdu, tid_q);
86a22acf
FF		 1556 list_add_tail(&bf->list, &bf_q);
1557 ath_set_rates(tid->an->vif, tid->an->sta, bf);
8fed1408 1558 ath_tx_addto_baw(sc, tid, bf);
86a22acf
FF		 1559 bf->bf_state.bf_type &= ~BUF_AGGR;
1560 if (bf_tail)
1561 bf_tail->bf_next = bf;
1562
1563 bf_tail = bf;
1564 nframes--;
1565 sent++;
1566 TX_STAT_INC(txq->axq_qnum, a_queued_hw);
1567
f89d1bc4 1568 if (an->sta && !ath_tid_has_buffered(tid))
86a22acf
FF		 1569 ieee80211_sta_set_buffered(an->sta, i, false);
1570 }
1571 ath_txq_unlock_complete(sc, tid->ac->txq);
1572 }
1573
1574 if (list_empty(&bf_q))
1575 return;
1576
1577 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1578 info->flags |= IEEE80211_TX_STATUS_EOSP;
1579
1580 bf = list_first_entry(&bf_q, struct ath_buf, list);
1581 ath_txq_lock(sc, txq);
1582 ath_tx_fill_desc(sc, bf, txq, 0);
1583 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1584 ath_txq_unlock(sc, txq);
1585}
1586
e8324357
S		 1587/********************/
1588/* Queue Management */
1589/********************/
f078f209 1590
e8324357 1591struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
f078f209 1592{
cbe61d8a 1593 struct ath_hw *ah = sc->sc_ah;
e8324357 1594 struct ath9k_tx_queue_info qi;
066dae93 1595 static const int subtype_txq_to_hwq[] = {
bea843c7
SM		 1596 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1597 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1598 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1599 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
066dae93 1600 };
60f2d1d5 1601 int axq_qnum, i;
f078f209 1602
e8324357 1603 memset(&qi, 0, sizeof(qi));
066dae93 1604 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
e8324357
S		 1605 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1606 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1607 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1608 qi.tqi_physCompBuf = 0;
f078f209
LR		 1609
1610 /*
e8324357
S		 1611 * Enable interrupts only for EOL and DESC conditions.
1612 * We mark tx descriptors to receive a DESC interrupt
1613 * when a tx queue gets deep; otherwise waiting for the
1614 * EOL to reap descriptors. Note that this is done to
1615 * reduce interrupt load and this only defers reaping
1616 * descriptors, never transmitting frames. Aside from
1617 * reducing interrupts this also permits more concurrency.
1618 * The only potential downside is if the tx queue backs
1619 * up in which case the top half of the kernel may backup
1620 * due to a lack of tx descriptors.
1621 *
1622 * The UAPSD queue is an exception, since we take a desc-
1623 * based intr on the EOSP frames.
f078f209 1624 */
afe754d6 1625 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
ce8fdf6e 1626 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
afe754d6
VT		 1627 } else {
1628 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1629 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1630 else
1631 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1632 TXQ_FLAG_TXDESCINT_ENABLE;
1633 }
60f2d1d5
BG		 1634 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1635 if (axq_qnum == -1) {
f078f209 1636 /*
e8324357
S		 1637 * NB: don't print a message, this happens
1638 * normally on parts with too few tx queues
f078f209 1639 */
e8324357 1640 return NULL;
f078f209 1641 }
60f2d1d5
BG		 1642 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1643 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
f078f209 1644
60f2d1d5
BG		 1645 txq->axq_qnum = axq_qnum;
1646 txq->mac80211_qnum = -1;
e8324357 1647 txq->axq_link = NULL;
23de5dc9 1648 __skb_queue_head_init(&txq->complete_q);
e8324357
S		 1649 INIT_LIST_HEAD(&txq->axq_q);
1650 INIT_LIST_HEAD(&txq->axq_acq);
1651 spin_lock_init(&txq->axq_lock);
1652 txq->axq_depth = 0;
4b3ba66a 1653 txq->axq_ampdu_depth = 0;
164ace38 1654 txq->axq_tx_inprogress = false;
60f2d1d5 1655 sc->tx.txqsetup |= 1<<axq_qnum;
e5003249
VT		 1656
1657 txq->txq_headidx = txq->txq_tailidx = 0;
1658 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1659 INIT_LIST_HEAD(&txq->txq_fifo[i]);
e8324357 1660 }
60f2d1d5 1661 return &sc->tx.txq[axq_qnum];
f078f209
LR		 1662}
1663
e8324357
S		 1664int ath_txq_update(struct ath_softc *sc, int qnum,
1665 struct ath9k_tx_queue_info *qinfo)
1666{
cbe61d8a 1667 struct ath_hw *ah = sc->sc_ah;
e8324357
S		 1668 int error = 0;
1669 struct ath9k_tx_queue_info qi;
1670
9680e8a3 1671 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
e8324357
S		 1672
1673 ath9k_hw_get_txq_props(ah, qnum, &qi);
1674 qi.tqi_aifs = qinfo->tqi_aifs;
1675 qi.tqi_cwmin = qinfo->tqi_cwmin;
1676 qi.tqi_cwmax = qinfo->tqi_cwmax;
1677 qi.tqi_burstTime = qinfo->tqi_burstTime;
1678 qi.tqi_readyTime = qinfo->tqi_readyTime;
1679
1680 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
3800276a
JP		 1681 ath_err(ath9k_hw_common(sc->sc_ah),
1682 "Unable to update hardware queue %u!\n", qnum);
e8324357
S		 1683 error = -EIO;
1684 } else {
1685 ath9k_hw_resettxqueue(ah, qnum);
1686 }
1687
1688 return error;
1689}
1690
1691int ath_cabq_update(struct ath_softc *sc)
1692{
1693 struct ath9k_tx_queue_info qi;
9814f6b3 1694 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
e8324357 1695 int qnum = sc->beacon.cabq->axq_qnum;
f078f209 1696
e8324357 1697 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
f078f209 1698 /*
e8324357 1699 * Ensure the readytime % is within the bounds.
f078f209 1700 */
17d7904d
S		 1701 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1702 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1703 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1704 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
f078f209 1705
9814f6b3 1706 qi.tqi_readyTime = (cur_conf->beacon_interval *
fdbf7335 1707 sc->config.cabqReadytime) / 100;
e8324357
S		 1708 ath_txq_update(sc, qnum, &qi);
1709
1710 return 0;
f078f209
LR		 1711}
1712
fce041be 1713static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1381559b 1714 struct list_head *list)
f078f209 1715{
e8324357
S		 1716 struct ath_buf *bf, *lastbf;
1717 struct list_head bf_head;
db1a052b
FF		 1718 struct ath_tx_status ts;
1719
1720 memset(&ts, 0, sizeof(ts));
daa5c408 1721 ts.ts_status = ATH9K_TX_FLUSH;
e8324357 1722 INIT_LIST_HEAD(&bf_head);
f078f209 1723
fce041be
FF		 1724 while (!list_empty(list)) {
1725 bf = list_first_entry(list, struct ath_buf, list);
f078f209 1726
50676b81 1727 if (bf->bf_state.stale) {
fce041be 1728 list_del(&bf->list);
f078f209 1729
fce041be
FF		 1730 ath_tx_return_buffer(sc, bf);
1731 continue;
e8324357 1732 }
f078f209 1733
e8324357 1734 lastbf = bf->bf_lastbf;
fce041be 1735 list_cut_position(&bf_head, list, &lastbf->list);
81b51950 1736 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
f078f209 1737 }
fce041be 1738}
f078f209 1739
fce041be
FF		 1740/*
1741 * Drain a given TX queue (could be Beacon or Data)
1742 *
1743 * This assumes output has been stopped and
1744 * we do not need to block ath_tx_tasklet.
1745 */
1381559b 1746void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
fce041be 1747{
23de5dc9
FF		 1748 ath_txq_lock(sc, txq);
1749
e5003249 1750 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
fce041be 1751 int idx = txq->txq_tailidx;
e5003249 1752
fce041be 1753 while (!list_empty(&txq->txq_fifo[idx])) {
1381559b 1754 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
fce041be
FF		 1755
1756 INCR(idx, ATH_TXFIFO_DEPTH);
e5003249 1757 }
fce041be 1758 txq->txq_tailidx = idx;
e5003249 1759 }
e609e2ea 1760
fce041be
FF		 1761 txq->axq_link = NULL;
1762 txq->axq_tx_inprogress = false;
1381559b 1763 ath_drain_txq_list(sc, txq, &txq->axq_q);
fce041be 1764
23de5dc9 1765 ath_txq_unlock_complete(sc, txq);
f078f209
LR		 1766}
1767
1381559b 1768bool ath_drain_all_txq(struct ath_softc *sc)
f078f209 1769{
cbe61d8a 1770 struct ath_hw *ah = sc->sc_ah;
c46917bb 1771 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
043a0405 1772 struct ath_txq *txq;
34d25810
FF		 1773 int i;
1774 u32 npend = 0;
043a0405 1775
781b14a3 1776 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
080e1a25 1777 return true;
043a0405 1778
0d51cccc 1779 ath9k_hw_abort_tx_dma(ah);
043a0405 1780
0d51cccc 1781 /* Check if any queue remains active */
043a0405 1782 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
0d51cccc
FF		 1783 if (!ATH_TXQ_SETUP(sc, i))
1784 continue;
1785
34d25810
FF		 1786 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1787 npend |= BIT(i);
043a0405
S		 1788 }
1789
080e1a25 1790 if (npend)
34d25810 1791 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
043a0405
S		 1792
1793 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
92460412
FF		 1794 if (!ATH_TXQ_SETUP(sc, i))
1795 continue;
1796
1797 /*
1798 * The caller will resume queues with ieee80211_wake_queues.
1799 * Mark the queue as not stopped to prevent ath_tx_complete
1800 * from waking the queue too early.
1801 */
1802 txq = &sc->tx.txq[i];
1803 txq->stopped = false;
1381559b 1804 ath_draintxq(sc, txq);
043a0405 1805 }
080e1a25
FF		 1806
1807 return !npend;
e8324357 1808}
f078f209 1809
043a0405 1810void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
e8324357 1811{
043a0405
S		 1812 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1813 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
e8324357 1814}
f078f209 1815
7755bad9
BG		 1816/* For each axq_acq entry, for each tid, try to schedule packets
1817 * for transmit until ampdu_depth has reached min Q depth.
1818 */
e8324357
S		 1819void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1820{
020f20f6 1821 struct ath_atx_ac *ac, *last_ac;
7755bad9 1822 struct ath_atx_tid *tid, *last_tid;
020f20f6 1823 bool sent = false;
f078f209 1824
124b979b 1825 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags) ||
020f20f6 1826 list_empty(&txq->axq_acq))
e8324357 1827 return;
f078f209 1828
23bc2021
FF		 1829 rcu_read_lock();
1830
7755bad9 1831 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
020f20f6
FF		 1832 while (!list_empty(&txq->axq_acq)) {
1833 bool stop = false;
f078f209 1834
020f20f6 1835 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
7755bad9
BG		 1836 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1837 list_del(&ac->list);
1838 ac->sched = false;
f078f209 1839
7755bad9 1840 while (!list_empty(&ac->tid_q)) {
020f20f6 1841
7755bad9
BG		 1842 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1843 list);
1844 list_del(&tid->list);
1845 tid->sched = false;
f078f209 1846
7755bad9
BG		 1847 if (tid->paused)
1848 continue;
f078f209 1849
020f20f6
FF		 1850 if (ath_tx_sched_aggr(sc, txq, tid, &stop))
1851 sent = true;
f078f209 1852
7755bad9
BG		 1853 /*
1854 * add tid to round-robin queue if more frames
1855 * are pending for the tid
1856 */
a7586ee4 1857 if (ath_tid_has_buffered(tid))
7755bad9 1858 ath_tx_queue_tid(txq, tid);
f078f209 1859
020f20f6 1860 if (stop || tid == last_tid)
7755bad9
BG		 1861 break;
1862 }
f078f209 1863
b0477013
FF		 1864 if (!list_empty(&ac->tid_q) && !ac->sched) {
1865 ac->sched = true;
1866 list_add_tail(&ac->list, &txq->axq_acq);
f078f209 1867 }
7755bad9 1868
020f20f6 1869 if (stop)
23bc2021 1870 break;
020f20f6
FF		 1871
1872 if (ac == last_ac) {
1873 if (!sent)
1874 break;
1875
1876 sent = false;
1877 last_ac = list_entry(txq->axq_acq.prev,
1878 struct ath_atx_ac, list);
1879 }
e8324357 1880 }
23bc2021
FF		 1881
1882 rcu_read_unlock();
e8324357 1883}
f078f209 1884
e8324357
S		 1885/***********/
1886/* TX, DMA */
1887/***********/
1888
f078f209 1889/*
e8324357
S		 1890 * Insert a chain of ath_buf (descriptors) on a txq and
1891 * assume the descriptors are already chained together by caller.
f078f209 1892 */
e8324357 1893static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
fce041be 1894 struct list_head *head, bool internal)
f078f209 1895{
cbe61d8a 1896 struct ath_hw *ah = sc->sc_ah;
c46917bb 1897 struct ath_common *common = ath9k_hw_common(ah);
fce041be
FF		 1898 struct ath_buf *bf, *bf_last;
1899 bool puttxbuf = false;
1900 bool edma;
f078f209 1901
e8324357
S		 1902 /*
1903 * Insert the frame on the outbound list and
1904 * pass it on to the hardware.
1905 */
f078f209 1906
e8324357
S		 1907 if (list_empty(head))
1908 return;
f078f209 1909
fce041be 1910 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
e8324357 1911 bf = list_first_entry(head, struct ath_buf, list);
fce041be 1912 bf_last = list_entry(head->prev, struct ath_buf, list);
f078f209 1913
d2182b69
JP		 1914 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
1915 txq->axq_qnum, txq->axq_depth);
f078f209 1916
fce041be
FF		 1917 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1918 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
e5003249 1919 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
fce041be 1920 puttxbuf = true;
e8324357 1921 } else {
e5003249
VT		 1922 list_splice_tail_init(head, &txq->axq_q);
1923
fce041be
FF		 1924 if (txq->axq_link) {
1925 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
d2182b69 1926 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
226afe68
JP		 1927 txq->axq_qnum, txq->axq_link,
1928 ito64(bf->bf_daddr), bf->bf_desc);
fce041be
FF		 1929 } else if (!edma)
1930 puttxbuf = true;
1931
1932 txq->axq_link = bf_last->bf_desc;
1933 }
1934
1935 if (puttxbuf) {
1936 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1937 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
d2182b69 1938 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
fce041be
FF		 1939 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1940 }
1941
1942 if (!edma) {
8d8d3fdc 1943 TX_STAT_INC(txq->axq_qnum, txstart);
e5003249 1944 ath9k_hw_txstart(ah, txq->axq_qnum);
e8324357 1945 }
fce041be
FF		 1946
1947 if (!internal) {
f56e121d
FF		 1948 while (bf) {
1949 txq->axq_depth++;
1950 if (bf_is_ampdu_not_probing(bf))
1951 txq->axq_ampdu_depth++;
1952
1953 bf = bf->bf_lastbf->bf_next;
1954 }
fce041be 1955 }
e8324357 1956}
f078f209 1957
82b873af 1958static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
44f1d26c 1959 struct ath_atx_tid *tid, struct sk_buff *skb)
e8324357 1960{
44f1d26c
FF		 1961 struct ath_frame_info *fi = get_frame_info(skb);
1962 struct list_head bf_head;
e8324357
S		 1963 struct ath_buf *bf;
1964
44f1d26c 1965 bf = fi->bf;
44f1d26c
FF		 1966
1967 INIT_LIST_HEAD(&bf_head);
1968 list_add_tail(&bf->list, &bf_head);
399c6489 1969 bf->bf_state.bf_type = 0;
e8324357 1970
8c6e3093 1971 bf->bf_next = NULL;
d43f3015 1972 bf->bf_lastbf = bf;
493cf04f 1973 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
44f1d26c 1974 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
fec247c0 1975 TX_STAT_INC(txq->axq_qnum, queued);
e8324357
S		 1976}
1977
36323f81
TH		 1978static void setup_frame_info(struct ieee80211_hw *hw,
1979 struct ieee80211_sta *sta,
1980 struct sk_buff *skb,
2d42efc4 1981 int framelen)
e8324357
S		 1982{
1983 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2d42efc4 1984 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
6a0ddaef 1985 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
80b08a8d 1986 const struct ieee80211_rate *rate;
2d42efc4 1987 struct ath_frame_info *fi = get_frame_info(skb);
93ae2dd2 1988 struct ath_node *an = NULL;
2d42efc4 1989 enum ath9k_key_type keytype;
80b08a8d
FF		 1990 bool short_preamble = false;
1991
1992 /*
1993 * We check if Short Preamble is needed for the CTS rate by
1994 * checking the BSS's global flag.
1995 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1996 */
1997 if (tx_info->control.vif &&
1998 tx_info->control.vif->bss_conf.use_short_preamble)
1999 short_preamble = true;
e8324357 2000
80b08a8d 2001 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
2d42efc4 2002 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
e8324357 2003
93ae2dd2
FF		 2004 if (sta)
2005 an = (struct ath_node *) sta->drv_priv;
2006
2d42efc4
FF		 2007 memset(fi, 0, sizeof(*fi));
2008 if (hw_key)
2009 fi->keyix = hw_key->hw_key_idx;
93ae2dd2
FF		 2010 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
2011 fi->keyix = an->ps_key;
2d42efc4
FF		 2012 else
2013 fi->keyix = ATH9K_TXKEYIX_INVALID;
2014 fi->keytype = keytype;
2015 fi->framelen = framelen;
80b08a8d
FF		 2016 fi->rtscts_rate = rate->hw_value;
2017 if (short_preamble)
2018 fi->rtscts_rate |= rate->hw_value_short;
e8324357
S		 2019}
2020
ea066d5a
MSS		 2021u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
2022{
2023 struct ath_hw *ah = sc->sc_ah;
2024 struct ath9k_channel *curchan = ah->curchan;
365d2ebc 2025
8896934c 2026 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) &&
d77bf3eb 2027 (chainmask == 0x7) && (rate < 0x90))
ea066d5a 2028 return 0x3;
365d2ebc
SM		 2029 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2030 IS_CCK_RATE(rate))
2031 return 0x2;
ea066d5a
MSS		 2032 else
2033 return chainmask;
2034}
2035
44f1d26c
FF		 2036/*
2037 * Assign a descriptor (and sequence number if necessary,
2038 * and map buffer for DMA. Frees skb on error
2039 */
fa05f87a 2040static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
04caf863 2041 struct ath_txq *txq,
fa05f87a 2042 struct ath_atx_tid *tid,
249ee722 2043 struct sk_buff *skb)
f078f209 2044{
82b873af 2045 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2d42efc4 2046 struct ath_frame_info *fi = get_frame_info(skb);
fa05f87a 2047 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
82b873af 2048 struct ath_buf *bf;
fd09c85f 2049 int fragno;
fa05f87a 2050 u16 seqno;
82b873af
FF		 2051
2052 bf = ath_tx_get_buffer(sc);
2053 if (!bf) {
d2182b69 2054 ath_dbg(common, XMIT, "TX buffers are full\n");
249ee722 2055 return NULL;
82b873af 2056 }
e022edbd 2057
528f0c6b 2058 ATH_TXBUF_RESET(bf);
f078f209 2059
fa05f87a 2060 if (tid) {
fd09c85f 2061 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
fa05f87a
FF		 2062 seqno = tid->seq_next;
2063 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
fd09c85f
SM		 2064
2065 if (fragno)
2066 hdr->seq_ctrl |= cpu_to_le16(fragno);
2067
2068 if (!ieee80211_has_morefrags(hdr->frame_control))
2069 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2070
fa05f87a
FF		 2071 bf->bf_state.seqno = seqno;
2072 }
2073
f078f209 2074 bf->bf_mpdu = skb;
f8316df1 2075
c1739eb3
BG		 2076 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2077 skb->len, DMA_TO_DEVICE);
2078 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
f8316df1 2079 bf->bf_mpdu = NULL;
6cf9e995 2080 bf->bf_buf_addr = 0;
3800276a
JP		 2081 ath_err(ath9k_hw_common(sc->sc_ah),
2082 "dma_mapping_error() on TX\n");
82b873af 2083 ath_tx_return_buffer(sc, bf);
249ee722 2084 return NULL;
f8316df1
LR		 2085 }
2086
56dc6336 2087 fi->bf = bf;
04caf863
FF		 2088
2089 return bf;
2090}
2091
59505c02
FF		 2092static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2093 struct ath_tx_control *txctl)
f078f209 2094{
28d16708
FF		 2095 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2096 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
36323f81 2097 struct ieee80211_sta *sta = txctl->sta;
f59a59fe 2098 struct ieee80211_vif *vif = info->control.vif;
f89d1bc4 2099 struct ath_vif *avp;
9ac58615 2100 struct ath_softc *sc = hw->priv;
04caf863 2101 int frmlen = skb->len + FCS_LEN;
59505c02 2102 int padpos, padsize;
f078f209 2103
a9927ba3
BG		 2104 /* NOTE: sta can be NULL according to net/mac80211.h */
2105 if (sta)
2106 txctl->an = (struct ath_node *)sta->drv_priv;
f89d1bc4
FF		 2107 else if (vif && ieee80211_is_data(hdr->frame_control)) {
2108 avp = (void *)vif->drv_priv;
2109 txctl->an = &avp->mcast_node;
2110 }
a9927ba3 2111
04caf863
FF		 2112 if (info->control.hw_key)
2113 frmlen += info->control.hw_key->icv_len;
2114
f078f209 2115 /*
e8324357
S		 2116 * As a temporary workaround, assign seq# here; this will likely need
2117 * to be cleaned up to work better with Beacon transmission and virtual
2118 * BSSes.
f078f209 2119 */
e8324357 2120 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
e8324357
S		 2121 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2122 sc->tx.seq_no += 0x10;
2123 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2124 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
f078f209 2125 }
f078f209 2126
59505c02
FF		 2127 if ((vif && vif->type != NL80211_IFTYPE_AP &&
2128 vif->type != NL80211_IFTYPE_AP_VLAN) ||
2129 !ieee80211_is_data(hdr->frame_control))
2130 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2131
42cecc34 2132 /* Add the padding after the header if this is not already done */
c60c9929 2133 padpos = ieee80211_hdrlen(hdr->frame_control);
42cecc34
JL		 2134 padsize = padpos & 3;
2135 if (padsize && skb->len > padpos) {
2136 if (skb_headroom(skb) < padsize)
2137 return -ENOMEM;
28d16708 2138
42cecc34
JL		 2139 skb_push(skb, padsize);
2140 memmove(skb->data, skb->data + padsize, padpos);
f078f209 2141 }
f078f209 2142
36323f81 2143 setup_frame_info(hw, sta, skb, frmlen);
59505c02
FF		 2144 return 0;
2145}
2146
2d42efc4 2147
59505c02
FF		 2148/* Upon failure caller should free skb */
2149int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2150 struct ath_tx_control *txctl)
2151{
2152 struct ieee80211_hdr *hdr;
2153 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2154 struct ieee80211_sta *sta = txctl->sta;
2155 struct ieee80211_vif *vif = info->control.vif;
2156 struct ath_softc *sc = hw->priv;
2157 struct ath_txq *txq = txctl->txq;
2158 struct ath_atx_tid *tid = NULL;
2159 struct ath_buf *bf;
59505c02
FF		 2160 int q;
2161 int ret;
2162
2163 ret = ath_tx_prepare(hw, skb, txctl);
2164 if (ret)
2165 return ret;
2166
2167 hdr = (struct ieee80211_hdr *) skb->data;
2d42efc4
FF		 2168 /*
2169 * At this point, the vif, hw_key and sta pointers in the tx control
2170 * info are no longer valid (overwritten by the ath_frame_info data.
2171 */
2172
28d16708 2173 q = skb_get_queue_mapping(skb);
23de5dc9
FF		 2174
2175 ath_txq_lock(sc, txq);
28d16708 2176 if (txq == sc->tx.txq_map[q] &&
7702e788
FF		 2177 ++txq->pending_frames > sc->tx.txq_max_pending[q] &&
2178 !txq->stopped) {
7545daf4 2179 ieee80211_stop_queue(sc->hw, q);
3db1cd5c 2180 txq->stopped = true;
f078f209 2181 }
f078f209 2182
f2c7a793
FF		 2183 if (info->flags & IEEE80211_TX_CTL_PS_RESPONSE) {
2184 ath_txq_unlock(sc, txq);
2185 txq = sc->tx.uapsdq;
2186 ath_txq_lock(sc, txq);
2800e82b
FF		 2187 } else if (txctl->an &&
2188 ieee80211_is_data_present(hdr->frame_control)) {
1803d02d 2189 tid = ath_get_skb_tid(sc, txctl->an, skb);
bdc21457
FF		 2190
2191 WARN_ON(tid->ac->txq != txctl->txq);
bdc21457 2192
2800e82b
FF		 2193 if (info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
2194 tid->ac->clear_ps_filter = true;
2195
bdc21457 2196 /*
2800e82b
FF		 2197 * Add this frame to software queue for scheduling later
2198 * for aggregation.
bdc21457 2199 */
2800e82b
FF		 2200 TX_STAT_INC(txq->axq_qnum, a_queued_sw);
2201 __skb_queue_tail(&tid->buf_q, skb);
2202 if (!txctl->an->sleeping)
2203 ath_tx_queue_tid(txq, tid);
2204
2205 ath_txq_schedule(sc, txq);
bdc21457
FF		 2206 goto out;
2207 }
2208
f2c7a793 2209 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
bdc21457 2210 if (!bf) {
a4943ccb 2211 ath_txq_skb_done(sc, txq, skb);
bdc21457
FF		 2212 if (txctl->paprd)
2213 dev_kfree_skb_any(skb);
2214 else
2215 ieee80211_free_txskb(sc->hw, skb);
2216 goto out;
2217 }
2218
2219 bf->bf_state.bfs_paprd = txctl->paprd;
2220
2221 if (txctl->paprd)
2222 bf->bf_state.bfs_paprd_timestamp = jiffies;
2223
79acac07 2224 ath_set_rates(vif, sta, bf);
f2c7a793 2225 ath_tx_send_normal(sc, txq, tid, skb);
3ad29529 2226
bdc21457 2227out:
23de5dc9 2228 ath_txq_unlock(sc, txq);
3ad29529 2229
44f1d26c 2230 return 0;
f078f209
LR		 2231}
2232
59505c02
FF		 2233void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2234 struct sk_buff *skb)
2235{
2236 struct ath_softc *sc = hw->priv;
2237 struct ath_tx_control txctl = {
2238 .txq = sc->beacon.cabq
2239 };
2240 struct ath_tx_info info = {};
2241 struct ieee80211_hdr *hdr;
2242 struct ath_buf *bf_tail = NULL;
2243 struct ath_buf *bf;
2244 LIST_HEAD(bf_q);
2245 int duration = 0;
2246 int max_duration;
2247
2248 max_duration =
2249 sc->cur_beacon_conf.beacon_interval * 1000 *
2250 sc->cur_beacon_conf.dtim_period / ATH_BCBUF;
2251
2252 do {
2253 struct ath_frame_info *fi = get_frame_info(skb);
2254
2255 if (ath_tx_prepare(hw, skb, &txctl))
2256 break;
2257
2258 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2259 if (!bf)
2260 break;
2261
2262 bf->bf_lastbf = bf;
2263 ath_set_rates(vif, NULL, bf);
a3835e9f 2264 ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
59505c02
FF		 2265 duration += info.rates[0].PktDuration;
2266 if (bf_tail)
2267 bf_tail->bf_next = bf;
2268
2269 list_add_tail(&bf->list, &bf_q);
2270 bf_tail = bf;
2271 skb = NULL;
2272
2273 if (duration > max_duration)
2274 break;
2275
2276 skb = ieee80211_get_buffered_bc(hw, vif);
2277 } while(skb);
2278
2279 if (skb)
2280 ieee80211_free_txskb(hw, skb);
2281
2282 if (list_empty(&bf_q))
2283 return;
2284
2285 bf = list_first_entry(&bf_q, struct ath_buf, list);
2286 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
2287
2288 if (hdr->frame_control & IEEE80211_FCTL_MOREDATA) {
2289 hdr->frame_control &= ~IEEE80211_FCTL_MOREDATA;
2290 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
2291 sizeof(*hdr), DMA_TO_DEVICE);
2292 }
2293
2294 ath_txq_lock(sc, txctl.txq);
2295 ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2296 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2297 TX_STAT_INC(txctl.txq->axq_qnum, queued);
2298 ath_txq_unlock(sc, txctl.txq);
2299}
2300
e8324357
S		 2301/*****************/
2302/* TX Completion */
2303/*****************/
528f0c6b 2304
e8324357 2305static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
0f9dc298 2306 int tx_flags, struct ath_txq *txq)
528f0c6b 2307{
e8324357 2308 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
c46917bb 2309 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
4d91f9f3 2310 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
a4943ccb 2311 int padpos, padsize;
07c15a3f 2312 unsigned long flags;
528f0c6b 2313
d2182b69 2314 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
528f0c6b 2315
51dea9be 2316 if (sc->sc_ah->caldata)
4b9b42bf 2317 set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags);
51dea9be 2318
55797b1a 2319 if (!(tx_flags & ATH_TX_ERROR))
e8324357
S		 2320 /* Frame was ACKed */
2321 tx_info->flags |= IEEE80211_TX_STAT_ACK;
528f0c6b 2322
c60c9929 2323 padpos = ieee80211_hdrlen(hdr->frame_control);
42cecc34
JL		 2324 padsize = padpos & 3;
2325 if (padsize && skb->len>padpos+padsize) {
2326 /*
2327 * Remove MAC header padding before giving the frame back to
2328 * mac80211.
2329 */
2330 memmove(skb->data + padsize, skb->data, padpos);
2331 skb_pull(skb, padsize);
e8324357 2332 }
528f0c6b 2333
07c15a3f 2334 spin_lock_irqsave(&sc->sc_pm_lock, flags);
c8e8868e 2335 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
1b04b930 2336 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
d2182b69 2337 ath_dbg(common, PS,
226afe68 2338 "Going back to sleep after having received TX status (0x%lx)\n",
1b04b930
S		 2339 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2340 PS_WAIT_FOR_CAB |
2341 PS_WAIT_FOR_PSPOLL_DATA |
2342 PS_WAIT_FOR_TX_ACK));
9a23f9ca 2343 }
07c15a3f 2344 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
9a23f9ca 2345
f2c7a793 2346 __skb_queue_tail(&txq->complete_q, skb);
a4943ccb 2347 ath_txq_skb_done(sc, txq, skb);
e8324357 2348}
f078f209 2349
e8324357 2350static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
db1a052b 2351 struct ath_txq *txq, struct list_head *bf_q,
156369fa 2352 struct ath_tx_status *ts, int txok)
f078f209 2353{
e8324357 2354 struct sk_buff *skb = bf->bf_mpdu;
3afd21e7 2355 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
e8324357 2356 unsigned long flags;
6b2c4032 2357 int tx_flags = 0;
f078f209 2358
55797b1a 2359 if (!txok)
6b2c4032 2360 tx_flags |= ATH_TX_ERROR;
f078f209 2361
3afd21e7
FF		 2362 if (ts->ts_status & ATH9K_TXERR_FILT)
2363 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2364
c1739eb3 2365 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
6cf9e995 2366 bf->bf_buf_addr = 0;
9f42c2b6
FF		 2367
2368 if (bf->bf_state.bfs_paprd) {
9cf04dcc
MSS		 2369 if (time_after(jiffies,
2370 bf->bf_state.bfs_paprd_timestamp +
2371 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
ca369eb4 2372 dev_kfree_skb_any(skb);
78a18172 2373 else
ca369eb4 2374 complete(&sc->paprd_complete);
9f42c2b6 2375 } else {
55797b1a 2376 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
0f9dc298 2377 ath_tx_complete(sc, skb, tx_flags, txq);
9f42c2b6 2378 }
6cf9e995
BG		 2379 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2380 * accidentally reference it later.
2381 */
2382 bf->bf_mpdu = NULL;
e8324357
S		 2383
2384 /*
2385 * Return the list of ath_buf of this mpdu to free queue
2386 */
2387 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2388 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2389 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
f078f209
LR		 2390}
2391
0cdd5c60
FF		 2392static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2393 struct ath_tx_status *ts, int nframes, int nbad,
3afd21e7 2394 int txok)
f078f209 2395{
a22be22a 2396 struct sk_buff *skb = bf->bf_mpdu;
254ad0ff 2397 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e8324357 2398 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
0cdd5c60 2399 struct ieee80211_hw *hw = sc->hw;
f0c255a0 2400 struct ath_hw *ah = sc->sc_ah;
8a92e2ee 2401 u8 i, tx_rateindex;
f078f209 2402
95e4acb7 2403 if (txok)
db1a052b 2404 tx_info->status.ack_signal = ts->ts_rssi;
95e4acb7 2405
db1a052b 2406 tx_rateindex = ts->ts_rateindex;
8a92e2ee
VT		 2407 WARN_ON(tx_rateindex >= hw->max_rates);
2408
3afd21e7 2409 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
d969847c 2410 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
f078f209 2411
b572d033 2412 BUG_ON(nbad > nframes);
ebd02287 2413 }
185d1589
RM		 2414 tx_info->status.ampdu_len = nframes;
2415 tx_info->status.ampdu_ack_len = nframes - nbad;
ebd02287 2416
db1a052b 2417 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
3afd21e7 2418 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
f0c255a0
FF		 2419 /*
2420 * If an underrun error is seen assume it as an excessive
2421 * retry only if max frame trigger level has been reached
2422 * (2 KB for single stream, and 4 KB for dual stream).
2423 * Adjust the long retry as if the frame was tried
2424 * hw->max_rate_tries times to affect how rate control updates
2425 * PER for the failed rate.
2426 * In case of congestion on the bus penalizing this type of
2427 * underruns should help hardware actually transmit new frames
2428 * successfully by eventually preferring slower rates.
2429 * This itself should also alleviate congestion on the bus.
2430 */
3afd21e7
FF		 2431 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2432 ATH9K_TX_DELIM_UNDERRUN)) &&
2433 ieee80211_is_data(hdr->frame_control) &&
83860c59 2434 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
f0c255a0
FF		 2435 tx_info->status.rates[tx_rateindex].count =
2436 hw->max_rate_tries;
f078f209 2437 }
8a92e2ee 2438
545750d3 2439 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
8a92e2ee 2440 tx_info->status.rates[i].count = 0;
545750d3
FF		 2441 tx_info->status.rates[i].idx = -1;
2442 }
8a92e2ee 2443
78c4653a 2444 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
f078f209
LR		 2445}
2446
e8324357 2447static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
f078f209 2448{
cbe61d8a 2449 struct ath_hw *ah = sc->sc_ah;
c46917bb 2450 struct ath_common *common = ath9k_hw_common(ah);
e8324357 2451 struct ath_buf *bf, *lastbf, *bf_held = NULL;
f078f209 2452 struct list_head bf_head;
e8324357 2453 struct ath_desc *ds;
29bffa96 2454 struct ath_tx_status ts;
e8324357 2455 int status;
f078f209 2456
d2182b69 2457 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
226afe68
JP		 2458 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2459 txq->axq_link);
f078f209 2460
23de5dc9 2461 ath_txq_lock(sc, txq);
f078f209 2462 for (;;) {
124b979b 2463 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
236de514
FF		 2464 break;
2465
f078f209
LR		 2466 if (list_empty(&txq->axq_q)) {
2467 txq->axq_link = NULL;
73364b0c 2468 ath_txq_schedule(sc, txq);
f078f209
LR		 2469 break;
2470 }
f078f209
LR		 2471 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2472
e8324357
S		 2473 /*
2474 * There is a race condition that a BH gets scheduled
2475 * after sw writes TxE and before hw re-load the last
2476 * descriptor to get the newly chained one.
2477 * Software must keep the last DONE descriptor as a
2478 * holding descriptor - software does so by marking
2479 * it with the STALE flag.
2480 */
2481 bf_held = NULL;
50676b81 2482 if (bf->bf_state.stale) {
e8324357 2483 bf_held = bf;
fce041be 2484 if (list_is_last(&bf_held->list, &txq->axq_q))
e8324357 2485 break;
fce041be
FF		 2486
2487 bf = list_entry(bf_held->list.next, struct ath_buf,
2488 list);
f078f209
LR		 2489 }
2490
2491 lastbf = bf->bf_lastbf;
e8324357 2492 ds = lastbf->bf_desc;
f078f209 2493
29bffa96
FF		 2494 memset(&ts, 0, sizeof(ts));
2495 status = ath9k_hw_txprocdesc(ah, ds, &ts);
fce041be 2496 if (status == -EINPROGRESS)
e8324357 2497 break;
fce041be 2498
2dac4fb9 2499 TX_STAT_INC(txq->axq_qnum, txprocdesc);
f078f209 2500
e8324357
S		 2501 /*
2502 * Remove ath_buf's of the same transmit unit from txq,
2503 * however leave the last descriptor back as the holding
2504 * descriptor for hw.
2505 */
50676b81 2506 lastbf->bf_state.stale = true;
e8324357 2507 INIT_LIST_HEAD(&bf_head);
e8324357
S		 2508 if (!list_is_singular(&lastbf->list))
2509 list_cut_position(&bf_head,
2510 &txq->axq_q, lastbf->list.prev);
f078f209 2511
fce041be 2512 if (bf_held) {
0a8cea84 2513 list_del(&bf_held->list);
0a8cea84 2514 ath_tx_return_buffer(sc, bf_held);
e8324357 2515 }
f078f209 2516
fce041be 2517 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
8469cdef 2518 }
23de5dc9 2519 ath_txq_unlock_complete(sc, txq);
8469cdef
S		 2520}
2521
e8324357 2522void ath_tx_tasklet(struct ath_softc *sc)
f078f209 2523{
239c795d
FF		 2524 struct ath_hw *ah = sc->sc_ah;
2525 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
e8324357 2526 int i;
f078f209 2527
e8324357
S		 2528 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2529 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2530 ath_tx_processq(sc, &sc->tx.txq[i]);
f078f209
LR		 2531 }
2532}
2533
e5003249
VT		 2534void ath_tx_edma_tasklet(struct ath_softc *sc)
2535{
fce041be 2536 struct ath_tx_status ts;
e5003249
VT		 2537 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2538 struct ath_hw *ah = sc->sc_ah;
2539 struct ath_txq *txq;
2540 struct ath_buf *bf, *lastbf;
2541 struct list_head bf_head;
99ba6a46 2542 struct list_head *fifo_list;
e5003249 2543 int status;
e5003249
VT		 2544
2545 for (;;) {
124b979b 2546 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
236de514
FF		 2547 break;
2548
fce041be 2549 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
e5003249
VT		 2550 if (status == -EINPROGRESS)
2551 break;
2552 if (status == -EIO) {
d2182b69 2553 ath_dbg(common, XMIT, "Error processing tx status\n");
e5003249
VT		 2554 break;
2555 }
2556
4e0ad259
FF		 2557 /* Process beacon completions separately */
2558 if (ts.qid == sc->beacon.beaconq) {
2559 sc->beacon.tx_processed = true;
2560 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
d074e8d5
SW		 2561
2562 ath9k_csa_is_finished(sc);
e5003249 2563 continue;
4e0ad259 2564 }
e5003249 2565
fce041be 2566 txq = &sc->tx.txq[ts.qid];
e5003249 2567
23de5dc9 2568 ath_txq_lock(sc, txq);
fce041be 2569
78ef731c
SM		 2570 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2571
99ba6a46
FF		 2572 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2573 if (list_empty(fifo_list)) {
23de5dc9 2574 ath_txq_unlock(sc, txq);
e5003249
VT		 2575 return;
2576 }
2577
99ba6a46 2578 bf = list_first_entry(fifo_list, struct ath_buf, list);
50676b81 2579 if (bf->bf_state.stale) {
99ba6a46
FF		 2580 list_del(&bf->list);
2581 ath_tx_return_buffer(sc, bf);
2582 bf = list_first_entry(fifo_list, struct ath_buf, list);
2583 }
2584
e5003249
VT		 2585 lastbf = bf->bf_lastbf;
2586
2587 INIT_LIST_HEAD(&bf_head);
99ba6a46
FF		 2588 if (list_is_last(&lastbf->list, fifo_list)) {
2589 list_splice_tail_init(fifo_list, &bf_head);
fce041be 2590 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
e5003249 2591
fce041be
FF		 2592 if (!list_empty(&txq->axq_q)) {
2593 struct list_head bf_q;
60f2d1d5 2594
fce041be
FF		 2595 INIT_LIST_HEAD(&bf_q);
2596 txq->axq_link = NULL;
2597 list_splice_tail_init(&txq->axq_q, &bf_q);
2598 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2599 }
99ba6a46 2600 } else {
50676b81 2601 lastbf->bf_state.stale = true;
99ba6a46
FF		 2602 if (bf != lastbf)
2603 list_cut_position(&bf_head, fifo_list,
2604 lastbf->list.prev);
fce041be 2605 }
86271e46 2606
fce041be 2607 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
23de5dc9 2608 ath_txq_unlock_complete(sc, txq);
e5003249
VT		 2609 }
2610}
2611
e8324357
S		 2612/*****************/
2613/* Init, Cleanup */
2614/*****************/
f078f209 2615
5088c2f1
VT		 2616static int ath_txstatus_setup(struct ath_softc *sc, int size)
2617{
2618 struct ath_descdma *dd = &sc->txsdma;
2619 u8 txs_len = sc->sc_ah->caps.txs_len;
2620
2621 dd->dd_desc_len = size * txs_len;
b81950b1
FF		 2622 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2623 &dd->dd_desc_paddr, GFP_KERNEL);
5088c2f1
VT		 2624 if (!dd->dd_desc)
2625 return -ENOMEM;
2626
2627 return 0;
2628}
2629
2630static int ath_tx_edma_init(struct ath_softc *sc)
2631{
2632 int err;
2633
2634 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2635 if (!err)
2636 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2637 sc->txsdma.dd_desc_paddr,
2638 ATH_TXSTATUS_RING_SIZE);
2639
2640 return err;
2641}
2642
e8324357 2643int ath_tx_init(struct ath_softc *sc, int nbufs)
f078f209 2644{
c46917bb 2645 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
e8324357 2646 int error = 0;
f078f209 2647
797fe5cb 2648 spin_lock_init(&sc->tx.txbuflock);
f078f209 2649
797fe5cb 2650 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
4adfcded 2651 "tx", nbufs, 1, 1);
797fe5cb 2652 if (error != 0) {
3800276a
JP		 2653 ath_err(common,
2654 "Failed to allocate tx descriptors: %d\n", error);
b81950b1 2655 return error;
797fe5cb 2656 }
f078f209 2657
797fe5cb 2658 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
5088c2f1 2659 "beacon", ATH_BCBUF, 1, 1);
797fe5cb 2660 if (error != 0) {
3800276a
JP		 2661 ath_err(common,
2662 "Failed to allocate beacon descriptors: %d\n", error);
b81950b1 2663 return error;
797fe5cb 2664 }
f078f209 2665
164ace38
SB		 2666 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2667
b81950b1 2668 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
5088c2f1 2669 error = ath_tx_edma_init(sc);
f078f209 2670
e8324357 2671 return error;
f078f209
LR		 2672}
2673
f078f209
LR		 2674void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2675{
c5170163
S		 2676 struct ath_atx_tid *tid;
2677 struct ath_atx_ac *ac;
2678 int tidno, acno;
f078f209 2679
8ee5afbc 2680 for (tidno = 0, tid = &an->tid[tidno];
de7b7604 2681 tidno < IEEE80211_NUM_TIDS;
c5170163
S		 2682 tidno++, tid++) {
2683 tid->an = an;
2684 tid->tidno = tidno;
2685 tid->seq_start = tid->seq_next = 0;
2686 tid->baw_size = WME_MAX_BA;
2687 tid->baw_head = tid->baw_tail = 0;
2688 tid->sched = false;
e8324357 2689 tid->paused = false;
08c96abd 2690 tid->active = false;
56dc6336 2691 __skb_queue_head_init(&tid->buf_q);
bb195ff6 2692 __skb_queue_head_init(&tid->retry_q);
c5170163 2693 acno = TID_TO_WME_AC(tidno);
8ee5afbc 2694 tid->ac = &an->ac[acno];
c5170163 2695 }
f078f209 2696
8ee5afbc 2697 for (acno = 0, ac = &an->ac[acno];
bea843c7 2698 acno < IEEE80211_NUM_ACS; acno++, ac++) {
c5170163 2699 ac->sched = false;
026d5b07 2700 ac->clear_ps_filter = true;
066dae93 2701 ac->txq = sc->tx.txq_map[acno];
c5170163 2702 INIT_LIST_HEAD(&ac->tid_q);
f078f209
LR		 2703 }
2704}
2705
b5aa9bf9 2706void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
f078f209 2707{
2b40994c
FF		 2708 struct ath_atx_ac *ac;
2709 struct ath_atx_tid *tid;
f078f209 2710 struct ath_txq *txq;
066dae93 2711 int tidno;
e8324357 2712
2b40994c 2713 for (tidno = 0, tid = &an->tid[tidno];
de7b7604 2714 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
f078f209 2715
2b40994c 2716 ac = tid->ac;
066dae93 2717 txq = ac->txq;
f078f209 2718
23de5dc9 2719 ath_txq_lock(sc, txq);
2b40994c
FF		 2720
2721 if (tid->sched) {
2722 list_del(&tid->list);
2723 tid->sched = false;
2724 }
2725
2726 if (ac->sched) {
2727 list_del(&ac->list);
2728 tid->ac->sched = false;
f078f209 2729 }
2b40994c
FF		 2730
2731 ath_tid_drain(sc, txq, tid);
08c96abd 2732 tid->active = false;
2b40994c 2733
23de5dc9 2734 ath_txq_unlock(sc, txq);
f078f209
LR		 2735 }
2736}
Linux kernel - Deliverables
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