Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
b7f080cf | 17 | #include <linux/dma-mapping.h> |
394cf0a1 | 18 | #include "ath9k.h" |
b622a720 | 19 | #include "ar9003_mac.h" |
f078f209 LR |
20 | |
21 | #define BITS_PER_BYTE 8 | |
22 | #define OFDM_PLCP_BITS 22 | |
f078f209 LR |
23 | #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) |
24 | #define L_STF 8 | |
25 | #define L_LTF 8 | |
26 | #define L_SIG 4 | |
27 | #define HT_SIG 8 | |
28 | #define HT_STF 4 | |
29 | #define HT_LTF(_ns) (4 * (_ns)) | |
30 | #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */ | |
31 | #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */ | |
aa5955c3 FF |
32 | #define TIME_SYMBOLS(t) ((t) >> 2) |
33 | #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18) | |
f078f209 LR |
34 | #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) |
35 | #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) | |
36 | ||
f078f209 | 37 | |
c6663876 | 38 | static u16 bits_per_symbol[][2] = { |
f078f209 LR |
39 | /* 20MHz 40MHz */ |
40 | { 26, 54 }, /* 0: BPSK */ | |
41 | { 52, 108 }, /* 1: QPSK 1/2 */ | |
42 | { 78, 162 }, /* 2: QPSK 3/4 */ | |
43 | { 104, 216 }, /* 3: 16-QAM 1/2 */ | |
44 | { 156, 324 }, /* 4: 16-QAM 3/4 */ | |
45 | { 208, 432 }, /* 5: 64-QAM 2/3 */ | |
46 | { 234, 486 }, /* 6: 64-QAM 3/4 */ | |
47 | { 260, 540 }, /* 7: 64-QAM 5/6 */ | |
f078f209 LR |
48 | }; |
49 | ||
82b873af | 50 | static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, |
44f1d26c FF |
51 | struct ath_atx_tid *tid, struct sk_buff *skb); |
52 | static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, | |
53 | int tx_flags, struct ath_txq *txq); | |
e8324357 | 54 | static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, |
db1a052b | 55 | struct ath_txq *txq, struct list_head *bf_q, |
156369fa | 56 | struct ath_tx_status *ts, int txok); |
102e0572 | 57 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, |
fce041be | 58 | struct list_head *head, bool internal); |
0cdd5c60 FF |
59 | static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, |
60 | struct ath_tx_status *ts, int nframes, int nbad, | |
3afd21e7 | 61 | int txok); |
90fa539c FF |
62 | static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
63 | int seqno); | |
44f1d26c FF |
64 | static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, |
65 | struct ath_txq *txq, | |
66 | struct ath_atx_tid *tid, | |
249ee722 | 67 | struct sk_buff *skb); |
c4288390 | 68 | |
545750d3 | 69 | enum { |
0e668cde FF |
70 | MCS_HT20, |
71 | MCS_HT20_SGI, | |
545750d3 FF |
72 | MCS_HT40, |
73 | MCS_HT40_SGI, | |
74 | }; | |
75 | ||
e8324357 S |
76 | /*********************/ |
77 | /* Aggregation logic */ | |
78 | /*********************/ | |
f078f209 | 79 | |
ef1b6cd9 | 80 | void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq) |
1512a486 | 81 | __acquires(&txq->axq_lock) |
23de5dc9 FF |
82 | { |
83 | spin_lock_bh(&txq->axq_lock); | |
84 | } | |
85 | ||
ef1b6cd9 | 86 | void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq) |
1512a486 | 87 | __releases(&txq->axq_lock) |
23de5dc9 FF |
88 | { |
89 | spin_unlock_bh(&txq->axq_lock); | |
90 | } | |
91 | ||
ef1b6cd9 | 92 | void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq) |
1512a486 | 93 | __releases(&txq->axq_lock) |
23de5dc9 FF |
94 | { |
95 | struct sk_buff_head q; | |
96 | struct sk_buff *skb; | |
97 | ||
98 | __skb_queue_head_init(&q); | |
99 | skb_queue_splice_init(&txq->complete_q, &q); | |
100 | spin_unlock_bh(&txq->axq_lock); | |
101 | ||
102 | while ((skb = __skb_dequeue(&q))) | |
103 | ieee80211_tx_status(sc->hw, skb); | |
104 | } | |
105 | ||
0453531e FF |
106 | static void ath_tx_queue_tid(struct ath_softc *sc, struct ath_txq *txq, |
107 | struct ath_atx_tid *tid) | |
ff37e337 | 108 | { |
e8324357 | 109 | struct ath_atx_ac *ac = tid->ac; |
0453531e FF |
110 | struct list_head *list; |
111 | struct ath_vif *avp = (struct ath_vif *) tid->an->vif->drv_priv; | |
112 | struct ath_chanctx *ctx = avp->chanctx; | |
113 | ||
114 | if (!ctx) | |
115 | return; | |
ff37e337 | 116 | |
e8324357 S |
117 | if (tid->sched) |
118 | return; | |
ff37e337 | 119 | |
e8324357 S |
120 | tid->sched = true; |
121 | list_add_tail(&tid->list, &ac->tid_q); | |
528f0c6b | 122 | |
e8324357 S |
123 | if (ac->sched) |
124 | return; | |
f078f209 | 125 | |
e8324357 | 126 | ac->sched = true; |
0453531e FF |
127 | |
128 | list = &ctx->acq[TID_TO_WME_AC(tid->tidno)]; | |
129 | list_add_tail(&ac->list, list); | |
e8324357 | 130 | } |
f078f209 | 131 | |
2d42efc4 | 132 | static struct ath_frame_info *get_frame_info(struct sk_buff *skb) |
76e45221 FF |
133 | { |
134 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
2d42efc4 FF |
135 | BUILD_BUG_ON(sizeof(struct ath_frame_info) > |
136 | sizeof(tx_info->rate_driver_data)); | |
137 | return (struct ath_frame_info *) &tx_info->rate_driver_data[0]; | |
76e45221 FF |
138 | } |
139 | ||
156369fa FF |
140 | static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno) |
141 | { | |
f89d1bc4 FF |
142 | if (!tid->an->sta) |
143 | return; | |
144 | ||
156369fa FF |
145 | ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno, |
146 | seqno << IEEE80211_SEQ_SEQ_SHIFT); | |
147 | } | |
148 | ||
79acac07 FF |
149 | static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta, |
150 | struct ath_buf *bf) | |
151 | { | |
152 | ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates, | |
153 | ARRAY_SIZE(bf->rates)); | |
154 | } | |
155 | ||
a4943ccb FF |
156 | static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq, |
157 | struct sk_buff *skb) | |
158 | { | |
3ad9c386 | 159 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
d954cd77 | 160 | struct ath_frame_info *fi = get_frame_info(skb); |
d954cd77 | 161 | int q = fi->txq; |
a4943ccb | 162 | |
d954cd77 | 163 | if (q < 0) |
a4943ccb FF |
164 | return; |
165 | ||
d954cd77 | 166 | txq = sc->tx.txq_map[q]; |
a4943ccb FF |
167 | if (WARN_ON(--txq->pending_frames < 0)) |
168 | txq->pending_frames = 0; | |
169 | ||
170 | if (txq->stopped && | |
171 | txq->pending_frames < sc->tx.txq_max_pending[q]) { | |
868caae3 SM |
172 | if (ath9k_is_chanctx_enabled()) |
173 | ieee80211_wake_queue(sc->hw, info->hw_queue); | |
174 | else | |
175 | ieee80211_wake_queue(sc->hw, q); | |
a4943ccb FF |
176 | txq->stopped = false; |
177 | } | |
178 | } | |
179 | ||
1803d02d FF |
180 | static struct ath_atx_tid * |
181 | ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb) | |
182 | { | |
39731b78 | 183 | u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK; |
1803d02d FF |
184 | return ATH_AN_2_TID(an, tidno); |
185 | } | |
186 | ||
a7586ee4 FF |
187 | static bool ath_tid_has_buffered(struct ath_atx_tid *tid) |
188 | { | |
bb195ff6 | 189 | return !skb_queue_empty(&tid->buf_q) || !skb_queue_empty(&tid->retry_q); |
a7586ee4 FF |
190 | } |
191 | ||
192 | static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid) | |
193 | { | |
bb195ff6 FF |
194 | struct sk_buff *skb; |
195 | ||
196 | skb = __skb_dequeue(&tid->retry_q); | |
197 | if (!skb) | |
198 | skb = __skb_dequeue(&tid->buf_q); | |
199 | ||
200 | return skb; | |
a7586ee4 FF |
201 | } |
202 | ||
2800e82b FF |
203 | /* |
204 | * ath_tx_tid_change_state: | |
205 | * - clears a-mpdu flag of previous session | |
206 | * - force sequence number allocation to fix next BlockAck Window | |
207 | */ | |
208 | static void | |
209 | ath_tx_tid_change_state(struct ath_softc *sc, struct ath_atx_tid *tid) | |
210 | { | |
211 | struct ath_txq *txq = tid->ac->txq; | |
212 | struct ieee80211_tx_info *tx_info; | |
213 | struct sk_buff *skb, *tskb; | |
214 | struct ath_buf *bf; | |
215 | struct ath_frame_info *fi; | |
216 | ||
217 | skb_queue_walk_safe(&tid->buf_q, skb, tskb) { | |
218 | fi = get_frame_info(skb); | |
219 | bf = fi->bf; | |
220 | ||
221 | tx_info = IEEE80211_SKB_CB(skb); | |
222 | tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU; | |
223 | ||
224 | if (bf) | |
225 | continue; | |
226 | ||
227 | bf = ath_tx_setup_buffer(sc, txq, tid, skb); | |
228 | if (!bf) { | |
229 | __skb_unlink(skb, &tid->buf_q); | |
230 | ath_txq_skb_done(sc, txq, skb); | |
231 | ieee80211_free_txskb(sc->hw, skb); | |
232 | continue; | |
233 | } | |
234 | } | |
235 | ||
236 | } | |
237 | ||
08c96abd | 238 | static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
528f0c6b | 239 | { |
066dae93 | 240 | struct ath_txq *txq = tid->ac->txq; |
56dc6336 | 241 | struct sk_buff *skb; |
e8324357 S |
242 | struct ath_buf *bf; |
243 | struct list_head bf_head; | |
90fa539c | 244 | struct ath_tx_status ts; |
2d42efc4 | 245 | struct ath_frame_info *fi; |
156369fa | 246 | bool sendbar = false; |
f078f209 | 247 | |
90fa539c | 248 | INIT_LIST_HEAD(&bf_head); |
e6a9854b | 249 | |
90fa539c | 250 | memset(&ts, 0, sizeof(ts)); |
f078f209 | 251 | |
2800e82b | 252 | while ((skb = __skb_dequeue(&tid->retry_q))) { |
56dc6336 FF |
253 | fi = get_frame_info(skb); |
254 | bf = fi->bf; | |
249ee722 | 255 | if (!bf) { |
2800e82b FF |
256 | ath_txq_skb_done(sc, txq, skb); |
257 | ieee80211_free_txskb(sc->hw, skb); | |
258 | continue; | |
249ee722 FF |
259 | } |
260 | ||
8fed1408 | 261 | if (fi->baw_tracked) { |
6a0ddaef | 262 | ath_tx_update_baw(sc, tid, bf->bf_state.seqno); |
156369fa | 263 | sendbar = true; |
90fa539c | 264 | } |
2800e82b FF |
265 | |
266 | list_add_tail(&bf->list, &bf_head); | |
267 | ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0); | |
528f0c6b | 268 | } |
f078f209 | 269 | |
08c96abd | 270 | if (sendbar) { |
23de5dc9 | 271 | ath_txq_unlock(sc, txq); |
156369fa | 272 | ath_send_bar(tid, tid->seq_start); |
23de5dc9 FF |
273 | ath_txq_lock(sc, txq); |
274 | } | |
528f0c6b | 275 | } |
f078f209 | 276 | |
e8324357 S |
277 | static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
278 | int seqno) | |
528f0c6b | 279 | { |
e8324357 | 280 | int index, cindex; |
f078f209 | 281 | |
e8324357 S |
282 | index = ATH_BA_INDEX(tid->seq_start, seqno); |
283 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | |
f078f209 | 284 | |
81ee13ba | 285 | __clear_bit(cindex, tid->tx_buf); |
528f0c6b | 286 | |
81ee13ba | 287 | while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) { |
e8324357 S |
288 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); |
289 | INCR(tid->baw_head, ATH_TID_MAX_BUFS); | |
f9437543 FF |
290 | if (tid->bar_index >= 0) |
291 | tid->bar_index--; | |
e8324357 | 292 | } |
528f0c6b | 293 | } |
f078f209 | 294 | |
e8324357 | 295 | static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
8fed1408 | 296 | struct ath_buf *bf) |
528f0c6b | 297 | { |
8fed1408 FF |
298 | struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); |
299 | u16 seqno = bf->bf_state.seqno; | |
e8324357 | 300 | int index, cindex; |
528f0c6b | 301 | |
2d3bcba0 | 302 | index = ATH_BA_INDEX(tid->seq_start, seqno); |
e8324357 | 303 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); |
81ee13ba | 304 | __set_bit(cindex, tid->tx_buf); |
8fed1408 | 305 | fi->baw_tracked = 1; |
f078f209 | 306 | |
e8324357 S |
307 | if (index >= ((tid->baw_tail - tid->baw_head) & |
308 | (ATH_TID_MAX_BUFS - 1))) { | |
309 | tid->baw_tail = cindex; | |
310 | INCR(tid->baw_tail, ATH_TID_MAX_BUFS); | |
f078f209 | 311 | } |
f078f209 LR |
312 | } |
313 | ||
e8324357 S |
314 | static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq, |
315 | struct ath_atx_tid *tid) | |
f078f209 | 316 | |
f078f209 | 317 | { |
56dc6336 | 318 | struct sk_buff *skb; |
e8324357 S |
319 | struct ath_buf *bf; |
320 | struct list_head bf_head; | |
db1a052b | 321 | struct ath_tx_status ts; |
2d42efc4 | 322 | struct ath_frame_info *fi; |
db1a052b FF |
323 | |
324 | memset(&ts, 0, sizeof(ts)); | |
e8324357 | 325 | INIT_LIST_HEAD(&bf_head); |
f078f209 | 326 | |
a7586ee4 | 327 | while ((skb = ath_tid_dequeue(tid))) { |
56dc6336 FF |
328 | fi = get_frame_info(skb); |
329 | bf = fi->bf; | |
f078f209 | 330 | |
44f1d26c | 331 | if (!bf) { |
44f1d26c | 332 | ath_tx_complete(sc, skb, ATH_TX_ERROR, txq); |
44f1d26c FF |
333 | continue; |
334 | } | |
335 | ||
56dc6336 | 336 | list_add_tail(&bf->list, &bf_head); |
156369fa | 337 | ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0); |
e8324357 | 338 | } |
f078f209 LR |
339 | } |
340 | ||
fec247c0 | 341 | static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq, |
da647626 | 342 | struct sk_buff *skb, int count) |
f078f209 | 343 | { |
8b7f8532 | 344 | struct ath_frame_info *fi = get_frame_info(skb); |
f11cc949 | 345 | struct ath_buf *bf = fi->bf; |
e8324357 | 346 | struct ieee80211_hdr *hdr; |
da647626 | 347 | int prev = fi->retries; |
f078f209 | 348 | |
fec247c0 | 349 | TX_STAT_INC(txq->axq_qnum, a_retries); |
da647626 FF |
350 | fi->retries += count; |
351 | ||
352 | if (prev > 0) | |
2d42efc4 | 353 | return; |
f078f209 | 354 | |
e8324357 S |
355 | hdr = (struct ieee80211_hdr *)skb->data; |
356 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); | |
f11cc949 FF |
357 | dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, |
358 | sizeof(*hdr), DMA_TO_DEVICE); | |
f078f209 LR |
359 | } |
360 | ||
0a8cea84 | 361 | static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc) |
d43f3015 | 362 | { |
0a8cea84 | 363 | struct ath_buf *bf = NULL; |
d43f3015 S |
364 | |
365 | spin_lock_bh(&sc->tx.txbuflock); | |
0a8cea84 FF |
366 | |
367 | if (unlikely(list_empty(&sc->tx.txbuf))) { | |
8a46097a VT |
368 | spin_unlock_bh(&sc->tx.txbuflock); |
369 | return NULL; | |
370 | } | |
0a8cea84 FF |
371 | |
372 | bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); | |
373 | list_del(&bf->list); | |
374 | ||
d43f3015 S |
375 | spin_unlock_bh(&sc->tx.txbuflock); |
376 | ||
0a8cea84 FF |
377 | return bf; |
378 | } | |
379 | ||
380 | static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf) | |
381 | { | |
382 | spin_lock_bh(&sc->tx.txbuflock); | |
383 | list_add_tail(&bf->list, &sc->tx.txbuf); | |
384 | spin_unlock_bh(&sc->tx.txbuflock); | |
385 | } | |
386 | ||
387 | static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf) | |
388 | { | |
389 | struct ath_buf *tbf; | |
390 | ||
391 | tbf = ath_tx_get_buffer(sc); | |
392 | if (WARN_ON(!tbf)) | |
393 | return NULL; | |
394 | ||
d43f3015 S |
395 | ATH_TXBUF_RESET(tbf); |
396 | ||
397 | tbf->bf_mpdu = bf->bf_mpdu; | |
398 | tbf->bf_buf_addr = bf->bf_buf_addr; | |
d826c832 | 399 | memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len); |
d43f3015 | 400 | tbf->bf_state = bf->bf_state; |
86c7d8d4 | 401 | tbf->bf_state.stale = false; |
d43f3015 S |
402 | |
403 | return tbf; | |
404 | } | |
405 | ||
b572d033 FF |
406 | static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf, |
407 | struct ath_tx_status *ts, int txok, | |
408 | int *nframes, int *nbad) | |
409 | { | |
2d42efc4 | 410 | struct ath_frame_info *fi; |
b572d033 FF |
411 | u16 seq_st = 0; |
412 | u32 ba[WME_BA_BMP_SIZE >> 5]; | |
413 | int ba_index; | |
414 | int isaggr = 0; | |
415 | ||
416 | *nbad = 0; | |
417 | *nframes = 0; | |
418 | ||
b572d033 FF |
419 | isaggr = bf_isaggr(bf); |
420 | if (isaggr) { | |
421 | seq_st = ts->ts_seqnum; | |
422 | memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); | |
423 | } | |
424 | ||
425 | while (bf) { | |
2d42efc4 | 426 | fi = get_frame_info(bf->bf_mpdu); |
6a0ddaef | 427 | ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno); |
b572d033 FF |
428 | |
429 | (*nframes)++; | |
430 | if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index))) | |
431 | (*nbad)++; | |
432 | ||
433 | bf = bf->bf_next; | |
434 | } | |
435 | } | |
436 | ||
437 | ||
d43f3015 S |
438 | static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, |
439 | struct ath_buf *bf, struct list_head *bf_q, | |
1381559b | 440 | struct ath_tx_status *ts, int txok) |
f078f209 | 441 | { |
e8324357 S |
442 | struct ath_node *an = NULL; |
443 | struct sk_buff *skb; | |
1286ec6d | 444 | struct ieee80211_sta *sta; |
0cdd5c60 | 445 | struct ieee80211_hw *hw = sc->hw; |
1286ec6d | 446 | struct ieee80211_hdr *hdr; |
76d5a9e8 | 447 | struct ieee80211_tx_info *tx_info; |
e8324357 | 448 | struct ath_atx_tid *tid = NULL; |
d43f3015 | 449 | struct ath_buf *bf_next, *bf_last = bf->bf_lastbf; |
56dc6336 FF |
450 | struct list_head bf_head; |
451 | struct sk_buff_head bf_pending; | |
156369fa | 452 | u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first; |
f078f209 | 453 | u32 ba[WME_BA_BMP_SIZE >> 5]; |
0934af23 | 454 | int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0; |
6fe7cc71 | 455 | bool rc_update = true, isba; |
78c4653a | 456 | struct ieee80211_tx_rate rates[4]; |
2d42efc4 | 457 | struct ath_frame_info *fi; |
ebd02287 | 458 | int nframes; |
daa5c408 | 459 | bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH); |
da647626 | 460 | int i, retries; |
156369fa | 461 | int bar_index = -1; |
f078f209 | 462 | |
a22be22a | 463 | skb = bf->bf_mpdu; |
1286ec6d S |
464 | hdr = (struct ieee80211_hdr *)skb->data; |
465 | ||
76d5a9e8 | 466 | tx_info = IEEE80211_SKB_CB(skb); |
76d5a9e8 | 467 | |
79acac07 | 468 | memcpy(rates, bf->rates, sizeof(rates)); |
78c4653a | 469 | |
da647626 FF |
470 | retries = ts->ts_longretry + 1; |
471 | for (i = 0; i < ts->ts_rateindex; i++) | |
472 | retries += rates[i].count; | |
473 | ||
1286ec6d | 474 | rcu_read_lock(); |
f078f209 | 475 | |
686b9cb9 | 476 | sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2); |
1286ec6d S |
477 | if (!sta) { |
478 | rcu_read_unlock(); | |
73e19463 | 479 | |
31e79a59 FF |
480 | INIT_LIST_HEAD(&bf_head); |
481 | while (bf) { | |
482 | bf_next = bf->bf_next; | |
483 | ||
50676b81 | 484 | if (!bf->bf_state.stale || bf_next != NULL) |
31e79a59 FF |
485 | list_move_tail(&bf->list, &bf_head); |
486 | ||
156369fa | 487 | ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0); |
31e79a59 FF |
488 | |
489 | bf = bf_next; | |
490 | } | |
1286ec6d | 491 | return; |
f078f209 LR |
492 | } |
493 | ||
1286ec6d | 494 | an = (struct ath_node *)sta->drv_priv; |
1803d02d | 495 | tid = ath_get_skb_tid(sc, an, skb); |
156369fa | 496 | seq_first = tid->seq_start; |
6fe7cc71 | 497 | isba = ts->ts_flags & ATH9K_TX_BA; |
1286ec6d | 498 | |
b11b160d FF |
499 | /* |
500 | * The hardware occasionally sends a tx status for the wrong TID. | |
501 | * In this case, the BA status cannot be considered valid and all | |
502 | * subframes need to be retransmitted | |
6fe7cc71 SE |
503 | * |
504 | * Only BlockAcks have a TID and therefore normal Acks cannot be | |
505 | * checked | |
b11b160d | 506 | */ |
1803d02d | 507 | if (isba && tid->tidno != ts->tid) |
b11b160d FF |
508 | txok = false; |
509 | ||
e8324357 | 510 | isaggr = bf_isaggr(bf); |
d43f3015 | 511 | memset(ba, 0, WME_BA_BMP_SIZE >> 3); |
f078f209 | 512 | |
d43f3015 | 513 | if (isaggr && txok) { |
db1a052b FF |
514 | if (ts->ts_flags & ATH9K_TX_BA) { |
515 | seq_st = ts->ts_seqnum; | |
516 | memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); | |
e8324357 | 517 | } else { |
d43f3015 S |
518 | /* |
519 | * AR5416 can become deaf/mute when BA | |
520 | * issue happens. Chip needs to be reset. | |
521 | * But AP code may have sychronization issues | |
522 | * when perform internal reset in this routine. | |
523 | * Only enable reset in STA mode for now. | |
524 | */ | |
2660b81a | 525 | if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) |
d43f3015 | 526 | needreset = 1; |
e8324357 | 527 | } |
f078f209 LR |
528 | } |
529 | ||
56dc6336 | 530 | __skb_queue_head_init(&bf_pending); |
f078f209 | 531 | |
b572d033 | 532 | ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad); |
e8324357 | 533 | while (bf) { |
6a0ddaef FF |
534 | u16 seqno = bf->bf_state.seqno; |
535 | ||
f0b8220c | 536 | txfail = txpending = sendbar = 0; |
e8324357 | 537 | bf_next = bf->bf_next; |
f078f209 | 538 | |
78c4653a FF |
539 | skb = bf->bf_mpdu; |
540 | tx_info = IEEE80211_SKB_CB(skb); | |
2d42efc4 | 541 | fi = get_frame_info(skb); |
78c4653a | 542 | |
897d7fd9 FF |
543 | if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) || |
544 | !tid->active) { | |
08c96abd FF |
545 | /* |
546 | * Outside of the current BlockAck window, | |
547 | * maybe part of a previous session | |
548 | */ | |
549 | txfail = 1; | |
550 | } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) { | |
e8324357 S |
551 | /* transmit completion, subframe is |
552 | * acked by block ack */ | |
0934af23 | 553 | acked_cnt++; |
e8324357 S |
554 | } else if (!isaggr && txok) { |
555 | /* transmit completion */ | |
0934af23 | 556 | acked_cnt++; |
b0477013 FF |
557 | } else if (flush) { |
558 | txpending = 1; | |
559 | } else if (fi->retries < ATH_MAX_SW_RETRIES) { | |
560 | if (txok || !an->sleeping) | |
561 | ath_tx_set_retry(sc, txq, bf->bf_mpdu, | |
562 | retries); | |
563 | ||
564 | txpending = 1; | |
e8324357 | 565 | } else { |
b0477013 FF |
566 | txfail = 1; |
567 | txfail_cnt++; | |
568 | bar_index = max_t(int, bar_index, | |
569 | ATH_BA_INDEX(seq_first, seqno)); | |
e8324357 | 570 | } |
f078f209 | 571 | |
fce041be FF |
572 | /* |
573 | * Make sure the last desc is reclaimed if it | |
574 | * not a holding desc. | |
575 | */ | |
56dc6336 | 576 | INIT_LIST_HEAD(&bf_head); |
50676b81 | 577 | if (bf_next != NULL || !bf_last->bf_state.stale) |
d43f3015 | 578 | list_move_tail(&bf->list, &bf_head); |
f078f209 | 579 | |
08c96abd | 580 | if (!txpending) { |
e8324357 S |
581 | /* |
582 | * complete the acked-ones/xretried ones; update | |
583 | * block-ack window | |
584 | */ | |
6a0ddaef | 585 | ath_tx_update_baw(sc, tid, seqno); |
f078f209 | 586 | |
8a92e2ee | 587 | if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) { |
78c4653a | 588 | memcpy(tx_info->control.rates, rates, sizeof(rates)); |
3afd21e7 | 589 | ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok); |
8a92e2ee | 590 | rc_update = false; |
982e0395 LB |
591 | if (bf == bf->bf_lastbf) |
592 | ath_dynack_sample_tx_ts(sc->sc_ah, | |
593 | bf->bf_mpdu, | |
594 | ts); | |
8a92e2ee VT |
595 | } |
596 | ||
db1a052b | 597 | ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, |
156369fa | 598 | !txfail); |
e8324357 | 599 | } else { |
86a22acf FF |
600 | if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) { |
601 | tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP; | |
602 | ieee80211_sta_eosp(sta); | |
603 | } | |
d43f3015 | 604 | /* retry the un-acked ones */ |
50676b81 | 605 | if (bf->bf_next == NULL && bf_last->bf_state.stale) { |
b0477013 FF |
606 | struct ath_buf *tbf; |
607 | ||
608 | tbf = ath_clone_txbuf(sc, bf_last); | |
609 | /* | |
610 | * Update tx baw and complete the | |
611 | * frame with failed status if we | |
612 | * run out of tx buf. | |
613 | */ | |
614 | if (!tbf) { | |
b0477013 | 615 | ath_tx_update_baw(sc, tid, seqno); |
b0477013 FF |
616 | |
617 | ath_tx_complete_buf(sc, bf, txq, | |
618 | &bf_head, ts, 0); | |
619 | bar_index = max_t(int, bar_index, | |
620 | ATH_BA_INDEX(seq_first, seqno)); | |
621 | break; | |
c41d92dc | 622 | } |
b0477013 FF |
623 | |
624 | fi->bf = tbf; | |
e8324357 S |
625 | } |
626 | ||
627 | /* | |
628 | * Put this buffer to the temporary pending | |
629 | * queue to retain ordering | |
630 | */ | |
56dc6336 | 631 | __skb_queue_tail(&bf_pending, skb); |
e8324357 S |
632 | } |
633 | ||
634 | bf = bf_next; | |
f078f209 | 635 | } |
f078f209 | 636 | |
4cee7861 | 637 | /* prepend un-acked frames to the beginning of the pending frame queue */ |
56dc6336 | 638 | if (!skb_queue_empty(&bf_pending)) { |
5519541d | 639 | if (an->sleeping) |
042ec453 | 640 | ieee80211_sta_set_buffered(sta, tid->tidno, true); |
5519541d | 641 | |
bb195ff6 | 642 | skb_queue_splice_tail(&bf_pending, &tid->retry_q); |
26a64259 | 643 | if (!an->sleeping) { |
0453531e | 644 | ath_tx_queue_tid(sc, txq, tid); |
26a64259 | 645 | |
adfbda62 | 646 | if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY)) |
26a64259 FF |
647 | tid->ac->clear_ps_filter = true; |
648 | } | |
4cee7861 FF |
649 | } |
650 | ||
23de5dc9 FF |
651 | if (bar_index >= 0) { |
652 | u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index); | |
653 | ||
654 | if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq)) | |
655 | tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq); | |
656 | ||
657 | ath_txq_unlock(sc, txq); | |
658 | ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1)); | |
659 | ath_txq_lock(sc, txq); | |
660 | } | |
661 | ||
1286ec6d S |
662 | rcu_read_unlock(); |
663 | ||
124b979b RM |
664 | if (needreset) |
665 | ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR); | |
e8324357 | 666 | } |
f078f209 | 667 | |
81b51950 FF |
668 | static bool bf_is_ampdu_not_probing(struct ath_buf *bf) |
669 | { | |
670 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu); | |
671 | return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE); | |
672 | } | |
673 | ||
674 | static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq, | |
675 | struct ath_tx_status *ts, struct ath_buf *bf, | |
676 | struct list_head *bf_head) | |
677 | { | |
0c585dda | 678 | struct ieee80211_tx_info *info; |
81b51950 FF |
679 | bool txok, flush; |
680 | ||
681 | txok = !(ts->ts_status & ATH9K_TXERR_MASK); | |
682 | flush = !!(ts->ts_status & ATH9K_TX_FLUSH); | |
683 | txq->axq_tx_inprogress = false; | |
684 | ||
685 | txq->axq_depth--; | |
686 | if (bf_is_ampdu_not_probing(bf)) | |
687 | txq->axq_ampdu_depth--; | |
688 | ||
315dd114 FF |
689 | ts->duration = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc, |
690 | ts->ts_rateindex); | |
81b51950 | 691 | if (!bf_isampdu(bf)) { |
0c585dda FF |
692 | if (!flush) { |
693 | info = IEEE80211_SKB_CB(bf->bf_mpdu); | |
694 | memcpy(info->control.rates, bf->rates, | |
695 | sizeof(info->control.rates)); | |
81b51950 | 696 | ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok); |
982e0395 | 697 | ath_dynack_sample_tx_ts(sc->sc_ah, bf->bf_mpdu, ts); |
0c585dda | 698 | } |
81b51950 FF |
699 | ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok); |
700 | } else | |
701 | ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok); | |
702 | ||
73364b0c | 703 | if (!flush) |
81b51950 FF |
704 | ath_txq_schedule(sc, txq); |
705 | } | |
706 | ||
1a6e9d0f RM |
707 | static bool ath_lookup_legacy(struct ath_buf *bf) |
708 | { | |
709 | struct sk_buff *skb; | |
710 | struct ieee80211_tx_info *tx_info; | |
711 | struct ieee80211_tx_rate *rates; | |
712 | int i; | |
713 | ||
714 | skb = bf->bf_mpdu; | |
715 | tx_info = IEEE80211_SKB_CB(skb); | |
716 | rates = tx_info->control.rates; | |
717 | ||
059ee09b FF |
718 | for (i = 0; i < 4; i++) { |
719 | if (!rates[i].count || rates[i].idx < 0) | |
720 | break; | |
721 | ||
1a6e9d0f RM |
722 | if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) |
723 | return true; | |
724 | } | |
725 | ||
726 | return false; | |
727 | } | |
728 | ||
e8324357 S |
729 | static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf, |
730 | struct ath_atx_tid *tid) | |
f078f209 | 731 | { |
528f0c6b S |
732 | struct sk_buff *skb; |
733 | struct ieee80211_tx_info *tx_info; | |
a8efee4f | 734 | struct ieee80211_tx_rate *rates; |
d43f3015 | 735 | u32 max_4ms_framelen, frmlen; |
c0ac53fa | 736 | u16 aggr_limit, bt_aggr_limit, legacy = 0; |
aa5955c3 | 737 | int q = tid->ac->txq->mac80211_qnum; |
e8324357 | 738 | int i; |
528f0c6b | 739 | |
a22be22a | 740 | skb = bf->bf_mpdu; |
528f0c6b | 741 | tx_info = IEEE80211_SKB_CB(skb); |
0c585dda | 742 | rates = bf->rates; |
528f0c6b | 743 | |
e8324357 S |
744 | /* |
745 | * Find the lowest frame length among the rate series that will have a | |
aa5955c3 | 746 | * 4ms (or TXOP limited) transmit duration. |
e8324357 S |
747 | */ |
748 | max_4ms_framelen = ATH_AMPDU_LIMIT_MAX; | |
e63835b0 | 749 | |
e8324357 | 750 | for (i = 0; i < 4; i++) { |
b0477013 | 751 | int modeidx; |
e8324357 | 752 | |
b0477013 FF |
753 | if (!rates[i].count) |
754 | continue; | |
545750d3 | 755 | |
b0477013 FF |
756 | if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) { |
757 | legacy = 1; | |
758 | break; | |
f078f209 | 759 | } |
b0477013 FF |
760 | |
761 | if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) | |
762 | modeidx = MCS_HT40; | |
763 | else | |
764 | modeidx = MCS_HT20; | |
765 | ||
766 | if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) | |
767 | modeidx++; | |
768 | ||
aa5955c3 | 769 | frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx]; |
b0477013 | 770 | max_4ms_framelen = min(max_4ms_framelen, frmlen); |
f078f209 | 771 | } |
e63835b0 | 772 | |
f078f209 | 773 | /* |
e8324357 S |
774 | * limit aggregate size by the minimum rate if rate selected is |
775 | * not a probe rate, if rate selected is a probe rate then | |
776 | * avoid aggregation of this packet. | |
f078f209 | 777 | */ |
e8324357 S |
778 | if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy) |
779 | return 0; | |
f078f209 | 780 | |
c0ac53fa SM |
781 | aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX); |
782 | ||
783 | /* | |
784 | * Override the default aggregation limit for BTCOEX. | |
785 | */ | |
786 | bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen); | |
787 | if (bt_aggr_limit) | |
788 | aggr_limit = bt_aggr_limit; | |
f078f209 | 789 | |
4ef70841 S |
790 | if (tid->an->maxampdu) |
791 | aggr_limit = min(aggr_limit, tid->an->maxampdu); | |
f078f209 | 792 | |
e8324357 S |
793 | return aggr_limit; |
794 | } | |
f078f209 | 795 | |
e8324357 | 796 | /* |
d43f3015 | 797 | * Returns the number of delimiters to be added to |
e8324357 | 798 | * meet the minimum required mpdudensity. |
e8324357 S |
799 | */ |
800 | static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid, | |
7a12dfdb RM |
801 | struct ath_buf *bf, u16 frmlen, |
802 | bool first_subfrm) | |
e8324357 | 803 | { |
7a12dfdb | 804 | #define FIRST_DESC_NDELIMS 60 |
4ef70841 | 805 | u32 nsymbits, nsymbols; |
e8324357 | 806 | u16 minlen; |
545750d3 | 807 | u8 flags, rix; |
c6663876 | 808 | int width, streams, half_gi, ndelim, mindelim; |
2d42efc4 | 809 | struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); |
e8324357 S |
810 | |
811 | /* Select standard number of delimiters based on frame length alone */ | |
812 | ndelim = ATH_AGGR_GET_NDELIM(frmlen); | |
f078f209 LR |
813 | |
814 | /* | |
e8324357 S |
815 | * If encryption enabled, hardware requires some more padding between |
816 | * subframes. | |
817 | * TODO - this could be improved to be dependent on the rate. | |
818 | * The hardware can keep up at lower rates, but not higher rates | |
f078f209 | 819 | */ |
4f6760b0 RM |
820 | if ((fi->keyix != ATH9K_TXKEYIX_INVALID) && |
821 | !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) | |
e8324357 | 822 | ndelim += ATH_AGGR_ENCRYPTDELIM; |
f078f209 | 823 | |
7a12dfdb RM |
824 | /* |
825 | * Add delimiter when using RTS/CTS with aggregation | |
826 | * and non enterprise AR9003 card | |
827 | */ | |
3459731a FF |
828 | if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) && |
829 | (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE)) | |
7a12dfdb RM |
830 | ndelim = max(ndelim, FIRST_DESC_NDELIMS); |
831 | ||
e8324357 S |
832 | /* |
833 | * Convert desired mpdu density from microeconds to bytes based | |
834 | * on highest rate in rate series (i.e. first rate) to determine | |
835 | * required minimum length for subframe. Take into account | |
836 | * whether high rate is 20 or 40Mhz and half or full GI. | |
4ef70841 | 837 | * |
e8324357 S |
838 | * If there is no mpdu density restriction, no further calculation |
839 | * is needed. | |
840 | */ | |
4ef70841 S |
841 | |
842 | if (tid->an->mpdudensity == 0) | |
e8324357 | 843 | return ndelim; |
f078f209 | 844 | |
79acac07 FF |
845 | rix = bf->rates[0].idx; |
846 | flags = bf->rates[0].flags; | |
e8324357 S |
847 | width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0; |
848 | half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0; | |
f078f209 | 849 | |
e8324357 | 850 | if (half_gi) |
4ef70841 | 851 | nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity); |
e8324357 | 852 | else |
4ef70841 | 853 | nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity); |
f078f209 | 854 | |
e8324357 S |
855 | if (nsymbols == 0) |
856 | nsymbols = 1; | |
f078f209 | 857 | |
c6663876 FF |
858 | streams = HT_RC_2_STREAMS(rix); |
859 | nsymbits = bits_per_symbol[rix % 8][width] * streams; | |
e8324357 | 860 | minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; |
f078f209 | 861 | |
e8324357 | 862 | if (frmlen < minlen) { |
e8324357 S |
863 | mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ; |
864 | ndelim = max(mindelim, ndelim); | |
f078f209 LR |
865 | } |
866 | ||
e8324357 | 867 | return ndelim; |
f078f209 LR |
868 | } |
869 | ||
86a22acf FF |
870 | static struct ath_buf * |
871 | ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq, | |
a7586ee4 | 872 | struct ath_atx_tid *tid, struct sk_buff_head **q) |
f078f209 | 873 | { |
73364b0c | 874 | struct ieee80211_tx_info *tx_info; |
2d42efc4 | 875 | struct ath_frame_info *fi; |
56dc6336 | 876 | struct sk_buff *skb; |
86a22acf | 877 | struct ath_buf *bf; |
6a0ddaef | 878 | u16 seqno; |
f078f209 | 879 | |
86a22acf | 880 | while (1) { |
bb195ff6 FF |
881 | *q = &tid->retry_q; |
882 | if (skb_queue_empty(*q)) | |
883 | *q = &tid->buf_q; | |
884 | ||
a7586ee4 | 885 | skb = skb_peek(*q); |
86a22acf FF |
886 | if (!skb) |
887 | break; | |
888 | ||
56dc6336 FF |
889 | fi = get_frame_info(skb); |
890 | bf = fi->bf; | |
44f1d26c | 891 | if (!fi->bf) |
249ee722 | 892 | bf = ath_tx_setup_buffer(sc, txq, tid, skb); |
563299d8 FF |
893 | else |
894 | bf->bf_state.stale = false; | |
56dc6336 | 895 | |
249ee722 | 896 | if (!bf) { |
a7586ee4 | 897 | __skb_unlink(skb, *q); |
a4943ccb | 898 | ath_txq_skb_done(sc, txq, skb); |
249ee722 | 899 | ieee80211_free_txskb(sc->hw, skb); |
44f1d26c | 900 | continue; |
249ee722 | 901 | } |
44f1d26c | 902 | |
73364b0c FF |
903 | bf->bf_next = NULL; |
904 | bf->bf_lastbf = bf; | |
905 | ||
906 | tx_info = IEEE80211_SKB_CB(skb); | |
907 | tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT; | |
c01fac1c FF |
908 | |
909 | /* | |
910 | * No aggregation session is running, but there may be frames | |
911 | * from a previous session or a failed attempt in the queue. | |
912 | * Send them out as normal data frames | |
913 | */ | |
914 | if (!tid->active) | |
915 | tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU; | |
916 | ||
73364b0c FF |
917 | if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) { |
918 | bf->bf_state.bf_type = 0; | |
919 | return bf; | |
920 | } | |
921 | ||
399c6489 | 922 | bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR; |
44f1d26c | 923 | seqno = bf->bf_state.seqno; |
f078f209 | 924 | |
d43f3015 | 925 | /* do not step over block-ack window */ |
86a22acf | 926 | if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) |
e8324357 | 927 | break; |
f078f209 | 928 | |
f9437543 FF |
929 | if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) { |
930 | struct ath_tx_status ts = {}; | |
931 | struct list_head bf_head; | |
932 | ||
933 | INIT_LIST_HEAD(&bf_head); | |
934 | list_add(&bf->list, &bf_head); | |
a7586ee4 | 935 | __skb_unlink(skb, *q); |
f9437543 FF |
936 | ath_tx_update_baw(sc, tid, seqno); |
937 | ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0); | |
938 | continue; | |
939 | } | |
940 | ||
86a22acf FF |
941 | return bf; |
942 | } | |
943 | ||
944 | return NULL; | |
945 | } | |
946 | ||
2800e82b FF |
947 | static bool |
948 | ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq, | |
949 | struct ath_atx_tid *tid, struct list_head *bf_q, | |
950 | struct ath_buf *bf_first, struct sk_buff_head *tid_q, | |
951 | int *aggr_len) | |
86a22acf FF |
952 | { |
953 | #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) | |
2800e82b | 954 | struct ath_buf *bf = bf_first, *bf_prev = NULL; |
a1cd94d3 | 955 | int nframes = 0, ndelim; |
86a22acf | 956 | u16 aggr_limit = 0, al = 0, bpad = 0, |
a1cd94d3 | 957 | al_delta, h_baw = tid->baw_size / 2; |
86a22acf FF |
958 | struct ieee80211_tx_info *tx_info; |
959 | struct ath_frame_info *fi; | |
960 | struct sk_buff *skb; | |
2800e82b | 961 | bool closed = false; |
86a22acf | 962 | |
2800e82b FF |
963 | bf = bf_first; |
964 | aggr_limit = ath_lookup_rate(sc, bf, tid); | |
86a22acf | 965 | |
2800e82b | 966 | do { |
86a22acf FF |
967 | skb = bf->bf_mpdu; |
968 | fi = get_frame_info(skb); | |
969 | ||
d43f3015 | 970 | /* do not exceed aggregation limit */ |
2d42efc4 | 971 | al_delta = ATH_AGGR_DELIM_SZ + fi->framelen; |
a1cd94d3 FF |
972 | if (nframes) { |
973 | if (aggr_limit < al + bpad + al_delta || | |
2800e82b | 974 | ath_lookup_legacy(bf) || nframes >= h_baw) |
a1cd94d3 | 975 | break; |
f078f209 | 976 | |
a1cd94d3 | 977 | tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); |
2800e82b FF |
978 | if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) || |
979 | !(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) | |
a1cd94d3 | 980 | break; |
e8324357 | 981 | } |
f078f209 | 982 | |
d43f3015 | 983 | /* add padding for previous frame to aggregation length */ |
e8324357 | 984 | al += bpad + al_delta; |
f078f209 | 985 | |
e8324357 S |
986 | /* |
987 | * Get the delimiters needed to meet the MPDU | |
988 | * density for this node. | |
989 | */ | |
7a12dfdb RM |
990 | ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen, |
991 | !nframes); | |
e8324357 | 992 | bpad = PADBYTES(al_delta) + (ndelim << 2); |
f078f209 | 993 | |
7a12dfdb | 994 | nframes++; |
e8324357 | 995 | bf->bf_next = NULL; |
f078f209 | 996 | |
d43f3015 | 997 | /* link buffers of this frame to the aggregate */ |
8fed1408 FF |
998 | if (!fi->baw_tracked) |
999 | ath_tx_addto_baw(sc, tid, bf); | |
399c6489 | 1000 | bf->bf_state.ndelim = ndelim; |
56dc6336 | 1001 | |
a7586ee4 | 1002 | __skb_unlink(skb, tid_q); |
56dc6336 | 1003 | list_add_tail(&bf->list, bf_q); |
399c6489 | 1004 | if (bf_prev) |
e8324357 | 1005 | bf_prev->bf_next = bf; |
399c6489 | 1006 | |
e8324357 | 1007 | bf_prev = bf; |
fec247c0 | 1008 | |
2800e82b FF |
1009 | bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q); |
1010 | if (!bf) { | |
1011 | closed = true; | |
1012 | break; | |
1013 | } | |
a7586ee4 | 1014 | } while (ath_tid_has_buffered(tid)); |
f078f209 | 1015 | |
2800e82b FF |
1016 | bf = bf_first; |
1017 | bf->bf_lastbf = bf_prev; | |
1018 | ||
1019 | if (bf == bf_prev) { | |
1020 | al = get_frame_info(bf->bf_mpdu)->framelen; | |
1021 | bf->bf_state.bf_type = BUF_AMPDU; | |
1022 | } else { | |
1023 | TX_STAT_INC(txq->axq_qnum, a_aggr); | |
1024 | } | |
1025 | ||
269c44bc | 1026 | *aggr_len = al; |
d43f3015 | 1027 | |
2800e82b | 1028 | return closed; |
e8324357 S |
1029 | #undef PADBYTES |
1030 | } | |
f078f209 | 1031 | |
38dad7ba FF |
1032 | /* |
1033 | * rix - rate index | |
1034 | * pktlen - total bytes (delims + data + fcs + pads + pad delims) | |
1035 | * width - 0 for 20 MHz, 1 for 40 MHz | |
1036 | * half_gi - to use 4us v/s 3.6 us for symbol time | |
1037 | */ | |
1038 | static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen, | |
1039 | int width, int half_gi, bool shortPreamble) | |
1040 | { | |
1041 | u32 nbits, nsymbits, duration, nsymbols; | |
1042 | int streams; | |
1043 | ||
1044 | /* find number of symbols: PLCP + data */ | |
1045 | streams = HT_RC_2_STREAMS(rix); | |
1046 | nbits = (pktlen << 3) + OFDM_PLCP_BITS; | |
1047 | nsymbits = bits_per_symbol[rix % 8][width] * streams; | |
1048 | nsymbols = (nbits + nsymbits - 1) / nsymbits; | |
1049 | ||
1050 | if (!half_gi) | |
1051 | duration = SYMBOL_TIME(nsymbols); | |
1052 | else | |
1053 | duration = SYMBOL_TIME_HALFGI(nsymbols); | |
1054 | ||
1055 | /* addup duration for legacy/ht training and signal fields */ | |
1056 | duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); | |
1057 | ||
1058 | return duration; | |
1059 | } | |
1060 | ||
aa5955c3 FF |
1061 | static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi) |
1062 | { | |
1063 | int streams = HT_RC_2_STREAMS(mcs); | |
1064 | int symbols, bits; | |
1065 | int bytes = 0; | |
1066 | ||
727b662c | 1067 | usec -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); |
aa5955c3 FF |
1068 | symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec); |
1069 | bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams; | |
1070 | bits -= OFDM_PLCP_BITS; | |
1071 | bytes = bits / 8; | |
aa5955c3 FF |
1072 | if (bytes > 65532) |
1073 | bytes = 65532; | |
1074 | ||
1075 | return bytes; | |
1076 | } | |
1077 | ||
1078 | void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop) | |
1079 | { | |
1080 | u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi; | |
1081 | int mcs; | |
1082 | ||
1083 | /* 4ms is the default (and maximum) duration */ | |
1084 | if (!txop || txop > 4096) | |
1085 | txop = 4096; | |
1086 | ||
1087 | cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20]; | |
1088 | cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI]; | |
1089 | cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40]; | |
1090 | cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI]; | |
1091 | for (mcs = 0; mcs < 32; mcs++) { | |
1092 | cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false); | |
1093 | cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true); | |
1094 | cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false); | |
1095 | cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true); | |
1096 | } | |
1097 | } | |
1098 | ||
8b537686 | 1099 | static u8 ath_get_rate_txpower(struct ath_softc *sc, struct ath_buf *bf, |
9ddad58b | 1100 | u8 rateidx, bool is_40, bool is_cck) |
8b537686 LB |
1101 | { |
1102 | u8 max_power; | |
9ddad58b LB |
1103 | struct sk_buff *skb; |
1104 | struct ath_frame_info *fi; | |
1105 | struct ieee80211_tx_info *info; | |
8b537686 LB |
1106 | struct ath_hw *ah = sc->sc_ah; |
1107 | ||
9ddad58b | 1108 | if (sc->tx99_state || !ah->tpc_enabled) |
8b537686 LB |
1109 | return MAX_RATE_POWER; |
1110 | ||
9ddad58b LB |
1111 | skb = bf->bf_mpdu; |
1112 | fi = get_frame_info(skb); | |
1113 | info = IEEE80211_SKB_CB(skb); | |
1114 | ||
8b537686 | 1115 | if (!AR_SREV_9300_20_OR_LATER(ah)) { |
9ddad58b | 1116 | int txpower = fi->tx_power; |
8b537686 | 1117 | |
9ddad58b LB |
1118 | if (is_40) { |
1119 | u8 power_ht40delta; | |
1120 | struct ar5416_eeprom_def *eep = &ah->eeprom.def; | |
8b537686 | 1121 | |
9ddad58b LB |
1122 | if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) { |
1123 | bool is_2ghz; | |
1124 | struct modal_eep_header *pmodal; | |
1125 | ||
1126 | is_2ghz = info->band == IEEE80211_BAND_2GHZ; | |
1127 | pmodal = &eep->modalHeader[is_2ghz]; | |
1128 | power_ht40delta = pmodal->ht40PowerIncForPdadc; | |
1129 | } else { | |
1130 | power_ht40delta = 2; | |
1131 | } | |
1132 | txpower += power_ht40delta; | |
1133 | } | |
1134 | ||
1135 | if (AR_SREV_9287(ah) || AR_SREV_9285(ah) || | |
1136 | AR_SREV_9271(ah)) { | |
1137 | txpower -= 2 * AR9287_PWR_TABLE_OFFSET_DB; | |
1138 | } else if (AR_SREV_9280_20_OR_LATER(ah)) { | |
1139 | s8 power_offset; | |
1140 | ||
1141 | power_offset = ah->eep_ops->get_eeprom(ah, | |
1142 | EEP_PWR_TABLE_OFFSET); | |
1143 | txpower -= 2 * power_offset; | |
1144 | } | |
1145 | ||
1146 | if (OLC_FOR_AR9280_20_LATER && is_cck) | |
1147 | txpower -= 2; | |
1148 | ||
1149 | txpower = max(txpower, 0); | |
1150 | max_power = min_t(u8, ah->tx_power[rateidx], txpower); | |
1151 | ||
1152 | /* XXX: clamp minimum TX power at 1 for AR9160 since if | |
1153 | * max_power is set to 0, frames are transmitted at max | |
1154 | * TX power | |
1155 | */ | |
1156 | if (!max_power && !AR_SREV_9280_20_OR_LATER(ah)) | |
1157 | max_power = 1; | |
1158 | } else if (!bf->bf_state.bfs_paprd) { | |
8b537686 LB |
1159 | if (rateidx < 8 && (info->flags & IEEE80211_TX_CTL_STBC)) |
1160 | max_power = min(ah->tx_power_stbc[rateidx], | |
1161 | fi->tx_power); | |
1162 | else | |
1163 | max_power = min(ah->tx_power[rateidx], fi->tx_power); | |
1164 | } else { | |
1165 | max_power = ah->paprd_training_power; | |
1166 | } | |
1167 | ||
1168 | return max_power; | |
1169 | } | |
1170 | ||
493cf04f | 1171 | static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, |
a3835e9f | 1172 | struct ath_tx_info *info, int len, bool rts) |
38dad7ba FF |
1173 | { |
1174 | struct ath_hw *ah = sc->sc_ah; | |
13f71050 | 1175 | struct ath_common *common = ath9k_hw_common(ah); |
38dad7ba FF |
1176 | struct sk_buff *skb; |
1177 | struct ieee80211_tx_info *tx_info; | |
1178 | struct ieee80211_tx_rate *rates; | |
1179 | const struct ieee80211_rate *rate; | |
1180 | struct ieee80211_hdr *hdr; | |
80b08a8d | 1181 | struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); |
a3835e9f | 1182 | u32 rts_thresh = sc->hw->wiphy->rts_threshold; |
493cf04f FF |
1183 | int i; |
1184 | u8 rix = 0; | |
38dad7ba FF |
1185 | |
1186 | skb = bf->bf_mpdu; | |
1187 | tx_info = IEEE80211_SKB_CB(skb); | |
79acac07 | 1188 | rates = bf->rates; |
38dad7ba | 1189 | hdr = (struct ieee80211_hdr *)skb->data; |
493cf04f FF |
1190 | |
1191 | /* set dur_update_en for l-sig computation except for PS-Poll frames */ | |
1192 | info->dur_update = !ieee80211_is_pspoll(hdr->frame_control); | |
80b08a8d | 1193 | info->rtscts_rate = fi->rtscts_rate; |
38dad7ba | 1194 | |
79acac07 | 1195 | for (i = 0; i < ARRAY_SIZE(bf->rates); i++) { |
9ddad58b | 1196 | bool is_40, is_sgi, is_sp, is_cck; |
38dad7ba FF |
1197 | int phy; |
1198 | ||
1199 | if (!rates[i].count || (rates[i].idx < 0)) | |
1200 | continue; | |
1201 | ||
1202 | rix = rates[i].idx; | |
493cf04f | 1203 | info->rates[i].Tries = rates[i].count; |
38dad7ba | 1204 | |
a3835e9f SM |
1205 | /* |
1206 | * Handle RTS threshold for unaggregated HT frames. | |
1207 | */ | |
1208 | if (bf_isampdu(bf) && !bf_isaggr(bf) && | |
1209 | (rates[i].flags & IEEE80211_TX_RC_MCS) && | |
1210 | unlikely(rts_thresh != (u32) -1)) { | |
1211 | if (!rts_thresh || (len > rts_thresh)) | |
1212 | rts = true; | |
1213 | } | |
1214 | ||
1215 | if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) { | |
493cf04f FF |
1216 | info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; |
1217 | info->flags |= ATH9K_TXDESC_RTSENA; | |
38dad7ba | 1218 | } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { |
493cf04f FF |
1219 | info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; |
1220 | info->flags |= ATH9K_TXDESC_CTSENA; | |
38dad7ba FF |
1221 | } |
1222 | ||
1223 | if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) | |
493cf04f | 1224 | info->rates[i].RateFlags |= ATH9K_RATESERIES_2040; |
38dad7ba | 1225 | if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) |
493cf04f | 1226 | info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI; |
38dad7ba FF |
1227 | |
1228 | is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI); | |
1229 | is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH); | |
1230 | is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE); | |
1231 | ||
1232 | if (rates[i].flags & IEEE80211_TX_RC_MCS) { | |
1233 | /* MCS rates */ | |
493cf04f FF |
1234 | info->rates[i].Rate = rix | 0x80; |
1235 | info->rates[i].ChSel = ath_txchainmask_reduction(sc, | |
1236 | ah->txchainmask, info->rates[i].Rate); | |
1237 | info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len, | |
38dad7ba FF |
1238 | is_40, is_sgi, is_sp); |
1239 | if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC)) | |
493cf04f | 1240 | info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC; |
8b537686 | 1241 | |
9ddad58b LB |
1242 | info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, |
1243 | is_40, false); | |
38dad7ba FF |
1244 | continue; |
1245 | } | |
1246 | ||
1247 | /* legacy rates */ | |
13f71050 | 1248 | rate = &common->sbands[tx_info->band].bitrates[rates[i].idx]; |
38dad7ba FF |
1249 | if ((tx_info->band == IEEE80211_BAND_2GHZ) && |
1250 | !(rate->flags & IEEE80211_RATE_ERP_G)) | |
1251 | phy = WLAN_RC_PHY_CCK; | |
1252 | else | |
1253 | phy = WLAN_RC_PHY_OFDM; | |
1254 | ||
493cf04f | 1255 | info->rates[i].Rate = rate->hw_value; |
38dad7ba FF |
1256 | if (rate->hw_value_short) { |
1257 | if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) | |
493cf04f | 1258 | info->rates[i].Rate |= rate->hw_value_short; |
38dad7ba FF |
1259 | } else { |
1260 | is_sp = false; | |
1261 | } | |
1262 | ||
1263 | if (bf->bf_state.bfs_paprd) | |
493cf04f | 1264 | info->rates[i].ChSel = ah->txchainmask; |
38dad7ba | 1265 | else |
493cf04f FF |
1266 | info->rates[i].ChSel = ath_txchainmask_reduction(sc, |
1267 | ah->txchainmask, info->rates[i].Rate); | |
38dad7ba | 1268 | |
493cf04f | 1269 | info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah, |
38dad7ba | 1270 | phy, rate->bitrate * 100, len, rix, is_sp); |
8b537686 | 1271 | |
9ddad58b LB |
1272 | is_cck = IS_CCK_RATE(info->rates[i].Rate); |
1273 | info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, false, | |
1274 | is_cck); | |
38dad7ba FF |
1275 | } |
1276 | ||
1277 | /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ | |
1278 | if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit)) | |
493cf04f | 1279 | info->flags &= ~ATH9K_TXDESC_RTSENA; |
38dad7ba FF |
1280 | |
1281 | /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */ | |
493cf04f FF |
1282 | if (info->flags & ATH9K_TXDESC_RTSENA) |
1283 | info->flags &= ~ATH9K_TXDESC_CTSENA; | |
1284 | } | |
38dad7ba | 1285 | |
493cf04f FF |
1286 | static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb) |
1287 | { | |
1288 | struct ieee80211_hdr *hdr; | |
1289 | enum ath9k_pkt_type htype; | |
1290 | __le16 fc; | |
1291 | ||
1292 | hdr = (struct ieee80211_hdr *)skb->data; | |
1293 | fc = hdr->frame_control; | |
38dad7ba | 1294 | |
493cf04f FF |
1295 | if (ieee80211_is_beacon(fc)) |
1296 | htype = ATH9K_PKT_TYPE_BEACON; | |
1297 | else if (ieee80211_is_probe_resp(fc)) | |
1298 | htype = ATH9K_PKT_TYPE_PROBE_RESP; | |
1299 | else if (ieee80211_is_atim(fc)) | |
1300 | htype = ATH9K_PKT_TYPE_ATIM; | |
1301 | else if (ieee80211_is_pspoll(fc)) | |
1302 | htype = ATH9K_PKT_TYPE_PSPOLL; | |
1303 | else | |
1304 | htype = ATH9K_PKT_TYPE_NORMAL; | |
1305 | ||
1306 | return htype; | |
38dad7ba FF |
1307 | } |
1308 | ||
493cf04f FF |
1309 | static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf, |
1310 | struct ath_txq *txq, int len) | |
399c6489 FF |
1311 | { |
1312 | struct ath_hw *ah = sc->sc_ah; | |
86a22acf | 1313 | struct ath_buf *bf_first = NULL; |
493cf04f | 1314 | struct ath_tx_info info; |
a3835e9f SM |
1315 | u32 rts_thresh = sc->hw->wiphy->rts_threshold; |
1316 | bool rts = false; | |
399c6489 | 1317 | |
493cf04f FF |
1318 | memset(&info, 0, sizeof(info)); |
1319 | info.is_first = true; | |
1320 | info.is_last = true; | |
493cf04f FF |
1321 | info.qcu = txq->axq_qnum; |
1322 | ||
399c6489 | 1323 | while (bf) { |
493cf04f | 1324 | struct sk_buff *skb = bf->bf_mpdu; |
86a22acf | 1325 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
493cf04f | 1326 | struct ath_frame_info *fi = get_frame_info(skb); |
86a22acf | 1327 | bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR); |
493cf04f FF |
1328 | |
1329 | info.type = get_hw_packet_type(skb); | |
399c6489 | 1330 | if (bf->bf_next) |
493cf04f | 1331 | info.link = bf->bf_next->bf_daddr; |
399c6489 | 1332 | else |
89f927af | 1333 | info.link = (sc->tx99_state) ? bf->bf_daddr : 0; |
493cf04f | 1334 | |
86a22acf FF |
1335 | if (!bf_first) { |
1336 | bf_first = bf; | |
1337 | ||
89f927af LR |
1338 | if (!sc->tx99_state) |
1339 | info.flags = ATH9K_TXDESC_INTREQ; | |
86a22acf FF |
1340 | if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) || |
1341 | txq == sc->tx.uapsdq) | |
1342 | info.flags |= ATH9K_TXDESC_CLRDMASK; | |
1343 | ||
1344 | if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) | |
1345 | info.flags |= ATH9K_TXDESC_NOACK; | |
1346 | if (tx_info->flags & IEEE80211_TX_CTL_LDPC) | |
1347 | info.flags |= ATH9K_TXDESC_LDPC; | |
1348 | ||
1349 | if (bf->bf_state.bfs_paprd) | |
1350 | info.flags |= (u32) bf->bf_state.bfs_paprd << | |
1351 | ATH9K_TXDESC_PAPRD_S; | |
1352 | ||
a3835e9f SM |
1353 | /* |
1354 | * mac80211 doesn't handle RTS threshold for HT because | |
1355 | * the decision has to be taken based on AMPDU length | |
1356 | * and aggregation is done entirely inside ath9k. | |
1357 | * Set the RTS/CTS flag for the first subframe based | |
1358 | * on the threshold. | |
1359 | */ | |
1360 | if (aggr && (bf == bf_first) && | |
1361 | unlikely(rts_thresh != (u32) -1)) { | |
1362 | /* | |
1363 | * "len" is the size of the entire AMPDU. | |
1364 | */ | |
1365 | if (!rts_thresh || (len > rts_thresh)) | |
1366 | rts = true; | |
1367 | } | |
bbf807bc FF |
1368 | |
1369 | if (!aggr) | |
1370 | len = fi->framelen; | |
1371 | ||
a3835e9f | 1372 | ath_buf_set_rate(sc, bf, &info, len, rts); |
86a22acf FF |
1373 | } |
1374 | ||
42cecc34 JL |
1375 | info.buf_addr[0] = bf->bf_buf_addr; |
1376 | info.buf_len[0] = skb->len; | |
493cf04f FF |
1377 | info.pkt_len = fi->framelen; |
1378 | info.keyix = fi->keyix; | |
1379 | info.keytype = fi->keytype; | |
1380 | ||
1381 | if (aggr) { | |
399c6489 | 1382 | if (bf == bf_first) |
493cf04f | 1383 | info.aggr = AGGR_BUF_FIRST; |
86a22acf | 1384 | else if (bf == bf_first->bf_lastbf) |
493cf04f FF |
1385 | info.aggr = AGGR_BUF_LAST; |
1386 | else | |
1387 | info.aggr = AGGR_BUF_MIDDLE; | |
399c6489 | 1388 | |
493cf04f FF |
1389 | info.ndelim = bf->bf_state.ndelim; |
1390 | info.aggr_len = len; | |
399c6489 FF |
1391 | } |
1392 | ||
86a22acf FF |
1393 | if (bf == bf_first->bf_lastbf) |
1394 | bf_first = NULL; | |
1395 | ||
493cf04f | 1396 | ath9k_hw_set_txdesc(ah, bf->bf_desc, &info); |
399c6489 FF |
1397 | bf = bf->bf_next; |
1398 | } | |
1399 | } | |
1400 | ||
2800e82b FF |
1401 | static void |
1402 | ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq, | |
1403 | struct ath_atx_tid *tid, struct list_head *bf_q, | |
1404 | struct ath_buf *bf_first, struct sk_buff_head *tid_q) | |
1405 | { | |
1406 | struct ath_buf *bf = bf_first, *bf_prev = NULL; | |
1407 | struct sk_buff *skb; | |
1408 | int nframes = 0; | |
1409 | ||
1410 | do { | |
1411 | struct ieee80211_tx_info *tx_info; | |
1412 | skb = bf->bf_mpdu; | |
1413 | ||
1414 | nframes++; | |
1415 | __skb_unlink(skb, tid_q); | |
1416 | list_add_tail(&bf->list, bf_q); | |
1417 | if (bf_prev) | |
1418 | bf_prev->bf_next = bf; | |
1419 | bf_prev = bf; | |
1420 | ||
1421 | if (nframes >= 2) | |
1422 | break; | |
1423 | ||
1424 | bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q); | |
1425 | if (!bf) | |
1426 | break; | |
1427 | ||
1428 | tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); | |
1429 | if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) | |
1430 | break; | |
1431 | ||
1432 | ath_set_rates(tid->an->vif, tid->an->sta, bf); | |
1433 | } while (1); | |
1434 | } | |
1435 | ||
020f20f6 FF |
1436 | static bool ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq, |
1437 | struct ath_atx_tid *tid, bool *stop) | |
e8324357 | 1438 | { |
d43f3015 | 1439 | struct ath_buf *bf; |
399c6489 | 1440 | struct ieee80211_tx_info *tx_info; |
2800e82b | 1441 | struct sk_buff_head *tid_q; |
e8324357 | 1442 | struct list_head bf_q; |
2800e82b FF |
1443 | int aggr_len = 0; |
1444 | bool aggr, last = true; | |
f078f209 | 1445 | |
020f20f6 FF |
1446 | if (!ath_tid_has_buffered(tid)) |
1447 | return false; | |
f078f209 | 1448 | |
020f20f6 | 1449 | INIT_LIST_HEAD(&bf_q); |
e8324357 | 1450 | |
020f20f6 FF |
1451 | bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q); |
1452 | if (!bf) | |
1453 | return false; | |
f078f209 | 1454 | |
020f20f6 FF |
1455 | tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); |
1456 | aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU); | |
1457 | if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) || | |
1458 | (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) { | |
1459 | *stop = true; | |
1460 | return false; | |
1461 | } | |
2800e82b | 1462 | |
020f20f6 FF |
1463 | ath_set_rates(tid->an->vif, tid->an->sta, bf); |
1464 | if (aggr) | |
1465 | last = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf, | |
1466 | tid_q, &aggr_len); | |
1467 | else | |
1468 | ath_tx_form_burst(sc, txq, tid, &bf_q, bf, tid_q); | |
2800e82b | 1469 | |
020f20f6 FF |
1470 | if (list_empty(&bf_q)) |
1471 | return false; | |
f078f209 | 1472 | |
f89d1bc4 | 1473 | if (tid->ac->clear_ps_filter || tid->an->no_ps_filter) { |
020f20f6 FF |
1474 | tid->ac->clear_ps_filter = false; |
1475 | tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT; | |
1476 | } | |
f078f209 | 1477 | |
020f20f6 FF |
1478 | ath_tx_fill_desc(sc, bf, txq, aggr_len); |
1479 | ath_tx_txqaddbuf(sc, txq, &bf_q, false); | |
1480 | return true; | |
e8324357 S |
1481 | } |
1482 | ||
231c3a1f FF |
1483 | int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, |
1484 | u16 tid, u16 *ssn) | |
e8324357 S |
1485 | { |
1486 | struct ath_atx_tid *txtid; | |
919123d2 | 1487 | struct ath_txq *txq; |
e8324357 | 1488 | struct ath_node *an; |
313eb87f | 1489 | u8 density; |
e8324357 S |
1490 | |
1491 | an = (struct ath_node *)sta->drv_priv; | |
f83da965 | 1492 | txtid = ATH_AN_2_TID(an, tid); |
919123d2 FF |
1493 | txq = txtid->ac->txq; |
1494 | ||
1495 | ath_txq_lock(sc, txq); | |
231c3a1f | 1496 | |
313eb87f SE |
1497 | /* update ampdu factor/density, they may have changed. This may happen |
1498 | * in HT IBSS when a beacon with HT-info is received after the station | |
1499 | * has already been added. | |
1500 | */ | |
dd5ee59b | 1501 | if (sta->ht_cap.ht_supported) { |
5b502c86 SM |
1502 | an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + |
1503 | sta->ht_cap.ampdu_factor)) - 1; | |
313eb87f SE |
1504 | density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density); |
1505 | an->mpdudensity = density; | |
1506 | } | |
1507 | ||
2800e82b FF |
1508 | /* force sequence number allocation for pending frames */ |
1509 | ath_tx_tid_change_state(sc, txtid); | |
1510 | ||
08c96abd | 1511 | txtid->active = true; |
49447f2f | 1512 | *ssn = txtid->seq_start = txtid->seq_next; |
f9437543 | 1513 | txtid->bar_index = -1; |
231c3a1f | 1514 | |
2ed72229 FF |
1515 | memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf)); |
1516 | txtid->baw_head = txtid->baw_tail = 0; | |
1517 | ||
919123d2 FF |
1518 | ath_txq_unlock_complete(sc, txq); |
1519 | ||
231c3a1f | 1520 | return 0; |
e8324357 | 1521 | } |
f078f209 | 1522 | |
08c96abd | 1523 | void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) |
e8324357 S |
1524 | { |
1525 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
1526 | struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid); | |
066dae93 | 1527 | struct ath_txq *txq = txtid->ac->txq; |
f078f209 | 1528 | |
23de5dc9 | 1529 | ath_txq_lock(sc, txq); |
08c96abd | 1530 | txtid->active = false; |
08c96abd | 1531 | ath_tx_flush_tid(sc, txtid); |
2800e82b | 1532 | ath_tx_tid_change_state(sc, txtid); |
23de5dc9 | 1533 | ath_txq_unlock_complete(sc, txq); |
e8324357 | 1534 | } |
f078f209 | 1535 | |
042ec453 JB |
1536 | void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc, |
1537 | struct ath_node *an) | |
5519541d FF |
1538 | { |
1539 | struct ath_atx_tid *tid; | |
1540 | struct ath_atx_ac *ac; | |
1541 | struct ath_txq *txq; | |
042ec453 | 1542 | bool buffered; |
5519541d FF |
1543 | int tidno; |
1544 | ||
1545 | for (tidno = 0, tid = &an->tid[tidno]; | |
de7b7604 | 1546 | tidno < IEEE80211_NUM_TIDS; tidno++, tid++) { |
5519541d | 1547 | |
5519541d FF |
1548 | ac = tid->ac; |
1549 | txq = ac->txq; | |
1550 | ||
23de5dc9 | 1551 | ath_txq_lock(sc, txq); |
5519541d | 1552 | |
21f8aaee SG |
1553 | if (!tid->sched) { |
1554 | ath_txq_unlock(sc, txq); | |
1555 | continue; | |
1556 | } | |
1557 | ||
a7586ee4 | 1558 | buffered = ath_tid_has_buffered(tid); |
5519541d FF |
1559 | |
1560 | tid->sched = false; | |
1561 | list_del(&tid->list); | |
1562 | ||
1563 | if (ac->sched) { | |
1564 | ac->sched = false; | |
1565 | list_del(&ac->list); | |
1566 | } | |
1567 | ||
23de5dc9 | 1568 | ath_txq_unlock(sc, txq); |
5519541d | 1569 | |
042ec453 JB |
1570 | ieee80211_sta_set_buffered(sta, tidno, buffered); |
1571 | } | |
5519541d FF |
1572 | } |
1573 | ||
1574 | void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an) | |
1575 | { | |
1576 | struct ath_atx_tid *tid; | |
1577 | struct ath_atx_ac *ac; | |
1578 | struct ath_txq *txq; | |
1579 | int tidno; | |
1580 | ||
1581 | for (tidno = 0, tid = &an->tid[tidno]; | |
de7b7604 | 1582 | tidno < IEEE80211_NUM_TIDS; tidno++, tid++) { |
5519541d FF |
1583 | |
1584 | ac = tid->ac; | |
1585 | txq = ac->txq; | |
1586 | ||
23de5dc9 | 1587 | ath_txq_lock(sc, txq); |
5519541d FF |
1588 | ac->clear_ps_filter = true; |
1589 | ||
62e54dbb | 1590 | if (ath_tid_has_buffered(tid)) { |
0453531e | 1591 | ath_tx_queue_tid(sc, txq, tid); |
5519541d FF |
1592 | ath_txq_schedule(sc, txq); |
1593 | } | |
1594 | ||
23de5dc9 | 1595 | ath_txq_unlock_complete(sc, txq); |
5519541d FF |
1596 | } |
1597 | } | |
1598 | ||
08c96abd FF |
1599 | void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, |
1600 | u16 tidno) | |
e8324357 | 1601 | { |
08c96abd | 1602 | struct ath_atx_tid *tid; |
e8324357 | 1603 | struct ath_node *an; |
08c96abd | 1604 | struct ath_txq *txq; |
e8324357 S |
1605 | |
1606 | an = (struct ath_node *)sta->drv_priv; | |
08c96abd FF |
1607 | tid = ATH_AN_2_TID(an, tidno); |
1608 | txq = tid->ac->txq; | |
e8324357 | 1609 | |
08c96abd FF |
1610 | ath_txq_lock(sc, txq); |
1611 | ||
1612 | tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor; | |
08c96abd | 1613 | |
a7586ee4 | 1614 | if (ath_tid_has_buffered(tid)) { |
0453531e | 1615 | ath_tx_queue_tid(sc, txq, tid); |
08c96abd FF |
1616 | ath_txq_schedule(sc, txq); |
1617 | } | |
1618 | ||
1619 | ath_txq_unlock_complete(sc, txq); | |
f078f209 LR |
1620 | } |
1621 | ||
86a22acf FF |
1622 | void ath9k_release_buffered_frames(struct ieee80211_hw *hw, |
1623 | struct ieee80211_sta *sta, | |
1624 | u16 tids, int nframes, | |
1625 | enum ieee80211_frame_release_type reason, | |
1626 | bool more_data) | |
1627 | { | |
1628 | struct ath_softc *sc = hw->priv; | |
1629 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
1630 | struct ath_txq *txq = sc->tx.uapsdq; | |
1631 | struct ieee80211_tx_info *info; | |
1632 | struct list_head bf_q; | |
1633 | struct ath_buf *bf_tail = NULL, *bf; | |
a7586ee4 | 1634 | struct sk_buff_head *tid_q; |
86a22acf FF |
1635 | int sent = 0; |
1636 | int i; | |
1637 | ||
1638 | INIT_LIST_HEAD(&bf_q); | |
1639 | for (i = 0; tids && nframes; i++, tids >>= 1) { | |
1640 | struct ath_atx_tid *tid; | |
1641 | ||
1642 | if (!(tids & 1)) | |
1643 | continue; | |
1644 | ||
1645 | tid = ATH_AN_2_TID(an, i); | |
86a22acf FF |
1646 | |
1647 | ath_txq_lock(sc, tid->ac->txq); | |
a7586ee4 FF |
1648 | while (nframes > 0) { |
1649 | bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid, &tid_q); | |
86a22acf FF |
1650 | if (!bf) |
1651 | break; | |
1652 | ||
a7586ee4 | 1653 | __skb_unlink(bf->bf_mpdu, tid_q); |
86a22acf FF |
1654 | list_add_tail(&bf->list, &bf_q); |
1655 | ath_set_rates(tid->an->vif, tid->an->sta, bf); | |
20e6e55a FF |
1656 | if (bf_isampdu(bf)) { |
1657 | ath_tx_addto_baw(sc, tid, bf); | |
1658 | bf->bf_state.bf_type &= ~BUF_AGGR; | |
1659 | } | |
86a22acf FF |
1660 | if (bf_tail) |
1661 | bf_tail->bf_next = bf; | |
1662 | ||
1663 | bf_tail = bf; | |
1664 | nframes--; | |
1665 | sent++; | |
1666 | TX_STAT_INC(txq->axq_qnum, a_queued_hw); | |
1667 | ||
f89d1bc4 | 1668 | if (an->sta && !ath_tid_has_buffered(tid)) |
86a22acf FF |
1669 | ieee80211_sta_set_buffered(an->sta, i, false); |
1670 | } | |
1671 | ath_txq_unlock_complete(sc, tid->ac->txq); | |
1672 | } | |
1673 | ||
1674 | if (list_empty(&bf_q)) | |
1675 | return; | |
1676 | ||
1677 | info = IEEE80211_SKB_CB(bf_tail->bf_mpdu); | |
1678 | info->flags |= IEEE80211_TX_STATUS_EOSP; | |
1679 | ||
1680 | bf = list_first_entry(&bf_q, struct ath_buf, list); | |
1681 | ath_txq_lock(sc, txq); | |
1682 | ath_tx_fill_desc(sc, bf, txq, 0); | |
1683 | ath_tx_txqaddbuf(sc, txq, &bf_q, false); | |
1684 | ath_txq_unlock(sc, txq); | |
1685 | } | |
1686 | ||
e8324357 S |
1687 | /********************/ |
1688 | /* Queue Management */ | |
1689 | /********************/ | |
f078f209 | 1690 | |
e8324357 | 1691 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) |
f078f209 | 1692 | { |
cbe61d8a | 1693 | struct ath_hw *ah = sc->sc_ah; |
e8324357 | 1694 | struct ath9k_tx_queue_info qi; |
066dae93 | 1695 | static const int subtype_txq_to_hwq[] = { |
bea843c7 SM |
1696 | [IEEE80211_AC_BE] = ATH_TXQ_AC_BE, |
1697 | [IEEE80211_AC_BK] = ATH_TXQ_AC_BK, | |
1698 | [IEEE80211_AC_VI] = ATH_TXQ_AC_VI, | |
1699 | [IEEE80211_AC_VO] = ATH_TXQ_AC_VO, | |
066dae93 | 1700 | }; |
60f2d1d5 | 1701 | int axq_qnum, i; |
f078f209 | 1702 | |
e8324357 | 1703 | memset(&qi, 0, sizeof(qi)); |
066dae93 | 1704 | qi.tqi_subtype = subtype_txq_to_hwq[subtype]; |
e8324357 S |
1705 | qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT; |
1706 | qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT; | |
1707 | qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT; | |
1708 | qi.tqi_physCompBuf = 0; | |
f078f209 LR |
1709 | |
1710 | /* | |
e8324357 S |
1711 | * Enable interrupts only for EOL and DESC conditions. |
1712 | * We mark tx descriptors to receive a DESC interrupt | |
1713 | * when a tx queue gets deep; otherwise waiting for the | |
1714 | * EOL to reap descriptors. Note that this is done to | |
1715 | * reduce interrupt load and this only defers reaping | |
1716 | * descriptors, never transmitting frames. Aside from | |
1717 | * reducing interrupts this also permits more concurrency. | |
1718 | * The only potential downside is if the tx queue backs | |
1719 | * up in which case the top half of the kernel may backup | |
1720 | * due to a lack of tx descriptors. | |
1721 | * | |
1722 | * The UAPSD queue is an exception, since we take a desc- | |
1723 | * based intr on the EOSP frames. | |
f078f209 | 1724 | */ |
afe754d6 | 1725 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
ce8fdf6e | 1726 | qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE; |
afe754d6 VT |
1727 | } else { |
1728 | if (qtype == ATH9K_TX_QUEUE_UAPSD) | |
1729 | qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; | |
1730 | else | |
1731 | qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | | |
1732 | TXQ_FLAG_TXDESCINT_ENABLE; | |
1733 | } | |
60f2d1d5 BG |
1734 | axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); |
1735 | if (axq_qnum == -1) { | |
f078f209 | 1736 | /* |
e8324357 S |
1737 | * NB: don't print a message, this happens |
1738 | * normally on parts with too few tx queues | |
f078f209 | 1739 | */ |
e8324357 | 1740 | return NULL; |
f078f209 | 1741 | } |
60f2d1d5 BG |
1742 | if (!ATH_TXQ_SETUP(sc, axq_qnum)) { |
1743 | struct ath_txq *txq = &sc->tx.txq[axq_qnum]; | |
f078f209 | 1744 | |
60f2d1d5 BG |
1745 | txq->axq_qnum = axq_qnum; |
1746 | txq->mac80211_qnum = -1; | |
e8324357 | 1747 | txq->axq_link = NULL; |
23de5dc9 | 1748 | __skb_queue_head_init(&txq->complete_q); |
e8324357 | 1749 | INIT_LIST_HEAD(&txq->axq_q); |
e8324357 S |
1750 | spin_lock_init(&txq->axq_lock); |
1751 | txq->axq_depth = 0; | |
4b3ba66a | 1752 | txq->axq_ampdu_depth = 0; |
164ace38 | 1753 | txq->axq_tx_inprogress = false; |
60f2d1d5 | 1754 | sc->tx.txqsetup |= 1<<axq_qnum; |
e5003249 VT |
1755 | |
1756 | txq->txq_headidx = txq->txq_tailidx = 0; | |
1757 | for (i = 0; i < ATH_TXFIFO_DEPTH; i++) | |
1758 | INIT_LIST_HEAD(&txq->txq_fifo[i]); | |
e8324357 | 1759 | } |
60f2d1d5 | 1760 | return &sc->tx.txq[axq_qnum]; |
f078f209 LR |
1761 | } |
1762 | ||
e8324357 S |
1763 | int ath_txq_update(struct ath_softc *sc, int qnum, |
1764 | struct ath9k_tx_queue_info *qinfo) | |
1765 | { | |
cbe61d8a | 1766 | struct ath_hw *ah = sc->sc_ah; |
e8324357 S |
1767 | int error = 0; |
1768 | struct ath9k_tx_queue_info qi; | |
1769 | ||
9680e8a3 | 1770 | BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum); |
e8324357 S |
1771 | |
1772 | ath9k_hw_get_txq_props(ah, qnum, &qi); | |
1773 | qi.tqi_aifs = qinfo->tqi_aifs; | |
1774 | qi.tqi_cwmin = qinfo->tqi_cwmin; | |
1775 | qi.tqi_cwmax = qinfo->tqi_cwmax; | |
1776 | qi.tqi_burstTime = qinfo->tqi_burstTime; | |
1777 | qi.tqi_readyTime = qinfo->tqi_readyTime; | |
1778 | ||
1779 | if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { | |
3800276a JP |
1780 | ath_err(ath9k_hw_common(sc->sc_ah), |
1781 | "Unable to update hardware queue %u!\n", qnum); | |
e8324357 S |
1782 | error = -EIO; |
1783 | } else { | |
1784 | ath9k_hw_resettxqueue(ah, qnum); | |
1785 | } | |
1786 | ||
1787 | return error; | |
1788 | } | |
1789 | ||
1790 | int ath_cabq_update(struct ath_softc *sc) | |
1791 | { | |
1792 | struct ath9k_tx_queue_info qi; | |
ca900ac9 | 1793 | struct ath_beacon_config *cur_conf = &sc->cur_chan->beacon; |
e8324357 | 1794 | int qnum = sc->beacon.cabq->axq_qnum; |
f078f209 | 1795 | |
e8324357 | 1796 | ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi); |
f078f209 | 1797 | |
3b3e0efb | 1798 | qi.tqi_readyTime = (TU_TO_USEC(cur_conf->beacon_interval) * |
7f329bbb | 1799 | ATH_CABQ_READY_TIME) / 100; |
e8324357 S |
1800 | ath_txq_update(sc, qnum, &qi); |
1801 | ||
1802 | return 0; | |
f078f209 LR |
1803 | } |
1804 | ||
fce041be | 1805 | static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq, |
1381559b | 1806 | struct list_head *list) |
f078f209 | 1807 | { |
e8324357 S |
1808 | struct ath_buf *bf, *lastbf; |
1809 | struct list_head bf_head; | |
db1a052b FF |
1810 | struct ath_tx_status ts; |
1811 | ||
1812 | memset(&ts, 0, sizeof(ts)); | |
daa5c408 | 1813 | ts.ts_status = ATH9K_TX_FLUSH; |
e8324357 | 1814 | INIT_LIST_HEAD(&bf_head); |
f078f209 | 1815 | |
fce041be FF |
1816 | while (!list_empty(list)) { |
1817 | bf = list_first_entry(list, struct ath_buf, list); | |
f078f209 | 1818 | |
50676b81 | 1819 | if (bf->bf_state.stale) { |
fce041be | 1820 | list_del(&bf->list); |
f078f209 | 1821 | |
fce041be FF |
1822 | ath_tx_return_buffer(sc, bf); |
1823 | continue; | |
e8324357 | 1824 | } |
f078f209 | 1825 | |
e8324357 | 1826 | lastbf = bf->bf_lastbf; |
fce041be | 1827 | list_cut_position(&bf_head, list, &lastbf->list); |
81b51950 | 1828 | ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); |
f078f209 | 1829 | } |
fce041be | 1830 | } |
f078f209 | 1831 | |
fce041be FF |
1832 | /* |
1833 | * Drain a given TX queue (could be Beacon or Data) | |
1834 | * | |
1835 | * This assumes output has been stopped and | |
1836 | * we do not need to block ath_tx_tasklet. | |
1837 | */ | |
1381559b | 1838 | void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq) |
fce041be | 1839 | { |
23de5dc9 FF |
1840 | ath_txq_lock(sc, txq); |
1841 | ||
e5003249 | 1842 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
fce041be | 1843 | int idx = txq->txq_tailidx; |
e5003249 | 1844 | |
fce041be | 1845 | while (!list_empty(&txq->txq_fifo[idx])) { |
1381559b | 1846 | ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]); |
fce041be FF |
1847 | |
1848 | INCR(idx, ATH_TXFIFO_DEPTH); | |
e5003249 | 1849 | } |
fce041be | 1850 | txq->txq_tailidx = idx; |
e5003249 | 1851 | } |
e609e2ea | 1852 | |
fce041be FF |
1853 | txq->axq_link = NULL; |
1854 | txq->axq_tx_inprogress = false; | |
1381559b | 1855 | ath_drain_txq_list(sc, txq, &txq->axq_q); |
fce041be | 1856 | |
23de5dc9 | 1857 | ath_txq_unlock_complete(sc, txq); |
f078f209 LR |
1858 | } |
1859 | ||
1381559b | 1860 | bool ath_drain_all_txq(struct ath_softc *sc) |
f078f209 | 1861 | { |
cbe61d8a | 1862 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1863 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
043a0405 | 1864 | struct ath_txq *txq; |
34d25810 FF |
1865 | int i; |
1866 | u32 npend = 0; | |
043a0405 | 1867 | |
eefa01dd | 1868 | if (test_bit(ATH_OP_INVALID, &common->op_flags)) |
080e1a25 | 1869 | return true; |
043a0405 | 1870 | |
0d51cccc | 1871 | ath9k_hw_abort_tx_dma(ah); |
043a0405 | 1872 | |
0d51cccc | 1873 | /* Check if any queue remains active */ |
043a0405 | 1874 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
0d51cccc FF |
1875 | if (!ATH_TXQ_SETUP(sc, i)) |
1876 | continue; | |
1877 | ||
10ffb6a7 FF |
1878 | if (!sc->tx.txq[i].axq_depth) |
1879 | continue; | |
1880 | ||
34d25810 FF |
1881 | if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum)) |
1882 | npend |= BIT(i); | |
043a0405 S |
1883 | } |
1884 | ||
080e1a25 | 1885 | if (npend) |
34d25810 | 1886 | ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend); |
043a0405 S |
1887 | |
1888 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
92460412 FF |
1889 | if (!ATH_TXQ_SETUP(sc, i)) |
1890 | continue; | |
1891 | ||
1892 | /* | |
1893 | * The caller will resume queues with ieee80211_wake_queues. | |
1894 | * Mark the queue as not stopped to prevent ath_tx_complete | |
1895 | * from waking the queue too early. | |
1896 | */ | |
1897 | txq = &sc->tx.txq[i]; | |
1898 | txq->stopped = false; | |
1381559b | 1899 | ath_draintxq(sc, txq); |
043a0405 | 1900 | } |
080e1a25 FF |
1901 | |
1902 | return !npend; | |
e8324357 | 1903 | } |
f078f209 | 1904 | |
043a0405 | 1905 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) |
e8324357 | 1906 | { |
043a0405 S |
1907 | ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum); |
1908 | sc->tx.txqsetup &= ~(1<<txq->axq_qnum); | |
e8324357 | 1909 | } |
f078f209 | 1910 | |
0453531e | 1911 | /* For each acq entry, for each tid, try to schedule packets |
7755bad9 BG |
1912 | * for transmit until ampdu_depth has reached min Q depth. |
1913 | */ | |
e8324357 S |
1914 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) |
1915 | { | |
eefa01dd | 1916 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
020f20f6 | 1917 | struct ath_atx_ac *ac, *last_ac; |
7755bad9 | 1918 | struct ath_atx_tid *tid, *last_tid; |
0453531e | 1919 | struct list_head *ac_list; |
020f20f6 | 1920 | bool sent = false; |
f078f209 | 1921 | |
0453531e FF |
1922 | if (txq->mac80211_qnum < 0) |
1923 | return; | |
1924 | ||
4d9f634b SM |
1925 | if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) |
1926 | return; | |
1927 | ||
bff11766 | 1928 | spin_lock_bh(&sc->chan_lock); |
0453531e FF |
1929 | ac_list = &sc->cur_chan->acq[txq->mac80211_qnum]; |
1930 | ||
4d9f634b SM |
1931 | if (list_empty(ac_list)) { |
1932 | spin_unlock_bh(&sc->chan_lock); | |
e8324357 | 1933 | return; |
4d9f634b | 1934 | } |
f078f209 | 1935 | |
23bc2021 FF |
1936 | rcu_read_lock(); |
1937 | ||
0453531e FF |
1938 | last_ac = list_entry(ac_list->prev, struct ath_atx_ac, list); |
1939 | while (!list_empty(ac_list)) { | |
020f20f6 | 1940 | bool stop = false; |
f078f209 | 1941 | |
bff11766 FF |
1942 | if (sc->cur_chan->stopped) |
1943 | break; | |
1944 | ||
0453531e | 1945 | ac = list_first_entry(ac_list, struct ath_atx_ac, list); |
7755bad9 BG |
1946 | last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list); |
1947 | list_del(&ac->list); | |
1948 | ac->sched = false; | |
f078f209 | 1949 | |
7755bad9 | 1950 | while (!list_empty(&ac->tid_q)) { |
020f20f6 | 1951 | |
7755bad9 BG |
1952 | tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, |
1953 | list); | |
1954 | list_del(&tid->list); | |
1955 | tid->sched = false; | |
f078f209 | 1956 | |
020f20f6 FF |
1957 | if (ath_tx_sched_aggr(sc, txq, tid, &stop)) |
1958 | sent = true; | |
f078f209 | 1959 | |
7755bad9 BG |
1960 | /* |
1961 | * add tid to round-robin queue if more frames | |
1962 | * are pending for the tid | |
1963 | */ | |
a7586ee4 | 1964 | if (ath_tid_has_buffered(tid)) |
0453531e | 1965 | ath_tx_queue_tid(sc, txq, tid); |
f078f209 | 1966 | |
020f20f6 | 1967 | if (stop || tid == last_tid) |
7755bad9 BG |
1968 | break; |
1969 | } | |
f078f209 | 1970 | |
b0477013 FF |
1971 | if (!list_empty(&ac->tid_q) && !ac->sched) { |
1972 | ac->sched = true; | |
0453531e | 1973 | list_add_tail(&ac->list, ac_list); |
f078f209 | 1974 | } |
7755bad9 | 1975 | |
020f20f6 | 1976 | if (stop) |
23bc2021 | 1977 | break; |
020f20f6 FF |
1978 | |
1979 | if (ac == last_ac) { | |
1980 | if (!sent) | |
1981 | break; | |
1982 | ||
1983 | sent = false; | |
0453531e | 1984 | last_ac = list_entry(ac_list->prev, |
020f20f6 FF |
1985 | struct ath_atx_ac, list); |
1986 | } | |
e8324357 | 1987 | } |
23bc2021 FF |
1988 | |
1989 | rcu_read_unlock(); | |
bff11766 | 1990 | spin_unlock_bh(&sc->chan_lock); |
e8324357 | 1991 | } |
f078f209 | 1992 | |
0453531e FF |
1993 | void ath_txq_schedule_all(struct ath_softc *sc) |
1994 | { | |
1995 | struct ath_txq *txq; | |
1996 | int i; | |
1997 | ||
1998 | for (i = 0; i < IEEE80211_NUM_ACS; i++) { | |
1999 | txq = sc->tx.txq_map[i]; | |
2000 | ||
2001 | spin_lock_bh(&txq->axq_lock); | |
2002 | ath_txq_schedule(sc, txq); | |
2003 | spin_unlock_bh(&txq->axq_lock); | |
2004 | } | |
2005 | } | |
2006 | ||
e8324357 S |
2007 | /***********/ |
2008 | /* TX, DMA */ | |
2009 | /***********/ | |
2010 | ||
f078f209 | 2011 | /* |
e8324357 S |
2012 | * Insert a chain of ath_buf (descriptors) on a txq and |
2013 | * assume the descriptors are already chained together by caller. | |
f078f209 | 2014 | */ |
e8324357 | 2015 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, |
fce041be | 2016 | struct list_head *head, bool internal) |
f078f209 | 2017 | { |
cbe61d8a | 2018 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 2019 | struct ath_common *common = ath9k_hw_common(ah); |
fce041be FF |
2020 | struct ath_buf *bf, *bf_last; |
2021 | bool puttxbuf = false; | |
2022 | bool edma; | |
f078f209 | 2023 | |
e8324357 S |
2024 | /* |
2025 | * Insert the frame on the outbound list and | |
2026 | * pass it on to the hardware. | |
2027 | */ | |
f078f209 | 2028 | |
e8324357 S |
2029 | if (list_empty(head)) |
2030 | return; | |
f078f209 | 2031 | |
fce041be | 2032 | edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); |
e8324357 | 2033 | bf = list_first_entry(head, struct ath_buf, list); |
fce041be | 2034 | bf_last = list_entry(head->prev, struct ath_buf, list); |
f078f209 | 2035 | |
d2182b69 JP |
2036 | ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n", |
2037 | txq->axq_qnum, txq->axq_depth); | |
f078f209 | 2038 | |
fce041be FF |
2039 | if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) { |
2040 | list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]); | |
e5003249 | 2041 | INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH); |
fce041be | 2042 | puttxbuf = true; |
e8324357 | 2043 | } else { |
e5003249 VT |
2044 | list_splice_tail_init(head, &txq->axq_q); |
2045 | ||
fce041be FF |
2046 | if (txq->axq_link) { |
2047 | ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr); | |
d2182b69 | 2048 | ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n", |
226afe68 JP |
2049 | txq->axq_qnum, txq->axq_link, |
2050 | ito64(bf->bf_daddr), bf->bf_desc); | |
fce041be FF |
2051 | } else if (!edma) |
2052 | puttxbuf = true; | |
2053 | ||
2054 | txq->axq_link = bf_last->bf_desc; | |
2055 | } | |
2056 | ||
2057 | if (puttxbuf) { | |
2058 | TX_STAT_INC(txq->axq_qnum, puttxbuf); | |
2059 | ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); | |
d2182b69 | 2060 | ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n", |
fce041be FF |
2061 | txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); |
2062 | } | |
2063 | ||
89f927af | 2064 | if (!edma || sc->tx99_state) { |
8d8d3fdc | 2065 | TX_STAT_INC(txq->axq_qnum, txstart); |
e5003249 | 2066 | ath9k_hw_txstart(ah, txq->axq_qnum); |
e8324357 | 2067 | } |
fce041be FF |
2068 | |
2069 | if (!internal) { | |
f56e121d FF |
2070 | while (bf) { |
2071 | txq->axq_depth++; | |
2072 | if (bf_is_ampdu_not_probing(bf)) | |
2073 | txq->axq_ampdu_depth++; | |
2074 | ||
440c1c87 FF |
2075 | bf_last = bf->bf_lastbf; |
2076 | bf = bf_last->bf_next; | |
2077 | bf_last->bf_next = NULL; | |
f56e121d | 2078 | } |
fce041be | 2079 | } |
e8324357 | 2080 | } |
f078f209 | 2081 | |
82b873af | 2082 | static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, |
44f1d26c | 2083 | struct ath_atx_tid *tid, struct sk_buff *skb) |
e8324357 | 2084 | { |
f69727fd | 2085 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
44f1d26c FF |
2086 | struct ath_frame_info *fi = get_frame_info(skb); |
2087 | struct list_head bf_head; | |
f69727fd | 2088 | struct ath_buf *bf = fi->bf; |
44f1d26c FF |
2089 | |
2090 | INIT_LIST_HEAD(&bf_head); | |
2091 | list_add_tail(&bf->list, &bf_head); | |
399c6489 | 2092 | bf->bf_state.bf_type = 0; |
f69727fd FF |
2093 | if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) { |
2094 | bf->bf_state.bf_type = BUF_AMPDU; | |
2095 | ath_tx_addto_baw(sc, tid, bf); | |
2096 | } | |
e8324357 | 2097 | |
8c6e3093 | 2098 | bf->bf_next = NULL; |
d43f3015 | 2099 | bf->bf_lastbf = bf; |
493cf04f | 2100 | ath_tx_fill_desc(sc, bf, txq, fi->framelen); |
44f1d26c | 2101 | ath_tx_txqaddbuf(sc, txq, &bf_head, false); |
fec247c0 | 2102 | TX_STAT_INC(txq->axq_qnum, queued); |
e8324357 S |
2103 | } |
2104 | ||
36323f81 TH |
2105 | static void setup_frame_info(struct ieee80211_hw *hw, |
2106 | struct ieee80211_sta *sta, | |
2107 | struct sk_buff *skb, | |
2d42efc4 | 2108 | int framelen) |
e8324357 S |
2109 | { |
2110 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
2d42efc4 | 2111 | struct ieee80211_key_conf *hw_key = tx_info->control.hw_key; |
6a0ddaef | 2112 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
80b08a8d | 2113 | const struct ieee80211_rate *rate; |
2d42efc4 | 2114 | struct ath_frame_info *fi = get_frame_info(skb); |
93ae2dd2 | 2115 | struct ath_node *an = NULL; |
2d42efc4 | 2116 | enum ath9k_key_type keytype; |
80b08a8d FF |
2117 | bool short_preamble = false; |
2118 | ||
2119 | /* | |
2120 | * We check if Short Preamble is needed for the CTS rate by | |
2121 | * checking the BSS's global flag. | |
2122 | * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used. | |
2123 | */ | |
2124 | if (tx_info->control.vif && | |
2125 | tx_info->control.vif->bss_conf.use_short_preamble) | |
2126 | short_preamble = true; | |
e8324357 | 2127 | |
80b08a8d | 2128 | rate = ieee80211_get_rts_cts_rate(hw, tx_info); |
2d42efc4 | 2129 | keytype = ath9k_cmn_get_hw_crypto_keytype(skb); |
e8324357 | 2130 | |
93ae2dd2 FF |
2131 | if (sta) |
2132 | an = (struct ath_node *) sta->drv_priv; | |
2133 | ||
2d42efc4 | 2134 | memset(fi, 0, sizeof(*fi)); |
d954cd77 | 2135 | fi->txq = -1; |
2d42efc4 FF |
2136 | if (hw_key) |
2137 | fi->keyix = hw_key->hw_key_idx; | |
93ae2dd2 FF |
2138 | else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0) |
2139 | fi->keyix = an->ps_key; | |
2d42efc4 FF |
2140 | else |
2141 | fi->keyix = ATH9K_TXKEYIX_INVALID; | |
2142 | fi->keytype = keytype; | |
2143 | fi->framelen = framelen; | |
8b537686 | 2144 | fi->tx_power = MAX_RATE_POWER; |
09b029b6 LR |
2145 | |
2146 | if (!rate) | |
2147 | return; | |
80b08a8d FF |
2148 | fi->rtscts_rate = rate->hw_value; |
2149 | if (short_preamble) | |
2150 | fi->rtscts_rate |= rate->hw_value_short; | |
e8324357 S |
2151 | } |
2152 | ||
ea066d5a MSS |
2153 | u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate) |
2154 | { | |
2155 | struct ath_hw *ah = sc->sc_ah; | |
2156 | struct ath9k_channel *curchan = ah->curchan; | |
365d2ebc | 2157 | |
8896934c | 2158 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) && |
d77bf3eb | 2159 | (chainmask == 0x7) && (rate < 0x90)) |
ea066d5a | 2160 | return 0x3; |
365d2ebc SM |
2161 | else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) && |
2162 | IS_CCK_RATE(rate)) | |
2163 | return 0x2; | |
ea066d5a MSS |
2164 | else |
2165 | return chainmask; | |
2166 | } | |
2167 | ||
44f1d26c FF |
2168 | /* |
2169 | * Assign a descriptor (and sequence number if necessary, | |
2170 | * and map buffer for DMA. Frees skb on error | |
2171 | */ | |
fa05f87a | 2172 | static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, |
04caf863 | 2173 | struct ath_txq *txq, |
fa05f87a | 2174 | struct ath_atx_tid *tid, |
249ee722 | 2175 | struct sk_buff *skb) |
f078f209 | 2176 | { |
82b873af | 2177 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
2d42efc4 | 2178 | struct ath_frame_info *fi = get_frame_info(skb); |
fa05f87a | 2179 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
82b873af | 2180 | struct ath_buf *bf; |
fd09c85f | 2181 | int fragno; |
fa05f87a | 2182 | u16 seqno; |
82b873af FF |
2183 | |
2184 | bf = ath_tx_get_buffer(sc); | |
2185 | if (!bf) { | |
d2182b69 | 2186 | ath_dbg(common, XMIT, "TX buffers are full\n"); |
249ee722 | 2187 | return NULL; |
82b873af | 2188 | } |
e022edbd | 2189 | |
528f0c6b | 2190 | ATH_TXBUF_RESET(bf); |
f078f209 | 2191 | |
5998be87 | 2192 | if (tid && ieee80211_is_data_present(hdr->frame_control)) { |
fd09c85f | 2193 | fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG; |
fa05f87a FF |
2194 | seqno = tid->seq_next; |
2195 | hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT); | |
fd09c85f SM |
2196 | |
2197 | if (fragno) | |
2198 | hdr->seq_ctrl |= cpu_to_le16(fragno); | |
2199 | ||
2200 | if (!ieee80211_has_morefrags(hdr->frame_control)) | |
2201 | INCR(tid->seq_next, IEEE80211_SEQ_MAX); | |
2202 | ||
fa05f87a FF |
2203 | bf->bf_state.seqno = seqno; |
2204 | } | |
2205 | ||
f078f209 | 2206 | bf->bf_mpdu = skb; |
f8316df1 | 2207 | |
c1739eb3 BG |
2208 | bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, |
2209 | skb->len, DMA_TO_DEVICE); | |
2210 | if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) { | |
f8316df1 | 2211 | bf->bf_mpdu = NULL; |
6cf9e995 | 2212 | bf->bf_buf_addr = 0; |
3800276a JP |
2213 | ath_err(ath9k_hw_common(sc->sc_ah), |
2214 | "dma_mapping_error() on TX\n"); | |
82b873af | 2215 | ath_tx_return_buffer(sc, bf); |
249ee722 | 2216 | return NULL; |
f8316df1 LR |
2217 | } |
2218 | ||
56dc6336 | 2219 | fi->bf = bf; |
04caf863 FF |
2220 | |
2221 | return bf; | |
2222 | } | |
2223 | ||
ca14405e SM |
2224 | void ath_assign_seq(struct ath_common *common, struct sk_buff *skb) |
2225 | { | |
2226 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
2227 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
2228 | struct ieee80211_vif *vif = info->control.vif; | |
2229 | struct ath_vif *avp; | |
2230 | ||
2231 | if (!(info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)) | |
2232 | return; | |
2233 | ||
2234 | if (!vif) | |
2235 | return; | |
2236 | ||
2237 | avp = (struct ath_vif *)vif->drv_priv; | |
2238 | ||
2239 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) | |
2240 | avp->seq_no += 0x10; | |
2241 | ||
2242 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); | |
2243 | hdr->seq_ctrl |= cpu_to_le16(avp->seq_no); | |
2244 | } | |
2245 | ||
59505c02 FF |
2246 | static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb, |
2247 | struct ath_tx_control *txctl) | |
f078f209 | 2248 | { |
28d16708 FF |
2249 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; |
2250 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
36323f81 | 2251 | struct ieee80211_sta *sta = txctl->sta; |
f59a59fe | 2252 | struct ieee80211_vif *vif = info->control.vif; |
f89d1bc4 | 2253 | struct ath_vif *avp; |
9ac58615 | 2254 | struct ath_softc *sc = hw->priv; |
04caf863 | 2255 | int frmlen = skb->len + FCS_LEN; |
59505c02 | 2256 | int padpos, padsize; |
f078f209 | 2257 | |
a9927ba3 BG |
2258 | /* NOTE: sta can be NULL according to net/mac80211.h */ |
2259 | if (sta) | |
2260 | txctl->an = (struct ath_node *)sta->drv_priv; | |
f89d1bc4 FF |
2261 | else if (vif && ieee80211_is_data(hdr->frame_control)) { |
2262 | avp = (void *)vif->drv_priv; | |
2263 | txctl->an = &avp->mcast_node; | |
2264 | } | |
a9927ba3 | 2265 | |
04caf863 FF |
2266 | if (info->control.hw_key) |
2267 | frmlen += info->control.hw_key->icv_len; | |
2268 | ||
ca14405e | 2269 | ath_assign_seq(ath9k_hw_common(sc->sc_ah), skb); |
f078f209 | 2270 | |
59505c02 FF |
2271 | if ((vif && vif->type != NL80211_IFTYPE_AP && |
2272 | vif->type != NL80211_IFTYPE_AP_VLAN) || | |
2273 | !ieee80211_is_data(hdr->frame_control)) | |
2274 | info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT; | |
2275 | ||
42cecc34 | 2276 | /* Add the padding after the header if this is not already done */ |
c60c9929 | 2277 | padpos = ieee80211_hdrlen(hdr->frame_control); |
42cecc34 JL |
2278 | padsize = padpos & 3; |
2279 | if (padsize && skb->len > padpos) { | |
2280 | if (skb_headroom(skb) < padsize) | |
2281 | return -ENOMEM; | |
28d16708 | 2282 | |
42cecc34 JL |
2283 | skb_push(skb, padsize); |
2284 | memmove(skb->data, skb->data + padsize, padpos); | |
f078f209 | 2285 | } |
f078f209 | 2286 | |
36323f81 | 2287 | setup_frame_info(hw, sta, skb, frmlen); |
59505c02 FF |
2288 | return 0; |
2289 | } | |
2290 | ||
2d42efc4 | 2291 | |
59505c02 FF |
2292 | /* Upon failure caller should free skb */ |
2293 | int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, | |
2294 | struct ath_tx_control *txctl) | |
2295 | { | |
2296 | struct ieee80211_hdr *hdr; | |
2297 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
2298 | struct ieee80211_sta *sta = txctl->sta; | |
2299 | struct ieee80211_vif *vif = info->control.vif; | |
d954cd77 | 2300 | struct ath_frame_info *fi = get_frame_info(skb); |
befcf7e7 | 2301 | struct ath_vif *avp = NULL; |
59505c02 FF |
2302 | struct ath_softc *sc = hw->priv; |
2303 | struct ath_txq *txq = txctl->txq; | |
2304 | struct ath_atx_tid *tid = NULL; | |
2305 | struct ath_buf *bf; | |
6b127c71 | 2306 | bool queue, skip_uapsd = false, ps_resp; |
d7017461 | 2307 | int q, ret; |
59505c02 | 2308 | |
befcf7e7 FF |
2309 | if (vif) |
2310 | avp = (void *)vif->drv_priv; | |
2311 | ||
405393cf FF |
2312 | if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN) |
2313 | txctl->force_channel = true; | |
2314 | ||
6b127c71 SM |
2315 | ps_resp = !!(info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE); |
2316 | ||
59505c02 FF |
2317 | ret = ath_tx_prepare(hw, skb, txctl); |
2318 | if (ret) | |
2319 | return ret; | |
2320 | ||
2321 | hdr = (struct ieee80211_hdr *) skb->data; | |
2d42efc4 FF |
2322 | /* |
2323 | * At this point, the vif, hw_key and sta pointers in the tx control | |
2324 | * info are no longer valid (overwritten by the ath_frame_info data. | |
2325 | */ | |
2326 | ||
28d16708 | 2327 | q = skb_get_queue_mapping(skb); |
23de5dc9 FF |
2328 | |
2329 | ath_txq_lock(sc, txq); | |
d954cd77 FF |
2330 | if (txq == sc->tx.txq_map[q]) { |
2331 | fi->txq = q; | |
2332 | if (++txq->pending_frames > sc->tx.txq_max_pending[q] && | |
2333 | !txq->stopped) { | |
868caae3 SM |
2334 | if (ath9k_is_chanctx_enabled()) |
2335 | ieee80211_stop_queue(sc->hw, info->hw_queue); | |
2336 | else | |
2337 | ieee80211_stop_queue(sc->hw, q); | |
d954cd77 FF |
2338 | txq->stopped = true; |
2339 | } | |
f078f209 | 2340 | } |
f078f209 | 2341 | |
befcf7e7 FF |
2342 | queue = ieee80211_is_data_present(hdr->frame_control); |
2343 | ||
2344 | /* Force queueing of all frames that belong to a virtual interface on | |
2345 | * a different channel context, to ensure that they are sent on the | |
2346 | * correct channel. | |
2347 | */ | |
2348 | if (((avp && avp->chanctx != sc->cur_chan) || | |
2349 | sc->cur_chan->stopped) && !txctl->force_channel) { | |
2350 | if (!txctl->an) | |
2351 | txctl->an = &avp->mcast_node; | |
befcf7e7 | 2352 | queue = true; |
8d9e464a | 2353 | skip_uapsd = true; |
befcf7e7 FF |
2354 | } |
2355 | ||
2356 | if (txctl->an && queue) | |
558ff225 FF |
2357 | tid = ath_get_skb_tid(sc, txctl->an, skb); |
2358 | ||
6b127c71 | 2359 | if (!skip_uapsd && ps_resp) { |
f2c7a793 FF |
2360 | ath_txq_unlock(sc, txq); |
2361 | txq = sc->tx.uapsdq; | |
2362 | ath_txq_lock(sc, txq); | |
befcf7e7 | 2363 | } else if (txctl->an && queue) { |
bdc21457 | 2364 | WARN_ON(tid->ac->txq != txctl->txq); |
bdc21457 | 2365 | |
2800e82b FF |
2366 | if (info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) |
2367 | tid->ac->clear_ps_filter = true; | |
2368 | ||
bdc21457 | 2369 | /* |
2800e82b FF |
2370 | * Add this frame to software queue for scheduling later |
2371 | * for aggregation. | |
bdc21457 | 2372 | */ |
2800e82b FF |
2373 | TX_STAT_INC(txq->axq_qnum, a_queued_sw); |
2374 | __skb_queue_tail(&tid->buf_q, skb); | |
2375 | if (!txctl->an->sleeping) | |
0453531e | 2376 | ath_tx_queue_tid(sc, txq, tid); |
2800e82b FF |
2377 | |
2378 | ath_txq_schedule(sc, txq); | |
bdc21457 FF |
2379 | goto out; |
2380 | } | |
2381 | ||
f2c7a793 | 2382 | bf = ath_tx_setup_buffer(sc, txq, tid, skb); |
bdc21457 | 2383 | if (!bf) { |
a4943ccb | 2384 | ath_txq_skb_done(sc, txq, skb); |
bdc21457 FF |
2385 | if (txctl->paprd) |
2386 | dev_kfree_skb_any(skb); | |
2387 | else | |
2388 | ieee80211_free_txskb(sc->hw, skb); | |
2389 | goto out; | |
2390 | } | |
2391 | ||
2392 | bf->bf_state.bfs_paprd = txctl->paprd; | |
2393 | ||
2394 | if (txctl->paprd) | |
2395 | bf->bf_state.bfs_paprd_timestamp = jiffies; | |
2396 | ||
79acac07 | 2397 | ath_set_rates(vif, sta, bf); |
f2c7a793 | 2398 | ath_tx_send_normal(sc, txq, tid, skb); |
3ad29529 | 2399 | |
bdc21457 | 2400 | out: |
23de5dc9 | 2401 | ath_txq_unlock(sc, txq); |
3ad29529 | 2402 | |
44f1d26c | 2403 | return 0; |
f078f209 LR |
2404 | } |
2405 | ||
59505c02 FF |
2406 | void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
2407 | struct sk_buff *skb) | |
2408 | { | |
2409 | struct ath_softc *sc = hw->priv; | |
2410 | struct ath_tx_control txctl = { | |
2411 | .txq = sc->beacon.cabq | |
2412 | }; | |
2413 | struct ath_tx_info info = {}; | |
2414 | struct ieee80211_hdr *hdr; | |
2415 | struct ath_buf *bf_tail = NULL; | |
2416 | struct ath_buf *bf; | |
2417 | LIST_HEAD(bf_q); | |
2418 | int duration = 0; | |
2419 | int max_duration; | |
2420 | ||
2421 | max_duration = | |
ca900ac9 RM |
2422 | sc->cur_chan->beacon.beacon_interval * 1000 * |
2423 | sc->cur_chan->beacon.dtim_period / ATH_BCBUF; | |
59505c02 FF |
2424 | |
2425 | do { | |
2426 | struct ath_frame_info *fi = get_frame_info(skb); | |
2427 | ||
2428 | if (ath_tx_prepare(hw, skb, &txctl)) | |
2429 | break; | |
2430 | ||
2431 | bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb); | |
2432 | if (!bf) | |
2433 | break; | |
2434 | ||
2435 | bf->bf_lastbf = bf; | |
2436 | ath_set_rates(vif, NULL, bf); | |
a3835e9f | 2437 | ath_buf_set_rate(sc, bf, &info, fi->framelen, false); |
59505c02 FF |
2438 | duration += info.rates[0].PktDuration; |
2439 | if (bf_tail) | |
2440 | bf_tail->bf_next = bf; | |
2441 | ||
2442 | list_add_tail(&bf->list, &bf_q); | |
2443 | bf_tail = bf; | |
2444 | skb = NULL; | |
2445 | ||
2446 | if (duration > max_duration) | |
2447 | break; | |
2448 | ||
2449 | skb = ieee80211_get_buffered_bc(hw, vif); | |
2450 | } while(skb); | |
2451 | ||
2452 | if (skb) | |
2453 | ieee80211_free_txskb(hw, skb); | |
2454 | ||
2455 | if (list_empty(&bf_q)) | |
2456 | return; | |
2457 | ||
2458 | bf = list_first_entry(&bf_q, struct ath_buf, list); | |
2459 | hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data; | |
2460 | ||
2461 | if (hdr->frame_control & IEEE80211_FCTL_MOREDATA) { | |
2462 | hdr->frame_control &= ~IEEE80211_FCTL_MOREDATA; | |
2463 | dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, | |
2464 | sizeof(*hdr), DMA_TO_DEVICE); | |
2465 | } | |
2466 | ||
2467 | ath_txq_lock(sc, txctl.txq); | |
2468 | ath_tx_fill_desc(sc, bf, txctl.txq, 0); | |
2469 | ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false); | |
2470 | TX_STAT_INC(txctl.txq->axq_qnum, queued); | |
2471 | ath_txq_unlock(sc, txctl.txq); | |
2472 | } | |
2473 | ||
e8324357 S |
2474 | /*****************/ |
2475 | /* TX Completion */ | |
2476 | /*****************/ | |
528f0c6b | 2477 | |
e8324357 | 2478 | static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, |
0f9dc298 | 2479 | int tx_flags, struct ath_txq *txq) |
528f0c6b | 2480 | { |
e8324357 | 2481 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
c46917bb | 2482 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
4d91f9f3 | 2483 | struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data; |
a4943ccb | 2484 | int padpos, padsize; |
07c15a3f | 2485 | unsigned long flags; |
528f0c6b | 2486 | |
d2182b69 | 2487 | ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb); |
528f0c6b | 2488 | |
51dea9be | 2489 | if (sc->sc_ah->caldata) |
4b9b42bf | 2490 | set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags); |
51dea9be | 2491 | |
55797b1a | 2492 | if (!(tx_flags & ATH_TX_ERROR)) |
e8324357 S |
2493 | /* Frame was ACKed */ |
2494 | tx_info->flags |= IEEE80211_TX_STAT_ACK; | |
528f0c6b | 2495 | |
c60c9929 | 2496 | padpos = ieee80211_hdrlen(hdr->frame_control); |
42cecc34 JL |
2497 | padsize = padpos & 3; |
2498 | if (padsize && skb->len>padpos+padsize) { | |
2499 | /* | |
2500 | * Remove MAC header padding before giving the frame back to | |
2501 | * mac80211. | |
2502 | */ | |
2503 | memmove(skb->data + padsize, skb->data, padpos); | |
2504 | skb_pull(skb, padsize); | |
e8324357 | 2505 | } |
528f0c6b | 2506 | |
07c15a3f | 2507 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
c8e8868e | 2508 | if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) { |
1b04b930 | 2509 | sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK; |
d2182b69 | 2510 | ath_dbg(common, PS, |
226afe68 | 2511 | "Going back to sleep after having received TX status (0x%lx)\n", |
1b04b930 S |
2512 | sc->ps_flags & (PS_WAIT_FOR_BEACON | |
2513 | PS_WAIT_FOR_CAB | | |
2514 | PS_WAIT_FOR_PSPOLL_DATA | | |
2515 | PS_WAIT_FOR_TX_ACK)); | |
9a23f9ca | 2516 | } |
07c15a3f | 2517 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
9a23f9ca | 2518 | |
f2c7a793 | 2519 | __skb_queue_tail(&txq->complete_q, skb); |
a4943ccb | 2520 | ath_txq_skb_done(sc, txq, skb); |
e8324357 | 2521 | } |
f078f209 | 2522 | |
e8324357 | 2523 | static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, |
db1a052b | 2524 | struct ath_txq *txq, struct list_head *bf_q, |
156369fa | 2525 | struct ath_tx_status *ts, int txok) |
f078f209 | 2526 | { |
e8324357 | 2527 | struct sk_buff *skb = bf->bf_mpdu; |
3afd21e7 | 2528 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
e8324357 | 2529 | unsigned long flags; |
6b2c4032 | 2530 | int tx_flags = 0; |
f078f209 | 2531 | |
55797b1a | 2532 | if (!txok) |
6b2c4032 | 2533 | tx_flags |= ATH_TX_ERROR; |
f078f209 | 2534 | |
3afd21e7 FF |
2535 | if (ts->ts_status & ATH9K_TXERR_FILT) |
2536 | tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; | |
2537 | ||
c1739eb3 | 2538 | dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE); |
6cf9e995 | 2539 | bf->bf_buf_addr = 0; |
89f927af LR |
2540 | if (sc->tx99_state) |
2541 | goto skip_tx_complete; | |
9f42c2b6 FF |
2542 | |
2543 | if (bf->bf_state.bfs_paprd) { | |
9cf04dcc MSS |
2544 | if (time_after(jiffies, |
2545 | bf->bf_state.bfs_paprd_timestamp + | |
2546 | msecs_to_jiffies(ATH_PAPRD_TIMEOUT))) | |
ca369eb4 | 2547 | dev_kfree_skb_any(skb); |
78a18172 | 2548 | else |
ca369eb4 | 2549 | complete(&sc->paprd_complete); |
9f42c2b6 | 2550 | } else { |
55797b1a | 2551 | ath_debug_stat_tx(sc, bf, ts, txq, tx_flags); |
0f9dc298 | 2552 | ath_tx_complete(sc, skb, tx_flags, txq); |
9f42c2b6 | 2553 | } |
89f927af | 2554 | skip_tx_complete: |
6cf9e995 BG |
2555 | /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't |
2556 | * accidentally reference it later. | |
2557 | */ | |
2558 | bf->bf_mpdu = NULL; | |
e8324357 S |
2559 | |
2560 | /* | |
2561 | * Return the list of ath_buf of this mpdu to free queue | |
2562 | */ | |
2563 | spin_lock_irqsave(&sc->tx.txbuflock, flags); | |
2564 | list_splice_tail_init(bf_q, &sc->tx.txbuf); | |
2565 | spin_unlock_irqrestore(&sc->tx.txbuflock, flags); | |
f078f209 LR |
2566 | } |
2567 | ||
0cdd5c60 FF |
2568 | static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, |
2569 | struct ath_tx_status *ts, int nframes, int nbad, | |
3afd21e7 | 2570 | int txok) |
f078f209 | 2571 | { |
a22be22a | 2572 | struct sk_buff *skb = bf->bf_mpdu; |
254ad0ff | 2573 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
e8324357 | 2574 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
0cdd5c60 | 2575 | struct ieee80211_hw *hw = sc->hw; |
f0c255a0 | 2576 | struct ath_hw *ah = sc->sc_ah; |
8a92e2ee | 2577 | u8 i, tx_rateindex; |
f078f209 | 2578 | |
95e4acb7 | 2579 | if (txok) |
db1a052b | 2580 | tx_info->status.ack_signal = ts->ts_rssi; |
95e4acb7 | 2581 | |
db1a052b | 2582 | tx_rateindex = ts->ts_rateindex; |
8a92e2ee VT |
2583 | WARN_ON(tx_rateindex >= hw->max_rates); |
2584 | ||
3afd21e7 | 2585 | if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { |
d969847c | 2586 | tx_info->flags |= IEEE80211_TX_STAT_AMPDU; |
f078f209 | 2587 | |
b572d033 | 2588 | BUG_ON(nbad > nframes); |
ebd02287 | 2589 | } |
185d1589 RM |
2590 | tx_info->status.ampdu_len = nframes; |
2591 | tx_info->status.ampdu_ack_len = nframes - nbad; | |
ebd02287 | 2592 | |
db1a052b | 2593 | if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 && |
3afd21e7 | 2594 | (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) { |
f0c255a0 FF |
2595 | /* |
2596 | * If an underrun error is seen assume it as an excessive | |
2597 | * retry only if max frame trigger level has been reached | |
2598 | * (2 KB for single stream, and 4 KB for dual stream). | |
2599 | * Adjust the long retry as if the frame was tried | |
2600 | * hw->max_rate_tries times to affect how rate control updates | |
2601 | * PER for the failed rate. | |
2602 | * In case of congestion on the bus penalizing this type of | |
2603 | * underruns should help hardware actually transmit new frames | |
2604 | * successfully by eventually preferring slower rates. | |
2605 | * This itself should also alleviate congestion on the bus. | |
2606 | */ | |
3afd21e7 FF |
2607 | if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN | |
2608 | ATH9K_TX_DELIM_UNDERRUN)) && | |
2609 | ieee80211_is_data(hdr->frame_control) && | |
83860c59 | 2610 | ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level) |
f0c255a0 FF |
2611 | tx_info->status.rates[tx_rateindex].count = |
2612 | hw->max_rate_tries; | |
f078f209 | 2613 | } |
8a92e2ee | 2614 | |
545750d3 | 2615 | for (i = tx_rateindex + 1; i < hw->max_rates; i++) { |
8a92e2ee | 2616 | tx_info->status.rates[i].count = 0; |
545750d3 FF |
2617 | tx_info->status.rates[i].idx = -1; |
2618 | } | |
8a92e2ee | 2619 | |
78c4653a | 2620 | tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1; |
f078f209 LR |
2621 | } |
2622 | ||
e8324357 | 2623 | static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) |
f078f209 | 2624 | { |
cbe61d8a | 2625 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 2626 | struct ath_common *common = ath9k_hw_common(ah); |
e8324357 | 2627 | struct ath_buf *bf, *lastbf, *bf_held = NULL; |
f078f209 | 2628 | struct list_head bf_head; |
e8324357 | 2629 | struct ath_desc *ds; |
29bffa96 | 2630 | struct ath_tx_status ts; |
e8324357 | 2631 | int status; |
f078f209 | 2632 | |
d2182b69 | 2633 | ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n", |
226afe68 JP |
2634 | txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), |
2635 | txq->axq_link); | |
f078f209 | 2636 | |
23de5dc9 | 2637 | ath_txq_lock(sc, txq); |
f078f209 | 2638 | for (;;) { |
eefa01dd | 2639 | if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) |
236de514 FF |
2640 | break; |
2641 | ||
f078f209 LR |
2642 | if (list_empty(&txq->axq_q)) { |
2643 | txq->axq_link = NULL; | |
73364b0c | 2644 | ath_txq_schedule(sc, txq); |
f078f209 LR |
2645 | break; |
2646 | } | |
f078f209 LR |
2647 | bf = list_first_entry(&txq->axq_q, struct ath_buf, list); |
2648 | ||
e8324357 S |
2649 | /* |
2650 | * There is a race condition that a BH gets scheduled | |
2651 | * after sw writes TxE and before hw re-load the last | |
2652 | * descriptor to get the newly chained one. | |
2653 | * Software must keep the last DONE descriptor as a | |
2654 | * holding descriptor - software does so by marking | |
2655 | * it with the STALE flag. | |
2656 | */ | |
2657 | bf_held = NULL; | |
50676b81 | 2658 | if (bf->bf_state.stale) { |
e8324357 | 2659 | bf_held = bf; |
fce041be | 2660 | if (list_is_last(&bf_held->list, &txq->axq_q)) |
e8324357 | 2661 | break; |
fce041be FF |
2662 | |
2663 | bf = list_entry(bf_held->list.next, struct ath_buf, | |
2664 | list); | |
f078f209 LR |
2665 | } |
2666 | ||
2667 | lastbf = bf->bf_lastbf; | |
e8324357 | 2668 | ds = lastbf->bf_desc; |
f078f209 | 2669 | |
29bffa96 FF |
2670 | memset(&ts, 0, sizeof(ts)); |
2671 | status = ath9k_hw_txprocdesc(ah, ds, &ts); | |
fce041be | 2672 | if (status == -EINPROGRESS) |
e8324357 | 2673 | break; |
fce041be | 2674 | |
2dac4fb9 | 2675 | TX_STAT_INC(txq->axq_qnum, txprocdesc); |
f078f209 | 2676 | |
e8324357 S |
2677 | /* |
2678 | * Remove ath_buf's of the same transmit unit from txq, | |
2679 | * however leave the last descriptor back as the holding | |
2680 | * descriptor for hw. | |
2681 | */ | |
50676b81 | 2682 | lastbf->bf_state.stale = true; |
e8324357 | 2683 | INIT_LIST_HEAD(&bf_head); |
e8324357 S |
2684 | if (!list_is_singular(&lastbf->list)) |
2685 | list_cut_position(&bf_head, | |
2686 | &txq->axq_q, lastbf->list.prev); | |
f078f209 | 2687 | |
fce041be | 2688 | if (bf_held) { |
0a8cea84 | 2689 | list_del(&bf_held->list); |
0a8cea84 | 2690 | ath_tx_return_buffer(sc, bf_held); |
e8324357 | 2691 | } |
f078f209 | 2692 | |
fce041be | 2693 | ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); |
8469cdef | 2694 | } |
23de5dc9 | 2695 | ath_txq_unlock_complete(sc, txq); |
8469cdef S |
2696 | } |
2697 | ||
e8324357 | 2698 | void ath_tx_tasklet(struct ath_softc *sc) |
f078f209 | 2699 | { |
239c795d FF |
2700 | struct ath_hw *ah = sc->sc_ah; |
2701 | u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs; | |
e8324357 | 2702 | int i; |
f078f209 | 2703 | |
e8324357 S |
2704 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
2705 | if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i))) | |
2706 | ath_tx_processq(sc, &sc->tx.txq[i]); | |
f078f209 LR |
2707 | } |
2708 | } | |
2709 | ||
e5003249 VT |
2710 | void ath_tx_edma_tasklet(struct ath_softc *sc) |
2711 | { | |
fce041be | 2712 | struct ath_tx_status ts; |
e5003249 VT |
2713 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
2714 | struct ath_hw *ah = sc->sc_ah; | |
2715 | struct ath_txq *txq; | |
2716 | struct ath_buf *bf, *lastbf; | |
2717 | struct list_head bf_head; | |
99ba6a46 | 2718 | struct list_head *fifo_list; |
e5003249 | 2719 | int status; |
e5003249 VT |
2720 | |
2721 | for (;;) { | |
eefa01dd | 2722 | if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) |
236de514 FF |
2723 | break; |
2724 | ||
fce041be | 2725 | status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts); |
e5003249 VT |
2726 | if (status == -EINPROGRESS) |
2727 | break; | |
2728 | if (status == -EIO) { | |
d2182b69 | 2729 | ath_dbg(common, XMIT, "Error processing tx status\n"); |
e5003249 VT |
2730 | break; |
2731 | } | |
2732 | ||
4e0ad259 FF |
2733 | /* Process beacon completions separately */ |
2734 | if (ts.qid == sc->beacon.beaconq) { | |
2735 | sc->beacon.tx_processed = true; | |
2736 | sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); | |
d074e8d5 | 2737 | |
27babf9f SM |
2738 | if (ath9k_is_chanctx_enabled()) { |
2739 | ath_chanctx_event(sc, NULL, | |
2740 | ATH_CHANCTX_EVENT_BEACON_SENT); | |
2741 | } | |
2742 | ||
4effc6fd | 2743 | ath9k_csa_update(sc); |
e5003249 | 2744 | continue; |
4e0ad259 | 2745 | } |
e5003249 | 2746 | |
fce041be | 2747 | txq = &sc->tx.txq[ts.qid]; |
e5003249 | 2748 | |
23de5dc9 | 2749 | ath_txq_lock(sc, txq); |
fce041be | 2750 | |
78ef731c SM |
2751 | TX_STAT_INC(txq->axq_qnum, txprocdesc); |
2752 | ||
99ba6a46 FF |
2753 | fifo_list = &txq->txq_fifo[txq->txq_tailidx]; |
2754 | if (list_empty(fifo_list)) { | |
23de5dc9 | 2755 | ath_txq_unlock(sc, txq); |
e5003249 VT |
2756 | return; |
2757 | } | |
2758 | ||
99ba6a46 | 2759 | bf = list_first_entry(fifo_list, struct ath_buf, list); |
50676b81 | 2760 | if (bf->bf_state.stale) { |
99ba6a46 FF |
2761 | list_del(&bf->list); |
2762 | ath_tx_return_buffer(sc, bf); | |
2763 | bf = list_first_entry(fifo_list, struct ath_buf, list); | |
2764 | } | |
2765 | ||
e5003249 VT |
2766 | lastbf = bf->bf_lastbf; |
2767 | ||
2768 | INIT_LIST_HEAD(&bf_head); | |
99ba6a46 FF |
2769 | if (list_is_last(&lastbf->list, fifo_list)) { |
2770 | list_splice_tail_init(fifo_list, &bf_head); | |
fce041be | 2771 | INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH); |
e5003249 | 2772 | |
fce041be FF |
2773 | if (!list_empty(&txq->axq_q)) { |
2774 | struct list_head bf_q; | |
60f2d1d5 | 2775 | |
fce041be FF |
2776 | INIT_LIST_HEAD(&bf_q); |
2777 | txq->axq_link = NULL; | |
2778 | list_splice_tail_init(&txq->axq_q, &bf_q); | |
2779 | ath_tx_txqaddbuf(sc, txq, &bf_q, true); | |
2780 | } | |
99ba6a46 | 2781 | } else { |
50676b81 | 2782 | lastbf->bf_state.stale = true; |
99ba6a46 FF |
2783 | if (bf != lastbf) |
2784 | list_cut_position(&bf_head, fifo_list, | |
2785 | lastbf->list.prev); | |
fce041be | 2786 | } |
86271e46 | 2787 | |
fce041be | 2788 | ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); |
23de5dc9 | 2789 | ath_txq_unlock_complete(sc, txq); |
e5003249 VT |
2790 | } |
2791 | } | |
2792 | ||
e8324357 S |
2793 | /*****************/ |
2794 | /* Init, Cleanup */ | |
2795 | /*****************/ | |
f078f209 | 2796 | |
5088c2f1 VT |
2797 | static int ath_txstatus_setup(struct ath_softc *sc, int size) |
2798 | { | |
2799 | struct ath_descdma *dd = &sc->txsdma; | |
2800 | u8 txs_len = sc->sc_ah->caps.txs_len; | |
2801 | ||
2802 | dd->dd_desc_len = size * txs_len; | |
b81950b1 FF |
2803 | dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len, |
2804 | &dd->dd_desc_paddr, GFP_KERNEL); | |
5088c2f1 VT |
2805 | if (!dd->dd_desc) |
2806 | return -ENOMEM; | |
2807 | ||
2808 | return 0; | |
2809 | } | |
2810 | ||
2811 | static int ath_tx_edma_init(struct ath_softc *sc) | |
2812 | { | |
2813 | int err; | |
2814 | ||
2815 | err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE); | |
2816 | if (!err) | |
2817 | ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc, | |
2818 | sc->txsdma.dd_desc_paddr, | |
2819 | ATH_TXSTATUS_RING_SIZE); | |
2820 | ||
2821 | return err; | |
2822 | } | |
2823 | ||
e8324357 | 2824 | int ath_tx_init(struct ath_softc *sc, int nbufs) |
f078f209 | 2825 | { |
c46917bb | 2826 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
e8324357 | 2827 | int error = 0; |
f078f209 | 2828 | |
797fe5cb | 2829 | spin_lock_init(&sc->tx.txbuflock); |
f078f209 | 2830 | |
797fe5cb | 2831 | error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, |
4adfcded | 2832 | "tx", nbufs, 1, 1); |
797fe5cb | 2833 | if (error != 0) { |
3800276a JP |
2834 | ath_err(common, |
2835 | "Failed to allocate tx descriptors: %d\n", error); | |
b81950b1 | 2836 | return error; |
797fe5cb | 2837 | } |
f078f209 | 2838 | |
797fe5cb | 2839 | error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, |
5088c2f1 | 2840 | "beacon", ATH_BCBUF, 1, 1); |
797fe5cb | 2841 | if (error != 0) { |
3800276a JP |
2842 | ath_err(common, |
2843 | "Failed to allocate beacon descriptors: %d\n", error); | |
b81950b1 | 2844 | return error; |
797fe5cb | 2845 | } |
f078f209 | 2846 | |
164ace38 SB |
2847 | INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work); |
2848 | ||
b81950b1 | 2849 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
5088c2f1 | 2850 | error = ath_tx_edma_init(sc); |
f078f209 | 2851 | |
e8324357 | 2852 | return error; |
f078f209 LR |
2853 | } |
2854 | ||
f078f209 LR |
2855 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an) |
2856 | { | |
c5170163 S |
2857 | struct ath_atx_tid *tid; |
2858 | struct ath_atx_ac *ac; | |
2859 | int tidno, acno; | |
f078f209 | 2860 | |
8ee5afbc | 2861 | for (tidno = 0, tid = &an->tid[tidno]; |
de7b7604 | 2862 | tidno < IEEE80211_NUM_TIDS; |
c5170163 S |
2863 | tidno++, tid++) { |
2864 | tid->an = an; | |
2865 | tid->tidno = tidno; | |
2866 | tid->seq_start = tid->seq_next = 0; | |
2867 | tid->baw_size = WME_MAX_BA; | |
2868 | tid->baw_head = tid->baw_tail = 0; | |
2869 | tid->sched = false; | |
08c96abd | 2870 | tid->active = false; |
56dc6336 | 2871 | __skb_queue_head_init(&tid->buf_q); |
bb195ff6 | 2872 | __skb_queue_head_init(&tid->retry_q); |
c5170163 | 2873 | acno = TID_TO_WME_AC(tidno); |
8ee5afbc | 2874 | tid->ac = &an->ac[acno]; |
c5170163 | 2875 | } |
f078f209 | 2876 | |
8ee5afbc | 2877 | for (acno = 0, ac = &an->ac[acno]; |
bea843c7 | 2878 | acno < IEEE80211_NUM_ACS; acno++, ac++) { |
c5170163 | 2879 | ac->sched = false; |
026d5b07 | 2880 | ac->clear_ps_filter = true; |
066dae93 | 2881 | ac->txq = sc->tx.txq_map[acno]; |
c5170163 | 2882 | INIT_LIST_HEAD(&ac->tid_q); |
f078f209 LR |
2883 | } |
2884 | } | |
2885 | ||
b5aa9bf9 | 2886 | void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an) |
f078f209 | 2887 | { |
2b40994c FF |
2888 | struct ath_atx_ac *ac; |
2889 | struct ath_atx_tid *tid; | |
f078f209 | 2890 | struct ath_txq *txq; |
066dae93 | 2891 | int tidno; |
e8324357 | 2892 | |
2b40994c | 2893 | for (tidno = 0, tid = &an->tid[tidno]; |
de7b7604 | 2894 | tidno < IEEE80211_NUM_TIDS; tidno++, tid++) { |
f078f209 | 2895 | |
2b40994c | 2896 | ac = tid->ac; |
066dae93 | 2897 | txq = ac->txq; |
f078f209 | 2898 | |
23de5dc9 | 2899 | ath_txq_lock(sc, txq); |
2b40994c FF |
2900 | |
2901 | if (tid->sched) { | |
2902 | list_del(&tid->list); | |
2903 | tid->sched = false; | |
2904 | } | |
2905 | ||
2906 | if (ac->sched) { | |
2907 | list_del(&ac->list); | |
2908 | tid->ac->sched = false; | |
f078f209 | 2909 | } |
2b40994c FF |
2910 | |
2911 | ath_tid_drain(sc, txq, tid); | |
08c96abd | 2912 | tid->active = false; |
2b40994c | 2913 | |
23de5dc9 | 2914 | ath_txq_unlock(sc, txq); |
f078f209 LR |
2915 | } |
2916 | } | |
89f927af | 2917 | |
ef6b19e4 SM |
2918 | #ifdef CONFIG_ATH9K_TX99 |
2919 | ||
89f927af LR |
2920 | int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb, |
2921 | struct ath_tx_control *txctl) | |
2922 | { | |
2923 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
2924 | struct ath_frame_info *fi = get_frame_info(skb); | |
2925 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
2926 | struct ath_buf *bf; | |
2927 | int padpos, padsize; | |
2928 | ||
2929 | padpos = ieee80211_hdrlen(hdr->frame_control); | |
2930 | padsize = padpos & 3; | |
2931 | ||
2932 | if (padsize && skb->len > padpos) { | |
2933 | if (skb_headroom(skb) < padsize) { | |
2934 | ath_dbg(common, XMIT, | |
2935 | "tx99 padding failed\n"); | |
2936 | return -EINVAL; | |
2937 | } | |
2938 | ||
2939 | skb_push(skb, padsize); | |
2940 | memmove(skb->data, skb->data + padsize, padpos); | |
2941 | } | |
2942 | ||
2943 | fi->keyix = ATH9K_TXKEYIX_INVALID; | |
2944 | fi->framelen = skb->len + FCS_LEN; | |
2945 | fi->keytype = ATH9K_KEY_TYPE_CLEAR; | |
2946 | ||
2947 | bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb); | |
2948 | if (!bf) { | |
2949 | ath_dbg(common, XMIT, "tx99 buffer setup failed\n"); | |
2950 | return -EINVAL; | |
2951 | } | |
2952 | ||
2953 | ath_set_rates(sc->tx99_vif, NULL, bf); | |
2954 | ||
2955 | ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr); | |
2956 | ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum); | |
2957 | ||
2958 | ath_tx_send_normal(sc, txctl->txq, NULL, skb); | |
2959 | ||
2960 | return 0; | |
2961 | } | |
ef6b19e4 SM |
2962 | |
2963 | #endif /* CONFIG_ATH9K_TX99 */ |