Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
b7f080cf | 17 | #include <linux/dma-mapping.h> |
394cf0a1 | 18 | #include "ath9k.h" |
b622a720 | 19 | #include "ar9003_mac.h" |
f078f209 LR |
20 | |
21 | #define BITS_PER_BYTE 8 | |
22 | #define OFDM_PLCP_BITS 22 | |
f078f209 LR |
23 | #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) |
24 | #define L_STF 8 | |
25 | #define L_LTF 8 | |
26 | #define L_SIG 4 | |
27 | #define HT_SIG 8 | |
28 | #define HT_STF 4 | |
29 | #define HT_LTF(_ns) (4 * (_ns)) | |
30 | #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */ | |
31 | #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */ | |
32 | #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) | |
33 | #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) | |
34 | ||
f078f209 | 35 | |
c6663876 | 36 | static u16 bits_per_symbol[][2] = { |
f078f209 LR |
37 | /* 20MHz 40MHz */ |
38 | { 26, 54 }, /* 0: BPSK */ | |
39 | { 52, 108 }, /* 1: QPSK 1/2 */ | |
40 | { 78, 162 }, /* 2: QPSK 3/4 */ | |
41 | { 104, 216 }, /* 3: 16-QAM 1/2 */ | |
42 | { 156, 324 }, /* 4: 16-QAM 3/4 */ | |
43 | { 208, 432 }, /* 5: 64-QAM 2/3 */ | |
44 | { 234, 486 }, /* 6: 64-QAM 3/4 */ | |
45 | { 260, 540 }, /* 7: 64-QAM 5/6 */ | |
f078f209 LR |
46 | }; |
47 | ||
48 | #define IS_HT_RATE(_rate) ((_rate) & 0x80) | |
49 | ||
82b873af | 50 | static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, |
44f1d26c FF |
51 | struct ath_atx_tid *tid, struct sk_buff *skb); |
52 | static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, | |
53 | int tx_flags, struct ath_txq *txq); | |
e8324357 | 54 | static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, |
db1a052b | 55 | struct ath_txq *txq, struct list_head *bf_q, |
156369fa | 56 | struct ath_tx_status *ts, int txok); |
102e0572 | 57 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, |
fce041be | 58 | struct list_head *head, bool internal); |
0cdd5c60 FF |
59 | static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, |
60 | struct ath_tx_status *ts, int nframes, int nbad, | |
3afd21e7 | 61 | int txok); |
90fa539c FF |
62 | static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
63 | int seqno); | |
44f1d26c FF |
64 | static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, |
65 | struct ath_txq *txq, | |
66 | struct ath_atx_tid *tid, | |
67 | struct sk_buff *skb); | |
c4288390 | 68 | |
545750d3 | 69 | enum { |
0e668cde FF |
70 | MCS_HT20, |
71 | MCS_HT20_SGI, | |
545750d3 FF |
72 | MCS_HT40, |
73 | MCS_HT40_SGI, | |
74 | }; | |
75 | ||
0e668cde FF |
76 | static int ath_max_4ms_framelen[4][32] = { |
77 | [MCS_HT20] = { | |
78 | 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172, | |
79 | 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280, | |
80 | 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532, | |
81 | 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532, | |
82 | }, | |
83 | [MCS_HT20_SGI] = { | |
84 | 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744, | |
85 | 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532, | |
86 | 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532, | |
87 | 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532, | |
545750d3 FF |
88 | }, |
89 | [MCS_HT40] = { | |
0e668cde FF |
90 | 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532, |
91 | 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532, | |
92 | 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532, | |
93 | 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532, | |
545750d3 FF |
94 | }, |
95 | [MCS_HT40_SGI] = { | |
0e668cde FF |
96 | 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532, |
97 | 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532, | |
98 | 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532, | |
99 | 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532, | |
545750d3 FF |
100 | } |
101 | }; | |
102 | ||
e8324357 S |
103 | /*********************/ |
104 | /* Aggregation logic */ | |
105 | /*********************/ | |
f078f209 | 106 | |
23de5dc9 | 107 | static void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq) |
1512a486 | 108 | __acquires(&txq->axq_lock) |
23de5dc9 FF |
109 | { |
110 | spin_lock_bh(&txq->axq_lock); | |
111 | } | |
112 | ||
113 | static void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq) | |
1512a486 | 114 | __releases(&txq->axq_lock) |
23de5dc9 FF |
115 | { |
116 | spin_unlock_bh(&txq->axq_lock); | |
117 | } | |
118 | ||
119 | static void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq) | |
1512a486 | 120 | __releases(&txq->axq_lock) |
23de5dc9 FF |
121 | { |
122 | struct sk_buff_head q; | |
123 | struct sk_buff *skb; | |
124 | ||
125 | __skb_queue_head_init(&q); | |
126 | skb_queue_splice_init(&txq->complete_q, &q); | |
127 | spin_unlock_bh(&txq->axq_lock); | |
128 | ||
129 | while ((skb = __skb_dequeue(&q))) | |
130 | ieee80211_tx_status(sc->hw, skb); | |
131 | } | |
132 | ||
e8324357 | 133 | static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid) |
ff37e337 | 134 | { |
e8324357 | 135 | struct ath_atx_ac *ac = tid->ac; |
ff37e337 | 136 | |
e8324357 S |
137 | if (tid->paused) |
138 | return; | |
ff37e337 | 139 | |
e8324357 S |
140 | if (tid->sched) |
141 | return; | |
ff37e337 | 142 | |
e8324357 S |
143 | tid->sched = true; |
144 | list_add_tail(&tid->list, &ac->tid_q); | |
528f0c6b | 145 | |
e8324357 S |
146 | if (ac->sched) |
147 | return; | |
f078f209 | 148 | |
e8324357 S |
149 | ac->sched = true; |
150 | list_add_tail(&ac->list, &txq->axq_acq); | |
151 | } | |
f078f209 | 152 | |
e8324357 | 153 | static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
f078f209 | 154 | { |
066dae93 | 155 | struct ath_txq *txq = tid->ac->txq; |
e6a9854b | 156 | |
75401849 | 157 | WARN_ON(!tid->paused); |
f078f209 | 158 | |
23de5dc9 | 159 | ath_txq_lock(sc, txq); |
75401849 | 160 | tid->paused = false; |
f078f209 | 161 | |
56dc6336 | 162 | if (skb_queue_empty(&tid->buf_q)) |
e8324357 | 163 | goto unlock; |
f078f209 | 164 | |
e8324357 S |
165 | ath_tx_queue_tid(txq, tid); |
166 | ath_txq_schedule(sc, txq); | |
167 | unlock: | |
23de5dc9 | 168 | ath_txq_unlock_complete(sc, txq); |
528f0c6b | 169 | } |
f078f209 | 170 | |
2d42efc4 | 171 | static struct ath_frame_info *get_frame_info(struct sk_buff *skb) |
76e45221 FF |
172 | { |
173 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
2d42efc4 FF |
174 | BUILD_BUG_ON(sizeof(struct ath_frame_info) > |
175 | sizeof(tx_info->rate_driver_data)); | |
176 | return (struct ath_frame_info *) &tx_info->rate_driver_data[0]; | |
76e45221 FF |
177 | } |
178 | ||
156369fa FF |
179 | static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno) |
180 | { | |
181 | ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno, | |
182 | seqno << IEEE80211_SEQ_SEQ_SHIFT); | |
183 | } | |
184 | ||
e8324357 | 185 | static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
528f0c6b | 186 | { |
066dae93 | 187 | struct ath_txq *txq = tid->ac->txq; |
56dc6336 | 188 | struct sk_buff *skb; |
e8324357 S |
189 | struct ath_buf *bf; |
190 | struct list_head bf_head; | |
90fa539c | 191 | struct ath_tx_status ts; |
2d42efc4 | 192 | struct ath_frame_info *fi; |
156369fa | 193 | bool sendbar = false; |
f078f209 | 194 | |
90fa539c | 195 | INIT_LIST_HEAD(&bf_head); |
e6a9854b | 196 | |
90fa539c | 197 | memset(&ts, 0, sizeof(ts)); |
f078f209 | 198 | |
56dc6336 FF |
199 | while ((skb = __skb_dequeue(&tid->buf_q))) { |
200 | fi = get_frame_info(skb); | |
201 | bf = fi->bf; | |
202 | ||
44f1d26c FF |
203 | if (bf && fi->retries) { |
204 | list_add_tail(&bf->list, &bf_head); | |
6a0ddaef | 205 | ath_tx_update_baw(sc, tid, bf->bf_state.seqno); |
156369fa FF |
206 | ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0); |
207 | sendbar = true; | |
90fa539c | 208 | } else { |
44f1d26c | 209 | ath_tx_send_normal(sc, txq, NULL, skb); |
90fa539c | 210 | } |
528f0c6b | 211 | } |
f078f209 | 212 | |
4eb287a4 NM |
213 | if (tid->baw_head == tid->baw_tail) { |
214 | tid->state &= ~AGGR_ADDBA_COMPLETE; | |
215 | tid->state &= ~AGGR_CLEANUP; | |
216 | } | |
217 | ||
23de5dc9 FF |
218 | if (sendbar) { |
219 | ath_txq_unlock(sc, txq); | |
156369fa | 220 | ath_send_bar(tid, tid->seq_start); |
23de5dc9 FF |
221 | ath_txq_lock(sc, txq); |
222 | } | |
528f0c6b | 223 | } |
f078f209 | 224 | |
e8324357 S |
225 | static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
226 | int seqno) | |
528f0c6b | 227 | { |
e8324357 | 228 | int index, cindex; |
f078f209 | 229 | |
e8324357 S |
230 | index = ATH_BA_INDEX(tid->seq_start, seqno); |
231 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | |
f078f209 | 232 | |
81ee13ba | 233 | __clear_bit(cindex, tid->tx_buf); |
528f0c6b | 234 | |
81ee13ba | 235 | while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) { |
e8324357 S |
236 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); |
237 | INCR(tid->baw_head, ATH_TID_MAX_BUFS); | |
f9437543 FF |
238 | if (tid->bar_index >= 0) |
239 | tid->bar_index--; | |
e8324357 | 240 | } |
528f0c6b | 241 | } |
f078f209 | 242 | |
e8324357 | 243 | static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
2d3bcba0 | 244 | u16 seqno) |
528f0c6b | 245 | { |
e8324357 | 246 | int index, cindex; |
528f0c6b | 247 | |
2d3bcba0 | 248 | index = ATH_BA_INDEX(tid->seq_start, seqno); |
e8324357 | 249 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); |
81ee13ba | 250 | __set_bit(cindex, tid->tx_buf); |
f078f209 | 251 | |
e8324357 S |
252 | if (index >= ((tid->baw_tail - tid->baw_head) & |
253 | (ATH_TID_MAX_BUFS - 1))) { | |
254 | tid->baw_tail = cindex; | |
255 | INCR(tid->baw_tail, ATH_TID_MAX_BUFS); | |
f078f209 | 256 | } |
f078f209 LR |
257 | } |
258 | ||
259 | /* | |
e8324357 S |
260 | * TODO: For frame(s) that are in the retry state, we will reuse the |
261 | * sequence number(s) without setting the retry bit. The | |
262 | * alternative is to give up on these and BAR the receiver's window | |
263 | * forward. | |
f078f209 | 264 | */ |
e8324357 S |
265 | static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq, |
266 | struct ath_atx_tid *tid) | |
f078f209 | 267 | |
f078f209 | 268 | { |
56dc6336 | 269 | struct sk_buff *skb; |
e8324357 S |
270 | struct ath_buf *bf; |
271 | struct list_head bf_head; | |
db1a052b | 272 | struct ath_tx_status ts; |
2d42efc4 | 273 | struct ath_frame_info *fi; |
db1a052b FF |
274 | |
275 | memset(&ts, 0, sizeof(ts)); | |
e8324357 | 276 | INIT_LIST_HEAD(&bf_head); |
f078f209 | 277 | |
56dc6336 FF |
278 | while ((skb = __skb_dequeue(&tid->buf_q))) { |
279 | fi = get_frame_info(skb); | |
280 | bf = fi->bf; | |
f078f209 | 281 | |
44f1d26c | 282 | if (!bf) { |
44f1d26c | 283 | ath_tx_complete(sc, skb, ATH_TX_ERROR, txq); |
44f1d26c FF |
284 | continue; |
285 | } | |
286 | ||
56dc6336 | 287 | list_add_tail(&bf->list, &bf_head); |
f078f209 | 288 | |
2d42efc4 | 289 | if (fi->retries) |
6a0ddaef | 290 | ath_tx_update_baw(sc, tid, bf->bf_state.seqno); |
f078f209 | 291 | |
156369fa | 292 | ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0); |
e8324357 | 293 | } |
f078f209 | 294 | |
e8324357 S |
295 | tid->seq_next = tid->seq_start; |
296 | tid->baw_tail = tid->baw_head; | |
f9437543 | 297 | tid->bar_index = -1; |
f078f209 LR |
298 | } |
299 | ||
fec247c0 | 300 | static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq, |
da647626 | 301 | struct sk_buff *skb, int count) |
f078f209 | 302 | { |
8b7f8532 | 303 | struct ath_frame_info *fi = get_frame_info(skb); |
f11cc949 | 304 | struct ath_buf *bf = fi->bf; |
e8324357 | 305 | struct ieee80211_hdr *hdr; |
da647626 | 306 | int prev = fi->retries; |
f078f209 | 307 | |
fec247c0 | 308 | TX_STAT_INC(txq->axq_qnum, a_retries); |
da647626 FF |
309 | fi->retries += count; |
310 | ||
311 | if (prev > 0) | |
2d42efc4 | 312 | return; |
f078f209 | 313 | |
e8324357 S |
314 | hdr = (struct ieee80211_hdr *)skb->data; |
315 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); | |
f11cc949 FF |
316 | dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, |
317 | sizeof(*hdr), DMA_TO_DEVICE); | |
f078f209 LR |
318 | } |
319 | ||
0a8cea84 | 320 | static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc) |
d43f3015 | 321 | { |
0a8cea84 | 322 | struct ath_buf *bf = NULL; |
d43f3015 S |
323 | |
324 | spin_lock_bh(&sc->tx.txbuflock); | |
0a8cea84 FF |
325 | |
326 | if (unlikely(list_empty(&sc->tx.txbuf))) { | |
8a46097a VT |
327 | spin_unlock_bh(&sc->tx.txbuflock); |
328 | return NULL; | |
329 | } | |
0a8cea84 FF |
330 | |
331 | bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); | |
332 | list_del(&bf->list); | |
333 | ||
d43f3015 S |
334 | spin_unlock_bh(&sc->tx.txbuflock); |
335 | ||
0a8cea84 FF |
336 | return bf; |
337 | } | |
338 | ||
339 | static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf) | |
340 | { | |
341 | spin_lock_bh(&sc->tx.txbuflock); | |
342 | list_add_tail(&bf->list, &sc->tx.txbuf); | |
343 | spin_unlock_bh(&sc->tx.txbuflock); | |
344 | } | |
345 | ||
346 | static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf) | |
347 | { | |
348 | struct ath_buf *tbf; | |
349 | ||
350 | tbf = ath_tx_get_buffer(sc); | |
351 | if (WARN_ON(!tbf)) | |
352 | return NULL; | |
353 | ||
d43f3015 S |
354 | ATH_TXBUF_RESET(tbf); |
355 | ||
356 | tbf->bf_mpdu = bf->bf_mpdu; | |
357 | tbf->bf_buf_addr = bf->bf_buf_addr; | |
d826c832 | 358 | memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len); |
d43f3015 | 359 | tbf->bf_state = bf->bf_state; |
d43f3015 S |
360 | |
361 | return tbf; | |
362 | } | |
363 | ||
b572d033 FF |
364 | static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf, |
365 | struct ath_tx_status *ts, int txok, | |
366 | int *nframes, int *nbad) | |
367 | { | |
2d42efc4 | 368 | struct ath_frame_info *fi; |
b572d033 FF |
369 | u16 seq_st = 0; |
370 | u32 ba[WME_BA_BMP_SIZE >> 5]; | |
371 | int ba_index; | |
372 | int isaggr = 0; | |
373 | ||
374 | *nbad = 0; | |
375 | *nframes = 0; | |
376 | ||
b572d033 FF |
377 | isaggr = bf_isaggr(bf); |
378 | if (isaggr) { | |
379 | seq_st = ts->ts_seqnum; | |
380 | memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); | |
381 | } | |
382 | ||
383 | while (bf) { | |
2d42efc4 | 384 | fi = get_frame_info(bf->bf_mpdu); |
6a0ddaef | 385 | ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno); |
b572d033 FF |
386 | |
387 | (*nframes)++; | |
388 | if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index))) | |
389 | (*nbad)++; | |
390 | ||
391 | bf = bf->bf_next; | |
392 | } | |
393 | } | |
394 | ||
395 | ||
d43f3015 S |
396 | static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, |
397 | struct ath_buf *bf, struct list_head *bf_q, | |
c5992618 | 398 | struct ath_tx_status *ts, int txok, bool retry) |
f078f209 | 399 | { |
e8324357 S |
400 | struct ath_node *an = NULL; |
401 | struct sk_buff *skb; | |
1286ec6d | 402 | struct ieee80211_sta *sta; |
0cdd5c60 | 403 | struct ieee80211_hw *hw = sc->hw; |
1286ec6d | 404 | struct ieee80211_hdr *hdr; |
76d5a9e8 | 405 | struct ieee80211_tx_info *tx_info; |
e8324357 | 406 | struct ath_atx_tid *tid = NULL; |
d43f3015 | 407 | struct ath_buf *bf_next, *bf_last = bf->bf_lastbf; |
56dc6336 FF |
408 | struct list_head bf_head; |
409 | struct sk_buff_head bf_pending; | |
156369fa | 410 | u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first; |
f078f209 | 411 | u32 ba[WME_BA_BMP_SIZE >> 5]; |
0934af23 VT |
412 | int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0; |
413 | bool rc_update = true; | |
78c4653a | 414 | struct ieee80211_tx_rate rates[4]; |
2d42efc4 | 415 | struct ath_frame_info *fi; |
ebd02287 | 416 | int nframes; |
5daefbd0 | 417 | u8 tidno; |
daa5c408 | 418 | bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH); |
da647626 | 419 | int i, retries; |
156369fa | 420 | int bar_index = -1; |
f078f209 | 421 | |
a22be22a | 422 | skb = bf->bf_mpdu; |
1286ec6d S |
423 | hdr = (struct ieee80211_hdr *)skb->data; |
424 | ||
76d5a9e8 | 425 | tx_info = IEEE80211_SKB_CB(skb); |
76d5a9e8 | 426 | |
78c4653a FF |
427 | memcpy(rates, tx_info->control.rates, sizeof(rates)); |
428 | ||
da647626 FF |
429 | retries = ts->ts_longretry + 1; |
430 | for (i = 0; i < ts->ts_rateindex; i++) | |
431 | retries += rates[i].count; | |
432 | ||
1286ec6d | 433 | rcu_read_lock(); |
f078f209 | 434 | |
686b9cb9 | 435 | sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2); |
1286ec6d S |
436 | if (!sta) { |
437 | rcu_read_unlock(); | |
73e19463 | 438 | |
31e79a59 FF |
439 | INIT_LIST_HEAD(&bf_head); |
440 | while (bf) { | |
441 | bf_next = bf->bf_next; | |
442 | ||
fce041be | 443 | if (!bf->bf_stale || bf_next != NULL) |
31e79a59 FF |
444 | list_move_tail(&bf->list, &bf_head); |
445 | ||
156369fa | 446 | ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0); |
31e79a59 FF |
447 | |
448 | bf = bf_next; | |
449 | } | |
1286ec6d | 450 | return; |
f078f209 LR |
451 | } |
452 | ||
1286ec6d | 453 | an = (struct ath_node *)sta->drv_priv; |
5daefbd0 FF |
454 | tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK; |
455 | tid = ATH_AN_2_TID(an, tidno); | |
156369fa | 456 | seq_first = tid->seq_start; |
1286ec6d | 457 | |
b11b160d FF |
458 | /* |
459 | * The hardware occasionally sends a tx status for the wrong TID. | |
460 | * In this case, the BA status cannot be considered valid and all | |
461 | * subframes need to be retransmitted | |
462 | */ | |
5daefbd0 | 463 | if (tidno != ts->tid) |
b11b160d FF |
464 | txok = false; |
465 | ||
e8324357 | 466 | isaggr = bf_isaggr(bf); |
d43f3015 | 467 | memset(ba, 0, WME_BA_BMP_SIZE >> 3); |
f078f209 | 468 | |
d43f3015 | 469 | if (isaggr && txok) { |
db1a052b FF |
470 | if (ts->ts_flags & ATH9K_TX_BA) { |
471 | seq_st = ts->ts_seqnum; | |
472 | memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); | |
e8324357 | 473 | } else { |
d43f3015 S |
474 | /* |
475 | * AR5416 can become deaf/mute when BA | |
476 | * issue happens. Chip needs to be reset. | |
477 | * But AP code may have sychronization issues | |
478 | * when perform internal reset in this routine. | |
479 | * Only enable reset in STA mode for now. | |
480 | */ | |
2660b81a | 481 | if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) |
d43f3015 | 482 | needreset = 1; |
e8324357 | 483 | } |
f078f209 LR |
484 | } |
485 | ||
56dc6336 | 486 | __skb_queue_head_init(&bf_pending); |
f078f209 | 487 | |
b572d033 | 488 | ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad); |
e8324357 | 489 | while (bf) { |
6a0ddaef FF |
490 | u16 seqno = bf->bf_state.seqno; |
491 | ||
f0b8220c | 492 | txfail = txpending = sendbar = 0; |
e8324357 | 493 | bf_next = bf->bf_next; |
f078f209 | 494 | |
78c4653a FF |
495 | skb = bf->bf_mpdu; |
496 | tx_info = IEEE80211_SKB_CB(skb); | |
2d42efc4 | 497 | fi = get_frame_info(skb); |
78c4653a | 498 | |
6a0ddaef | 499 | if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) { |
e8324357 S |
500 | /* transmit completion, subframe is |
501 | * acked by block ack */ | |
0934af23 | 502 | acked_cnt++; |
e8324357 S |
503 | } else if (!isaggr && txok) { |
504 | /* transmit completion */ | |
0934af23 | 505 | acked_cnt++; |
b0477013 FF |
506 | } else if ((tid->state & AGGR_CLEANUP) || !retry) { |
507 | /* | |
508 | * cleanup in progress, just fail | |
509 | * the un-acked sub-frames | |
510 | */ | |
511 | txfail = 1; | |
512 | } else if (flush) { | |
513 | txpending = 1; | |
514 | } else if (fi->retries < ATH_MAX_SW_RETRIES) { | |
515 | if (txok || !an->sleeping) | |
516 | ath_tx_set_retry(sc, txq, bf->bf_mpdu, | |
517 | retries); | |
518 | ||
519 | txpending = 1; | |
e8324357 | 520 | } else { |
b0477013 FF |
521 | txfail = 1; |
522 | txfail_cnt++; | |
523 | bar_index = max_t(int, bar_index, | |
524 | ATH_BA_INDEX(seq_first, seqno)); | |
e8324357 | 525 | } |
f078f209 | 526 | |
fce041be FF |
527 | /* |
528 | * Make sure the last desc is reclaimed if it | |
529 | * not a holding desc. | |
530 | */ | |
56dc6336 FF |
531 | INIT_LIST_HEAD(&bf_head); |
532 | if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) || | |
533 | bf_next != NULL || !bf_last->bf_stale) | |
d43f3015 | 534 | list_move_tail(&bf->list, &bf_head); |
f078f209 | 535 | |
90fa539c | 536 | if (!txpending || (tid->state & AGGR_CLEANUP)) { |
e8324357 S |
537 | /* |
538 | * complete the acked-ones/xretried ones; update | |
539 | * block-ack window | |
540 | */ | |
6a0ddaef | 541 | ath_tx_update_baw(sc, tid, seqno); |
f078f209 | 542 | |
8a92e2ee | 543 | if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) { |
78c4653a | 544 | memcpy(tx_info->control.rates, rates, sizeof(rates)); |
3afd21e7 | 545 | ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok); |
8a92e2ee | 546 | rc_update = false; |
8a92e2ee VT |
547 | } |
548 | ||
db1a052b | 549 | ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, |
156369fa | 550 | !txfail); |
e8324357 | 551 | } else { |
d43f3015 | 552 | /* retry the un-acked ones */ |
b0477013 FF |
553 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && |
554 | bf->bf_next == NULL && bf_last->bf_stale) { | |
555 | struct ath_buf *tbf; | |
556 | ||
557 | tbf = ath_clone_txbuf(sc, bf_last); | |
558 | /* | |
559 | * Update tx baw and complete the | |
560 | * frame with failed status if we | |
561 | * run out of tx buf. | |
562 | */ | |
563 | if (!tbf) { | |
b0477013 | 564 | ath_tx_update_baw(sc, tid, seqno); |
b0477013 FF |
565 | |
566 | ath_tx_complete_buf(sc, bf, txq, | |
567 | &bf_head, ts, 0); | |
568 | bar_index = max_t(int, bar_index, | |
569 | ATH_BA_INDEX(seq_first, seqno)); | |
570 | break; | |
c41d92dc | 571 | } |
b0477013 FF |
572 | |
573 | fi->bf = tbf; | |
e8324357 S |
574 | } |
575 | ||
576 | /* | |
577 | * Put this buffer to the temporary pending | |
578 | * queue to retain ordering | |
579 | */ | |
56dc6336 | 580 | __skb_queue_tail(&bf_pending, skb); |
e8324357 S |
581 | } |
582 | ||
583 | bf = bf_next; | |
f078f209 | 584 | } |
f078f209 | 585 | |
4cee7861 | 586 | /* prepend un-acked frames to the beginning of the pending frame queue */ |
56dc6336 | 587 | if (!skb_queue_empty(&bf_pending)) { |
5519541d | 588 | if (an->sleeping) |
042ec453 | 589 | ieee80211_sta_set_buffered(sta, tid->tidno, true); |
5519541d | 590 | |
56dc6336 | 591 | skb_queue_splice(&bf_pending, &tid->buf_q); |
26a64259 | 592 | if (!an->sleeping) { |
9af73cf7 | 593 | ath_tx_queue_tid(txq, tid); |
26a64259 FF |
594 | |
595 | if (ts->ts_status & ATH9K_TXERR_FILT) | |
596 | tid->ac->clear_ps_filter = true; | |
597 | } | |
4cee7861 FF |
598 | } |
599 | ||
23de5dc9 FF |
600 | if (bar_index >= 0) { |
601 | u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index); | |
602 | ||
603 | if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq)) | |
604 | tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq); | |
605 | ||
606 | ath_txq_unlock(sc, txq); | |
607 | ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1)); | |
608 | ath_txq_lock(sc, txq); | |
609 | } | |
610 | ||
4eb287a4 | 611 | if (tid->state & AGGR_CLEANUP) |
90fa539c FF |
612 | ath_tx_flush_tid(sc, tid); |
613 | ||
1286ec6d S |
614 | rcu_read_unlock(); |
615 | ||
030d6294 FF |
616 | if (needreset) { |
617 | RESET_STAT_INC(sc, RESET_TYPE_TX_ERROR); | |
236de514 | 618 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); |
030d6294 | 619 | } |
e8324357 | 620 | } |
f078f209 | 621 | |
1a6e9d0f RM |
622 | static bool ath_lookup_legacy(struct ath_buf *bf) |
623 | { | |
624 | struct sk_buff *skb; | |
625 | struct ieee80211_tx_info *tx_info; | |
626 | struct ieee80211_tx_rate *rates; | |
627 | int i; | |
628 | ||
629 | skb = bf->bf_mpdu; | |
630 | tx_info = IEEE80211_SKB_CB(skb); | |
631 | rates = tx_info->control.rates; | |
632 | ||
059ee09b FF |
633 | for (i = 0; i < 4; i++) { |
634 | if (!rates[i].count || rates[i].idx < 0) | |
635 | break; | |
636 | ||
1a6e9d0f RM |
637 | if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) |
638 | return true; | |
639 | } | |
640 | ||
641 | return false; | |
642 | } | |
643 | ||
e8324357 S |
644 | static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf, |
645 | struct ath_atx_tid *tid) | |
f078f209 | 646 | { |
528f0c6b S |
647 | struct sk_buff *skb; |
648 | struct ieee80211_tx_info *tx_info; | |
a8efee4f | 649 | struct ieee80211_tx_rate *rates; |
d43f3015 | 650 | u32 max_4ms_framelen, frmlen; |
c0ac53fa | 651 | u16 aggr_limit, bt_aggr_limit, legacy = 0; |
e8324357 | 652 | int i; |
528f0c6b | 653 | |
a22be22a | 654 | skb = bf->bf_mpdu; |
528f0c6b | 655 | tx_info = IEEE80211_SKB_CB(skb); |
e63835b0 | 656 | rates = tx_info->control.rates; |
528f0c6b | 657 | |
e8324357 S |
658 | /* |
659 | * Find the lowest frame length among the rate series that will have a | |
660 | * 4ms transmit duration. | |
661 | * TODO - TXOP limit needs to be considered. | |
662 | */ | |
663 | max_4ms_framelen = ATH_AMPDU_LIMIT_MAX; | |
e63835b0 | 664 | |
e8324357 | 665 | for (i = 0; i < 4; i++) { |
b0477013 | 666 | int modeidx; |
e8324357 | 667 | |
b0477013 FF |
668 | if (!rates[i].count) |
669 | continue; | |
545750d3 | 670 | |
b0477013 FF |
671 | if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) { |
672 | legacy = 1; | |
673 | break; | |
f078f209 | 674 | } |
b0477013 FF |
675 | |
676 | if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) | |
677 | modeidx = MCS_HT40; | |
678 | else | |
679 | modeidx = MCS_HT20; | |
680 | ||
681 | if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) | |
682 | modeidx++; | |
683 | ||
684 | frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx]; | |
685 | max_4ms_framelen = min(max_4ms_framelen, frmlen); | |
f078f209 | 686 | } |
e63835b0 | 687 | |
f078f209 | 688 | /* |
e8324357 S |
689 | * limit aggregate size by the minimum rate if rate selected is |
690 | * not a probe rate, if rate selected is a probe rate then | |
691 | * avoid aggregation of this packet. | |
f078f209 | 692 | */ |
e8324357 S |
693 | if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy) |
694 | return 0; | |
f078f209 | 695 | |
c0ac53fa SM |
696 | aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX); |
697 | ||
698 | /* | |
699 | * Override the default aggregation limit for BTCOEX. | |
700 | */ | |
701 | bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen); | |
702 | if (bt_aggr_limit) | |
703 | aggr_limit = bt_aggr_limit; | |
f078f209 | 704 | |
e8324357 | 705 | /* |
25985edc LDM |
706 | * h/w can accept aggregates up to 16 bit lengths (65535). |
707 | * The IE, however can hold up to 65536, which shows up here | |
e8324357 | 708 | * as zero. Ignore 65536 since we are constrained by hw. |
f078f209 | 709 | */ |
4ef70841 S |
710 | if (tid->an->maxampdu) |
711 | aggr_limit = min(aggr_limit, tid->an->maxampdu); | |
f078f209 | 712 | |
e8324357 S |
713 | return aggr_limit; |
714 | } | |
f078f209 | 715 | |
e8324357 | 716 | /* |
d43f3015 | 717 | * Returns the number of delimiters to be added to |
e8324357 | 718 | * meet the minimum required mpdudensity. |
e8324357 S |
719 | */ |
720 | static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid, | |
7a12dfdb RM |
721 | struct ath_buf *bf, u16 frmlen, |
722 | bool first_subfrm) | |
e8324357 | 723 | { |
7a12dfdb | 724 | #define FIRST_DESC_NDELIMS 60 |
e8324357 S |
725 | struct sk_buff *skb = bf->bf_mpdu; |
726 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
4ef70841 | 727 | u32 nsymbits, nsymbols; |
e8324357 | 728 | u16 minlen; |
545750d3 | 729 | u8 flags, rix; |
c6663876 | 730 | int width, streams, half_gi, ndelim, mindelim; |
2d42efc4 | 731 | struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); |
e8324357 S |
732 | |
733 | /* Select standard number of delimiters based on frame length alone */ | |
734 | ndelim = ATH_AGGR_GET_NDELIM(frmlen); | |
f078f209 LR |
735 | |
736 | /* | |
e8324357 S |
737 | * If encryption enabled, hardware requires some more padding between |
738 | * subframes. | |
739 | * TODO - this could be improved to be dependent on the rate. | |
740 | * The hardware can keep up at lower rates, but not higher rates | |
f078f209 | 741 | */ |
4f6760b0 RM |
742 | if ((fi->keyix != ATH9K_TXKEYIX_INVALID) && |
743 | !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) | |
e8324357 | 744 | ndelim += ATH_AGGR_ENCRYPTDELIM; |
f078f209 | 745 | |
7a12dfdb RM |
746 | /* |
747 | * Add delimiter when using RTS/CTS with aggregation | |
748 | * and non enterprise AR9003 card | |
749 | */ | |
3459731a FF |
750 | if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) && |
751 | (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE)) | |
7a12dfdb RM |
752 | ndelim = max(ndelim, FIRST_DESC_NDELIMS); |
753 | ||
e8324357 S |
754 | /* |
755 | * Convert desired mpdu density from microeconds to bytes based | |
756 | * on highest rate in rate series (i.e. first rate) to determine | |
757 | * required minimum length for subframe. Take into account | |
758 | * whether high rate is 20 or 40Mhz and half or full GI. | |
4ef70841 | 759 | * |
e8324357 S |
760 | * If there is no mpdu density restriction, no further calculation |
761 | * is needed. | |
762 | */ | |
4ef70841 S |
763 | |
764 | if (tid->an->mpdudensity == 0) | |
e8324357 | 765 | return ndelim; |
f078f209 | 766 | |
e8324357 S |
767 | rix = tx_info->control.rates[0].idx; |
768 | flags = tx_info->control.rates[0].flags; | |
e8324357 S |
769 | width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0; |
770 | half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0; | |
f078f209 | 771 | |
e8324357 | 772 | if (half_gi) |
4ef70841 | 773 | nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity); |
e8324357 | 774 | else |
4ef70841 | 775 | nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity); |
f078f209 | 776 | |
e8324357 S |
777 | if (nsymbols == 0) |
778 | nsymbols = 1; | |
f078f209 | 779 | |
c6663876 FF |
780 | streams = HT_RC_2_STREAMS(rix); |
781 | nsymbits = bits_per_symbol[rix % 8][width] * streams; | |
e8324357 | 782 | minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; |
f078f209 | 783 | |
e8324357 | 784 | if (frmlen < minlen) { |
e8324357 S |
785 | mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ; |
786 | ndelim = max(mindelim, ndelim); | |
f078f209 LR |
787 | } |
788 | ||
e8324357 | 789 | return ndelim; |
f078f209 LR |
790 | } |
791 | ||
e8324357 | 792 | static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc, |
fec247c0 | 793 | struct ath_txq *txq, |
d43f3015 | 794 | struct ath_atx_tid *tid, |
269c44bc FF |
795 | struct list_head *bf_q, |
796 | int *aggr_len) | |
f078f209 | 797 | { |
e8324357 | 798 | #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) |
56dc6336 | 799 | struct ath_buf *bf, *bf_first = NULL, *bf_prev = NULL; |
d43f3015 | 800 | int rl = 0, nframes = 0, ndelim, prev_al = 0; |
e8324357 S |
801 | u16 aggr_limit = 0, al = 0, bpad = 0, |
802 | al_delta, h_baw = tid->baw_size / 2; | |
803 | enum ATH_AGGR_STATUS status = ATH_AGGR_DONE; | |
0299a50a | 804 | struct ieee80211_tx_info *tx_info; |
2d42efc4 | 805 | struct ath_frame_info *fi; |
56dc6336 | 806 | struct sk_buff *skb; |
6a0ddaef | 807 | u16 seqno; |
f078f209 | 808 | |
e8324357 | 809 | do { |
56dc6336 FF |
810 | skb = skb_peek(&tid->buf_q); |
811 | fi = get_frame_info(skb); | |
812 | bf = fi->bf; | |
44f1d26c FF |
813 | if (!fi->bf) |
814 | bf = ath_tx_setup_buffer(sc, txq, tid, skb); | |
56dc6336 | 815 | |
44f1d26c FF |
816 | if (!bf) |
817 | continue; | |
818 | ||
399c6489 | 819 | bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR; |
44f1d26c | 820 | seqno = bf->bf_state.seqno; |
f078f209 | 821 | |
d43f3015 | 822 | /* do not step over block-ack window */ |
6a0ddaef | 823 | if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) { |
e8324357 S |
824 | status = ATH_AGGR_BAW_CLOSED; |
825 | break; | |
826 | } | |
f078f209 | 827 | |
f9437543 FF |
828 | if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) { |
829 | struct ath_tx_status ts = {}; | |
830 | struct list_head bf_head; | |
831 | ||
832 | INIT_LIST_HEAD(&bf_head); | |
833 | list_add(&bf->list, &bf_head); | |
834 | __skb_unlink(skb, &tid->buf_q); | |
835 | ath_tx_update_baw(sc, tid, seqno); | |
836 | ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0); | |
837 | continue; | |
838 | } | |
839 | ||
840 | if (!bf_first) | |
841 | bf_first = bf; | |
842 | ||
e8324357 S |
843 | if (!rl) { |
844 | aggr_limit = ath_lookup_rate(sc, bf, tid); | |
845 | rl = 1; | |
846 | } | |
f078f209 | 847 | |
d43f3015 | 848 | /* do not exceed aggregation limit */ |
2d42efc4 | 849 | al_delta = ATH_AGGR_DELIM_SZ + fi->framelen; |
f078f209 | 850 | |
d43f3015 | 851 | if (nframes && |
1a6e9d0f RM |
852 | ((aggr_limit < (al + bpad + al_delta + prev_al)) || |
853 | ath_lookup_legacy(bf))) { | |
e8324357 S |
854 | status = ATH_AGGR_LIMITED; |
855 | break; | |
856 | } | |
f078f209 | 857 | |
0299a50a | 858 | tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); |
bdf2dbfb | 859 | if (nframes && (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) |
0299a50a FF |
860 | break; |
861 | ||
d43f3015 S |
862 | /* do not exceed subframe limit */ |
863 | if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) { | |
e8324357 S |
864 | status = ATH_AGGR_LIMITED; |
865 | break; | |
866 | } | |
f078f209 | 867 | |
d43f3015 | 868 | /* add padding for previous frame to aggregation length */ |
e8324357 | 869 | al += bpad + al_delta; |
f078f209 | 870 | |
e8324357 S |
871 | /* |
872 | * Get the delimiters needed to meet the MPDU | |
873 | * density for this node. | |
874 | */ | |
7a12dfdb RM |
875 | ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen, |
876 | !nframes); | |
e8324357 | 877 | bpad = PADBYTES(al_delta) + (ndelim << 2); |
f078f209 | 878 | |
7a12dfdb | 879 | nframes++; |
e8324357 | 880 | bf->bf_next = NULL; |
f078f209 | 881 | |
d43f3015 | 882 | /* link buffers of this frame to the aggregate */ |
2d42efc4 | 883 | if (!fi->retries) |
6a0ddaef | 884 | ath_tx_addto_baw(sc, tid, seqno); |
399c6489 | 885 | bf->bf_state.ndelim = ndelim; |
56dc6336 FF |
886 | |
887 | __skb_unlink(skb, &tid->buf_q); | |
888 | list_add_tail(&bf->list, bf_q); | |
399c6489 | 889 | if (bf_prev) |
e8324357 | 890 | bf_prev->bf_next = bf; |
399c6489 | 891 | |
e8324357 | 892 | bf_prev = bf; |
fec247c0 | 893 | |
56dc6336 | 894 | } while (!skb_queue_empty(&tid->buf_q)); |
f078f209 | 895 | |
269c44bc | 896 | *aggr_len = al; |
d43f3015 | 897 | |
e8324357 S |
898 | return status; |
899 | #undef PADBYTES | |
900 | } | |
f078f209 | 901 | |
38dad7ba FF |
902 | /* |
903 | * rix - rate index | |
904 | * pktlen - total bytes (delims + data + fcs + pads + pad delims) | |
905 | * width - 0 for 20 MHz, 1 for 40 MHz | |
906 | * half_gi - to use 4us v/s 3.6 us for symbol time | |
907 | */ | |
908 | static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen, | |
909 | int width, int half_gi, bool shortPreamble) | |
910 | { | |
911 | u32 nbits, nsymbits, duration, nsymbols; | |
912 | int streams; | |
913 | ||
914 | /* find number of symbols: PLCP + data */ | |
915 | streams = HT_RC_2_STREAMS(rix); | |
916 | nbits = (pktlen << 3) + OFDM_PLCP_BITS; | |
917 | nsymbits = bits_per_symbol[rix % 8][width] * streams; | |
918 | nsymbols = (nbits + nsymbits - 1) / nsymbits; | |
919 | ||
920 | if (!half_gi) | |
921 | duration = SYMBOL_TIME(nsymbols); | |
922 | else | |
923 | duration = SYMBOL_TIME_HALFGI(nsymbols); | |
924 | ||
925 | /* addup duration for legacy/ht training and signal fields */ | |
926 | duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); | |
927 | ||
928 | return duration; | |
929 | } | |
930 | ||
493cf04f FF |
931 | static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, |
932 | struct ath_tx_info *info, int len) | |
38dad7ba FF |
933 | { |
934 | struct ath_hw *ah = sc->sc_ah; | |
38dad7ba FF |
935 | struct sk_buff *skb; |
936 | struct ieee80211_tx_info *tx_info; | |
937 | struct ieee80211_tx_rate *rates; | |
938 | const struct ieee80211_rate *rate; | |
939 | struct ieee80211_hdr *hdr; | |
493cf04f FF |
940 | int i; |
941 | u8 rix = 0; | |
38dad7ba FF |
942 | |
943 | skb = bf->bf_mpdu; | |
944 | tx_info = IEEE80211_SKB_CB(skb); | |
945 | rates = tx_info->control.rates; | |
946 | hdr = (struct ieee80211_hdr *)skb->data; | |
493cf04f FF |
947 | |
948 | /* set dur_update_en for l-sig computation except for PS-Poll frames */ | |
949 | info->dur_update = !ieee80211_is_pspoll(hdr->frame_control); | |
38dad7ba FF |
950 | |
951 | /* | |
952 | * We check if Short Preamble is needed for the CTS rate by | |
953 | * checking the BSS's global flag. | |
954 | * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used. | |
955 | */ | |
956 | rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info); | |
493cf04f | 957 | info->rtscts_rate = rate->hw_value; |
38dad7ba | 958 | if (sc->sc_flags & SC_OP_PREAMBLE_SHORT) |
493cf04f | 959 | info->rtscts_rate |= rate->hw_value_short; |
38dad7ba FF |
960 | |
961 | for (i = 0; i < 4; i++) { | |
962 | bool is_40, is_sgi, is_sp; | |
963 | int phy; | |
964 | ||
965 | if (!rates[i].count || (rates[i].idx < 0)) | |
966 | continue; | |
967 | ||
968 | rix = rates[i].idx; | |
493cf04f | 969 | info->rates[i].Tries = rates[i].count; |
38dad7ba FF |
970 | |
971 | if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) { | |
493cf04f FF |
972 | info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; |
973 | info->flags |= ATH9K_TXDESC_RTSENA; | |
38dad7ba | 974 | } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { |
493cf04f FF |
975 | info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; |
976 | info->flags |= ATH9K_TXDESC_CTSENA; | |
38dad7ba FF |
977 | } |
978 | ||
979 | if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) | |
493cf04f | 980 | info->rates[i].RateFlags |= ATH9K_RATESERIES_2040; |
38dad7ba | 981 | if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) |
493cf04f | 982 | info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI; |
38dad7ba FF |
983 | |
984 | is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI); | |
985 | is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH); | |
986 | is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE); | |
987 | ||
988 | if (rates[i].flags & IEEE80211_TX_RC_MCS) { | |
989 | /* MCS rates */ | |
493cf04f FF |
990 | info->rates[i].Rate = rix | 0x80; |
991 | info->rates[i].ChSel = ath_txchainmask_reduction(sc, | |
992 | ah->txchainmask, info->rates[i].Rate); | |
993 | info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len, | |
38dad7ba FF |
994 | is_40, is_sgi, is_sp); |
995 | if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC)) | |
493cf04f | 996 | info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC; |
38dad7ba FF |
997 | continue; |
998 | } | |
999 | ||
1000 | /* legacy rates */ | |
1001 | if ((tx_info->band == IEEE80211_BAND_2GHZ) && | |
1002 | !(rate->flags & IEEE80211_RATE_ERP_G)) | |
1003 | phy = WLAN_RC_PHY_CCK; | |
1004 | else | |
1005 | phy = WLAN_RC_PHY_OFDM; | |
1006 | ||
1007 | rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx]; | |
493cf04f | 1008 | info->rates[i].Rate = rate->hw_value; |
38dad7ba FF |
1009 | if (rate->hw_value_short) { |
1010 | if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) | |
493cf04f | 1011 | info->rates[i].Rate |= rate->hw_value_short; |
38dad7ba FF |
1012 | } else { |
1013 | is_sp = false; | |
1014 | } | |
1015 | ||
1016 | if (bf->bf_state.bfs_paprd) | |
493cf04f | 1017 | info->rates[i].ChSel = ah->txchainmask; |
38dad7ba | 1018 | else |
493cf04f FF |
1019 | info->rates[i].ChSel = ath_txchainmask_reduction(sc, |
1020 | ah->txchainmask, info->rates[i].Rate); | |
38dad7ba | 1021 | |
493cf04f | 1022 | info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah, |
38dad7ba FF |
1023 | phy, rate->bitrate * 100, len, rix, is_sp); |
1024 | } | |
1025 | ||
1026 | /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ | |
1027 | if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit)) | |
493cf04f | 1028 | info->flags &= ~ATH9K_TXDESC_RTSENA; |
38dad7ba FF |
1029 | |
1030 | /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */ | |
493cf04f FF |
1031 | if (info->flags & ATH9K_TXDESC_RTSENA) |
1032 | info->flags &= ~ATH9K_TXDESC_CTSENA; | |
1033 | } | |
38dad7ba | 1034 | |
493cf04f FF |
1035 | static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb) |
1036 | { | |
1037 | struct ieee80211_hdr *hdr; | |
1038 | enum ath9k_pkt_type htype; | |
1039 | __le16 fc; | |
1040 | ||
1041 | hdr = (struct ieee80211_hdr *)skb->data; | |
1042 | fc = hdr->frame_control; | |
38dad7ba | 1043 | |
493cf04f FF |
1044 | if (ieee80211_is_beacon(fc)) |
1045 | htype = ATH9K_PKT_TYPE_BEACON; | |
1046 | else if (ieee80211_is_probe_resp(fc)) | |
1047 | htype = ATH9K_PKT_TYPE_PROBE_RESP; | |
1048 | else if (ieee80211_is_atim(fc)) | |
1049 | htype = ATH9K_PKT_TYPE_ATIM; | |
1050 | else if (ieee80211_is_pspoll(fc)) | |
1051 | htype = ATH9K_PKT_TYPE_PSPOLL; | |
1052 | else | |
1053 | htype = ATH9K_PKT_TYPE_NORMAL; | |
1054 | ||
1055 | return htype; | |
38dad7ba FF |
1056 | } |
1057 | ||
493cf04f FF |
1058 | static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf, |
1059 | struct ath_txq *txq, int len) | |
399c6489 FF |
1060 | { |
1061 | struct ath_hw *ah = sc->sc_ah; | |
1062 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); | |
1063 | struct ath_buf *bf_first = bf; | |
493cf04f | 1064 | struct ath_tx_info info; |
399c6489 | 1065 | bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR); |
399c6489 | 1066 | |
493cf04f FF |
1067 | memset(&info, 0, sizeof(info)); |
1068 | info.is_first = true; | |
1069 | info.is_last = true; | |
1070 | info.txpower = MAX_RATE_POWER; | |
1071 | info.qcu = txq->axq_qnum; | |
1072 | ||
1073 | info.flags = ATH9K_TXDESC_INTREQ; | |
1074 | if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) | |
1075 | info.flags |= ATH9K_TXDESC_NOACK; | |
1076 | if (tx_info->flags & IEEE80211_TX_CTL_LDPC) | |
1077 | info.flags |= ATH9K_TXDESC_LDPC; | |
1078 | ||
1079 | ath_buf_set_rate(sc, bf, &info, len); | |
1080 | ||
1081 | if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) | |
1082 | info.flags |= ATH9K_TXDESC_CLRDMASK; | |
1083 | ||
1084 | if (bf->bf_state.bfs_paprd) | |
1085 | info.flags |= (u32) bf->bf_state.bfs_paprd << ATH9K_TXDESC_PAPRD_S; | |
399c6489 | 1086 | |
399c6489 FF |
1087 | |
1088 | while (bf) { | |
493cf04f FF |
1089 | struct sk_buff *skb = bf->bf_mpdu; |
1090 | struct ath_frame_info *fi = get_frame_info(skb); | |
1091 | ||
1092 | info.type = get_hw_packet_type(skb); | |
399c6489 | 1093 | if (bf->bf_next) |
493cf04f | 1094 | info.link = bf->bf_next->bf_daddr; |
399c6489 | 1095 | else |
493cf04f FF |
1096 | info.link = 0; |
1097 | ||
42cecc34 JL |
1098 | info.buf_addr[0] = bf->bf_buf_addr; |
1099 | info.buf_len[0] = skb->len; | |
493cf04f FF |
1100 | info.pkt_len = fi->framelen; |
1101 | info.keyix = fi->keyix; | |
1102 | info.keytype = fi->keytype; | |
1103 | ||
1104 | if (aggr) { | |
399c6489 | 1105 | if (bf == bf_first) |
493cf04f FF |
1106 | info.aggr = AGGR_BUF_FIRST; |
1107 | else if (!bf->bf_next) | |
1108 | info.aggr = AGGR_BUF_LAST; | |
1109 | else | |
1110 | info.aggr = AGGR_BUF_MIDDLE; | |
399c6489 | 1111 | |
493cf04f FF |
1112 | info.ndelim = bf->bf_state.ndelim; |
1113 | info.aggr_len = len; | |
399c6489 FF |
1114 | } |
1115 | ||
493cf04f | 1116 | ath9k_hw_set_txdesc(ah, bf->bf_desc, &info); |
399c6489 FF |
1117 | bf = bf->bf_next; |
1118 | } | |
1119 | } | |
1120 | ||
e8324357 S |
1121 | static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq, |
1122 | struct ath_atx_tid *tid) | |
1123 | { | |
d43f3015 | 1124 | struct ath_buf *bf; |
e8324357 | 1125 | enum ATH_AGGR_STATUS status; |
399c6489 | 1126 | struct ieee80211_tx_info *tx_info; |
e8324357 | 1127 | struct list_head bf_q; |
269c44bc | 1128 | int aggr_len; |
f078f209 | 1129 | |
e8324357 | 1130 | do { |
56dc6336 | 1131 | if (skb_queue_empty(&tid->buf_q)) |
e8324357 | 1132 | return; |
f078f209 | 1133 | |
e8324357 S |
1134 | INIT_LIST_HEAD(&bf_q); |
1135 | ||
269c44bc | 1136 | status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len); |
f078f209 | 1137 | |
f078f209 | 1138 | /* |
d43f3015 S |
1139 | * no frames picked up to be aggregated; |
1140 | * block-ack window is not open. | |
f078f209 | 1141 | */ |
e8324357 S |
1142 | if (list_empty(&bf_q)) |
1143 | break; | |
f078f209 | 1144 | |
e8324357 | 1145 | bf = list_first_entry(&bf_q, struct ath_buf, list); |
d43f3015 | 1146 | bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list); |
399c6489 | 1147 | tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); |
f078f209 | 1148 | |
5519541d FF |
1149 | if (tid->ac->clear_ps_filter) { |
1150 | tid->ac->clear_ps_filter = false; | |
399c6489 FF |
1151 | tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT; |
1152 | } else { | |
1153 | tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT; | |
5519541d FF |
1154 | } |
1155 | ||
d43f3015 | 1156 | /* if only one frame, send as non-aggregate */ |
b572d033 | 1157 | if (bf == bf->bf_lastbf) { |
399c6489 FF |
1158 | aggr_len = get_frame_info(bf->bf_mpdu)->framelen; |
1159 | bf->bf_state.bf_type = BUF_AMPDU; | |
1160 | } else { | |
1161 | TX_STAT_INC(txq->axq_qnum, a_aggr); | |
e8324357 | 1162 | } |
f078f209 | 1163 | |
493cf04f | 1164 | ath_tx_fill_desc(sc, bf, txq, aggr_len); |
fce041be | 1165 | ath_tx_txqaddbuf(sc, txq, &bf_q, false); |
4b3ba66a | 1166 | } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH && |
e8324357 S |
1167 | status != ATH_AGGR_BAW_CLOSED); |
1168 | } | |
1169 | ||
231c3a1f FF |
1170 | int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, |
1171 | u16 tid, u16 *ssn) | |
e8324357 S |
1172 | { |
1173 | struct ath_atx_tid *txtid; | |
1174 | struct ath_node *an; | |
1175 | ||
1176 | an = (struct ath_node *)sta->drv_priv; | |
f83da965 | 1177 | txtid = ATH_AN_2_TID(an, tid); |
231c3a1f FF |
1178 | |
1179 | if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE)) | |
1180 | return -EAGAIN; | |
1181 | ||
f83da965 | 1182 | txtid->state |= AGGR_ADDBA_PROGRESS; |
75401849 | 1183 | txtid->paused = true; |
49447f2f | 1184 | *ssn = txtid->seq_start = txtid->seq_next; |
f9437543 | 1185 | txtid->bar_index = -1; |
231c3a1f | 1186 | |
2ed72229 FF |
1187 | memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf)); |
1188 | txtid->baw_head = txtid->baw_tail = 0; | |
1189 | ||
231c3a1f | 1190 | return 0; |
e8324357 | 1191 | } |
f078f209 | 1192 | |
f83da965 | 1193 | void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) |
e8324357 S |
1194 | { |
1195 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
1196 | struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid); | |
066dae93 | 1197 | struct ath_txq *txq = txtid->ac->txq; |
f078f209 | 1198 | |
e8324357 | 1199 | if (txtid->state & AGGR_CLEANUP) |
f83da965 | 1200 | return; |
f078f209 | 1201 | |
e8324357 | 1202 | if (!(txtid->state & AGGR_ADDBA_COMPLETE)) { |
5eae6592 | 1203 | txtid->state &= ~AGGR_ADDBA_PROGRESS; |
f83da965 | 1204 | return; |
e8324357 | 1205 | } |
f078f209 | 1206 | |
23de5dc9 | 1207 | ath_txq_lock(sc, txq); |
75401849 | 1208 | txtid->paused = true; |
f078f209 | 1209 | |
90fa539c FF |
1210 | /* |
1211 | * If frames are still being transmitted for this TID, they will be | |
1212 | * cleaned up during tx completion. To prevent race conditions, this | |
1213 | * TID can only be reused after all in-progress subframes have been | |
1214 | * completed. | |
1215 | */ | |
1216 | if (txtid->baw_head != txtid->baw_tail) | |
e8324357 | 1217 | txtid->state |= AGGR_CLEANUP; |
90fa539c | 1218 | else |
e8324357 | 1219 | txtid->state &= ~AGGR_ADDBA_COMPLETE; |
90fa539c FF |
1220 | |
1221 | ath_tx_flush_tid(sc, txtid); | |
23de5dc9 | 1222 | ath_txq_unlock_complete(sc, txq); |
e8324357 | 1223 | } |
f078f209 | 1224 | |
042ec453 JB |
1225 | void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc, |
1226 | struct ath_node *an) | |
5519541d FF |
1227 | { |
1228 | struct ath_atx_tid *tid; | |
1229 | struct ath_atx_ac *ac; | |
1230 | struct ath_txq *txq; | |
042ec453 | 1231 | bool buffered; |
5519541d FF |
1232 | int tidno; |
1233 | ||
1234 | for (tidno = 0, tid = &an->tid[tidno]; | |
1235 | tidno < WME_NUM_TID; tidno++, tid++) { | |
1236 | ||
1237 | if (!tid->sched) | |
1238 | continue; | |
1239 | ||
1240 | ac = tid->ac; | |
1241 | txq = ac->txq; | |
1242 | ||
23de5dc9 | 1243 | ath_txq_lock(sc, txq); |
5519541d | 1244 | |
042ec453 | 1245 | buffered = !skb_queue_empty(&tid->buf_q); |
5519541d FF |
1246 | |
1247 | tid->sched = false; | |
1248 | list_del(&tid->list); | |
1249 | ||
1250 | if (ac->sched) { | |
1251 | ac->sched = false; | |
1252 | list_del(&ac->list); | |
1253 | } | |
1254 | ||
23de5dc9 | 1255 | ath_txq_unlock(sc, txq); |
5519541d | 1256 | |
042ec453 JB |
1257 | ieee80211_sta_set_buffered(sta, tidno, buffered); |
1258 | } | |
5519541d FF |
1259 | } |
1260 | ||
1261 | void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an) | |
1262 | { | |
1263 | struct ath_atx_tid *tid; | |
1264 | struct ath_atx_ac *ac; | |
1265 | struct ath_txq *txq; | |
1266 | int tidno; | |
1267 | ||
1268 | for (tidno = 0, tid = &an->tid[tidno]; | |
1269 | tidno < WME_NUM_TID; tidno++, tid++) { | |
1270 | ||
1271 | ac = tid->ac; | |
1272 | txq = ac->txq; | |
1273 | ||
23de5dc9 | 1274 | ath_txq_lock(sc, txq); |
5519541d FF |
1275 | ac->clear_ps_filter = true; |
1276 | ||
56dc6336 | 1277 | if (!skb_queue_empty(&tid->buf_q) && !tid->paused) { |
5519541d FF |
1278 | ath_tx_queue_tid(txq, tid); |
1279 | ath_txq_schedule(sc, txq); | |
1280 | } | |
1281 | ||
23de5dc9 | 1282 | ath_txq_unlock_complete(sc, txq); |
5519541d FF |
1283 | } |
1284 | } | |
1285 | ||
e8324357 S |
1286 | void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) |
1287 | { | |
1288 | struct ath_atx_tid *txtid; | |
1289 | struct ath_node *an; | |
1290 | ||
1291 | an = (struct ath_node *)sta->drv_priv; | |
1292 | ||
1293 | if (sc->sc_flags & SC_OP_TXAGGR) { | |
1294 | txtid = ATH_AN_2_TID(an, tid); | |
1295 | txtid->baw_size = | |
1296 | IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor; | |
1297 | txtid->state |= AGGR_ADDBA_COMPLETE; | |
1298 | txtid->state &= ~AGGR_ADDBA_PROGRESS; | |
1299 | ath_tx_resume_tid(sc, txtid); | |
1300 | } | |
f078f209 LR |
1301 | } |
1302 | ||
e8324357 S |
1303 | /********************/ |
1304 | /* Queue Management */ | |
1305 | /********************/ | |
f078f209 | 1306 | |
e8324357 S |
1307 | static void ath_txq_drain_pending_buffers(struct ath_softc *sc, |
1308 | struct ath_txq *txq) | |
f078f209 | 1309 | { |
e8324357 S |
1310 | struct ath_atx_ac *ac, *ac_tmp; |
1311 | struct ath_atx_tid *tid, *tid_tmp; | |
f078f209 | 1312 | |
e8324357 S |
1313 | list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) { |
1314 | list_del(&ac->list); | |
1315 | ac->sched = false; | |
1316 | list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) { | |
1317 | list_del(&tid->list); | |
1318 | tid->sched = false; | |
1319 | ath_tid_drain(sc, txq, tid); | |
1320 | } | |
f078f209 LR |
1321 | } |
1322 | } | |
1323 | ||
e8324357 | 1324 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) |
f078f209 | 1325 | { |
cbe61d8a | 1326 | struct ath_hw *ah = sc->sc_ah; |
e8324357 | 1327 | struct ath9k_tx_queue_info qi; |
066dae93 FF |
1328 | static const int subtype_txq_to_hwq[] = { |
1329 | [WME_AC_BE] = ATH_TXQ_AC_BE, | |
1330 | [WME_AC_BK] = ATH_TXQ_AC_BK, | |
1331 | [WME_AC_VI] = ATH_TXQ_AC_VI, | |
1332 | [WME_AC_VO] = ATH_TXQ_AC_VO, | |
1333 | }; | |
60f2d1d5 | 1334 | int axq_qnum, i; |
f078f209 | 1335 | |
e8324357 | 1336 | memset(&qi, 0, sizeof(qi)); |
066dae93 | 1337 | qi.tqi_subtype = subtype_txq_to_hwq[subtype]; |
e8324357 S |
1338 | qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT; |
1339 | qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT; | |
1340 | qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT; | |
1341 | qi.tqi_physCompBuf = 0; | |
f078f209 LR |
1342 | |
1343 | /* | |
e8324357 S |
1344 | * Enable interrupts only for EOL and DESC conditions. |
1345 | * We mark tx descriptors to receive a DESC interrupt | |
1346 | * when a tx queue gets deep; otherwise waiting for the | |
1347 | * EOL to reap descriptors. Note that this is done to | |
1348 | * reduce interrupt load and this only defers reaping | |
1349 | * descriptors, never transmitting frames. Aside from | |
1350 | * reducing interrupts this also permits more concurrency. | |
1351 | * The only potential downside is if the tx queue backs | |
1352 | * up in which case the top half of the kernel may backup | |
1353 | * due to a lack of tx descriptors. | |
1354 | * | |
1355 | * The UAPSD queue is an exception, since we take a desc- | |
1356 | * based intr on the EOSP frames. | |
f078f209 | 1357 | */ |
afe754d6 VT |
1358 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
1359 | qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE | | |
1360 | TXQ_FLAG_TXERRINT_ENABLE; | |
1361 | } else { | |
1362 | if (qtype == ATH9K_TX_QUEUE_UAPSD) | |
1363 | qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; | |
1364 | else | |
1365 | qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | | |
1366 | TXQ_FLAG_TXDESCINT_ENABLE; | |
1367 | } | |
60f2d1d5 BG |
1368 | axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); |
1369 | if (axq_qnum == -1) { | |
f078f209 | 1370 | /* |
e8324357 S |
1371 | * NB: don't print a message, this happens |
1372 | * normally on parts with too few tx queues | |
f078f209 | 1373 | */ |
e8324357 | 1374 | return NULL; |
f078f209 | 1375 | } |
60f2d1d5 BG |
1376 | if (!ATH_TXQ_SETUP(sc, axq_qnum)) { |
1377 | struct ath_txq *txq = &sc->tx.txq[axq_qnum]; | |
f078f209 | 1378 | |
60f2d1d5 BG |
1379 | txq->axq_qnum = axq_qnum; |
1380 | txq->mac80211_qnum = -1; | |
e8324357 | 1381 | txq->axq_link = NULL; |
23de5dc9 | 1382 | __skb_queue_head_init(&txq->complete_q); |
e8324357 S |
1383 | INIT_LIST_HEAD(&txq->axq_q); |
1384 | INIT_LIST_HEAD(&txq->axq_acq); | |
1385 | spin_lock_init(&txq->axq_lock); | |
1386 | txq->axq_depth = 0; | |
4b3ba66a | 1387 | txq->axq_ampdu_depth = 0; |
164ace38 | 1388 | txq->axq_tx_inprogress = false; |
60f2d1d5 | 1389 | sc->tx.txqsetup |= 1<<axq_qnum; |
e5003249 VT |
1390 | |
1391 | txq->txq_headidx = txq->txq_tailidx = 0; | |
1392 | for (i = 0; i < ATH_TXFIFO_DEPTH; i++) | |
1393 | INIT_LIST_HEAD(&txq->txq_fifo[i]); | |
e8324357 | 1394 | } |
60f2d1d5 | 1395 | return &sc->tx.txq[axq_qnum]; |
f078f209 LR |
1396 | } |
1397 | ||
e8324357 S |
1398 | int ath_txq_update(struct ath_softc *sc, int qnum, |
1399 | struct ath9k_tx_queue_info *qinfo) | |
1400 | { | |
cbe61d8a | 1401 | struct ath_hw *ah = sc->sc_ah; |
e8324357 S |
1402 | int error = 0; |
1403 | struct ath9k_tx_queue_info qi; | |
1404 | ||
1405 | if (qnum == sc->beacon.beaconq) { | |
1406 | /* | |
1407 | * XXX: for beacon queue, we just save the parameter. | |
1408 | * It will be picked up by ath_beaconq_config when | |
1409 | * it's necessary. | |
1410 | */ | |
1411 | sc->beacon.beacon_qi = *qinfo; | |
f078f209 | 1412 | return 0; |
e8324357 | 1413 | } |
f078f209 | 1414 | |
9680e8a3 | 1415 | BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum); |
e8324357 S |
1416 | |
1417 | ath9k_hw_get_txq_props(ah, qnum, &qi); | |
1418 | qi.tqi_aifs = qinfo->tqi_aifs; | |
1419 | qi.tqi_cwmin = qinfo->tqi_cwmin; | |
1420 | qi.tqi_cwmax = qinfo->tqi_cwmax; | |
1421 | qi.tqi_burstTime = qinfo->tqi_burstTime; | |
1422 | qi.tqi_readyTime = qinfo->tqi_readyTime; | |
1423 | ||
1424 | if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { | |
3800276a JP |
1425 | ath_err(ath9k_hw_common(sc->sc_ah), |
1426 | "Unable to update hardware queue %u!\n", qnum); | |
e8324357 S |
1427 | error = -EIO; |
1428 | } else { | |
1429 | ath9k_hw_resettxqueue(ah, qnum); | |
1430 | } | |
1431 | ||
1432 | return error; | |
1433 | } | |
1434 | ||
1435 | int ath_cabq_update(struct ath_softc *sc) | |
1436 | { | |
1437 | struct ath9k_tx_queue_info qi; | |
9814f6b3 | 1438 | struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf; |
e8324357 | 1439 | int qnum = sc->beacon.cabq->axq_qnum; |
f078f209 | 1440 | |
e8324357 | 1441 | ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi); |
f078f209 | 1442 | /* |
e8324357 | 1443 | * Ensure the readytime % is within the bounds. |
f078f209 | 1444 | */ |
17d7904d S |
1445 | if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND) |
1446 | sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND; | |
1447 | else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND) | |
1448 | sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND; | |
f078f209 | 1449 | |
9814f6b3 | 1450 | qi.tqi_readyTime = (cur_conf->beacon_interval * |
fdbf7335 | 1451 | sc->config.cabqReadytime) / 100; |
e8324357 S |
1452 | ath_txq_update(sc, qnum, &qi); |
1453 | ||
1454 | return 0; | |
f078f209 LR |
1455 | } |
1456 | ||
4b3ba66a FF |
1457 | static bool bf_is_ampdu_not_probing(struct ath_buf *bf) |
1458 | { | |
1459 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu); | |
1460 | return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE); | |
1461 | } | |
1462 | ||
fce041be FF |
1463 | static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq, |
1464 | struct list_head *list, bool retry_tx) | |
f078f209 | 1465 | { |
e8324357 S |
1466 | struct ath_buf *bf, *lastbf; |
1467 | struct list_head bf_head; | |
db1a052b FF |
1468 | struct ath_tx_status ts; |
1469 | ||
1470 | memset(&ts, 0, sizeof(ts)); | |
daa5c408 | 1471 | ts.ts_status = ATH9K_TX_FLUSH; |
e8324357 | 1472 | INIT_LIST_HEAD(&bf_head); |
f078f209 | 1473 | |
fce041be FF |
1474 | while (!list_empty(list)) { |
1475 | bf = list_first_entry(list, struct ath_buf, list); | |
f078f209 | 1476 | |
fce041be FF |
1477 | if (bf->bf_stale) { |
1478 | list_del(&bf->list); | |
f078f209 | 1479 | |
fce041be FF |
1480 | ath_tx_return_buffer(sc, bf); |
1481 | continue; | |
e8324357 | 1482 | } |
f078f209 | 1483 | |
e8324357 | 1484 | lastbf = bf->bf_lastbf; |
fce041be | 1485 | list_cut_position(&bf_head, list, &lastbf->list); |
e5003249 | 1486 | |
e8324357 | 1487 | txq->axq_depth--; |
4b3ba66a FF |
1488 | if (bf_is_ampdu_not_probing(bf)) |
1489 | txq->axq_ampdu_depth--; | |
e8324357 S |
1490 | |
1491 | if (bf_isampdu(bf)) | |
c5992618 FF |
1492 | ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0, |
1493 | retry_tx); | |
e8324357 | 1494 | else |
156369fa | 1495 | ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0); |
f078f209 | 1496 | } |
fce041be | 1497 | } |
f078f209 | 1498 | |
fce041be FF |
1499 | /* |
1500 | * Drain a given TX queue (could be Beacon or Data) | |
1501 | * | |
1502 | * This assumes output has been stopped and | |
1503 | * we do not need to block ath_tx_tasklet. | |
1504 | */ | |
1505 | void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx) | |
1506 | { | |
23de5dc9 FF |
1507 | ath_txq_lock(sc, txq); |
1508 | ||
e5003249 | 1509 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
fce041be | 1510 | int idx = txq->txq_tailidx; |
e5003249 | 1511 | |
fce041be FF |
1512 | while (!list_empty(&txq->txq_fifo[idx])) { |
1513 | ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx], | |
1514 | retry_tx); | |
1515 | ||
1516 | INCR(idx, ATH_TXFIFO_DEPTH); | |
e5003249 | 1517 | } |
fce041be | 1518 | txq->txq_tailidx = idx; |
e5003249 | 1519 | } |
e609e2ea | 1520 | |
fce041be FF |
1521 | txq->axq_link = NULL; |
1522 | txq->axq_tx_inprogress = false; | |
1523 | ath_drain_txq_list(sc, txq, &txq->axq_q, retry_tx); | |
1524 | ||
e609e2ea | 1525 | /* flush any pending frames if aggregation is enabled */ |
fce041be FF |
1526 | if ((sc->sc_flags & SC_OP_TXAGGR) && !retry_tx) |
1527 | ath_txq_drain_pending_buffers(sc, txq); | |
1528 | ||
23de5dc9 | 1529 | ath_txq_unlock_complete(sc, txq); |
f078f209 LR |
1530 | } |
1531 | ||
080e1a25 | 1532 | bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) |
f078f209 | 1533 | { |
cbe61d8a | 1534 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1535 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
043a0405 | 1536 | struct ath_txq *txq; |
34d25810 FF |
1537 | int i; |
1538 | u32 npend = 0; | |
043a0405 S |
1539 | |
1540 | if (sc->sc_flags & SC_OP_INVALID) | |
080e1a25 | 1541 | return true; |
043a0405 | 1542 | |
0d51cccc | 1543 | ath9k_hw_abort_tx_dma(ah); |
043a0405 | 1544 | |
0d51cccc | 1545 | /* Check if any queue remains active */ |
043a0405 | 1546 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
0d51cccc FF |
1547 | if (!ATH_TXQ_SETUP(sc, i)) |
1548 | continue; | |
1549 | ||
34d25810 FF |
1550 | if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum)) |
1551 | npend |= BIT(i); | |
043a0405 S |
1552 | } |
1553 | ||
080e1a25 | 1554 | if (npend) |
34d25810 | 1555 | ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend); |
043a0405 S |
1556 | |
1557 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
92460412 FF |
1558 | if (!ATH_TXQ_SETUP(sc, i)) |
1559 | continue; | |
1560 | ||
1561 | /* | |
1562 | * The caller will resume queues with ieee80211_wake_queues. | |
1563 | * Mark the queue as not stopped to prevent ath_tx_complete | |
1564 | * from waking the queue too early. | |
1565 | */ | |
1566 | txq = &sc->tx.txq[i]; | |
1567 | txq->stopped = false; | |
1568 | ath_draintxq(sc, txq, retry_tx); | |
043a0405 | 1569 | } |
080e1a25 FF |
1570 | |
1571 | return !npend; | |
e8324357 | 1572 | } |
f078f209 | 1573 | |
043a0405 | 1574 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) |
e8324357 | 1575 | { |
043a0405 S |
1576 | ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum); |
1577 | sc->tx.txqsetup &= ~(1<<txq->axq_qnum); | |
e8324357 | 1578 | } |
f078f209 | 1579 | |
7755bad9 BG |
1580 | /* For each axq_acq entry, for each tid, try to schedule packets |
1581 | * for transmit until ampdu_depth has reached min Q depth. | |
1582 | */ | |
e8324357 S |
1583 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) |
1584 | { | |
7755bad9 BG |
1585 | struct ath_atx_ac *ac, *ac_tmp, *last_ac; |
1586 | struct ath_atx_tid *tid, *last_tid; | |
f078f209 | 1587 | |
236de514 | 1588 | if (work_pending(&sc->hw_reset_work) || list_empty(&txq->axq_acq) || |
21f28e6f | 1589 | txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) |
e8324357 | 1590 | return; |
f078f209 | 1591 | |
e8324357 | 1592 | ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list); |
7755bad9 | 1593 | last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list); |
f078f209 | 1594 | |
7755bad9 BG |
1595 | list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) { |
1596 | last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list); | |
1597 | list_del(&ac->list); | |
1598 | ac->sched = false; | |
f078f209 | 1599 | |
7755bad9 BG |
1600 | while (!list_empty(&ac->tid_q)) { |
1601 | tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, | |
1602 | list); | |
1603 | list_del(&tid->list); | |
1604 | tid->sched = false; | |
f078f209 | 1605 | |
7755bad9 BG |
1606 | if (tid->paused) |
1607 | continue; | |
f078f209 | 1608 | |
7755bad9 | 1609 | ath_tx_sched_aggr(sc, txq, tid); |
f078f209 | 1610 | |
7755bad9 BG |
1611 | /* |
1612 | * add tid to round-robin queue if more frames | |
1613 | * are pending for the tid | |
1614 | */ | |
56dc6336 | 1615 | if (!skb_queue_empty(&tid->buf_q)) |
7755bad9 | 1616 | ath_tx_queue_tid(txq, tid); |
f078f209 | 1617 | |
7755bad9 BG |
1618 | if (tid == last_tid || |
1619 | txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) | |
1620 | break; | |
1621 | } | |
f078f209 | 1622 | |
b0477013 FF |
1623 | if (!list_empty(&ac->tid_q) && !ac->sched) { |
1624 | ac->sched = true; | |
1625 | list_add_tail(&ac->list, &txq->axq_acq); | |
f078f209 | 1626 | } |
7755bad9 BG |
1627 | |
1628 | if (ac == last_ac || | |
1629 | txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) | |
1630 | return; | |
e8324357 S |
1631 | } |
1632 | } | |
f078f209 | 1633 | |
e8324357 S |
1634 | /***********/ |
1635 | /* TX, DMA */ | |
1636 | /***********/ | |
1637 | ||
f078f209 | 1638 | /* |
e8324357 S |
1639 | * Insert a chain of ath_buf (descriptors) on a txq and |
1640 | * assume the descriptors are already chained together by caller. | |
f078f209 | 1641 | */ |
e8324357 | 1642 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, |
fce041be | 1643 | struct list_head *head, bool internal) |
f078f209 | 1644 | { |
cbe61d8a | 1645 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1646 | struct ath_common *common = ath9k_hw_common(ah); |
fce041be FF |
1647 | struct ath_buf *bf, *bf_last; |
1648 | bool puttxbuf = false; | |
1649 | bool edma; | |
f078f209 | 1650 | |
e8324357 S |
1651 | /* |
1652 | * Insert the frame on the outbound list and | |
1653 | * pass it on to the hardware. | |
1654 | */ | |
f078f209 | 1655 | |
e8324357 S |
1656 | if (list_empty(head)) |
1657 | return; | |
f078f209 | 1658 | |
fce041be | 1659 | edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); |
e8324357 | 1660 | bf = list_first_entry(head, struct ath_buf, list); |
fce041be | 1661 | bf_last = list_entry(head->prev, struct ath_buf, list); |
f078f209 | 1662 | |
d2182b69 JP |
1663 | ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n", |
1664 | txq->axq_qnum, txq->axq_depth); | |
f078f209 | 1665 | |
fce041be FF |
1666 | if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) { |
1667 | list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]); | |
e5003249 | 1668 | INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH); |
fce041be | 1669 | puttxbuf = true; |
e8324357 | 1670 | } else { |
e5003249 VT |
1671 | list_splice_tail_init(head, &txq->axq_q); |
1672 | ||
fce041be FF |
1673 | if (txq->axq_link) { |
1674 | ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr); | |
d2182b69 | 1675 | ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n", |
226afe68 JP |
1676 | txq->axq_qnum, txq->axq_link, |
1677 | ito64(bf->bf_daddr), bf->bf_desc); | |
fce041be FF |
1678 | } else if (!edma) |
1679 | puttxbuf = true; | |
1680 | ||
1681 | txq->axq_link = bf_last->bf_desc; | |
1682 | } | |
1683 | ||
1684 | if (puttxbuf) { | |
1685 | TX_STAT_INC(txq->axq_qnum, puttxbuf); | |
1686 | ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); | |
d2182b69 | 1687 | ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n", |
fce041be FF |
1688 | txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); |
1689 | } | |
1690 | ||
1691 | if (!edma) { | |
8d8d3fdc | 1692 | TX_STAT_INC(txq->axq_qnum, txstart); |
e5003249 | 1693 | ath9k_hw_txstart(ah, txq->axq_qnum); |
e8324357 | 1694 | } |
fce041be FF |
1695 | |
1696 | if (!internal) { | |
1697 | txq->axq_depth++; | |
1698 | if (bf_is_ampdu_not_probing(bf)) | |
1699 | txq->axq_ampdu_depth++; | |
1700 | } | |
e8324357 | 1701 | } |
f078f209 | 1702 | |
e8324357 | 1703 | static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid, |
44f1d26c | 1704 | struct sk_buff *skb, struct ath_tx_control *txctl) |
f078f209 | 1705 | { |
44f1d26c | 1706 | struct ath_frame_info *fi = get_frame_info(skb); |
04caf863 | 1707 | struct list_head bf_head; |
44f1d26c | 1708 | struct ath_buf *bf; |
f078f209 | 1709 | |
e8324357 S |
1710 | /* |
1711 | * Do not queue to h/w when any of the following conditions is true: | |
1712 | * - there are pending frames in software queue | |
1713 | * - the TID is currently paused for ADDBA/BAR request | |
1714 | * - seqno is not within block-ack window | |
1715 | * - h/w queue depth exceeds low water mark | |
1716 | */ | |
56dc6336 | 1717 | if (!skb_queue_empty(&tid->buf_q) || tid->paused || |
44f1d26c | 1718 | !BAW_WITHIN(tid->seq_start, tid->baw_size, tid->seq_next) || |
4b3ba66a | 1719 | txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) { |
f078f209 | 1720 | /* |
e8324357 S |
1721 | * Add this frame to software queue for scheduling later |
1722 | * for aggregation. | |
f078f209 | 1723 | */ |
bda8adda | 1724 | TX_STAT_INC(txctl->txq->axq_qnum, a_queued_sw); |
44f1d26c | 1725 | __skb_queue_tail(&tid->buf_q, skb); |
9af73cf7 FF |
1726 | if (!txctl->an || !txctl->an->sleeping) |
1727 | ath_tx_queue_tid(txctl->txq, tid); | |
e8324357 S |
1728 | return; |
1729 | } | |
1730 | ||
44f1d26c FF |
1731 | bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb); |
1732 | if (!bf) | |
1733 | return; | |
1734 | ||
399c6489 | 1735 | bf->bf_state.bf_type = BUF_AMPDU; |
04caf863 FF |
1736 | INIT_LIST_HEAD(&bf_head); |
1737 | list_add(&bf->list, &bf_head); | |
1738 | ||
e8324357 | 1739 | /* Add sub-frame to BAW */ |
44f1d26c | 1740 | ath_tx_addto_baw(sc, tid, bf->bf_state.seqno); |
e8324357 S |
1741 | |
1742 | /* Queue to h/w without aggregation */ | |
bda8adda | 1743 | TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw); |
d43f3015 | 1744 | bf->bf_lastbf = bf; |
493cf04f | 1745 | ath_tx_fill_desc(sc, bf, txctl->txq, fi->framelen); |
fce041be | 1746 | ath_tx_txqaddbuf(sc, txctl->txq, &bf_head, false); |
e8324357 S |
1747 | } |
1748 | ||
82b873af | 1749 | static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, |
44f1d26c | 1750 | struct ath_atx_tid *tid, struct sk_buff *skb) |
e8324357 | 1751 | { |
44f1d26c FF |
1752 | struct ath_frame_info *fi = get_frame_info(skb); |
1753 | struct list_head bf_head; | |
e8324357 S |
1754 | struct ath_buf *bf; |
1755 | ||
44f1d26c FF |
1756 | bf = fi->bf; |
1757 | if (!bf) | |
1758 | bf = ath_tx_setup_buffer(sc, txq, tid, skb); | |
1759 | ||
1760 | if (!bf) | |
1761 | return; | |
1762 | ||
1763 | INIT_LIST_HEAD(&bf_head); | |
1764 | list_add_tail(&bf->list, &bf_head); | |
399c6489 | 1765 | bf->bf_state.bf_type = 0; |
e8324357 | 1766 | |
d43f3015 | 1767 | bf->bf_lastbf = bf; |
493cf04f | 1768 | ath_tx_fill_desc(sc, bf, txq, fi->framelen); |
44f1d26c | 1769 | ath_tx_txqaddbuf(sc, txq, &bf_head, false); |
fec247c0 | 1770 | TX_STAT_INC(txq->axq_qnum, queued); |
e8324357 S |
1771 | } |
1772 | ||
2d42efc4 FF |
1773 | static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb, |
1774 | int framelen) | |
e8324357 S |
1775 | { |
1776 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
2d42efc4 FF |
1777 | struct ieee80211_sta *sta = tx_info->control.sta; |
1778 | struct ieee80211_key_conf *hw_key = tx_info->control.hw_key; | |
6a0ddaef | 1779 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
2d42efc4 | 1780 | struct ath_frame_info *fi = get_frame_info(skb); |
93ae2dd2 | 1781 | struct ath_node *an = NULL; |
2d42efc4 | 1782 | enum ath9k_key_type keytype; |
e8324357 | 1783 | |
2d42efc4 | 1784 | keytype = ath9k_cmn_get_hw_crypto_keytype(skb); |
e8324357 | 1785 | |
93ae2dd2 FF |
1786 | if (sta) |
1787 | an = (struct ath_node *) sta->drv_priv; | |
1788 | ||
2d42efc4 FF |
1789 | memset(fi, 0, sizeof(*fi)); |
1790 | if (hw_key) | |
1791 | fi->keyix = hw_key->hw_key_idx; | |
93ae2dd2 FF |
1792 | else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0) |
1793 | fi->keyix = an->ps_key; | |
2d42efc4 FF |
1794 | else |
1795 | fi->keyix = ATH9K_TXKEYIX_INVALID; | |
1796 | fi->keytype = keytype; | |
1797 | fi->framelen = framelen; | |
e8324357 S |
1798 | } |
1799 | ||
ea066d5a MSS |
1800 | u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate) |
1801 | { | |
1802 | struct ath_hw *ah = sc->sc_ah; | |
1803 | struct ath9k_channel *curchan = ah->curchan; | |
d77bf3eb RM |
1804 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && |
1805 | (curchan->channelFlags & CHANNEL_5GHZ) && | |
1806 | (chainmask == 0x7) && (rate < 0x90)) | |
ea066d5a MSS |
1807 | return 0x3; |
1808 | else | |
1809 | return chainmask; | |
1810 | } | |
1811 | ||
44f1d26c FF |
1812 | /* |
1813 | * Assign a descriptor (and sequence number if necessary, | |
1814 | * and map buffer for DMA. Frees skb on error | |
1815 | */ | |
fa05f87a | 1816 | static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, |
04caf863 | 1817 | struct ath_txq *txq, |
fa05f87a | 1818 | struct ath_atx_tid *tid, |
2d42efc4 | 1819 | struct sk_buff *skb) |
f078f209 | 1820 | { |
82b873af | 1821 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
2d42efc4 | 1822 | struct ath_frame_info *fi = get_frame_info(skb); |
fa05f87a | 1823 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
82b873af | 1824 | struct ath_buf *bf; |
fa05f87a | 1825 | u16 seqno; |
82b873af FF |
1826 | |
1827 | bf = ath_tx_get_buffer(sc); | |
1828 | if (!bf) { | |
d2182b69 | 1829 | ath_dbg(common, XMIT, "TX buffers are full\n"); |
44f1d26c | 1830 | goto error; |
82b873af | 1831 | } |
e022edbd | 1832 | |
528f0c6b | 1833 | ATH_TXBUF_RESET(bf); |
f078f209 | 1834 | |
fa05f87a FF |
1835 | if (tid) { |
1836 | seqno = tid->seq_next; | |
1837 | hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT); | |
1838 | INCR(tid->seq_next, IEEE80211_SEQ_MAX); | |
1839 | bf->bf_state.seqno = seqno; | |
1840 | } | |
1841 | ||
f078f209 | 1842 | bf->bf_mpdu = skb; |
f8316df1 | 1843 | |
c1739eb3 BG |
1844 | bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, |
1845 | skb->len, DMA_TO_DEVICE); | |
1846 | if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) { | |
f8316df1 | 1847 | bf->bf_mpdu = NULL; |
6cf9e995 | 1848 | bf->bf_buf_addr = 0; |
3800276a JP |
1849 | ath_err(ath9k_hw_common(sc->sc_ah), |
1850 | "dma_mapping_error() on TX\n"); | |
82b873af | 1851 | ath_tx_return_buffer(sc, bf); |
44f1d26c | 1852 | goto error; |
f8316df1 LR |
1853 | } |
1854 | ||
56dc6336 | 1855 | fi->bf = bf; |
04caf863 FF |
1856 | |
1857 | return bf; | |
44f1d26c FF |
1858 | |
1859 | error: | |
1860 | dev_kfree_skb_any(skb); | |
1861 | return NULL; | |
04caf863 FF |
1862 | } |
1863 | ||
1864 | /* FIXME: tx power */ | |
44f1d26c | 1865 | static void ath_tx_start_dma(struct ath_softc *sc, struct sk_buff *skb, |
04caf863 FF |
1866 | struct ath_tx_control *txctl) |
1867 | { | |
04caf863 FF |
1868 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
1869 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
248a38d0 | 1870 | struct ath_atx_tid *tid = NULL; |
fa05f87a | 1871 | struct ath_buf *bf; |
04caf863 | 1872 | u8 tidno; |
f078f209 | 1873 | |
61e1b0b0 MSS |
1874 | if ((sc->sc_flags & SC_OP_TXAGGR) && txctl->an && |
1875 | ieee80211_is_data_qos(hdr->frame_control)) { | |
5daefbd0 FF |
1876 | tidno = ieee80211_get_qos_ctl(hdr)[0] & |
1877 | IEEE80211_QOS_CTL_TID_MASK; | |
2d42efc4 | 1878 | tid = ATH_AN_2_TID(txctl->an, tidno); |
5daefbd0 | 1879 | |
066dae93 | 1880 | WARN_ON(tid->ac->txq != txctl->txq); |
248a38d0 FF |
1881 | } |
1882 | ||
1883 | if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) { | |
04caf863 FF |
1884 | /* |
1885 | * Try aggregation if it's a unicast data frame | |
1886 | * and the destination is HT capable. | |
1887 | */ | |
44f1d26c | 1888 | ath_tx_send_ampdu(sc, tid, skb, txctl); |
f078f209 | 1889 | } else { |
44f1d26c FF |
1890 | bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb); |
1891 | if (!bf) | |
3ad29529 | 1892 | return; |
04caf863 | 1893 | |
82b873af FF |
1894 | bf->bf_state.bfs_paprd = txctl->paprd; |
1895 | ||
9cf04dcc MSS |
1896 | if (txctl->paprd) |
1897 | bf->bf_state.bfs_paprd_timestamp = jiffies; | |
1898 | ||
44f1d26c | 1899 | ath_tx_send_normal(sc, txctl->txq, tid, skb); |
f078f209 | 1900 | } |
f078f209 LR |
1901 | } |
1902 | ||
f8316df1 | 1903 | /* Upon failure caller should free skb */ |
c52f33d0 | 1904 | int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, |
528f0c6b | 1905 | struct ath_tx_control *txctl) |
f078f209 | 1906 | { |
28d16708 FF |
1907 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; |
1908 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
2d42efc4 | 1909 | struct ieee80211_sta *sta = info->control.sta; |
f59a59fe | 1910 | struct ieee80211_vif *vif = info->control.vif; |
9ac58615 | 1911 | struct ath_softc *sc = hw->priv; |
84642d6b | 1912 | struct ath_txq *txq = txctl->txq; |
4d91f9f3 | 1913 | int padpos, padsize; |
04caf863 | 1914 | int frmlen = skb->len + FCS_LEN; |
28d16708 | 1915 | int q; |
f078f209 | 1916 | |
a9927ba3 BG |
1917 | /* NOTE: sta can be NULL according to net/mac80211.h */ |
1918 | if (sta) | |
1919 | txctl->an = (struct ath_node *)sta->drv_priv; | |
1920 | ||
04caf863 FF |
1921 | if (info->control.hw_key) |
1922 | frmlen += info->control.hw_key->icv_len; | |
1923 | ||
f078f209 | 1924 | /* |
e8324357 S |
1925 | * As a temporary workaround, assign seq# here; this will likely need |
1926 | * to be cleaned up to work better with Beacon transmission and virtual | |
1927 | * BSSes. | |
f078f209 | 1928 | */ |
e8324357 | 1929 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { |
e8324357 S |
1930 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) |
1931 | sc->tx.seq_no += 0x10; | |
1932 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); | |
1933 | hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); | |
f078f209 | 1934 | } |
f078f209 | 1935 | |
42cecc34 JL |
1936 | /* Add the padding after the header if this is not already done */ |
1937 | padpos = ath9k_cmn_padpos(hdr->frame_control); | |
1938 | padsize = padpos & 3; | |
1939 | if (padsize && skb->len > padpos) { | |
1940 | if (skb_headroom(skb) < padsize) | |
1941 | return -ENOMEM; | |
28d16708 | 1942 | |
42cecc34 JL |
1943 | skb_push(skb, padsize); |
1944 | memmove(skb->data, skb->data + padsize, padpos); | |
6e82bc4a | 1945 | hdr = (struct ieee80211_hdr *) skb->data; |
f078f209 | 1946 | } |
f078f209 | 1947 | |
f59a59fe FF |
1948 | if ((vif && vif->type != NL80211_IFTYPE_AP && |
1949 | vif->type != NL80211_IFTYPE_AP_VLAN) || | |
1950 | !ieee80211_is_data(hdr->frame_control)) | |
1951 | info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT; | |
1952 | ||
2d42efc4 FF |
1953 | setup_frame_info(hw, skb, frmlen); |
1954 | ||
1955 | /* | |
1956 | * At this point, the vif, hw_key and sta pointers in the tx control | |
1957 | * info are no longer valid (overwritten by the ath_frame_info data. | |
1958 | */ | |
1959 | ||
28d16708 | 1960 | q = skb_get_queue_mapping(skb); |
23de5dc9 FF |
1961 | |
1962 | ath_txq_lock(sc, txq); | |
28d16708 FF |
1963 | if (txq == sc->tx.txq_map[q] && |
1964 | ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) { | |
7545daf4 | 1965 | ieee80211_stop_queue(sc->hw, q); |
3db1cd5c | 1966 | txq->stopped = true; |
f078f209 | 1967 | } |
f078f209 | 1968 | |
44f1d26c | 1969 | ath_tx_start_dma(sc, skb, txctl); |
3ad29529 | 1970 | |
23de5dc9 | 1971 | ath_txq_unlock(sc, txq); |
3ad29529 | 1972 | |
44f1d26c | 1973 | return 0; |
f078f209 LR |
1974 | } |
1975 | ||
e8324357 S |
1976 | /*****************/ |
1977 | /* TX Completion */ | |
1978 | /*****************/ | |
528f0c6b | 1979 | |
e8324357 | 1980 | static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, |
0f9dc298 | 1981 | int tx_flags, struct ath_txq *txq) |
528f0c6b | 1982 | { |
e8324357 | 1983 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
c46917bb | 1984 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
4d91f9f3 | 1985 | struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data; |
97923b14 | 1986 | int q, padpos, padsize; |
528f0c6b | 1987 | |
d2182b69 | 1988 | ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb); |
528f0c6b | 1989 | |
55797b1a | 1990 | if (!(tx_flags & ATH_TX_ERROR)) |
e8324357 S |
1991 | /* Frame was ACKed */ |
1992 | tx_info->flags |= IEEE80211_TX_STAT_ACK; | |
528f0c6b | 1993 | |
42cecc34 JL |
1994 | padpos = ath9k_cmn_padpos(hdr->frame_control); |
1995 | padsize = padpos & 3; | |
1996 | if (padsize && skb->len>padpos+padsize) { | |
1997 | /* | |
1998 | * Remove MAC header padding before giving the frame back to | |
1999 | * mac80211. | |
2000 | */ | |
2001 | memmove(skb->data + padsize, skb->data, padpos); | |
2002 | skb_pull(skb, padsize); | |
e8324357 | 2003 | } |
528f0c6b | 2004 | |
c8e8868e | 2005 | if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) { |
1b04b930 | 2006 | sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK; |
d2182b69 | 2007 | ath_dbg(common, PS, |
226afe68 | 2008 | "Going back to sleep after having received TX status (0x%lx)\n", |
1b04b930 S |
2009 | sc->ps_flags & (PS_WAIT_FOR_BEACON | |
2010 | PS_WAIT_FOR_CAB | | |
2011 | PS_WAIT_FOR_PSPOLL_DATA | | |
2012 | PS_WAIT_FOR_TX_ACK)); | |
9a23f9ca JM |
2013 | } |
2014 | ||
7545daf4 FF |
2015 | q = skb_get_queue_mapping(skb); |
2016 | if (txq == sc->tx.txq_map[q]) { | |
7545daf4 FF |
2017 | if (WARN_ON(--txq->pending_frames < 0)) |
2018 | txq->pending_frames = 0; | |
92460412 | 2019 | |
7545daf4 FF |
2020 | if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) { |
2021 | ieee80211_wake_queue(sc->hw, q); | |
3db1cd5c | 2022 | txq->stopped = false; |
066dae93 | 2023 | } |
97923b14 | 2024 | } |
7545daf4 | 2025 | |
23de5dc9 | 2026 | __skb_queue_tail(&txq->complete_q, skb); |
e8324357 | 2027 | } |
f078f209 | 2028 | |
e8324357 | 2029 | static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, |
db1a052b | 2030 | struct ath_txq *txq, struct list_head *bf_q, |
156369fa | 2031 | struct ath_tx_status *ts, int txok) |
f078f209 | 2032 | { |
e8324357 | 2033 | struct sk_buff *skb = bf->bf_mpdu; |
3afd21e7 | 2034 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
e8324357 | 2035 | unsigned long flags; |
6b2c4032 | 2036 | int tx_flags = 0; |
f078f209 | 2037 | |
55797b1a | 2038 | if (!txok) |
6b2c4032 | 2039 | tx_flags |= ATH_TX_ERROR; |
f078f209 | 2040 | |
3afd21e7 FF |
2041 | if (ts->ts_status & ATH9K_TXERR_FILT) |
2042 | tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; | |
2043 | ||
c1739eb3 | 2044 | dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE); |
6cf9e995 | 2045 | bf->bf_buf_addr = 0; |
9f42c2b6 FF |
2046 | |
2047 | if (bf->bf_state.bfs_paprd) { | |
9cf04dcc MSS |
2048 | if (time_after(jiffies, |
2049 | bf->bf_state.bfs_paprd_timestamp + | |
2050 | msecs_to_jiffies(ATH_PAPRD_TIMEOUT))) | |
ca369eb4 | 2051 | dev_kfree_skb_any(skb); |
78a18172 | 2052 | else |
ca369eb4 | 2053 | complete(&sc->paprd_complete); |
9f42c2b6 | 2054 | } else { |
55797b1a | 2055 | ath_debug_stat_tx(sc, bf, ts, txq, tx_flags); |
0f9dc298 | 2056 | ath_tx_complete(sc, skb, tx_flags, txq); |
9f42c2b6 | 2057 | } |
6cf9e995 BG |
2058 | /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't |
2059 | * accidentally reference it later. | |
2060 | */ | |
2061 | bf->bf_mpdu = NULL; | |
e8324357 S |
2062 | |
2063 | /* | |
2064 | * Return the list of ath_buf of this mpdu to free queue | |
2065 | */ | |
2066 | spin_lock_irqsave(&sc->tx.txbuflock, flags); | |
2067 | list_splice_tail_init(bf_q, &sc->tx.txbuf); | |
2068 | spin_unlock_irqrestore(&sc->tx.txbuflock, flags); | |
f078f209 LR |
2069 | } |
2070 | ||
0cdd5c60 FF |
2071 | static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, |
2072 | struct ath_tx_status *ts, int nframes, int nbad, | |
3afd21e7 | 2073 | int txok) |
f078f209 | 2074 | { |
a22be22a | 2075 | struct sk_buff *skb = bf->bf_mpdu; |
254ad0ff | 2076 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
e8324357 | 2077 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
0cdd5c60 | 2078 | struct ieee80211_hw *hw = sc->hw; |
f0c255a0 | 2079 | struct ath_hw *ah = sc->sc_ah; |
8a92e2ee | 2080 | u8 i, tx_rateindex; |
f078f209 | 2081 | |
95e4acb7 | 2082 | if (txok) |
db1a052b | 2083 | tx_info->status.ack_signal = ts->ts_rssi; |
95e4acb7 | 2084 | |
db1a052b | 2085 | tx_rateindex = ts->ts_rateindex; |
8a92e2ee VT |
2086 | WARN_ON(tx_rateindex >= hw->max_rates); |
2087 | ||
3afd21e7 | 2088 | if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { |
d969847c | 2089 | tx_info->flags |= IEEE80211_TX_STAT_AMPDU; |
f078f209 | 2090 | |
b572d033 | 2091 | BUG_ON(nbad > nframes); |
ebd02287 | 2092 | } |
185d1589 RM |
2093 | tx_info->status.ampdu_len = nframes; |
2094 | tx_info->status.ampdu_ack_len = nframes - nbad; | |
ebd02287 | 2095 | |
db1a052b | 2096 | if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 && |
3afd21e7 | 2097 | (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) { |
f0c255a0 FF |
2098 | /* |
2099 | * If an underrun error is seen assume it as an excessive | |
2100 | * retry only if max frame trigger level has been reached | |
2101 | * (2 KB for single stream, and 4 KB for dual stream). | |
2102 | * Adjust the long retry as if the frame was tried | |
2103 | * hw->max_rate_tries times to affect how rate control updates | |
2104 | * PER for the failed rate. | |
2105 | * In case of congestion on the bus penalizing this type of | |
2106 | * underruns should help hardware actually transmit new frames | |
2107 | * successfully by eventually preferring slower rates. | |
2108 | * This itself should also alleviate congestion on the bus. | |
2109 | */ | |
3afd21e7 FF |
2110 | if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN | |
2111 | ATH9K_TX_DELIM_UNDERRUN)) && | |
2112 | ieee80211_is_data(hdr->frame_control) && | |
83860c59 | 2113 | ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level) |
f0c255a0 FF |
2114 | tx_info->status.rates[tx_rateindex].count = |
2115 | hw->max_rate_tries; | |
f078f209 | 2116 | } |
8a92e2ee | 2117 | |
545750d3 | 2118 | for (i = tx_rateindex + 1; i < hw->max_rates; i++) { |
8a92e2ee | 2119 | tx_info->status.rates[i].count = 0; |
545750d3 FF |
2120 | tx_info->status.rates[i].idx = -1; |
2121 | } | |
8a92e2ee | 2122 | |
78c4653a | 2123 | tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1; |
f078f209 LR |
2124 | } |
2125 | ||
fce041be FF |
2126 | static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq, |
2127 | struct ath_tx_status *ts, struct ath_buf *bf, | |
2128 | struct list_head *bf_head) | |
2129 | { | |
2130 | int txok; | |
2131 | ||
2132 | txq->axq_depth--; | |
2133 | txok = !(ts->ts_status & ATH9K_TXERR_MASK); | |
2134 | txq->axq_tx_inprogress = false; | |
2135 | if (bf_is_ampdu_not_probing(bf)) | |
2136 | txq->axq_ampdu_depth--; | |
2137 | ||
fce041be | 2138 | if (!bf_isampdu(bf)) { |
3afd21e7 | 2139 | ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok); |
156369fa | 2140 | ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok); |
fce041be FF |
2141 | } else |
2142 | ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok, true); | |
2143 | ||
fce041be FF |
2144 | if (sc->sc_flags & SC_OP_TXAGGR) |
2145 | ath_txq_schedule(sc, txq); | |
2146 | } | |
2147 | ||
e8324357 | 2148 | static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) |
f078f209 | 2149 | { |
cbe61d8a | 2150 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 2151 | struct ath_common *common = ath9k_hw_common(ah); |
e8324357 | 2152 | struct ath_buf *bf, *lastbf, *bf_held = NULL; |
f078f209 | 2153 | struct list_head bf_head; |
e8324357 | 2154 | struct ath_desc *ds; |
29bffa96 | 2155 | struct ath_tx_status ts; |
e8324357 | 2156 | int status; |
f078f209 | 2157 | |
d2182b69 | 2158 | ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n", |
226afe68 JP |
2159 | txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), |
2160 | txq->axq_link); | |
f078f209 | 2161 | |
23de5dc9 | 2162 | ath_txq_lock(sc, txq); |
f078f209 | 2163 | for (;;) { |
236de514 FF |
2164 | if (work_pending(&sc->hw_reset_work)) |
2165 | break; | |
2166 | ||
f078f209 LR |
2167 | if (list_empty(&txq->axq_q)) { |
2168 | txq->axq_link = NULL; | |
86271e46 | 2169 | if (sc->sc_flags & SC_OP_TXAGGR) |
082f6536 | 2170 | ath_txq_schedule(sc, txq); |
f078f209 LR |
2171 | break; |
2172 | } | |
f078f209 LR |
2173 | bf = list_first_entry(&txq->axq_q, struct ath_buf, list); |
2174 | ||
e8324357 S |
2175 | /* |
2176 | * There is a race condition that a BH gets scheduled | |
2177 | * after sw writes TxE and before hw re-load the last | |
2178 | * descriptor to get the newly chained one. | |
2179 | * Software must keep the last DONE descriptor as a | |
2180 | * holding descriptor - software does so by marking | |
2181 | * it with the STALE flag. | |
2182 | */ | |
2183 | bf_held = NULL; | |
a119cc49 | 2184 | if (bf->bf_stale) { |
e8324357 | 2185 | bf_held = bf; |
fce041be | 2186 | if (list_is_last(&bf_held->list, &txq->axq_q)) |
e8324357 | 2187 | break; |
fce041be FF |
2188 | |
2189 | bf = list_entry(bf_held->list.next, struct ath_buf, | |
2190 | list); | |
f078f209 LR |
2191 | } |
2192 | ||
2193 | lastbf = bf->bf_lastbf; | |
e8324357 | 2194 | ds = lastbf->bf_desc; |
f078f209 | 2195 | |
29bffa96 FF |
2196 | memset(&ts, 0, sizeof(ts)); |
2197 | status = ath9k_hw_txprocdesc(ah, ds, &ts); | |
fce041be | 2198 | if (status == -EINPROGRESS) |
e8324357 | 2199 | break; |
fce041be | 2200 | |
2dac4fb9 | 2201 | TX_STAT_INC(txq->axq_qnum, txprocdesc); |
f078f209 | 2202 | |
e8324357 S |
2203 | /* |
2204 | * Remove ath_buf's of the same transmit unit from txq, | |
2205 | * however leave the last descriptor back as the holding | |
2206 | * descriptor for hw. | |
2207 | */ | |
a119cc49 | 2208 | lastbf->bf_stale = true; |
e8324357 | 2209 | INIT_LIST_HEAD(&bf_head); |
e8324357 S |
2210 | if (!list_is_singular(&lastbf->list)) |
2211 | list_cut_position(&bf_head, | |
2212 | &txq->axq_q, lastbf->list.prev); | |
f078f209 | 2213 | |
fce041be | 2214 | if (bf_held) { |
0a8cea84 | 2215 | list_del(&bf_held->list); |
0a8cea84 | 2216 | ath_tx_return_buffer(sc, bf_held); |
e8324357 | 2217 | } |
f078f209 | 2218 | |
fce041be | 2219 | ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); |
8469cdef | 2220 | } |
23de5dc9 | 2221 | ath_txq_unlock_complete(sc, txq); |
8469cdef S |
2222 | } |
2223 | ||
305fe47f | 2224 | static void ath_tx_complete_poll_work(struct work_struct *work) |
164ace38 SB |
2225 | { |
2226 | struct ath_softc *sc = container_of(work, struct ath_softc, | |
2227 | tx_complete_work.work); | |
2228 | struct ath_txq *txq; | |
2229 | int i; | |
2230 | bool needreset = false; | |
60f2d1d5 BG |
2231 | #ifdef CONFIG_ATH9K_DEBUGFS |
2232 | sc->tx_complete_poll_work_seen++; | |
2233 | #endif | |
164ace38 SB |
2234 | |
2235 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) | |
2236 | if (ATH_TXQ_SETUP(sc, i)) { | |
2237 | txq = &sc->tx.txq[i]; | |
23de5dc9 | 2238 | ath_txq_lock(sc, txq); |
164ace38 SB |
2239 | if (txq->axq_depth) { |
2240 | if (txq->axq_tx_inprogress) { | |
2241 | needreset = true; | |
23de5dc9 | 2242 | ath_txq_unlock(sc, txq); |
164ace38 SB |
2243 | break; |
2244 | } else { | |
2245 | txq->axq_tx_inprogress = true; | |
2246 | } | |
2247 | } | |
23de5dc9 | 2248 | ath_txq_unlock_complete(sc, txq); |
164ace38 SB |
2249 | } |
2250 | ||
2251 | if (needreset) { | |
d2182b69 | 2252 | ath_dbg(ath9k_hw_common(sc->sc_ah), RESET, |
226afe68 | 2253 | "tx hung, resetting the chip\n"); |
030d6294 | 2254 | RESET_STAT_INC(sc, RESET_TYPE_TX_HANG); |
236de514 | 2255 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); |
164ace38 SB |
2256 | } |
2257 | ||
42935eca | 2258 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, |
164ace38 SB |
2259 | msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT)); |
2260 | } | |
2261 | ||
2262 | ||
f078f209 | 2263 | |
e8324357 | 2264 | void ath_tx_tasklet(struct ath_softc *sc) |
f078f209 | 2265 | { |
e8324357 S |
2266 | int i; |
2267 | u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1); | |
f078f209 | 2268 | |
e8324357 | 2269 | ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask); |
f078f209 | 2270 | |
e8324357 S |
2271 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
2272 | if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i))) | |
2273 | ath_tx_processq(sc, &sc->tx.txq[i]); | |
f078f209 LR |
2274 | } |
2275 | } | |
2276 | ||
e5003249 VT |
2277 | void ath_tx_edma_tasklet(struct ath_softc *sc) |
2278 | { | |
fce041be | 2279 | struct ath_tx_status ts; |
e5003249 VT |
2280 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
2281 | struct ath_hw *ah = sc->sc_ah; | |
2282 | struct ath_txq *txq; | |
2283 | struct ath_buf *bf, *lastbf; | |
2284 | struct list_head bf_head; | |
2285 | int status; | |
e5003249 VT |
2286 | |
2287 | for (;;) { | |
236de514 FF |
2288 | if (work_pending(&sc->hw_reset_work)) |
2289 | break; | |
2290 | ||
fce041be | 2291 | status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts); |
e5003249 VT |
2292 | if (status == -EINPROGRESS) |
2293 | break; | |
2294 | if (status == -EIO) { | |
d2182b69 | 2295 | ath_dbg(common, XMIT, "Error processing tx status\n"); |
e5003249 VT |
2296 | break; |
2297 | } | |
2298 | ||
4e0ad259 FF |
2299 | /* Process beacon completions separately */ |
2300 | if (ts.qid == sc->beacon.beaconq) { | |
2301 | sc->beacon.tx_processed = true; | |
2302 | sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); | |
e5003249 | 2303 | continue; |
4e0ad259 | 2304 | } |
e5003249 | 2305 | |
fce041be | 2306 | txq = &sc->tx.txq[ts.qid]; |
e5003249 | 2307 | |
23de5dc9 | 2308 | ath_txq_lock(sc, txq); |
fce041be | 2309 | |
e5003249 | 2310 | if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) { |
23de5dc9 | 2311 | ath_txq_unlock(sc, txq); |
e5003249 VT |
2312 | return; |
2313 | } | |
2314 | ||
2315 | bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx], | |
2316 | struct ath_buf, list); | |
2317 | lastbf = bf->bf_lastbf; | |
2318 | ||
2319 | INIT_LIST_HEAD(&bf_head); | |
2320 | list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx], | |
2321 | &lastbf->list); | |
e5003249 | 2322 | |
fce041be FF |
2323 | if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) { |
2324 | INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH); | |
e5003249 | 2325 | |
fce041be FF |
2326 | if (!list_empty(&txq->axq_q)) { |
2327 | struct list_head bf_q; | |
60f2d1d5 | 2328 | |
fce041be FF |
2329 | INIT_LIST_HEAD(&bf_q); |
2330 | txq->axq_link = NULL; | |
2331 | list_splice_tail_init(&txq->axq_q, &bf_q); | |
2332 | ath_tx_txqaddbuf(sc, txq, &bf_q, true); | |
2333 | } | |
2334 | } | |
86271e46 | 2335 | |
fce041be | 2336 | ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); |
23de5dc9 | 2337 | ath_txq_unlock_complete(sc, txq); |
e5003249 VT |
2338 | } |
2339 | } | |
2340 | ||
e8324357 S |
2341 | /*****************/ |
2342 | /* Init, Cleanup */ | |
2343 | /*****************/ | |
f078f209 | 2344 | |
5088c2f1 VT |
2345 | static int ath_txstatus_setup(struct ath_softc *sc, int size) |
2346 | { | |
2347 | struct ath_descdma *dd = &sc->txsdma; | |
2348 | u8 txs_len = sc->sc_ah->caps.txs_len; | |
2349 | ||
2350 | dd->dd_desc_len = size * txs_len; | |
2351 | dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len, | |
2352 | &dd->dd_desc_paddr, GFP_KERNEL); | |
2353 | if (!dd->dd_desc) | |
2354 | return -ENOMEM; | |
2355 | ||
2356 | return 0; | |
2357 | } | |
2358 | ||
2359 | static int ath_tx_edma_init(struct ath_softc *sc) | |
2360 | { | |
2361 | int err; | |
2362 | ||
2363 | err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE); | |
2364 | if (!err) | |
2365 | ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc, | |
2366 | sc->txsdma.dd_desc_paddr, | |
2367 | ATH_TXSTATUS_RING_SIZE); | |
2368 | ||
2369 | return err; | |
2370 | } | |
2371 | ||
2372 | static void ath_tx_edma_cleanup(struct ath_softc *sc) | |
2373 | { | |
2374 | struct ath_descdma *dd = &sc->txsdma; | |
2375 | ||
2376 | dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc, | |
2377 | dd->dd_desc_paddr); | |
2378 | } | |
2379 | ||
e8324357 | 2380 | int ath_tx_init(struct ath_softc *sc, int nbufs) |
f078f209 | 2381 | { |
c46917bb | 2382 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
e8324357 | 2383 | int error = 0; |
f078f209 | 2384 | |
797fe5cb | 2385 | spin_lock_init(&sc->tx.txbuflock); |
f078f209 | 2386 | |
797fe5cb | 2387 | error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, |
4adfcded | 2388 | "tx", nbufs, 1, 1); |
797fe5cb | 2389 | if (error != 0) { |
3800276a JP |
2390 | ath_err(common, |
2391 | "Failed to allocate tx descriptors: %d\n", error); | |
797fe5cb S |
2392 | goto err; |
2393 | } | |
f078f209 | 2394 | |
797fe5cb | 2395 | error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, |
5088c2f1 | 2396 | "beacon", ATH_BCBUF, 1, 1); |
797fe5cb | 2397 | if (error != 0) { |
3800276a JP |
2398 | ath_err(common, |
2399 | "Failed to allocate beacon descriptors: %d\n", error); | |
797fe5cb S |
2400 | goto err; |
2401 | } | |
f078f209 | 2402 | |
164ace38 SB |
2403 | INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work); |
2404 | ||
5088c2f1 VT |
2405 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
2406 | error = ath_tx_edma_init(sc); | |
2407 | if (error) | |
2408 | goto err; | |
2409 | } | |
2410 | ||
797fe5cb | 2411 | err: |
e8324357 S |
2412 | if (error != 0) |
2413 | ath_tx_cleanup(sc); | |
f078f209 | 2414 | |
e8324357 | 2415 | return error; |
f078f209 LR |
2416 | } |
2417 | ||
797fe5cb | 2418 | void ath_tx_cleanup(struct ath_softc *sc) |
e8324357 S |
2419 | { |
2420 | if (sc->beacon.bdma.dd_desc_len != 0) | |
2421 | ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf); | |
2422 | ||
2423 | if (sc->tx.txdma.dd_desc_len != 0) | |
2424 | ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf); | |
5088c2f1 VT |
2425 | |
2426 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
2427 | ath_tx_edma_cleanup(sc); | |
e8324357 | 2428 | } |
f078f209 LR |
2429 | |
2430 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an) | |
2431 | { | |
c5170163 S |
2432 | struct ath_atx_tid *tid; |
2433 | struct ath_atx_ac *ac; | |
2434 | int tidno, acno; | |
f078f209 | 2435 | |
8ee5afbc | 2436 | for (tidno = 0, tid = &an->tid[tidno]; |
c5170163 S |
2437 | tidno < WME_NUM_TID; |
2438 | tidno++, tid++) { | |
2439 | tid->an = an; | |
2440 | tid->tidno = tidno; | |
2441 | tid->seq_start = tid->seq_next = 0; | |
2442 | tid->baw_size = WME_MAX_BA; | |
2443 | tid->baw_head = tid->baw_tail = 0; | |
2444 | tid->sched = false; | |
e8324357 | 2445 | tid->paused = false; |
a37c2c79 | 2446 | tid->state &= ~AGGR_CLEANUP; |
56dc6336 | 2447 | __skb_queue_head_init(&tid->buf_q); |
c5170163 | 2448 | acno = TID_TO_WME_AC(tidno); |
8ee5afbc | 2449 | tid->ac = &an->ac[acno]; |
a37c2c79 S |
2450 | tid->state &= ~AGGR_ADDBA_COMPLETE; |
2451 | tid->state &= ~AGGR_ADDBA_PROGRESS; | |
c5170163 | 2452 | } |
f078f209 | 2453 | |
8ee5afbc | 2454 | for (acno = 0, ac = &an->ac[acno]; |
c5170163 S |
2455 | acno < WME_NUM_AC; acno++, ac++) { |
2456 | ac->sched = false; | |
066dae93 | 2457 | ac->txq = sc->tx.txq_map[acno]; |
c5170163 | 2458 | INIT_LIST_HEAD(&ac->tid_q); |
f078f209 LR |
2459 | } |
2460 | } | |
2461 | ||
b5aa9bf9 | 2462 | void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an) |
f078f209 | 2463 | { |
2b40994c FF |
2464 | struct ath_atx_ac *ac; |
2465 | struct ath_atx_tid *tid; | |
f078f209 | 2466 | struct ath_txq *txq; |
066dae93 | 2467 | int tidno; |
e8324357 | 2468 | |
2b40994c FF |
2469 | for (tidno = 0, tid = &an->tid[tidno]; |
2470 | tidno < WME_NUM_TID; tidno++, tid++) { | |
f078f209 | 2471 | |
2b40994c | 2472 | ac = tid->ac; |
066dae93 | 2473 | txq = ac->txq; |
f078f209 | 2474 | |
23de5dc9 | 2475 | ath_txq_lock(sc, txq); |
2b40994c FF |
2476 | |
2477 | if (tid->sched) { | |
2478 | list_del(&tid->list); | |
2479 | tid->sched = false; | |
2480 | } | |
2481 | ||
2482 | if (ac->sched) { | |
2483 | list_del(&ac->list); | |
2484 | tid->ac->sched = false; | |
f078f209 | 2485 | } |
2b40994c FF |
2486 | |
2487 | ath_tid_drain(sc, txq, tid); | |
2488 | tid->state &= ~AGGR_ADDBA_COMPLETE; | |
2489 | tid->state &= ~AGGR_CLEANUP; | |
2490 | ||
23de5dc9 | 2491 | ath_txq_unlock(sc, txq); |
f078f209 LR |
2492 | } |
2493 | } |