Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
394cf0a1 | 17 | #include "ath9k.h" |
b622a720 | 18 | #include "ar9003_mac.h" |
f078f209 LR |
19 | |
20 | #define BITS_PER_BYTE 8 | |
21 | #define OFDM_PLCP_BITS 22 | |
22 | #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f) | |
23 | #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) | |
24 | #define L_STF 8 | |
25 | #define L_LTF 8 | |
26 | #define L_SIG 4 | |
27 | #define HT_SIG 8 | |
28 | #define HT_STF 4 | |
29 | #define HT_LTF(_ns) (4 * (_ns)) | |
30 | #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */ | |
31 | #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */ | |
32 | #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) | |
33 | #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) | |
34 | ||
35 | #define OFDM_SIFS_TIME 16 | |
36 | ||
37 | static u32 bits_per_symbol[][2] = { | |
38 | /* 20MHz 40MHz */ | |
39 | { 26, 54 }, /* 0: BPSK */ | |
40 | { 52, 108 }, /* 1: QPSK 1/2 */ | |
41 | { 78, 162 }, /* 2: QPSK 3/4 */ | |
42 | { 104, 216 }, /* 3: 16-QAM 1/2 */ | |
43 | { 156, 324 }, /* 4: 16-QAM 3/4 */ | |
44 | { 208, 432 }, /* 5: 64-QAM 2/3 */ | |
45 | { 234, 486 }, /* 6: 64-QAM 3/4 */ | |
46 | { 260, 540 }, /* 7: 64-QAM 5/6 */ | |
47 | { 52, 108 }, /* 8: BPSK */ | |
48 | { 104, 216 }, /* 9: QPSK 1/2 */ | |
49 | { 156, 324 }, /* 10: QPSK 3/4 */ | |
50 | { 208, 432 }, /* 11: 16-QAM 1/2 */ | |
51 | { 312, 648 }, /* 12: 16-QAM 3/4 */ | |
52 | { 416, 864 }, /* 13: 64-QAM 2/3 */ | |
53 | { 468, 972 }, /* 14: 64-QAM 3/4 */ | |
54 | { 520, 1080 }, /* 15: 64-QAM 5/6 */ | |
55 | }; | |
56 | ||
57 | #define IS_HT_RATE(_rate) ((_rate) & 0x80) | |
58 | ||
c37452b0 S |
59 | static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq, |
60 | struct ath_atx_tid *tid, | |
61 | struct list_head *bf_head); | |
e8324357 | 62 | static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, |
db1a052b FF |
63 | struct ath_txq *txq, struct list_head *bf_q, |
64 | struct ath_tx_status *ts, int txok, int sendbar); | |
102e0572 | 65 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, |
e8324357 S |
66 | struct list_head *head); |
67 | static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf); | |
0934af23 | 68 | static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf, |
db1a052b FF |
69 | struct ath_tx_status *ts, int txok); |
70 | static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts, | |
8a92e2ee | 71 | int nbad, int txok, bool update_rc); |
c4288390 | 72 | |
545750d3 FF |
73 | enum { |
74 | MCS_DEFAULT, | |
75 | MCS_HT40, | |
76 | MCS_HT40_SGI, | |
77 | }; | |
78 | ||
79 | static int ath_max_4ms_framelen[3][16] = { | |
80 | [MCS_DEFAULT] = { | |
81 | 3216, 6434, 9650, 12868, 19304, 25740, 28956, 32180, | |
82 | 6430, 12860, 19300, 25736, 38600, 51472, 57890, 64320, | |
83 | }, | |
84 | [MCS_HT40] = { | |
85 | 6684, 13368, 20052, 26738, 40104, 53476, 60156, 66840, | |
86 | 13360, 26720, 40080, 53440, 80160, 106880, 120240, 133600, | |
87 | }, | |
88 | [MCS_HT40_SGI] = { | |
89 | /* TODO: Only MCS 7 and 15 updated, recalculate the rest */ | |
90 | 6684, 13368, 20052, 26738, 40104, 53476, 60156, 74200, | |
91 | 13360, 26720, 40080, 53440, 80160, 106880, 120240, 148400, | |
92 | } | |
93 | }; | |
94 | ||
e8324357 S |
95 | /*********************/ |
96 | /* Aggregation logic */ | |
97 | /*********************/ | |
f078f209 | 98 | |
e8324357 | 99 | static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid) |
ff37e337 | 100 | { |
e8324357 | 101 | struct ath_atx_ac *ac = tid->ac; |
ff37e337 | 102 | |
e8324357 S |
103 | if (tid->paused) |
104 | return; | |
ff37e337 | 105 | |
e8324357 S |
106 | if (tid->sched) |
107 | return; | |
ff37e337 | 108 | |
e8324357 S |
109 | tid->sched = true; |
110 | list_add_tail(&tid->list, &ac->tid_q); | |
528f0c6b | 111 | |
e8324357 S |
112 | if (ac->sched) |
113 | return; | |
f078f209 | 114 | |
e8324357 S |
115 | ac->sched = true; |
116 | list_add_tail(&ac->list, &txq->axq_acq); | |
117 | } | |
f078f209 | 118 | |
e8324357 S |
119 | static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
120 | { | |
121 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; | |
f078f209 | 122 | |
e8324357 S |
123 | spin_lock_bh(&txq->axq_lock); |
124 | tid->paused++; | |
125 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 LR |
126 | } |
127 | ||
e8324357 | 128 | static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
f078f209 | 129 | { |
e8324357 | 130 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; |
e6a9854b | 131 | |
9680e8a3 | 132 | BUG_ON(tid->paused <= 0); |
e8324357 | 133 | spin_lock_bh(&txq->axq_lock); |
f078f209 | 134 | |
e8324357 | 135 | tid->paused--; |
f078f209 | 136 | |
e8324357 S |
137 | if (tid->paused > 0) |
138 | goto unlock; | |
f078f209 | 139 | |
e8324357 S |
140 | if (list_empty(&tid->buf_q)) |
141 | goto unlock; | |
f078f209 | 142 | |
e8324357 S |
143 | ath_tx_queue_tid(txq, tid); |
144 | ath_txq_schedule(sc, txq); | |
145 | unlock: | |
146 | spin_unlock_bh(&txq->axq_lock); | |
528f0c6b | 147 | } |
f078f209 | 148 | |
e8324357 | 149 | static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
528f0c6b | 150 | { |
e8324357 S |
151 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; |
152 | struct ath_buf *bf; | |
153 | struct list_head bf_head; | |
154 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 155 | |
9680e8a3 | 156 | BUG_ON(tid->paused <= 0); |
e8324357 | 157 | spin_lock_bh(&txq->axq_lock); |
e6a9854b | 158 | |
e8324357 | 159 | tid->paused--; |
f078f209 | 160 | |
e8324357 S |
161 | if (tid->paused > 0) { |
162 | spin_unlock_bh(&txq->axq_lock); | |
163 | return; | |
164 | } | |
f078f209 | 165 | |
e8324357 S |
166 | while (!list_empty(&tid->buf_q)) { |
167 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); | |
9680e8a3 | 168 | BUG_ON(bf_isretried(bf)); |
d43f3015 | 169 | list_move_tail(&bf->list, &bf_head); |
c37452b0 | 170 | ath_tx_send_ht_normal(sc, txq, tid, &bf_head); |
528f0c6b | 171 | } |
f078f209 | 172 | |
e8324357 | 173 | spin_unlock_bh(&txq->axq_lock); |
528f0c6b | 174 | } |
f078f209 | 175 | |
e8324357 S |
176 | static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
177 | int seqno) | |
528f0c6b | 178 | { |
e8324357 | 179 | int index, cindex; |
f078f209 | 180 | |
e8324357 S |
181 | index = ATH_BA_INDEX(tid->seq_start, seqno); |
182 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | |
f078f209 | 183 | |
e8324357 | 184 | tid->tx_buf[cindex] = NULL; |
528f0c6b | 185 | |
e8324357 S |
186 | while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) { |
187 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); | |
188 | INCR(tid->baw_head, ATH_TID_MAX_BUFS); | |
189 | } | |
528f0c6b | 190 | } |
f078f209 | 191 | |
e8324357 S |
192 | static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
193 | struct ath_buf *bf) | |
528f0c6b | 194 | { |
e8324357 | 195 | int index, cindex; |
528f0c6b | 196 | |
e8324357 S |
197 | if (bf_isretried(bf)) |
198 | return; | |
528f0c6b | 199 | |
e8324357 S |
200 | index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno); |
201 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | |
f078f209 | 202 | |
9680e8a3 | 203 | BUG_ON(tid->tx_buf[cindex] != NULL); |
e8324357 | 204 | tid->tx_buf[cindex] = bf; |
f078f209 | 205 | |
e8324357 S |
206 | if (index >= ((tid->baw_tail - tid->baw_head) & |
207 | (ATH_TID_MAX_BUFS - 1))) { | |
208 | tid->baw_tail = cindex; | |
209 | INCR(tid->baw_tail, ATH_TID_MAX_BUFS); | |
f078f209 | 210 | } |
f078f209 LR |
211 | } |
212 | ||
213 | /* | |
e8324357 S |
214 | * TODO: For frame(s) that are in the retry state, we will reuse the |
215 | * sequence number(s) without setting the retry bit. The | |
216 | * alternative is to give up on these and BAR the receiver's window | |
217 | * forward. | |
f078f209 | 218 | */ |
e8324357 S |
219 | static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq, |
220 | struct ath_atx_tid *tid) | |
f078f209 | 221 | |
f078f209 | 222 | { |
e8324357 S |
223 | struct ath_buf *bf; |
224 | struct list_head bf_head; | |
db1a052b FF |
225 | struct ath_tx_status ts; |
226 | ||
227 | memset(&ts, 0, sizeof(ts)); | |
e8324357 | 228 | INIT_LIST_HEAD(&bf_head); |
f078f209 | 229 | |
e8324357 S |
230 | for (;;) { |
231 | if (list_empty(&tid->buf_q)) | |
232 | break; | |
f078f209 | 233 | |
d43f3015 S |
234 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); |
235 | list_move_tail(&bf->list, &bf_head); | |
f078f209 | 236 | |
e8324357 S |
237 | if (bf_isretried(bf)) |
238 | ath_tx_update_baw(sc, tid, bf->bf_seqno); | |
f078f209 | 239 | |
e8324357 | 240 | spin_unlock(&txq->axq_lock); |
db1a052b | 241 | ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0); |
e8324357 S |
242 | spin_lock(&txq->axq_lock); |
243 | } | |
f078f209 | 244 | |
e8324357 S |
245 | tid->seq_next = tid->seq_start; |
246 | tid->baw_tail = tid->baw_head; | |
f078f209 LR |
247 | } |
248 | ||
fec247c0 S |
249 | static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq, |
250 | struct ath_buf *bf) | |
f078f209 | 251 | { |
e8324357 S |
252 | struct sk_buff *skb; |
253 | struct ieee80211_hdr *hdr; | |
f078f209 | 254 | |
e8324357 S |
255 | bf->bf_state.bf_type |= BUF_RETRY; |
256 | bf->bf_retries++; | |
fec247c0 | 257 | TX_STAT_INC(txq->axq_qnum, a_retries); |
f078f209 | 258 | |
e8324357 S |
259 | skb = bf->bf_mpdu; |
260 | hdr = (struct ieee80211_hdr *)skb->data; | |
261 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); | |
f078f209 LR |
262 | } |
263 | ||
d43f3015 S |
264 | static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf) |
265 | { | |
266 | struct ath_buf *tbf; | |
267 | ||
268 | spin_lock_bh(&sc->tx.txbuflock); | |
8a46097a VT |
269 | if (WARN_ON(list_empty(&sc->tx.txbuf))) { |
270 | spin_unlock_bh(&sc->tx.txbuflock); | |
271 | return NULL; | |
272 | } | |
d43f3015 S |
273 | tbf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); |
274 | list_del(&tbf->list); | |
275 | spin_unlock_bh(&sc->tx.txbuflock); | |
276 | ||
277 | ATH_TXBUF_RESET(tbf); | |
278 | ||
827e69bf | 279 | tbf->aphy = bf->aphy; |
d43f3015 S |
280 | tbf->bf_mpdu = bf->bf_mpdu; |
281 | tbf->bf_buf_addr = bf->bf_buf_addr; | |
d826c832 | 282 | memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len); |
d43f3015 S |
283 | tbf->bf_state = bf->bf_state; |
284 | tbf->bf_dmacontext = bf->bf_dmacontext; | |
285 | ||
286 | return tbf; | |
287 | } | |
288 | ||
289 | static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, | |
290 | struct ath_buf *bf, struct list_head *bf_q, | |
db1a052b | 291 | struct ath_tx_status *ts, int txok) |
f078f209 | 292 | { |
e8324357 S |
293 | struct ath_node *an = NULL; |
294 | struct sk_buff *skb; | |
1286ec6d | 295 | struct ieee80211_sta *sta; |
76d5a9e8 | 296 | struct ieee80211_hw *hw; |
1286ec6d | 297 | struct ieee80211_hdr *hdr; |
76d5a9e8 | 298 | struct ieee80211_tx_info *tx_info; |
e8324357 | 299 | struct ath_atx_tid *tid = NULL; |
d43f3015 | 300 | struct ath_buf *bf_next, *bf_last = bf->bf_lastbf; |
e8324357 | 301 | struct list_head bf_head, bf_pending; |
0934af23 | 302 | u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0; |
f078f209 | 303 | u32 ba[WME_BA_BMP_SIZE >> 5]; |
0934af23 VT |
304 | int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0; |
305 | bool rc_update = true; | |
f078f209 | 306 | |
a22be22a | 307 | skb = bf->bf_mpdu; |
1286ec6d S |
308 | hdr = (struct ieee80211_hdr *)skb->data; |
309 | ||
76d5a9e8 | 310 | tx_info = IEEE80211_SKB_CB(skb); |
827e69bf | 311 | hw = bf->aphy->hw; |
76d5a9e8 | 312 | |
1286ec6d | 313 | rcu_read_lock(); |
f078f209 | 314 | |
5ed176e1 | 315 | /* XXX: use ieee80211_find_sta! */ |
76d5a9e8 | 316 | sta = ieee80211_find_sta_by_hw(hw, hdr->addr1); |
1286ec6d S |
317 | if (!sta) { |
318 | rcu_read_unlock(); | |
319 | return; | |
f078f209 LR |
320 | } |
321 | ||
1286ec6d S |
322 | an = (struct ath_node *)sta->drv_priv; |
323 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
324 | ||
e8324357 | 325 | isaggr = bf_isaggr(bf); |
d43f3015 | 326 | memset(ba, 0, WME_BA_BMP_SIZE >> 3); |
f078f209 | 327 | |
d43f3015 | 328 | if (isaggr && txok) { |
db1a052b FF |
329 | if (ts->ts_flags & ATH9K_TX_BA) { |
330 | seq_st = ts->ts_seqnum; | |
331 | memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); | |
e8324357 | 332 | } else { |
d43f3015 S |
333 | /* |
334 | * AR5416 can become deaf/mute when BA | |
335 | * issue happens. Chip needs to be reset. | |
336 | * But AP code may have sychronization issues | |
337 | * when perform internal reset in this routine. | |
338 | * Only enable reset in STA mode for now. | |
339 | */ | |
2660b81a | 340 | if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) |
d43f3015 | 341 | needreset = 1; |
e8324357 | 342 | } |
f078f209 LR |
343 | } |
344 | ||
e8324357 S |
345 | INIT_LIST_HEAD(&bf_pending); |
346 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 347 | |
db1a052b | 348 | nbad = ath_tx_num_badfrms(sc, bf, ts, txok); |
e8324357 S |
349 | while (bf) { |
350 | txfail = txpending = 0; | |
351 | bf_next = bf->bf_next; | |
f078f209 | 352 | |
e8324357 S |
353 | if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) { |
354 | /* transmit completion, subframe is | |
355 | * acked by block ack */ | |
0934af23 | 356 | acked_cnt++; |
e8324357 S |
357 | } else if (!isaggr && txok) { |
358 | /* transmit completion */ | |
0934af23 | 359 | acked_cnt++; |
e8324357 | 360 | } else { |
e8324357 | 361 | if (!(tid->state & AGGR_CLEANUP) && |
6d913f7d | 362 | !bf_last->bf_tx_aborted) { |
e8324357 | 363 | if (bf->bf_retries < ATH_MAX_SW_RETRIES) { |
fec247c0 | 364 | ath_tx_set_retry(sc, txq, bf); |
e8324357 S |
365 | txpending = 1; |
366 | } else { | |
367 | bf->bf_state.bf_type |= BUF_XRETRY; | |
368 | txfail = 1; | |
369 | sendbar = 1; | |
0934af23 | 370 | txfail_cnt++; |
e8324357 S |
371 | } |
372 | } else { | |
373 | /* | |
374 | * cleanup in progress, just fail | |
375 | * the un-acked sub-frames | |
376 | */ | |
377 | txfail = 1; | |
378 | } | |
379 | } | |
f078f209 | 380 | |
e5003249 VT |
381 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && |
382 | bf_next == NULL) { | |
cbfe89c6 VT |
383 | /* |
384 | * Make sure the last desc is reclaimed if it | |
385 | * not a holding desc. | |
386 | */ | |
387 | if (!bf_last->bf_stale) | |
388 | list_move_tail(&bf->list, &bf_head); | |
389 | else | |
390 | INIT_LIST_HEAD(&bf_head); | |
e8324357 | 391 | } else { |
9680e8a3 | 392 | BUG_ON(list_empty(bf_q)); |
d43f3015 | 393 | list_move_tail(&bf->list, &bf_head); |
e8324357 | 394 | } |
f078f209 | 395 | |
e8324357 S |
396 | if (!txpending) { |
397 | /* | |
398 | * complete the acked-ones/xretried ones; update | |
399 | * block-ack window | |
400 | */ | |
401 | spin_lock_bh(&txq->axq_lock); | |
402 | ath_tx_update_baw(sc, tid, bf->bf_seqno); | |
403 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 | 404 | |
8a92e2ee | 405 | if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) { |
db1a052b | 406 | ath_tx_rc_status(bf, ts, nbad, txok, true); |
8a92e2ee VT |
407 | rc_update = false; |
408 | } else { | |
db1a052b | 409 | ath_tx_rc_status(bf, ts, nbad, txok, false); |
8a92e2ee VT |
410 | } |
411 | ||
db1a052b FF |
412 | ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, |
413 | !txfail, sendbar); | |
e8324357 | 414 | } else { |
d43f3015 | 415 | /* retry the un-acked ones */ |
e5003249 VT |
416 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) { |
417 | if (bf->bf_next == NULL && bf_last->bf_stale) { | |
418 | struct ath_buf *tbf; | |
419 | ||
420 | tbf = ath_clone_txbuf(sc, bf_last); | |
421 | /* | |
422 | * Update tx baw and complete the | |
423 | * frame with failed status if we | |
424 | * run out of tx buf. | |
425 | */ | |
426 | if (!tbf) { | |
427 | spin_lock_bh(&txq->axq_lock); | |
428 | ath_tx_update_baw(sc, tid, | |
429 | bf->bf_seqno); | |
430 | spin_unlock_bh(&txq->axq_lock); | |
431 | ||
432 | bf->bf_state.bf_type |= | |
433 | BUF_XRETRY; | |
434 | ath_tx_rc_status(bf, ts, nbad, | |
435 | 0, false); | |
436 | ath_tx_complete_buf(sc, bf, txq, | |
437 | &bf_head, | |
438 | ts, 0, 0); | |
439 | break; | |
440 | } | |
441 | ||
442 | ath9k_hw_cleartxdesc(sc->sc_ah, | |
443 | tbf->bf_desc); | |
444 | list_add_tail(&tbf->list, &bf_head); | |
445 | } else { | |
446 | /* | |
447 | * Clear descriptor status words for | |
448 | * software retry | |
449 | */ | |
450 | ath9k_hw_cleartxdesc(sc->sc_ah, | |
451 | bf->bf_desc); | |
c41d92dc | 452 | } |
e8324357 S |
453 | } |
454 | ||
455 | /* | |
456 | * Put this buffer to the temporary pending | |
457 | * queue to retain ordering | |
458 | */ | |
459 | list_splice_tail_init(&bf_head, &bf_pending); | |
460 | } | |
461 | ||
462 | bf = bf_next; | |
f078f209 | 463 | } |
f078f209 | 464 | |
e8324357 | 465 | if (tid->state & AGGR_CLEANUP) { |
e8324357 S |
466 | if (tid->baw_head == tid->baw_tail) { |
467 | tid->state &= ~AGGR_ADDBA_COMPLETE; | |
e8324357 | 468 | tid->state &= ~AGGR_CLEANUP; |
e63835b0 | 469 | |
e8324357 S |
470 | /* send buffered frames as singles */ |
471 | ath_tx_flush_tid(sc, tid); | |
d43f3015 | 472 | } |
1286ec6d | 473 | rcu_read_unlock(); |
e8324357 S |
474 | return; |
475 | } | |
f078f209 | 476 | |
d43f3015 | 477 | /* prepend un-acked frames to the beginning of the pending frame queue */ |
e8324357 S |
478 | if (!list_empty(&bf_pending)) { |
479 | spin_lock_bh(&txq->axq_lock); | |
480 | list_splice(&bf_pending, &tid->buf_q); | |
481 | ath_tx_queue_tid(txq, tid); | |
482 | spin_unlock_bh(&txq->axq_lock); | |
483 | } | |
102e0572 | 484 | |
1286ec6d S |
485 | rcu_read_unlock(); |
486 | ||
e8324357 S |
487 | if (needreset) |
488 | ath_reset(sc, false); | |
e8324357 | 489 | } |
f078f209 | 490 | |
e8324357 S |
491 | static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf, |
492 | struct ath_atx_tid *tid) | |
f078f209 | 493 | { |
528f0c6b S |
494 | struct sk_buff *skb; |
495 | struct ieee80211_tx_info *tx_info; | |
a8efee4f | 496 | struct ieee80211_tx_rate *rates; |
d43f3015 | 497 | u32 max_4ms_framelen, frmlen; |
4ef70841 | 498 | u16 aggr_limit, legacy = 0; |
e8324357 | 499 | int i; |
528f0c6b | 500 | |
a22be22a | 501 | skb = bf->bf_mpdu; |
528f0c6b | 502 | tx_info = IEEE80211_SKB_CB(skb); |
e63835b0 | 503 | rates = tx_info->control.rates; |
528f0c6b | 504 | |
e8324357 S |
505 | /* |
506 | * Find the lowest frame length among the rate series that will have a | |
507 | * 4ms transmit duration. | |
508 | * TODO - TXOP limit needs to be considered. | |
509 | */ | |
510 | max_4ms_framelen = ATH_AMPDU_LIMIT_MAX; | |
e63835b0 | 511 | |
e8324357 S |
512 | for (i = 0; i < 4; i++) { |
513 | if (rates[i].count) { | |
545750d3 FF |
514 | int modeidx; |
515 | if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) { | |
e8324357 S |
516 | legacy = 1; |
517 | break; | |
518 | } | |
519 | ||
545750d3 FF |
520 | if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) |
521 | modeidx = MCS_HT40_SGI; | |
522 | else if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) | |
523 | modeidx = MCS_HT40; | |
524 | else | |
525 | modeidx = MCS_DEFAULT; | |
526 | ||
527 | frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx]; | |
d43f3015 | 528 | max_4ms_framelen = min(max_4ms_framelen, frmlen); |
f078f209 LR |
529 | } |
530 | } | |
e63835b0 | 531 | |
f078f209 | 532 | /* |
e8324357 S |
533 | * limit aggregate size by the minimum rate if rate selected is |
534 | * not a probe rate, if rate selected is a probe rate then | |
535 | * avoid aggregation of this packet. | |
f078f209 | 536 | */ |
e8324357 S |
537 | if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy) |
538 | return 0; | |
f078f209 | 539 | |
1773912b VT |
540 | if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED) |
541 | aggr_limit = min((max_4ms_framelen * 3) / 8, | |
542 | (u32)ATH_AMPDU_LIMIT_MAX); | |
543 | else | |
544 | aggr_limit = min(max_4ms_framelen, | |
545 | (u32)ATH_AMPDU_LIMIT_MAX); | |
f078f209 | 546 | |
e8324357 S |
547 | /* |
548 | * h/w can accept aggregates upto 16 bit lengths (65535). | |
549 | * The IE, however can hold upto 65536, which shows up here | |
550 | * as zero. Ignore 65536 since we are constrained by hw. | |
f078f209 | 551 | */ |
4ef70841 S |
552 | if (tid->an->maxampdu) |
553 | aggr_limit = min(aggr_limit, tid->an->maxampdu); | |
f078f209 | 554 | |
e8324357 S |
555 | return aggr_limit; |
556 | } | |
f078f209 | 557 | |
e8324357 | 558 | /* |
d43f3015 | 559 | * Returns the number of delimiters to be added to |
e8324357 | 560 | * meet the minimum required mpdudensity. |
e8324357 S |
561 | */ |
562 | static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid, | |
563 | struct ath_buf *bf, u16 frmlen) | |
564 | { | |
e8324357 S |
565 | struct sk_buff *skb = bf->bf_mpdu; |
566 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
4ef70841 | 567 | u32 nsymbits, nsymbols; |
e8324357 | 568 | u16 minlen; |
545750d3 | 569 | u8 flags, rix; |
e8324357 S |
570 | int width, half_gi, ndelim, mindelim; |
571 | ||
572 | /* Select standard number of delimiters based on frame length alone */ | |
573 | ndelim = ATH_AGGR_GET_NDELIM(frmlen); | |
f078f209 LR |
574 | |
575 | /* | |
e8324357 S |
576 | * If encryption enabled, hardware requires some more padding between |
577 | * subframes. | |
578 | * TODO - this could be improved to be dependent on the rate. | |
579 | * The hardware can keep up at lower rates, but not higher rates | |
f078f209 | 580 | */ |
e8324357 S |
581 | if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) |
582 | ndelim += ATH_AGGR_ENCRYPTDELIM; | |
f078f209 | 583 | |
e8324357 S |
584 | /* |
585 | * Convert desired mpdu density from microeconds to bytes based | |
586 | * on highest rate in rate series (i.e. first rate) to determine | |
587 | * required minimum length for subframe. Take into account | |
588 | * whether high rate is 20 or 40Mhz and half or full GI. | |
4ef70841 | 589 | * |
e8324357 S |
590 | * If there is no mpdu density restriction, no further calculation |
591 | * is needed. | |
592 | */ | |
4ef70841 S |
593 | |
594 | if (tid->an->mpdudensity == 0) | |
e8324357 | 595 | return ndelim; |
f078f209 | 596 | |
e8324357 S |
597 | rix = tx_info->control.rates[0].idx; |
598 | flags = tx_info->control.rates[0].flags; | |
e8324357 S |
599 | width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0; |
600 | half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0; | |
f078f209 | 601 | |
e8324357 | 602 | if (half_gi) |
4ef70841 | 603 | nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity); |
e8324357 | 604 | else |
4ef70841 | 605 | nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity); |
f078f209 | 606 | |
e8324357 S |
607 | if (nsymbols == 0) |
608 | nsymbols = 1; | |
f078f209 | 609 | |
545750d3 | 610 | nsymbits = bits_per_symbol[rix][width]; |
e8324357 | 611 | minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; |
f078f209 | 612 | |
e8324357 | 613 | if (frmlen < minlen) { |
e8324357 S |
614 | mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ; |
615 | ndelim = max(mindelim, ndelim); | |
f078f209 LR |
616 | } |
617 | ||
e8324357 | 618 | return ndelim; |
f078f209 LR |
619 | } |
620 | ||
e8324357 | 621 | static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc, |
fec247c0 | 622 | struct ath_txq *txq, |
d43f3015 S |
623 | struct ath_atx_tid *tid, |
624 | struct list_head *bf_q) | |
f078f209 | 625 | { |
e8324357 | 626 | #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) |
d43f3015 S |
627 | struct ath_buf *bf, *bf_first, *bf_prev = NULL; |
628 | int rl = 0, nframes = 0, ndelim, prev_al = 0; | |
e8324357 S |
629 | u16 aggr_limit = 0, al = 0, bpad = 0, |
630 | al_delta, h_baw = tid->baw_size / 2; | |
631 | enum ATH_AGGR_STATUS status = ATH_AGGR_DONE; | |
f078f209 | 632 | |
e8324357 | 633 | bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list); |
f078f209 | 634 | |
e8324357 S |
635 | do { |
636 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); | |
f078f209 | 637 | |
d43f3015 | 638 | /* do not step over block-ack window */ |
e8324357 S |
639 | if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) { |
640 | status = ATH_AGGR_BAW_CLOSED; | |
641 | break; | |
642 | } | |
f078f209 | 643 | |
e8324357 S |
644 | if (!rl) { |
645 | aggr_limit = ath_lookup_rate(sc, bf, tid); | |
646 | rl = 1; | |
647 | } | |
f078f209 | 648 | |
d43f3015 | 649 | /* do not exceed aggregation limit */ |
e8324357 | 650 | al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen; |
f078f209 | 651 | |
d43f3015 S |
652 | if (nframes && |
653 | (aggr_limit < (al + bpad + al_delta + prev_al))) { | |
e8324357 S |
654 | status = ATH_AGGR_LIMITED; |
655 | break; | |
656 | } | |
f078f209 | 657 | |
d43f3015 S |
658 | /* do not exceed subframe limit */ |
659 | if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) { | |
e8324357 S |
660 | status = ATH_AGGR_LIMITED; |
661 | break; | |
662 | } | |
d43f3015 | 663 | nframes++; |
f078f209 | 664 | |
d43f3015 | 665 | /* add padding for previous frame to aggregation length */ |
e8324357 | 666 | al += bpad + al_delta; |
f078f209 | 667 | |
e8324357 S |
668 | /* |
669 | * Get the delimiters needed to meet the MPDU | |
670 | * density for this node. | |
671 | */ | |
672 | ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen); | |
e8324357 | 673 | bpad = PADBYTES(al_delta) + (ndelim << 2); |
f078f209 | 674 | |
e8324357 | 675 | bf->bf_next = NULL; |
87d5efbb | 676 | ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0); |
f078f209 | 677 | |
d43f3015 | 678 | /* link buffers of this frame to the aggregate */ |
e8324357 | 679 | ath_tx_addto_baw(sc, tid, bf); |
d43f3015 S |
680 | ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim); |
681 | list_move_tail(&bf->list, bf_q); | |
e8324357 S |
682 | if (bf_prev) { |
683 | bf_prev->bf_next = bf; | |
87d5efbb VT |
684 | ath9k_hw_set_desc_link(sc->sc_ah, bf_prev->bf_desc, |
685 | bf->bf_daddr); | |
e8324357 S |
686 | } |
687 | bf_prev = bf; | |
fec247c0 | 688 | |
e8324357 | 689 | } while (!list_empty(&tid->buf_q)); |
f078f209 | 690 | |
e8324357 S |
691 | bf_first->bf_al = al; |
692 | bf_first->bf_nframes = nframes; | |
d43f3015 | 693 | |
e8324357 S |
694 | return status; |
695 | #undef PADBYTES | |
696 | } | |
f078f209 | 697 | |
e8324357 S |
698 | static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq, |
699 | struct ath_atx_tid *tid) | |
700 | { | |
d43f3015 | 701 | struct ath_buf *bf; |
e8324357 S |
702 | enum ATH_AGGR_STATUS status; |
703 | struct list_head bf_q; | |
f078f209 | 704 | |
e8324357 S |
705 | do { |
706 | if (list_empty(&tid->buf_q)) | |
707 | return; | |
f078f209 | 708 | |
e8324357 S |
709 | INIT_LIST_HEAD(&bf_q); |
710 | ||
fec247c0 | 711 | status = ath_tx_form_aggr(sc, txq, tid, &bf_q); |
f078f209 | 712 | |
f078f209 | 713 | /* |
d43f3015 S |
714 | * no frames picked up to be aggregated; |
715 | * block-ack window is not open. | |
f078f209 | 716 | */ |
e8324357 S |
717 | if (list_empty(&bf_q)) |
718 | break; | |
f078f209 | 719 | |
e8324357 | 720 | bf = list_first_entry(&bf_q, struct ath_buf, list); |
d43f3015 | 721 | bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list); |
f078f209 | 722 | |
d43f3015 | 723 | /* if only one frame, send as non-aggregate */ |
e8324357 | 724 | if (bf->bf_nframes == 1) { |
e8324357 | 725 | bf->bf_state.bf_type &= ~BUF_AGGR; |
d43f3015 | 726 | ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc); |
e8324357 S |
727 | ath_buf_set_rate(sc, bf); |
728 | ath_tx_txqaddbuf(sc, txq, &bf_q); | |
729 | continue; | |
730 | } | |
f078f209 | 731 | |
d43f3015 | 732 | /* setup first desc of aggregate */ |
e8324357 S |
733 | bf->bf_state.bf_type |= BUF_AGGR; |
734 | ath_buf_set_rate(sc, bf); | |
735 | ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al); | |
f078f209 | 736 | |
d43f3015 S |
737 | /* anchor last desc of aggregate */ |
738 | ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc); | |
f078f209 | 739 | |
e8324357 | 740 | ath_tx_txqaddbuf(sc, txq, &bf_q); |
fec247c0 | 741 | TX_STAT_INC(txq->axq_qnum, a_aggr); |
f078f209 | 742 | |
e8324357 S |
743 | } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH && |
744 | status != ATH_AGGR_BAW_CLOSED); | |
745 | } | |
746 | ||
f83da965 S |
747 | void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, |
748 | u16 tid, u16 *ssn) | |
e8324357 S |
749 | { |
750 | struct ath_atx_tid *txtid; | |
751 | struct ath_node *an; | |
752 | ||
753 | an = (struct ath_node *)sta->drv_priv; | |
f83da965 S |
754 | txtid = ATH_AN_2_TID(an, tid); |
755 | txtid->state |= AGGR_ADDBA_PROGRESS; | |
756 | ath_tx_pause_tid(sc, txtid); | |
757 | *ssn = txtid->seq_start; | |
e8324357 | 758 | } |
f078f209 | 759 | |
f83da965 | 760 | void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) |
e8324357 S |
761 | { |
762 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
763 | struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid); | |
764 | struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum]; | |
db1a052b | 765 | struct ath_tx_status ts; |
e8324357 S |
766 | struct ath_buf *bf; |
767 | struct list_head bf_head; | |
db1a052b FF |
768 | |
769 | memset(&ts, 0, sizeof(ts)); | |
e8324357 | 770 | INIT_LIST_HEAD(&bf_head); |
f078f209 | 771 | |
e8324357 | 772 | if (txtid->state & AGGR_CLEANUP) |
f83da965 | 773 | return; |
f078f209 | 774 | |
e8324357 | 775 | if (!(txtid->state & AGGR_ADDBA_COMPLETE)) { |
5eae6592 | 776 | txtid->state &= ~AGGR_ADDBA_PROGRESS; |
f83da965 | 777 | return; |
e8324357 | 778 | } |
f078f209 | 779 | |
e8324357 S |
780 | ath_tx_pause_tid(sc, txtid); |
781 | ||
782 | /* drop all software retried frames and mark this TID */ | |
783 | spin_lock_bh(&txq->axq_lock); | |
784 | while (!list_empty(&txtid->buf_q)) { | |
785 | bf = list_first_entry(&txtid->buf_q, struct ath_buf, list); | |
786 | if (!bf_isretried(bf)) { | |
787 | /* | |
788 | * NB: it's based on the assumption that | |
789 | * software retried frame will always stay | |
790 | * at the head of software queue. | |
791 | */ | |
792 | break; | |
793 | } | |
d43f3015 | 794 | list_move_tail(&bf->list, &bf_head); |
e8324357 | 795 | ath_tx_update_baw(sc, txtid, bf->bf_seqno); |
db1a052b | 796 | ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0); |
f078f209 | 797 | } |
d43f3015 | 798 | spin_unlock_bh(&txq->axq_lock); |
f078f209 | 799 | |
e8324357 | 800 | if (txtid->baw_head != txtid->baw_tail) { |
e8324357 S |
801 | txtid->state |= AGGR_CLEANUP; |
802 | } else { | |
803 | txtid->state &= ~AGGR_ADDBA_COMPLETE; | |
e8324357 | 804 | ath_tx_flush_tid(sc, txtid); |
f078f209 | 805 | } |
e8324357 | 806 | } |
f078f209 | 807 | |
e8324357 S |
808 | void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) |
809 | { | |
810 | struct ath_atx_tid *txtid; | |
811 | struct ath_node *an; | |
812 | ||
813 | an = (struct ath_node *)sta->drv_priv; | |
814 | ||
815 | if (sc->sc_flags & SC_OP_TXAGGR) { | |
816 | txtid = ATH_AN_2_TID(an, tid); | |
817 | txtid->baw_size = | |
818 | IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor; | |
819 | txtid->state |= AGGR_ADDBA_COMPLETE; | |
820 | txtid->state &= ~AGGR_ADDBA_PROGRESS; | |
821 | ath_tx_resume_tid(sc, txtid); | |
822 | } | |
f078f209 LR |
823 | } |
824 | ||
e8324357 | 825 | bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno) |
c4288390 | 826 | { |
e8324357 | 827 | struct ath_atx_tid *txtid; |
c4288390 | 828 | |
e8324357 S |
829 | if (!(sc->sc_flags & SC_OP_TXAGGR)) |
830 | return false; | |
c4288390 | 831 | |
e8324357 S |
832 | txtid = ATH_AN_2_TID(an, tidno); |
833 | ||
c3d8f02e | 834 | if (!(txtid->state & (AGGR_ADDBA_COMPLETE | AGGR_ADDBA_PROGRESS))) |
e8324357 | 835 | return true; |
e8324357 | 836 | return false; |
c4288390 S |
837 | } |
838 | ||
e8324357 S |
839 | /********************/ |
840 | /* Queue Management */ | |
841 | /********************/ | |
f078f209 | 842 | |
e8324357 S |
843 | static void ath_txq_drain_pending_buffers(struct ath_softc *sc, |
844 | struct ath_txq *txq) | |
f078f209 | 845 | { |
e8324357 S |
846 | struct ath_atx_ac *ac, *ac_tmp; |
847 | struct ath_atx_tid *tid, *tid_tmp; | |
f078f209 | 848 | |
e8324357 S |
849 | list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) { |
850 | list_del(&ac->list); | |
851 | ac->sched = false; | |
852 | list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) { | |
853 | list_del(&tid->list); | |
854 | tid->sched = false; | |
855 | ath_tid_drain(sc, txq, tid); | |
856 | } | |
f078f209 LR |
857 | } |
858 | } | |
859 | ||
e8324357 | 860 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) |
f078f209 | 861 | { |
cbe61d8a | 862 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 863 | struct ath_common *common = ath9k_hw_common(ah); |
e8324357 | 864 | struct ath9k_tx_queue_info qi; |
e5003249 | 865 | int qnum, i; |
f078f209 | 866 | |
e8324357 S |
867 | memset(&qi, 0, sizeof(qi)); |
868 | qi.tqi_subtype = subtype; | |
869 | qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT; | |
870 | qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT; | |
871 | qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT; | |
872 | qi.tqi_physCompBuf = 0; | |
f078f209 LR |
873 | |
874 | /* | |
e8324357 S |
875 | * Enable interrupts only for EOL and DESC conditions. |
876 | * We mark tx descriptors to receive a DESC interrupt | |
877 | * when a tx queue gets deep; otherwise waiting for the | |
878 | * EOL to reap descriptors. Note that this is done to | |
879 | * reduce interrupt load and this only defers reaping | |
880 | * descriptors, never transmitting frames. Aside from | |
881 | * reducing interrupts this also permits more concurrency. | |
882 | * The only potential downside is if the tx queue backs | |
883 | * up in which case the top half of the kernel may backup | |
884 | * due to a lack of tx descriptors. | |
885 | * | |
886 | * The UAPSD queue is an exception, since we take a desc- | |
887 | * based intr on the EOSP frames. | |
f078f209 | 888 | */ |
e8324357 S |
889 | if (qtype == ATH9K_TX_QUEUE_UAPSD) |
890 | qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; | |
891 | else | |
892 | qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | | |
893 | TXQ_FLAG_TXDESCINT_ENABLE; | |
894 | qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); | |
895 | if (qnum == -1) { | |
f078f209 | 896 | /* |
e8324357 S |
897 | * NB: don't print a message, this happens |
898 | * normally on parts with too few tx queues | |
f078f209 | 899 | */ |
e8324357 | 900 | return NULL; |
f078f209 | 901 | } |
e8324357 | 902 | if (qnum >= ARRAY_SIZE(sc->tx.txq)) { |
c46917bb LR |
903 | ath_print(common, ATH_DBG_FATAL, |
904 | "qnum %u out of range, max %u!\n", | |
905 | qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq)); | |
e8324357 S |
906 | ath9k_hw_releasetxqueue(ah, qnum); |
907 | return NULL; | |
908 | } | |
909 | if (!ATH_TXQ_SETUP(sc, qnum)) { | |
910 | struct ath_txq *txq = &sc->tx.txq[qnum]; | |
f078f209 | 911 | |
e8324357 S |
912 | txq->axq_qnum = qnum; |
913 | txq->axq_link = NULL; | |
914 | INIT_LIST_HEAD(&txq->axq_q); | |
915 | INIT_LIST_HEAD(&txq->axq_acq); | |
916 | spin_lock_init(&txq->axq_lock); | |
917 | txq->axq_depth = 0; | |
164ace38 | 918 | txq->axq_tx_inprogress = false; |
e8324357 | 919 | sc->tx.txqsetup |= 1<<qnum; |
e5003249 VT |
920 | |
921 | txq->txq_headidx = txq->txq_tailidx = 0; | |
922 | for (i = 0; i < ATH_TXFIFO_DEPTH; i++) | |
923 | INIT_LIST_HEAD(&txq->txq_fifo[i]); | |
924 | INIT_LIST_HEAD(&txq->txq_fifo_pending); | |
e8324357 S |
925 | } |
926 | return &sc->tx.txq[qnum]; | |
f078f209 LR |
927 | } |
928 | ||
1773912b | 929 | int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype) |
f078f209 | 930 | { |
e8324357 | 931 | int qnum; |
f078f209 | 932 | |
e8324357 S |
933 | switch (qtype) { |
934 | case ATH9K_TX_QUEUE_DATA: | |
935 | if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { | |
c46917bb LR |
936 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
937 | "HAL AC %u out of range, max %zu!\n", | |
938 | haltype, ARRAY_SIZE(sc->tx.hwq_map)); | |
e8324357 S |
939 | return -1; |
940 | } | |
941 | qnum = sc->tx.hwq_map[haltype]; | |
942 | break; | |
943 | case ATH9K_TX_QUEUE_BEACON: | |
944 | qnum = sc->beacon.beaconq; | |
945 | break; | |
946 | case ATH9K_TX_QUEUE_CAB: | |
947 | qnum = sc->beacon.cabq->axq_qnum; | |
948 | break; | |
949 | default: | |
950 | qnum = -1; | |
951 | } | |
952 | return qnum; | |
953 | } | |
f078f209 | 954 | |
e8324357 S |
955 | struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb) |
956 | { | |
957 | struct ath_txq *txq = NULL; | |
f52de03b | 958 | u16 skb_queue = skb_get_queue_mapping(skb); |
e8324357 | 959 | int qnum; |
f078f209 | 960 | |
f52de03b | 961 | qnum = ath_get_hal_qnum(skb_queue, sc); |
e8324357 | 962 | txq = &sc->tx.txq[qnum]; |
f078f209 | 963 | |
e8324357 S |
964 | spin_lock_bh(&txq->axq_lock); |
965 | ||
966 | if (txq->axq_depth >= (ATH_TXBUF - 20)) { | |
c46917bb LR |
967 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_XMIT, |
968 | "TX queue: %d is full, depth: %d\n", | |
969 | qnum, txq->axq_depth); | |
f52de03b | 970 | ath_mac80211_stop_queue(sc, skb_queue); |
e8324357 S |
971 | txq->stopped = 1; |
972 | spin_unlock_bh(&txq->axq_lock); | |
973 | return NULL; | |
f078f209 LR |
974 | } |
975 | ||
e8324357 S |
976 | spin_unlock_bh(&txq->axq_lock); |
977 | ||
978 | return txq; | |
979 | } | |
980 | ||
981 | int ath_txq_update(struct ath_softc *sc, int qnum, | |
982 | struct ath9k_tx_queue_info *qinfo) | |
983 | { | |
cbe61d8a | 984 | struct ath_hw *ah = sc->sc_ah; |
e8324357 S |
985 | int error = 0; |
986 | struct ath9k_tx_queue_info qi; | |
987 | ||
988 | if (qnum == sc->beacon.beaconq) { | |
989 | /* | |
990 | * XXX: for beacon queue, we just save the parameter. | |
991 | * It will be picked up by ath_beaconq_config when | |
992 | * it's necessary. | |
993 | */ | |
994 | sc->beacon.beacon_qi = *qinfo; | |
f078f209 | 995 | return 0; |
e8324357 | 996 | } |
f078f209 | 997 | |
9680e8a3 | 998 | BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum); |
e8324357 S |
999 | |
1000 | ath9k_hw_get_txq_props(ah, qnum, &qi); | |
1001 | qi.tqi_aifs = qinfo->tqi_aifs; | |
1002 | qi.tqi_cwmin = qinfo->tqi_cwmin; | |
1003 | qi.tqi_cwmax = qinfo->tqi_cwmax; | |
1004 | qi.tqi_burstTime = qinfo->tqi_burstTime; | |
1005 | qi.tqi_readyTime = qinfo->tqi_readyTime; | |
1006 | ||
1007 | if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { | |
c46917bb LR |
1008 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
1009 | "Unable to update hardware queue %u!\n", qnum); | |
e8324357 S |
1010 | error = -EIO; |
1011 | } else { | |
1012 | ath9k_hw_resettxqueue(ah, qnum); | |
1013 | } | |
1014 | ||
1015 | return error; | |
1016 | } | |
1017 | ||
1018 | int ath_cabq_update(struct ath_softc *sc) | |
1019 | { | |
1020 | struct ath9k_tx_queue_info qi; | |
1021 | int qnum = sc->beacon.cabq->axq_qnum; | |
f078f209 | 1022 | |
e8324357 | 1023 | ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi); |
f078f209 | 1024 | /* |
e8324357 | 1025 | * Ensure the readytime % is within the bounds. |
f078f209 | 1026 | */ |
17d7904d S |
1027 | if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND) |
1028 | sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND; | |
1029 | else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND) | |
1030 | sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND; | |
f078f209 | 1031 | |
57c4d7b4 | 1032 | qi.tqi_readyTime = (sc->beacon_interval * |
fdbf7335 | 1033 | sc->config.cabqReadytime) / 100; |
e8324357 S |
1034 | ath_txq_update(sc, qnum, &qi); |
1035 | ||
1036 | return 0; | |
f078f209 LR |
1037 | } |
1038 | ||
043a0405 S |
1039 | /* |
1040 | * Drain a given TX queue (could be Beacon or Data) | |
1041 | * | |
1042 | * This assumes output has been stopped and | |
1043 | * we do not need to block ath_tx_tasklet. | |
1044 | */ | |
1045 | void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx) | |
f078f209 | 1046 | { |
e8324357 S |
1047 | struct ath_buf *bf, *lastbf; |
1048 | struct list_head bf_head; | |
db1a052b FF |
1049 | struct ath_tx_status ts; |
1050 | ||
1051 | memset(&ts, 0, sizeof(ts)); | |
e8324357 | 1052 | INIT_LIST_HEAD(&bf_head); |
f078f209 | 1053 | |
e8324357 S |
1054 | for (;;) { |
1055 | spin_lock_bh(&txq->axq_lock); | |
f078f209 | 1056 | |
e5003249 VT |
1057 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
1058 | if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) { | |
1059 | txq->txq_headidx = txq->txq_tailidx = 0; | |
1060 | spin_unlock_bh(&txq->axq_lock); | |
1061 | break; | |
1062 | } else { | |
1063 | bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx], | |
1064 | struct ath_buf, list); | |
1065 | } | |
1066 | } else { | |
1067 | if (list_empty(&txq->axq_q)) { | |
1068 | txq->axq_link = NULL; | |
1069 | spin_unlock_bh(&txq->axq_lock); | |
1070 | break; | |
1071 | } | |
1072 | bf = list_first_entry(&txq->axq_q, struct ath_buf, | |
1073 | list); | |
f078f209 | 1074 | |
e5003249 VT |
1075 | if (bf->bf_stale) { |
1076 | list_del(&bf->list); | |
1077 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 | 1078 | |
e5003249 VT |
1079 | spin_lock_bh(&sc->tx.txbuflock); |
1080 | list_add_tail(&bf->list, &sc->tx.txbuf); | |
1081 | spin_unlock_bh(&sc->tx.txbuflock); | |
1082 | continue; | |
1083 | } | |
e8324357 | 1084 | } |
f078f209 | 1085 | |
e8324357 | 1086 | lastbf = bf->bf_lastbf; |
6d913f7d VT |
1087 | if (!retry_tx) |
1088 | lastbf->bf_tx_aborted = true; | |
f078f209 | 1089 | |
e5003249 VT |
1090 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
1091 | list_cut_position(&bf_head, | |
1092 | &txq->txq_fifo[txq->txq_tailidx], | |
1093 | &lastbf->list); | |
1094 | INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH); | |
1095 | } else { | |
1096 | /* remove ath_buf's of the same mpdu from txq */ | |
1097 | list_cut_position(&bf_head, &txq->axq_q, &lastbf->list); | |
1098 | } | |
1099 | ||
e8324357 | 1100 | txq->axq_depth--; |
f078f209 | 1101 | |
e8324357 S |
1102 | spin_unlock_bh(&txq->axq_lock); |
1103 | ||
1104 | if (bf_isampdu(bf)) | |
db1a052b | 1105 | ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0); |
e8324357 | 1106 | else |
db1a052b | 1107 | ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0); |
f078f209 LR |
1108 | } |
1109 | ||
164ace38 SB |
1110 | spin_lock_bh(&txq->axq_lock); |
1111 | txq->axq_tx_inprogress = false; | |
1112 | spin_unlock_bh(&txq->axq_lock); | |
1113 | ||
e8324357 S |
1114 | /* flush any pending frames if aggregation is enabled */ |
1115 | if (sc->sc_flags & SC_OP_TXAGGR) { | |
1116 | if (!retry_tx) { | |
1117 | spin_lock_bh(&txq->axq_lock); | |
1118 | ath_txq_drain_pending_buffers(sc, txq); | |
1119 | spin_unlock_bh(&txq->axq_lock); | |
1120 | } | |
1121 | } | |
e5003249 VT |
1122 | |
1123 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { | |
1124 | spin_lock_bh(&txq->axq_lock); | |
1125 | while (!list_empty(&txq->txq_fifo_pending)) { | |
1126 | bf = list_first_entry(&txq->txq_fifo_pending, | |
1127 | struct ath_buf, list); | |
1128 | list_cut_position(&bf_head, | |
1129 | &txq->txq_fifo_pending, | |
1130 | &bf->bf_lastbf->list); | |
1131 | spin_unlock_bh(&txq->axq_lock); | |
1132 | ||
1133 | if (bf_isampdu(bf)) | |
1134 | ath_tx_complete_aggr(sc, txq, bf, &bf_head, | |
1135 | &ts, 0); | |
1136 | else | |
1137 | ath_tx_complete_buf(sc, bf, txq, &bf_head, | |
1138 | &ts, 0, 0); | |
1139 | spin_lock_bh(&txq->axq_lock); | |
1140 | } | |
1141 | spin_unlock_bh(&txq->axq_lock); | |
1142 | } | |
f078f209 LR |
1143 | } |
1144 | ||
043a0405 | 1145 | void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) |
f078f209 | 1146 | { |
cbe61d8a | 1147 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1148 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
043a0405 S |
1149 | struct ath_txq *txq; |
1150 | int i, npend = 0; | |
1151 | ||
1152 | if (sc->sc_flags & SC_OP_INVALID) | |
1153 | return; | |
1154 | ||
1155 | /* Stop beacon queue */ | |
1156 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
1157 | ||
1158 | /* Stop data queues */ | |
1159 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1160 | if (ATH_TXQ_SETUP(sc, i)) { | |
1161 | txq = &sc->tx.txq[i]; | |
1162 | ath9k_hw_stoptxdma(ah, txq->axq_qnum); | |
1163 | npend += ath9k_hw_numtxpending(ah, txq->axq_qnum); | |
1164 | } | |
1165 | } | |
1166 | ||
1167 | if (npend) { | |
1168 | int r; | |
1169 | ||
e8009e98 | 1170 | ath_print(common, ATH_DBG_FATAL, |
c46917bb | 1171 | "Unable to stop TxDMA. Reset HAL!\n"); |
043a0405 S |
1172 | |
1173 | spin_lock_bh(&sc->sc_resetlock); | |
e8009e98 | 1174 | r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false); |
043a0405 | 1175 | if (r) |
c46917bb LR |
1176 | ath_print(common, ATH_DBG_FATAL, |
1177 | "Unable to reset hardware; reset status %d\n", | |
1178 | r); | |
043a0405 S |
1179 | spin_unlock_bh(&sc->sc_resetlock); |
1180 | } | |
1181 | ||
1182 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1183 | if (ATH_TXQ_SETUP(sc, i)) | |
1184 | ath_draintxq(sc, &sc->tx.txq[i], retry_tx); | |
1185 | } | |
e8324357 | 1186 | } |
f078f209 | 1187 | |
043a0405 | 1188 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) |
e8324357 | 1189 | { |
043a0405 S |
1190 | ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum); |
1191 | sc->tx.txqsetup &= ~(1<<txq->axq_qnum); | |
e8324357 | 1192 | } |
f078f209 | 1193 | |
e8324357 S |
1194 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) |
1195 | { | |
1196 | struct ath_atx_ac *ac; | |
1197 | struct ath_atx_tid *tid; | |
f078f209 | 1198 | |
e8324357 S |
1199 | if (list_empty(&txq->axq_acq)) |
1200 | return; | |
f078f209 | 1201 | |
e8324357 S |
1202 | ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list); |
1203 | list_del(&ac->list); | |
1204 | ac->sched = false; | |
f078f209 | 1205 | |
e8324357 S |
1206 | do { |
1207 | if (list_empty(&ac->tid_q)) | |
1208 | return; | |
f078f209 | 1209 | |
e8324357 S |
1210 | tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list); |
1211 | list_del(&tid->list); | |
1212 | tid->sched = false; | |
f078f209 | 1213 | |
e8324357 S |
1214 | if (tid->paused) |
1215 | continue; | |
f078f209 | 1216 | |
164ace38 | 1217 | ath_tx_sched_aggr(sc, txq, tid); |
f078f209 LR |
1218 | |
1219 | /* | |
e8324357 S |
1220 | * add tid to round-robin queue if more frames |
1221 | * are pending for the tid | |
f078f209 | 1222 | */ |
e8324357 S |
1223 | if (!list_empty(&tid->buf_q)) |
1224 | ath_tx_queue_tid(txq, tid); | |
f078f209 | 1225 | |
e8324357 S |
1226 | break; |
1227 | } while (!list_empty(&ac->tid_q)); | |
f078f209 | 1228 | |
e8324357 S |
1229 | if (!list_empty(&ac->tid_q)) { |
1230 | if (!ac->sched) { | |
1231 | ac->sched = true; | |
1232 | list_add_tail(&ac->list, &txq->axq_acq); | |
f078f209 | 1233 | } |
e8324357 S |
1234 | } |
1235 | } | |
f078f209 | 1236 | |
e8324357 S |
1237 | int ath_tx_setup(struct ath_softc *sc, int haltype) |
1238 | { | |
1239 | struct ath_txq *txq; | |
f078f209 | 1240 | |
e8324357 | 1241 | if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { |
c46917bb LR |
1242 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
1243 | "HAL AC %u out of range, max %zu!\n", | |
e8324357 S |
1244 | haltype, ARRAY_SIZE(sc->tx.hwq_map)); |
1245 | return 0; | |
1246 | } | |
1247 | txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype); | |
1248 | if (txq != NULL) { | |
1249 | sc->tx.hwq_map[haltype] = txq->axq_qnum; | |
1250 | return 1; | |
1251 | } else | |
1252 | return 0; | |
f078f209 LR |
1253 | } |
1254 | ||
e8324357 S |
1255 | /***********/ |
1256 | /* TX, DMA */ | |
1257 | /***********/ | |
1258 | ||
f078f209 | 1259 | /* |
e8324357 S |
1260 | * Insert a chain of ath_buf (descriptors) on a txq and |
1261 | * assume the descriptors are already chained together by caller. | |
f078f209 | 1262 | */ |
e8324357 S |
1263 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, |
1264 | struct list_head *head) | |
f078f209 | 1265 | { |
cbe61d8a | 1266 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1267 | struct ath_common *common = ath9k_hw_common(ah); |
e8324357 | 1268 | struct ath_buf *bf; |
f078f209 | 1269 | |
e8324357 S |
1270 | /* |
1271 | * Insert the frame on the outbound list and | |
1272 | * pass it on to the hardware. | |
1273 | */ | |
f078f209 | 1274 | |
e8324357 S |
1275 | if (list_empty(head)) |
1276 | return; | |
f078f209 | 1277 | |
e8324357 | 1278 | bf = list_first_entry(head, struct ath_buf, list); |
f078f209 | 1279 | |
c46917bb LR |
1280 | ath_print(common, ATH_DBG_QUEUE, |
1281 | "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth); | |
f078f209 | 1282 | |
e5003249 VT |
1283 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
1284 | if (txq->axq_depth >= ATH_TXFIFO_DEPTH) { | |
1285 | list_splice_tail_init(head, &txq->txq_fifo_pending); | |
1286 | return; | |
1287 | } | |
1288 | if (!list_empty(&txq->txq_fifo[txq->txq_headidx])) | |
1289 | ath_print(common, ATH_DBG_XMIT, | |
1290 | "Initializing tx fifo %d which " | |
1291 | "is non-empty\n", | |
1292 | txq->txq_headidx); | |
1293 | INIT_LIST_HEAD(&txq->txq_fifo[txq->txq_headidx]); | |
1294 | list_splice_init(head, &txq->txq_fifo[txq->txq_headidx]); | |
1295 | INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH); | |
e8324357 | 1296 | ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); |
c46917bb LR |
1297 | ath_print(common, ATH_DBG_XMIT, |
1298 | "TXDP[%u] = %llx (%p)\n", | |
1299 | txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); | |
e8324357 | 1300 | } else { |
e5003249 VT |
1301 | list_splice_tail_init(head, &txq->axq_q); |
1302 | ||
1303 | if (txq->axq_link == NULL) { | |
1304 | ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); | |
1305 | ath_print(common, ATH_DBG_XMIT, | |
1306 | "TXDP[%u] = %llx (%p)\n", | |
1307 | txq->axq_qnum, ito64(bf->bf_daddr), | |
1308 | bf->bf_desc); | |
1309 | } else { | |
1310 | *txq->axq_link = bf->bf_daddr; | |
1311 | ath_print(common, ATH_DBG_XMIT, | |
1312 | "link[%u] (%p)=%llx (%p)\n", | |
1313 | txq->axq_qnum, txq->axq_link, | |
1314 | ito64(bf->bf_daddr), bf->bf_desc); | |
1315 | } | |
1316 | ath9k_hw_get_desc_link(ah, bf->bf_lastbf->bf_desc, | |
1317 | &txq->axq_link); | |
1318 | ath9k_hw_txstart(ah, txq->axq_qnum); | |
e8324357 | 1319 | } |
e5003249 | 1320 | txq->axq_depth++; |
e8324357 | 1321 | } |
f078f209 | 1322 | |
e8324357 S |
1323 | static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc) |
1324 | { | |
1325 | struct ath_buf *bf = NULL; | |
f078f209 | 1326 | |
e8324357 | 1327 | spin_lock_bh(&sc->tx.txbuflock); |
f078f209 | 1328 | |
e8324357 S |
1329 | if (unlikely(list_empty(&sc->tx.txbuf))) { |
1330 | spin_unlock_bh(&sc->tx.txbuflock); | |
1331 | return NULL; | |
1332 | } | |
f078f209 | 1333 | |
e8324357 S |
1334 | bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); |
1335 | list_del(&bf->list); | |
f078f209 | 1336 | |
e8324357 | 1337 | spin_unlock_bh(&sc->tx.txbuflock); |
f078f209 | 1338 | |
e8324357 | 1339 | return bf; |
f078f209 LR |
1340 | } |
1341 | ||
e8324357 S |
1342 | static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid, |
1343 | struct list_head *bf_head, | |
1344 | struct ath_tx_control *txctl) | |
f078f209 LR |
1345 | { |
1346 | struct ath_buf *bf; | |
f078f209 | 1347 | |
e8324357 S |
1348 | bf = list_first_entry(bf_head, struct ath_buf, list); |
1349 | bf->bf_state.bf_type |= BUF_AMPDU; | |
fec247c0 | 1350 | TX_STAT_INC(txctl->txq->axq_qnum, a_queued); |
f078f209 | 1351 | |
e8324357 S |
1352 | /* |
1353 | * Do not queue to h/w when any of the following conditions is true: | |
1354 | * - there are pending frames in software queue | |
1355 | * - the TID is currently paused for ADDBA/BAR request | |
1356 | * - seqno is not within block-ack window | |
1357 | * - h/w queue depth exceeds low water mark | |
1358 | */ | |
1359 | if (!list_empty(&tid->buf_q) || tid->paused || | |
1360 | !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) || | |
1361 | txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) { | |
f078f209 | 1362 | /* |
e8324357 S |
1363 | * Add this frame to software queue for scheduling later |
1364 | * for aggregation. | |
f078f209 | 1365 | */ |
d43f3015 | 1366 | list_move_tail(&bf->list, &tid->buf_q); |
e8324357 S |
1367 | ath_tx_queue_tid(txctl->txq, tid); |
1368 | return; | |
1369 | } | |
1370 | ||
1371 | /* Add sub-frame to BAW */ | |
1372 | ath_tx_addto_baw(sc, tid, bf); | |
1373 | ||
1374 | /* Queue to h/w without aggregation */ | |
1375 | bf->bf_nframes = 1; | |
d43f3015 | 1376 | bf->bf_lastbf = bf; |
e8324357 S |
1377 | ath_buf_set_rate(sc, bf); |
1378 | ath_tx_txqaddbuf(sc, txctl->txq, bf_head); | |
e8324357 S |
1379 | } |
1380 | ||
c37452b0 S |
1381 | static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq, |
1382 | struct ath_atx_tid *tid, | |
1383 | struct list_head *bf_head) | |
e8324357 S |
1384 | { |
1385 | struct ath_buf *bf; | |
1386 | ||
e8324357 S |
1387 | bf = list_first_entry(bf_head, struct ath_buf, list); |
1388 | bf->bf_state.bf_type &= ~BUF_AMPDU; | |
1389 | ||
1390 | /* update starting sequence number for subsequent ADDBA request */ | |
1391 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); | |
1392 | ||
1393 | bf->bf_nframes = 1; | |
d43f3015 | 1394 | bf->bf_lastbf = bf; |
e8324357 S |
1395 | ath_buf_set_rate(sc, bf); |
1396 | ath_tx_txqaddbuf(sc, txq, bf_head); | |
fec247c0 | 1397 | TX_STAT_INC(txq->axq_qnum, queued); |
e8324357 S |
1398 | } |
1399 | ||
c37452b0 S |
1400 | static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, |
1401 | struct list_head *bf_head) | |
1402 | { | |
1403 | struct ath_buf *bf; | |
1404 | ||
1405 | bf = list_first_entry(bf_head, struct ath_buf, list); | |
1406 | ||
1407 | bf->bf_lastbf = bf; | |
1408 | bf->bf_nframes = 1; | |
1409 | ath_buf_set_rate(sc, bf); | |
1410 | ath_tx_txqaddbuf(sc, txq, bf_head); | |
fec247c0 | 1411 | TX_STAT_INC(txq->axq_qnum, queued); |
c37452b0 S |
1412 | } |
1413 | ||
e8324357 S |
1414 | static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb) |
1415 | { | |
1416 | struct ieee80211_hdr *hdr; | |
1417 | enum ath9k_pkt_type htype; | |
1418 | __le16 fc; | |
1419 | ||
1420 | hdr = (struct ieee80211_hdr *)skb->data; | |
1421 | fc = hdr->frame_control; | |
1422 | ||
1423 | if (ieee80211_is_beacon(fc)) | |
1424 | htype = ATH9K_PKT_TYPE_BEACON; | |
1425 | else if (ieee80211_is_probe_resp(fc)) | |
1426 | htype = ATH9K_PKT_TYPE_PROBE_RESP; | |
1427 | else if (ieee80211_is_atim(fc)) | |
1428 | htype = ATH9K_PKT_TYPE_ATIM; | |
1429 | else if (ieee80211_is_pspoll(fc)) | |
1430 | htype = ATH9K_PKT_TYPE_PSPOLL; | |
1431 | else | |
1432 | htype = ATH9K_PKT_TYPE_NORMAL; | |
1433 | ||
1434 | return htype; | |
1435 | } | |
1436 | ||
e8324357 S |
1437 | static int get_hw_crypto_keytype(struct sk_buff *skb) |
1438 | { | |
1439 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1440 | ||
1441 | if (tx_info->control.hw_key) { | |
1442 | if (tx_info->control.hw_key->alg == ALG_WEP) | |
1443 | return ATH9K_KEY_TYPE_WEP; | |
1444 | else if (tx_info->control.hw_key->alg == ALG_TKIP) | |
1445 | return ATH9K_KEY_TYPE_TKIP; | |
1446 | else if (tx_info->control.hw_key->alg == ALG_CCMP) | |
1447 | return ATH9K_KEY_TYPE_AES; | |
1448 | } | |
1449 | ||
1450 | return ATH9K_KEY_TYPE_CLEAR; | |
1451 | } | |
1452 | ||
1453 | static void assign_aggr_tid_seqno(struct sk_buff *skb, | |
1454 | struct ath_buf *bf) | |
1455 | { | |
1456 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1457 | struct ieee80211_hdr *hdr; | |
1458 | struct ath_node *an; | |
1459 | struct ath_atx_tid *tid; | |
1460 | __le16 fc; | |
1461 | u8 *qc; | |
1462 | ||
1463 | if (!tx_info->control.sta) | |
1464 | return; | |
1465 | ||
1466 | an = (struct ath_node *)tx_info->control.sta->drv_priv; | |
1467 | hdr = (struct ieee80211_hdr *)skb->data; | |
1468 | fc = hdr->frame_control; | |
1469 | ||
1470 | if (ieee80211_is_data_qos(fc)) { | |
1471 | qc = ieee80211_get_qos_ctl(hdr); | |
1472 | bf->bf_tidno = qc[0] & 0xf; | |
1473 | } | |
1474 | ||
1475 | /* | |
1476 | * For HT capable stations, we save tidno for later use. | |
1477 | * We also override seqno set by upper layer with the one | |
1478 | * in tx aggregation state. | |
e8324357 S |
1479 | */ |
1480 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
17b182e3 | 1481 | hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT); |
e8324357 S |
1482 | bf->bf_seqno = tid->seq_next; |
1483 | INCR(tid->seq_next, IEEE80211_SEQ_MAX); | |
1484 | } | |
1485 | ||
1486 | static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb, | |
1487 | struct ath_txq *txq) | |
1488 | { | |
1489 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1490 | int flags = 0; | |
1491 | ||
1492 | flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */ | |
1493 | flags |= ATH9K_TXDESC_INTREQ; | |
1494 | ||
1495 | if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) | |
1496 | flags |= ATH9K_TXDESC_NOACK; | |
e8324357 S |
1497 | |
1498 | return flags; | |
1499 | } | |
1500 | ||
1501 | /* | |
1502 | * rix - rate index | |
1503 | * pktlen - total bytes (delims + data + fcs + pads + pad delims) | |
1504 | * width - 0 for 20 MHz, 1 for 40 MHz | |
1505 | * half_gi - to use 4us v/s 3.6 us for symbol time | |
1506 | */ | |
1507 | static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf, | |
1508 | int width, int half_gi, bool shortPreamble) | |
1509 | { | |
e8324357 | 1510 | u32 nbits, nsymbits, duration, nsymbols; |
e8324357 S |
1511 | int streams, pktlen; |
1512 | ||
1513 | pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen; | |
e8324357 S |
1514 | |
1515 | /* find number of symbols: PLCP + data */ | |
1516 | nbits = (pktlen << 3) + OFDM_PLCP_BITS; | |
545750d3 | 1517 | nsymbits = bits_per_symbol[rix][width]; |
e8324357 S |
1518 | nsymbols = (nbits + nsymbits - 1) / nsymbits; |
1519 | ||
1520 | if (!half_gi) | |
1521 | duration = SYMBOL_TIME(nsymbols); | |
1522 | else | |
1523 | duration = SYMBOL_TIME_HALFGI(nsymbols); | |
1524 | ||
1525 | /* addup duration for legacy/ht training and signal fields */ | |
545750d3 | 1526 | streams = HT_RC_2_STREAMS(rix); |
e8324357 S |
1527 | duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); |
1528 | ||
1529 | return duration; | |
1530 | } | |
1531 | ||
1532 | static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf) | |
1533 | { | |
43c27613 | 1534 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
e8324357 S |
1535 | struct ath9k_11n_rate_series series[4]; |
1536 | struct sk_buff *skb; | |
1537 | struct ieee80211_tx_info *tx_info; | |
1538 | struct ieee80211_tx_rate *rates; | |
545750d3 | 1539 | const struct ieee80211_rate *rate; |
254ad0ff | 1540 | struct ieee80211_hdr *hdr; |
c89424df S |
1541 | int i, flags = 0; |
1542 | u8 rix = 0, ctsrate = 0; | |
254ad0ff | 1543 | bool is_pspoll; |
e8324357 S |
1544 | |
1545 | memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4); | |
1546 | ||
a22be22a | 1547 | skb = bf->bf_mpdu; |
e8324357 S |
1548 | tx_info = IEEE80211_SKB_CB(skb); |
1549 | rates = tx_info->control.rates; | |
254ad0ff S |
1550 | hdr = (struct ieee80211_hdr *)skb->data; |
1551 | is_pspoll = ieee80211_is_pspoll(hdr->frame_control); | |
e8324357 | 1552 | |
e8324357 | 1553 | /* |
c89424df S |
1554 | * We check if Short Preamble is needed for the CTS rate by |
1555 | * checking the BSS's global flag. | |
1556 | * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used. | |
e8324357 | 1557 | */ |
545750d3 FF |
1558 | rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info); |
1559 | ctsrate = rate->hw_value; | |
c89424df | 1560 | if (sc->sc_flags & SC_OP_PREAMBLE_SHORT) |
545750d3 | 1561 | ctsrate |= rate->hw_value_short; |
e8324357 | 1562 | |
e8324357 | 1563 | for (i = 0; i < 4; i++) { |
545750d3 FF |
1564 | bool is_40, is_sgi, is_sp; |
1565 | int phy; | |
1566 | ||
e8324357 S |
1567 | if (!rates[i].count || (rates[i].idx < 0)) |
1568 | continue; | |
1569 | ||
1570 | rix = rates[i].idx; | |
e8324357 | 1571 | series[i].Tries = rates[i].count; |
43c27613 | 1572 | series[i].ChSel = common->tx_chainmask; |
e8324357 | 1573 | |
27032059 FF |
1574 | if ((sc->config.ath_aggr_prot && bf_isaggr(bf)) || |
1575 | (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)) { | |
c89424df | 1576 | series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; |
27032059 FF |
1577 | flags |= ATH9K_TXDESC_RTSENA; |
1578 | } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { | |
1579 | series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; | |
1580 | flags |= ATH9K_TXDESC_CTSENA; | |
1581 | } | |
1582 | ||
c89424df S |
1583 | if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) |
1584 | series[i].RateFlags |= ATH9K_RATESERIES_2040; | |
1585 | if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) | |
1586 | series[i].RateFlags |= ATH9K_RATESERIES_HALFGI; | |
e8324357 | 1587 | |
545750d3 FF |
1588 | is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI); |
1589 | is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH); | |
1590 | is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE); | |
1591 | ||
1592 | if (rates[i].flags & IEEE80211_TX_RC_MCS) { | |
1593 | /* MCS rates */ | |
1594 | series[i].Rate = rix | 0x80; | |
1595 | series[i].PktDuration = ath_pkt_duration(sc, rix, bf, | |
1596 | is_40, is_sgi, is_sp); | |
1597 | continue; | |
1598 | } | |
1599 | ||
1600 | /* legcay rates */ | |
1601 | if ((tx_info->band == IEEE80211_BAND_2GHZ) && | |
1602 | !(rate->flags & IEEE80211_RATE_ERP_G)) | |
1603 | phy = WLAN_RC_PHY_CCK; | |
1604 | else | |
1605 | phy = WLAN_RC_PHY_OFDM; | |
1606 | ||
1607 | rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx]; | |
1608 | series[i].Rate = rate->hw_value; | |
1609 | if (rate->hw_value_short) { | |
1610 | if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) | |
1611 | series[i].Rate |= rate->hw_value_short; | |
1612 | } else { | |
1613 | is_sp = false; | |
1614 | } | |
1615 | ||
1616 | series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah, | |
1617 | phy, rate->bitrate * 100, bf->bf_frmlen, rix, is_sp); | |
f078f209 LR |
1618 | } |
1619 | ||
27032059 FF |
1620 | /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ |
1621 | if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit)) | |
1622 | flags &= ~ATH9K_TXDESC_RTSENA; | |
1623 | ||
1624 | /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */ | |
1625 | if (flags & ATH9K_TXDESC_RTSENA) | |
1626 | flags &= ~ATH9K_TXDESC_CTSENA; | |
1627 | ||
e8324357 | 1628 | /* set dur_update_en for l-sig computation except for PS-Poll frames */ |
c89424df S |
1629 | ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc, |
1630 | bf->bf_lastbf->bf_desc, | |
254ad0ff | 1631 | !is_pspoll, ctsrate, |
c89424df | 1632 | 0, series, 4, flags); |
f078f209 | 1633 | |
17d7904d | 1634 | if (sc->config.ath_aggr_prot && flags) |
c89424df | 1635 | ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192); |
f078f209 LR |
1636 | } |
1637 | ||
c52f33d0 | 1638 | static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf, |
8f93b8b3 | 1639 | struct sk_buff *skb, |
528f0c6b | 1640 | struct ath_tx_control *txctl) |
f078f209 | 1641 | { |
c52f33d0 JM |
1642 | struct ath_wiphy *aphy = hw->priv; |
1643 | struct ath_softc *sc = aphy->sc; | |
528f0c6b S |
1644 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
1645 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
528f0c6b S |
1646 | int hdrlen; |
1647 | __le16 fc; | |
1bc14880 | 1648 | int padpos, padsize; |
e022edbd | 1649 | |
827e69bf FF |
1650 | tx_info->pad[0] = 0; |
1651 | switch (txctl->frame_type) { | |
c81494d5 | 1652 | case ATH9K_IFT_NOT_INTERNAL: |
827e69bf | 1653 | break; |
c81494d5 | 1654 | case ATH9K_IFT_PAUSE: |
827e69bf FF |
1655 | tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_PAUSE; |
1656 | /* fall through */ | |
c81494d5 | 1657 | case ATH9K_IFT_UNPAUSE: |
827e69bf FF |
1658 | tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_INTERNAL; |
1659 | break; | |
1660 | } | |
528f0c6b S |
1661 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); |
1662 | fc = hdr->frame_control; | |
f078f209 | 1663 | |
528f0c6b | 1664 | ATH_TXBUF_RESET(bf); |
f078f209 | 1665 | |
827e69bf | 1666 | bf->aphy = aphy; |
1bc14880 BP |
1667 | bf->bf_frmlen = skb->len + FCS_LEN; |
1668 | /* Remove the padding size from bf_frmlen, if any */ | |
1669 | padpos = ath9k_cmn_padpos(hdr->frame_control); | |
1670 | padsize = padpos & 3; | |
1671 | if (padsize && skb->len>padpos+padsize) { | |
1672 | bf->bf_frmlen -= padsize; | |
1673 | } | |
cd3d39a6 | 1674 | |
6c8afef5 | 1675 | if (conf_is_ht(&hw->conf)) |
c656bbb5 | 1676 | bf->bf_state.bf_type |= BUF_HT; |
528f0c6b S |
1677 | |
1678 | bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq); | |
1679 | ||
528f0c6b | 1680 | bf->bf_keytype = get_hw_crypto_keytype(skb); |
528f0c6b S |
1681 | if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) { |
1682 | bf->bf_frmlen += tx_info->control.hw_key->icv_len; | |
1683 | bf->bf_keyix = tx_info->control.hw_key->hw_key_idx; | |
1684 | } else { | |
1685 | bf->bf_keyix = ATH9K_TXKEYIX_INVALID; | |
1686 | } | |
1687 | ||
17b182e3 S |
1688 | if (ieee80211_is_data_qos(fc) && bf_isht(bf) && |
1689 | (sc->sc_flags & SC_OP_TXAGGR)) | |
528f0c6b S |
1690 | assign_aggr_tid_seqno(skb, bf); |
1691 | ||
f078f209 | 1692 | bf->bf_mpdu = skb; |
f8316df1 | 1693 | |
7da3c55c GJ |
1694 | bf->bf_dmacontext = dma_map_single(sc->dev, skb->data, |
1695 | skb->len, DMA_TO_DEVICE); | |
1696 | if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) { | |
f8316df1 | 1697 | bf->bf_mpdu = NULL; |
c46917bb LR |
1698 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
1699 | "dma_mapping_error() on TX\n"); | |
f8316df1 LR |
1700 | return -ENOMEM; |
1701 | } | |
1702 | ||
528f0c6b | 1703 | bf->bf_buf_addr = bf->bf_dmacontext; |
e7824a50 LR |
1704 | |
1705 | /* tag if this is a nullfunc frame to enable PS when AP acks it */ | |
1706 | if (ieee80211_is_nullfunc(fc) && ieee80211_has_pm(fc)) { | |
1707 | bf->bf_isnullfunc = true; | |
1b04b930 | 1708 | sc->ps_flags &= ~PS_NULLFUNC_COMPLETED; |
e7824a50 LR |
1709 | } else |
1710 | bf->bf_isnullfunc = false; | |
1711 | ||
f8316df1 | 1712 | return 0; |
528f0c6b S |
1713 | } |
1714 | ||
1715 | /* FIXME: tx power */ | |
1716 | static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf, | |
528f0c6b S |
1717 | struct ath_tx_control *txctl) |
1718 | { | |
a22be22a | 1719 | struct sk_buff *skb = bf->bf_mpdu; |
528f0c6b | 1720 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
c37452b0 | 1721 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
528f0c6b S |
1722 | struct ath_node *an = NULL; |
1723 | struct list_head bf_head; | |
1724 | struct ath_desc *ds; | |
1725 | struct ath_atx_tid *tid; | |
cbe61d8a | 1726 | struct ath_hw *ah = sc->sc_ah; |
528f0c6b | 1727 | int frm_type; |
c37452b0 | 1728 | __le16 fc; |
528f0c6b | 1729 | |
528f0c6b | 1730 | frm_type = get_hw_packet_type(skb); |
c37452b0 | 1731 | fc = hdr->frame_control; |
528f0c6b S |
1732 | |
1733 | INIT_LIST_HEAD(&bf_head); | |
1734 | list_add_tail(&bf->list, &bf_head); | |
f078f209 | 1735 | |
f078f209 | 1736 | ds = bf->bf_desc; |
87d5efbb | 1737 | ath9k_hw_set_desc_link(ah, ds, 0); |
f078f209 | 1738 | |
528f0c6b S |
1739 | ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER, |
1740 | bf->bf_keyix, bf->bf_keytype, bf->bf_flags); | |
1741 | ||
1742 | ath9k_hw_filltxdesc(ah, ds, | |
8f93b8b3 S |
1743 | skb->len, /* segment length */ |
1744 | true, /* first segment */ | |
1745 | true, /* last segment */ | |
3f3a1c80 | 1746 | ds, /* first descriptor */ |
cc610ac0 VT |
1747 | bf->bf_buf_addr, |
1748 | txctl->txq->axq_qnum); | |
f078f209 | 1749 | |
528f0c6b | 1750 | spin_lock_bh(&txctl->txq->axq_lock); |
f078f209 | 1751 | |
f1617967 JL |
1752 | if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) && |
1753 | tx_info->control.sta) { | |
1754 | an = (struct ath_node *)tx_info->control.sta->drv_priv; | |
1755 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
1756 | ||
c37452b0 S |
1757 | if (!ieee80211_is_data_qos(fc)) { |
1758 | ath_tx_send_normal(sc, txctl->txq, &bf_head); | |
1759 | goto tx_done; | |
1760 | } | |
1761 | ||
4fdec031 | 1762 | if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { |
f078f209 LR |
1763 | /* |
1764 | * Try aggregation if it's a unicast data frame | |
1765 | * and the destination is HT capable. | |
1766 | */ | |
528f0c6b | 1767 | ath_tx_send_ampdu(sc, tid, &bf_head, txctl); |
f078f209 LR |
1768 | } else { |
1769 | /* | |
528f0c6b S |
1770 | * Send this frame as regular when ADDBA |
1771 | * exchange is neither complete nor pending. | |
f078f209 | 1772 | */ |
c37452b0 S |
1773 | ath_tx_send_ht_normal(sc, txctl->txq, |
1774 | tid, &bf_head); | |
f078f209 LR |
1775 | } |
1776 | } else { | |
c37452b0 | 1777 | ath_tx_send_normal(sc, txctl->txq, &bf_head); |
f078f209 | 1778 | } |
528f0c6b | 1779 | |
c37452b0 | 1780 | tx_done: |
528f0c6b | 1781 | spin_unlock_bh(&txctl->txq->axq_lock); |
f078f209 LR |
1782 | } |
1783 | ||
f8316df1 | 1784 | /* Upon failure caller should free skb */ |
c52f33d0 | 1785 | int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, |
528f0c6b | 1786 | struct ath_tx_control *txctl) |
f078f209 | 1787 | { |
c52f33d0 JM |
1788 | struct ath_wiphy *aphy = hw->priv; |
1789 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1790 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
528f0c6b | 1791 | struct ath_buf *bf; |
f8316df1 | 1792 | int r; |
f078f209 | 1793 | |
528f0c6b S |
1794 | bf = ath_tx_get_buffer(sc); |
1795 | if (!bf) { | |
c46917bb | 1796 | ath_print(common, ATH_DBG_XMIT, "TX buffers are full\n"); |
528f0c6b S |
1797 | return -1; |
1798 | } | |
1799 | ||
c52f33d0 | 1800 | r = ath_tx_setup_buffer(hw, bf, skb, txctl); |
f8316df1 | 1801 | if (unlikely(r)) { |
c112d0c5 LR |
1802 | struct ath_txq *txq = txctl->txq; |
1803 | ||
c46917bb | 1804 | ath_print(common, ATH_DBG_FATAL, "TX mem alloc failure\n"); |
c112d0c5 LR |
1805 | |
1806 | /* upon ath_tx_processq() this TX queue will be resumed, we | |
1807 | * guarantee this will happen by knowing beforehand that | |
1808 | * we will at least have to run TX completionon one buffer | |
1809 | * on the queue */ | |
1810 | spin_lock_bh(&txq->axq_lock); | |
f7a99e46 | 1811 | if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) { |
f52de03b | 1812 | ath_mac80211_stop_queue(sc, skb_get_queue_mapping(skb)); |
c112d0c5 LR |
1813 | txq->stopped = 1; |
1814 | } | |
1815 | spin_unlock_bh(&txq->axq_lock); | |
1816 | ||
b77f483f S |
1817 | spin_lock_bh(&sc->tx.txbuflock); |
1818 | list_add_tail(&bf->list, &sc->tx.txbuf); | |
1819 | spin_unlock_bh(&sc->tx.txbuflock); | |
c112d0c5 | 1820 | |
f8316df1 LR |
1821 | return r; |
1822 | } | |
1823 | ||
8f93b8b3 | 1824 | ath_tx_start_dma(sc, bf, txctl); |
f078f209 | 1825 | |
528f0c6b | 1826 | return 0; |
f078f209 LR |
1827 | } |
1828 | ||
c52f33d0 | 1829 | void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb) |
f078f209 | 1830 | { |
c52f33d0 JM |
1831 | struct ath_wiphy *aphy = hw->priv; |
1832 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1833 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
4d91f9f3 BP |
1834 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; |
1835 | int padpos, padsize; | |
e8324357 S |
1836 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
1837 | struct ath_tx_control txctl; | |
f078f209 | 1838 | |
e8324357 | 1839 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
f078f209 LR |
1840 | |
1841 | /* | |
e8324357 S |
1842 | * As a temporary workaround, assign seq# here; this will likely need |
1843 | * to be cleaned up to work better with Beacon transmission and virtual | |
1844 | * BSSes. | |
f078f209 | 1845 | */ |
e8324357 | 1846 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { |
e8324357 S |
1847 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) |
1848 | sc->tx.seq_no += 0x10; | |
1849 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); | |
1850 | hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); | |
f078f209 | 1851 | } |
f078f209 | 1852 | |
e8324357 | 1853 | /* Add the padding after the header if this is not already done */ |
4d91f9f3 BP |
1854 | padpos = ath9k_cmn_padpos(hdr->frame_control); |
1855 | padsize = padpos & 3; | |
1856 | if (padsize && skb->len>padpos) { | |
e8324357 | 1857 | if (skb_headroom(skb) < padsize) { |
c46917bb LR |
1858 | ath_print(common, ATH_DBG_XMIT, |
1859 | "TX CABQ padding failed\n"); | |
e8324357 S |
1860 | dev_kfree_skb_any(skb); |
1861 | return; | |
1862 | } | |
1863 | skb_push(skb, padsize); | |
4d91f9f3 | 1864 | memmove(skb->data, skb->data + padsize, padpos); |
f078f209 | 1865 | } |
f078f209 | 1866 | |
e8324357 | 1867 | txctl.txq = sc->beacon.cabq; |
f078f209 | 1868 | |
c46917bb LR |
1869 | ath_print(common, ATH_DBG_XMIT, |
1870 | "transmitting CABQ packet, skb: %p\n", skb); | |
f078f209 | 1871 | |
c52f33d0 | 1872 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
c46917bb | 1873 | ath_print(common, ATH_DBG_XMIT, "CABQ TX failed\n"); |
e8324357 | 1874 | goto exit; |
f078f209 | 1875 | } |
f078f209 | 1876 | |
e8324357 S |
1877 | return; |
1878 | exit: | |
1879 | dev_kfree_skb_any(skb); | |
f078f209 LR |
1880 | } |
1881 | ||
e8324357 S |
1882 | /*****************/ |
1883 | /* TX Completion */ | |
1884 | /*****************/ | |
528f0c6b | 1885 | |
e8324357 | 1886 | static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, |
827e69bf | 1887 | struct ath_wiphy *aphy, int tx_flags) |
528f0c6b | 1888 | { |
e8324357 S |
1889 | struct ieee80211_hw *hw = sc->hw; |
1890 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
c46917bb | 1891 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
4d91f9f3 BP |
1892 | struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data; |
1893 | int padpos, padsize; | |
528f0c6b | 1894 | |
c46917bb | 1895 | ath_print(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb); |
528f0c6b | 1896 | |
827e69bf FF |
1897 | if (aphy) |
1898 | hw = aphy->hw; | |
528f0c6b | 1899 | |
6b2c4032 | 1900 | if (tx_flags & ATH_TX_BAR) |
e8324357 | 1901 | tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; |
e8324357 | 1902 | |
6b2c4032 | 1903 | if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) { |
e8324357 S |
1904 | /* Frame was ACKed */ |
1905 | tx_info->flags |= IEEE80211_TX_STAT_ACK; | |
528f0c6b S |
1906 | } |
1907 | ||
4d91f9f3 BP |
1908 | padpos = ath9k_cmn_padpos(hdr->frame_control); |
1909 | padsize = padpos & 3; | |
1910 | if (padsize && skb->len>padpos+padsize) { | |
e8324357 S |
1911 | /* |
1912 | * Remove MAC header padding before giving the frame back to | |
1913 | * mac80211. | |
1914 | */ | |
4d91f9f3 | 1915 | memmove(skb->data + padsize, skb->data, padpos); |
e8324357 S |
1916 | skb_pull(skb, padsize); |
1917 | } | |
528f0c6b | 1918 | |
1b04b930 S |
1919 | if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) { |
1920 | sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK; | |
c46917bb LR |
1921 | ath_print(common, ATH_DBG_PS, |
1922 | "Going back to sleep after having " | |
f643e51d | 1923 | "received TX status (0x%lx)\n", |
1b04b930 S |
1924 | sc->ps_flags & (PS_WAIT_FOR_BEACON | |
1925 | PS_WAIT_FOR_CAB | | |
1926 | PS_WAIT_FOR_PSPOLL_DATA | | |
1927 | PS_WAIT_FOR_TX_ACK)); | |
9a23f9ca JM |
1928 | } |
1929 | ||
827e69bf | 1930 | if (unlikely(tx_info->pad[0] & ATH_TX_INFO_FRAME_TYPE_INTERNAL)) |
f0ed85c6 | 1931 | ath9k_tx_status(hw, skb); |
827e69bf FF |
1932 | else |
1933 | ieee80211_tx_status(hw, skb); | |
e8324357 | 1934 | } |
f078f209 | 1935 | |
e8324357 | 1936 | static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, |
db1a052b FF |
1937 | struct ath_txq *txq, struct list_head *bf_q, |
1938 | struct ath_tx_status *ts, int txok, int sendbar) | |
f078f209 | 1939 | { |
e8324357 | 1940 | struct sk_buff *skb = bf->bf_mpdu; |
e8324357 | 1941 | unsigned long flags; |
6b2c4032 | 1942 | int tx_flags = 0; |
f078f209 | 1943 | |
e8324357 | 1944 | if (sendbar) |
6b2c4032 | 1945 | tx_flags = ATH_TX_BAR; |
f078f209 | 1946 | |
e8324357 | 1947 | if (!txok) { |
6b2c4032 | 1948 | tx_flags |= ATH_TX_ERROR; |
f078f209 | 1949 | |
e8324357 | 1950 | if (bf_isxretried(bf)) |
6b2c4032 | 1951 | tx_flags |= ATH_TX_XRETRY; |
f078f209 LR |
1952 | } |
1953 | ||
e8324357 | 1954 | dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE); |
827e69bf | 1955 | ath_tx_complete(sc, skb, bf->aphy, tx_flags); |
db1a052b | 1956 | ath_debug_stat_tx(sc, txq, bf, ts); |
e8324357 S |
1957 | |
1958 | /* | |
1959 | * Return the list of ath_buf of this mpdu to free queue | |
1960 | */ | |
1961 | spin_lock_irqsave(&sc->tx.txbuflock, flags); | |
1962 | list_splice_tail_init(bf_q, &sc->tx.txbuf); | |
1963 | spin_unlock_irqrestore(&sc->tx.txbuflock, flags); | |
f078f209 LR |
1964 | } |
1965 | ||
e8324357 | 1966 | static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf, |
db1a052b | 1967 | struct ath_tx_status *ts, int txok) |
f078f209 | 1968 | { |
e8324357 S |
1969 | u16 seq_st = 0; |
1970 | u32 ba[WME_BA_BMP_SIZE >> 5]; | |
1971 | int ba_index; | |
1972 | int nbad = 0; | |
1973 | int isaggr = 0; | |
f078f209 | 1974 | |
6d913f7d | 1975 | if (bf->bf_tx_aborted) |
e8324357 | 1976 | return 0; |
f078f209 | 1977 | |
e8324357 S |
1978 | isaggr = bf_isaggr(bf); |
1979 | if (isaggr) { | |
db1a052b FF |
1980 | seq_st = ts->ts_seqnum; |
1981 | memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); | |
e8324357 | 1982 | } |
f078f209 | 1983 | |
e8324357 S |
1984 | while (bf) { |
1985 | ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno); | |
1986 | if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index))) | |
1987 | nbad++; | |
1988 | ||
1989 | bf = bf->bf_next; | |
1990 | } | |
f078f209 | 1991 | |
e8324357 S |
1992 | return nbad; |
1993 | } | |
f078f209 | 1994 | |
db1a052b | 1995 | static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts, |
8a92e2ee | 1996 | int nbad, int txok, bool update_rc) |
f078f209 | 1997 | { |
a22be22a | 1998 | struct sk_buff *skb = bf->bf_mpdu; |
254ad0ff | 1999 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
e8324357 | 2000 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
827e69bf | 2001 | struct ieee80211_hw *hw = bf->aphy->hw; |
8a92e2ee | 2002 | u8 i, tx_rateindex; |
f078f209 | 2003 | |
95e4acb7 | 2004 | if (txok) |
db1a052b | 2005 | tx_info->status.ack_signal = ts->ts_rssi; |
95e4acb7 | 2006 | |
db1a052b | 2007 | tx_rateindex = ts->ts_rateindex; |
8a92e2ee VT |
2008 | WARN_ON(tx_rateindex >= hw->max_rates); |
2009 | ||
db1a052b | 2010 | if (ts->ts_status & ATH9K_TXERR_FILT) |
e8324357 | 2011 | tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; |
d969847c FF |
2012 | if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc) |
2013 | tx_info->flags |= IEEE80211_TX_STAT_AMPDU; | |
f078f209 | 2014 | |
db1a052b | 2015 | if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 && |
8a92e2ee | 2016 | (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) { |
254ad0ff | 2017 | if (ieee80211_is_data(hdr->frame_control)) { |
db1a052b | 2018 | if (ts->ts_flags & |
827e69bf FF |
2019 | (ATH9K_TX_DATA_UNDERRUN | ATH9K_TX_DELIM_UNDERRUN)) |
2020 | tx_info->pad[0] |= ATH_TX_INFO_UNDERRUN; | |
db1a052b FF |
2021 | if ((ts->ts_status & ATH9K_TXERR_XRETRY) || |
2022 | (ts->ts_status & ATH9K_TXERR_FIFO)) | |
827e69bf FF |
2023 | tx_info->pad[0] |= ATH_TX_INFO_XRETRY; |
2024 | tx_info->status.ampdu_len = bf->bf_nframes; | |
2025 | tx_info->status.ampdu_ack_len = bf->bf_nframes - nbad; | |
e8324357 | 2026 | } |
f078f209 | 2027 | } |
8a92e2ee | 2028 | |
545750d3 | 2029 | for (i = tx_rateindex + 1; i < hw->max_rates; i++) { |
8a92e2ee | 2030 | tx_info->status.rates[i].count = 0; |
545750d3 FF |
2031 | tx_info->status.rates[i].idx = -1; |
2032 | } | |
8a92e2ee VT |
2033 | |
2034 | tx_info->status.rates[tx_rateindex].count = bf->bf_retries + 1; | |
f078f209 LR |
2035 | } |
2036 | ||
059d806c S |
2037 | static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq) |
2038 | { | |
2039 | int qnum; | |
2040 | ||
2041 | spin_lock_bh(&txq->axq_lock); | |
2042 | if (txq->stopped && | |
f7a99e46 | 2043 | sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) { |
059d806c S |
2044 | qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc); |
2045 | if (qnum != -1) { | |
f52de03b | 2046 | ath_mac80211_start_queue(sc, qnum); |
059d806c S |
2047 | txq->stopped = 0; |
2048 | } | |
2049 | } | |
2050 | spin_unlock_bh(&txq->axq_lock); | |
2051 | } | |
2052 | ||
e8324357 | 2053 | static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) |
f078f209 | 2054 | { |
cbe61d8a | 2055 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 2056 | struct ath_common *common = ath9k_hw_common(ah); |
e8324357 | 2057 | struct ath_buf *bf, *lastbf, *bf_held = NULL; |
f078f209 | 2058 | struct list_head bf_head; |
e8324357 | 2059 | struct ath_desc *ds; |
29bffa96 | 2060 | struct ath_tx_status ts; |
0934af23 | 2061 | int txok; |
e8324357 | 2062 | int status; |
f078f209 | 2063 | |
c46917bb LR |
2064 | ath_print(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n", |
2065 | txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), | |
2066 | txq->axq_link); | |
f078f209 | 2067 | |
f078f209 LR |
2068 | for (;;) { |
2069 | spin_lock_bh(&txq->axq_lock); | |
f078f209 LR |
2070 | if (list_empty(&txq->axq_q)) { |
2071 | txq->axq_link = NULL; | |
f078f209 LR |
2072 | spin_unlock_bh(&txq->axq_lock); |
2073 | break; | |
2074 | } | |
f078f209 LR |
2075 | bf = list_first_entry(&txq->axq_q, struct ath_buf, list); |
2076 | ||
e8324357 S |
2077 | /* |
2078 | * There is a race condition that a BH gets scheduled | |
2079 | * after sw writes TxE and before hw re-load the last | |
2080 | * descriptor to get the newly chained one. | |
2081 | * Software must keep the last DONE descriptor as a | |
2082 | * holding descriptor - software does so by marking | |
2083 | * it with the STALE flag. | |
2084 | */ | |
2085 | bf_held = NULL; | |
a119cc49 | 2086 | if (bf->bf_stale) { |
e8324357 S |
2087 | bf_held = bf; |
2088 | if (list_is_last(&bf_held->list, &txq->axq_q)) { | |
6ef9b13d | 2089 | spin_unlock_bh(&txq->axq_lock); |
e8324357 S |
2090 | break; |
2091 | } else { | |
2092 | bf = list_entry(bf_held->list.next, | |
6ef9b13d | 2093 | struct ath_buf, list); |
e8324357 | 2094 | } |
f078f209 LR |
2095 | } |
2096 | ||
2097 | lastbf = bf->bf_lastbf; | |
e8324357 | 2098 | ds = lastbf->bf_desc; |
f078f209 | 2099 | |
29bffa96 FF |
2100 | memset(&ts, 0, sizeof(ts)); |
2101 | status = ath9k_hw_txprocdesc(ah, ds, &ts); | |
e8324357 | 2102 | if (status == -EINPROGRESS) { |
f078f209 | 2103 | spin_unlock_bh(&txq->axq_lock); |
e8324357 | 2104 | break; |
f078f209 | 2105 | } |
f078f209 | 2106 | |
e7824a50 LR |
2107 | /* |
2108 | * We now know the nullfunc frame has been ACKed so we | |
2109 | * can disable RX. | |
2110 | */ | |
2111 | if (bf->bf_isnullfunc && | |
29bffa96 | 2112 | (ts.ts_status & ATH9K_TX_ACKED)) { |
3f7c5c10 SB |
2113 | if ((sc->ps_flags & PS_ENABLED)) |
2114 | ath9k_enable_ps(sc); | |
2115 | else | |
1b04b930 | 2116 | sc->ps_flags |= PS_NULLFUNC_COMPLETED; |
e7824a50 LR |
2117 | } |
2118 | ||
e8324357 S |
2119 | /* |
2120 | * Remove ath_buf's of the same transmit unit from txq, | |
2121 | * however leave the last descriptor back as the holding | |
2122 | * descriptor for hw. | |
2123 | */ | |
a119cc49 | 2124 | lastbf->bf_stale = true; |
e8324357 | 2125 | INIT_LIST_HEAD(&bf_head); |
e8324357 S |
2126 | if (!list_is_singular(&lastbf->list)) |
2127 | list_cut_position(&bf_head, | |
2128 | &txq->axq_q, lastbf->list.prev); | |
f078f209 | 2129 | |
e8324357 | 2130 | txq->axq_depth--; |
29bffa96 | 2131 | txok = !(ts.ts_status & ATH9K_TXERR_MASK); |
164ace38 | 2132 | txq->axq_tx_inprogress = false; |
e8324357 | 2133 | spin_unlock_bh(&txq->axq_lock); |
f078f209 | 2134 | |
e8324357 | 2135 | if (bf_held) { |
e8324357 | 2136 | spin_lock_bh(&sc->tx.txbuflock); |
6ef9b13d | 2137 | list_move_tail(&bf_held->list, &sc->tx.txbuf); |
e8324357 S |
2138 | spin_unlock_bh(&sc->tx.txbuflock); |
2139 | } | |
f078f209 | 2140 | |
e8324357 S |
2141 | if (!bf_isampdu(bf)) { |
2142 | /* | |
2143 | * This frame is sent out as a single frame. | |
2144 | * Use hardware retry status for this frame. | |
2145 | */ | |
29bffa96 FF |
2146 | bf->bf_retries = ts.ts_longretry; |
2147 | if (ts.ts_status & ATH9K_TXERR_XRETRY) | |
e8324357 | 2148 | bf->bf_state.bf_type |= BUF_XRETRY; |
29bffa96 | 2149 | ath_tx_rc_status(bf, &ts, 0, txok, true); |
e8324357 | 2150 | } |
f078f209 | 2151 | |
e8324357 | 2152 | if (bf_isampdu(bf)) |
29bffa96 | 2153 | ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, txok); |
e8324357 | 2154 | else |
29bffa96 | 2155 | ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, txok, 0); |
8469cdef | 2156 | |
059d806c | 2157 | ath_wake_mac80211_queue(sc, txq); |
8469cdef | 2158 | |
059d806c | 2159 | spin_lock_bh(&txq->axq_lock); |
e8324357 S |
2160 | if (sc->sc_flags & SC_OP_TXAGGR) |
2161 | ath_txq_schedule(sc, txq); | |
2162 | spin_unlock_bh(&txq->axq_lock); | |
8469cdef S |
2163 | } |
2164 | } | |
2165 | ||
305fe47f | 2166 | static void ath_tx_complete_poll_work(struct work_struct *work) |
164ace38 SB |
2167 | { |
2168 | struct ath_softc *sc = container_of(work, struct ath_softc, | |
2169 | tx_complete_work.work); | |
2170 | struct ath_txq *txq; | |
2171 | int i; | |
2172 | bool needreset = false; | |
2173 | ||
2174 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) | |
2175 | if (ATH_TXQ_SETUP(sc, i)) { | |
2176 | txq = &sc->tx.txq[i]; | |
2177 | spin_lock_bh(&txq->axq_lock); | |
2178 | if (txq->axq_depth) { | |
2179 | if (txq->axq_tx_inprogress) { | |
2180 | needreset = true; | |
2181 | spin_unlock_bh(&txq->axq_lock); | |
2182 | break; | |
2183 | } else { | |
2184 | txq->axq_tx_inprogress = true; | |
2185 | } | |
2186 | } | |
2187 | spin_unlock_bh(&txq->axq_lock); | |
2188 | } | |
2189 | ||
2190 | if (needreset) { | |
c46917bb LR |
2191 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET, |
2192 | "tx hung, resetting the chip\n"); | |
332c5566 | 2193 | ath9k_ps_wakeup(sc); |
164ace38 | 2194 | ath_reset(sc, false); |
332c5566 | 2195 | ath9k_ps_restore(sc); |
164ace38 SB |
2196 | } |
2197 | ||
42935eca | 2198 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, |
164ace38 SB |
2199 | msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT)); |
2200 | } | |
2201 | ||
2202 | ||
f078f209 | 2203 | |
e8324357 | 2204 | void ath_tx_tasklet(struct ath_softc *sc) |
f078f209 | 2205 | { |
e8324357 S |
2206 | int i; |
2207 | u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1); | |
f078f209 | 2208 | |
e8324357 | 2209 | ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask); |
f078f209 | 2210 | |
e8324357 S |
2211 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
2212 | if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i))) | |
2213 | ath_tx_processq(sc, &sc->tx.txq[i]); | |
f078f209 LR |
2214 | } |
2215 | } | |
2216 | ||
e5003249 VT |
2217 | void ath_tx_edma_tasklet(struct ath_softc *sc) |
2218 | { | |
2219 | struct ath_tx_status txs; | |
2220 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
2221 | struct ath_hw *ah = sc->sc_ah; | |
2222 | struct ath_txq *txq; | |
2223 | struct ath_buf *bf, *lastbf; | |
2224 | struct list_head bf_head; | |
2225 | int status; | |
2226 | int txok; | |
2227 | ||
2228 | for (;;) { | |
2229 | status = ath9k_hw_txprocdesc(ah, NULL, (void *)&txs); | |
2230 | if (status == -EINPROGRESS) | |
2231 | break; | |
2232 | if (status == -EIO) { | |
2233 | ath_print(common, ATH_DBG_XMIT, | |
2234 | "Error processing tx status\n"); | |
2235 | break; | |
2236 | } | |
2237 | ||
2238 | /* Skip beacon completions */ | |
2239 | if (txs.qid == sc->beacon.beaconq) | |
2240 | continue; | |
2241 | ||
2242 | txq = &sc->tx.txq[txs.qid]; | |
2243 | ||
2244 | spin_lock_bh(&txq->axq_lock); | |
2245 | if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) { | |
2246 | spin_unlock_bh(&txq->axq_lock); | |
2247 | return; | |
2248 | } | |
2249 | ||
2250 | bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx], | |
2251 | struct ath_buf, list); | |
2252 | lastbf = bf->bf_lastbf; | |
2253 | ||
2254 | INIT_LIST_HEAD(&bf_head); | |
2255 | list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx], | |
2256 | &lastbf->list); | |
2257 | INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH); | |
2258 | txq->axq_depth--; | |
2259 | txq->axq_tx_inprogress = false; | |
2260 | spin_unlock_bh(&txq->axq_lock); | |
2261 | ||
2262 | txok = !(txs.ts_status & ATH9K_TXERR_MASK); | |
2263 | ||
2264 | if (!bf_isampdu(bf)) { | |
2265 | bf->bf_retries = txs.ts_longretry; | |
2266 | if (txs.ts_status & ATH9K_TXERR_XRETRY) | |
2267 | bf->bf_state.bf_type |= BUF_XRETRY; | |
2268 | ath_tx_rc_status(bf, &txs, 0, txok, true); | |
2269 | } | |
2270 | ||
2271 | if (bf_isampdu(bf)) | |
2272 | ath_tx_complete_aggr(sc, txq, bf, &bf_head, &txs, txok); | |
2273 | else | |
2274 | ath_tx_complete_buf(sc, bf, txq, &bf_head, | |
2275 | &txs, txok, 0); | |
2276 | ||
2277 | spin_lock_bh(&txq->axq_lock); | |
2278 | if (!list_empty(&txq->txq_fifo_pending)) { | |
2279 | INIT_LIST_HEAD(&bf_head); | |
2280 | bf = list_first_entry(&txq->txq_fifo_pending, | |
2281 | struct ath_buf, list); | |
2282 | list_cut_position(&bf_head, &txq->txq_fifo_pending, | |
2283 | &bf->bf_lastbf->list); | |
2284 | ath_tx_txqaddbuf(sc, txq, &bf_head); | |
2285 | } else if (sc->sc_flags & SC_OP_TXAGGR) | |
2286 | ath_txq_schedule(sc, txq); | |
2287 | spin_unlock_bh(&txq->axq_lock); | |
2288 | } | |
2289 | } | |
2290 | ||
e8324357 S |
2291 | /*****************/ |
2292 | /* Init, Cleanup */ | |
2293 | /*****************/ | |
f078f209 | 2294 | |
5088c2f1 VT |
2295 | static int ath_txstatus_setup(struct ath_softc *sc, int size) |
2296 | { | |
2297 | struct ath_descdma *dd = &sc->txsdma; | |
2298 | u8 txs_len = sc->sc_ah->caps.txs_len; | |
2299 | ||
2300 | dd->dd_desc_len = size * txs_len; | |
2301 | dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len, | |
2302 | &dd->dd_desc_paddr, GFP_KERNEL); | |
2303 | if (!dd->dd_desc) | |
2304 | return -ENOMEM; | |
2305 | ||
2306 | return 0; | |
2307 | } | |
2308 | ||
2309 | static int ath_tx_edma_init(struct ath_softc *sc) | |
2310 | { | |
2311 | int err; | |
2312 | ||
2313 | err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE); | |
2314 | if (!err) | |
2315 | ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc, | |
2316 | sc->txsdma.dd_desc_paddr, | |
2317 | ATH_TXSTATUS_RING_SIZE); | |
2318 | ||
2319 | return err; | |
2320 | } | |
2321 | ||
2322 | static void ath_tx_edma_cleanup(struct ath_softc *sc) | |
2323 | { | |
2324 | struct ath_descdma *dd = &sc->txsdma; | |
2325 | ||
2326 | dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc, | |
2327 | dd->dd_desc_paddr); | |
2328 | } | |
2329 | ||
e8324357 | 2330 | int ath_tx_init(struct ath_softc *sc, int nbufs) |
f078f209 | 2331 | { |
c46917bb | 2332 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
e8324357 | 2333 | int error = 0; |
f078f209 | 2334 | |
797fe5cb | 2335 | spin_lock_init(&sc->tx.txbuflock); |
f078f209 | 2336 | |
797fe5cb | 2337 | error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, |
4adfcded | 2338 | "tx", nbufs, 1, 1); |
797fe5cb | 2339 | if (error != 0) { |
c46917bb LR |
2340 | ath_print(common, ATH_DBG_FATAL, |
2341 | "Failed to allocate tx descriptors: %d\n", error); | |
797fe5cb S |
2342 | goto err; |
2343 | } | |
f078f209 | 2344 | |
797fe5cb | 2345 | error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, |
5088c2f1 | 2346 | "beacon", ATH_BCBUF, 1, 1); |
797fe5cb | 2347 | if (error != 0) { |
c46917bb LR |
2348 | ath_print(common, ATH_DBG_FATAL, |
2349 | "Failed to allocate beacon descriptors: %d\n", error); | |
797fe5cb S |
2350 | goto err; |
2351 | } | |
f078f209 | 2352 | |
164ace38 SB |
2353 | INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work); |
2354 | ||
5088c2f1 VT |
2355 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
2356 | error = ath_tx_edma_init(sc); | |
2357 | if (error) | |
2358 | goto err; | |
2359 | } | |
2360 | ||
797fe5cb | 2361 | err: |
e8324357 S |
2362 | if (error != 0) |
2363 | ath_tx_cleanup(sc); | |
f078f209 | 2364 | |
e8324357 | 2365 | return error; |
f078f209 LR |
2366 | } |
2367 | ||
797fe5cb | 2368 | void ath_tx_cleanup(struct ath_softc *sc) |
e8324357 S |
2369 | { |
2370 | if (sc->beacon.bdma.dd_desc_len != 0) | |
2371 | ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf); | |
2372 | ||
2373 | if (sc->tx.txdma.dd_desc_len != 0) | |
2374 | ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf); | |
5088c2f1 VT |
2375 | |
2376 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
2377 | ath_tx_edma_cleanup(sc); | |
e8324357 | 2378 | } |
f078f209 LR |
2379 | |
2380 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an) | |
2381 | { | |
c5170163 S |
2382 | struct ath_atx_tid *tid; |
2383 | struct ath_atx_ac *ac; | |
2384 | int tidno, acno; | |
f078f209 | 2385 | |
8ee5afbc | 2386 | for (tidno = 0, tid = &an->tid[tidno]; |
c5170163 S |
2387 | tidno < WME_NUM_TID; |
2388 | tidno++, tid++) { | |
2389 | tid->an = an; | |
2390 | tid->tidno = tidno; | |
2391 | tid->seq_start = tid->seq_next = 0; | |
2392 | tid->baw_size = WME_MAX_BA; | |
2393 | tid->baw_head = tid->baw_tail = 0; | |
2394 | tid->sched = false; | |
e8324357 | 2395 | tid->paused = false; |
a37c2c79 | 2396 | tid->state &= ~AGGR_CLEANUP; |
c5170163 | 2397 | INIT_LIST_HEAD(&tid->buf_q); |
c5170163 | 2398 | acno = TID_TO_WME_AC(tidno); |
8ee5afbc | 2399 | tid->ac = &an->ac[acno]; |
a37c2c79 S |
2400 | tid->state &= ~AGGR_ADDBA_COMPLETE; |
2401 | tid->state &= ~AGGR_ADDBA_PROGRESS; | |
c5170163 | 2402 | } |
f078f209 | 2403 | |
8ee5afbc | 2404 | for (acno = 0, ac = &an->ac[acno]; |
c5170163 S |
2405 | acno < WME_NUM_AC; acno++, ac++) { |
2406 | ac->sched = false; | |
2407 | INIT_LIST_HEAD(&ac->tid_q); | |
2408 | ||
2409 | switch (acno) { | |
2410 | case WME_AC_BE: | |
2411 | ac->qnum = ath_tx_get_qnum(sc, | |
2412 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE); | |
2413 | break; | |
2414 | case WME_AC_BK: | |
2415 | ac->qnum = ath_tx_get_qnum(sc, | |
2416 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK); | |
2417 | break; | |
2418 | case WME_AC_VI: | |
2419 | ac->qnum = ath_tx_get_qnum(sc, | |
2420 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI); | |
2421 | break; | |
2422 | case WME_AC_VO: | |
2423 | ac->qnum = ath_tx_get_qnum(sc, | |
2424 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO); | |
2425 | break; | |
f078f209 LR |
2426 | } |
2427 | } | |
2428 | } | |
2429 | ||
b5aa9bf9 | 2430 | void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an) |
f078f209 LR |
2431 | { |
2432 | int i; | |
2433 | struct ath_atx_ac *ac, *ac_tmp; | |
2434 | struct ath_atx_tid *tid, *tid_tmp; | |
2435 | struct ath_txq *txq; | |
e8324357 | 2436 | |
f078f209 LR |
2437 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
2438 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f | 2439 | txq = &sc->tx.txq[i]; |
f078f209 | 2440 | |
a9f042cb | 2441 | spin_lock_bh(&txq->axq_lock); |
f078f209 LR |
2442 | |
2443 | list_for_each_entry_safe(ac, | |
2444 | ac_tmp, &txq->axq_acq, list) { | |
2445 | tid = list_first_entry(&ac->tid_q, | |
2446 | struct ath_atx_tid, list); | |
2447 | if (tid && tid->an != an) | |
2448 | continue; | |
2449 | list_del(&ac->list); | |
2450 | ac->sched = false; | |
2451 | ||
2452 | list_for_each_entry_safe(tid, | |
2453 | tid_tmp, &ac->tid_q, list) { | |
2454 | list_del(&tid->list); | |
2455 | tid->sched = false; | |
b5aa9bf9 | 2456 | ath_tid_drain(sc, txq, tid); |
a37c2c79 | 2457 | tid->state &= ~AGGR_ADDBA_COMPLETE; |
a37c2c79 | 2458 | tid->state &= ~AGGR_CLEANUP; |
f078f209 LR |
2459 | } |
2460 | } | |
2461 | ||
a9f042cb | 2462 | spin_unlock_bh(&txq->axq_lock); |
f078f209 LR |
2463 | } |
2464 | } | |
2465 | } |