Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
394cf0a1 | 17 | #include "ath9k.h" |
f078f209 LR |
18 | |
19 | #define BITS_PER_BYTE 8 | |
20 | #define OFDM_PLCP_BITS 22 | |
21 | #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f) | |
22 | #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) | |
23 | #define L_STF 8 | |
24 | #define L_LTF 8 | |
25 | #define L_SIG 4 | |
26 | #define HT_SIG 8 | |
27 | #define HT_STF 4 | |
28 | #define HT_LTF(_ns) (4 * (_ns)) | |
29 | #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */ | |
30 | #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */ | |
31 | #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) | |
32 | #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) | |
33 | ||
34 | #define OFDM_SIFS_TIME 16 | |
35 | ||
36 | static u32 bits_per_symbol[][2] = { | |
37 | /* 20MHz 40MHz */ | |
38 | { 26, 54 }, /* 0: BPSK */ | |
39 | { 52, 108 }, /* 1: QPSK 1/2 */ | |
40 | { 78, 162 }, /* 2: QPSK 3/4 */ | |
41 | { 104, 216 }, /* 3: 16-QAM 1/2 */ | |
42 | { 156, 324 }, /* 4: 16-QAM 3/4 */ | |
43 | { 208, 432 }, /* 5: 64-QAM 2/3 */ | |
44 | { 234, 486 }, /* 6: 64-QAM 3/4 */ | |
45 | { 260, 540 }, /* 7: 64-QAM 5/6 */ | |
46 | { 52, 108 }, /* 8: BPSK */ | |
47 | { 104, 216 }, /* 9: QPSK 1/2 */ | |
48 | { 156, 324 }, /* 10: QPSK 3/4 */ | |
49 | { 208, 432 }, /* 11: 16-QAM 1/2 */ | |
50 | { 312, 648 }, /* 12: 16-QAM 3/4 */ | |
51 | { 416, 864 }, /* 13: 64-QAM 2/3 */ | |
52 | { 468, 972 }, /* 14: 64-QAM 3/4 */ | |
53 | { 520, 1080 }, /* 15: 64-QAM 5/6 */ | |
54 | }; | |
55 | ||
56 | #define IS_HT_RATE(_rate) ((_rate) & 0x80) | |
57 | ||
c37452b0 S |
58 | static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq, |
59 | struct ath_atx_tid *tid, | |
60 | struct list_head *bf_head); | |
e8324357 | 61 | static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, |
db1a052b FF |
62 | struct ath_txq *txq, struct list_head *bf_q, |
63 | struct ath_tx_status *ts, int txok, int sendbar); | |
102e0572 | 64 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, |
e8324357 S |
65 | struct list_head *head); |
66 | static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf); | |
0934af23 | 67 | static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf, |
db1a052b FF |
68 | struct ath_tx_status *ts, int txok); |
69 | static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts, | |
8a92e2ee | 70 | int nbad, int txok, bool update_rc); |
c4288390 | 71 | |
545750d3 FF |
72 | enum { |
73 | MCS_DEFAULT, | |
74 | MCS_HT40, | |
75 | MCS_HT40_SGI, | |
76 | }; | |
77 | ||
78 | static int ath_max_4ms_framelen[3][16] = { | |
79 | [MCS_DEFAULT] = { | |
80 | 3216, 6434, 9650, 12868, 19304, 25740, 28956, 32180, | |
81 | 6430, 12860, 19300, 25736, 38600, 51472, 57890, 64320, | |
82 | }, | |
83 | [MCS_HT40] = { | |
84 | 6684, 13368, 20052, 26738, 40104, 53476, 60156, 66840, | |
85 | 13360, 26720, 40080, 53440, 80160, 106880, 120240, 133600, | |
86 | }, | |
87 | [MCS_HT40_SGI] = { | |
88 | /* TODO: Only MCS 7 and 15 updated, recalculate the rest */ | |
89 | 6684, 13368, 20052, 26738, 40104, 53476, 60156, 74200, | |
90 | 13360, 26720, 40080, 53440, 80160, 106880, 120240, 148400, | |
91 | } | |
92 | }; | |
93 | ||
94 | ||
e8324357 S |
95 | /*********************/ |
96 | /* Aggregation logic */ | |
97 | /*********************/ | |
f078f209 | 98 | |
e8324357 | 99 | static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid) |
ff37e337 | 100 | { |
e8324357 | 101 | struct ath_atx_ac *ac = tid->ac; |
ff37e337 | 102 | |
e8324357 S |
103 | if (tid->paused) |
104 | return; | |
ff37e337 | 105 | |
e8324357 S |
106 | if (tid->sched) |
107 | return; | |
ff37e337 | 108 | |
e8324357 S |
109 | tid->sched = true; |
110 | list_add_tail(&tid->list, &ac->tid_q); | |
528f0c6b | 111 | |
e8324357 S |
112 | if (ac->sched) |
113 | return; | |
f078f209 | 114 | |
e8324357 S |
115 | ac->sched = true; |
116 | list_add_tail(&ac->list, &txq->axq_acq); | |
117 | } | |
f078f209 | 118 | |
e8324357 S |
119 | static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
120 | { | |
121 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; | |
f078f209 | 122 | |
e8324357 S |
123 | spin_lock_bh(&txq->axq_lock); |
124 | tid->paused++; | |
125 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 LR |
126 | } |
127 | ||
e8324357 | 128 | static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
f078f209 | 129 | { |
e8324357 | 130 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; |
e6a9854b | 131 | |
9680e8a3 | 132 | BUG_ON(tid->paused <= 0); |
e8324357 | 133 | spin_lock_bh(&txq->axq_lock); |
f078f209 | 134 | |
e8324357 | 135 | tid->paused--; |
f078f209 | 136 | |
e8324357 S |
137 | if (tid->paused > 0) |
138 | goto unlock; | |
f078f209 | 139 | |
e8324357 S |
140 | if (list_empty(&tid->buf_q)) |
141 | goto unlock; | |
f078f209 | 142 | |
e8324357 S |
143 | ath_tx_queue_tid(txq, tid); |
144 | ath_txq_schedule(sc, txq); | |
145 | unlock: | |
146 | spin_unlock_bh(&txq->axq_lock); | |
528f0c6b | 147 | } |
f078f209 | 148 | |
e8324357 | 149 | static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
528f0c6b | 150 | { |
e8324357 S |
151 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; |
152 | struct ath_buf *bf; | |
153 | struct list_head bf_head; | |
154 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 155 | |
9680e8a3 | 156 | BUG_ON(tid->paused <= 0); |
e8324357 | 157 | spin_lock_bh(&txq->axq_lock); |
e6a9854b | 158 | |
e8324357 | 159 | tid->paused--; |
f078f209 | 160 | |
e8324357 S |
161 | if (tid->paused > 0) { |
162 | spin_unlock_bh(&txq->axq_lock); | |
163 | return; | |
164 | } | |
f078f209 | 165 | |
e8324357 S |
166 | while (!list_empty(&tid->buf_q)) { |
167 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); | |
9680e8a3 | 168 | BUG_ON(bf_isretried(bf)); |
d43f3015 | 169 | list_move_tail(&bf->list, &bf_head); |
c37452b0 | 170 | ath_tx_send_ht_normal(sc, txq, tid, &bf_head); |
528f0c6b | 171 | } |
f078f209 | 172 | |
e8324357 | 173 | spin_unlock_bh(&txq->axq_lock); |
528f0c6b | 174 | } |
f078f209 | 175 | |
e8324357 S |
176 | static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
177 | int seqno) | |
528f0c6b | 178 | { |
e8324357 | 179 | int index, cindex; |
f078f209 | 180 | |
e8324357 S |
181 | index = ATH_BA_INDEX(tid->seq_start, seqno); |
182 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | |
f078f209 | 183 | |
e8324357 | 184 | tid->tx_buf[cindex] = NULL; |
528f0c6b | 185 | |
e8324357 S |
186 | while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) { |
187 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); | |
188 | INCR(tid->baw_head, ATH_TID_MAX_BUFS); | |
189 | } | |
528f0c6b | 190 | } |
f078f209 | 191 | |
e8324357 S |
192 | static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
193 | struct ath_buf *bf) | |
528f0c6b | 194 | { |
e8324357 | 195 | int index, cindex; |
528f0c6b | 196 | |
e8324357 S |
197 | if (bf_isretried(bf)) |
198 | return; | |
528f0c6b | 199 | |
e8324357 S |
200 | index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno); |
201 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | |
f078f209 | 202 | |
9680e8a3 | 203 | BUG_ON(tid->tx_buf[cindex] != NULL); |
e8324357 | 204 | tid->tx_buf[cindex] = bf; |
f078f209 | 205 | |
e8324357 S |
206 | if (index >= ((tid->baw_tail - tid->baw_head) & |
207 | (ATH_TID_MAX_BUFS - 1))) { | |
208 | tid->baw_tail = cindex; | |
209 | INCR(tid->baw_tail, ATH_TID_MAX_BUFS); | |
f078f209 | 210 | } |
f078f209 LR |
211 | } |
212 | ||
213 | /* | |
e8324357 S |
214 | * TODO: For frame(s) that are in the retry state, we will reuse the |
215 | * sequence number(s) without setting the retry bit. The | |
216 | * alternative is to give up on these and BAR the receiver's window | |
217 | * forward. | |
f078f209 | 218 | */ |
e8324357 S |
219 | static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq, |
220 | struct ath_atx_tid *tid) | |
f078f209 | 221 | |
f078f209 | 222 | { |
e8324357 S |
223 | struct ath_buf *bf; |
224 | struct list_head bf_head; | |
db1a052b FF |
225 | struct ath_tx_status ts; |
226 | ||
227 | memset(&ts, 0, sizeof(ts)); | |
e8324357 | 228 | INIT_LIST_HEAD(&bf_head); |
f078f209 | 229 | |
e8324357 S |
230 | for (;;) { |
231 | if (list_empty(&tid->buf_q)) | |
232 | break; | |
f078f209 | 233 | |
d43f3015 S |
234 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); |
235 | list_move_tail(&bf->list, &bf_head); | |
f078f209 | 236 | |
e8324357 S |
237 | if (bf_isretried(bf)) |
238 | ath_tx_update_baw(sc, tid, bf->bf_seqno); | |
f078f209 | 239 | |
e8324357 | 240 | spin_unlock(&txq->axq_lock); |
db1a052b | 241 | ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0); |
e8324357 S |
242 | spin_lock(&txq->axq_lock); |
243 | } | |
f078f209 | 244 | |
e8324357 S |
245 | tid->seq_next = tid->seq_start; |
246 | tid->baw_tail = tid->baw_head; | |
f078f209 LR |
247 | } |
248 | ||
fec247c0 S |
249 | static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq, |
250 | struct ath_buf *bf) | |
f078f209 | 251 | { |
e8324357 S |
252 | struct sk_buff *skb; |
253 | struct ieee80211_hdr *hdr; | |
f078f209 | 254 | |
e8324357 S |
255 | bf->bf_state.bf_type |= BUF_RETRY; |
256 | bf->bf_retries++; | |
fec247c0 | 257 | TX_STAT_INC(txq->axq_qnum, a_retries); |
f078f209 | 258 | |
e8324357 S |
259 | skb = bf->bf_mpdu; |
260 | hdr = (struct ieee80211_hdr *)skb->data; | |
261 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); | |
f078f209 LR |
262 | } |
263 | ||
d43f3015 S |
264 | static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf) |
265 | { | |
266 | struct ath_buf *tbf; | |
267 | ||
268 | spin_lock_bh(&sc->tx.txbuflock); | |
8a46097a VT |
269 | if (WARN_ON(list_empty(&sc->tx.txbuf))) { |
270 | spin_unlock_bh(&sc->tx.txbuflock); | |
271 | return NULL; | |
272 | } | |
d43f3015 S |
273 | tbf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); |
274 | list_del(&tbf->list); | |
275 | spin_unlock_bh(&sc->tx.txbuflock); | |
276 | ||
277 | ATH_TXBUF_RESET(tbf); | |
278 | ||
827e69bf | 279 | tbf->aphy = bf->aphy; |
d43f3015 S |
280 | tbf->bf_mpdu = bf->bf_mpdu; |
281 | tbf->bf_buf_addr = bf->bf_buf_addr; | |
d826c832 | 282 | memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len); |
d43f3015 S |
283 | tbf->bf_state = bf->bf_state; |
284 | tbf->bf_dmacontext = bf->bf_dmacontext; | |
285 | ||
286 | return tbf; | |
287 | } | |
288 | ||
289 | static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, | |
290 | struct ath_buf *bf, struct list_head *bf_q, | |
db1a052b | 291 | struct ath_tx_status *ts, int txok) |
f078f209 | 292 | { |
e8324357 S |
293 | struct ath_node *an = NULL; |
294 | struct sk_buff *skb; | |
1286ec6d | 295 | struct ieee80211_sta *sta; |
76d5a9e8 | 296 | struct ieee80211_hw *hw; |
1286ec6d | 297 | struct ieee80211_hdr *hdr; |
76d5a9e8 | 298 | struct ieee80211_tx_info *tx_info; |
e8324357 | 299 | struct ath_atx_tid *tid = NULL; |
d43f3015 | 300 | struct ath_buf *bf_next, *bf_last = bf->bf_lastbf; |
e8324357 | 301 | struct list_head bf_head, bf_pending; |
0934af23 | 302 | u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0; |
f078f209 | 303 | u32 ba[WME_BA_BMP_SIZE >> 5]; |
0934af23 VT |
304 | int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0; |
305 | bool rc_update = true; | |
f078f209 | 306 | |
a22be22a | 307 | skb = bf->bf_mpdu; |
1286ec6d S |
308 | hdr = (struct ieee80211_hdr *)skb->data; |
309 | ||
76d5a9e8 | 310 | tx_info = IEEE80211_SKB_CB(skb); |
827e69bf | 311 | hw = bf->aphy->hw; |
76d5a9e8 | 312 | |
1286ec6d | 313 | rcu_read_lock(); |
f078f209 | 314 | |
5ed176e1 | 315 | /* XXX: use ieee80211_find_sta! */ |
76d5a9e8 | 316 | sta = ieee80211_find_sta_by_hw(hw, hdr->addr1); |
1286ec6d S |
317 | if (!sta) { |
318 | rcu_read_unlock(); | |
319 | return; | |
f078f209 LR |
320 | } |
321 | ||
1286ec6d S |
322 | an = (struct ath_node *)sta->drv_priv; |
323 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
324 | ||
e8324357 | 325 | isaggr = bf_isaggr(bf); |
d43f3015 | 326 | memset(ba, 0, WME_BA_BMP_SIZE >> 3); |
f078f209 | 327 | |
d43f3015 | 328 | if (isaggr && txok) { |
db1a052b FF |
329 | if (ts->ts_flags & ATH9K_TX_BA) { |
330 | seq_st = ts->ts_seqnum; | |
331 | memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); | |
e8324357 | 332 | } else { |
d43f3015 S |
333 | /* |
334 | * AR5416 can become deaf/mute when BA | |
335 | * issue happens. Chip needs to be reset. | |
336 | * But AP code may have sychronization issues | |
337 | * when perform internal reset in this routine. | |
338 | * Only enable reset in STA mode for now. | |
339 | */ | |
2660b81a | 340 | if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) |
d43f3015 | 341 | needreset = 1; |
e8324357 | 342 | } |
f078f209 LR |
343 | } |
344 | ||
e8324357 S |
345 | INIT_LIST_HEAD(&bf_pending); |
346 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 347 | |
db1a052b | 348 | nbad = ath_tx_num_badfrms(sc, bf, ts, txok); |
e8324357 S |
349 | while (bf) { |
350 | txfail = txpending = 0; | |
351 | bf_next = bf->bf_next; | |
f078f209 | 352 | |
e8324357 S |
353 | if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) { |
354 | /* transmit completion, subframe is | |
355 | * acked by block ack */ | |
0934af23 | 356 | acked_cnt++; |
e8324357 S |
357 | } else if (!isaggr && txok) { |
358 | /* transmit completion */ | |
0934af23 | 359 | acked_cnt++; |
e8324357 | 360 | } else { |
e8324357 | 361 | if (!(tid->state & AGGR_CLEANUP) && |
db1a052b | 362 | ts->ts_flags != ATH9K_TX_SW_ABORTED) { |
e8324357 | 363 | if (bf->bf_retries < ATH_MAX_SW_RETRIES) { |
fec247c0 | 364 | ath_tx_set_retry(sc, txq, bf); |
e8324357 S |
365 | txpending = 1; |
366 | } else { | |
367 | bf->bf_state.bf_type |= BUF_XRETRY; | |
368 | txfail = 1; | |
369 | sendbar = 1; | |
0934af23 | 370 | txfail_cnt++; |
e8324357 S |
371 | } |
372 | } else { | |
373 | /* | |
374 | * cleanup in progress, just fail | |
375 | * the un-acked sub-frames | |
376 | */ | |
377 | txfail = 1; | |
378 | } | |
379 | } | |
f078f209 | 380 | |
e8324357 | 381 | if (bf_next == NULL) { |
cbfe89c6 VT |
382 | /* |
383 | * Make sure the last desc is reclaimed if it | |
384 | * not a holding desc. | |
385 | */ | |
386 | if (!bf_last->bf_stale) | |
387 | list_move_tail(&bf->list, &bf_head); | |
388 | else | |
389 | INIT_LIST_HEAD(&bf_head); | |
e8324357 | 390 | } else { |
9680e8a3 | 391 | BUG_ON(list_empty(bf_q)); |
d43f3015 | 392 | list_move_tail(&bf->list, &bf_head); |
e8324357 | 393 | } |
f078f209 | 394 | |
e8324357 S |
395 | if (!txpending) { |
396 | /* | |
397 | * complete the acked-ones/xretried ones; update | |
398 | * block-ack window | |
399 | */ | |
400 | spin_lock_bh(&txq->axq_lock); | |
401 | ath_tx_update_baw(sc, tid, bf->bf_seqno); | |
402 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 | 403 | |
8a92e2ee | 404 | if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) { |
db1a052b | 405 | ath_tx_rc_status(bf, ts, nbad, txok, true); |
8a92e2ee VT |
406 | rc_update = false; |
407 | } else { | |
db1a052b | 408 | ath_tx_rc_status(bf, ts, nbad, txok, false); |
8a92e2ee VT |
409 | } |
410 | ||
db1a052b FF |
411 | ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, |
412 | !txfail, sendbar); | |
e8324357 | 413 | } else { |
d43f3015 | 414 | /* retry the un-acked ones */ |
a119cc49 | 415 | if (bf->bf_next == NULL && bf_last->bf_stale) { |
e8324357 | 416 | struct ath_buf *tbf; |
f078f209 | 417 | |
d43f3015 | 418 | tbf = ath_clone_txbuf(sc, bf_last); |
c41d92dc VT |
419 | /* |
420 | * Update tx baw and complete the frame with | |
421 | * failed status if we run out of tx buf | |
422 | */ | |
423 | if (!tbf) { | |
424 | spin_lock_bh(&txq->axq_lock); | |
425 | ath_tx_update_baw(sc, tid, | |
426 | bf->bf_seqno); | |
427 | spin_unlock_bh(&txq->axq_lock); | |
428 | ||
429 | bf->bf_state.bf_type |= BUF_XRETRY; | |
db1a052b | 430 | ath_tx_rc_status(bf, ts, nbad, |
c41d92dc | 431 | 0, false); |
fec247c0 | 432 | ath_tx_complete_buf(sc, bf, txq, |
db1a052b | 433 | &bf_head, ts, 0, 0); |
8a46097a | 434 | break; |
c41d92dc VT |
435 | } |
436 | ||
d43f3015 | 437 | ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc); |
e8324357 S |
438 | list_add_tail(&tbf->list, &bf_head); |
439 | } else { | |
440 | /* | |
441 | * Clear descriptor status words for | |
442 | * software retry | |
443 | */ | |
d43f3015 | 444 | ath9k_hw_cleartxdesc(sc->sc_ah, bf->bf_desc); |
e8324357 S |
445 | } |
446 | ||
447 | /* | |
448 | * Put this buffer to the temporary pending | |
449 | * queue to retain ordering | |
450 | */ | |
451 | list_splice_tail_init(&bf_head, &bf_pending); | |
452 | } | |
453 | ||
454 | bf = bf_next; | |
f078f209 | 455 | } |
f078f209 | 456 | |
e8324357 | 457 | if (tid->state & AGGR_CLEANUP) { |
e8324357 S |
458 | if (tid->baw_head == tid->baw_tail) { |
459 | tid->state &= ~AGGR_ADDBA_COMPLETE; | |
e8324357 | 460 | tid->state &= ~AGGR_CLEANUP; |
e63835b0 | 461 | |
e8324357 S |
462 | /* send buffered frames as singles */ |
463 | ath_tx_flush_tid(sc, tid); | |
d43f3015 | 464 | } |
1286ec6d | 465 | rcu_read_unlock(); |
e8324357 S |
466 | return; |
467 | } | |
f078f209 | 468 | |
d43f3015 | 469 | /* prepend un-acked frames to the beginning of the pending frame queue */ |
e8324357 S |
470 | if (!list_empty(&bf_pending)) { |
471 | spin_lock_bh(&txq->axq_lock); | |
472 | list_splice(&bf_pending, &tid->buf_q); | |
473 | ath_tx_queue_tid(txq, tid); | |
474 | spin_unlock_bh(&txq->axq_lock); | |
475 | } | |
102e0572 | 476 | |
1286ec6d S |
477 | rcu_read_unlock(); |
478 | ||
e8324357 S |
479 | if (needreset) |
480 | ath_reset(sc, false); | |
e8324357 | 481 | } |
f078f209 | 482 | |
e8324357 S |
483 | static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf, |
484 | struct ath_atx_tid *tid) | |
f078f209 | 485 | { |
528f0c6b S |
486 | struct sk_buff *skb; |
487 | struct ieee80211_tx_info *tx_info; | |
a8efee4f | 488 | struct ieee80211_tx_rate *rates; |
d43f3015 | 489 | u32 max_4ms_framelen, frmlen; |
4ef70841 | 490 | u16 aggr_limit, legacy = 0; |
e8324357 | 491 | int i; |
528f0c6b | 492 | |
a22be22a | 493 | skb = bf->bf_mpdu; |
528f0c6b | 494 | tx_info = IEEE80211_SKB_CB(skb); |
e63835b0 | 495 | rates = tx_info->control.rates; |
528f0c6b | 496 | |
e8324357 S |
497 | /* |
498 | * Find the lowest frame length among the rate series that will have a | |
499 | * 4ms transmit duration. | |
500 | * TODO - TXOP limit needs to be considered. | |
501 | */ | |
502 | max_4ms_framelen = ATH_AMPDU_LIMIT_MAX; | |
e63835b0 | 503 | |
e8324357 S |
504 | for (i = 0; i < 4; i++) { |
505 | if (rates[i].count) { | |
545750d3 FF |
506 | int modeidx; |
507 | if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) { | |
e8324357 S |
508 | legacy = 1; |
509 | break; | |
510 | } | |
511 | ||
545750d3 FF |
512 | if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) |
513 | modeidx = MCS_HT40_SGI; | |
514 | else if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) | |
515 | modeidx = MCS_HT40; | |
516 | else | |
517 | modeidx = MCS_DEFAULT; | |
518 | ||
519 | frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx]; | |
d43f3015 | 520 | max_4ms_framelen = min(max_4ms_framelen, frmlen); |
f078f209 LR |
521 | } |
522 | } | |
e63835b0 | 523 | |
f078f209 | 524 | /* |
e8324357 S |
525 | * limit aggregate size by the minimum rate if rate selected is |
526 | * not a probe rate, if rate selected is a probe rate then | |
527 | * avoid aggregation of this packet. | |
f078f209 | 528 | */ |
e8324357 S |
529 | if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy) |
530 | return 0; | |
f078f209 | 531 | |
1773912b VT |
532 | if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED) |
533 | aggr_limit = min((max_4ms_framelen * 3) / 8, | |
534 | (u32)ATH_AMPDU_LIMIT_MAX); | |
535 | else | |
536 | aggr_limit = min(max_4ms_framelen, | |
537 | (u32)ATH_AMPDU_LIMIT_MAX); | |
f078f209 | 538 | |
e8324357 S |
539 | /* |
540 | * h/w can accept aggregates upto 16 bit lengths (65535). | |
541 | * The IE, however can hold upto 65536, which shows up here | |
542 | * as zero. Ignore 65536 since we are constrained by hw. | |
f078f209 | 543 | */ |
4ef70841 S |
544 | if (tid->an->maxampdu) |
545 | aggr_limit = min(aggr_limit, tid->an->maxampdu); | |
f078f209 | 546 | |
e8324357 S |
547 | return aggr_limit; |
548 | } | |
f078f209 | 549 | |
e8324357 | 550 | /* |
d43f3015 | 551 | * Returns the number of delimiters to be added to |
e8324357 | 552 | * meet the minimum required mpdudensity. |
e8324357 S |
553 | */ |
554 | static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid, | |
555 | struct ath_buf *bf, u16 frmlen) | |
556 | { | |
e8324357 S |
557 | struct sk_buff *skb = bf->bf_mpdu; |
558 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
4ef70841 | 559 | u32 nsymbits, nsymbols; |
e8324357 | 560 | u16 minlen; |
545750d3 | 561 | u8 flags, rix; |
e8324357 S |
562 | int width, half_gi, ndelim, mindelim; |
563 | ||
564 | /* Select standard number of delimiters based on frame length alone */ | |
565 | ndelim = ATH_AGGR_GET_NDELIM(frmlen); | |
f078f209 LR |
566 | |
567 | /* | |
e8324357 S |
568 | * If encryption enabled, hardware requires some more padding between |
569 | * subframes. | |
570 | * TODO - this could be improved to be dependent on the rate. | |
571 | * The hardware can keep up at lower rates, but not higher rates | |
f078f209 | 572 | */ |
e8324357 S |
573 | if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) |
574 | ndelim += ATH_AGGR_ENCRYPTDELIM; | |
f078f209 | 575 | |
e8324357 S |
576 | /* |
577 | * Convert desired mpdu density from microeconds to bytes based | |
578 | * on highest rate in rate series (i.e. first rate) to determine | |
579 | * required minimum length for subframe. Take into account | |
580 | * whether high rate is 20 or 40Mhz and half or full GI. | |
4ef70841 | 581 | * |
e8324357 S |
582 | * If there is no mpdu density restriction, no further calculation |
583 | * is needed. | |
584 | */ | |
4ef70841 S |
585 | |
586 | if (tid->an->mpdudensity == 0) | |
e8324357 | 587 | return ndelim; |
f078f209 | 588 | |
e8324357 S |
589 | rix = tx_info->control.rates[0].idx; |
590 | flags = tx_info->control.rates[0].flags; | |
e8324357 S |
591 | width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0; |
592 | half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0; | |
f078f209 | 593 | |
e8324357 | 594 | if (half_gi) |
4ef70841 | 595 | nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity); |
e8324357 | 596 | else |
4ef70841 | 597 | nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity); |
f078f209 | 598 | |
e8324357 S |
599 | if (nsymbols == 0) |
600 | nsymbols = 1; | |
f078f209 | 601 | |
545750d3 | 602 | nsymbits = bits_per_symbol[rix][width]; |
e8324357 | 603 | minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; |
f078f209 | 604 | |
e8324357 | 605 | if (frmlen < minlen) { |
e8324357 S |
606 | mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ; |
607 | ndelim = max(mindelim, ndelim); | |
f078f209 LR |
608 | } |
609 | ||
e8324357 | 610 | return ndelim; |
f078f209 LR |
611 | } |
612 | ||
e8324357 | 613 | static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc, |
fec247c0 | 614 | struct ath_txq *txq, |
d43f3015 S |
615 | struct ath_atx_tid *tid, |
616 | struct list_head *bf_q) | |
f078f209 | 617 | { |
e8324357 | 618 | #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) |
d43f3015 S |
619 | struct ath_buf *bf, *bf_first, *bf_prev = NULL; |
620 | int rl = 0, nframes = 0, ndelim, prev_al = 0; | |
e8324357 S |
621 | u16 aggr_limit = 0, al = 0, bpad = 0, |
622 | al_delta, h_baw = tid->baw_size / 2; | |
623 | enum ATH_AGGR_STATUS status = ATH_AGGR_DONE; | |
f078f209 | 624 | |
e8324357 | 625 | bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list); |
f078f209 | 626 | |
e8324357 S |
627 | do { |
628 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); | |
f078f209 | 629 | |
d43f3015 | 630 | /* do not step over block-ack window */ |
e8324357 S |
631 | if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) { |
632 | status = ATH_AGGR_BAW_CLOSED; | |
633 | break; | |
634 | } | |
f078f209 | 635 | |
e8324357 S |
636 | if (!rl) { |
637 | aggr_limit = ath_lookup_rate(sc, bf, tid); | |
638 | rl = 1; | |
639 | } | |
f078f209 | 640 | |
d43f3015 | 641 | /* do not exceed aggregation limit */ |
e8324357 | 642 | al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen; |
f078f209 | 643 | |
d43f3015 S |
644 | if (nframes && |
645 | (aggr_limit < (al + bpad + al_delta + prev_al))) { | |
e8324357 S |
646 | status = ATH_AGGR_LIMITED; |
647 | break; | |
648 | } | |
f078f209 | 649 | |
d43f3015 S |
650 | /* do not exceed subframe limit */ |
651 | if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) { | |
e8324357 S |
652 | status = ATH_AGGR_LIMITED; |
653 | break; | |
654 | } | |
d43f3015 | 655 | nframes++; |
f078f209 | 656 | |
d43f3015 | 657 | /* add padding for previous frame to aggregation length */ |
e8324357 | 658 | al += bpad + al_delta; |
f078f209 | 659 | |
e8324357 S |
660 | /* |
661 | * Get the delimiters needed to meet the MPDU | |
662 | * density for this node. | |
663 | */ | |
664 | ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen); | |
e8324357 | 665 | bpad = PADBYTES(al_delta) + (ndelim << 2); |
f078f209 | 666 | |
e8324357 | 667 | bf->bf_next = NULL; |
87d5efbb | 668 | ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0); |
f078f209 | 669 | |
d43f3015 | 670 | /* link buffers of this frame to the aggregate */ |
e8324357 | 671 | ath_tx_addto_baw(sc, tid, bf); |
d43f3015 S |
672 | ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim); |
673 | list_move_tail(&bf->list, bf_q); | |
e8324357 S |
674 | if (bf_prev) { |
675 | bf_prev->bf_next = bf; | |
87d5efbb VT |
676 | ath9k_hw_set_desc_link(sc->sc_ah, bf_prev->bf_desc, |
677 | bf->bf_daddr); | |
e8324357 S |
678 | } |
679 | bf_prev = bf; | |
fec247c0 | 680 | |
e8324357 | 681 | } while (!list_empty(&tid->buf_q)); |
f078f209 | 682 | |
e8324357 S |
683 | bf_first->bf_al = al; |
684 | bf_first->bf_nframes = nframes; | |
d43f3015 | 685 | |
e8324357 S |
686 | return status; |
687 | #undef PADBYTES | |
688 | } | |
f078f209 | 689 | |
e8324357 S |
690 | static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq, |
691 | struct ath_atx_tid *tid) | |
692 | { | |
d43f3015 | 693 | struct ath_buf *bf; |
e8324357 S |
694 | enum ATH_AGGR_STATUS status; |
695 | struct list_head bf_q; | |
f078f209 | 696 | |
e8324357 S |
697 | do { |
698 | if (list_empty(&tid->buf_q)) | |
699 | return; | |
f078f209 | 700 | |
e8324357 S |
701 | INIT_LIST_HEAD(&bf_q); |
702 | ||
fec247c0 | 703 | status = ath_tx_form_aggr(sc, txq, tid, &bf_q); |
f078f209 | 704 | |
f078f209 | 705 | /* |
d43f3015 S |
706 | * no frames picked up to be aggregated; |
707 | * block-ack window is not open. | |
f078f209 | 708 | */ |
e8324357 S |
709 | if (list_empty(&bf_q)) |
710 | break; | |
f078f209 | 711 | |
e8324357 | 712 | bf = list_first_entry(&bf_q, struct ath_buf, list); |
d43f3015 | 713 | bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list); |
f078f209 | 714 | |
d43f3015 | 715 | /* if only one frame, send as non-aggregate */ |
e8324357 | 716 | if (bf->bf_nframes == 1) { |
e8324357 | 717 | bf->bf_state.bf_type &= ~BUF_AGGR; |
d43f3015 | 718 | ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc); |
e8324357 S |
719 | ath_buf_set_rate(sc, bf); |
720 | ath_tx_txqaddbuf(sc, txq, &bf_q); | |
721 | continue; | |
722 | } | |
f078f209 | 723 | |
d43f3015 | 724 | /* setup first desc of aggregate */ |
e8324357 S |
725 | bf->bf_state.bf_type |= BUF_AGGR; |
726 | ath_buf_set_rate(sc, bf); | |
727 | ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al); | |
f078f209 | 728 | |
d43f3015 S |
729 | /* anchor last desc of aggregate */ |
730 | ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc); | |
f078f209 | 731 | |
e8324357 | 732 | ath_tx_txqaddbuf(sc, txq, &bf_q); |
fec247c0 | 733 | TX_STAT_INC(txq->axq_qnum, a_aggr); |
f078f209 | 734 | |
e8324357 S |
735 | } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH && |
736 | status != ATH_AGGR_BAW_CLOSED); | |
737 | } | |
738 | ||
f83da965 S |
739 | void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, |
740 | u16 tid, u16 *ssn) | |
e8324357 S |
741 | { |
742 | struct ath_atx_tid *txtid; | |
743 | struct ath_node *an; | |
744 | ||
745 | an = (struct ath_node *)sta->drv_priv; | |
f83da965 S |
746 | txtid = ATH_AN_2_TID(an, tid); |
747 | txtid->state |= AGGR_ADDBA_PROGRESS; | |
748 | ath_tx_pause_tid(sc, txtid); | |
749 | *ssn = txtid->seq_start; | |
e8324357 | 750 | } |
f078f209 | 751 | |
f83da965 | 752 | void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) |
e8324357 S |
753 | { |
754 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
755 | struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid); | |
756 | struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum]; | |
db1a052b | 757 | struct ath_tx_status ts; |
e8324357 S |
758 | struct ath_buf *bf; |
759 | struct list_head bf_head; | |
db1a052b FF |
760 | |
761 | memset(&ts, 0, sizeof(ts)); | |
e8324357 | 762 | INIT_LIST_HEAD(&bf_head); |
f078f209 | 763 | |
e8324357 | 764 | if (txtid->state & AGGR_CLEANUP) |
f83da965 | 765 | return; |
f078f209 | 766 | |
e8324357 | 767 | if (!(txtid->state & AGGR_ADDBA_COMPLETE)) { |
5eae6592 | 768 | txtid->state &= ~AGGR_ADDBA_PROGRESS; |
f83da965 | 769 | return; |
e8324357 | 770 | } |
f078f209 | 771 | |
e8324357 S |
772 | ath_tx_pause_tid(sc, txtid); |
773 | ||
774 | /* drop all software retried frames and mark this TID */ | |
775 | spin_lock_bh(&txq->axq_lock); | |
776 | while (!list_empty(&txtid->buf_q)) { | |
777 | bf = list_first_entry(&txtid->buf_q, struct ath_buf, list); | |
778 | if (!bf_isretried(bf)) { | |
779 | /* | |
780 | * NB: it's based on the assumption that | |
781 | * software retried frame will always stay | |
782 | * at the head of software queue. | |
783 | */ | |
784 | break; | |
785 | } | |
d43f3015 | 786 | list_move_tail(&bf->list, &bf_head); |
e8324357 | 787 | ath_tx_update_baw(sc, txtid, bf->bf_seqno); |
db1a052b | 788 | ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0); |
f078f209 | 789 | } |
d43f3015 | 790 | spin_unlock_bh(&txq->axq_lock); |
f078f209 | 791 | |
e8324357 | 792 | if (txtid->baw_head != txtid->baw_tail) { |
e8324357 S |
793 | txtid->state |= AGGR_CLEANUP; |
794 | } else { | |
795 | txtid->state &= ~AGGR_ADDBA_COMPLETE; | |
e8324357 | 796 | ath_tx_flush_tid(sc, txtid); |
f078f209 | 797 | } |
e8324357 | 798 | } |
f078f209 | 799 | |
e8324357 S |
800 | void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) |
801 | { | |
802 | struct ath_atx_tid *txtid; | |
803 | struct ath_node *an; | |
804 | ||
805 | an = (struct ath_node *)sta->drv_priv; | |
806 | ||
807 | if (sc->sc_flags & SC_OP_TXAGGR) { | |
808 | txtid = ATH_AN_2_TID(an, tid); | |
809 | txtid->baw_size = | |
810 | IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor; | |
811 | txtid->state |= AGGR_ADDBA_COMPLETE; | |
812 | txtid->state &= ~AGGR_ADDBA_PROGRESS; | |
813 | ath_tx_resume_tid(sc, txtid); | |
814 | } | |
f078f209 LR |
815 | } |
816 | ||
e8324357 | 817 | bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno) |
c4288390 | 818 | { |
e8324357 | 819 | struct ath_atx_tid *txtid; |
c4288390 | 820 | |
e8324357 S |
821 | if (!(sc->sc_flags & SC_OP_TXAGGR)) |
822 | return false; | |
c4288390 | 823 | |
e8324357 S |
824 | txtid = ATH_AN_2_TID(an, tidno); |
825 | ||
c3d8f02e | 826 | if (!(txtid->state & (AGGR_ADDBA_COMPLETE | AGGR_ADDBA_PROGRESS))) |
e8324357 | 827 | return true; |
e8324357 | 828 | return false; |
c4288390 S |
829 | } |
830 | ||
e8324357 S |
831 | /********************/ |
832 | /* Queue Management */ | |
833 | /********************/ | |
f078f209 | 834 | |
e8324357 S |
835 | static void ath_txq_drain_pending_buffers(struct ath_softc *sc, |
836 | struct ath_txq *txq) | |
f078f209 | 837 | { |
e8324357 S |
838 | struct ath_atx_ac *ac, *ac_tmp; |
839 | struct ath_atx_tid *tid, *tid_tmp; | |
f078f209 | 840 | |
e8324357 S |
841 | list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) { |
842 | list_del(&ac->list); | |
843 | ac->sched = false; | |
844 | list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) { | |
845 | list_del(&tid->list); | |
846 | tid->sched = false; | |
847 | ath_tid_drain(sc, txq, tid); | |
848 | } | |
f078f209 LR |
849 | } |
850 | } | |
851 | ||
e8324357 | 852 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) |
f078f209 | 853 | { |
cbe61d8a | 854 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 855 | struct ath_common *common = ath9k_hw_common(ah); |
e8324357 S |
856 | struct ath9k_tx_queue_info qi; |
857 | int qnum; | |
f078f209 | 858 | |
e8324357 S |
859 | memset(&qi, 0, sizeof(qi)); |
860 | qi.tqi_subtype = subtype; | |
861 | qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT; | |
862 | qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT; | |
863 | qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT; | |
864 | qi.tqi_physCompBuf = 0; | |
f078f209 LR |
865 | |
866 | /* | |
e8324357 S |
867 | * Enable interrupts only for EOL and DESC conditions. |
868 | * We mark tx descriptors to receive a DESC interrupt | |
869 | * when a tx queue gets deep; otherwise waiting for the | |
870 | * EOL to reap descriptors. Note that this is done to | |
871 | * reduce interrupt load and this only defers reaping | |
872 | * descriptors, never transmitting frames. Aside from | |
873 | * reducing interrupts this also permits more concurrency. | |
874 | * The only potential downside is if the tx queue backs | |
875 | * up in which case the top half of the kernel may backup | |
876 | * due to a lack of tx descriptors. | |
877 | * | |
878 | * The UAPSD queue is an exception, since we take a desc- | |
879 | * based intr on the EOSP frames. | |
f078f209 | 880 | */ |
e8324357 S |
881 | if (qtype == ATH9K_TX_QUEUE_UAPSD) |
882 | qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; | |
883 | else | |
884 | qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | | |
885 | TXQ_FLAG_TXDESCINT_ENABLE; | |
886 | qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); | |
887 | if (qnum == -1) { | |
f078f209 | 888 | /* |
e8324357 S |
889 | * NB: don't print a message, this happens |
890 | * normally on parts with too few tx queues | |
f078f209 | 891 | */ |
e8324357 | 892 | return NULL; |
f078f209 | 893 | } |
e8324357 | 894 | if (qnum >= ARRAY_SIZE(sc->tx.txq)) { |
c46917bb LR |
895 | ath_print(common, ATH_DBG_FATAL, |
896 | "qnum %u out of range, max %u!\n", | |
897 | qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq)); | |
e8324357 S |
898 | ath9k_hw_releasetxqueue(ah, qnum); |
899 | return NULL; | |
900 | } | |
901 | if (!ATH_TXQ_SETUP(sc, qnum)) { | |
902 | struct ath_txq *txq = &sc->tx.txq[qnum]; | |
f078f209 | 903 | |
e8324357 S |
904 | txq->axq_qnum = qnum; |
905 | txq->axq_link = NULL; | |
906 | INIT_LIST_HEAD(&txq->axq_q); | |
907 | INIT_LIST_HEAD(&txq->axq_acq); | |
908 | spin_lock_init(&txq->axq_lock); | |
909 | txq->axq_depth = 0; | |
164ace38 | 910 | txq->axq_tx_inprogress = false; |
e8324357 S |
911 | sc->tx.txqsetup |= 1<<qnum; |
912 | } | |
913 | return &sc->tx.txq[qnum]; | |
f078f209 LR |
914 | } |
915 | ||
1773912b | 916 | int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype) |
f078f209 | 917 | { |
e8324357 | 918 | int qnum; |
f078f209 | 919 | |
e8324357 S |
920 | switch (qtype) { |
921 | case ATH9K_TX_QUEUE_DATA: | |
922 | if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { | |
c46917bb LR |
923 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
924 | "HAL AC %u out of range, max %zu!\n", | |
925 | haltype, ARRAY_SIZE(sc->tx.hwq_map)); | |
e8324357 S |
926 | return -1; |
927 | } | |
928 | qnum = sc->tx.hwq_map[haltype]; | |
929 | break; | |
930 | case ATH9K_TX_QUEUE_BEACON: | |
931 | qnum = sc->beacon.beaconq; | |
932 | break; | |
933 | case ATH9K_TX_QUEUE_CAB: | |
934 | qnum = sc->beacon.cabq->axq_qnum; | |
935 | break; | |
936 | default: | |
937 | qnum = -1; | |
938 | } | |
939 | return qnum; | |
940 | } | |
f078f209 | 941 | |
e8324357 S |
942 | struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb) |
943 | { | |
944 | struct ath_txq *txq = NULL; | |
f52de03b | 945 | u16 skb_queue = skb_get_queue_mapping(skb); |
e8324357 | 946 | int qnum; |
f078f209 | 947 | |
f52de03b | 948 | qnum = ath_get_hal_qnum(skb_queue, sc); |
e8324357 | 949 | txq = &sc->tx.txq[qnum]; |
f078f209 | 950 | |
e8324357 S |
951 | spin_lock_bh(&txq->axq_lock); |
952 | ||
953 | if (txq->axq_depth >= (ATH_TXBUF - 20)) { | |
c46917bb LR |
954 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_XMIT, |
955 | "TX queue: %d is full, depth: %d\n", | |
956 | qnum, txq->axq_depth); | |
f52de03b | 957 | ath_mac80211_stop_queue(sc, skb_queue); |
e8324357 S |
958 | txq->stopped = 1; |
959 | spin_unlock_bh(&txq->axq_lock); | |
960 | return NULL; | |
f078f209 LR |
961 | } |
962 | ||
e8324357 S |
963 | spin_unlock_bh(&txq->axq_lock); |
964 | ||
965 | return txq; | |
966 | } | |
967 | ||
968 | int ath_txq_update(struct ath_softc *sc, int qnum, | |
969 | struct ath9k_tx_queue_info *qinfo) | |
970 | { | |
cbe61d8a | 971 | struct ath_hw *ah = sc->sc_ah; |
e8324357 S |
972 | int error = 0; |
973 | struct ath9k_tx_queue_info qi; | |
974 | ||
975 | if (qnum == sc->beacon.beaconq) { | |
976 | /* | |
977 | * XXX: for beacon queue, we just save the parameter. | |
978 | * It will be picked up by ath_beaconq_config when | |
979 | * it's necessary. | |
980 | */ | |
981 | sc->beacon.beacon_qi = *qinfo; | |
f078f209 | 982 | return 0; |
e8324357 | 983 | } |
f078f209 | 984 | |
9680e8a3 | 985 | BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum); |
e8324357 S |
986 | |
987 | ath9k_hw_get_txq_props(ah, qnum, &qi); | |
988 | qi.tqi_aifs = qinfo->tqi_aifs; | |
989 | qi.tqi_cwmin = qinfo->tqi_cwmin; | |
990 | qi.tqi_cwmax = qinfo->tqi_cwmax; | |
991 | qi.tqi_burstTime = qinfo->tqi_burstTime; | |
992 | qi.tqi_readyTime = qinfo->tqi_readyTime; | |
993 | ||
994 | if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { | |
c46917bb LR |
995 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
996 | "Unable to update hardware queue %u!\n", qnum); | |
e8324357 S |
997 | error = -EIO; |
998 | } else { | |
999 | ath9k_hw_resettxqueue(ah, qnum); | |
1000 | } | |
1001 | ||
1002 | return error; | |
1003 | } | |
1004 | ||
1005 | int ath_cabq_update(struct ath_softc *sc) | |
1006 | { | |
1007 | struct ath9k_tx_queue_info qi; | |
1008 | int qnum = sc->beacon.cabq->axq_qnum; | |
f078f209 | 1009 | |
e8324357 | 1010 | ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi); |
f078f209 | 1011 | /* |
e8324357 | 1012 | * Ensure the readytime % is within the bounds. |
f078f209 | 1013 | */ |
17d7904d S |
1014 | if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND) |
1015 | sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND; | |
1016 | else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND) | |
1017 | sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND; | |
f078f209 | 1018 | |
57c4d7b4 | 1019 | qi.tqi_readyTime = (sc->beacon_interval * |
fdbf7335 | 1020 | sc->config.cabqReadytime) / 100; |
e8324357 S |
1021 | ath_txq_update(sc, qnum, &qi); |
1022 | ||
1023 | return 0; | |
f078f209 LR |
1024 | } |
1025 | ||
043a0405 S |
1026 | /* |
1027 | * Drain a given TX queue (could be Beacon or Data) | |
1028 | * | |
1029 | * This assumes output has been stopped and | |
1030 | * we do not need to block ath_tx_tasklet. | |
1031 | */ | |
1032 | void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx) | |
f078f209 | 1033 | { |
e8324357 S |
1034 | struct ath_buf *bf, *lastbf; |
1035 | struct list_head bf_head; | |
db1a052b FF |
1036 | struct ath_tx_status ts; |
1037 | ||
1038 | memset(&ts, 0, sizeof(ts)); | |
1039 | if (!retry_tx) | |
1040 | ts.ts_flags = ATH9K_TX_SW_ABORTED; | |
f078f209 | 1041 | |
e8324357 | 1042 | INIT_LIST_HEAD(&bf_head); |
f078f209 | 1043 | |
e8324357 S |
1044 | for (;;) { |
1045 | spin_lock_bh(&txq->axq_lock); | |
f078f209 | 1046 | |
e8324357 S |
1047 | if (list_empty(&txq->axq_q)) { |
1048 | txq->axq_link = NULL; | |
e8324357 S |
1049 | spin_unlock_bh(&txq->axq_lock); |
1050 | break; | |
1051 | } | |
f078f209 | 1052 | |
e8324357 | 1053 | bf = list_first_entry(&txq->axq_q, struct ath_buf, list); |
f078f209 | 1054 | |
a119cc49 | 1055 | if (bf->bf_stale) { |
e8324357 S |
1056 | list_del(&bf->list); |
1057 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 | 1058 | |
e8324357 S |
1059 | spin_lock_bh(&sc->tx.txbuflock); |
1060 | list_add_tail(&bf->list, &sc->tx.txbuf); | |
1061 | spin_unlock_bh(&sc->tx.txbuflock); | |
1062 | continue; | |
1063 | } | |
f078f209 | 1064 | |
e8324357 | 1065 | lastbf = bf->bf_lastbf; |
f078f209 | 1066 | |
e8324357 S |
1067 | /* remove ath_buf's of the same mpdu from txq */ |
1068 | list_cut_position(&bf_head, &txq->axq_q, &lastbf->list); | |
1069 | txq->axq_depth--; | |
f078f209 | 1070 | |
e8324357 S |
1071 | spin_unlock_bh(&txq->axq_lock); |
1072 | ||
1073 | if (bf_isampdu(bf)) | |
db1a052b | 1074 | ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0); |
e8324357 | 1075 | else |
db1a052b | 1076 | ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0); |
f078f209 LR |
1077 | } |
1078 | ||
164ace38 SB |
1079 | spin_lock_bh(&txq->axq_lock); |
1080 | txq->axq_tx_inprogress = false; | |
1081 | spin_unlock_bh(&txq->axq_lock); | |
1082 | ||
e8324357 S |
1083 | /* flush any pending frames if aggregation is enabled */ |
1084 | if (sc->sc_flags & SC_OP_TXAGGR) { | |
1085 | if (!retry_tx) { | |
1086 | spin_lock_bh(&txq->axq_lock); | |
1087 | ath_txq_drain_pending_buffers(sc, txq); | |
1088 | spin_unlock_bh(&txq->axq_lock); | |
1089 | } | |
1090 | } | |
f078f209 LR |
1091 | } |
1092 | ||
043a0405 | 1093 | void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) |
f078f209 | 1094 | { |
cbe61d8a | 1095 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1096 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
043a0405 S |
1097 | struct ath_txq *txq; |
1098 | int i, npend = 0; | |
1099 | ||
1100 | if (sc->sc_flags & SC_OP_INVALID) | |
1101 | return; | |
1102 | ||
1103 | /* Stop beacon queue */ | |
1104 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
1105 | ||
1106 | /* Stop data queues */ | |
1107 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1108 | if (ATH_TXQ_SETUP(sc, i)) { | |
1109 | txq = &sc->tx.txq[i]; | |
1110 | ath9k_hw_stoptxdma(ah, txq->axq_qnum); | |
1111 | npend += ath9k_hw_numtxpending(ah, txq->axq_qnum); | |
1112 | } | |
1113 | } | |
1114 | ||
1115 | if (npend) { | |
1116 | int r; | |
1117 | ||
e8009e98 | 1118 | ath_print(common, ATH_DBG_FATAL, |
c46917bb | 1119 | "Unable to stop TxDMA. Reset HAL!\n"); |
043a0405 S |
1120 | |
1121 | spin_lock_bh(&sc->sc_resetlock); | |
e8009e98 | 1122 | r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false); |
043a0405 | 1123 | if (r) |
c46917bb LR |
1124 | ath_print(common, ATH_DBG_FATAL, |
1125 | "Unable to reset hardware; reset status %d\n", | |
1126 | r); | |
043a0405 S |
1127 | spin_unlock_bh(&sc->sc_resetlock); |
1128 | } | |
1129 | ||
1130 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1131 | if (ATH_TXQ_SETUP(sc, i)) | |
1132 | ath_draintxq(sc, &sc->tx.txq[i], retry_tx); | |
1133 | } | |
e8324357 | 1134 | } |
f078f209 | 1135 | |
043a0405 | 1136 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) |
e8324357 | 1137 | { |
043a0405 S |
1138 | ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum); |
1139 | sc->tx.txqsetup &= ~(1<<txq->axq_qnum); | |
e8324357 | 1140 | } |
f078f209 | 1141 | |
e8324357 S |
1142 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) |
1143 | { | |
1144 | struct ath_atx_ac *ac; | |
1145 | struct ath_atx_tid *tid; | |
f078f209 | 1146 | |
e8324357 S |
1147 | if (list_empty(&txq->axq_acq)) |
1148 | return; | |
f078f209 | 1149 | |
e8324357 S |
1150 | ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list); |
1151 | list_del(&ac->list); | |
1152 | ac->sched = false; | |
f078f209 | 1153 | |
e8324357 S |
1154 | do { |
1155 | if (list_empty(&ac->tid_q)) | |
1156 | return; | |
f078f209 | 1157 | |
e8324357 S |
1158 | tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list); |
1159 | list_del(&tid->list); | |
1160 | tid->sched = false; | |
f078f209 | 1161 | |
e8324357 S |
1162 | if (tid->paused) |
1163 | continue; | |
f078f209 | 1164 | |
164ace38 | 1165 | ath_tx_sched_aggr(sc, txq, tid); |
f078f209 LR |
1166 | |
1167 | /* | |
e8324357 S |
1168 | * add tid to round-robin queue if more frames |
1169 | * are pending for the tid | |
f078f209 | 1170 | */ |
e8324357 S |
1171 | if (!list_empty(&tid->buf_q)) |
1172 | ath_tx_queue_tid(txq, tid); | |
f078f209 | 1173 | |
e8324357 S |
1174 | break; |
1175 | } while (!list_empty(&ac->tid_q)); | |
f078f209 | 1176 | |
e8324357 S |
1177 | if (!list_empty(&ac->tid_q)) { |
1178 | if (!ac->sched) { | |
1179 | ac->sched = true; | |
1180 | list_add_tail(&ac->list, &txq->axq_acq); | |
f078f209 | 1181 | } |
e8324357 S |
1182 | } |
1183 | } | |
f078f209 | 1184 | |
e8324357 S |
1185 | int ath_tx_setup(struct ath_softc *sc, int haltype) |
1186 | { | |
1187 | struct ath_txq *txq; | |
f078f209 | 1188 | |
e8324357 | 1189 | if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { |
c46917bb LR |
1190 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
1191 | "HAL AC %u out of range, max %zu!\n", | |
e8324357 S |
1192 | haltype, ARRAY_SIZE(sc->tx.hwq_map)); |
1193 | return 0; | |
1194 | } | |
1195 | txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype); | |
1196 | if (txq != NULL) { | |
1197 | sc->tx.hwq_map[haltype] = txq->axq_qnum; | |
1198 | return 1; | |
1199 | } else | |
1200 | return 0; | |
f078f209 LR |
1201 | } |
1202 | ||
e8324357 S |
1203 | /***********/ |
1204 | /* TX, DMA */ | |
1205 | /***********/ | |
1206 | ||
f078f209 | 1207 | /* |
e8324357 S |
1208 | * Insert a chain of ath_buf (descriptors) on a txq and |
1209 | * assume the descriptors are already chained together by caller. | |
f078f209 | 1210 | */ |
e8324357 S |
1211 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, |
1212 | struct list_head *head) | |
f078f209 | 1213 | { |
cbe61d8a | 1214 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1215 | struct ath_common *common = ath9k_hw_common(ah); |
e8324357 | 1216 | struct ath_buf *bf; |
f078f209 | 1217 | |
e8324357 S |
1218 | /* |
1219 | * Insert the frame on the outbound list and | |
1220 | * pass it on to the hardware. | |
1221 | */ | |
f078f209 | 1222 | |
e8324357 S |
1223 | if (list_empty(head)) |
1224 | return; | |
f078f209 | 1225 | |
e8324357 | 1226 | bf = list_first_entry(head, struct ath_buf, list); |
f078f209 | 1227 | |
e8324357 S |
1228 | list_splice_tail_init(head, &txq->axq_q); |
1229 | txq->axq_depth++; | |
f078f209 | 1230 | |
c46917bb LR |
1231 | ath_print(common, ATH_DBG_QUEUE, |
1232 | "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth); | |
f078f209 | 1233 | |
e8324357 S |
1234 | if (txq->axq_link == NULL) { |
1235 | ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); | |
c46917bb LR |
1236 | ath_print(common, ATH_DBG_XMIT, |
1237 | "TXDP[%u] = %llx (%p)\n", | |
1238 | txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); | |
e8324357 S |
1239 | } else { |
1240 | *txq->axq_link = bf->bf_daddr; | |
c46917bb LR |
1241 | ath_print(common, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n", |
1242 | txq->axq_qnum, txq->axq_link, | |
1243 | ito64(bf->bf_daddr), bf->bf_desc); | |
e8324357 | 1244 | } |
5c3a338f | 1245 | ath9k_hw_get_desc_link(ah, bf->bf_lastbf->bf_desc, &txq->axq_link); |
e8324357 S |
1246 | ath9k_hw_txstart(ah, txq->axq_qnum); |
1247 | } | |
f078f209 | 1248 | |
e8324357 S |
1249 | static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc) |
1250 | { | |
1251 | struct ath_buf *bf = NULL; | |
f078f209 | 1252 | |
e8324357 | 1253 | spin_lock_bh(&sc->tx.txbuflock); |
f078f209 | 1254 | |
e8324357 S |
1255 | if (unlikely(list_empty(&sc->tx.txbuf))) { |
1256 | spin_unlock_bh(&sc->tx.txbuflock); | |
1257 | return NULL; | |
1258 | } | |
f078f209 | 1259 | |
e8324357 S |
1260 | bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); |
1261 | list_del(&bf->list); | |
f078f209 | 1262 | |
e8324357 | 1263 | spin_unlock_bh(&sc->tx.txbuflock); |
f078f209 | 1264 | |
e8324357 | 1265 | return bf; |
f078f209 LR |
1266 | } |
1267 | ||
e8324357 S |
1268 | static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid, |
1269 | struct list_head *bf_head, | |
1270 | struct ath_tx_control *txctl) | |
f078f209 LR |
1271 | { |
1272 | struct ath_buf *bf; | |
f078f209 | 1273 | |
e8324357 S |
1274 | bf = list_first_entry(bf_head, struct ath_buf, list); |
1275 | bf->bf_state.bf_type |= BUF_AMPDU; | |
fec247c0 | 1276 | TX_STAT_INC(txctl->txq->axq_qnum, a_queued); |
f078f209 | 1277 | |
e8324357 S |
1278 | /* |
1279 | * Do not queue to h/w when any of the following conditions is true: | |
1280 | * - there are pending frames in software queue | |
1281 | * - the TID is currently paused for ADDBA/BAR request | |
1282 | * - seqno is not within block-ack window | |
1283 | * - h/w queue depth exceeds low water mark | |
1284 | */ | |
1285 | if (!list_empty(&tid->buf_q) || tid->paused || | |
1286 | !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) || | |
1287 | txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) { | |
f078f209 | 1288 | /* |
e8324357 S |
1289 | * Add this frame to software queue for scheduling later |
1290 | * for aggregation. | |
f078f209 | 1291 | */ |
d43f3015 | 1292 | list_move_tail(&bf->list, &tid->buf_q); |
e8324357 S |
1293 | ath_tx_queue_tid(txctl->txq, tid); |
1294 | return; | |
1295 | } | |
1296 | ||
1297 | /* Add sub-frame to BAW */ | |
1298 | ath_tx_addto_baw(sc, tid, bf); | |
1299 | ||
1300 | /* Queue to h/w without aggregation */ | |
1301 | bf->bf_nframes = 1; | |
d43f3015 | 1302 | bf->bf_lastbf = bf; |
e8324357 S |
1303 | ath_buf_set_rate(sc, bf); |
1304 | ath_tx_txqaddbuf(sc, txctl->txq, bf_head); | |
e8324357 S |
1305 | } |
1306 | ||
c37452b0 S |
1307 | static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq, |
1308 | struct ath_atx_tid *tid, | |
1309 | struct list_head *bf_head) | |
e8324357 S |
1310 | { |
1311 | struct ath_buf *bf; | |
1312 | ||
e8324357 S |
1313 | bf = list_first_entry(bf_head, struct ath_buf, list); |
1314 | bf->bf_state.bf_type &= ~BUF_AMPDU; | |
1315 | ||
1316 | /* update starting sequence number for subsequent ADDBA request */ | |
1317 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); | |
1318 | ||
1319 | bf->bf_nframes = 1; | |
d43f3015 | 1320 | bf->bf_lastbf = bf; |
e8324357 S |
1321 | ath_buf_set_rate(sc, bf); |
1322 | ath_tx_txqaddbuf(sc, txq, bf_head); | |
fec247c0 | 1323 | TX_STAT_INC(txq->axq_qnum, queued); |
e8324357 S |
1324 | } |
1325 | ||
c37452b0 S |
1326 | static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, |
1327 | struct list_head *bf_head) | |
1328 | { | |
1329 | struct ath_buf *bf; | |
1330 | ||
1331 | bf = list_first_entry(bf_head, struct ath_buf, list); | |
1332 | ||
1333 | bf->bf_lastbf = bf; | |
1334 | bf->bf_nframes = 1; | |
1335 | ath_buf_set_rate(sc, bf); | |
1336 | ath_tx_txqaddbuf(sc, txq, bf_head); | |
fec247c0 | 1337 | TX_STAT_INC(txq->axq_qnum, queued); |
c37452b0 S |
1338 | } |
1339 | ||
e8324357 S |
1340 | static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb) |
1341 | { | |
1342 | struct ieee80211_hdr *hdr; | |
1343 | enum ath9k_pkt_type htype; | |
1344 | __le16 fc; | |
1345 | ||
1346 | hdr = (struct ieee80211_hdr *)skb->data; | |
1347 | fc = hdr->frame_control; | |
1348 | ||
1349 | if (ieee80211_is_beacon(fc)) | |
1350 | htype = ATH9K_PKT_TYPE_BEACON; | |
1351 | else if (ieee80211_is_probe_resp(fc)) | |
1352 | htype = ATH9K_PKT_TYPE_PROBE_RESP; | |
1353 | else if (ieee80211_is_atim(fc)) | |
1354 | htype = ATH9K_PKT_TYPE_ATIM; | |
1355 | else if (ieee80211_is_pspoll(fc)) | |
1356 | htype = ATH9K_PKT_TYPE_PSPOLL; | |
1357 | else | |
1358 | htype = ATH9K_PKT_TYPE_NORMAL; | |
1359 | ||
1360 | return htype; | |
1361 | } | |
1362 | ||
e8324357 S |
1363 | static int get_hw_crypto_keytype(struct sk_buff *skb) |
1364 | { | |
1365 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1366 | ||
1367 | if (tx_info->control.hw_key) { | |
1368 | if (tx_info->control.hw_key->alg == ALG_WEP) | |
1369 | return ATH9K_KEY_TYPE_WEP; | |
1370 | else if (tx_info->control.hw_key->alg == ALG_TKIP) | |
1371 | return ATH9K_KEY_TYPE_TKIP; | |
1372 | else if (tx_info->control.hw_key->alg == ALG_CCMP) | |
1373 | return ATH9K_KEY_TYPE_AES; | |
1374 | } | |
1375 | ||
1376 | return ATH9K_KEY_TYPE_CLEAR; | |
1377 | } | |
1378 | ||
1379 | static void assign_aggr_tid_seqno(struct sk_buff *skb, | |
1380 | struct ath_buf *bf) | |
1381 | { | |
1382 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1383 | struct ieee80211_hdr *hdr; | |
1384 | struct ath_node *an; | |
1385 | struct ath_atx_tid *tid; | |
1386 | __le16 fc; | |
1387 | u8 *qc; | |
1388 | ||
1389 | if (!tx_info->control.sta) | |
1390 | return; | |
1391 | ||
1392 | an = (struct ath_node *)tx_info->control.sta->drv_priv; | |
1393 | hdr = (struct ieee80211_hdr *)skb->data; | |
1394 | fc = hdr->frame_control; | |
1395 | ||
1396 | if (ieee80211_is_data_qos(fc)) { | |
1397 | qc = ieee80211_get_qos_ctl(hdr); | |
1398 | bf->bf_tidno = qc[0] & 0xf; | |
1399 | } | |
1400 | ||
1401 | /* | |
1402 | * For HT capable stations, we save tidno for later use. | |
1403 | * We also override seqno set by upper layer with the one | |
1404 | * in tx aggregation state. | |
e8324357 S |
1405 | */ |
1406 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
17b182e3 | 1407 | hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT); |
e8324357 S |
1408 | bf->bf_seqno = tid->seq_next; |
1409 | INCR(tid->seq_next, IEEE80211_SEQ_MAX); | |
1410 | } | |
1411 | ||
1412 | static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb, | |
1413 | struct ath_txq *txq) | |
1414 | { | |
1415 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1416 | int flags = 0; | |
1417 | ||
1418 | flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */ | |
1419 | flags |= ATH9K_TXDESC_INTREQ; | |
1420 | ||
1421 | if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) | |
1422 | flags |= ATH9K_TXDESC_NOACK; | |
e8324357 S |
1423 | |
1424 | return flags; | |
1425 | } | |
1426 | ||
1427 | /* | |
1428 | * rix - rate index | |
1429 | * pktlen - total bytes (delims + data + fcs + pads + pad delims) | |
1430 | * width - 0 for 20 MHz, 1 for 40 MHz | |
1431 | * half_gi - to use 4us v/s 3.6 us for symbol time | |
1432 | */ | |
1433 | static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf, | |
1434 | int width, int half_gi, bool shortPreamble) | |
1435 | { | |
e8324357 | 1436 | u32 nbits, nsymbits, duration, nsymbols; |
e8324357 S |
1437 | int streams, pktlen; |
1438 | ||
1439 | pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen; | |
e8324357 S |
1440 | |
1441 | /* find number of symbols: PLCP + data */ | |
1442 | nbits = (pktlen << 3) + OFDM_PLCP_BITS; | |
545750d3 | 1443 | nsymbits = bits_per_symbol[rix][width]; |
e8324357 S |
1444 | nsymbols = (nbits + nsymbits - 1) / nsymbits; |
1445 | ||
1446 | if (!half_gi) | |
1447 | duration = SYMBOL_TIME(nsymbols); | |
1448 | else | |
1449 | duration = SYMBOL_TIME_HALFGI(nsymbols); | |
1450 | ||
1451 | /* addup duration for legacy/ht training and signal fields */ | |
545750d3 | 1452 | streams = HT_RC_2_STREAMS(rix); |
e8324357 S |
1453 | duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); |
1454 | ||
1455 | return duration; | |
1456 | } | |
1457 | ||
1458 | static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf) | |
1459 | { | |
43c27613 | 1460 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
e8324357 S |
1461 | struct ath9k_11n_rate_series series[4]; |
1462 | struct sk_buff *skb; | |
1463 | struct ieee80211_tx_info *tx_info; | |
1464 | struct ieee80211_tx_rate *rates; | |
545750d3 | 1465 | const struct ieee80211_rate *rate; |
254ad0ff | 1466 | struct ieee80211_hdr *hdr; |
c89424df S |
1467 | int i, flags = 0; |
1468 | u8 rix = 0, ctsrate = 0; | |
254ad0ff | 1469 | bool is_pspoll; |
e8324357 S |
1470 | |
1471 | memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4); | |
1472 | ||
a22be22a | 1473 | skb = bf->bf_mpdu; |
e8324357 S |
1474 | tx_info = IEEE80211_SKB_CB(skb); |
1475 | rates = tx_info->control.rates; | |
254ad0ff S |
1476 | hdr = (struct ieee80211_hdr *)skb->data; |
1477 | is_pspoll = ieee80211_is_pspoll(hdr->frame_control); | |
e8324357 | 1478 | |
e8324357 | 1479 | /* |
c89424df S |
1480 | * We check if Short Preamble is needed for the CTS rate by |
1481 | * checking the BSS's global flag. | |
1482 | * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used. | |
e8324357 | 1483 | */ |
545750d3 FF |
1484 | rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info); |
1485 | ctsrate = rate->hw_value; | |
c89424df | 1486 | if (sc->sc_flags & SC_OP_PREAMBLE_SHORT) |
545750d3 | 1487 | ctsrate |= rate->hw_value_short; |
e8324357 | 1488 | |
e8324357 | 1489 | for (i = 0; i < 4; i++) { |
545750d3 FF |
1490 | bool is_40, is_sgi, is_sp; |
1491 | int phy; | |
1492 | ||
e8324357 S |
1493 | if (!rates[i].count || (rates[i].idx < 0)) |
1494 | continue; | |
1495 | ||
1496 | rix = rates[i].idx; | |
e8324357 | 1497 | series[i].Tries = rates[i].count; |
43c27613 | 1498 | series[i].ChSel = common->tx_chainmask; |
e8324357 | 1499 | |
27032059 FF |
1500 | if ((sc->config.ath_aggr_prot && bf_isaggr(bf)) || |
1501 | (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)) { | |
c89424df | 1502 | series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; |
27032059 FF |
1503 | flags |= ATH9K_TXDESC_RTSENA; |
1504 | } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { | |
1505 | series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; | |
1506 | flags |= ATH9K_TXDESC_CTSENA; | |
1507 | } | |
1508 | ||
c89424df S |
1509 | if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) |
1510 | series[i].RateFlags |= ATH9K_RATESERIES_2040; | |
1511 | if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) | |
1512 | series[i].RateFlags |= ATH9K_RATESERIES_HALFGI; | |
e8324357 | 1513 | |
545750d3 FF |
1514 | is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI); |
1515 | is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH); | |
1516 | is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE); | |
1517 | ||
1518 | if (rates[i].flags & IEEE80211_TX_RC_MCS) { | |
1519 | /* MCS rates */ | |
1520 | series[i].Rate = rix | 0x80; | |
1521 | series[i].PktDuration = ath_pkt_duration(sc, rix, bf, | |
1522 | is_40, is_sgi, is_sp); | |
1523 | continue; | |
1524 | } | |
1525 | ||
1526 | /* legcay rates */ | |
1527 | if ((tx_info->band == IEEE80211_BAND_2GHZ) && | |
1528 | !(rate->flags & IEEE80211_RATE_ERP_G)) | |
1529 | phy = WLAN_RC_PHY_CCK; | |
1530 | else | |
1531 | phy = WLAN_RC_PHY_OFDM; | |
1532 | ||
1533 | rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx]; | |
1534 | series[i].Rate = rate->hw_value; | |
1535 | if (rate->hw_value_short) { | |
1536 | if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) | |
1537 | series[i].Rate |= rate->hw_value_short; | |
1538 | } else { | |
1539 | is_sp = false; | |
1540 | } | |
1541 | ||
1542 | series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah, | |
1543 | phy, rate->bitrate * 100, bf->bf_frmlen, rix, is_sp); | |
f078f209 LR |
1544 | } |
1545 | ||
27032059 FF |
1546 | /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ |
1547 | if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit)) | |
1548 | flags &= ~ATH9K_TXDESC_RTSENA; | |
1549 | ||
1550 | /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */ | |
1551 | if (flags & ATH9K_TXDESC_RTSENA) | |
1552 | flags &= ~ATH9K_TXDESC_CTSENA; | |
1553 | ||
e8324357 | 1554 | /* set dur_update_en for l-sig computation except for PS-Poll frames */ |
c89424df S |
1555 | ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc, |
1556 | bf->bf_lastbf->bf_desc, | |
254ad0ff | 1557 | !is_pspoll, ctsrate, |
c89424df | 1558 | 0, series, 4, flags); |
f078f209 | 1559 | |
17d7904d | 1560 | if (sc->config.ath_aggr_prot && flags) |
c89424df | 1561 | ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192); |
f078f209 LR |
1562 | } |
1563 | ||
c52f33d0 | 1564 | static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf, |
8f93b8b3 | 1565 | struct sk_buff *skb, |
528f0c6b | 1566 | struct ath_tx_control *txctl) |
f078f209 | 1567 | { |
c52f33d0 JM |
1568 | struct ath_wiphy *aphy = hw->priv; |
1569 | struct ath_softc *sc = aphy->sc; | |
528f0c6b S |
1570 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
1571 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
528f0c6b S |
1572 | int hdrlen; |
1573 | __le16 fc; | |
1bc14880 | 1574 | int padpos, padsize; |
e022edbd | 1575 | |
827e69bf FF |
1576 | tx_info->pad[0] = 0; |
1577 | switch (txctl->frame_type) { | |
c81494d5 | 1578 | case ATH9K_IFT_NOT_INTERNAL: |
827e69bf | 1579 | break; |
c81494d5 | 1580 | case ATH9K_IFT_PAUSE: |
827e69bf FF |
1581 | tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_PAUSE; |
1582 | /* fall through */ | |
c81494d5 | 1583 | case ATH9K_IFT_UNPAUSE: |
827e69bf FF |
1584 | tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_INTERNAL; |
1585 | break; | |
1586 | } | |
528f0c6b S |
1587 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); |
1588 | fc = hdr->frame_control; | |
f078f209 | 1589 | |
528f0c6b | 1590 | ATH_TXBUF_RESET(bf); |
f078f209 | 1591 | |
827e69bf | 1592 | bf->aphy = aphy; |
1bc14880 BP |
1593 | bf->bf_frmlen = skb->len + FCS_LEN; |
1594 | /* Remove the padding size from bf_frmlen, if any */ | |
1595 | padpos = ath9k_cmn_padpos(hdr->frame_control); | |
1596 | padsize = padpos & 3; | |
1597 | if (padsize && skb->len>padpos+padsize) { | |
1598 | bf->bf_frmlen -= padsize; | |
1599 | } | |
cd3d39a6 | 1600 | |
6c8afef5 | 1601 | if (conf_is_ht(&hw->conf)) |
c656bbb5 | 1602 | bf->bf_state.bf_type |= BUF_HT; |
528f0c6b S |
1603 | |
1604 | bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq); | |
1605 | ||
528f0c6b | 1606 | bf->bf_keytype = get_hw_crypto_keytype(skb); |
528f0c6b S |
1607 | if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) { |
1608 | bf->bf_frmlen += tx_info->control.hw_key->icv_len; | |
1609 | bf->bf_keyix = tx_info->control.hw_key->hw_key_idx; | |
1610 | } else { | |
1611 | bf->bf_keyix = ATH9K_TXKEYIX_INVALID; | |
1612 | } | |
1613 | ||
17b182e3 S |
1614 | if (ieee80211_is_data_qos(fc) && bf_isht(bf) && |
1615 | (sc->sc_flags & SC_OP_TXAGGR)) | |
528f0c6b S |
1616 | assign_aggr_tid_seqno(skb, bf); |
1617 | ||
f078f209 | 1618 | bf->bf_mpdu = skb; |
f8316df1 | 1619 | |
7da3c55c GJ |
1620 | bf->bf_dmacontext = dma_map_single(sc->dev, skb->data, |
1621 | skb->len, DMA_TO_DEVICE); | |
1622 | if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) { | |
f8316df1 | 1623 | bf->bf_mpdu = NULL; |
c46917bb LR |
1624 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
1625 | "dma_mapping_error() on TX\n"); | |
f8316df1 LR |
1626 | return -ENOMEM; |
1627 | } | |
1628 | ||
528f0c6b | 1629 | bf->bf_buf_addr = bf->bf_dmacontext; |
e7824a50 LR |
1630 | |
1631 | /* tag if this is a nullfunc frame to enable PS when AP acks it */ | |
1632 | if (ieee80211_is_nullfunc(fc) && ieee80211_has_pm(fc)) { | |
1633 | bf->bf_isnullfunc = true; | |
1b04b930 | 1634 | sc->ps_flags &= ~PS_NULLFUNC_COMPLETED; |
e7824a50 LR |
1635 | } else |
1636 | bf->bf_isnullfunc = false; | |
1637 | ||
f8316df1 | 1638 | return 0; |
528f0c6b S |
1639 | } |
1640 | ||
1641 | /* FIXME: tx power */ | |
1642 | static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf, | |
528f0c6b S |
1643 | struct ath_tx_control *txctl) |
1644 | { | |
a22be22a | 1645 | struct sk_buff *skb = bf->bf_mpdu; |
528f0c6b | 1646 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
c37452b0 | 1647 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
528f0c6b S |
1648 | struct ath_node *an = NULL; |
1649 | struct list_head bf_head; | |
1650 | struct ath_desc *ds; | |
1651 | struct ath_atx_tid *tid; | |
cbe61d8a | 1652 | struct ath_hw *ah = sc->sc_ah; |
528f0c6b | 1653 | int frm_type; |
c37452b0 | 1654 | __le16 fc; |
528f0c6b | 1655 | |
528f0c6b | 1656 | frm_type = get_hw_packet_type(skb); |
c37452b0 | 1657 | fc = hdr->frame_control; |
528f0c6b S |
1658 | |
1659 | INIT_LIST_HEAD(&bf_head); | |
1660 | list_add_tail(&bf->list, &bf_head); | |
f078f209 | 1661 | |
f078f209 | 1662 | ds = bf->bf_desc; |
87d5efbb | 1663 | ath9k_hw_set_desc_link(ah, ds, 0); |
f078f209 | 1664 | |
528f0c6b S |
1665 | ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER, |
1666 | bf->bf_keyix, bf->bf_keytype, bf->bf_flags); | |
1667 | ||
1668 | ath9k_hw_filltxdesc(ah, ds, | |
8f93b8b3 S |
1669 | skb->len, /* segment length */ |
1670 | true, /* first segment */ | |
1671 | true, /* last segment */ | |
3f3a1c80 VT |
1672 | ds, /* first descriptor */ |
1673 | bf->bf_buf_addr); | |
f078f209 | 1674 | |
528f0c6b | 1675 | spin_lock_bh(&txctl->txq->axq_lock); |
f078f209 | 1676 | |
f1617967 JL |
1677 | if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) && |
1678 | tx_info->control.sta) { | |
1679 | an = (struct ath_node *)tx_info->control.sta->drv_priv; | |
1680 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
1681 | ||
c37452b0 S |
1682 | if (!ieee80211_is_data_qos(fc)) { |
1683 | ath_tx_send_normal(sc, txctl->txq, &bf_head); | |
1684 | goto tx_done; | |
1685 | } | |
1686 | ||
4fdec031 | 1687 | if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { |
f078f209 LR |
1688 | /* |
1689 | * Try aggregation if it's a unicast data frame | |
1690 | * and the destination is HT capable. | |
1691 | */ | |
528f0c6b | 1692 | ath_tx_send_ampdu(sc, tid, &bf_head, txctl); |
f078f209 LR |
1693 | } else { |
1694 | /* | |
528f0c6b S |
1695 | * Send this frame as regular when ADDBA |
1696 | * exchange is neither complete nor pending. | |
f078f209 | 1697 | */ |
c37452b0 S |
1698 | ath_tx_send_ht_normal(sc, txctl->txq, |
1699 | tid, &bf_head); | |
f078f209 LR |
1700 | } |
1701 | } else { | |
c37452b0 | 1702 | ath_tx_send_normal(sc, txctl->txq, &bf_head); |
f078f209 | 1703 | } |
528f0c6b | 1704 | |
c37452b0 | 1705 | tx_done: |
528f0c6b | 1706 | spin_unlock_bh(&txctl->txq->axq_lock); |
f078f209 LR |
1707 | } |
1708 | ||
f8316df1 | 1709 | /* Upon failure caller should free skb */ |
c52f33d0 | 1710 | int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, |
528f0c6b | 1711 | struct ath_tx_control *txctl) |
f078f209 | 1712 | { |
c52f33d0 JM |
1713 | struct ath_wiphy *aphy = hw->priv; |
1714 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1715 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
528f0c6b | 1716 | struct ath_buf *bf; |
f8316df1 | 1717 | int r; |
f078f209 | 1718 | |
528f0c6b S |
1719 | bf = ath_tx_get_buffer(sc); |
1720 | if (!bf) { | |
c46917bb | 1721 | ath_print(common, ATH_DBG_XMIT, "TX buffers are full\n"); |
528f0c6b S |
1722 | return -1; |
1723 | } | |
1724 | ||
c52f33d0 | 1725 | r = ath_tx_setup_buffer(hw, bf, skb, txctl); |
f8316df1 | 1726 | if (unlikely(r)) { |
c112d0c5 LR |
1727 | struct ath_txq *txq = txctl->txq; |
1728 | ||
c46917bb | 1729 | ath_print(common, ATH_DBG_FATAL, "TX mem alloc failure\n"); |
c112d0c5 LR |
1730 | |
1731 | /* upon ath_tx_processq() this TX queue will be resumed, we | |
1732 | * guarantee this will happen by knowing beforehand that | |
1733 | * we will at least have to run TX completionon one buffer | |
1734 | * on the queue */ | |
1735 | spin_lock_bh(&txq->axq_lock); | |
f7a99e46 | 1736 | if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) { |
f52de03b | 1737 | ath_mac80211_stop_queue(sc, skb_get_queue_mapping(skb)); |
c112d0c5 LR |
1738 | txq->stopped = 1; |
1739 | } | |
1740 | spin_unlock_bh(&txq->axq_lock); | |
1741 | ||
b77f483f S |
1742 | spin_lock_bh(&sc->tx.txbuflock); |
1743 | list_add_tail(&bf->list, &sc->tx.txbuf); | |
1744 | spin_unlock_bh(&sc->tx.txbuflock); | |
c112d0c5 | 1745 | |
f8316df1 LR |
1746 | return r; |
1747 | } | |
1748 | ||
8f93b8b3 | 1749 | ath_tx_start_dma(sc, bf, txctl); |
f078f209 | 1750 | |
528f0c6b | 1751 | return 0; |
f078f209 LR |
1752 | } |
1753 | ||
c52f33d0 | 1754 | void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb) |
f078f209 | 1755 | { |
c52f33d0 JM |
1756 | struct ath_wiphy *aphy = hw->priv; |
1757 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1758 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
4d91f9f3 BP |
1759 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; |
1760 | int padpos, padsize; | |
e8324357 S |
1761 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
1762 | struct ath_tx_control txctl; | |
f078f209 | 1763 | |
e8324357 | 1764 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
f078f209 LR |
1765 | |
1766 | /* | |
e8324357 S |
1767 | * As a temporary workaround, assign seq# here; this will likely need |
1768 | * to be cleaned up to work better with Beacon transmission and virtual | |
1769 | * BSSes. | |
f078f209 | 1770 | */ |
e8324357 | 1771 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { |
e8324357 S |
1772 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) |
1773 | sc->tx.seq_no += 0x10; | |
1774 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); | |
1775 | hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); | |
f078f209 | 1776 | } |
f078f209 | 1777 | |
e8324357 | 1778 | /* Add the padding after the header if this is not already done */ |
4d91f9f3 BP |
1779 | padpos = ath9k_cmn_padpos(hdr->frame_control); |
1780 | padsize = padpos & 3; | |
1781 | if (padsize && skb->len>padpos) { | |
e8324357 | 1782 | if (skb_headroom(skb) < padsize) { |
c46917bb LR |
1783 | ath_print(common, ATH_DBG_XMIT, |
1784 | "TX CABQ padding failed\n"); | |
e8324357 S |
1785 | dev_kfree_skb_any(skb); |
1786 | return; | |
1787 | } | |
1788 | skb_push(skb, padsize); | |
4d91f9f3 | 1789 | memmove(skb->data, skb->data + padsize, padpos); |
f078f209 | 1790 | } |
f078f209 | 1791 | |
e8324357 | 1792 | txctl.txq = sc->beacon.cabq; |
f078f209 | 1793 | |
c46917bb LR |
1794 | ath_print(common, ATH_DBG_XMIT, |
1795 | "transmitting CABQ packet, skb: %p\n", skb); | |
f078f209 | 1796 | |
c52f33d0 | 1797 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
c46917bb | 1798 | ath_print(common, ATH_DBG_XMIT, "CABQ TX failed\n"); |
e8324357 | 1799 | goto exit; |
f078f209 | 1800 | } |
f078f209 | 1801 | |
e8324357 S |
1802 | return; |
1803 | exit: | |
1804 | dev_kfree_skb_any(skb); | |
f078f209 LR |
1805 | } |
1806 | ||
e8324357 S |
1807 | /*****************/ |
1808 | /* TX Completion */ | |
1809 | /*****************/ | |
528f0c6b | 1810 | |
e8324357 | 1811 | static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, |
827e69bf | 1812 | struct ath_wiphy *aphy, int tx_flags) |
528f0c6b | 1813 | { |
e8324357 S |
1814 | struct ieee80211_hw *hw = sc->hw; |
1815 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
c46917bb | 1816 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
4d91f9f3 BP |
1817 | struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data; |
1818 | int padpos, padsize; | |
528f0c6b | 1819 | |
c46917bb | 1820 | ath_print(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb); |
528f0c6b | 1821 | |
827e69bf FF |
1822 | if (aphy) |
1823 | hw = aphy->hw; | |
528f0c6b | 1824 | |
6b2c4032 | 1825 | if (tx_flags & ATH_TX_BAR) |
e8324357 | 1826 | tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; |
e8324357 | 1827 | |
6b2c4032 | 1828 | if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) { |
e8324357 S |
1829 | /* Frame was ACKed */ |
1830 | tx_info->flags |= IEEE80211_TX_STAT_ACK; | |
528f0c6b S |
1831 | } |
1832 | ||
4d91f9f3 BP |
1833 | padpos = ath9k_cmn_padpos(hdr->frame_control); |
1834 | padsize = padpos & 3; | |
1835 | if (padsize && skb->len>padpos+padsize) { | |
e8324357 S |
1836 | /* |
1837 | * Remove MAC header padding before giving the frame back to | |
1838 | * mac80211. | |
1839 | */ | |
4d91f9f3 | 1840 | memmove(skb->data + padsize, skb->data, padpos); |
e8324357 S |
1841 | skb_pull(skb, padsize); |
1842 | } | |
528f0c6b | 1843 | |
1b04b930 S |
1844 | if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) { |
1845 | sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK; | |
c46917bb LR |
1846 | ath_print(common, ATH_DBG_PS, |
1847 | "Going back to sleep after having " | |
f643e51d | 1848 | "received TX status (0x%lx)\n", |
1b04b930 S |
1849 | sc->ps_flags & (PS_WAIT_FOR_BEACON | |
1850 | PS_WAIT_FOR_CAB | | |
1851 | PS_WAIT_FOR_PSPOLL_DATA | | |
1852 | PS_WAIT_FOR_TX_ACK)); | |
9a23f9ca JM |
1853 | } |
1854 | ||
827e69bf | 1855 | if (unlikely(tx_info->pad[0] & ATH_TX_INFO_FRAME_TYPE_INTERNAL)) |
f0ed85c6 | 1856 | ath9k_tx_status(hw, skb); |
827e69bf FF |
1857 | else |
1858 | ieee80211_tx_status(hw, skb); | |
e8324357 | 1859 | } |
f078f209 | 1860 | |
e8324357 | 1861 | static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, |
db1a052b FF |
1862 | struct ath_txq *txq, struct list_head *bf_q, |
1863 | struct ath_tx_status *ts, int txok, int sendbar) | |
f078f209 | 1864 | { |
e8324357 | 1865 | struct sk_buff *skb = bf->bf_mpdu; |
e8324357 | 1866 | unsigned long flags; |
6b2c4032 | 1867 | int tx_flags = 0; |
f078f209 | 1868 | |
e8324357 | 1869 | if (sendbar) |
6b2c4032 | 1870 | tx_flags = ATH_TX_BAR; |
f078f209 | 1871 | |
e8324357 | 1872 | if (!txok) { |
6b2c4032 | 1873 | tx_flags |= ATH_TX_ERROR; |
f078f209 | 1874 | |
e8324357 | 1875 | if (bf_isxretried(bf)) |
6b2c4032 | 1876 | tx_flags |= ATH_TX_XRETRY; |
f078f209 LR |
1877 | } |
1878 | ||
e8324357 | 1879 | dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE); |
827e69bf | 1880 | ath_tx_complete(sc, skb, bf->aphy, tx_flags); |
db1a052b | 1881 | ath_debug_stat_tx(sc, txq, bf, ts); |
e8324357 S |
1882 | |
1883 | /* | |
1884 | * Return the list of ath_buf of this mpdu to free queue | |
1885 | */ | |
1886 | spin_lock_irqsave(&sc->tx.txbuflock, flags); | |
1887 | list_splice_tail_init(bf_q, &sc->tx.txbuf); | |
1888 | spin_unlock_irqrestore(&sc->tx.txbuflock, flags); | |
f078f209 LR |
1889 | } |
1890 | ||
e8324357 | 1891 | static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf, |
db1a052b | 1892 | struct ath_tx_status *ts, int txok) |
f078f209 | 1893 | { |
e8324357 S |
1894 | u16 seq_st = 0; |
1895 | u32 ba[WME_BA_BMP_SIZE >> 5]; | |
1896 | int ba_index; | |
1897 | int nbad = 0; | |
1898 | int isaggr = 0; | |
f078f209 | 1899 | |
db1a052b | 1900 | if (ts->ts_flags == ATH9K_TX_SW_ABORTED) |
e8324357 | 1901 | return 0; |
f078f209 | 1902 | |
e8324357 S |
1903 | isaggr = bf_isaggr(bf); |
1904 | if (isaggr) { | |
db1a052b FF |
1905 | seq_st = ts->ts_seqnum; |
1906 | memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); | |
e8324357 | 1907 | } |
f078f209 | 1908 | |
e8324357 S |
1909 | while (bf) { |
1910 | ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno); | |
1911 | if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index))) | |
1912 | nbad++; | |
1913 | ||
1914 | bf = bf->bf_next; | |
1915 | } | |
f078f209 | 1916 | |
e8324357 S |
1917 | return nbad; |
1918 | } | |
f078f209 | 1919 | |
db1a052b | 1920 | static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts, |
8a92e2ee | 1921 | int nbad, int txok, bool update_rc) |
f078f209 | 1922 | { |
a22be22a | 1923 | struct sk_buff *skb = bf->bf_mpdu; |
254ad0ff | 1924 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
e8324357 | 1925 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
827e69bf | 1926 | struct ieee80211_hw *hw = bf->aphy->hw; |
8a92e2ee | 1927 | u8 i, tx_rateindex; |
f078f209 | 1928 | |
95e4acb7 | 1929 | if (txok) |
db1a052b | 1930 | tx_info->status.ack_signal = ts->ts_rssi; |
95e4acb7 | 1931 | |
db1a052b | 1932 | tx_rateindex = ts->ts_rateindex; |
8a92e2ee VT |
1933 | WARN_ON(tx_rateindex >= hw->max_rates); |
1934 | ||
db1a052b | 1935 | if (ts->ts_status & ATH9K_TXERR_FILT) |
e8324357 | 1936 | tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; |
d969847c FF |
1937 | if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc) |
1938 | tx_info->flags |= IEEE80211_TX_STAT_AMPDU; | |
f078f209 | 1939 | |
db1a052b | 1940 | if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 && |
8a92e2ee | 1941 | (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) { |
254ad0ff | 1942 | if (ieee80211_is_data(hdr->frame_control)) { |
db1a052b | 1943 | if (ts->ts_flags & |
827e69bf FF |
1944 | (ATH9K_TX_DATA_UNDERRUN | ATH9K_TX_DELIM_UNDERRUN)) |
1945 | tx_info->pad[0] |= ATH_TX_INFO_UNDERRUN; | |
db1a052b FF |
1946 | if ((ts->ts_status & ATH9K_TXERR_XRETRY) || |
1947 | (ts->ts_status & ATH9K_TXERR_FIFO)) | |
827e69bf FF |
1948 | tx_info->pad[0] |= ATH_TX_INFO_XRETRY; |
1949 | tx_info->status.ampdu_len = bf->bf_nframes; | |
1950 | tx_info->status.ampdu_ack_len = bf->bf_nframes - nbad; | |
e8324357 | 1951 | } |
f078f209 | 1952 | } |
8a92e2ee | 1953 | |
545750d3 | 1954 | for (i = tx_rateindex + 1; i < hw->max_rates; i++) { |
8a92e2ee | 1955 | tx_info->status.rates[i].count = 0; |
545750d3 FF |
1956 | tx_info->status.rates[i].idx = -1; |
1957 | } | |
8a92e2ee VT |
1958 | |
1959 | tx_info->status.rates[tx_rateindex].count = bf->bf_retries + 1; | |
f078f209 LR |
1960 | } |
1961 | ||
059d806c S |
1962 | static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq) |
1963 | { | |
1964 | int qnum; | |
1965 | ||
1966 | spin_lock_bh(&txq->axq_lock); | |
1967 | if (txq->stopped && | |
f7a99e46 | 1968 | sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) { |
059d806c S |
1969 | qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc); |
1970 | if (qnum != -1) { | |
f52de03b | 1971 | ath_mac80211_start_queue(sc, qnum); |
059d806c S |
1972 | txq->stopped = 0; |
1973 | } | |
1974 | } | |
1975 | spin_unlock_bh(&txq->axq_lock); | |
1976 | } | |
1977 | ||
e8324357 | 1978 | static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) |
f078f209 | 1979 | { |
cbe61d8a | 1980 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1981 | struct ath_common *common = ath9k_hw_common(ah); |
e8324357 | 1982 | struct ath_buf *bf, *lastbf, *bf_held = NULL; |
f078f209 | 1983 | struct list_head bf_head; |
e8324357 | 1984 | struct ath_desc *ds; |
29bffa96 | 1985 | struct ath_tx_status ts; |
0934af23 | 1986 | int txok; |
e8324357 | 1987 | int status; |
f078f209 | 1988 | |
c46917bb LR |
1989 | ath_print(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n", |
1990 | txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), | |
1991 | txq->axq_link); | |
f078f209 | 1992 | |
f078f209 LR |
1993 | for (;;) { |
1994 | spin_lock_bh(&txq->axq_lock); | |
f078f209 LR |
1995 | if (list_empty(&txq->axq_q)) { |
1996 | txq->axq_link = NULL; | |
f078f209 LR |
1997 | spin_unlock_bh(&txq->axq_lock); |
1998 | break; | |
1999 | } | |
f078f209 LR |
2000 | bf = list_first_entry(&txq->axq_q, struct ath_buf, list); |
2001 | ||
e8324357 S |
2002 | /* |
2003 | * There is a race condition that a BH gets scheduled | |
2004 | * after sw writes TxE and before hw re-load the last | |
2005 | * descriptor to get the newly chained one. | |
2006 | * Software must keep the last DONE descriptor as a | |
2007 | * holding descriptor - software does so by marking | |
2008 | * it with the STALE flag. | |
2009 | */ | |
2010 | bf_held = NULL; | |
a119cc49 | 2011 | if (bf->bf_stale) { |
e8324357 S |
2012 | bf_held = bf; |
2013 | if (list_is_last(&bf_held->list, &txq->axq_q)) { | |
6ef9b13d | 2014 | spin_unlock_bh(&txq->axq_lock); |
e8324357 S |
2015 | break; |
2016 | } else { | |
2017 | bf = list_entry(bf_held->list.next, | |
6ef9b13d | 2018 | struct ath_buf, list); |
e8324357 | 2019 | } |
f078f209 LR |
2020 | } |
2021 | ||
2022 | lastbf = bf->bf_lastbf; | |
e8324357 | 2023 | ds = lastbf->bf_desc; |
f078f209 | 2024 | |
29bffa96 FF |
2025 | memset(&ts, 0, sizeof(ts)); |
2026 | status = ath9k_hw_txprocdesc(ah, ds, &ts); | |
e8324357 | 2027 | if (status == -EINPROGRESS) { |
f078f209 | 2028 | spin_unlock_bh(&txq->axq_lock); |
e8324357 | 2029 | break; |
f078f209 | 2030 | } |
f078f209 | 2031 | |
e7824a50 LR |
2032 | /* |
2033 | * We now know the nullfunc frame has been ACKed so we | |
2034 | * can disable RX. | |
2035 | */ | |
2036 | if (bf->bf_isnullfunc && | |
29bffa96 | 2037 | (ts.ts_status & ATH9K_TX_ACKED)) { |
3f7c5c10 SB |
2038 | if ((sc->ps_flags & PS_ENABLED)) |
2039 | ath9k_enable_ps(sc); | |
2040 | else | |
1b04b930 | 2041 | sc->ps_flags |= PS_NULLFUNC_COMPLETED; |
e7824a50 LR |
2042 | } |
2043 | ||
e8324357 S |
2044 | /* |
2045 | * Remove ath_buf's of the same transmit unit from txq, | |
2046 | * however leave the last descriptor back as the holding | |
2047 | * descriptor for hw. | |
2048 | */ | |
a119cc49 | 2049 | lastbf->bf_stale = true; |
e8324357 | 2050 | INIT_LIST_HEAD(&bf_head); |
e8324357 S |
2051 | if (!list_is_singular(&lastbf->list)) |
2052 | list_cut_position(&bf_head, | |
2053 | &txq->axq_q, lastbf->list.prev); | |
f078f209 | 2054 | |
e8324357 | 2055 | txq->axq_depth--; |
29bffa96 | 2056 | txok = !(ts.ts_status & ATH9K_TXERR_MASK); |
164ace38 | 2057 | txq->axq_tx_inprogress = false; |
e8324357 | 2058 | spin_unlock_bh(&txq->axq_lock); |
f078f209 | 2059 | |
e8324357 | 2060 | if (bf_held) { |
e8324357 | 2061 | spin_lock_bh(&sc->tx.txbuflock); |
6ef9b13d | 2062 | list_move_tail(&bf_held->list, &sc->tx.txbuf); |
e8324357 S |
2063 | spin_unlock_bh(&sc->tx.txbuflock); |
2064 | } | |
f078f209 | 2065 | |
e8324357 S |
2066 | if (!bf_isampdu(bf)) { |
2067 | /* | |
2068 | * This frame is sent out as a single frame. | |
2069 | * Use hardware retry status for this frame. | |
2070 | */ | |
29bffa96 FF |
2071 | bf->bf_retries = ts.ts_longretry; |
2072 | if (ts.ts_status & ATH9K_TXERR_XRETRY) | |
e8324357 | 2073 | bf->bf_state.bf_type |= BUF_XRETRY; |
29bffa96 | 2074 | ath_tx_rc_status(bf, &ts, 0, txok, true); |
e8324357 | 2075 | } |
f078f209 | 2076 | |
e8324357 | 2077 | if (bf_isampdu(bf)) |
29bffa96 | 2078 | ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, txok); |
e8324357 | 2079 | else |
29bffa96 | 2080 | ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, txok, 0); |
8469cdef | 2081 | |
059d806c | 2082 | ath_wake_mac80211_queue(sc, txq); |
8469cdef | 2083 | |
059d806c | 2084 | spin_lock_bh(&txq->axq_lock); |
e8324357 S |
2085 | if (sc->sc_flags & SC_OP_TXAGGR) |
2086 | ath_txq_schedule(sc, txq); | |
2087 | spin_unlock_bh(&txq->axq_lock); | |
8469cdef S |
2088 | } |
2089 | } | |
2090 | ||
305fe47f | 2091 | static void ath_tx_complete_poll_work(struct work_struct *work) |
164ace38 SB |
2092 | { |
2093 | struct ath_softc *sc = container_of(work, struct ath_softc, | |
2094 | tx_complete_work.work); | |
2095 | struct ath_txq *txq; | |
2096 | int i; | |
2097 | bool needreset = false; | |
2098 | ||
2099 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) | |
2100 | if (ATH_TXQ_SETUP(sc, i)) { | |
2101 | txq = &sc->tx.txq[i]; | |
2102 | spin_lock_bh(&txq->axq_lock); | |
2103 | if (txq->axq_depth) { | |
2104 | if (txq->axq_tx_inprogress) { | |
2105 | needreset = true; | |
2106 | spin_unlock_bh(&txq->axq_lock); | |
2107 | break; | |
2108 | } else { | |
2109 | txq->axq_tx_inprogress = true; | |
2110 | } | |
2111 | } | |
2112 | spin_unlock_bh(&txq->axq_lock); | |
2113 | } | |
2114 | ||
2115 | if (needreset) { | |
c46917bb LR |
2116 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET, |
2117 | "tx hung, resetting the chip\n"); | |
332c5566 | 2118 | ath9k_ps_wakeup(sc); |
164ace38 | 2119 | ath_reset(sc, false); |
332c5566 | 2120 | ath9k_ps_restore(sc); |
164ace38 SB |
2121 | } |
2122 | ||
42935eca | 2123 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, |
164ace38 SB |
2124 | msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT)); |
2125 | } | |
2126 | ||
2127 | ||
f078f209 | 2128 | |
e8324357 | 2129 | void ath_tx_tasklet(struct ath_softc *sc) |
f078f209 | 2130 | { |
e8324357 S |
2131 | int i; |
2132 | u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1); | |
f078f209 | 2133 | |
e8324357 | 2134 | ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask); |
f078f209 | 2135 | |
e8324357 S |
2136 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
2137 | if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i))) | |
2138 | ath_tx_processq(sc, &sc->tx.txq[i]); | |
f078f209 LR |
2139 | } |
2140 | } | |
2141 | ||
e8324357 S |
2142 | /*****************/ |
2143 | /* Init, Cleanup */ | |
2144 | /*****************/ | |
f078f209 | 2145 | |
e8324357 | 2146 | int ath_tx_init(struct ath_softc *sc, int nbufs) |
f078f209 | 2147 | { |
c46917bb | 2148 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
e8324357 | 2149 | int error = 0; |
f078f209 | 2150 | |
797fe5cb | 2151 | spin_lock_init(&sc->tx.txbuflock); |
f078f209 | 2152 | |
797fe5cb S |
2153 | error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, |
2154 | "tx", nbufs, 1); | |
2155 | if (error != 0) { | |
c46917bb LR |
2156 | ath_print(common, ATH_DBG_FATAL, |
2157 | "Failed to allocate tx descriptors: %d\n", error); | |
797fe5cb S |
2158 | goto err; |
2159 | } | |
f078f209 | 2160 | |
797fe5cb S |
2161 | error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, |
2162 | "beacon", ATH_BCBUF, 1); | |
2163 | if (error != 0) { | |
c46917bb LR |
2164 | ath_print(common, ATH_DBG_FATAL, |
2165 | "Failed to allocate beacon descriptors: %d\n", error); | |
797fe5cb S |
2166 | goto err; |
2167 | } | |
f078f209 | 2168 | |
164ace38 SB |
2169 | INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work); |
2170 | ||
797fe5cb | 2171 | err: |
e8324357 S |
2172 | if (error != 0) |
2173 | ath_tx_cleanup(sc); | |
f078f209 | 2174 | |
e8324357 | 2175 | return error; |
f078f209 LR |
2176 | } |
2177 | ||
797fe5cb | 2178 | void ath_tx_cleanup(struct ath_softc *sc) |
e8324357 S |
2179 | { |
2180 | if (sc->beacon.bdma.dd_desc_len != 0) | |
2181 | ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf); | |
2182 | ||
2183 | if (sc->tx.txdma.dd_desc_len != 0) | |
2184 | ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf); | |
e8324357 | 2185 | } |
f078f209 LR |
2186 | |
2187 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an) | |
2188 | { | |
c5170163 S |
2189 | struct ath_atx_tid *tid; |
2190 | struct ath_atx_ac *ac; | |
2191 | int tidno, acno; | |
f078f209 | 2192 | |
8ee5afbc | 2193 | for (tidno = 0, tid = &an->tid[tidno]; |
c5170163 S |
2194 | tidno < WME_NUM_TID; |
2195 | tidno++, tid++) { | |
2196 | tid->an = an; | |
2197 | tid->tidno = tidno; | |
2198 | tid->seq_start = tid->seq_next = 0; | |
2199 | tid->baw_size = WME_MAX_BA; | |
2200 | tid->baw_head = tid->baw_tail = 0; | |
2201 | tid->sched = false; | |
e8324357 | 2202 | tid->paused = false; |
a37c2c79 | 2203 | tid->state &= ~AGGR_CLEANUP; |
c5170163 | 2204 | INIT_LIST_HEAD(&tid->buf_q); |
c5170163 | 2205 | acno = TID_TO_WME_AC(tidno); |
8ee5afbc | 2206 | tid->ac = &an->ac[acno]; |
a37c2c79 S |
2207 | tid->state &= ~AGGR_ADDBA_COMPLETE; |
2208 | tid->state &= ~AGGR_ADDBA_PROGRESS; | |
c5170163 | 2209 | } |
f078f209 | 2210 | |
8ee5afbc | 2211 | for (acno = 0, ac = &an->ac[acno]; |
c5170163 S |
2212 | acno < WME_NUM_AC; acno++, ac++) { |
2213 | ac->sched = false; | |
2214 | INIT_LIST_HEAD(&ac->tid_q); | |
2215 | ||
2216 | switch (acno) { | |
2217 | case WME_AC_BE: | |
2218 | ac->qnum = ath_tx_get_qnum(sc, | |
2219 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE); | |
2220 | break; | |
2221 | case WME_AC_BK: | |
2222 | ac->qnum = ath_tx_get_qnum(sc, | |
2223 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK); | |
2224 | break; | |
2225 | case WME_AC_VI: | |
2226 | ac->qnum = ath_tx_get_qnum(sc, | |
2227 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI); | |
2228 | break; | |
2229 | case WME_AC_VO: | |
2230 | ac->qnum = ath_tx_get_qnum(sc, | |
2231 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO); | |
2232 | break; | |
f078f209 LR |
2233 | } |
2234 | } | |
2235 | } | |
2236 | ||
b5aa9bf9 | 2237 | void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an) |
f078f209 LR |
2238 | { |
2239 | int i; | |
2240 | struct ath_atx_ac *ac, *ac_tmp; | |
2241 | struct ath_atx_tid *tid, *tid_tmp; | |
2242 | struct ath_txq *txq; | |
e8324357 | 2243 | |
f078f209 LR |
2244 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
2245 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f | 2246 | txq = &sc->tx.txq[i]; |
f078f209 | 2247 | |
a9f042cb | 2248 | spin_lock_bh(&txq->axq_lock); |
f078f209 LR |
2249 | |
2250 | list_for_each_entry_safe(ac, | |
2251 | ac_tmp, &txq->axq_acq, list) { | |
2252 | tid = list_first_entry(&ac->tid_q, | |
2253 | struct ath_atx_tid, list); | |
2254 | if (tid && tid->an != an) | |
2255 | continue; | |
2256 | list_del(&ac->list); | |
2257 | ac->sched = false; | |
2258 | ||
2259 | list_for_each_entry_safe(tid, | |
2260 | tid_tmp, &ac->tid_q, list) { | |
2261 | list_del(&tid->list); | |
2262 | tid->sched = false; | |
b5aa9bf9 | 2263 | ath_tid_drain(sc, txq, tid); |
a37c2c79 | 2264 | tid->state &= ~AGGR_ADDBA_COMPLETE; |
a37c2c79 | 2265 | tid->state &= ~AGGR_CLEANUP; |
f078f209 LR |
2266 | } |
2267 | } | |
2268 | ||
a9f042cb | 2269 | spin_unlock_bh(&txq->axq_lock); |
f078f209 LR |
2270 | } |
2271 | } | |
2272 | } |