Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
394cf0a1 | 17 | #include "ath9k.h" |
f078f209 LR |
18 | |
19 | #define BITS_PER_BYTE 8 | |
20 | #define OFDM_PLCP_BITS 22 | |
21 | #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f) | |
22 | #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) | |
23 | #define L_STF 8 | |
24 | #define L_LTF 8 | |
25 | #define L_SIG 4 | |
26 | #define HT_SIG 8 | |
27 | #define HT_STF 4 | |
28 | #define HT_LTF(_ns) (4 * (_ns)) | |
29 | #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */ | |
30 | #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */ | |
31 | #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) | |
32 | #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) | |
33 | ||
34 | #define OFDM_SIFS_TIME 16 | |
35 | ||
36 | static u32 bits_per_symbol[][2] = { | |
37 | /* 20MHz 40MHz */ | |
38 | { 26, 54 }, /* 0: BPSK */ | |
39 | { 52, 108 }, /* 1: QPSK 1/2 */ | |
40 | { 78, 162 }, /* 2: QPSK 3/4 */ | |
41 | { 104, 216 }, /* 3: 16-QAM 1/2 */ | |
42 | { 156, 324 }, /* 4: 16-QAM 3/4 */ | |
43 | { 208, 432 }, /* 5: 64-QAM 2/3 */ | |
44 | { 234, 486 }, /* 6: 64-QAM 3/4 */ | |
45 | { 260, 540 }, /* 7: 64-QAM 5/6 */ | |
46 | { 52, 108 }, /* 8: BPSK */ | |
47 | { 104, 216 }, /* 9: QPSK 1/2 */ | |
48 | { 156, 324 }, /* 10: QPSK 3/4 */ | |
49 | { 208, 432 }, /* 11: 16-QAM 1/2 */ | |
50 | { 312, 648 }, /* 12: 16-QAM 3/4 */ | |
51 | { 416, 864 }, /* 13: 64-QAM 2/3 */ | |
52 | { 468, 972 }, /* 14: 64-QAM 3/4 */ | |
53 | { 520, 1080 }, /* 15: 64-QAM 5/6 */ | |
54 | }; | |
55 | ||
56 | #define IS_HT_RATE(_rate) ((_rate) & 0x80) | |
57 | ||
c37452b0 S |
58 | static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq, |
59 | struct ath_atx_tid *tid, | |
60 | struct list_head *bf_head); | |
e8324357 S |
61 | static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, |
62 | struct list_head *bf_q, | |
63 | int txok, int sendbar); | |
102e0572 | 64 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, |
e8324357 S |
65 | struct list_head *head); |
66 | static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf); | |
0934af23 VT |
67 | static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf, |
68 | int txok); | |
69 | static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds, | |
8a92e2ee | 70 | int nbad, int txok, bool update_rc); |
c4288390 | 71 | |
e8324357 S |
72 | /*********************/ |
73 | /* Aggregation logic */ | |
74 | /*********************/ | |
f078f209 | 75 | |
a37c2c79 | 76 | static int ath_aggr_query(struct ath_softc *sc, struct ath_node *an, u8 tidno) |
f078f209 LR |
77 | { |
78 | struct ath_atx_tid *tid; | |
79 | tid = ATH_AN_2_TID(an, tidno); | |
80 | ||
a37c2c79 S |
81 | if (tid->state & AGGR_ADDBA_COMPLETE || |
82 | tid->state & AGGR_ADDBA_PROGRESS) | |
f078f209 LR |
83 | return 1; |
84 | else | |
85 | return 0; | |
86 | } | |
87 | ||
e8324357 | 88 | static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid) |
ff37e337 | 89 | { |
e8324357 | 90 | struct ath_atx_ac *ac = tid->ac; |
ff37e337 | 91 | |
e8324357 S |
92 | if (tid->paused) |
93 | return; | |
ff37e337 | 94 | |
e8324357 S |
95 | if (tid->sched) |
96 | return; | |
ff37e337 | 97 | |
e8324357 S |
98 | tid->sched = true; |
99 | list_add_tail(&tid->list, &ac->tid_q); | |
528f0c6b | 100 | |
e8324357 S |
101 | if (ac->sched) |
102 | return; | |
f078f209 | 103 | |
e8324357 S |
104 | ac->sched = true; |
105 | list_add_tail(&ac->list, &txq->axq_acq); | |
106 | } | |
f078f209 | 107 | |
e8324357 S |
108 | static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
109 | { | |
110 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; | |
f078f209 | 111 | |
e8324357 S |
112 | spin_lock_bh(&txq->axq_lock); |
113 | tid->paused++; | |
114 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 LR |
115 | } |
116 | ||
e8324357 | 117 | static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
f078f209 | 118 | { |
e8324357 | 119 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; |
e6a9854b | 120 | |
e8324357 S |
121 | ASSERT(tid->paused > 0); |
122 | spin_lock_bh(&txq->axq_lock); | |
f078f209 | 123 | |
e8324357 | 124 | tid->paused--; |
f078f209 | 125 | |
e8324357 S |
126 | if (tid->paused > 0) |
127 | goto unlock; | |
f078f209 | 128 | |
e8324357 S |
129 | if (list_empty(&tid->buf_q)) |
130 | goto unlock; | |
f078f209 | 131 | |
e8324357 S |
132 | ath_tx_queue_tid(txq, tid); |
133 | ath_txq_schedule(sc, txq); | |
134 | unlock: | |
135 | spin_unlock_bh(&txq->axq_lock); | |
528f0c6b | 136 | } |
f078f209 | 137 | |
e8324357 | 138 | static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
528f0c6b | 139 | { |
e8324357 S |
140 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; |
141 | struct ath_buf *bf; | |
142 | struct list_head bf_head; | |
143 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 144 | |
e8324357 S |
145 | ASSERT(tid->paused > 0); |
146 | spin_lock_bh(&txq->axq_lock); | |
e6a9854b | 147 | |
e8324357 | 148 | tid->paused--; |
f078f209 | 149 | |
e8324357 S |
150 | if (tid->paused > 0) { |
151 | spin_unlock_bh(&txq->axq_lock); | |
152 | return; | |
153 | } | |
f078f209 | 154 | |
e8324357 S |
155 | while (!list_empty(&tid->buf_q)) { |
156 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); | |
157 | ASSERT(!bf_isretried(bf)); | |
d43f3015 | 158 | list_move_tail(&bf->list, &bf_head); |
c37452b0 | 159 | ath_tx_send_ht_normal(sc, txq, tid, &bf_head); |
528f0c6b | 160 | } |
f078f209 | 161 | |
e8324357 | 162 | spin_unlock_bh(&txq->axq_lock); |
528f0c6b | 163 | } |
f078f209 | 164 | |
e8324357 S |
165 | static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
166 | int seqno) | |
528f0c6b | 167 | { |
e8324357 | 168 | int index, cindex; |
f078f209 | 169 | |
e8324357 S |
170 | index = ATH_BA_INDEX(tid->seq_start, seqno); |
171 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | |
f078f209 | 172 | |
e8324357 | 173 | tid->tx_buf[cindex] = NULL; |
528f0c6b | 174 | |
e8324357 S |
175 | while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) { |
176 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); | |
177 | INCR(tid->baw_head, ATH_TID_MAX_BUFS); | |
178 | } | |
528f0c6b | 179 | } |
f078f209 | 180 | |
e8324357 S |
181 | static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
182 | struct ath_buf *bf) | |
528f0c6b | 183 | { |
e8324357 | 184 | int index, cindex; |
528f0c6b | 185 | |
e8324357 S |
186 | if (bf_isretried(bf)) |
187 | return; | |
528f0c6b | 188 | |
e8324357 S |
189 | index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno); |
190 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | |
f078f209 | 191 | |
e8324357 S |
192 | ASSERT(tid->tx_buf[cindex] == NULL); |
193 | tid->tx_buf[cindex] = bf; | |
f078f209 | 194 | |
e8324357 S |
195 | if (index >= ((tid->baw_tail - tid->baw_head) & |
196 | (ATH_TID_MAX_BUFS - 1))) { | |
197 | tid->baw_tail = cindex; | |
198 | INCR(tid->baw_tail, ATH_TID_MAX_BUFS); | |
f078f209 | 199 | } |
f078f209 LR |
200 | } |
201 | ||
202 | /* | |
e8324357 S |
203 | * TODO: For frame(s) that are in the retry state, we will reuse the |
204 | * sequence number(s) without setting the retry bit. The | |
205 | * alternative is to give up on these and BAR the receiver's window | |
206 | * forward. | |
f078f209 | 207 | */ |
e8324357 S |
208 | static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq, |
209 | struct ath_atx_tid *tid) | |
f078f209 | 210 | |
f078f209 | 211 | { |
e8324357 S |
212 | struct ath_buf *bf; |
213 | struct list_head bf_head; | |
214 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 215 | |
e8324357 S |
216 | for (;;) { |
217 | if (list_empty(&tid->buf_q)) | |
218 | break; | |
f078f209 | 219 | |
d43f3015 S |
220 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); |
221 | list_move_tail(&bf->list, &bf_head); | |
f078f209 | 222 | |
e8324357 S |
223 | if (bf_isretried(bf)) |
224 | ath_tx_update_baw(sc, tid, bf->bf_seqno); | |
f078f209 | 225 | |
e8324357 S |
226 | spin_unlock(&txq->axq_lock); |
227 | ath_tx_complete_buf(sc, bf, &bf_head, 0, 0); | |
228 | spin_lock(&txq->axq_lock); | |
229 | } | |
f078f209 | 230 | |
e8324357 S |
231 | tid->seq_next = tid->seq_start; |
232 | tid->baw_tail = tid->baw_head; | |
f078f209 LR |
233 | } |
234 | ||
e8324357 | 235 | static void ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf) |
f078f209 | 236 | { |
e8324357 S |
237 | struct sk_buff *skb; |
238 | struct ieee80211_hdr *hdr; | |
f078f209 | 239 | |
e8324357 S |
240 | bf->bf_state.bf_type |= BUF_RETRY; |
241 | bf->bf_retries++; | |
f078f209 | 242 | |
e8324357 S |
243 | skb = bf->bf_mpdu; |
244 | hdr = (struct ieee80211_hdr *)skb->data; | |
245 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); | |
f078f209 LR |
246 | } |
247 | ||
d43f3015 S |
248 | static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf) |
249 | { | |
250 | struct ath_buf *tbf; | |
251 | ||
252 | spin_lock_bh(&sc->tx.txbuflock); | |
253 | ASSERT(!list_empty((&sc->tx.txbuf))); | |
254 | tbf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); | |
255 | list_del(&tbf->list); | |
256 | spin_unlock_bh(&sc->tx.txbuflock); | |
257 | ||
258 | ATH_TXBUF_RESET(tbf); | |
259 | ||
260 | tbf->bf_mpdu = bf->bf_mpdu; | |
261 | tbf->bf_buf_addr = bf->bf_buf_addr; | |
262 | *(tbf->bf_desc) = *(bf->bf_desc); | |
263 | tbf->bf_state = bf->bf_state; | |
264 | tbf->bf_dmacontext = bf->bf_dmacontext; | |
265 | ||
266 | return tbf; | |
267 | } | |
268 | ||
269 | static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, | |
270 | struct ath_buf *bf, struct list_head *bf_q, | |
271 | int txok) | |
f078f209 | 272 | { |
e8324357 S |
273 | struct ath_node *an = NULL; |
274 | struct sk_buff *skb; | |
1286ec6d S |
275 | struct ieee80211_sta *sta; |
276 | struct ieee80211_hdr *hdr; | |
e8324357 | 277 | struct ath_atx_tid *tid = NULL; |
d43f3015 | 278 | struct ath_buf *bf_next, *bf_last = bf->bf_lastbf; |
f078f209 | 279 | struct ath_desc *ds = bf_last->bf_desc; |
e8324357 | 280 | struct list_head bf_head, bf_pending; |
0934af23 | 281 | u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0; |
f078f209 | 282 | u32 ba[WME_BA_BMP_SIZE >> 5]; |
0934af23 VT |
283 | int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0; |
284 | bool rc_update = true; | |
f078f209 | 285 | |
a22be22a | 286 | skb = bf->bf_mpdu; |
1286ec6d S |
287 | hdr = (struct ieee80211_hdr *)skb->data; |
288 | ||
289 | rcu_read_lock(); | |
f078f209 | 290 | |
1286ec6d S |
291 | sta = ieee80211_find_sta(sc->hw, hdr->addr1); |
292 | if (!sta) { | |
293 | rcu_read_unlock(); | |
294 | return; | |
f078f209 LR |
295 | } |
296 | ||
1286ec6d S |
297 | an = (struct ath_node *)sta->drv_priv; |
298 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
299 | ||
e8324357 | 300 | isaggr = bf_isaggr(bf); |
d43f3015 | 301 | memset(ba, 0, WME_BA_BMP_SIZE >> 3); |
f078f209 | 302 | |
d43f3015 S |
303 | if (isaggr && txok) { |
304 | if (ATH_DS_TX_BA(ds)) { | |
305 | seq_st = ATH_DS_BA_SEQ(ds); | |
306 | memcpy(ba, ATH_DS_BA_BITMAP(ds), | |
307 | WME_BA_BMP_SIZE >> 3); | |
e8324357 | 308 | } else { |
d43f3015 S |
309 | /* |
310 | * AR5416 can become deaf/mute when BA | |
311 | * issue happens. Chip needs to be reset. | |
312 | * But AP code may have sychronization issues | |
313 | * when perform internal reset in this routine. | |
314 | * Only enable reset in STA mode for now. | |
315 | */ | |
2660b81a | 316 | if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) |
d43f3015 | 317 | needreset = 1; |
e8324357 | 318 | } |
f078f209 LR |
319 | } |
320 | ||
e8324357 S |
321 | INIT_LIST_HEAD(&bf_pending); |
322 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 323 | |
0934af23 | 324 | nbad = ath_tx_num_badfrms(sc, bf, txok); |
e8324357 S |
325 | while (bf) { |
326 | txfail = txpending = 0; | |
327 | bf_next = bf->bf_next; | |
f078f209 | 328 | |
e8324357 S |
329 | if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) { |
330 | /* transmit completion, subframe is | |
331 | * acked by block ack */ | |
0934af23 | 332 | acked_cnt++; |
e8324357 S |
333 | } else if (!isaggr && txok) { |
334 | /* transmit completion */ | |
0934af23 | 335 | acked_cnt++; |
e8324357 | 336 | } else { |
e8324357 S |
337 | if (!(tid->state & AGGR_CLEANUP) && |
338 | ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) { | |
339 | if (bf->bf_retries < ATH_MAX_SW_RETRIES) { | |
340 | ath_tx_set_retry(sc, bf); | |
341 | txpending = 1; | |
342 | } else { | |
343 | bf->bf_state.bf_type |= BUF_XRETRY; | |
344 | txfail = 1; | |
345 | sendbar = 1; | |
0934af23 | 346 | txfail_cnt++; |
e8324357 S |
347 | } |
348 | } else { | |
349 | /* | |
350 | * cleanup in progress, just fail | |
351 | * the un-acked sub-frames | |
352 | */ | |
353 | txfail = 1; | |
354 | } | |
355 | } | |
f078f209 | 356 | |
e8324357 | 357 | if (bf_next == NULL) { |
d43f3015 | 358 | INIT_LIST_HEAD(&bf_head); |
e8324357 S |
359 | } else { |
360 | ASSERT(!list_empty(bf_q)); | |
d43f3015 | 361 | list_move_tail(&bf->list, &bf_head); |
e8324357 | 362 | } |
f078f209 | 363 | |
e8324357 S |
364 | if (!txpending) { |
365 | /* | |
366 | * complete the acked-ones/xretried ones; update | |
367 | * block-ack window | |
368 | */ | |
369 | spin_lock_bh(&txq->axq_lock); | |
370 | ath_tx_update_baw(sc, tid, bf->bf_seqno); | |
371 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 | 372 | |
8a92e2ee VT |
373 | if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) { |
374 | ath_tx_rc_status(bf, ds, nbad, txok, true); | |
375 | rc_update = false; | |
376 | } else { | |
377 | ath_tx_rc_status(bf, ds, nbad, txok, false); | |
378 | } | |
379 | ||
e8324357 S |
380 | ath_tx_complete_buf(sc, bf, &bf_head, !txfail, sendbar); |
381 | } else { | |
d43f3015 | 382 | /* retry the un-acked ones */ |
a119cc49 | 383 | if (bf->bf_next == NULL && bf_last->bf_stale) { |
e8324357 | 384 | struct ath_buf *tbf; |
f078f209 | 385 | |
d43f3015 S |
386 | tbf = ath_clone_txbuf(sc, bf_last); |
387 | ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc); | |
e8324357 S |
388 | list_add_tail(&tbf->list, &bf_head); |
389 | } else { | |
390 | /* | |
391 | * Clear descriptor status words for | |
392 | * software retry | |
393 | */ | |
d43f3015 | 394 | ath9k_hw_cleartxdesc(sc->sc_ah, bf->bf_desc); |
e8324357 S |
395 | } |
396 | ||
397 | /* | |
398 | * Put this buffer to the temporary pending | |
399 | * queue to retain ordering | |
400 | */ | |
401 | list_splice_tail_init(&bf_head, &bf_pending); | |
402 | } | |
403 | ||
404 | bf = bf_next; | |
f078f209 | 405 | } |
f078f209 | 406 | |
e8324357 | 407 | if (tid->state & AGGR_CLEANUP) { |
e8324357 S |
408 | if (tid->baw_head == tid->baw_tail) { |
409 | tid->state &= ~AGGR_ADDBA_COMPLETE; | |
410 | tid->addba_exchangeattempts = 0; | |
e8324357 | 411 | tid->state &= ~AGGR_CLEANUP; |
e63835b0 | 412 | |
e8324357 S |
413 | /* send buffered frames as singles */ |
414 | ath_tx_flush_tid(sc, tid); | |
d43f3015 | 415 | } |
1286ec6d | 416 | rcu_read_unlock(); |
e8324357 S |
417 | return; |
418 | } | |
f078f209 | 419 | |
d43f3015 | 420 | /* prepend un-acked frames to the beginning of the pending frame queue */ |
e8324357 S |
421 | if (!list_empty(&bf_pending)) { |
422 | spin_lock_bh(&txq->axq_lock); | |
423 | list_splice(&bf_pending, &tid->buf_q); | |
424 | ath_tx_queue_tid(txq, tid); | |
425 | spin_unlock_bh(&txq->axq_lock); | |
426 | } | |
102e0572 | 427 | |
1286ec6d S |
428 | rcu_read_unlock(); |
429 | ||
e8324357 S |
430 | if (needreset) |
431 | ath_reset(sc, false); | |
e8324357 | 432 | } |
f078f209 | 433 | |
e8324357 S |
434 | static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf, |
435 | struct ath_atx_tid *tid) | |
f078f209 | 436 | { |
e8324357 | 437 | struct ath_rate_table *rate_table = sc->cur_rate_table; |
528f0c6b S |
438 | struct sk_buff *skb; |
439 | struct ieee80211_tx_info *tx_info; | |
a8efee4f | 440 | struct ieee80211_tx_rate *rates; |
e8324357 | 441 | struct ath_tx_info_priv *tx_info_priv; |
d43f3015 | 442 | u32 max_4ms_framelen, frmlen; |
e8324357 S |
443 | u16 aggr_limit, legacy = 0, maxampdu; |
444 | int i; | |
528f0c6b | 445 | |
a22be22a | 446 | skb = bf->bf_mpdu; |
528f0c6b | 447 | tx_info = IEEE80211_SKB_CB(skb); |
e63835b0 | 448 | rates = tx_info->control.rates; |
d43f3015 | 449 | tx_info_priv = (struct ath_tx_info_priv *)tx_info->rate_driver_data[0]; |
528f0c6b | 450 | |
e8324357 S |
451 | /* |
452 | * Find the lowest frame length among the rate series that will have a | |
453 | * 4ms transmit duration. | |
454 | * TODO - TXOP limit needs to be considered. | |
455 | */ | |
456 | max_4ms_framelen = ATH_AMPDU_LIMIT_MAX; | |
e63835b0 | 457 | |
e8324357 S |
458 | for (i = 0; i < 4; i++) { |
459 | if (rates[i].count) { | |
460 | if (!WLAN_RC_PHY_HT(rate_table->info[rates[i].idx].phy)) { | |
461 | legacy = 1; | |
462 | break; | |
463 | } | |
464 | ||
d43f3015 S |
465 | frmlen = rate_table->info[rates[i].idx].max_4ms_framelen; |
466 | max_4ms_framelen = min(max_4ms_framelen, frmlen); | |
f078f209 LR |
467 | } |
468 | } | |
e63835b0 | 469 | |
f078f209 | 470 | /* |
e8324357 S |
471 | * limit aggregate size by the minimum rate if rate selected is |
472 | * not a probe rate, if rate selected is a probe rate then | |
473 | * avoid aggregation of this packet. | |
f078f209 | 474 | */ |
e8324357 S |
475 | if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy) |
476 | return 0; | |
f078f209 | 477 | |
d43f3015 | 478 | aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_DEFAULT); |
f078f209 | 479 | |
e8324357 S |
480 | /* |
481 | * h/w can accept aggregates upto 16 bit lengths (65535). | |
482 | * The IE, however can hold upto 65536, which shows up here | |
483 | * as zero. Ignore 65536 since we are constrained by hw. | |
f078f209 | 484 | */ |
e8324357 S |
485 | maxampdu = tid->an->maxampdu; |
486 | if (maxampdu) | |
487 | aggr_limit = min(aggr_limit, maxampdu); | |
f078f209 | 488 | |
e8324357 S |
489 | return aggr_limit; |
490 | } | |
f078f209 | 491 | |
e8324357 | 492 | /* |
d43f3015 | 493 | * Returns the number of delimiters to be added to |
e8324357 | 494 | * meet the minimum required mpdudensity. |
d43f3015 | 495 | * caller should make sure that the rate is HT rate . |
e8324357 S |
496 | */ |
497 | static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid, | |
498 | struct ath_buf *bf, u16 frmlen) | |
499 | { | |
500 | struct ath_rate_table *rt = sc->cur_rate_table; | |
501 | struct sk_buff *skb = bf->bf_mpdu; | |
502 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
503 | u32 nsymbits, nsymbols, mpdudensity; | |
504 | u16 minlen; | |
505 | u8 rc, flags, rix; | |
506 | int width, half_gi, ndelim, mindelim; | |
507 | ||
508 | /* Select standard number of delimiters based on frame length alone */ | |
509 | ndelim = ATH_AGGR_GET_NDELIM(frmlen); | |
f078f209 LR |
510 | |
511 | /* | |
e8324357 S |
512 | * If encryption enabled, hardware requires some more padding between |
513 | * subframes. | |
514 | * TODO - this could be improved to be dependent on the rate. | |
515 | * The hardware can keep up at lower rates, but not higher rates | |
f078f209 | 516 | */ |
e8324357 S |
517 | if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) |
518 | ndelim += ATH_AGGR_ENCRYPTDELIM; | |
f078f209 | 519 | |
e8324357 S |
520 | /* |
521 | * Convert desired mpdu density from microeconds to bytes based | |
522 | * on highest rate in rate series (i.e. first rate) to determine | |
523 | * required minimum length for subframe. Take into account | |
524 | * whether high rate is 20 or 40Mhz and half or full GI. | |
525 | */ | |
526 | mpdudensity = tid->an->mpdudensity; | |
f078f209 | 527 | |
e8324357 S |
528 | /* |
529 | * If there is no mpdu density restriction, no further calculation | |
530 | * is needed. | |
531 | */ | |
532 | if (mpdudensity == 0) | |
533 | return ndelim; | |
f078f209 | 534 | |
e8324357 S |
535 | rix = tx_info->control.rates[0].idx; |
536 | flags = tx_info->control.rates[0].flags; | |
537 | rc = rt->info[rix].ratecode; | |
538 | width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0; | |
539 | half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0; | |
f078f209 | 540 | |
e8324357 S |
541 | if (half_gi) |
542 | nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity); | |
543 | else | |
544 | nsymbols = NUM_SYMBOLS_PER_USEC(mpdudensity); | |
f078f209 | 545 | |
e8324357 S |
546 | if (nsymbols == 0) |
547 | nsymbols = 1; | |
f078f209 | 548 | |
e8324357 S |
549 | nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width]; |
550 | minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; | |
f078f209 | 551 | |
e8324357 | 552 | if (frmlen < minlen) { |
e8324357 S |
553 | mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ; |
554 | ndelim = max(mindelim, ndelim); | |
f078f209 LR |
555 | } |
556 | ||
e8324357 | 557 | return ndelim; |
f078f209 LR |
558 | } |
559 | ||
e8324357 | 560 | static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc, |
d43f3015 S |
561 | struct ath_atx_tid *tid, |
562 | struct list_head *bf_q) | |
f078f209 | 563 | { |
e8324357 | 564 | #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) |
d43f3015 S |
565 | struct ath_buf *bf, *bf_first, *bf_prev = NULL; |
566 | int rl = 0, nframes = 0, ndelim, prev_al = 0; | |
e8324357 S |
567 | u16 aggr_limit = 0, al = 0, bpad = 0, |
568 | al_delta, h_baw = tid->baw_size / 2; | |
569 | enum ATH_AGGR_STATUS status = ATH_AGGR_DONE; | |
f078f209 | 570 | |
e8324357 | 571 | bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list); |
f078f209 | 572 | |
e8324357 S |
573 | do { |
574 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); | |
f078f209 | 575 | |
d43f3015 | 576 | /* do not step over block-ack window */ |
e8324357 S |
577 | if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) { |
578 | status = ATH_AGGR_BAW_CLOSED; | |
579 | break; | |
580 | } | |
f078f209 | 581 | |
e8324357 S |
582 | if (!rl) { |
583 | aggr_limit = ath_lookup_rate(sc, bf, tid); | |
584 | rl = 1; | |
585 | } | |
f078f209 | 586 | |
d43f3015 | 587 | /* do not exceed aggregation limit */ |
e8324357 | 588 | al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen; |
f078f209 | 589 | |
d43f3015 S |
590 | if (nframes && |
591 | (aggr_limit < (al + bpad + al_delta + prev_al))) { | |
e8324357 S |
592 | status = ATH_AGGR_LIMITED; |
593 | break; | |
594 | } | |
f078f209 | 595 | |
d43f3015 S |
596 | /* do not exceed subframe limit */ |
597 | if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) { | |
e8324357 S |
598 | status = ATH_AGGR_LIMITED; |
599 | break; | |
600 | } | |
d43f3015 | 601 | nframes++; |
f078f209 | 602 | |
d43f3015 | 603 | /* add padding for previous frame to aggregation length */ |
e8324357 | 604 | al += bpad + al_delta; |
f078f209 | 605 | |
e8324357 S |
606 | /* |
607 | * Get the delimiters needed to meet the MPDU | |
608 | * density for this node. | |
609 | */ | |
610 | ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen); | |
e8324357 | 611 | bpad = PADBYTES(al_delta) + (ndelim << 2); |
f078f209 | 612 | |
e8324357 | 613 | bf->bf_next = NULL; |
d43f3015 | 614 | bf->bf_desc->ds_link = 0; |
f078f209 | 615 | |
d43f3015 | 616 | /* link buffers of this frame to the aggregate */ |
e8324357 | 617 | ath_tx_addto_baw(sc, tid, bf); |
d43f3015 S |
618 | ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim); |
619 | list_move_tail(&bf->list, bf_q); | |
e8324357 S |
620 | if (bf_prev) { |
621 | bf_prev->bf_next = bf; | |
d43f3015 | 622 | bf_prev->bf_desc->ds_link = bf->bf_daddr; |
e8324357 S |
623 | } |
624 | bf_prev = bf; | |
e8324357 | 625 | } while (!list_empty(&tid->buf_q)); |
f078f209 | 626 | |
e8324357 S |
627 | bf_first->bf_al = al; |
628 | bf_first->bf_nframes = nframes; | |
d43f3015 | 629 | |
e8324357 S |
630 | return status; |
631 | #undef PADBYTES | |
632 | } | |
f078f209 | 633 | |
e8324357 S |
634 | static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq, |
635 | struct ath_atx_tid *tid) | |
636 | { | |
d43f3015 | 637 | struct ath_buf *bf; |
e8324357 S |
638 | enum ATH_AGGR_STATUS status; |
639 | struct list_head bf_q; | |
f078f209 | 640 | |
e8324357 S |
641 | do { |
642 | if (list_empty(&tid->buf_q)) | |
643 | return; | |
f078f209 | 644 | |
e8324357 S |
645 | INIT_LIST_HEAD(&bf_q); |
646 | ||
d43f3015 | 647 | status = ath_tx_form_aggr(sc, tid, &bf_q); |
f078f209 | 648 | |
f078f209 | 649 | /* |
d43f3015 S |
650 | * no frames picked up to be aggregated; |
651 | * block-ack window is not open. | |
f078f209 | 652 | */ |
e8324357 S |
653 | if (list_empty(&bf_q)) |
654 | break; | |
f078f209 | 655 | |
e8324357 | 656 | bf = list_first_entry(&bf_q, struct ath_buf, list); |
d43f3015 | 657 | bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list); |
f078f209 | 658 | |
d43f3015 | 659 | /* if only one frame, send as non-aggregate */ |
e8324357 | 660 | if (bf->bf_nframes == 1) { |
e8324357 | 661 | bf->bf_state.bf_type &= ~BUF_AGGR; |
d43f3015 | 662 | ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc); |
e8324357 S |
663 | ath_buf_set_rate(sc, bf); |
664 | ath_tx_txqaddbuf(sc, txq, &bf_q); | |
665 | continue; | |
666 | } | |
f078f209 | 667 | |
d43f3015 | 668 | /* setup first desc of aggregate */ |
e8324357 S |
669 | bf->bf_state.bf_type |= BUF_AGGR; |
670 | ath_buf_set_rate(sc, bf); | |
671 | ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al); | |
f078f209 | 672 | |
d43f3015 S |
673 | /* anchor last desc of aggregate */ |
674 | ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc); | |
f078f209 | 675 | |
e8324357 | 676 | txq->axq_aggr_depth++; |
e8324357 | 677 | ath_tx_txqaddbuf(sc, txq, &bf_q); |
f078f209 | 678 | |
e8324357 S |
679 | } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH && |
680 | status != ATH_AGGR_BAW_CLOSED); | |
681 | } | |
682 | ||
683 | int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, | |
684 | u16 tid, u16 *ssn) | |
685 | { | |
686 | struct ath_atx_tid *txtid; | |
687 | struct ath_node *an; | |
688 | ||
689 | an = (struct ath_node *)sta->drv_priv; | |
690 | ||
691 | if (sc->sc_flags & SC_OP_TXAGGR) { | |
692 | txtid = ATH_AN_2_TID(an, tid); | |
693 | txtid->state |= AGGR_ADDBA_PROGRESS; | |
694 | ath_tx_pause_tid(sc, txtid); | |
d22b0022 | 695 | *ssn = txtid->seq_start; |
f078f209 LR |
696 | } |
697 | ||
e8324357 S |
698 | return 0; |
699 | } | |
f078f209 | 700 | |
e8324357 S |
701 | int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) |
702 | { | |
703 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
704 | struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid); | |
705 | struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum]; | |
706 | struct ath_buf *bf; | |
707 | struct list_head bf_head; | |
708 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 709 | |
e8324357 S |
710 | if (txtid->state & AGGR_CLEANUP) |
711 | return 0; | |
f078f209 | 712 | |
e8324357 S |
713 | if (!(txtid->state & AGGR_ADDBA_COMPLETE)) { |
714 | txtid->addba_exchangeattempts = 0; | |
715 | return 0; | |
716 | } | |
f078f209 | 717 | |
e8324357 S |
718 | ath_tx_pause_tid(sc, txtid); |
719 | ||
720 | /* drop all software retried frames and mark this TID */ | |
721 | spin_lock_bh(&txq->axq_lock); | |
722 | while (!list_empty(&txtid->buf_q)) { | |
723 | bf = list_first_entry(&txtid->buf_q, struct ath_buf, list); | |
724 | if (!bf_isretried(bf)) { | |
725 | /* | |
726 | * NB: it's based on the assumption that | |
727 | * software retried frame will always stay | |
728 | * at the head of software queue. | |
729 | */ | |
730 | break; | |
731 | } | |
d43f3015 | 732 | list_move_tail(&bf->list, &bf_head); |
e8324357 S |
733 | ath_tx_update_baw(sc, txtid, bf->bf_seqno); |
734 | ath_tx_complete_buf(sc, bf, &bf_head, 0, 0); | |
f078f209 | 735 | } |
d43f3015 | 736 | spin_unlock_bh(&txq->axq_lock); |
f078f209 | 737 | |
e8324357 | 738 | if (txtid->baw_head != txtid->baw_tail) { |
e8324357 S |
739 | txtid->state |= AGGR_CLEANUP; |
740 | } else { | |
741 | txtid->state &= ~AGGR_ADDBA_COMPLETE; | |
742 | txtid->addba_exchangeattempts = 0; | |
e8324357 | 743 | ath_tx_flush_tid(sc, txtid); |
f078f209 LR |
744 | } |
745 | ||
e8324357 S |
746 | return 0; |
747 | } | |
f078f209 | 748 | |
e8324357 S |
749 | void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) |
750 | { | |
751 | struct ath_atx_tid *txtid; | |
752 | struct ath_node *an; | |
753 | ||
754 | an = (struct ath_node *)sta->drv_priv; | |
755 | ||
756 | if (sc->sc_flags & SC_OP_TXAGGR) { | |
757 | txtid = ATH_AN_2_TID(an, tid); | |
758 | txtid->baw_size = | |
759 | IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor; | |
760 | txtid->state |= AGGR_ADDBA_COMPLETE; | |
761 | txtid->state &= ~AGGR_ADDBA_PROGRESS; | |
762 | ath_tx_resume_tid(sc, txtid); | |
763 | } | |
f078f209 LR |
764 | } |
765 | ||
e8324357 | 766 | bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno) |
c4288390 | 767 | { |
e8324357 | 768 | struct ath_atx_tid *txtid; |
c4288390 | 769 | |
e8324357 S |
770 | if (!(sc->sc_flags & SC_OP_TXAGGR)) |
771 | return false; | |
c4288390 | 772 | |
e8324357 S |
773 | txtid = ATH_AN_2_TID(an, tidno); |
774 | ||
775 | if (!(txtid->state & AGGR_ADDBA_COMPLETE)) { | |
776 | if (!(txtid->state & AGGR_ADDBA_PROGRESS) && | |
777 | (txtid->addba_exchangeattempts < ADDBA_EXCHANGE_ATTEMPTS)) { | |
778 | txtid->addba_exchangeattempts++; | |
779 | return true; | |
c4288390 S |
780 | } |
781 | } | |
e8324357 S |
782 | |
783 | return false; | |
c4288390 S |
784 | } |
785 | ||
e8324357 S |
786 | /********************/ |
787 | /* Queue Management */ | |
788 | /********************/ | |
f078f209 | 789 | |
e8324357 S |
790 | static void ath_txq_drain_pending_buffers(struct ath_softc *sc, |
791 | struct ath_txq *txq) | |
f078f209 | 792 | { |
e8324357 S |
793 | struct ath_atx_ac *ac, *ac_tmp; |
794 | struct ath_atx_tid *tid, *tid_tmp; | |
f078f209 | 795 | |
e8324357 S |
796 | list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) { |
797 | list_del(&ac->list); | |
798 | ac->sched = false; | |
799 | list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) { | |
800 | list_del(&tid->list); | |
801 | tid->sched = false; | |
802 | ath_tid_drain(sc, txq, tid); | |
803 | } | |
f078f209 LR |
804 | } |
805 | } | |
806 | ||
e8324357 | 807 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) |
f078f209 | 808 | { |
cbe61d8a | 809 | struct ath_hw *ah = sc->sc_ah; |
e8324357 S |
810 | struct ath9k_tx_queue_info qi; |
811 | int qnum; | |
f078f209 | 812 | |
e8324357 S |
813 | memset(&qi, 0, sizeof(qi)); |
814 | qi.tqi_subtype = subtype; | |
815 | qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT; | |
816 | qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT; | |
817 | qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT; | |
818 | qi.tqi_physCompBuf = 0; | |
f078f209 LR |
819 | |
820 | /* | |
e8324357 S |
821 | * Enable interrupts only for EOL and DESC conditions. |
822 | * We mark tx descriptors to receive a DESC interrupt | |
823 | * when a tx queue gets deep; otherwise waiting for the | |
824 | * EOL to reap descriptors. Note that this is done to | |
825 | * reduce interrupt load and this only defers reaping | |
826 | * descriptors, never transmitting frames. Aside from | |
827 | * reducing interrupts this also permits more concurrency. | |
828 | * The only potential downside is if the tx queue backs | |
829 | * up in which case the top half of the kernel may backup | |
830 | * due to a lack of tx descriptors. | |
831 | * | |
832 | * The UAPSD queue is an exception, since we take a desc- | |
833 | * based intr on the EOSP frames. | |
f078f209 | 834 | */ |
e8324357 S |
835 | if (qtype == ATH9K_TX_QUEUE_UAPSD) |
836 | qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; | |
837 | else | |
838 | qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | | |
839 | TXQ_FLAG_TXDESCINT_ENABLE; | |
840 | qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); | |
841 | if (qnum == -1) { | |
f078f209 | 842 | /* |
e8324357 S |
843 | * NB: don't print a message, this happens |
844 | * normally on parts with too few tx queues | |
f078f209 | 845 | */ |
e8324357 | 846 | return NULL; |
f078f209 | 847 | } |
e8324357 S |
848 | if (qnum >= ARRAY_SIZE(sc->tx.txq)) { |
849 | DPRINTF(sc, ATH_DBG_FATAL, | |
850 | "qnum %u out of range, max %u!\n", | |
851 | qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq)); | |
852 | ath9k_hw_releasetxqueue(ah, qnum); | |
853 | return NULL; | |
854 | } | |
855 | if (!ATH_TXQ_SETUP(sc, qnum)) { | |
856 | struct ath_txq *txq = &sc->tx.txq[qnum]; | |
f078f209 | 857 | |
e8324357 S |
858 | txq->axq_qnum = qnum; |
859 | txq->axq_link = NULL; | |
860 | INIT_LIST_HEAD(&txq->axq_q); | |
861 | INIT_LIST_HEAD(&txq->axq_acq); | |
862 | spin_lock_init(&txq->axq_lock); | |
863 | txq->axq_depth = 0; | |
864 | txq->axq_aggr_depth = 0; | |
865 | txq->axq_totalqueued = 0; | |
866 | txq->axq_linkbuf = NULL; | |
867 | sc->tx.txqsetup |= 1<<qnum; | |
868 | } | |
869 | return &sc->tx.txq[qnum]; | |
f078f209 LR |
870 | } |
871 | ||
e8324357 | 872 | static int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype) |
f078f209 | 873 | { |
e8324357 | 874 | int qnum; |
f078f209 | 875 | |
e8324357 S |
876 | switch (qtype) { |
877 | case ATH9K_TX_QUEUE_DATA: | |
878 | if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { | |
879 | DPRINTF(sc, ATH_DBG_FATAL, | |
880 | "HAL AC %u out of range, max %zu!\n", | |
881 | haltype, ARRAY_SIZE(sc->tx.hwq_map)); | |
882 | return -1; | |
883 | } | |
884 | qnum = sc->tx.hwq_map[haltype]; | |
885 | break; | |
886 | case ATH9K_TX_QUEUE_BEACON: | |
887 | qnum = sc->beacon.beaconq; | |
888 | break; | |
889 | case ATH9K_TX_QUEUE_CAB: | |
890 | qnum = sc->beacon.cabq->axq_qnum; | |
891 | break; | |
892 | default: | |
893 | qnum = -1; | |
894 | } | |
895 | return qnum; | |
896 | } | |
f078f209 | 897 | |
e8324357 S |
898 | struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb) |
899 | { | |
900 | struct ath_txq *txq = NULL; | |
901 | int qnum; | |
f078f209 | 902 | |
e8324357 S |
903 | qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc); |
904 | txq = &sc->tx.txq[qnum]; | |
f078f209 | 905 | |
e8324357 S |
906 | spin_lock_bh(&txq->axq_lock); |
907 | ||
908 | if (txq->axq_depth >= (ATH_TXBUF - 20)) { | |
c117fa0b | 909 | DPRINTF(sc, ATH_DBG_XMIT, |
e8324357 S |
910 | "TX queue: %d is full, depth: %d\n", |
911 | qnum, txq->axq_depth); | |
912 | ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb)); | |
913 | txq->stopped = 1; | |
914 | spin_unlock_bh(&txq->axq_lock); | |
915 | return NULL; | |
f078f209 LR |
916 | } |
917 | ||
e8324357 S |
918 | spin_unlock_bh(&txq->axq_lock); |
919 | ||
920 | return txq; | |
921 | } | |
922 | ||
923 | int ath_txq_update(struct ath_softc *sc, int qnum, | |
924 | struct ath9k_tx_queue_info *qinfo) | |
925 | { | |
cbe61d8a | 926 | struct ath_hw *ah = sc->sc_ah; |
e8324357 S |
927 | int error = 0; |
928 | struct ath9k_tx_queue_info qi; | |
929 | ||
930 | if (qnum == sc->beacon.beaconq) { | |
931 | /* | |
932 | * XXX: for beacon queue, we just save the parameter. | |
933 | * It will be picked up by ath_beaconq_config when | |
934 | * it's necessary. | |
935 | */ | |
936 | sc->beacon.beacon_qi = *qinfo; | |
f078f209 | 937 | return 0; |
e8324357 | 938 | } |
f078f209 | 939 | |
e8324357 S |
940 | ASSERT(sc->tx.txq[qnum].axq_qnum == qnum); |
941 | ||
942 | ath9k_hw_get_txq_props(ah, qnum, &qi); | |
943 | qi.tqi_aifs = qinfo->tqi_aifs; | |
944 | qi.tqi_cwmin = qinfo->tqi_cwmin; | |
945 | qi.tqi_cwmax = qinfo->tqi_cwmax; | |
946 | qi.tqi_burstTime = qinfo->tqi_burstTime; | |
947 | qi.tqi_readyTime = qinfo->tqi_readyTime; | |
948 | ||
949 | if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { | |
950 | DPRINTF(sc, ATH_DBG_FATAL, | |
951 | "Unable to update hardware queue %u!\n", qnum); | |
952 | error = -EIO; | |
953 | } else { | |
954 | ath9k_hw_resettxqueue(ah, qnum); | |
955 | } | |
956 | ||
957 | return error; | |
958 | } | |
959 | ||
960 | int ath_cabq_update(struct ath_softc *sc) | |
961 | { | |
962 | struct ath9k_tx_queue_info qi; | |
963 | int qnum = sc->beacon.cabq->axq_qnum; | |
f078f209 | 964 | |
e8324357 | 965 | ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi); |
f078f209 | 966 | /* |
e8324357 | 967 | * Ensure the readytime % is within the bounds. |
f078f209 | 968 | */ |
17d7904d S |
969 | if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND) |
970 | sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND; | |
971 | else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND) | |
972 | sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND; | |
f078f209 | 973 | |
fdbf7335 S |
974 | qi.tqi_readyTime = (sc->hw->conf.beacon_int * |
975 | sc->config.cabqReadytime) / 100; | |
e8324357 S |
976 | ath_txq_update(sc, qnum, &qi); |
977 | ||
978 | return 0; | |
f078f209 LR |
979 | } |
980 | ||
043a0405 S |
981 | /* |
982 | * Drain a given TX queue (could be Beacon or Data) | |
983 | * | |
984 | * This assumes output has been stopped and | |
985 | * we do not need to block ath_tx_tasklet. | |
986 | */ | |
987 | void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx) | |
f078f209 | 988 | { |
e8324357 S |
989 | struct ath_buf *bf, *lastbf; |
990 | struct list_head bf_head; | |
f078f209 | 991 | |
e8324357 | 992 | INIT_LIST_HEAD(&bf_head); |
f078f209 | 993 | |
e8324357 S |
994 | for (;;) { |
995 | spin_lock_bh(&txq->axq_lock); | |
f078f209 | 996 | |
e8324357 S |
997 | if (list_empty(&txq->axq_q)) { |
998 | txq->axq_link = NULL; | |
999 | txq->axq_linkbuf = NULL; | |
1000 | spin_unlock_bh(&txq->axq_lock); | |
1001 | break; | |
1002 | } | |
f078f209 | 1003 | |
e8324357 | 1004 | bf = list_first_entry(&txq->axq_q, struct ath_buf, list); |
f078f209 | 1005 | |
a119cc49 | 1006 | if (bf->bf_stale) { |
e8324357 S |
1007 | list_del(&bf->list); |
1008 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 | 1009 | |
e8324357 S |
1010 | spin_lock_bh(&sc->tx.txbuflock); |
1011 | list_add_tail(&bf->list, &sc->tx.txbuf); | |
1012 | spin_unlock_bh(&sc->tx.txbuflock); | |
1013 | continue; | |
1014 | } | |
f078f209 | 1015 | |
e8324357 S |
1016 | lastbf = bf->bf_lastbf; |
1017 | if (!retry_tx) | |
1018 | lastbf->bf_desc->ds_txstat.ts_flags = | |
1019 | ATH9K_TX_SW_ABORTED; | |
f078f209 | 1020 | |
e8324357 S |
1021 | /* remove ath_buf's of the same mpdu from txq */ |
1022 | list_cut_position(&bf_head, &txq->axq_q, &lastbf->list); | |
1023 | txq->axq_depth--; | |
f078f209 | 1024 | |
e8324357 S |
1025 | spin_unlock_bh(&txq->axq_lock); |
1026 | ||
1027 | if (bf_isampdu(bf)) | |
d43f3015 | 1028 | ath_tx_complete_aggr(sc, txq, bf, &bf_head, 0); |
e8324357 S |
1029 | else |
1030 | ath_tx_complete_buf(sc, bf, &bf_head, 0, 0); | |
f078f209 LR |
1031 | } |
1032 | ||
e8324357 S |
1033 | /* flush any pending frames if aggregation is enabled */ |
1034 | if (sc->sc_flags & SC_OP_TXAGGR) { | |
1035 | if (!retry_tx) { | |
1036 | spin_lock_bh(&txq->axq_lock); | |
1037 | ath_txq_drain_pending_buffers(sc, txq); | |
1038 | spin_unlock_bh(&txq->axq_lock); | |
1039 | } | |
1040 | } | |
f078f209 LR |
1041 | } |
1042 | ||
043a0405 | 1043 | void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) |
f078f209 | 1044 | { |
cbe61d8a | 1045 | struct ath_hw *ah = sc->sc_ah; |
043a0405 S |
1046 | struct ath_txq *txq; |
1047 | int i, npend = 0; | |
1048 | ||
1049 | if (sc->sc_flags & SC_OP_INVALID) | |
1050 | return; | |
1051 | ||
1052 | /* Stop beacon queue */ | |
1053 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
1054 | ||
1055 | /* Stop data queues */ | |
1056 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1057 | if (ATH_TXQ_SETUP(sc, i)) { | |
1058 | txq = &sc->tx.txq[i]; | |
1059 | ath9k_hw_stoptxdma(ah, txq->axq_qnum); | |
1060 | npend += ath9k_hw_numtxpending(ah, txq->axq_qnum); | |
1061 | } | |
1062 | } | |
1063 | ||
1064 | if (npend) { | |
1065 | int r; | |
1066 | ||
1067 | DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n"); | |
1068 | ||
1069 | spin_lock_bh(&sc->sc_resetlock); | |
2660b81a | 1070 | r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true); |
043a0405 S |
1071 | if (r) |
1072 | DPRINTF(sc, ATH_DBG_FATAL, | |
1073 | "Unable to reset hardware; reset status %u\n", | |
1074 | r); | |
1075 | spin_unlock_bh(&sc->sc_resetlock); | |
1076 | } | |
1077 | ||
1078 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1079 | if (ATH_TXQ_SETUP(sc, i)) | |
1080 | ath_draintxq(sc, &sc->tx.txq[i], retry_tx); | |
1081 | } | |
e8324357 | 1082 | } |
f078f209 | 1083 | |
043a0405 | 1084 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) |
e8324357 | 1085 | { |
043a0405 S |
1086 | ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum); |
1087 | sc->tx.txqsetup &= ~(1<<txq->axq_qnum); | |
e8324357 | 1088 | } |
f078f209 | 1089 | |
e8324357 S |
1090 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) |
1091 | { | |
1092 | struct ath_atx_ac *ac; | |
1093 | struct ath_atx_tid *tid; | |
f078f209 | 1094 | |
e8324357 S |
1095 | if (list_empty(&txq->axq_acq)) |
1096 | return; | |
f078f209 | 1097 | |
e8324357 S |
1098 | ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list); |
1099 | list_del(&ac->list); | |
1100 | ac->sched = false; | |
f078f209 | 1101 | |
e8324357 S |
1102 | do { |
1103 | if (list_empty(&ac->tid_q)) | |
1104 | return; | |
f078f209 | 1105 | |
e8324357 S |
1106 | tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list); |
1107 | list_del(&tid->list); | |
1108 | tid->sched = false; | |
f078f209 | 1109 | |
e8324357 S |
1110 | if (tid->paused) |
1111 | continue; | |
f078f209 | 1112 | |
e8324357 S |
1113 | if ((txq->axq_depth % 2) == 0) |
1114 | ath_tx_sched_aggr(sc, txq, tid); | |
f078f209 LR |
1115 | |
1116 | /* | |
e8324357 S |
1117 | * add tid to round-robin queue if more frames |
1118 | * are pending for the tid | |
f078f209 | 1119 | */ |
e8324357 S |
1120 | if (!list_empty(&tid->buf_q)) |
1121 | ath_tx_queue_tid(txq, tid); | |
f078f209 | 1122 | |
e8324357 S |
1123 | break; |
1124 | } while (!list_empty(&ac->tid_q)); | |
f078f209 | 1125 | |
e8324357 S |
1126 | if (!list_empty(&ac->tid_q)) { |
1127 | if (!ac->sched) { | |
1128 | ac->sched = true; | |
1129 | list_add_tail(&ac->list, &txq->axq_acq); | |
f078f209 | 1130 | } |
e8324357 S |
1131 | } |
1132 | } | |
f078f209 | 1133 | |
e8324357 S |
1134 | int ath_tx_setup(struct ath_softc *sc, int haltype) |
1135 | { | |
1136 | struct ath_txq *txq; | |
f078f209 | 1137 | |
e8324357 S |
1138 | if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { |
1139 | DPRINTF(sc, ATH_DBG_FATAL, | |
1140 | "HAL AC %u out of range, max %zu!\n", | |
1141 | haltype, ARRAY_SIZE(sc->tx.hwq_map)); | |
1142 | return 0; | |
1143 | } | |
1144 | txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype); | |
1145 | if (txq != NULL) { | |
1146 | sc->tx.hwq_map[haltype] = txq->axq_qnum; | |
1147 | return 1; | |
1148 | } else | |
1149 | return 0; | |
f078f209 LR |
1150 | } |
1151 | ||
e8324357 S |
1152 | /***********/ |
1153 | /* TX, DMA */ | |
1154 | /***********/ | |
1155 | ||
f078f209 | 1156 | /* |
e8324357 S |
1157 | * Insert a chain of ath_buf (descriptors) on a txq and |
1158 | * assume the descriptors are already chained together by caller. | |
f078f209 | 1159 | */ |
e8324357 S |
1160 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, |
1161 | struct list_head *head) | |
f078f209 | 1162 | { |
cbe61d8a | 1163 | struct ath_hw *ah = sc->sc_ah; |
e8324357 | 1164 | struct ath_buf *bf; |
f078f209 | 1165 | |
e8324357 S |
1166 | /* |
1167 | * Insert the frame on the outbound list and | |
1168 | * pass it on to the hardware. | |
1169 | */ | |
f078f209 | 1170 | |
e8324357 S |
1171 | if (list_empty(head)) |
1172 | return; | |
f078f209 | 1173 | |
e8324357 | 1174 | bf = list_first_entry(head, struct ath_buf, list); |
f078f209 | 1175 | |
e8324357 S |
1176 | list_splice_tail_init(head, &txq->axq_q); |
1177 | txq->axq_depth++; | |
1178 | txq->axq_totalqueued++; | |
1179 | txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list); | |
f078f209 | 1180 | |
e8324357 S |
1181 | DPRINTF(sc, ATH_DBG_QUEUE, |
1182 | "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth); | |
f078f209 | 1183 | |
e8324357 S |
1184 | if (txq->axq_link == NULL) { |
1185 | ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); | |
1186 | DPRINTF(sc, ATH_DBG_XMIT, | |
1187 | "TXDP[%u] = %llx (%p)\n", | |
1188 | txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); | |
1189 | } else { | |
1190 | *txq->axq_link = bf->bf_daddr; | |
1191 | DPRINTF(sc, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n", | |
1192 | txq->axq_qnum, txq->axq_link, | |
1193 | ito64(bf->bf_daddr), bf->bf_desc); | |
1194 | } | |
1195 | txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link); | |
1196 | ath9k_hw_txstart(ah, txq->axq_qnum); | |
1197 | } | |
f078f209 | 1198 | |
e8324357 S |
1199 | static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc) |
1200 | { | |
1201 | struct ath_buf *bf = NULL; | |
f078f209 | 1202 | |
e8324357 | 1203 | spin_lock_bh(&sc->tx.txbuflock); |
f078f209 | 1204 | |
e8324357 S |
1205 | if (unlikely(list_empty(&sc->tx.txbuf))) { |
1206 | spin_unlock_bh(&sc->tx.txbuflock); | |
1207 | return NULL; | |
1208 | } | |
f078f209 | 1209 | |
e8324357 S |
1210 | bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); |
1211 | list_del(&bf->list); | |
f078f209 | 1212 | |
e8324357 | 1213 | spin_unlock_bh(&sc->tx.txbuflock); |
f078f209 | 1214 | |
e8324357 | 1215 | return bf; |
f078f209 LR |
1216 | } |
1217 | ||
e8324357 S |
1218 | static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid, |
1219 | struct list_head *bf_head, | |
1220 | struct ath_tx_control *txctl) | |
f078f209 LR |
1221 | { |
1222 | struct ath_buf *bf; | |
f078f209 | 1223 | |
e8324357 S |
1224 | bf = list_first_entry(bf_head, struct ath_buf, list); |
1225 | bf->bf_state.bf_type |= BUF_AMPDU; | |
f078f209 | 1226 | |
e8324357 S |
1227 | /* |
1228 | * Do not queue to h/w when any of the following conditions is true: | |
1229 | * - there are pending frames in software queue | |
1230 | * - the TID is currently paused for ADDBA/BAR request | |
1231 | * - seqno is not within block-ack window | |
1232 | * - h/w queue depth exceeds low water mark | |
1233 | */ | |
1234 | if (!list_empty(&tid->buf_q) || tid->paused || | |
1235 | !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) || | |
1236 | txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) { | |
f078f209 | 1237 | /* |
e8324357 S |
1238 | * Add this frame to software queue for scheduling later |
1239 | * for aggregation. | |
f078f209 | 1240 | */ |
d43f3015 | 1241 | list_move_tail(&bf->list, &tid->buf_q); |
e8324357 S |
1242 | ath_tx_queue_tid(txctl->txq, tid); |
1243 | return; | |
1244 | } | |
1245 | ||
1246 | /* Add sub-frame to BAW */ | |
1247 | ath_tx_addto_baw(sc, tid, bf); | |
1248 | ||
1249 | /* Queue to h/w without aggregation */ | |
1250 | bf->bf_nframes = 1; | |
d43f3015 | 1251 | bf->bf_lastbf = bf; |
e8324357 S |
1252 | ath_buf_set_rate(sc, bf); |
1253 | ath_tx_txqaddbuf(sc, txctl->txq, bf_head); | |
e8324357 S |
1254 | } |
1255 | ||
c37452b0 S |
1256 | static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq, |
1257 | struct ath_atx_tid *tid, | |
1258 | struct list_head *bf_head) | |
e8324357 S |
1259 | { |
1260 | struct ath_buf *bf; | |
1261 | ||
e8324357 S |
1262 | bf = list_first_entry(bf_head, struct ath_buf, list); |
1263 | bf->bf_state.bf_type &= ~BUF_AMPDU; | |
1264 | ||
1265 | /* update starting sequence number for subsequent ADDBA request */ | |
1266 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); | |
1267 | ||
1268 | bf->bf_nframes = 1; | |
d43f3015 | 1269 | bf->bf_lastbf = bf; |
e8324357 S |
1270 | ath_buf_set_rate(sc, bf); |
1271 | ath_tx_txqaddbuf(sc, txq, bf_head); | |
1272 | } | |
1273 | ||
c37452b0 S |
1274 | static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, |
1275 | struct list_head *bf_head) | |
1276 | { | |
1277 | struct ath_buf *bf; | |
1278 | ||
1279 | bf = list_first_entry(bf_head, struct ath_buf, list); | |
1280 | ||
1281 | bf->bf_lastbf = bf; | |
1282 | bf->bf_nframes = 1; | |
1283 | ath_buf_set_rate(sc, bf); | |
1284 | ath_tx_txqaddbuf(sc, txq, bf_head); | |
1285 | } | |
1286 | ||
e8324357 S |
1287 | static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb) |
1288 | { | |
1289 | struct ieee80211_hdr *hdr; | |
1290 | enum ath9k_pkt_type htype; | |
1291 | __le16 fc; | |
1292 | ||
1293 | hdr = (struct ieee80211_hdr *)skb->data; | |
1294 | fc = hdr->frame_control; | |
1295 | ||
1296 | if (ieee80211_is_beacon(fc)) | |
1297 | htype = ATH9K_PKT_TYPE_BEACON; | |
1298 | else if (ieee80211_is_probe_resp(fc)) | |
1299 | htype = ATH9K_PKT_TYPE_PROBE_RESP; | |
1300 | else if (ieee80211_is_atim(fc)) | |
1301 | htype = ATH9K_PKT_TYPE_ATIM; | |
1302 | else if (ieee80211_is_pspoll(fc)) | |
1303 | htype = ATH9K_PKT_TYPE_PSPOLL; | |
1304 | else | |
1305 | htype = ATH9K_PKT_TYPE_NORMAL; | |
1306 | ||
1307 | return htype; | |
1308 | } | |
1309 | ||
1310 | static bool is_pae(struct sk_buff *skb) | |
1311 | { | |
1312 | struct ieee80211_hdr *hdr; | |
1313 | __le16 fc; | |
1314 | ||
1315 | hdr = (struct ieee80211_hdr *)skb->data; | |
1316 | fc = hdr->frame_control; | |
1317 | ||
1318 | if (ieee80211_is_data(fc)) { | |
1319 | if (ieee80211_is_nullfunc(fc) || | |
1320 | /* Port Access Entity (IEEE 802.1X) */ | |
1321 | (skb->protocol == cpu_to_be16(ETH_P_PAE))) { | |
1322 | return true; | |
1323 | } | |
1324 | } | |
1325 | ||
1326 | return false; | |
1327 | } | |
1328 | ||
1329 | static int get_hw_crypto_keytype(struct sk_buff *skb) | |
1330 | { | |
1331 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1332 | ||
1333 | if (tx_info->control.hw_key) { | |
1334 | if (tx_info->control.hw_key->alg == ALG_WEP) | |
1335 | return ATH9K_KEY_TYPE_WEP; | |
1336 | else if (tx_info->control.hw_key->alg == ALG_TKIP) | |
1337 | return ATH9K_KEY_TYPE_TKIP; | |
1338 | else if (tx_info->control.hw_key->alg == ALG_CCMP) | |
1339 | return ATH9K_KEY_TYPE_AES; | |
1340 | } | |
1341 | ||
1342 | return ATH9K_KEY_TYPE_CLEAR; | |
1343 | } | |
1344 | ||
1345 | static void assign_aggr_tid_seqno(struct sk_buff *skb, | |
1346 | struct ath_buf *bf) | |
1347 | { | |
1348 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1349 | struct ieee80211_hdr *hdr; | |
1350 | struct ath_node *an; | |
1351 | struct ath_atx_tid *tid; | |
1352 | __le16 fc; | |
1353 | u8 *qc; | |
1354 | ||
1355 | if (!tx_info->control.sta) | |
1356 | return; | |
1357 | ||
1358 | an = (struct ath_node *)tx_info->control.sta->drv_priv; | |
1359 | hdr = (struct ieee80211_hdr *)skb->data; | |
1360 | fc = hdr->frame_control; | |
1361 | ||
1362 | if (ieee80211_is_data_qos(fc)) { | |
1363 | qc = ieee80211_get_qos_ctl(hdr); | |
1364 | bf->bf_tidno = qc[0] & 0xf; | |
1365 | } | |
1366 | ||
1367 | /* | |
1368 | * For HT capable stations, we save tidno for later use. | |
1369 | * We also override seqno set by upper layer with the one | |
1370 | * in tx aggregation state. | |
1371 | * | |
1372 | * If fragmentation is on, the sequence number is | |
1373 | * not overridden, since it has been | |
1374 | * incremented by the fragmentation routine. | |
1375 | * | |
1376 | * FIXME: check if the fragmentation threshold exceeds | |
1377 | * IEEE80211 max. | |
1378 | */ | |
1379 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
1380 | hdr->seq_ctrl = cpu_to_le16(tid->seq_next << | |
1381 | IEEE80211_SEQ_SEQ_SHIFT); | |
1382 | bf->bf_seqno = tid->seq_next; | |
1383 | INCR(tid->seq_next, IEEE80211_SEQ_MAX); | |
1384 | } | |
1385 | ||
1386 | static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb, | |
1387 | struct ath_txq *txq) | |
1388 | { | |
1389 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1390 | int flags = 0; | |
1391 | ||
1392 | flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */ | |
1393 | flags |= ATH9K_TXDESC_INTREQ; | |
1394 | ||
1395 | if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) | |
1396 | flags |= ATH9K_TXDESC_NOACK; | |
e8324357 S |
1397 | |
1398 | return flags; | |
1399 | } | |
1400 | ||
1401 | /* | |
1402 | * rix - rate index | |
1403 | * pktlen - total bytes (delims + data + fcs + pads + pad delims) | |
1404 | * width - 0 for 20 MHz, 1 for 40 MHz | |
1405 | * half_gi - to use 4us v/s 3.6 us for symbol time | |
1406 | */ | |
1407 | static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf, | |
1408 | int width, int half_gi, bool shortPreamble) | |
1409 | { | |
1410 | struct ath_rate_table *rate_table = sc->cur_rate_table; | |
1411 | u32 nbits, nsymbits, duration, nsymbols; | |
1412 | u8 rc; | |
1413 | int streams, pktlen; | |
1414 | ||
1415 | pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen; | |
1416 | rc = rate_table->info[rix].ratecode; | |
1417 | ||
1418 | /* for legacy rates, use old function to compute packet duration */ | |
1419 | if (!IS_HT_RATE(rc)) | |
1420 | return ath9k_hw_computetxtime(sc->sc_ah, rate_table, pktlen, | |
1421 | rix, shortPreamble); | |
1422 | ||
1423 | /* find number of symbols: PLCP + data */ | |
1424 | nbits = (pktlen << 3) + OFDM_PLCP_BITS; | |
1425 | nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width]; | |
1426 | nsymbols = (nbits + nsymbits - 1) / nsymbits; | |
1427 | ||
1428 | if (!half_gi) | |
1429 | duration = SYMBOL_TIME(nsymbols); | |
1430 | else | |
1431 | duration = SYMBOL_TIME_HALFGI(nsymbols); | |
1432 | ||
1433 | /* addup duration for legacy/ht training and signal fields */ | |
1434 | streams = HT_RC_2_STREAMS(rc); | |
1435 | duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); | |
1436 | ||
1437 | return duration; | |
1438 | } | |
1439 | ||
1440 | static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf) | |
1441 | { | |
c89424df | 1442 | struct ath_rate_table *rt = sc->cur_rate_table; |
e8324357 S |
1443 | struct ath9k_11n_rate_series series[4]; |
1444 | struct sk_buff *skb; | |
1445 | struct ieee80211_tx_info *tx_info; | |
1446 | struct ieee80211_tx_rate *rates; | |
254ad0ff | 1447 | struct ieee80211_hdr *hdr; |
c89424df S |
1448 | int i, flags = 0; |
1449 | u8 rix = 0, ctsrate = 0; | |
254ad0ff | 1450 | bool is_pspoll; |
e8324357 S |
1451 | |
1452 | memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4); | |
1453 | ||
a22be22a | 1454 | skb = bf->bf_mpdu; |
e8324357 S |
1455 | tx_info = IEEE80211_SKB_CB(skb); |
1456 | rates = tx_info->control.rates; | |
254ad0ff S |
1457 | hdr = (struct ieee80211_hdr *)skb->data; |
1458 | is_pspoll = ieee80211_is_pspoll(hdr->frame_control); | |
e8324357 | 1459 | |
e8324357 | 1460 | /* |
c89424df S |
1461 | * We check if Short Preamble is needed for the CTS rate by |
1462 | * checking the BSS's global flag. | |
1463 | * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used. | |
e8324357 | 1464 | */ |
c89424df S |
1465 | if (sc->sc_flags & SC_OP_PREAMBLE_SHORT) |
1466 | ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode | | |
1467 | rt->info[tx_info->control.rts_cts_rate_idx].short_preamble; | |
1468 | else | |
1469 | ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode; | |
e8324357 | 1470 | |
c89424df S |
1471 | /* |
1472 | * ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. | |
1473 | * Check the first rate in the series to decide whether RTS/CTS | |
1474 | * or CTS-to-self has to be used. | |
e8324357 | 1475 | */ |
c89424df S |
1476 | if (rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) |
1477 | flags = ATH9K_TXDESC_CTSENA; | |
1478 | else if (rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) | |
1479 | flags = ATH9K_TXDESC_RTSENA; | |
e8324357 | 1480 | |
c89424df | 1481 | /* FIXME: Handle aggregation protection */ |
17d7904d | 1482 | if (sc->config.ath_aggr_prot && |
e8324357 S |
1483 | (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) { |
1484 | flags = ATH9K_TXDESC_RTSENA; | |
e8324357 S |
1485 | } |
1486 | ||
1487 | /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ | |
2660b81a | 1488 | if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit)) |
e8324357 S |
1489 | flags &= ~(ATH9K_TXDESC_RTSENA); |
1490 | ||
e8324357 S |
1491 | for (i = 0; i < 4; i++) { |
1492 | if (!rates[i].count || (rates[i].idx < 0)) | |
1493 | continue; | |
1494 | ||
1495 | rix = rates[i].idx; | |
e8324357 | 1496 | series[i].Tries = rates[i].count; |
17d7904d | 1497 | series[i].ChSel = sc->tx_chainmask; |
e8324357 | 1498 | |
c89424df S |
1499 | if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) |
1500 | series[i].Rate = rt->info[rix].ratecode | | |
1501 | rt->info[rix].short_preamble; | |
1502 | else | |
1503 | series[i].Rate = rt->info[rix].ratecode; | |
1504 | ||
1505 | if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) | |
1506 | series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; | |
1507 | if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) | |
1508 | series[i].RateFlags |= ATH9K_RATESERIES_2040; | |
1509 | if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) | |
1510 | series[i].RateFlags |= ATH9K_RATESERIES_HALFGI; | |
e8324357 S |
1511 | |
1512 | series[i].PktDuration = ath_pkt_duration(sc, rix, bf, | |
1513 | (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) != 0, | |
1514 | (rates[i].flags & IEEE80211_TX_RC_SHORT_GI), | |
c89424df | 1515 | (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)); |
f078f209 LR |
1516 | } |
1517 | ||
e8324357 | 1518 | /* set dur_update_en for l-sig computation except for PS-Poll frames */ |
c89424df S |
1519 | ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc, |
1520 | bf->bf_lastbf->bf_desc, | |
254ad0ff | 1521 | !is_pspoll, ctsrate, |
c89424df | 1522 | 0, series, 4, flags); |
f078f209 | 1523 | |
17d7904d | 1524 | if (sc->config.ath_aggr_prot && flags) |
c89424df | 1525 | ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192); |
f078f209 LR |
1526 | } |
1527 | ||
c52f33d0 | 1528 | static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf, |
8f93b8b3 | 1529 | struct sk_buff *skb, |
528f0c6b | 1530 | struct ath_tx_control *txctl) |
f078f209 | 1531 | { |
c52f33d0 JM |
1532 | struct ath_wiphy *aphy = hw->priv; |
1533 | struct ath_softc *sc = aphy->sc; | |
528f0c6b S |
1534 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
1535 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
f078f209 | 1536 | struct ath_tx_info_priv *tx_info_priv; |
528f0c6b S |
1537 | int hdrlen; |
1538 | __le16 fc; | |
e022edbd | 1539 | |
c112d0c5 LR |
1540 | tx_info_priv = kzalloc(sizeof(*tx_info_priv), GFP_ATOMIC); |
1541 | if (unlikely(!tx_info_priv)) | |
1542 | return -ENOMEM; | |
a8efee4f | 1543 | tx_info->rate_driver_data[0] = tx_info_priv; |
c52f33d0 | 1544 | tx_info_priv->aphy = aphy; |
f0ed85c6 | 1545 | tx_info_priv->frame_type = txctl->frame_type; |
528f0c6b S |
1546 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); |
1547 | fc = hdr->frame_control; | |
f078f209 | 1548 | |
528f0c6b | 1549 | ATH_TXBUF_RESET(bf); |
f078f209 | 1550 | |
528f0c6b | 1551 | bf->bf_frmlen = skb->len + FCS_LEN - (hdrlen & 3); |
cd3d39a6 | 1552 | |
c37452b0 | 1553 | if (conf_is_ht(&sc->hw->conf) && !is_pae(skb)) |
c656bbb5 | 1554 | bf->bf_state.bf_type |= BUF_HT; |
528f0c6b S |
1555 | |
1556 | bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq); | |
1557 | ||
528f0c6b | 1558 | bf->bf_keytype = get_hw_crypto_keytype(skb); |
528f0c6b S |
1559 | if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) { |
1560 | bf->bf_frmlen += tx_info->control.hw_key->icv_len; | |
1561 | bf->bf_keyix = tx_info->control.hw_key->hw_key_idx; | |
1562 | } else { | |
1563 | bf->bf_keyix = ATH9K_TXKEYIX_INVALID; | |
1564 | } | |
1565 | ||
d3a1db1c | 1566 | if (ieee80211_is_data_qos(fc) && (sc->sc_flags & SC_OP_TXAGGR)) |
528f0c6b S |
1567 | assign_aggr_tid_seqno(skb, bf); |
1568 | ||
f078f209 | 1569 | bf->bf_mpdu = skb; |
f8316df1 | 1570 | |
7da3c55c GJ |
1571 | bf->bf_dmacontext = dma_map_single(sc->dev, skb->data, |
1572 | skb->len, DMA_TO_DEVICE); | |
1573 | if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) { | |
f8316df1 | 1574 | bf->bf_mpdu = NULL; |
675902ef S |
1575 | kfree(tx_info_priv); |
1576 | tx_info->rate_driver_data[0] = NULL; | |
1577 | DPRINTF(sc, ATH_DBG_FATAL, "dma_mapping_error() on TX\n"); | |
f8316df1 LR |
1578 | return -ENOMEM; |
1579 | } | |
1580 | ||
528f0c6b | 1581 | bf->bf_buf_addr = bf->bf_dmacontext; |
f8316df1 | 1582 | return 0; |
528f0c6b S |
1583 | } |
1584 | ||
1585 | /* FIXME: tx power */ | |
1586 | static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf, | |
528f0c6b S |
1587 | struct ath_tx_control *txctl) |
1588 | { | |
a22be22a | 1589 | struct sk_buff *skb = bf->bf_mpdu; |
528f0c6b | 1590 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
c37452b0 | 1591 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
528f0c6b S |
1592 | struct ath_node *an = NULL; |
1593 | struct list_head bf_head; | |
1594 | struct ath_desc *ds; | |
1595 | struct ath_atx_tid *tid; | |
cbe61d8a | 1596 | struct ath_hw *ah = sc->sc_ah; |
528f0c6b | 1597 | int frm_type; |
c37452b0 | 1598 | __le16 fc; |
528f0c6b | 1599 | |
528f0c6b | 1600 | frm_type = get_hw_packet_type(skb); |
c37452b0 | 1601 | fc = hdr->frame_control; |
528f0c6b S |
1602 | |
1603 | INIT_LIST_HEAD(&bf_head); | |
1604 | list_add_tail(&bf->list, &bf_head); | |
f078f209 | 1605 | |
f078f209 LR |
1606 | ds = bf->bf_desc; |
1607 | ds->ds_link = 0; | |
1608 | ds->ds_data = bf->bf_buf_addr; | |
1609 | ||
528f0c6b S |
1610 | ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER, |
1611 | bf->bf_keyix, bf->bf_keytype, bf->bf_flags); | |
1612 | ||
1613 | ath9k_hw_filltxdesc(ah, ds, | |
8f93b8b3 S |
1614 | skb->len, /* segment length */ |
1615 | true, /* first segment */ | |
1616 | true, /* last segment */ | |
1617 | ds); /* first descriptor */ | |
f078f209 | 1618 | |
528f0c6b | 1619 | spin_lock_bh(&txctl->txq->axq_lock); |
f078f209 | 1620 | |
f1617967 JL |
1621 | if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) && |
1622 | tx_info->control.sta) { | |
1623 | an = (struct ath_node *)tx_info->control.sta->drv_priv; | |
1624 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
1625 | ||
c37452b0 S |
1626 | if (!ieee80211_is_data_qos(fc)) { |
1627 | ath_tx_send_normal(sc, txctl->txq, &bf_head); | |
1628 | goto tx_done; | |
1629 | } | |
1630 | ||
528f0c6b | 1631 | if (ath_aggr_query(sc, an, bf->bf_tidno)) { |
f078f209 LR |
1632 | /* |
1633 | * Try aggregation if it's a unicast data frame | |
1634 | * and the destination is HT capable. | |
1635 | */ | |
528f0c6b | 1636 | ath_tx_send_ampdu(sc, tid, &bf_head, txctl); |
f078f209 LR |
1637 | } else { |
1638 | /* | |
528f0c6b S |
1639 | * Send this frame as regular when ADDBA |
1640 | * exchange is neither complete nor pending. | |
f078f209 | 1641 | */ |
c37452b0 S |
1642 | ath_tx_send_ht_normal(sc, txctl->txq, |
1643 | tid, &bf_head); | |
f078f209 LR |
1644 | } |
1645 | } else { | |
c37452b0 | 1646 | ath_tx_send_normal(sc, txctl->txq, &bf_head); |
f078f209 | 1647 | } |
528f0c6b | 1648 | |
c37452b0 | 1649 | tx_done: |
528f0c6b | 1650 | spin_unlock_bh(&txctl->txq->axq_lock); |
f078f209 LR |
1651 | } |
1652 | ||
f8316df1 | 1653 | /* Upon failure caller should free skb */ |
c52f33d0 | 1654 | int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, |
528f0c6b | 1655 | struct ath_tx_control *txctl) |
f078f209 | 1656 | { |
c52f33d0 JM |
1657 | struct ath_wiphy *aphy = hw->priv; |
1658 | struct ath_softc *sc = aphy->sc; | |
528f0c6b | 1659 | struct ath_buf *bf; |
f8316df1 | 1660 | int r; |
f078f209 | 1661 | |
528f0c6b S |
1662 | bf = ath_tx_get_buffer(sc); |
1663 | if (!bf) { | |
04bd4638 | 1664 | DPRINTF(sc, ATH_DBG_XMIT, "TX buffers are full\n"); |
528f0c6b S |
1665 | return -1; |
1666 | } | |
1667 | ||
c52f33d0 | 1668 | r = ath_tx_setup_buffer(hw, bf, skb, txctl); |
f8316df1 | 1669 | if (unlikely(r)) { |
c112d0c5 LR |
1670 | struct ath_txq *txq = txctl->txq; |
1671 | ||
f8316df1 | 1672 | DPRINTF(sc, ATH_DBG_FATAL, "TX mem alloc failure\n"); |
c112d0c5 LR |
1673 | |
1674 | /* upon ath_tx_processq() this TX queue will be resumed, we | |
1675 | * guarantee this will happen by knowing beforehand that | |
1676 | * we will at least have to run TX completionon one buffer | |
1677 | * on the queue */ | |
1678 | spin_lock_bh(&txq->axq_lock); | |
f7a99e46 | 1679 | if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) { |
c112d0c5 LR |
1680 | ieee80211_stop_queue(sc->hw, |
1681 | skb_get_queue_mapping(skb)); | |
1682 | txq->stopped = 1; | |
1683 | } | |
1684 | spin_unlock_bh(&txq->axq_lock); | |
1685 | ||
b77f483f S |
1686 | spin_lock_bh(&sc->tx.txbuflock); |
1687 | list_add_tail(&bf->list, &sc->tx.txbuf); | |
1688 | spin_unlock_bh(&sc->tx.txbuflock); | |
c112d0c5 | 1689 | |
f8316df1 LR |
1690 | return r; |
1691 | } | |
1692 | ||
8f93b8b3 | 1693 | ath_tx_start_dma(sc, bf, txctl); |
f078f209 | 1694 | |
528f0c6b | 1695 | return 0; |
f078f209 LR |
1696 | } |
1697 | ||
c52f33d0 | 1698 | void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb) |
f078f209 | 1699 | { |
c52f33d0 JM |
1700 | struct ath_wiphy *aphy = hw->priv; |
1701 | struct ath_softc *sc = aphy->sc; | |
e8324357 S |
1702 | int hdrlen, padsize; |
1703 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
1704 | struct ath_tx_control txctl; | |
f078f209 | 1705 | |
e8324357 | 1706 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
f078f209 LR |
1707 | |
1708 | /* | |
e8324357 S |
1709 | * As a temporary workaround, assign seq# here; this will likely need |
1710 | * to be cleaned up to work better with Beacon transmission and virtual | |
1711 | * BSSes. | |
f078f209 | 1712 | */ |
e8324357 S |
1713 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { |
1714 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
1715 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) | |
1716 | sc->tx.seq_no += 0x10; | |
1717 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); | |
1718 | hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); | |
f078f209 | 1719 | } |
f078f209 | 1720 | |
e8324357 S |
1721 | /* Add the padding after the header if this is not already done */ |
1722 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); | |
1723 | if (hdrlen & 3) { | |
1724 | padsize = hdrlen % 4; | |
1725 | if (skb_headroom(skb) < padsize) { | |
1726 | DPRINTF(sc, ATH_DBG_XMIT, "TX CABQ padding failed\n"); | |
1727 | dev_kfree_skb_any(skb); | |
1728 | return; | |
1729 | } | |
1730 | skb_push(skb, padsize); | |
1731 | memmove(skb->data, skb->data + padsize, hdrlen); | |
f078f209 | 1732 | } |
f078f209 | 1733 | |
e8324357 | 1734 | txctl.txq = sc->beacon.cabq; |
f078f209 | 1735 | |
e8324357 | 1736 | DPRINTF(sc, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb); |
f078f209 | 1737 | |
c52f33d0 | 1738 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
e8324357 S |
1739 | DPRINTF(sc, ATH_DBG_XMIT, "CABQ TX failed\n"); |
1740 | goto exit; | |
f078f209 | 1741 | } |
f078f209 | 1742 | |
e8324357 S |
1743 | return; |
1744 | exit: | |
1745 | dev_kfree_skb_any(skb); | |
f078f209 LR |
1746 | } |
1747 | ||
e8324357 S |
1748 | /*****************/ |
1749 | /* TX Completion */ | |
1750 | /*****************/ | |
528f0c6b | 1751 | |
e8324357 | 1752 | static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, |
6b2c4032 | 1753 | int tx_flags) |
528f0c6b | 1754 | { |
e8324357 S |
1755 | struct ieee80211_hw *hw = sc->hw; |
1756 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1757 | struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info); | |
1758 | int hdrlen, padsize; | |
f0ed85c6 | 1759 | int frame_type = ATH9K_NOT_INTERNAL; |
528f0c6b | 1760 | |
e8324357 | 1761 | DPRINTF(sc, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb); |
528f0c6b | 1762 | |
f0ed85c6 | 1763 | if (tx_info_priv) { |
c52f33d0 | 1764 | hw = tx_info_priv->aphy->hw; |
f0ed85c6 JM |
1765 | frame_type = tx_info_priv->frame_type; |
1766 | } | |
c52f33d0 | 1767 | |
e8324357 S |
1768 | if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK || |
1769 | tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) { | |
1770 | kfree(tx_info_priv); | |
1771 | tx_info->rate_driver_data[0] = NULL; | |
1772 | } | |
528f0c6b | 1773 | |
6b2c4032 | 1774 | if (tx_flags & ATH_TX_BAR) |
e8324357 | 1775 | tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; |
e8324357 | 1776 | |
6b2c4032 | 1777 | if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) { |
e8324357 S |
1778 | /* Frame was ACKed */ |
1779 | tx_info->flags |= IEEE80211_TX_STAT_ACK; | |
528f0c6b S |
1780 | } |
1781 | ||
e8324357 S |
1782 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); |
1783 | padsize = hdrlen & 3; | |
1784 | if (padsize && hdrlen >= 24) { | |
1785 | /* | |
1786 | * Remove MAC header padding before giving the frame back to | |
1787 | * mac80211. | |
1788 | */ | |
1789 | memmove(skb->data + padsize, skb->data, hdrlen); | |
1790 | skb_pull(skb, padsize); | |
1791 | } | |
528f0c6b | 1792 | |
f0ed85c6 JM |
1793 | if (frame_type == ATH9K_NOT_INTERNAL) |
1794 | ieee80211_tx_status(hw, skb); | |
1795 | else | |
1796 | ath9k_tx_status(hw, skb); | |
e8324357 | 1797 | } |
f078f209 | 1798 | |
e8324357 S |
1799 | static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, |
1800 | struct list_head *bf_q, | |
1801 | int txok, int sendbar) | |
f078f209 | 1802 | { |
e8324357 | 1803 | struct sk_buff *skb = bf->bf_mpdu; |
e8324357 | 1804 | unsigned long flags; |
6b2c4032 | 1805 | int tx_flags = 0; |
f078f209 | 1806 | |
f078f209 | 1807 | |
e8324357 | 1808 | if (sendbar) |
6b2c4032 | 1809 | tx_flags = ATH_TX_BAR; |
f078f209 | 1810 | |
e8324357 | 1811 | if (!txok) { |
6b2c4032 | 1812 | tx_flags |= ATH_TX_ERROR; |
f078f209 | 1813 | |
e8324357 | 1814 | if (bf_isxretried(bf)) |
6b2c4032 | 1815 | tx_flags |= ATH_TX_XRETRY; |
f078f209 LR |
1816 | } |
1817 | ||
e8324357 | 1818 | dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE); |
6b2c4032 | 1819 | ath_tx_complete(sc, skb, tx_flags); |
e8324357 S |
1820 | |
1821 | /* | |
1822 | * Return the list of ath_buf of this mpdu to free queue | |
1823 | */ | |
1824 | spin_lock_irqsave(&sc->tx.txbuflock, flags); | |
1825 | list_splice_tail_init(bf_q, &sc->tx.txbuf); | |
1826 | spin_unlock_irqrestore(&sc->tx.txbuflock, flags); | |
f078f209 LR |
1827 | } |
1828 | ||
e8324357 S |
1829 | static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf, |
1830 | int txok) | |
f078f209 | 1831 | { |
e8324357 S |
1832 | struct ath_buf *bf_last = bf->bf_lastbf; |
1833 | struct ath_desc *ds = bf_last->bf_desc; | |
1834 | u16 seq_st = 0; | |
1835 | u32 ba[WME_BA_BMP_SIZE >> 5]; | |
1836 | int ba_index; | |
1837 | int nbad = 0; | |
1838 | int isaggr = 0; | |
f078f209 | 1839 | |
e8324357 S |
1840 | if (ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED) |
1841 | return 0; | |
f078f209 | 1842 | |
e8324357 S |
1843 | isaggr = bf_isaggr(bf); |
1844 | if (isaggr) { | |
1845 | seq_st = ATH_DS_BA_SEQ(ds); | |
1846 | memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3); | |
1847 | } | |
f078f209 | 1848 | |
e8324357 S |
1849 | while (bf) { |
1850 | ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno); | |
1851 | if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index))) | |
1852 | nbad++; | |
1853 | ||
1854 | bf = bf->bf_next; | |
1855 | } | |
f078f209 | 1856 | |
e8324357 S |
1857 | return nbad; |
1858 | } | |
f078f209 | 1859 | |
95e4acb7 | 1860 | static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds, |
8a92e2ee | 1861 | int nbad, int txok, bool update_rc) |
f078f209 | 1862 | { |
a22be22a | 1863 | struct sk_buff *skb = bf->bf_mpdu; |
254ad0ff | 1864 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
e8324357 S |
1865 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
1866 | struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info); | |
8a92e2ee VT |
1867 | struct ieee80211_hw *hw = tx_info_priv->aphy->hw; |
1868 | u8 i, tx_rateindex; | |
f078f209 | 1869 | |
95e4acb7 S |
1870 | if (txok) |
1871 | tx_info->status.ack_signal = ds->ds_txstat.ts_rssi; | |
1872 | ||
8a92e2ee VT |
1873 | tx_rateindex = ds->ds_txstat.ts_rateindex; |
1874 | WARN_ON(tx_rateindex >= hw->max_rates); | |
1875 | ||
1876 | tx_info_priv->update_rc = update_rc; | |
e8324357 S |
1877 | if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) |
1878 | tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; | |
f078f209 | 1879 | |
e8324357 | 1880 | if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 && |
8a92e2ee | 1881 | (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) { |
254ad0ff | 1882 | if (ieee80211_is_data(hdr->frame_control)) { |
e8324357 S |
1883 | memcpy(&tx_info_priv->tx, &ds->ds_txstat, |
1884 | sizeof(tx_info_priv->tx)); | |
1885 | tx_info_priv->n_frames = bf->bf_nframes; | |
1886 | tx_info_priv->n_bad_frames = nbad; | |
e8324357 | 1887 | } |
f078f209 | 1888 | } |
8a92e2ee VT |
1889 | |
1890 | for (i = tx_rateindex + 1; i < hw->max_rates; i++) | |
1891 | tx_info->status.rates[i].count = 0; | |
1892 | ||
1893 | tx_info->status.rates[tx_rateindex].count = bf->bf_retries + 1; | |
f078f209 LR |
1894 | } |
1895 | ||
059d806c S |
1896 | static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq) |
1897 | { | |
1898 | int qnum; | |
1899 | ||
1900 | spin_lock_bh(&txq->axq_lock); | |
1901 | if (txq->stopped && | |
f7a99e46 | 1902 | sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) { |
059d806c S |
1903 | qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc); |
1904 | if (qnum != -1) { | |
1905 | ieee80211_wake_queue(sc->hw, qnum); | |
1906 | txq->stopped = 0; | |
1907 | } | |
1908 | } | |
1909 | spin_unlock_bh(&txq->axq_lock); | |
1910 | } | |
1911 | ||
e8324357 | 1912 | static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) |
f078f209 | 1913 | { |
cbe61d8a | 1914 | struct ath_hw *ah = sc->sc_ah; |
e8324357 | 1915 | struct ath_buf *bf, *lastbf, *bf_held = NULL; |
f078f209 | 1916 | struct list_head bf_head; |
e8324357 | 1917 | struct ath_desc *ds; |
0934af23 | 1918 | int txok; |
e8324357 | 1919 | int status; |
f078f209 | 1920 | |
e8324357 S |
1921 | DPRINTF(sc, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n", |
1922 | txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), | |
1923 | txq->axq_link); | |
f078f209 | 1924 | |
f078f209 LR |
1925 | for (;;) { |
1926 | spin_lock_bh(&txq->axq_lock); | |
f078f209 LR |
1927 | if (list_empty(&txq->axq_q)) { |
1928 | txq->axq_link = NULL; | |
1929 | txq->axq_linkbuf = NULL; | |
1930 | spin_unlock_bh(&txq->axq_lock); | |
1931 | break; | |
1932 | } | |
f078f209 LR |
1933 | bf = list_first_entry(&txq->axq_q, struct ath_buf, list); |
1934 | ||
e8324357 S |
1935 | /* |
1936 | * There is a race condition that a BH gets scheduled | |
1937 | * after sw writes TxE and before hw re-load the last | |
1938 | * descriptor to get the newly chained one. | |
1939 | * Software must keep the last DONE descriptor as a | |
1940 | * holding descriptor - software does so by marking | |
1941 | * it with the STALE flag. | |
1942 | */ | |
1943 | bf_held = NULL; | |
a119cc49 | 1944 | if (bf->bf_stale) { |
e8324357 S |
1945 | bf_held = bf; |
1946 | if (list_is_last(&bf_held->list, &txq->axq_q)) { | |
6ef9b13d S |
1947 | txq->axq_link = NULL; |
1948 | txq->axq_linkbuf = NULL; | |
1949 | spin_unlock_bh(&txq->axq_lock); | |
1950 | ||
1951 | /* | |
e8324357 S |
1952 | * The holding descriptor is the last |
1953 | * descriptor in queue. It's safe to remove | |
1954 | * the last holding descriptor in BH context. | |
1955 | */ | |
6ef9b13d S |
1956 | spin_lock_bh(&sc->tx.txbuflock); |
1957 | list_move_tail(&bf_held->list, &sc->tx.txbuf); | |
1958 | spin_unlock_bh(&sc->tx.txbuflock); | |
1959 | ||
e8324357 S |
1960 | break; |
1961 | } else { | |
1962 | bf = list_entry(bf_held->list.next, | |
6ef9b13d | 1963 | struct ath_buf, list); |
e8324357 | 1964 | } |
f078f209 LR |
1965 | } |
1966 | ||
1967 | lastbf = bf->bf_lastbf; | |
e8324357 | 1968 | ds = lastbf->bf_desc; |
f078f209 | 1969 | |
e8324357 S |
1970 | status = ath9k_hw_txprocdesc(ah, ds); |
1971 | if (status == -EINPROGRESS) { | |
f078f209 | 1972 | spin_unlock_bh(&txq->axq_lock); |
e8324357 | 1973 | break; |
f078f209 | 1974 | } |
e8324357 S |
1975 | if (bf->bf_desc == txq->axq_lastdsWithCTS) |
1976 | txq->axq_lastdsWithCTS = NULL; | |
1977 | if (ds == txq->axq_gatingds) | |
1978 | txq->axq_gatingds = NULL; | |
f078f209 | 1979 | |
e8324357 S |
1980 | /* |
1981 | * Remove ath_buf's of the same transmit unit from txq, | |
1982 | * however leave the last descriptor back as the holding | |
1983 | * descriptor for hw. | |
1984 | */ | |
a119cc49 | 1985 | lastbf->bf_stale = true; |
e8324357 | 1986 | INIT_LIST_HEAD(&bf_head); |
e8324357 S |
1987 | if (!list_is_singular(&lastbf->list)) |
1988 | list_cut_position(&bf_head, | |
1989 | &txq->axq_q, lastbf->list.prev); | |
f078f209 | 1990 | |
e8324357 | 1991 | txq->axq_depth--; |
e8324357 S |
1992 | if (bf_isaggr(bf)) |
1993 | txq->axq_aggr_depth--; | |
f078f209 | 1994 | |
e8324357 | 1995 | txok = (ds->ds_txstat.ts_status == 0); |
e8324357 | 1996 | spin_unlock_bh(&txq->axq_lock); |
f078f209 | 1997 | |
e8324357 | 1998 | if (bf_held) { |
e8324357 | 1999 | spin_lock_bh(&sc->tx.txbuflock); |
6ef9b13d | 2000 | list_move_tail(&bf_held->list, &sc->tx.txbuf); |
e8324357 S |
2001 | spin_unlock_bh(&sc->tx.txbuflock); |
2002 | } | |
f078f209 | 2003 | |
e8324357 S |
2004 | if (!bf_isampdu(bf)) { |
2005 | /* | |
2006 | * This frame is sent out as a single frame. | |
2007 | * Use hardware retry status for this frame. | |
2008 | */ | |
2009 | bf->bf_retries = ds->ds_txstat.ts_longretry; | |
2010 | if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY) | |
2011 | bf->bf_state.bf_type |= BUF_XRETRY; | |
8a92e2ee | 2012 | ath_tx_rc_status(bf, ds, 0, txok, true); |
e8324357 | 2013 | } |
f078f209 | 2014 | |
e8324357 | 2015 | if (bf_isampdu(bf)) |
d43f3015 | 2016 | ath_tx_complete_aggr(sc, txq, bf, &bf_head, txok); |
e8324357 S |
2017 | else |
2018 | ath_tx_complete_buf(sc, bf, &bf_head, txok, 0); | |
8469cdef | 2019 | |
059d806c | 2020 | ath_wake_mac80211_queue(sc, txq); |
8469cdef | 2021 | |
059d806c | 2022 | spin_lock_bh(&txq->axq_lock); |
e8324357 S |
2023 | if (sc->sc_flags & SC_OP_TXAGGR) |
2024 | ath_txq_schedule(sc, txq); | |
2025 | spin_unlock_bh(&txq->axq_lock); | |
8469cdef S |
2026 | } |
2027 | } | |
2028 | ||
f078f209 | 2029 | |
e8324357 | 2030 | void ath_tx_tasklet(struct ath_softc *sc) |
f078f209 | 2031 | { |
e8324357 S |
2032 | int i; |
2033 | u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1); | |
f078f209 | 2034 | |
e8324357 | 2035 | ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask); |
f078f209 | 2036 | |
e8324357 S |
2037 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
2038 | if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i))) | |
2039 | ath_tx_processq(sc, &sc->tx.txq[i]); | |
f078f209 LR |
2040 | } |
2041 | } | |
2042 | ||
e8324357 S |
2043 | /*****************/ |
2044 | /* Init, Cleanup */ | |
2045 | /*****************/ | |
f078f209 | 2046 | |
e8324357 | 2047 | int ath_tx_init(struct ath_softc *sc, int nbufs) |
f078f209 | 2048 | { |
e8324357 | 2049 | int error = 0; |
f078f209 | 2050 | |
797fe5cb | 2051 | spin_lock_init(&sc->tx.txbuflock); |
f078f209 | 2052 | |
797fe5cb S |
2053 | error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, |
2054 | "tx", nbufs, 1); | |
2055 | if (error != 0) { | |
2056 | DPRINTF(sc, ATH_DBG_FATAL, | |
2057 | "Failed to allocate tx descriptors: %d\n", error); | |
2058 | goto err; | |
2059 | } | |
f078f209 | 2060 | |
797fe5cb S |
2061 | error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, |
2062 | "beacon", ATH_BCBUF, 1); | |
2063 | if (error != 0) { | |
2064 | DPRINTF(sc, ATH_DBG_FATAL, | |
2065 | "Failed to allocate beacon descriptors: %d\n", error); | |
2066 | goto err; | |
2067 | } | |
f078f209 | 2068 | |
797fe5cb | 2069 | err: |
e8324357 S |
2070 | if (error != 0) |
2071 | ath_tx_cleanup(sc); | |
f078f209 | 2072 | |
e8324357 | 2073 | return error; |
f078f209 LR |
2074 | } |
2075 | ||
797fe5cb | 2076 | void ath_tx_cleanup(struct ath_softc *sc) |
e8324357 S |
2077 | { |
2078 | if (sc->beacon.bdma.dd_desc_len != 0) | |
2079 | ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf); | |
2080 | ||
2081 | if (sc->tx.txdma.dd_desc_len != 0) | |
2082 | ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf); | |
e8324357 | 2083 | } |
f078f209 LR |
2084 | |
2085 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an) | |
2086 | { | |
c5170163 S |
2087 | struct ath_atx_tid *tid; |
2088 | struct ath_atx_ac *ac; | |
2089 | int tidno, acno; | |
f078f209 | 2090 | |
8ee5afbc | 2091 | for (tidno = 0, tid = &an->tid[tidno]; |
c5170163 S |
2092 | tidno < WME_NUM_TID; |
2093 | tidno++, tid++) { | |
2094 | tid->an = an; | |
2095 | tid->tidno = tidno; | |
2096 | tid->seq_start = tid->seq_next = 0; | |
2097 | tid->baw_size = WME_MAX_BA; | |
2098 | tid->baw_head = tid->baw_tail = 0; | |
2099 | tid->sched = false; | |
e8324357 | 2100 | tid->paused = false; |
a37c2c79 | 2101 | tid->state &= ~AGGR_CLEANUP; |
c5170163 | 2102 | INIT_LIST_HEAD(&tid->buf_q); |
c5170163 | 2103 | acno = TID_TO_WME_AC(tidno); |
8ee5afbc | 2104 | tid->ac = &an->ac[acno]; |
a37c2c79 S |
2105 | tid->state &= ~AGGR_ADDBA_COMPLETE; |
2106 | tid->state &= ~AGGR_ADDBA_PROGRESS; | |
2107 | tid->addba_exchangeattempts = 0; | |
c5170163 | 2108 | } |
f078f209 | 2109 | |
8ee5afbc | 2110 | for (acno = 0, ac = &an->ac[acno]; |
c5170163 S |
2111 | acno < WME_NUM_AC; acno++, ac++) { |
2112 | ac->sched = false; | |
2113 | INIT_LIST_HEAD(&ac->tid_q); | |
2114 | ||
2115 | switch (acno) { | |
2116 | case WME_AC_BE: | |
2117 | ac->qnum = ath_tx_get_qnum(sc, | |
2118 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE); | |
2119 | break; | |
2120 | case WME_AC_BK: | |
2121 | ac->qnum = ath_tx_get_qnum(sc, | |
2122 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK); | |
2123 | break; | |
2124 | case WME_AC_VI: | |
2125 | ac->qnum = ath_tx_get_qnum(sc, | |
2126 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI); | |
2127 | break; | |
2128 | case WME_AC_VO: | |
2129 | ac->qnum = ath_tx_get_qnum(sc, | |
2130 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO); | |
2131 | break; | |
f078f209 LR |
2132 | } |
2133 | } | |
2134 | } | |
2135 | ||
b5aa9bf9 | 2136 | void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an) |
f078f209 LR |
2137 | { |
2138 | int i; | |
2139 | struct ath_atx_ac *ac, *ac_tmp; | |
2140 | struct ath_atx_tid *tid, *tid_tmp; | |
2141 | struct ath_txq *txq; | |
e8324357 | 2142 | |
f078f209 LR |
2143 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
2144 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f | 2145 | txq = &sc->tx.txq[i]; |
f078f209 | 2146 | |
b5aa9bf9 | 2147 | spin_lock(&txq->axq_lock); |
f078f209 LR |
2148 | |
2149 | list_for_each_entry_safe(ac, | |
2150 | ac_tmp, &txq->axq_acq, list) { | |
2151 | tid = list_first_entry(&ac->tid_q, | |
2152 | struct ath_atx_tid, list); | |
2153 | if (tid && tid->an != an) | |
2154 | continue; | |
2155 | list_del(&ac->list); | |
2156 | ac->sched = false; | |
2157 | ||
2158 | list_for_each_entry_safe(tid, | |
2159 | tid_tmp, &ac->tid_q, list) { | |
2160 | list_del(&tid->list); | |
2161 | tid->sched = false; | |
b5aa9bf9 | 2162 | ath_tid_drain(sc, txq, tid); |
a37c2c79 | 2163 | tid->state &= ~AGGR_ADDBA_COMPLETE; |
f078f209 | 2164 | tid->addba_exchangeattempts = 0; |
a37c2c79 | 2165 | tid->state &= ~AGGR_CLEANUP; |
f078f209 LR |
2166 | } |
2167 | } | |
2168 | ||
b5aa9bf9 | 2169 | spin_unlock(&txq->axq_lock); |
f078f209 LR |
2170 | } |
2171 | } | |
2172 | } |