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2be7d22f | 1 | /* |
02525a79 | 2 | * Copyright (c) 2012-2014 Qualcomm Atheros, Inc. |
2be7d22f VK |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include <linux/interrupt.h> | |
18 | ||
19 | #include "wil6210.h" | |
98658095 | 20 | #include "trace.h" |
2be7d22f VK |
21 | |
22 | /** | |
23 | * Theory of operation: | |
24 | * | |
25 | * There is ISR pseudo-cause register, | |
26 | * dma_rgf->DMA_RGF.PSEUDO_CAUSE.PSEUDO_CAUSE | |
27 | * Its bits represents OR'ed bits from 3 real ISR registers: | |
28 | * TX, RX, and MISC. | |
29 | * | |
30 | * Registers may be configured to either "write 1 to clear" or | |
31 | * "clear on read" mode | |
32 | * | |
33 | * When handling interrupt, one have to mask/unmask interrupts for the | |
34 | * real ISR registers, or hardware may malfunction. | |
35 | * | |
36 | */ | |
37 | ||
38 | #define WIL6210_IRQ_DISABLE (0xFFFFFFFFUL) | |
39 | #define WIL6210_IMC_RX BIT_DMA_EP_RX_ICR_RX_DONE | |
40 | #define WIL6210_IMC_TX (BIT_DMA_EP_TX_ICR_TX_DONE | \ | |
41 | BIT_DMA_EP_TX_ICR_TX_DONE_N(0)) | |
7269494e VK |
42 | #define WIL6210_IMC_MISC (ISR_MISC_FW_READY | \ |
43 | ISR_MISC_MBOX_EVT | \ | |
44 | ISR_MISC_FW_ERROR) | |
2be7d22f VK |
45 | |
46 | #define WIL6210_IRQ_PSEUDO_MASK (u32)(~(BIT_DMA_PSEUDO_CAUSE_RX | \ | |
47 | BIT_DMA_PSEUDO_CAUSE_TX | \ | |
48 | BIT_DMA_PSEUDO_CAUSE_MISC)) | |
49 | ||
50 | #if defined(CONFIG_WIL6210_ISR_COR) | |
51 | /* configure to Clear-On-Read mode */ | |
52 | #define WIL_ICR_ICC_VALUE (0xFFFFFFFFUL) | |
53 | ||
54 | static inline void wil_icr_clear(u32 x, void __iomem *addr) | |
55 | { | |
2be7d22f VK |
56 | } |
57 | #else /* defined(CONFIG_WIL6210_ISR_COR) */ | |
58 | /* configure to Write-1-to-Clear mode */ | |
59 | #define WIL_ICR_ICC_VALUE (0UL) | |
60 | ||
61 | static inline void wil_icr_clear(u32 x, void __iomem *addr) | |
62 | { | |
63 | iowrite32(x, addr); | |
64 | } | |
65 | #endif /* defined(CONFIG_WIL6210_ISR_COR) */ | |
66 | ||
67 | static inline u32 wil_ioread32_and_clear(void __iomem *addr) | |
68 | { | |
69 | u32 x = ioread32(addr); | |
70 | ||
71 | wil_icr_clear(x, addr); | |
72 | ||
73 | return x; | |
74 | } | |
75 | ||
76 | static void wil6210_mask_irq_tx(struct wil6210_priv *wil) | |
77 | { | |
78 | iowrite32(WIL6210_IRQ_DISABLE, wil->csr + | |
79 | HOSTADDR(RGF_DMA_EP_TX_ICR) + | |
80 | offsetof(struct RGF_ICR, IMS)); | |
81 | } | |
82 | ||
83 | static void wil6210_mask_irq_rx(struct wil6210_priv *wil) | |
84 | { | |
85 | iowrite32(WIL6210_IRQ_DISABLE, wil->csr + | |
86 | HOSTADDR(RGF_DMA_EP_RX_ICR) + | |
87 | offsetof(struct RGF_ICR, IMS)); | |
88 | } | |
89 | ||
90 | static void wil6210_mask_irq_misc(struct wil6210_priv *wil) | |
91 | { | |
92 | iowrite32(WIL6210_IRQ_DISABLE, wil->csr + | |
93 | HOSTADDR(RGF_DMA_EP_MISC_ICR) + | |
94 | offsetof(struct RGF_ICR, IMS)); | |
95 | } | |
96 | ||
97 | static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil) | |
98 | { | |
7743882d | 99 | wil_dbg_irq(wil, "%s()\n", __func__); |
2be7d22f VK |
100 | |
101 | iowrite32(WIL6210_IRQ_DISABLE, wil->csr + | |
102 | HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW)); | |
103 | ||
104 | clear_bit(wil_status_irqen, &wil->status); | |
105 | } | |
106 | ||
e0287c4a | 107 | void wil6210_unmask_irq_tx(struct wil6210_priv *wil) |
2be7d22f VK |
108 | { |
109 | iowrite32(WIL6210_IMC_TX, wil->csr + | |
110 | HOSTADDR(RGF_DMA_EP_TX_ICR) + | |
111 | offsetof(struct RGF_ICR, IMC)); | |
112 | } | |
113 | ||
e0287c4a | 114 | void wil6210_unmask_irq_rx(struct wil6210_priv *wil) |
2be7d22f VK |
115 | { |
116 | iowrite32(WIL6210_IMC_RX, wil->csr + | |
117 | HOSTADDR(RGF_DMA_EP_RX_ICR) + | |
118 | offsetof(struct RGF_ICR, IMC)); | |
119 | } | |
120 | ||
121 | static void wil6210_unmask_irq_misc(struct wil6210_priv *wil) | |
122 | { | |
123 | iowrite32(WIL6210_IMC_MISC, wil->csr + | |
124 | HOSTADDR(RGF_DMA_EP_MISC_ICR) + | |
125 | offsetof(struct RGF_ICR, IMC)); | |
126 | } | |
127 | ||
128 | static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil) | |
129 | { | |
7743882d | 130 | wil_dbg_irq(wil, "%s()\n", __func__); |
2be7d22f VK |
131 | |
132 | set_bit(wil_status_irqen, &wil->status); | |
133 | ||
134 | iowrite32(WIL6210_IRQ_PSEUDO_MASK, wil->csr + | |
135 | HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW)); | |
136 | } | |
137 | ||
138 | void wil6210_disable_irq(struct wil6210_priv *wil) | |
139 | { | |
7743882d | 140 | wil_dbg_irq(wil, "%s()\n", __func__); |
2be7d22f VK |
141 | |
142 | wil6210_mask_irq_tx(wil); | |
143 | wil6210_mask_irq_rx(wil); | |
144 | wil6210_mask_irq_misc(wil); | |
145 | wil6210_mask_irq_pseudo(wil); | |
146 | } | |
147 | ||
148 | void wil6210_enable_irq(struct wil6210_priv *wil) | |
149 | { | |
7743882d | 150 | wil_dbg_irq(wil, "%s()\n", __func__); |
2be7d22f VK |
151 | |
152 | iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) + | |
153 | offsetof(struct RGF_ICR, ICC)); | |
154 | iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) + | |
155 | offsetof(struct RGF_ICR, ICC)); | |
156 | iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) + | |
157 | offsetof(struct RGF_ICR, ICC)); | |
158 | ||
83982cbe VK |
159 | /* interrupt moderation parameters */ |
160 | if (wil->wdev->iftype == NL80211_IFTYPE_MONITOR) { | |
161 | /* disable interrupt moderation for monitor | |
162 | * to get better timestamp precision | |
163 | */ | |
164 | iowrite32(0, wil->csr + HOSTADDR(RGF_DMA_ITR_CNT_CRL)); | |
165 | } else { | |
166 | iowrite32(WIL6210_ITR_TRSH, | |
167 | wil->csr + HOSTADDR(RGF_DMA_ITR_CNT_TRSH)); | |
168 | iowrite32(BIT_DMA_ITR_CNT_CRL_EN, | |
169 | wil->csr + HOSTADDR(RGF_DMA_ITR_CNT_CRL)); | |
170 | } | |
171 | ||
2be7d22f VK |
172 | wil6210_unmask_irq_pseudo(wil); |
173 | wil6210_unmask_irq_tx(wil); | |
174 | wil6210_unmask_irq_rx(wil); | |
175 | wil6210_unmask_irq_misc(wil); | |
176 | } | |
177 | ||
178 | static irqreturn_t wil6210_irq_rx(int irq, void *cookie) | |
179 | { | |
180 | struct wil6210_priv *wil = cookie; | |
181 | u32 isr = wil_ioread32_and_clear(wil->csr + | |
182 | HOSTADDR(RGF_DMA_EP_RX_ICR) + | |
183 | offsetof(struct RGF_ICR, ICR)); | |
184 | ||
98658095 | 185 | trace_wil6210_irq_rx(isr); |
7743882d | 186 | wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr); |
2be7d22f VK |
187 | |
188 | if (!isr) { | |
189 | wil_err(wil, "spurious IRQ: RX\n"); | |
190 | return IRQ_NONE; | |
191 | } | |
192 | ||
193 | wil6210_mask_irq_rx(wil); | |
194 | ||
195 | if (isr & BIT_DMA_EP_RX_ICR_RX_DONE) { | |
7743882d | 196 | wil_dbg_irq(wil, "RX done\n"); |
2be7d22f | 197 | isr &= ~BIT_DMA_EP_RX_ICR_RX_DONE; |
0fef1818 VK |
198 | if (test_bit(wil_status_reset_done, &wil->status)) { |
199 | wil_dbg_txrx(wil, "NAPI(Rx) schedule\n"); | |
200 | napi_schedule(&wil->napi_rx); | |
201 | } else { | |
202 | wil_err(wil, "Got Rx interrupt while in reset\n"); | |
203 | } | |
2be7d22f VK |
204 | } |
205 | ||
206 | if (isr) | |
207 | wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr); | |
208 | ||
e0287c4a | 209 | /* Rx IRQ will be enabled when NAPI processing finished */ |
2be7d22f | 210 | |
be299858 | 211 | atomic_inc(&wil->isr_count_rx); |
2be7d22f VK |
212 | return IRQ_HANDLED; |
213 | } | |
214 | ||
215 | static irqreturn_t wil6210_irq_tx(int irq, void *cookie) | |
216 | { | |
217 | struct wil6210_priv *wil = cookie; | |
218 | u32 isr = wil_ioread32_and_clear(wil->csr + | |
219 | HOSTADDR(RGF_DMA_EP_TX_ICR) + | |
220 | offsetof(struct RGF_ICR, ICR)); | |
221 | ||
98658095 | 222 | trace_wil6210_irq_tx(isr); |
7743882d | 223 | wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr); |
2be7d22f VK |
224 | |
225 | if (!isr) { | |
226 | wil_err(wil, "spurious IRQ: TX\n"); | |
227 | return IRQ_NONE; | |
228 | } | |
229 | ||
230 | wil6210_mask_irq_tx(wil); | |
231 | ||
232 | if (isr & BIT_DMA_EP_TX_ICR_TX_DONE) { | |
7743882d | 233 | wil_dbg_irq(wil, "TX done\n"); |
2be7d22f | 234 | isr &= ~BIT_DMA_EP_TX_ICR_TX_DONE; |
e0287c4a VK |
235 | /* clear also all VRING interrupts */ |
236 | isr &= ~(BIT(25) - 1UL); | |
0fef1818 VK |
237 | if (test_bit(wil_status_reset_done, &wil->status)) { |
238 | wil_dbg_txrx(wil, "NAPI(Tx) schedule\n"); | |
239 | napi_schedule(&wil->napi_tx); | |
240 | } else { | |
241 | wil_err(wil, "Got Tx interrupt while in reset\n"); | |
242 | } | |
2be7d22f VK |
243 | } |
244 | ||
245 | if (isr) | |
246 | wil_err(wil, "un-handled TX ISR bits 0x%08x\n", isr); | |
247 | ||
e0287c4a | 248 | /* Tx IRQ will be enabled when NAPI processing finished */ |
2be7d22f | 249 | |
be299858 | 250 | atomic_inc(&wil->isr_count_tx); |
2be7d22f VK |
251 | return IRQ_HANDLED; |
252 | } | |
253 | ||
7269494e VK |
254 | static void wil_notify_fw_error(struct wil6210_priv *wil) |
255 | { | |
256 | struct device *dev = &wil_to_ndev(wil)->dev; | |
257 | char *envp[3] = { | |
258 | [0] = "SOURCE=wil6210", | |
259 | [1] = "EVENT=FW_ERROR", | |
260 | [2] = NULL, | |
261 | }; | |
92b6747e | 262 | wil_err(wil, "Notify about firmware error\n"); |
7269494e VK |
263 | kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, envp); |
264 | } | |
265 | ||
55f7acdd VK |
266 | static void wil_cache_mbox_regs(struct wil6210_priv *wil) |
267 | { | |
268 | /* make shadow copy of registers that should not change on run time */ | |
269 | wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX, | |
270 | sizeof(struct wil6210_mbox_ctl)); | |
271 | wil_mbox_ring_le2cpus(&wil->mbox_ctl.rx); | |
272 | wil_mbox_ring_le2cpus(&wil->mbox_ctl.tx); | |
273 | } | |
274 | ||
2be7d22f VK |
275 | static irqreturn_t wil6210_irq_misc(int irq, void *cookie) |
276 | { | |
277 | struct wil6210_priv *wil = cookie; | |
278 | u32 isr = wil_ioread32_and_clear(wil->csr + | |
279 | HOSTADDR(RGF_DMA_EP_MISC_ICR) + | |
280 | offsetof(struct RGF_ICR, ICR)); | |
281 | ||
98658095 | 282 | trace_wil6210_irq_misc(isr); |
7743882d | 283 | wil_dbg_irq(wil, "ISR MISC 0x%08x\n", isr); |
2be7d22f VK |
284 | |
285 | if (!isr) { | |
286 | wil_err(wil, "spurious IRQ: MISC\n"); | |
287 | return IRQ_NONE; | |
288 | } | |
289 | ||
290 | wil6210_mask_irq_misc(wil); | |
291 | ||
7269494e | 292 | if (isr & ISR_MISC_FW_ERROR) { |
de70ab87 | 293 | wil_err(wil, "Firmware error detected\n"); |
7269494e | 294 | clear_bit(wil_status_fwready, &wil->status); |
de70ab87 VK |
295 | /* |
296 | * do not clear @isr here - we do 2-nd part in thread | |
297 | * there, user space get notified, and it should be done | |
298 | * in non-atomic context | |
299 | */ | |
7269494e VK |
300 | } |
301 | ||
2be7d22f | 302 | if (isr & ISR_MISC_FW_READY) { |
7743882d | 303 | wil_dbg_irq(wil, "IRQ: FW ready\n"); |
55f7acdd VK |
304 | wil_cache_mbox_regs(wil); |
305 | set_bit(wil_status_reset_done, &wil->status); | |
2be7d22f VK |
306 | /** |
307 | * Actual FW ready indicated by the | |
308 | * WMI_FW_READY_EVENTID | |
309 | */ | |
310 | isr &= ~ISR_MISC_FW_READY; | |
311 | } | |
312 | ||
313 | wil->isr_misc = isr; | |
314 | ||
315 | if (isr) { | |
316 | return IRQ_WAKE_THREAD; | |
317 | } else { | |
318 | wil6210_unmask_irq_misc(wil); | |
319 | return IRQ_HANDLED; | |
320 | } | |
321 | } | |
322 | ||
323 | static irqreturn_t wil6210_irq_misc_thread(int irq, void *cookie) | |
324 | { | |
325 | struct wil6210_priv *wil = cookie; | |
326 | u32 isr = wil->isr_misc; | |
327 | ||
98658095 | 328 | trace_wil6210_irq_misc_thread(isr); |
7743882d | 329 | wil_dbg_irq(wil, "Thread ISR MISC 0x%08x\n", isr); |
2be7d22f | 330 | |
de70ab87 VK |
331 | if (isr & ISR_MISC_FW_ERROR) { |
332 | wil_notify_fw_error(wil); | |
333 | isr &= ~ISR_MISC_FW_ERROR; | |
ed6f9dc6 | 334 | wil_fw_error_recovery(wil); |
de70ab87 VK |
335 | } |
336 | ||
2be7d22f | 337 | if (isr & ISR_MISC_MBOX_EVT) { |
7743882d | 338 | wil_dbg_irq(wil, "MBOX event\n"); |
2be7d22f VK |
339 | wmi_recv_cmd(wil); |
340 | isr &= ~ISR_MISC_MBOX_EVT; | |
341 | } | |
342 | ||
343 | if (isr) | |
15e23124 | 344 | wil_dbg_irq(wil, "un-handled MISC ISR bits 0x%08x\n", isr); |
2be7d22f VK |
345 | |
346 | wil->isr_misc = 0; | |
347 | ||
348 | wil6210_unmask_irq_misc(wil); | |
349 | ||
350 | return IRQ_HANDLED; | |
351 | } | |
352 | ||
353 | /** | |
354 | * thread IRQ handler | |
355 | */ | |
356 | static irqreturn_t wil6210_thread_irq(int irq, void *cookie) | |
357 | { | |
358 | struct wil6210_priv *wil = cookie; | |
359 | ||
7743882d | 360 | wil_dbg_irq(wil, "Thread IRQ\n"); |
2be7d22f VK |
361 | /* Discover real IRQ cause */ |
362 | if (wil->isr_misc) | |
363 | wil6210_irq_misc_thread(irq, cookie); | |
364 | ||
365 | wil6210_unmask_irq_pseudo(wil); | |
366 | ||
367 | return IRQ_HANDLED; | |
368 | } | |
369 | ||
370 | /* DEBUG | |
371 | * There is subtle bug in hardware that causes IRQ to raise when it should be | |
372 | * masked. It is quite rare and hard to debug. | |
373 | * | |
374 | * Catch irq issue if it happens and print all I can. | |
375 | */ | |
376 | static int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause) | |
377 | { | |
378 | if (!test_bit(wil_status_irqen, &wil->status)) { | |
379 | u32 icm_rx = wil_ioread32_and_clear(wil->csr + | |
380 | HOSTADDR(RGF_DMA_EP_RX_ICR) + | |
381 | offsetof(struct RGF_ICR, ICM)); | |
382 | u32 icr_rx = wil_ioread32_and_clear(wil->csr + | |
383 | HOSTADDR(RGF_DMA_EP_RX_ICR) + | |
384 | offsetof(struct RGF_ICR, ICR)); | |
385 | u32 imv_rx = ioread32(wil->csr + | |
386 | HOSTADDR(RGF_DMA_EP_RX_ICR) + | |
387 | offsetof(struct RGF_ICR, IMV)); | |
388 | u32 icm_tx = wil_ioread32_and_clear(wil->csr + | |
389 | HOSTADDR(RGF_DMA_EP_TX_ICR) + | |
390 | offsetof(struct RGF_ICR, ICM)); | |
391 | u32 icr_tx = wil_ioread32_and_clear(wil->csr + | |
392 | HOSTADDR(RGF_DMA_EP_TX_ICR) + | |
393 | offsetof(struct RGF_ICR, ICR)); | |
394 | u32 imv_tx = ioread32(wil->csr + | |
395 | HOSTADDR(RGF_DMA_EP_TX_ICR) + | |
396 | offsetof(struct RGF_ICR, IMV)); | |
397 | u32 icm_misc = wil_ioread32_and_clear(wil->csr + | |
398 | HOSTADDR(RGF_DMA_EP_MISC_ICR) + | |
399 | offsetof(struct RGF_ICR, ICM)); | |
400 | u32 icr_misc = wil_ioread32_and_clear(wil->csr + | |
401 | HOSTADDR(RGF_DMA_EP_MISC_ICR) + | |
402 | offsetof(struct RGF_ICR, ICR)); | |
403 | u32 imv_misc = ioread32(wil->csr + | |
404 | HOSTADDR(RGF_DMA_EP_MISC_ICR) + | |
405 | offsetof(struct RGF_ICR, IMV)); | |
406 | wil_err(wil, "IRQ when it should be masked: pseudo 0x%08x\n" | |
407 | "Rx icm:icr:imv 0x%08x 0x%08x 0x%08x\n" | |
408 | "Tx icm:icr:imv 0x%08x 0x%08x 0x%08x\n" | |
409 | "Misc icm:icr:imv 0x%08x 0x%08x 0x%08x\n", | |
410 | pseudo_cause, | |
411 | icm_rx, icr_rx, imv_rx, | |
412 | icm_tx, icr_tx, imv_tx, | |
413 | icm_misc, icr_misc, imv_misc); | |
414 | ||
415 | return -EINVAL; | |
416 | } | |
417 | ||
418 | return 0; | |
419 | } | |
420 | ||
421 | static irqreturn_t wil6210_hardirq(int irq, void *cookie) | |
422 | { | |
423 | irqreturn_t rc = IRQ_HANDLED; | |
424 | struct wil6210_priv *wil = cookie; | |
425 | u32 pseudo_cause = ioread32(wil->csr + HOSTADDR(RGF_DMA_PSEUDO_CAUSE)); | |
426 | ||
427 | /** | |
428 | * pseudo_cause is Clear-On-Read, no need to ACK | |
429 | */ | |
430 | if ((pseudo_cause == 0) || ((pseudo_cause & 0xff) == 0xff)) | |
431 | return IRQ_NONE; | |
432 | ||
433 | /* FIXME: IRQ mask debug */ | |
434 | if (wil6210_debug_irq_mask(wil, pseudo_cause)) | |
435 | return IRQ_NONE; | |
436 | ||
98658095 | 437 | trace_wil6210_irq_pseudo(pseudo_cause); |
7743882d | 438 | wil_dbg_irq(wil, "Pseudo IRQ 0x%08x\n", pseudo_cause); |
4789d728 | 439 | |
2be7d22f VK |
440 | wil6210_mask_irq_pseudo(wil); |
441 | ||
442 | /* Discover real IRQ cause | |
443 | * There are 2 possible phases for every IRQ: | |
444 | * - hard IRQ handler called right here | |
445 | * - threaded handler called later | |
446 | * | |
447 | * Hard IRQ handler reads and clears ISR. | |
448 | * | |
449 | * If threaded handler requested, hard IRQ handler | |
450 | * returns IRQ_WAKE_THREAD and saves ISR register value | |
451 | * for the threaded handler use. | |
452 | * | |
453 | * voting for wake thread - need at least 1 vote | |
454 | */ | |
455 | if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_RX) && | |
456 | (wil6210_irq_rx(irq, cookie) == IRQ_WAKE_THREAD)) | |
457 | rc = IRQ_WAKE_THREAD; | |
458 | ||
459 | if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_TX) && | |
460 | (wil6210_irq_tx(irq, cookie) == IRQ_WAKE_THREAD)) | |
461 | rc = IRQ_WAKE_THREAD; | |
462 | ||
463 | if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_MISC) && | |
464 | (wil6210_irq_misc(irq, cookie) == IRQ_WAKE_THREAD)) | |
465 | rc = IRQ_WAKE_THREAD; | |
466 | ||
467 | /* if thread is requested, it will unmask IRQ */ | |
468 | if (rc != IRQ_WAKE_THREAD) | |
469 | wil6210_unmask_irq_pseudo(wil); | |
470 | ||
2be7d22f VK |
471 | return rc; |
472 | } | |
473 | ||
474 | static int wil6210_request_3msi(struct wil6210_priv *wil, int irq) | |
475 | { | |
476 | int rc; | |
477 | /* | |
478 | * IRQ's are in the following order: | |
479 | * - Tx | |
480 | * - Rx | |
481 | * - Misc | |
482 | */ | |
483 | ||
484 | rc = request_irq(irq, wil6210_irq_tx, IRQF_SHARED, | |
485 | WIL_NAME"_tx", wil); | |
486 | if (rc) | |
487 | return rc; | |
488 | ||
489 | rc = request_irq(irq + 1, wil6210_irq_rx, IRQF_SHARED, | |
490 | WIL_NAME"_rx", wil); | |
491 | if (rc) | |
492 | goto free0; | |
493 | ||
494 | rc = request_threaded_irq(irq + 2, wil6210_irq_misc, | |
495 | wil6210_irq_misc_thread, | |
496 | IRQF_SHARED, WIL_NAME"_misc", wil); | |
497 | if (rc) | |
498 | goto free1; | |
499 | ||
500 | return 0; | |
501 | /* error branch */ | |
502 | free1: | |
503 | free_irq(irq + 1, wil); | |
504 | free0: | |
505 | free_irq(irq, wil); | |
506 | ||
507 | return rc; | |
508 | } | |
f4b5a803 VK |
509 | /* can't use wil_ioread32_and_clear because ICC value is not ser yet */ |
510 | static inline void wil_clear32(void __iomem *addr) | |
511 | { | |
512 | u32 x = ioread32(addr); | |
513 | ||
514 | iowrite32(x, addr); | |
515 | } | |
516 | ||
517 | void wil6210_clear_irq(struct wil6210_priv *wil) | |
518 | { | |
519 | wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) + | |
520 | offsetof(struct RGF_ICR, ICR)); | |
521 | wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) + | |
522 | offsetof(struct RGF_ICR, ICR)); | |
523 | wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) + | |
524 | offsetof(struct RGF_ICR, ICR)); | |
151a9706 | 525 | wmb(); /* make sure write completed */ |
f4b5a803 | 526 | } |
2be7d22f VK |
527 | |
528 | int wil6210_init_irq(struct wil6210_priv *wil, int irq) | |
529 | { | |
530 | int rc; | |
9cf10d62 VK |
531 | |
532 | wil_dbg_misc(wil, "%s() n_msi=%d\n", __func__, wil->n_msi); | |
533 | ||
2be7d22f VK |
534 | if (wil->n_msi == 3) |
535 | rc = wil6210_request_3msi(wil, irq); | |
536 | else | |
537 | rc = request_threaded_irq(irq, wil6210_hardirq, | |
538 | wil6210_thread_irq, | |
539 | wil->n_msi ? 0 : IRQF_SHARED, | |
540 | WIL_NAME, wil); | |
69778059 | 541 | return rc; |
2be7d22f VK |
542 | } |
543 | ||
544 | void wil6210_fini_irq(struct wil6210_priv *wil, int irq) | |
545 | { | |
9cf10d62 VK |
546 | wil_dbg_misc(wil, "%s()\n", __func__); |
547 | ||
2be7d22f VK |
548 | wil6210_disable_irq(wil); |
549 | free_irq(irq, wil); | |
550 | if (wil->n_msi == 3) { | |
551 | free_irq(irq + 1, wil); | |
552 | free_irq(irq + 2, wil); | |
553 | } | |
554 | } |