[deliverable/linux.git] / drivers / net / wireless / ath / wil6210 / interrupt.c

/*
 * Copyright (c) 2012 Qualcomm Atheros, Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/interrupt.h>

#include "wil6210.h"

/**
 * Theory of operation:
 *
 * There is ISR pseudo-cause register,
 * dma_rgf->DMA_RGF.PSEUDO_CAUSE.PSEUDO_CAUSE
 * Its bits represents OR'ed bits from 3 real ISR registers:
 * TX, RX, and MISC.
 *
 * Registers may be configured to either "write 1 to clear" or
 * "clear on read" mode
 *
 * When handling interrupt, one have to mask/unmask interrupts for the
 * real ISR registers, or hardware may malfunction.
 *
 */

#define WIL6210_IRQ_DISABLE	(0xFFFFFFFFUL)
#define WIL6210_IMC_RX		BIT_DMA_EP_RX_ICR_RX_DONE
#define WIL6210_IMC_TX		(BIT_DMA_EP_TX_ICR_TX_DONE | \
				BIT_DMA_EP_TX_ICR_TX_DONE_N(0))
#define WIL6210_IMC_MISC	(ISR_MISC_FW_READY | \
				 ISR_MISC_MBOX_EVT | \
				 ISR_MISC_FW_ERROR)

#define WIL6210_IRQ_PSEUDO_MASK (u32)(~(BIT_DMA_PSEUDO_CAUSE_RX | \
					BIT_DMA_PSEUDO_CAUSE_TX | \
					BIT_DMA_PSEUDO_CAUSE_MISC))

#if defined(CONFIG_WIL6210_ISR_COR)
/* configure to Clear-On-Read mode */
#define WIL_ICR_ICC_VALUE	(0xFFFFFFFFUL)

static inline void wil_icr_clear(u32 x, void __iomem *addr)
{
}
#else /* defined(CONFIG_WIL6210_ISR_COR) */
/* configure to Write-1-to-Clear mode */
#define WIL_ICR_ICC_VALUE	(0UL)

static inline void wil_icr_clear(u32 x, void __iomem *addr)
{
	iowrite32(x, addr);
}
#endif /* defined(CONFIG_WIL6210_ISR_COR) */

static inline u32 wil_ioread32_and_clear(void __iomem *addr)
{
	u32 x = ioread32(addr);

	wil_icr_clear(x, addr);

	return x;
}

static void wil6210_mask_irq_tx(struct wil6210_priv *wil)
{
	iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
		  HOSTADDR(RGF_DMA_EP_TX_ICR) +
		  offsetof(struct RGF_ICR, IMS));
}

static void wil6210_mask_irq_rx(struct wil6210_priv *wil)
{
	iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
		  HOSTADDR(RGF_DMA_EP_RX_ICR) +
		  offsetof(struct RGF_ICR, IMS));
}

static void wil6210_mask_irq_misc(struct wil6210_priv *wil)
{
	iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
		  HOSTADDR(RGF_DMA_EP_MISC_ICR) +
		  offsetof(struct RGF_ICR, IMS));
}

static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil)
{
	wil_dbg_irq(wil, "%s()\n", __func__);

	iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
		  HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));

	clear_bit(wil_status_irqen, &wil->status);
}

static void wil6210_unmask_irq_tx(struct wil6210_priv *wil)
{
	iowrite32(WIL6210_IMC_TX, wil->csr +
		  HOSTADDR(RGF_DMA_EP_TX_ICR) +
		  offsetof(struct RGF_ICR, IMC));
}

static void wil6210_unmask_irq_rx(struct wil6210_priv *wil)
{
	iowrite32(WIL6210_IMC_RX, wil->csr +
		  HOSTADDR(RGF_DMA_EP_RX_ICR) +
		  offsetof(struct RGF_ICR, IMC));
}

static void wil6210_unmask_irq_misc(struct wil6210_priv *wil)
{
	iowrite32(WIL6210_IMC_MISC, wil->csr +
		  HOSTADDR(RGF_DMA_EP_MISC_ICR) +
		  offsetof(struct RGF_ICR, IMC));
}

static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil)
{
	wil_dbg_irq(wil, "%s()\n", __func__);

	set_bit(wil_status_irqen, &wil->status);

	iowrite32(WIL6210_IRQ_PSEUDO_MASK, wil->csr +
		  HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));
}

void wil6210_disable_irq(struct wil6210_priv *wil)
{
	wil_dbg_irq(wil, "%s()\n", __func__);

	wil6210_mask_irq_tx(wil);
	wil6210_mask_irq_rx(wil);
	wil6210_mask_irq_misc(wil);
	wil6210_mask_irq_pseudo(wil);
}

void wil6210_enable_irq(struct wil6210_priv *wil)
{
	wil_dbg_irq(wil, "%s()\n", __func__);

	iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) +
		  offsetof(struct RGF_ICR, ICC));
	iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) +
		  offsetof(struct RGF_ICR, ICC));
	iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) +
		  offsetof(struct RGF_ICR, ICC));

	wil6210_unmask_irq_pseudo(wil);
	wil6210_unmask_irq_tx(wil);
	wil6210_unmask_irq_rx(wil);
	wil6210_unmask_irq_misc(wil);
}

static irqreturn_t wil6210_irq_rx(int irq, void *cookie)
{
	struct wil6210_priv *wil = cookie;
	u32 isr = wil_ioread32_and_clear(wil->csr +
					 HOSTADDR(RGF_DMA_EP_RX_ICR) +
					 offsetof(struct RGF_ICR, ICR));

	wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr);

	if (!isr) {
		wil_err(wil, "spurious IRQ: RX\n");
		return IRQ_NONE;
	}

	wil6210_mask_irq_rx(wil);

	if (isr & BIT_DMA_EP_RX_ICR_RX_DONE) {
		wil_dbg_irq(wil, "RX done\n");
		isr &= ~BIT_DMA_EP_RX_ICR_RX_DONE;
		wil_rx_handle(wil);
	}

	if (isr)
		wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr);

	wil6210_unmask_irq_rx(wil);

	return IRQ_HANDLED;
}

static irqreturn_t wil6210_irq_tx(int irq, void *cookie)
{
	struct wil6210_priv *wil = cookie;
	u32 isr = wil_ioread32_and_clear(wil->csr +
					 HOSTADDR(RGF_DMA_EP_TX_ICR) +
					 offsetof(struct RGF_ICR, ICR));

	wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr);

	if (!isr) {
		wil_err(wil, "spurious IRQ: TX\n");
		return IRQ_NONE;
	}

	wil6210_mask_irq_tx(wil);

	if (isr & BIT_DMA_EP_TX_ICR_TX_DONE) {
		uint i;
		wil_dbg_irq(wil, "TX done\n");
		isr &= ~BIT_DMA_EP_TX_ICR_TX_DONE;
		for (i = 0; i < 24; i++) {
			u32 mask = BIT_DMA_EP_TX_ICR_TX_DONE_N(i);
			if (isr & mask) {
				isr &= ~mask;
				wil_dbg_irq(wil, "TX done(%i)\n", i);
				wil_tx_complete(wil, i);
			}
		}
	}

	if (isr)
		wil_err(wil, "un-handled TX ISR bits 0x%08x\n", isr);

	wil6210_unmask_irq_tx(wil);

	return IRQ_HANDLED;
}

static void wil_notify_fw_error(struct wil6210_priv *wil)
{
	struct device *dev = &wil_to_ndev(wil)->dev;
	char *envp[3] = {
		[0] = "SOURCE=wil6210",
		[1] = "EVENT=FW_ERROR",
		[2] = NULL,
	};
	kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, envp);
}

static irqreturn_t wil6210_irq_misc(int irq, void *cookie)
{
	struct wil6210_priv *wil = cookie;
	u32 isr = wil_ioread32_and_clear(wil->csr +
					 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
					 offsetof(struct RGF_ICR, ICR));

	wil_dbg_irq(wil, "ISR MISC 0x%08x\n", isr);

	if (!isr) {
		wil_err(wil, "spurious IRQ: MISC\n");
		return IRQ_NONE;
	}

	wil6210_mask_irq_misc(wil);

	if (isr & ISR_MISC_FW_ERROR) {
		wil_dbg_irq(wil, "IRQ: Firmware error\n");
		clear_bit(wil_status_fwready, &wil->status);
		wil_notify_fw_error(wil);
		isr &= ~ISR_MISC_FW_ERROR;
	}

	if (isr & ISR_MISC_FW_READY) {
		wil_dbg_irq(wil, "IRQ: FW ready\n");
		/**
		 * Actual FW ready indicated by the
		 * WMI_FW_READY_EVENTID
		 */
		isr &= ~ISR_MISC_FW_READY;
	}

	wil->isr_misc = isr;

	if (isr) {
		return IRQ_WAKE_THREAD;
	} else {
		wil6210_unmask_irq_misc(wil);
		return IRQ_HANDLED;
	}
}

static irqreturn_t wil6210_irq_misc_thread(int irq, void *cookie)
{
	struct wil6210_priv *wil = cookie;
	u32 isr = wil->isr_misc;

	wil_dbg_irq(wil, "Thread ISR MISC 0x%08x\n", isr);

	if (isr & ISR_MISC_MBOX_EVT) {
		wil_dbg_irq(wil, "MBOX event\n");
		wmi_recv_cmd(wil);
		isr &= ~ISR_MISC_MBOX_EVT;
	}

	if (isr)
		wil_err(wil, "un-handled MISC ISR bits 0x%08x\n", isr);

	wil->isr_misc = 0;

	wil6210_unmask_irq_misc(wil);

	return IRQ_HANDLED;
}

/**
 * thread IRQ handler
 */
static irqreturn_t wil6210_thread_irq(int irq, void *cookie)
{
	struct wil6210_priv *wil = cookie;

	wil_dbg_irq(wil, "Thread IRQ\n");
	/* Discover real IRQ cause */
	if (wil->isr_misc)
		wil6210_irq_misc_thread(irq, cookie);

	wil6210_unmask_irq_pseudo(wil);

	return IRQ_HANDLED;
}

/* DEBUG
 * There is subtle bug in hardware that causes IRQ to raise when it should be
 * masked. It is quite rare and hard to debug.
 *
 * Catch irq issue if it happens and print all I can.
 */
static int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause)
{
	if (!test_bit(wil_status_irqen, &wil->status)) {
		u32 icm_rx = wil_ioread32_and_clear(wil->csr +
				HOSTADDR(RGF_DMA_EP_RX_ICR) +
				offsetof(struct RGF_ICR, ICM));
		u32 icr_rx = wil_ioread32_and_clear(wil->csr +
				HOSTADDR(RGF_DMA_EP_RX_ICR) +
				offsetof(struct RGF_ICR, ICR));
		u32 imv_rx = ioread32(wil->csr +
				HOSTADDR(RGF_DMA_EP_RX_ICR) +
				offsetof(struct RGF_ICR, IMV));
		u32 icm_tx = wil_ioread32_and_clear(wil->csr +
				HOSTADDR(RGF_DMA_EP_TX_ICR) +
				offsetof(struct RGF_ICR, ICM));
		u32 icr_tx = wil_ioread32_and_clear(wil->csr +
				HOSTADDR(RGF_DMA_EP_TX_ICR) +
				offsetof(struct RGF_ICR, ICR));
		u32 imv_tx = ioread32(wil->csr +
				HOSTADDR(RGF_DMA_EP_TX_ICR) +
				offsetof(struct RGF_ICR, IMV));
		u32 icm_misc = wil_ioread32_and_clear(wil->csr +
				HOSTADDR(RGF_DMA_EP_MISC_ICR) +
				offsetof(struct RGF_ICR, ICM));
		u32 icr_misc = wil_ioread32_and_clear(wil->csr +
				HOSTADDR(RGF_DMA_EP_MISC_ICR) +
				offsetof(struct RGF_ICR, ICR));
		u32 imv_misc = ioread32(wil->csr +
				HOSTADDR(RGF_DMA_EP_MISC_ICR) +
				offsetof(struct RGF_ICR, IMV));
		wil_err(wil, "IRQ when it should be masked: pseudo 0x%08x\n"
				"Rx   icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
				"Tx   icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
				"Misc icm:icr:imv 0x%08x 0x%08x 0x%08x\n",
				pseudo_cause,
				icm_rx, icr_rx, imv_rx,
				icm_tx, icr_tx, imv_tx,
				icm_misc, icr_misc, imv_misc);

		return -EINVAL;
	}

	return 0;
}

static irqreturn_t wil6210_hardirq(int irq, void *cookie)
{
	irqreturn_t rc = IRQ_HANDLED;
	struct wil6210_priv *wil = cookie;
	u32 pseudo_cause = ioread32(wil->csr + HOSTADDR(RGF_DMA_PSEUDO_CAUSE));

	/**
	 * pseudo_cause is Clear-On-Read, no need to ACK
	 */
	if ((pseudo_cause == 0) || ((pseudo_cause & 0xff) == 0xff))
		return IRQ_NONE;

	/* FIXME: IRQ mask debug */
	if (wil6210_debug_irq_mask(wil, pseudo_cause))
		return IRQ_NONE;

	wil_dbg_irq(wil, "Pseudo IRQ 0x%08x\n", pseudo_cause);

	wil6210_mask_irq_pseudo(wil);

	/* Discover real IRQ cause
	 * There are 2 possible phases for every IRQ:
	 * - hard IRQ handler called right here
	 * - threaded handler called later
	 *
	 * Hard IRQ handler reads and clears ISR.
	 *
	 * If threaded handler requested, hard IRQ handler
	 * returns IRQ_WAKE_THREAD and saves ISR register value
	 * for the threaded handler use.
	 *
	 * voting for wake thread - need at least 1 vote
	 */
	if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_RX) &&
	    (wil6210_irq_rx(irq, cookie) == IRQ_WAKE_THREAD))
		rc = IRQ_WAKE_THREAD;

	if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_TX) &&
	    (wil6210_irq_tx(irq, cookie) == IRQ_WAKE_THREAD))
		rc = IRQ_WAKE_THREAD;

	if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_MISC) &&
	    (wil6210_irq_misc(irq, cookie) == IRQ_WAKE_THREAD))
		rc = IRQ_WAKE_THREAD;

	/* if thread is requested, it will unmask IRQ */
	if (rc != IRQ_WAKE_THREAD)
		wil6210_unmask_irq_pseudo(wil);

	return rc;
}

static int wil6210_request_3msi(struct wil6210_priv *wil, int irq)
{
	int rc;
	/*
	 * IRQ's are in the following order:
	 * - Tx
	 * - Rx
	 * - Misc
	 */

	rc = request_irq(irq, wil6210_irq_tx, IRQF_SHARED,
			 WIL_NAME"_tx", wil);
	if (rc)
		return rc;

	rc = request_irq(irq + 1, wil6210_irq_rx, IRQF_SHARED,
			 WIL_NAME"_rx", wil);
	if (rc)
		goto free0;

	rc = request_threaded_irq(irq + 2, wil6210_irq_misc,
				  wil6210_irq_misc_thread,
				  IRQF_SHARED, WIL_NAME"_misc", wil);
	if (rc)
		goto free1;

	return 0;
	/* error branch */
free1:
	free_irq(irq + 1, wil);
free0:
	free_irq(irq, wil);

	return rc;
}

int wil6210_init_irq(struct wil6210_priv *wil, int irq)
{
	int rc;
	if (wil->n_msi == 3)
		rc = wil6210_request_3msi(wil, irq);
	else
		rc = request_threaded_irq(irq, wil6210_hardirq,
					  wil6210_thread_irq,
					  wil->n_msi ? 0 : IRQF_SHARED,
					  WIL_NAME, wil);
	if (rc)
		return rc;

	wil6210_enable_irq(wil);

	return 0;
}

void wil6210_fini_irq(struct wil6210_priv *wil, int irq)
{
	wil6210_disable_irq(wil);
	free_irq(irq, wil);
	if (wil->n_msi == 3) {
		free_irq(irq + 1, wil);
		free_irq(irq + 2, wil);
	}
}
Commit	Line	Data
2be7d22f VK	1	/*
	2	* Copyright (c) 2012 Qualcomm Atheros, Inc.
	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#include <linux/interrupt.h>
	18
	19	#include "wil6210.h"
	20
	21	/**
	22	* Theory of operation:
	23	*
	24	* There is ISR pseudo-cause register,
	25	* dma_rgf->DMA_RGF.PSEUDO_CAUSE.PSEUDO_CAUSE
	26	* Its bits represents OR'ed bits from 3 real ISR registers:
	27	* TX, RX, and MISC.
	28	*
	29	* Registers may be configured to either "write 1 to clear" or
	30	* "clear on read" mode
	31	*
	32	* When handling interrupt, one have to mask/unmask interrupts for the
	33	* real ISR registers, or hardware may malfunction.
	34	*
	35	*/
	36
	37	#define WIL6210_IRQ_DISABLE (0xFFFFFFFFUL)
	38	#define WIL6210_IMC_RX BIT_DMA_EP_RX_ICR_RX_DONE
	39	#define WIL6210_IMC_TX (BIT_DMA_EP_TX_ICR_TX_DONE \| \
	40	BIT_DMA_EP_TX_ICR_TX_DONE_N(0))
7269494e VK	41	#define WIL6210_IMC_MISC (ISR_MISC_FW_READY \| \
	42	ISR_MISC_MBOX_EVT \| \
	43	ISR_MISC_FW_ERROR)
2be7d22f VK	44
	45	#define WIL6210_IRQ_PSEUDO_MASK (u32)(~(BIT_DMA_PSEUDO_CAUSE_RX \| \
	46	BIT_DMA_PSEUDO_CAUSE_TX \| \
	47	BIT_DMA_PSEUDO_CAUSE_MISC))
	48
	49	#if defined(CONFIG_WIL6210_ISR_COR)
	50	/* configure to Clear-On-Read mode */
	51	#define WIL_ICR_ICC_VALUE (0xFFFFFFFFUL)
	52
	53	static inline void wil_icr_clear(u32 x, void __iomem *addr)
	54	{
2be7d22f VK	55	}
	56	#else /* defined(CONFIG_WIL6210_ISR_COR) */
	57	/* configure to Write-1-to-Clear mode */
	58	#define WIL_ICR_ICC_VALUE (0UL)
	59
	60	static inline void wil_icr_clear(u32 x, void __iomem *addr)
	61	{
	62	iowrite32(x, addr);
	63	}
	64	#endif /* defined(CONFIG_WIL6210_ISR_COR) */
	65
	66	static inline u32 wil_ioread32_and_clear(void __iomem *addr)
	67	{
	68	u32 x = ioread32(addr);
	69
	70	wil_icr_clear(x, addr);
	71
	72	return x;
	73	}
	74
	75	static void wil6210_mask_irq_tx(struct wil6210_priv *wil)
	76	{
	77	iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
	78	HOSTADDR(RGF_DMA_EP_TX_ICR) +
	79	offsetof(struct RGF_ICR, IMS));
	80	}
	81
	82	static void wil6210_mask_irq_rx(struct wil6210_priv *wil)
	83	{
	84	iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
	85	HOSTADDR(RGF_DMA_EP_RX_ICR) +
	86	offsetof(struct RGF_ICR, IMS));
	87	}
	88
	89	static void wil6210_mask_irq_misc(struct wil6210_priv *wil)
	90	{
	91	iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
	92	HOSTADDR(RGF_DMA_EP_MISC_ICR) +
	93	offsetof(struct RGF_ICR, IMS));
	94	}
	95
	96	static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil)
	97	{
7743882d	98	wil_dbg_irq(wil, "%s()\n", __func__);
2be7d22f VK	99
	100	iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
	101	HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));
	102
	103	clear_bit(wil_status_irqen, &wil->status);
	104	}
	105
	106	static void wil6210_unmask_irq_tx(struct wil6210_priv *wil)
	107	{
	108	iowrite32(WIL6210_IMC_TX, wil->csr +
	109	HOSTADDR(RGF_DMA_EP_TX_ICR) +
	110	offsetof(struct RGF_ICR, IMC));
	111	}
	112
	113	static void wil6210_unmask_irq_rx(struct wil6210_priv *wil)
	114	{
	115	iowrite32(WIL6210_IMC_RX, wil->csr +
	116	HOSTADDR(RGF_DMA_EP_RX_ICR) +
	117	offsetof(struct RGF_ICR, IMC));
	118	}
	119
	120	static void wil6210_unmask_irq_misc(struct wil6210_priv *wil)
	121	{
	122	iowrite32(WIL6210_IMC_MISC, wil->csr +
	123	HOSTADDR(RGF_DMA_EP_MISC_ICR) +
	124	offsetof(struct RGF_ICR, IMC));
	125	}
	126
	127	static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil)
	128	{
7743882d	129	wil_dbg_irq(wil, "%s()\n", __func__);
2be7d22f VK	130
	131	set_bit(wil_status_irqen, &wil->status);
	132
	133	iowrite32(WIL6210_IRQ_PSEUDO_MASK, wil->csr +
	134	HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));
	135	}
	136
	137	void wil6210_disable_irq(struct wil6210_priv *wil)
	138	{
7743882d	139	wil_dbg_irq(wil, "%s()\n", __func__);
2be7d22f VK	140
	141	wil6210_mask_irq_tx(wil);
	142	wil6210_mask_irq_rx(wil);
	143	wil6210_mask_irq_misc(wil);
	144	wil6210_mask_irq_pseudo(wil);
	145	}
	146
	147	void wil6210_enable_irq(struct wil6210_priv *wil)
	148	{
7743882d	149	wil_dbg_irq(wil, "%s()\n", __func__);
2be7d22f VK	150
	151	iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) +
	152	offsetof(struct RGF_ICR, ICC));
	153	iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) +
	154	offsetof(struct RGF_ICR, ICC));
	155	iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) +
	156	offsetof(struct RGF_ICR, ICC));
	157
	158	wil6210_unmask_irq_pseudo(wil);
	159	wil6210_unmask_irq_tx(wil);
	160	wil6210_unmask_irq_rx(wil);
	161	wil6210_unmask_irq_misc(wil);
	162	}
	163
	164	static irqreturn_t wil6210_irq_rx(int irq, void *cookie)
	165	{
	166	struct wil6210_priv *wil = cookie;
	167	u32 isr = wil_ioread32_and_clear(wil->csr +
	168	HOSTADDR(RGF_DMA_EP_RX_ICR) +
	169	offsetof(struct RGF_ICR, ICR));
	170
7743882d	171	wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr);
2be7d22f VK	172
	173	if (!isr) {
	174	wil_err(wil, "spurious IRQ: RX\n");
	175	return IRQ_NONE;
	176	}
	177
	178	wil6210_mask_irq_rx(wil);
	179
	180	if (isr & BIT_DMA_EP_RX_ICR_RX_DONE) {
7743882d	181	wil_dbg_irq(wil, "RX done\n");
2be7d22f VK	182	isr &= ~BIT_DMA_EP_RX_ICR_RX_DONE;
	183	wil_rx_handle(wil);
	184	}
	185
	186	if (isr)
	187	wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr);
	188
	189	wil6210_unmask_irq_rx(wil);
	190
	191	return IRQ_HANDLED;
	192	}
	193
	194	static irqreturn_t wil6210_irq_tx(int irq, void *cookie)
	195	{
	196	struct wil6210_priv *wil = cookie;
	197	u32 isr = wil_ioread32_and_clear(wil->csr +
	198	HOSTADDR(RGF_DMA_EP_TX_ICR) +
	199	offsetof(struct RGF_ICR, ICR));
	200
7743882d	201	wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr);
2be7d22f VK	202
	203	if (!isr) {
	204	wil_err(wil, "spurious IRQ: TX\n");
	205	return IRQ_NONE;
	206	}
	207
	208	wil6210_mask_irq_tx(wil);
	209
	210	if (isr & BIT_DMA_EP_TX_ICR_TX_DONE) {
	211	uint i;
7743882d	212	wil_dbg_irq(wil, "TX done\n");
2be7d22f VK	213	isr &= ~BIT_DMA_EP_TX_ICR_TX_DONE;
	214	for (i = 0; i < 24; i++) {
	215	u32 mask = BIT_DMA_EP_TX_ICR_TX_DONE_N(i);
	216	if (isr & mask) {
	217	isr &= ~mask;
7743882d	218	wil_dbg_irq(wil, "TX done(%i)\n", i);
2be7d22f VK	219	wil_tx_complete(wil, i);
	220	}
	221	}
	222	}
	223
	224	if (isr)
	225	wil_err(wil, "un-handled TX ISR bits 0x%08x\n", isr);
	226
	227	wil6210_unmask_irq_tx(wil);
	228
	229	return IRQ_HANDLED;
	230	}
	231
7269494e VK	232	static void wil_notify_fw_error(struct wil6210_priv *wil)
	233	{
	234	struct device *dev = &wil_to_ndev(wil)->dev;
	235	char *envp[3] = {
	236	[0] = "SOURCE=wil6210",
	237	[1] = "EVENT=FW_ERROR",
	238	[2] = NULL,
	239	};
	240	kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, envp);
	241	}
	242
2be7d22f VK	243	static irqreturn_t wil6210_irq_misc(int irq, void *cookie)
	244	{
	245	struct wil6210_priv *wil = cookie;
	246	u32 isr = wil_ioread32_and_clear(wil->csr +
	247	HOSTADDR(RGF_DMA_EP_MISC_ICR) +
	248	offsetof(struct RGF_ICR, ICR));
	249
7743882d	250	wil_dbg_irq(wil, "ISR MISC 0x%08x\n", isr);
2be7d22f VK	251
	252	if (!isr) {
	253	wil_err(wil, "spurious IRQ: MISC\n");
	254	return IRQ_NONE;
	255	}
	256
	257	wil6210_mask_irq_misc(wil);
	258
7269494e	259	if (isr & ISR_MISC_FW_ERROR) {
7743882d	260	wil_dbg_irq(wil, "IRQ: Firmware error\n");
7269494e VK	261	clear_bit(wil_status_fwready, &wil->status);
	262	wil_notify_fw_error(wil);
	263	isr &= ~ISR_MISC_FW_ERROR;
	264	}
	265
2be7d22f	266	if (isr & ISR_MISC_FW_READY) {
7743882d	267	wil_dbg_irq(wil, "IRQ: FW ready\n");
2be7d22f VK	268	/**
	269	* Actual FW ready indicated by the
	270	* WMI_FW_READY_EVENTID
	271	*/
	272	isr &= ~ISR_MISC_FW_READY;
	273	}
	274
	275	wil->isr_misc = isr;
	276
	277	if (isr) {
	278	return IRQ_WAKE_THREAD;
	279	} else {
	280	wil6210_unmask_irq_misc(wil);
	281	return IRQ_HANDLED;
	282	}
	283	}
	284
	285	static irqreturn_t wil6210_irq_misc_thread(int irq, void *cookie)
	286	{
	287	struct wil6210_priv *wil = cookie;
	288	u32 isr = wil->isr_misc;
	289
7743882d	290	wil_dbg_irq(wil, "Thread ISR MISC 0x%08x\n", isr);
2be7d22f VK	291
2be7d22f VK	292	if (isr & ISR_MISC_MBOX_EVT) {
7743882d	293	wil_dbg_irq(wil, "MBOX event\n");
2be7d22f VK	294	wmi_recv_cmd(wil);
	295	isr &= ~ISR_MISC_MBOX_EVT;
	296	}
	297
	298	if (isr)
	299	wil_err(wil, "un-handled MISC ISR bits 0x%08x\n", isr);
	300
	301	wil->isr_misc = 0;
	302
	303	wil6210_unmask_irq_misc(wil);
	304
	305	return IRQ_HANDLED;
	306	}
	307
	308	/**
	309	* thread IRQ handler
	310	*/
	311	static irqreturn_t wil6210_thread_irq(int irq, void *cookie)
	312	{
	313	struct wil6210_priv *wil = cookie;
	314
7743882d	315	wil_dbg_irq(wil, "Thread IRQ\n");
2be7d22f VK	316	/* Discover real IRQ cause */
	317	if (wil->isr_misc)
	318	wil6210_irq_misc_thread(irq, cookie);
	319
	320	wil6210_unmask_irq_pseudo(wil);
	321
	322	return IRQ_HANDLED;
	323	}
	324
	325	/* DEBUG
	326	* There is subtle bug in hardware that causes IRQ to raise when it should be
	327	* masked. It is quite rare and hard to debug.
	328	*
	329	* Catch irq issue if it happens and print all I can.
	330	*/
	331	static int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause)
	332	{
	333	if (!test_bit(wil_status_irqen, &wil->status)) {
	334	u32 icm_rx = wil_ioread32_and_clear(wil->csr +
	335	HOSTADDR(RGF_DMA_EP_RX_ICR) +
	336	offsetof(struct RGF_ICR, ICM));
	337	u32 icr_rx = wil_ioread32_and_clear(wil->csr +
	338	HOSTADDR(RGF_DMA_EP_RX_ICR) +
	339	offsetof(struct RGF_ICR, ICR));
	340	u32 imv_rx = ioread32(wil->csr +
	341	HOSTADDR(RGF_DMA_EP_RX_ICR) +
	342	offsetof(struct RGF_ICR, IMV));
	343	u32 icm_tx = wil_ioread32_and_clear(wil->csr +
	344	HOSTADDR(RGF_DMA_EP_TX_ICR) +
	345	offsetof(struct RGF_ICR, ICM));
	346	u32 icr_tx = wil_ioread32_and_clear(wil->csr +
	347	HOSTADDR(RGF_DMA_EP_TX_ICR) +
	348	offsetof(struct RGF_ICR, ICR));
	349	u32 imv_tx = ioread32(wil->csr +
	350	HOSTADDR(RGF_DMA_EP_TX_ICR) +
	351	offsetof(struct RGF_ICR, IMV));
	352	u32 icm_misc = wil_ioread32_and_clear(wil->csr +
	353	HOSTADDR(RGF_DMA_EP_MISC_ICR) +
	354	offsetof(struct RGF_ICR, ICM));
	355	u32 icr_misc = wil_ioread32_and_clear(wil->csr +
	356	HOSTADDR(RGF_DMA_EP_MISC_ICR) +
	357	offsetof(struct RGF_ICR, ICR));
	358	u32 imv_misc = ioread32(wil->csr +
	359	HOSTADDR(RGF_DMA_EP_MISC_ICR) +
	360	offsetof(struct RGF_ICR, IMV));
	361	wil_err(wil, "IRQ when it should be masked: pseudo 0x%08x\n"
	362	"Rx icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
	363	"Tx icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
	364	"Misc icm:icr:imv 0x%08x 0x%08x 0x%08x\n",
	365	pseudo_cause,
	366	icm_rx, icr_rx, imv_rx,
	367	icm_tx, icr_tx, imv_tx,
	368	icm_misc, icr_misc, imv_misc);
	369
	370	return -EINVAL;
	371	}
	372
	373	return 0;
	374	}
	375
	376	static irqreturn_t wil6210_hardirq(int irq, void *cookie)
	377	{
	378	irqreturn_t rc = IRQ_HANDLED;
	379	struct wil6210_priv *wil = cookie;
380	u32 pseudo_cause = ioread32(wil->csr + HOSTADDR(RGF_DMA_PSEUDO_CAUSE));
381
382	/**
383	* pseudo_cause is Clear-On-Read, no need to ACK
384	*/
385	if ((pseudo_cause == 0) \|\| ((pseudo_cause & 0xff) == 0xff))
386	return IRQ_NONE;
387
388	/* FIXME: IRQ mask debug */
389	if (wil6210_debug_irq_mask(wil, pseudo_cause))
390	return IRQ_NONE;
391
7743882d	392	wil_dbg_irq(wil, "Pseudo IRQ 0x%08x\n", pseudo_cause);
4789d728	393
2be7d22f VK	394	wil6210_mask_irq_pseudo(wil);
	395
	396	/* Discover real IRQ cause
	397	* There are 2 possible phases for every IRQ:
	398	* - hard IRQ handler called right here
	399	* - threaded handler called later
	400	*
	401	* Hard IRQ handler reads and clears ISR.
	402	*
	403	* If threaded handler requested, hard IRQ handler
	404	* returns IRQ_WAKE_THREAD and saves ISR register value
	405	* for the threaded handler use.
	406	*
	407	* voting for wake thread - need at least 1 vote
	408	*/
	409	if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_RX) &&
	410	(wil6210_irq_rx(irq, cookie) == IRQ_WAKE_THREAD))
	411	rc = IRQ_WAKE_THREAD;
	412
	413	if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_TX) &&
	414	(wil6210_irq_tx(irq, cookie) == IRQ_WAKE_THREAD))
	415	rc = IRQ_WAKE_THREAD;
	416
	417	if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_MISC) &&
	418	(wil6210_irq_misc(irq, cookie) == IRQ_WAKE_THREAD))
	419	rc = IRQ_WAKE_THREAD;
	420
	421	/* if thread is requested, it will unmask IRQ */
	422	if (rc != IRQ_WAKE_THREAD)
	423	wil6210_unmask_irq_pseudo(wil);
	424
2be7d22f VK	425	return rc;
	426	}
	427
	428	static int wil6210_request_3msi(struct wil6210_priv *wil, int irq)
	429	{
	430	int rc;
	431	/*
	432	* IRQ's are in the following order:
	433	* - Tx
	434	* - Rx
	435	* - Misc
	436	*/
	437
	438	rc = request_irq(irq, wil6210_irq_tx, IRQF_SHARED,
	439	WIL_NAME"_tx", wil);
	440	if (rc)
	441	return rc;
	442
	443	rc = request_irq(irq + 1, wil6210_irq_rx, IRQF_SHARED,
	444	WIL_NAME"_rx", wil);
	445	if (rc)
	446	goto free0;
	447
	448	rc = request_threaded_irq(irq + 2, wil6210_irq_misc,
	449	wil6210_irq_misc_thread,
	450	IRQF_SHARED, WIL_NAME"_misc", wil);
	451	if (rc)
	452	goto free1;
	453
	454	return 0;
	455	/* error branch */
	456	free1:
	457	free_irq(irq + 1, wil);
	458	free0:
	459	free_irq(irq, wil);
	460
	461	return rc;
	462	}
	463
	464	int wil6210_init_irq(struct wil6210_priv *wil, int irq)
	465	{
	466	int rc;
	467	if (wil->n_msi == 3)
	468	rc = wil6210_request_3msi(wil, irq);
	469	else
	470	rc = request_threaded_irq(irq, wil6210_hardirq,
	471	wil6210_thread_irq,
	472	wil->n_msi ? 0 : IRQF_SHARED,
	473	WIL_NAME, wil);
	474	if (rc)
	475	return rc;
	476
	477	wil6210_enable_irq(wil);
	478
	479	return 0;
	480	}
	481
	482	void wil6210_fini_irq(struct wil6210_priv *wil, int irq)
	483	{
	484	wil6210_disable_irq(wil);
	485	free_irq(irq, wil);
	486	if (wil->n_msi == 3) {
	487	free_irq(irq + 1, wil);
	488	free_irq(irq + 2, wil);
489	}
490	}