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ath5k: PHY code cleanup
[deliverable/linux.git] / drivers / net / wireless / ath5k / ath5k.h
CommitLineData
fa1c114f
JS		 1/*
2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#ifndef _ATH5K_H
19#define _ATH5K_H
20
c6e387a2
NK		 21/* TODO: Clean up channel debuging -doesn't work anyway- and start
22 * working on reg. control code using all available eeprom information
23 * -rev. engineering needed- */
fa1c114f
JS		 24#define CHAN_DEBUG 0
25
26#include <linux/io.h>
27#include <linux/types.h>
28#include <net/mac80211.h>
29
c6e387a2
NK		 30/* RX/TX descriptor hw structs
31 * TODO: Driver part should only see sw structs */
32#include "desc.h"
33
34/* EEPROM structs/offsets
35 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities)
36 * and clean up common bits, then introduce set/get functions in eeprom.c */
37#include "eeprom.h"
fa1c114f
JS		 38
39/* PCI IDs */
40#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */
41#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */
42#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */
43#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */
44#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */
45#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */
46#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */
47#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */
48#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */
49#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */
50#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */
51#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */
52#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */
53#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */
54#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
55#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
56#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */
57#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */
58#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */
59#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */
60#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */
61#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */
62#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */
63#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */
64#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */
65#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */
66#define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */
67#define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */
68
69/****************************\
70 GENERIC DRIVER DEFINITIONS
71\****************************/
72
73#define ATH5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__)
74
75#define ATH5K_PRINTK(_sc, _level, _fmt, ...) \
76 printk(_level "ath5k %s: " _fmt, \
77 ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \
78 ##__VA_ARGS__)
79
80#define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \
81 if (net_ratelimit()) \
82 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \
83 } while (0)
84
85#define ATH5K_INFO(_sc, _fmt, ...) \
86 ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__)
87
88#define ATH5K_WARN(_sc, _fmt, ...) \
89 ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__)
90
91#define ATH5K_ERR(_sc, _fmt, ...) \
92 ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__)
93
c6e387a2
NK		 94/*
95 * AR5K REGISTER ACCESS
96 */
97
98/* Some macros to read/write fields */
99
100/* First shift, then mask */
101#define AR5K_REG_SM(_val, _flags) \
102 (((_val) << _flags##_S) & (_flags))
103
104/* First mask, then shift */
105#define AR5K_REG_MS(_val, _flags) \
106 (((_val) & (_flags)) >> _flags##_S)
107
108/* Some registers can hold multiple values of interest. For this
109 * reason when we want to write to these registers we must first
110 * retrieve the values which we do not want to clear (lets call this
111 * old_data) and then set the register with this and our new_value:
112 * ( old_data | new_value) */
113#define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \
114 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
115 (((_val) << _flags##_S) & (_flags)), _reg)
116
117#define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \
118 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \
119 (_mask)) | (_flags), _reg)
120
121#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \
122 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
123
124#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \
125 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
126
127/* Access to PHY registers */
128#define AR5K_PHY_READ(ah, _reg) \
129 ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2))
130
131#define AR5K_PHY_WRITE(ah, _reg, _val) \
132 ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2))
133
134/* Access QCU registers per queue */
135#define AR5K_REG_READ_Q(ah, _reg, _queue) \
136 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \
137
138#define AR5K_REG_WRITE_Q(ah, _reg, _queue) \
139 ath5k_hw_reg_write(ah, (1 << _queue), _reg)
140
141#define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \
142 _reg |= 1 << _queue; \
143} while (0)
144
145#define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \
146 _reg &= ~(1 << _queue); \
147} while (0)
148
149/* Used while writing initvals */
150#define AR5K_REG_WAIT(_i) do { \
151 if (_i % 64) \
152 udelay(1); \
153} while (0)
154
155/* Register dumps are done per operation mode */
156#define AR5K_INI_RFGAIN_5GHZ 0
157#define AR5K_INI_RFGAIN_2GHZ 1
158
159/* TODO: Clean this up */
160#define AR5K_INI_VAL_11A 0
161#define AR5K_INI_VAL_11A_TURBO 1
162#define AR5K_INI_VAL_11B 2
163#define AR5K_INI_VAL_11G 3
164#define AR5K_INI_VAL_11G_TURBO 4
165#define AR5K_INI_VAL_XR 0
166#define AR5K_INI_VAL_MAX 5
167
168#define AR5K_RF5111_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS
169#define AR5K_RF5112_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS
170
171/* Used for BSSID etc manipulation */
172#define AR5K_LOW_ID(_a)( \
173(_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24 \
174)
175
176#define AR5K_HIGH_ID(_a) ((_a)[4] | (_a)[5] << 8)
177
fa1c114f
JS		 178/*
179 * Some tuneable values (these should be changeable by the user)
c6e387a2 180 * TODO: Make use of them and add more options OR use debug/configfs
fa1c114f
JS		 181 */
182#define AR5K_TUNE_DMA_BEACON_RESP 2
183#define AR5K_TUNE_SW_BEACON_RESP 10
184#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0
185#define AR5K_TUNE_RADAR_ALERT false
186#define AR5K_TUNE_MIN_TX_FIFO_THRES 1
187#define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_LEN / 64) + 1)
188#define AR5K_TUNE_REGISTER_TIMEOUT 20000
189/* Register for RSSI threshold has a mask of 0xff, so 255 seems to
190 * be the max value. */
c6e387a2 191#define AR5K_TUNE_RSSI_THRES 129
fa1c114f
JS		 192/* This must be set when setting the RSSI threshold otherwise it can
193 * prevent a reset. If AR5K_RSSI_THR is read after writing to it
194 * the BMISS_THRES will be seen as 0, seems harware doesn't keep
195 * track of it. Max value depends on harware. For AR5210 this is just 7.
196 * For AR5211+ this seems to be up to 255. */
c6e387a2 197#define AR5K_TUNE_BMISS_THRES 7
fa1c114f
JS		 198#define AR5K_TUNE_REGISTER_DWELL_TIME 20000
199#define AR5K_TUNE_BEACON_INTERVAL 100
200#define AR5K_TUNE_AIFS 2
201#define AR5K_TUNE_AIFS_11B 2
202#define AR5K_TUNE_AIFS_XR 0
203#define AR5K_TUNE_CWMIN 15
204#define AR5K_TUNE_CWMIN_11B 31
205#define AR5K_TUNE_CWMIN_XR 3
206#define AR5K_TUNE_CWMAX 1023
207#define AR5K_TUNE_CWMAX_11B 1023
208#define AR5K_TUNE_CWMAX_XR 7
209#define AR5K_TUNE_NOISE_FLOOR -72
210#define AR5K_TUNE_MAX_TXPOWER 60
211#define AR5K_TUNE_DEFAULT_TXPOWER 30
212#define AR5K_TUNE_TPC_TXPOWER true
213#define AR5K_TUNE_ANT_DIVERSITY true
214#define AR5K_TUNE_HWTXTRIES 4
215
c6e387a2
NK		 216#define AR5K_INIT_CARR_SENSE_EN 1
217
218/*Swap RX/TX Descriptor for big endian archs*/
219#if defined(__BIG_ENDIAN)
220#define AR5K_INIT_CFG ( \
221 AR5K_CFG_SWTD | AR5K_CFG_SWRD \
222)
223#else
224#define AR5K_INIT_CFG 0x00000000
225#endif
226
227/* Initial values */
228#define AR5K_INIT_TX_LATENCY 502
229#define AR5K_INIT_USEC 39
230#define AR5K_INIT_USEC_TURBO 79
231#define AR5K_INIT_USEC_32 31
232#define AR5K_INIT_SLOT_TIME 396
233#define AR5K_INIT_SLOT_TIME_TURBO 480
234#define AR5K_INIT_ACK_CTS_TIMEOUT 1024
235#define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800
236#define AR5K_INIT_PROG_IFS 920
237#define AR5K_INIT_PROG_IFS_TURBO 960
238#define AR5K_INIT_EIFS 3440
239#define AR5K_INIT_EIFS_TURBO 6880
240#define AR5K_INIT_SIFS 560
241#define AR5K_INIT_SIFS_TURBO 480
242#define AR5K_INIT_SH_RETRY 10
243#define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY
244#define AR5K_INIT_SSH_RETRY 32
245#define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY
246#define AR5K_INIT_TX_RETRY 10
247
248#define AR5K_INIT_TRANSMIT_LATENCY ( \
249 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
250 (AR5K_INIT_USEC) \
251)
252#define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \
253 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
254 (AR5K_INIT_USEC_TURBO) \
255)
256#define AR5K_INIT_PROTO_TIME_CNTRL ( \
257 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \
258 (AR5K_INIT_PROG_IFS) \
259)
260#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \
261 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \
262 (AR5K_INIT_PROG_IFS_TURBO) \
263)
264
fa1c114f
JS		 265/* token to use for aifs, cwmin, cwmax in MadWiFi */
266#define AR5K_TXQ_USEDEFAULT ((u32) -1)
267
268/* GENERIC CHIPSET DEFINITIONS */
269
270/* MAC Chips */
271enum ath5k_version {
272 AR5K_AR5210 = 0,
273 AR5K_AR5211 = 1,
274 AR5K_AR5212 = 2,
275};
276
277/* PHY Chips */
278enum ath5k_radio {
279 AR5K_RF5110 = 0,
280 AR5K_RF5111 = 1,
281 AR5K_RF5112 = 2,
8daeef97
NK		 282 AR5K_RF2413 = 3,
283 AR5K_RF5413 = 4,
1bef016a
NK		 284 AR5K_RF2316 = 5,
285 AR5K_RF2317 = 6,
286 AR5K_RF2425 = 7,
fa1c114f
JS		 287};
288
289/*
290 * Common silicon revision/version values
291 */
292
293enum ath5k_srev_type {
1bef016a 294 AR5K_VERSION_MAC,
fa1c114f
JS		 295 AR5K_VERSION_RAD,
296};
297
298struct ath5k_srev_name {
299 const char *sr_name;
300 enum ath5k_srev_type sr_type;
301 u_int sr_val;
302};
303
304#define AR5K_SREV_UNKNOWN 0xffff
305
1bef016a
NK		 306#define AR5K_SREV_AR5210 0x00 /* Crete */
307#define AR5K_SREV_AR5311 0x10 /* Maui 1 */
308#define AR5K_SREV_AR5311A 0x20 /* Maui 2 */
309#define AR5K_SREV_AR5311B 0x30 /* Spirit */
310#define AR5K_SREV_AR5211 0x40 /* Oahu */
311#define AR5K_SREV_AR5212 0x50 /* Venice */
312#define AR5K_SREV_AR5213 0x55 /* ??? */
313#define AR5K_SREV_AR5213A 0x59 /* Hainan */
314#define AR5K_SREV_AR2413 0x78 /* Griffin lite */
315#define AR5K_SREV_AR2414 0x70 /* Griffin */
316#define AR5K_SREV_AR5424 0x90 /* Condor */
317#define AR5K_SREV_AR5413 0xa4 /* Eagle lite */
318#define AR5K_SREV_AR5414 0xa0 /* Eagle */
319#define AR5K_SREV_AR2415 0xb0 /* Cobra */
320#define AR5K_SREV_AR5416 0xc0 /* PCI-E */
321#define AR5K_SREV_AR5418 0xca /* PCI-E */
322#define AR5K_SREV_AR2425 0xe0 /* Swan */
323#define AR5K_SREV_AR2417 0xf0 /* Nala */
fa1c114f
JS		 324
325#define AR5K_SREV_RAD_5110 0x00
326#define AR5K_SREV_RAD_5111 0x10
327#define AR5K_SREV_RAD_5111A 0x15
328#define AR5K_SREV_RAD_2111 0x20
329#define AR5K_SREV_RAD_5112 0x30
330#define AR5K_SREV_RAD_5112A 0x35
e5a4ad0d 331#define AR5K_SREV_RAD_5112B 0x36
fa1c114f
JS		 332#define AR5K_SREV_RAD_2112 0x40
333#define AR5K_SREV_RAD_2112A 0x45
e5a4ad0d 334#define AR5K_SREV_RAD_2112B 0x46
1bef016a
NK		 335#define AR5K_SREV_RAD_2413 0x50
336#define AR5K_SREV_RAD_5413 0x60
337#define AR5K_SREV_RAD_2316 0x70
338#define AR5K_SREV_RAD_2317 0x80
339#define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */
340#define AR5K_SREV_RAD_2425 0xa2
341#define AR5K_SREV_RAD_5133 0xc0
342
343#define AR5K_SREV_PHY_5211 0x30
344#define AR5K_SREV_PHY_5212 0x41
345#define AR5K_SREV_PHY_2112B 0x43
346#define AR5K_SREV_PHY_2413 0x45
347#define AR5K_SREV_PHY_5413 0x61
348#define AR5K_SREV_PHY_2425 0x70
fa1c114f
JS		 349
350/* IEEE defs */
fa1c114f
JS		 351#define IEEE80211_MAX_LEN 2500
352
353/* TODO add support to mac80211 for vendor-specific rates and modes */
354
355/*
356 * Some of this information is based on Documentation from:
357 *
358 * http://madwifi.org/wiki/ChipsetFeatures/SuperAG
359 *
360 * Modulation for Atheros' eXtended Range - range enhancing extension that is
361 * supposed to double the distance an Atheros client device can keep a
362 * connection with an Atheros access point. This is achieved by increasing
363 * the receiver sensitivity up to, -105dBm, which is about 20dB above what
364 * the 802.11 specifications demand. In addition, new (proprietary) data rates
365 * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
366 *
367 * Please note that can you either use XR or TURBO but you cannot use both,
368 * they are exclusive.
369 *
370 */
371#define MODULATION_XR 0x00000200
372/*
373 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a
374 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s
375 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g
376 * channels. To use this feature your Access Point must also suport it.
377 * There is also a distinction between "static" and "dynamic" turbo modes:
378 *
379 * - Static: is the dumb version: devices set to this mode stick to it until
380 * the mode is turned off.
381 * - Dynamic: is the intelligent version, the network decides itself if it
382 * is ok to use turbo. As soon as traffic is detected on adjacent channels
383 * (which would get used in turbo mode), or when a non-turbo station joins
384 * the network, turbo mode won't be used until the situation changes again.
385 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which
386 * monitors the used radio band in order to decide whether turbo mode may
387 * be used or not.
388 *
389 * This article claims Super G sticks to bonding of channels 5 and 6 for
390 * USA:
391 *
392 * http://www.pcworld.com/article/id,113428-page,1/article.html
393 *
394 * The channel bonding seems to be driver specific though. In addition to
395 * deciding what channels will be used, these "Turbo" modes are accomplished
396 * by also enabling the following features:
397 *
398 * - Bursting: allows multiple frames to be sent at once, rather than pausing
399 * after each frame. Bursting is a standards-compliant feature that can be
400 * used with any Access Point.
401 * - Fast frames: increases the amount of information that can be sent per
402 * frame, also resulting in a reduction of transmission overhead. It is a
403 * proprietary feature that needs to be supported by the Access Point.
404 * - Compression: data frames are compressed in real time using a Lempel Ziv
405 * algorithm. This is done transparently. Once this feature is enabled,
406 * compression and decompression takes place inside the chipset, without
407 * putting additional load on the host CPU.
408 *
409 */
410#define MODULATION_TURBO 0x00000080
411
d8ee398d
LR		 412enum ath5k_driver_mode {
413 AR5K_MODE_11A = 0,
414 AR5K_MODE_11A_TURBO = 1,
415 AR5K_MODE_11B = 2,
416 AR5K_MODE_11G = 3,
417 AR5K_MODE_11G_TURBO = 4,
418 AR5K_MODE_XR = 0,
419 AR5K_MODE_MAX = 5
fa1c114f
JS		 420};
421
19fd6e55 422
fa1c114f
JS		 423/****************\
424 TX DEFINITIONS
425\****************/
426
427/*
c6e387a2 428 * TX Status descriptor
fa1c114f
JS		 429 */
430struct ath5k_tx_status {
431 u16 ts_seqnum;
432 u16 ts_tstamp;
433 u8 ts_status;
2f7fe870
FF		 434 u8 ts_rate[4];
435 u8 ts_retry[4];
436 u8 ts_final_idx;
fa1c114f
JS		 437 s8 ts_rssi;
438 u8 ts_shortretry;
439 u8 ts_longretry;
440 u8 ts_virtcol;
441 u8 ts_antenna;
442};
443
444#define AR5K_TXSTAT_ALTRATE 0x80
445#define AR5K_TXERR_XRETRY 0x01
446#define AR5K_TXERR_FILT 0x02
447#define AR5K_TXERR_FIFO 0x04
448
449/**
450 * enum ath5k_tx_queue - Queue types used to classify tx queues.
451 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
452 * @AR5K_TX_QUEUE_DATA: A normal data queue
453 * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue
454 * @AR5K_TX_QUEUE_BEACON: The beacon queue
455 * @AR5K_TX_QUEUE_CAB: The after-beacon queue
456 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
457 */
458enum ath5k_tx_queue {
459 AR5K_TX_QUEUE_INACTIVE = 0,
460 AR5K_TX_QUEUE_DATA,
461 AR5K_TX_QUEUE_XR_DATA,
462 AR5K_TX_QUEUE_BEACON,
463 AR5K_TX_QUEUE_CAB,
464 AR5K_TX_QUEUE_UAPSD,
465};
466
467#define AR5K_NUM_TX_QUEUES 10
468#define AR5K_NUM_TX_QUEUES_NOQCU 2
469
470/*
471 * Queue syb-types to classify normal data queues.
472 * These are the 4 Access Categories as defined in
473 * WME spec. 0 is the lowest priority and 4 is the
474 * highest. Normal data that hasn't been classified
475 * goes to the Best Effort AC.
476 */
477enum ath5k_tx_queue_subtype {
478 AR5K_WME_AC_BK = 0, /*Background traffic*/
479 AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/
480 AR5K_WME_AC_VI, /*Video traffic*/
481 AR5K_WME_AC_VO, /*Voice traffic*/
482};
483
484/*
485 * Queue ID numbers as returned by the hw functions, each number
486 * represents a hw queue. If hw does not support hw queues
487 * (eg 5210) all data goes in one queue. These match
488 * d80211 definitions (net80211/MadWiFi don't use them).
489 */
490enum ath5k_tx_queue_id {
491 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0,
492 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1,
493 AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/
494 AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/
495 AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/
496 AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/
497 AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/
498 AR5K_TX_QUEUE_ID_UAPSD = 8,
499 AR5K_TX_QUEUE_ID_XR_DATA = 9,
500};
501
fa1c114f
JS		 502/*
503 * Flags to set hw queue's parameters...
504 */
505#define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */
506#define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */
507#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */
508#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */
509#define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */
4c674c60
NK		 510#define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */
511#define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */
512#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */
513#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */
514#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */
515#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/
516#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */
517#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */
518#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/
fa1c114f
JS		 519
520/*
521 * A struct to hold tx queue's parameters
522 */
523struct ath5k_txq_info {
524 enum ath5k_tx_queue tqi_type;
525 enum ath5k_tx_queue_subtype tqi_subtype;
526 u16 tqi_flags; /* Tx queue flags (see above) */
527 u32 tqi_aifs; /* Arbitrated Interframe Space */
528 s32 tqi_cw_min; /* Minimum Contention Window */
529 s32 tqi_cw_max; /* Maximum Contention Window */
530 u32 tqi_cbr_period; /* Constant bit rate period */
531 u32 tqi_cbr_overflow_limit;
532 u32 tqi_burst_time;
533 u32 tqi_ready_time; /* Not used */
534};
535
536/*
537 * Transmit packet types.
c6e387a2
NK		 538 * used on tx control descriptor
539 * TODO: Use them inside base.c corectly
fa1c114f
JS		 540 */
541enum ath5k_pkt_type {
542 AR5K_PKT_TYPE_NORMAL = 0,
543 AR5K_PKT_TYPE_ATIM = 1,
544 AR5K_PKT_TYPE_PSPOLL = 2,
545 AR5K_PKT_TYPE_BEACON = 3,
546 AR5K_PKT_TYPE_PROBE_RESP = 4,
547 AR5K_PKT_TYPE_PIFS = 5,
548};
549
550/*
551 * TX power and TPC settings
552 */
553#define AR5K_TXPOWER_OFDM(_r, _v) ( \
554 ((0 & 1) << ((_v) + 6)) | \
555 (((ah->ah_txpower.txp_rates[(_r)]) & 0x3f) << (_v)) \
556)
557
558#define AR5K_TXPOWER_CCK(_r, _v) ( \
559 (ah->ah_txpower.txp_rates[(_r)] & 0x3f) << (_v) \
560)
561
562/*
563 * DMA size definitions (2^n+2)
564 */
565enum ath5k_dmasize {
566 AR5K_DMASIZE_4B = 0,
567 AR5K_DMASIZE_8B,
568 AR5K_DMASIZE_16B,
569 AR5K_DMASIZE_32B,
570 AR5K_DMASIZE_64B,
571 AR5K_DMASIZE_128B,
572 AR5K_DMASIZE_256B,
573 AR5K_DMASIZE_512B
574};
575
576
577/****************\
578 RX DEFINITIONS
579\****************/
580
581/*
c6e387a2 582 * RX Status descriptor
fa1c114f
JS		 583 */
584struct ath5k_rx_status {
585 u16 rs_datalen;
586 u16 rs_tstamp;
587 u8 rs_status;
588 u8 rs_phyerr;
589 s8 rs_rssi;
590 u8 rs_keyix;
591 u8 rs_rate;
592 u8 rs_antenna;
593 u8 rs_more;
594};
595
596#define AR5K_RXERR_CRC 0x01
597#define AR5K_RXERR_PHY 0x02
598#define AR5K_RXERR_FIFO 0x04
599#define AR5K_RXERR_DECRYPT 0x08
600#define AR5K_RXERR_MIC 0x10
601#define AR5K_RXKEYIX_INVALID ((u8) - 1)
602#define AR5K_TXKEYIX_INVALID ((u32) - 1)
603
fa1c114f 604
fa1c114f
JS		 605/**************************\
606 BEACON TIMERS DEFINITIONS
607\**************************/
608
609#define AR5K_BEACON_PERIOD 0x0000ffff
610#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/
611#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/
612
613#if 0
614/**
615 * struct ath5k_beacon_state - Per-station beacon timer state.
616 * @bs_interval: in TU's, can also include the above flags
617 * @bs_cfp_max_duration: if non-zero hw is setup to coexist with a
618 * Point Coordination Function capable AP
619 */
620struct ath5k_beacon_state {
621 u32 bs_next_beacon;
622 u32 bs_next_dtim;
623 u32 bs_interval;
624 u8 bs_dtim_period;
625 u8 bs_cfp_period;
626 u16 bs_cfp_max_duration;
627 u16 bs_cfp_du_remain;
628 u16 bs_tim_offset;
629 u16 bs_sleep_duration;
630 u16 bs_bmiss_threshold;
631 u32 bs_cfp_next;
632};
633#endif
634
635
636/*
637 * TSF to TU conversion:
638 *
639 * TSF is a 64bit value in usec (microseconds).
e535c1ac
BR		 640 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
641 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
fa1c114f
JS		 642 */
643#define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
644
645
c6e387a2
NK		 646/*******************************\
647 GAIN OPTIMIZATION DEFINITIONS
648\*******************************/
649
650enum ath5k_rfgain {
651 AR5K_RFGAIN_INACTIVE = 0,
652 AR5K_RFGAIN_READ_REQUESTED,
653 AR5K_RFGAIN_NEED_CHANGE,
654};
655
656#define AR5K_GAIN_CRN_FIX_BITS_5111 4
657#define AR5K_GAIN_CRN_FIX_BITS_5112 7
658#define AR5K_GAIN_CRN_MAX_FIX_BITS AR5K_GAIN_CRN_FIX_BITS_5112
659#define AR5K_GAIN_DYN_ADJUST_HI_MARGIN 15
660#define AR5K_GAIN_DYN_ADJUST_LO_MARGIN 20
661#define AR5K_GAIN_CCK_PROBE_CORR 5
662#define AR5K_GAIN_CCK_OFDM_GAIN_DELTA 15
663#define AR5K_GAIN_STEP_COUNT 10
664#define AR5K_GAIN_PARAM_TX_CLIP 0
665#define AR5K_GAIN_PARAM_PD_90 1
666#define AR5K_GAIN_PARAM_PD_84 2
667#define AR5K_GAIN_PARAM_GAIN_SEL 3
668#define AR5K_GAIN_PARAM_MIX_ORN 0
669#define AR5K_GAIN_PARAM_PD_138 1
670#define AR5K_GAIN_PARAM_PD_137 2
671#define AR5K_GAIN_PARAM_PD_136 3
672#define AR5K_GAIN_PARAM_PD_132 4
673#define AR5K_GAIN_PARAM_PD_131 5
674#define AR5K_GAIN_PARAM_PD_130 6
675#define AR5K_GAIN_CHECK_ADJUST(_g) \
676 ((_g)->g_current <= (_g)->g_low || (_g)->g_current >= (_g)->g_high)
677
678struct ath5k_gain_opt_step {
679 s16 gos_param[AR5K_GAIN_CRN_MAX_FIX_BITS];
680 s32 gos_gain;
681};
682
683struct ath5k_gain {
684 u32 g_step_idx;
685 u32 g_current;
686 u32 g_target;
687 u32 g_low;
688 u32 g_high;
689 u32 g_f_corr;
690 u32 g_active;
691 const struct ath5k_gain_opt_step *g_step;
692};
693
694
fa1c114f
JS		 695/********************\
696 COMMON DEFINITIONS
697\********************/
698
fa1c114f
JS		 699#define AR5K_SLOT_TIME_9 396
700#define AR5K_SLOT_TIME_20 880
701#define AR5K_SLOT_TIME_MAX 0xffff
702
703/* channel_flags */
704#define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */
705#define CHANNEL_TURBO 0x0010 /* Turbo Channel */
706#define CHANNEL_CCK 0x0020 /* CCK channel */
707#define CHANNEL_OFDM 0x0040 /* OFDM channel */
708#define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */
709#define CHANNEL_5GHZ 0x0100 /* 5GHz channel */
710#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */
711#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */
712#define CHANNEL_XR 0x0800 /* XR channel */
713
714#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
715#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
716#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
717#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
718#define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
719#define CHANNEL_108A CHANNEL_T
720#define CHANNEL_108G CHANNEL_TG
721#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
722
723#define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \
724 CHANNEL_TURBO)
725
726#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL & ~CHANNEL_TURBO)
727#define CHANNEL_MODES CHANNEL_ALL
728
729/*
c6e387a2
NK		 730 * Used internaly for reset_tx_queue).
731 * Also see struct struct ieee80211_channel.
fa1c114f 732 */
d8ee398d
LR		 733#define IS_CHAN_XR(_c) ((_c.hw_value & CHANNEL_XR) != 0)
734#define IS_CHAN_B(_c) ((_c.hw_value & CHANNEL_B) != 0)
fa1c114f
JS		 735
736/*
c6e387a2 737 * The following structure is used to map 2GHz channels to
fa1c114f 738 * 5GHz Atheros channels.
c6e387a2 739 * TODO: Clean up
fa1c114f
JS		 740 */
741struct ath5k_athchan_2ghz {
742 u32 a2_flags;
743 u16 a2_athchan;
744};
745
63266a65 746
c6e387a2
NK		 747/******************\
748 RATE DEFINITIONS
749\******************/
fa1c114f 750
fa1c114f 751/**
63266a65 752 * Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32.
fa1c114f 753 *
63266a65 754 * The rate code is used to get the RX rate or set the TX rate on the
fa1c114f
JS		 755 * hardware descriptors. It is also used for internal modulation control
756 * and settings.
757 *
63266a65 758 * This is the hardware rate map we are aware of:
fa1c114f 759 *
63266a65 760 * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08
fa1c114f
JS		 761 * rate_kbps 3000 1000 ? ? ? 2000 500 48000
762 *
63266a65 763 * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10
fa1c114f
JS		 764 * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ?
765 *
766 * rate_code 17 18 19 20 21 22 23 24
767 * rate_kbps ? ? ? ? ? ? ? 11000
768 *
769 * rate_code 25 26 27 28 29 30 31 32
63266a65
BR		 770 * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ?
771 *
772 * "S" indicates CCK rates with short preamble.
fa1c114f 773 *
63266a65
BR		 774 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the
775 * lowest 4 bits, so they are the same as below with a 0xF mask.
776 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M).
777 * We handle this in ath5k_setup_bands().
fa1c114f 778 */
63266a65 779#define AR5K_MAX_RATES 32
fa1c114f 780
63266a65
BR		 781/* B */
782#define ATH5K_RATE_CODE_1M 0x1B
783#define ATH5K_RATE_CODE_2M 0x1A
784#define ATH5K_RATE_CODE_5_5M 0x19
785#define ATH5K_RATE_CODE_11M 0x18
786/* A and G */
787#define ATH5K_RATE_CODE_6M 0x0B
788#define ATH5K_RATE_CODE_9M 0x0F
789#define ATH5K_RATE_CODE_12M 0x0A
790#define ATH5K_RATE_CODE_18M 0x0E
791#define ATH5K_RATE_CODE_24M 0x09
792#define ATH5K_RATE_CODE_36M 0x0D
793#define ATH5K_RATE_CODE_48M 0x08
794#define ATH5K_RATE_CODE_54M 0x0C
795/* XR */
796#define ATH5K_RATE_CODE_XR_500K 0x07
797#define ATH5K_RATE_CODE_XR_1M 0x02
798#define ATH5K_RATE_CODE_XR_2M 0x06
799#define ATH5K_RATE_CODE_XR_3M 0x01
fa1c114f 800
c6e387a2
NK		 801/* adding this flag to rate_code enables short preamble */
802#define AR5K_SET_SHORT_PREAMBLE 0x04
fa1c114f
JS		 803
804/*
805 * Crypto definitions
806 */
807
808#define AR5K_KEYCACHE_SIZE 8
809
810/***********************\
811 HW RELATED DEFINITIONS
812\***********************/
813
814/*
815 * Misc definitions
816 */
817#define AR5K_RSSI_EP_MULTIPLIER (1<<7)
818
819#define AR5K_ASSERT_ENTRY(_e, _s) do { \
820 if (_e >= _s) \
821 return (false); \
822} while (0)
823
fa1c114f
JS		 824/*
825 * Hardware interrupt abstraction
826 */
827
828/**
829 * enum ath5k_int - Hardware interrupt masks helpers
830 *
831 * @AR5K_INT_RX: mask to identify received frame interrupts, of type
832 * AR5K_ISR_RXOK or AR5K_ISR_RXERR
833 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?)
834 * @AR5K_INT_RXNOFRM: No frame received (?)
835 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The
836 * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's
837 * LinkPtr is NULL. For more details, refer to:
838 * http://www.freepatentsonline.com/20030225739.html
839 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors).
840 * Note that Rx overrun is not always fatal, on some chips we can continue
841 * operation without reseting the card, that's why int_fatal is not
842 * common for all chips.
843 * @AR5K_INT_TX: mask to identify received frame interrupts, of type
844 * AR5K_ISR_TXOK or AR5K_ISR_TXERR
845 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?)
846 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold
847 * We currently do increments on interrupt by
848 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
849 * @AR5K_INT_MIB: Indicates the Management Information Base counters should be
850 * checked. We should do this with ath5k_hw_update_mib_counters() but
851 * it seems we should also then do some noise immunity work.
852 * @AR5K_INT_RXPHY: RX PHY Error
4c674c60 853 * @AR5K_INT_RXKCM: RX Key cache miss
fa1c114f
JS		 854 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
855 * beacon that must be handled in software. The alternative is if you
856 * have VEOL support, in that case you let the hardware deal with things.
857 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
858 * beacons from the AP have associated with, we should probably try to
859 * reassociate. When in IBSS mode this might mean we have not received
860 * any beacons from any local stations. Note that every station in an
861 * IBSS schedules to send beacons at the Target Beacon Transmission Time
862 * (TBTT) with a random backoff.
863 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ??
864 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now
865 * until properly handled
866 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA
867 * errors. These types of errors we can enable seem to be of type
868 * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR.
4c674c60 869 * @AR5K_INT_GLOBAL: Used to clear and set the IER
fa1c114f
JS		 870 * @AR5K_INT_NOCARD: signals the card has been removed
871 * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same
872 * bit value
873 *
874 * These are mapped to take advantage of some common bits
875 * between the MACs, to be able to set intr properties
876 * easier. Some of them are not used yet inside hw.c. Most map
877 * to the respective hw interrupt value as they are common amogst different
878 * MACs.
879 */
880enum ath5k_int {
4c674c60 881 AR5K_INT_RXOK = 0x00000001,
fa1c114f 882 AR5K_INT_RXDESC = 0x00000002,
4c674c60 883 AR5K_INT_RXERR = 0x00000004,
fa1c114f
JS		 884 AR5K_INT_RXNOFRM = 0x00000008,
885 AR5K_INT_RXEOL = 0x00000010,
886 AR5K_INT_RXORN = 0x00000020,
4c674c60 887 AR5K_INT_TXOK = 0x00000040,
fa1c114f 888 AR5K_INT_TXDESC = 0x00000080,
4c674c60
NK		 889 AR5K_INT_TXERR = 0x00000100,
890 AR5K_INT_TXNOFRM = 0x00000200,
891 AR5K_INT_TXEOL = 0x00000400,
fa1c114f
JS		 892 AR5K_INT_TXURN = 0x00000800,
893 AR5K_INT_MIB = 0x00001000,
4c674c60 894 AR5K_INT_SWI = 0x00002000,
fa1c114f
JS		 895 AR5K_INT_RXPHY = 0x00004000,
896 AR5K_INT_RXKCM = 0x00008000,
897 AR5K_INT_SWBA = 0x00010000,
4c674c60 898 AR5K_INT_BRSSI = 0x00020000,
fa1c114f 899 AR5K_INT_BMISS = 0x00040000,
4c674c60
NK		 900 AR5K_INT_FATAL = 0x00080000, /* Non common */
901 AR5K_INT_BNR = 0x00100000, /* Non common */
902 AR5K_INT_TIM = 0x00200000, /* Non common */
903 AR5K_INT_DTIM = 0x00400000, /* Non common */
904 AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */
905 AR5K_INT_GPIO = 0x01000000,
906 AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */
907 AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */
908 AR5K_INT_RX_DOPPLER = 0x08000000, /* Non common */
909 AR5K_INT_QCBRORN = 0x10000000, /* Non common */
910 AR5K_INT_QCBRURN = 0x20000000, /* Non common */
911 AR5K_INT_QTRIG = 0x40000000, /* Non common */
912 AR5K_INT_GLOBAL = 0x80000000,
913
914 AR5K_INT_COMMON = AR5K_INT_RXOK
915 | AR5K_INT_RXDESC
916 | AR5K_INT_RXERR
917 | AR5K_INT_RXNOFRM
918 | AR5K_INT_RXEOL
919 | AR5K_INT_RXORN
920 | AR5K_INT_TXOK
921 | AR5K_INT_TXDESC
922 | AR5K_INT_TXERR
923 | AR5K_INT_TXNOFRM
924 | AR5K_INT_TXEOL
925 | AR5K_INT_TXURN
926 | AR5K_INT_MIB
927 | AR5K_INT_SWI
928 | AR5K_INT_RXPHY
929 | AR5K_INT_RXKCM
930 | AR5K_INT_SWBA
931 | AR5K_INT_BRSSI
932 | AR5K_INT_BMISS
933 | AR5K_INT_GPIO
934 | AR5K_INT_GLOBAL,
935
fa1c114f
JS		 936 AR5K_INT_NOCARD = 0xffffffff
937};
938
939/*
940 * Power management
941 */
942enum ath5k_power_mode {
943 AR5K_PM_UNDEFINED = 0,
944 AR5K_PM_AUTO,
945 AR5K_PM_AWAKE,
946 AR5K_PM_FULL_SLEEP,
947 AR5K_PM_NETWORK_SLEEP,
948};
949
950/*
951 * These match net80211 definitions (not used in
c6e387a2
NK		 952 * mac80211).
953 * TODO: Clean this up
fa1c114f
JS		 954 */
955#define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/
956#define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/
957#define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/
958#define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/
959#define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/
960
961/* GPIO-controlled software LED */
962#define AR5K_SOFTLED_PIN 0
963#define AR5K_SOFTLED_ON 0
964#define AR5K_SOFTLED_OFF 1
965
966/*
967 * Chipset capabilities -see ath5k_hw_get_capability-
968 * get_capability function is not yet fully implemented
c6e387a2
NK		 969 * in ath5k so most of these don't work yet...
970 * TODO: Implement these & merge with _TUNE_ stuff above
fa1c114f
JS		 971 */
972enum ath5k_capability_type {
973 AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */
974 AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */
975 AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */
976 AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */
977 AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */
978 AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */
979 AR5K_CAP_VEOL = 7, /* Supports virtual EOL */
980 AR5K_CAP_COMPRESSION = 8, /* Supports compression */
981 AR5K_CAP_BURST = 9, /* Supports packet bursting */
982 AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */
983 AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */
984 AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */
985 AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */
986 AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */
987 AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */
988 AR5K_CAP_XR = 16, /* Supports XR mode */
989 AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */
990 AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */
991 AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */
992 AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */
993};
994
400ec45a
LR		 995
996/* XXX: we *may* move cap_range stuff to struct wiphy */
fa1c114f
JS		 997struct ath5k_capabilities {
998 /*
999 * Supported PHY modes
1000 * (ie. CHANNEL_A, CHANNEL_B, ...)
1001 */
d8ee398d 1002 DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX);
fa1c114f
JS		 1003
1004 /*
1005 * Frequency range (without regulation restrictions)
1006 */
1007 struct {
1008 u16 range_2ghz_min;
1009 u16 range_2ghz_max;
1010 u16 range_5ghz_min;
1011 u16 range_5ghz_max;
1012 } cap_range;
1013
fa1c114f
JS		 1014 /*
1015 * Values stored in the EEPROM (some of them...)
1016 */
1017 struct ath5k_eeprom_info cap_eeprom;
1018
1019 /*
1020 * Queue information
1021 */
1022 struct {
1023 u8 q_tx_num;
1024 } cap_queues;
1025};
1026
1027
1028/***************************************\
1029 HARDWARE ABSTRACTION LAYER STRUCTURE
1030\***************************************/
1031
1032/*
1033 * Misc defines
1034 */
1035
1036#define AR5K_MAX_GPIO 10
1037#define AR5K_MAX_RF_BANKS 8
1038
c6e387a2 1039/* TODO: Clean up and merge with ath5k_softc */
fa1c114f
JS		 1040struct ath5k_hw {
1041 u32 ah_magic;
1042
1043 struct ath5k_softc *ah_sc;
1044 void __iomem *ah_iobase;
1045
1046 enum ath5k_int ah_imr;
1047
05c914fe 1048 enum nl80211_iftype ah_op_mode;
fa1c114f
JS		 1049 enum ath5k_power_mode ah_power_mode;
1050 struct ieee80211_channel ah_current_channel;
1051 bool ah_turbo;
1052 bool ah_calibration;
1053 bool ah_running;
1054 bool ah_single_chip;
f650470a 1055 bool ah_combined_mic;
fa1c114f
JS		 1056 enum ath5k_rfgain ah_rf_gain;
1057
1058 u32 ah_mac_srev;
1059 u16 ah_mac_version;
1060 u16 ah_mac_revision;
1061 u16 ah_phy_revision;
1062 u16 ah_radio_5ghz_revision;
1063 u16 ah_radio_2ghz_revision;
0af22563 1064 u32 ah_phy_spending;
fa1c114f
JS		 1065
1066 enum ath5k_version ah_version;
1067 enum ath5k_radio ah_radio;
1068 u32 ah_phy;
1069
1070 bool ah_5ghz;
1071 bool ah_2ghz;
1072
1073#define ah_regdomain ah_capabilities.cap_regdomain.reg_current
1074#define ah_regdomain_hw ah_capabilities.cap_regdomain.reg_hw
1075#define ah_modes ah_capabilities.cap_mode
1076#define ah_ee_version ah_capabilities.cap_eeprom.ee_version
1077
1078 u32 ah_atim_window;
1079 u32 ah_aifs;
1080 u32 ah_cw_min;
1081 u32 ah_cw_max;
1082 bool ah_software_retry;
1083 u32 ah_limit_tx_retries;
1084
1085 u32 ah_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
1086 bool ah_ant_diversity;
1087
1088 u8 ah_sta_id[ETH_ALEN];
1089
f07a6c49 1090 /* Current BSSID we are trying to assoc to / create.
fa1c114f
JS		 1091 * This is passed by mac80211 on config_interface() and cached here for
1092 * use in resets */
1093 u8 ah_bssid[ETH_ALEN];
f07a6c49 1094 u8 ah_bssid_mask[ETH_ALEN];
fa1c114f
JS		 1095
1096 u32 ah_gpio[AR5K_MAX_GPIO];
1097 int ah_gpio_npins;
1098
1099 struct ath5k_capabilities ah_capabilities;
1100
1101 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES];
1102 u32 ah_txq_status;
1103 u32 ah_txq_imr_txok;
1104 u32 ah_txq_imr_txerr;
1105 u32 ah_txq_imr_txurn;
1106 u32 ah_txq_imr_txdesc;
1107 u32 ah_txq_imr_txeol;
4c674c60
NK		 1108 u32 ah_txq_imr_cbrorn;
1109 u32 ah_txq_imr_cbrurn;
1110 u32 ah_txq_imr_qtrig;
1111 u32 ah_txq_imr_nofrm;
1112 u32 ah_txq_isr;
fa1c114f
JS		 1113 u32 *ah_rf_banks;
1114 size_t ah_rf_banks_size;
1115 struct ath5k_gain ah_gain;
1116 u32 ah_offset[AR5K_MAX_RF_BANKS];
1117
1118 struct {
1119 u16 txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE];
1120 u16 txp_rates[AR5K_MAX_RATES];
1121 s16 txp_min;
1122 s16 txp_max;
1123 bool txp_tpc;
1124 s16 txp_ofdm;
1125 } ah_txpower;
1126
1127 struct {
1128 bool r_enabled;
1129 int r_last_alert;
1130 struct ieee80211_channel r_last_channel;
1131 } ah_radar;
1132
1133 /* noise floor from last periodic calibration */
1134 s32 ah_noise_floor;
1135
1136 /*
1137 * Function pointers
1138 */
c6e387a2
NK		 1139 int (*ah_setup_rx_desc)(struct ath5k_hw *ah, struct ath5k_desc *desc,
1140 u32 size, unsigned int flags);
fa1c114f
JS		 1141 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1142 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
1143 unsigned int, unsigned int, unsigned int, unsigned int,
1144 unsigned int, unsigned int, unsigned int);
c6e387a2 1145 int (*ah_setup_mrr_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
fa1c114f
JS		 1146 unsigned int, unsigned int, unsigned int, unsigned int,
1147 unsigned int, unsigned int);
b47f407b
BR		 1148 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1149 struct ath5k_tx_status *);
1150 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1151 struct ath5k_rx_status *);
fa1c114f
JS		 1152};
1153
1154/*
1155 * Prototypes
1156 */
1157
fa1c114f
JS		 1158/* Attach/Detach Functions */
1159extern struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version);
fa1c114f 1160extern void ath5k_hw_detach(struct ath5k_hw *ah);
c6e387a2 1161
fa1c114f 1162/* Reset Functions */
c6e387a2 1163extern int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial);
05c914fe 1164extern int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, struct ieee80211_channel *channel, bool change_channel);
fa1c114f
JS		 1165/* Power management functions */
1166extern int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration);
c6e387a2 1167
fa1c114f 1168/* DMA Related Functions */
c6e387a2 1169extern void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);
fa1c114f 1170extern int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah);
c6e387a2
NK		 1171extern u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);
1172extern void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
1173extern int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);
fa1c114f 1174extern int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue);
c6e387a2
NK		 1175extern u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);
1176extern int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,
1177 u32 phys_addr);
fa1c114f
JS		 1178extern int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
1179/* Interrupt handling */
1180extern bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
1181extern int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
c6e387a2
NK		 1182extern enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum
1183ath5k_int new_mask);
194828a2 1184extern void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, struct ieee80211_low_level_stats *stats);
c6e387a2 1185
fa1c114f 1186/* EEPROM access functions */
c6e387a2
NK		 1187extern int ath5k_eeprom_init(struct ath5k_hw *ah);
1188extern int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac);
1189
fa1c114f
JS		 1190/* Protocol Control Unit Functions */
1191extern int ath5k_hw_set_opmode(struct ath5k_hw *ah);
1192/* BSSID Functions */
1193extern void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac);
1194extern int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
1195extern void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id);
1196extern int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
1197/* Receive start/stop functions */
1198extern void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
c6e387a2 1199extern void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
fa1c114f
JS		 1200/* RX Filter functions */
1201extern void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
c6e387a2 1202extern int ath5k_hw_set_mcast_filter_idx(struct ath5k_hw *ah, u32 index);
fa1c114f
JS		 1203extern int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index);
1204extern u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
1205extern void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
c6e387a2 1206/* Beacon control functions */
fa1c114f
JS		 1207extern u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah);
1208extern u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
8cab7581 1209extern void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64);
fa1c114f
JS		 1210extern void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
1211extern void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval);
1212#if 0
1213extern int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah, const struct ath5k_beacon_state *state);
1214extern void ath5k_hw_reset_beacon(struct ath5k_hw *ah);
1215extern int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr);
1216#endif
fa1c114f
JS		 1217/* ACK bit rate */
1218void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high);
1219/* ACK/CTS Timeouts */
1220extern int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout);
1221extern unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah);
1222extern int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout);
1223extern unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah);
1224/* Key table (WEP) functions */
1225extern int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry);
1226extern int ath5k_hw_is_key_valid(struct ath5k_hw *ah, u16 entry);
1227extern int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry, const struct ieee80211_key_conf *key, const u8 *mac);
1228extern int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac);
c6e387a2 1229
fa1c114f 1230/* Queue Control Unit, DFS Control Unit Functions */
fa1c114f 1231extern int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, struct ath5k_txq_info *queue_info);
c6e387a2
NK		 1232extern int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
1233 const struct ath5k_txq_info *queue_info);
1234extern int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
1235 enum ath5k_tx_queue queue_type,
1236 struct ath5k_txq_info *queue_info);
1237extern u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);
fa1c114f
JS		 1238extern void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1239extern int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);
fa1c114f 1240extern unsigned int ath5k_hw_get_slot_time(struct ath5k_hw *ah);
c6e387a2
NK		 1241extern int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time);
1242
fa1c114f 1243/* Hardware Descriptor Functions */
c6e387a2
NK		 1244extern int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
1245
fa1c114f
JS		 1246/* GPIO Functions */
1247extern void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
fa1c114f 1248extern int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
c6e387a2 1249extern int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
fa1c114f
JS		 1250extern u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
1251extern int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
1252extern void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level);
c6e387a2 1253
fa1c114f 1254/* Misc functions */
c6e387a2 1255int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
fa1c114f 1256extern int ath5k_hw_get_capability(struct ath5k_hw *ah, enum ath5k_capability_type cap_type, u32 capability, u32 *result);
c6e387a2
NK		 1257extern int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
1258extern int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
fa1c114f
JS		 1259
1260/* Initial register settings functions */
1261extern int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
c6e387a2 1262
fa1c114f
JS		 1263/* Initialize RF */
1264extern int ath5k_hw_rfregs(struct ath5k_hw *ah, struct ieee80211_channel *channel, unsigned int mode);
1265extern int ath5k_hw_rfgain(struct ath5k_hw *ah, unsigned int freq);
1266extern enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath5k_hw *ah);
1267extern int ath5k_hw_set_rfgain_opt(struct ath5k_hw *ah);
fa1c114f
JS		 1268/* PHY/RF channel functions */
1269extern bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags);
1270extern int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel);
1271/* PHY calibration */
1272extern int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, struct ieee80211_channel *channel);
c6e387a2 1273extern int ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq);
fa1c114f
JS		 1274/* Misc PHY functions */
1275extern u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan);
1276extern void ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant);
1277extern unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah);
c6e387a2 1278extern int ath5k_hw_phy_disable(struct ath5k_hw *ah);
fa1c114f
JS		 1279/* TX power setup */
1280extern int ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, unsigned int txpower);
1281extern int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, unsigned int power);
1282
c6e387a2
NK		 1283/*
1284 * Functions used internaly
1285 */
1286
1287/*
1288 * Translate usec to hw clock units
1289 */
1290static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo)
1291{
1292 return turbo ? (usec * 80) : (usec * 40);
1293}
fa1c114f 1294
c6e387a2
NK		 1295/*
1296 * Translate hw clock units to usec
1297 */
1298static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo)
1299{
1300 return turbo ? (clock / 80) : (clock / 40);
1301}
1302
1303/*
1304 * Read from a register
1305 */
fa1c114f
JS		 1306static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
1307{
1308 return ioread32(ah->ah_iobase + reg);
1309}
1310
c6e387a2
NK		 1311/*
1312 * Write to a register
1313 */
fa1c114f
JS		 1314static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1315{
1316 iowrite32(val, ah->ah_iobase + reg);
1317}
1318
c6e387a2
NK		 1319#if defined(_ATH5K_RESET) || defined(_ATH5K_PHY)
1320/*
1321 * Check if a register write has been completed
1322 */
1323static int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag,
1324 u32 val, bool is_set)
1325{
1326 int i;
1327 u32 data;
1328
1329 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
1330 data = ath5k_hw_reg_read(ah, reg);
1331 if (is_set && (data & flag))
1332 break;
1333 else if ((data & flag) == val)
1334 break;
1335 udelay(15);
1336 }
1337
1338 return (i <= 0) ? -EAGAIN : 0;
1339}
1340#endif
1341
1342static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
1343{
1344 u32 retval = 0, bit, i;
1345
1346 for (i = 0; i < bits; i++) {
1347 bit = (val >> i) & 1;
1348 retval = (retval << 1) | bit;
1349 }
1350
1351 return retval;
1352}
1353
fd6effca
BC		 1354static inline int ath5k_pad_size(int hdrlen)
1355{
1356 return (hdrlen < 24) ? 0 : hdrlen & 3;
1357}
1358
fa1c114f 1359#endif
Linux kernel - Deliverables
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