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hwmon: (max6650) Add support for alarms
[deliverable/linux.git] / drivers / net / wireless / ath5k / ath5k.h
CommitLineData
fa1c114f
JS		 1/*
2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#ifndef _ATH5K_H
19#define _ATH5K_H
20
c6e387a2
NK		 21/* TODO: Clean up channel debuging -doesn't work anyway- and start
22 * working on reg. control code using all available eeprom information
23 * -rev. engineering needed- */
fa1c114f
JS		 24#define CHAN_DEBUG 0
25
26#include <linux/io.h>
27#include <linux/types.h>
28#include <net/mac80211.h>
29
c6e387a2
NK		 30/* RX/TX descriptor hw structs
31 * TODO: Driver part should only see sw structs */
32#include "desc.h"
33
34/* EEPROM structs/offsets
35 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities)
36 * and clean up common bits, then introduce set/get functions in eeprom.c */
37#include "eeprom.h"
fa1c114f
JS		 38
39/* PCI IDs */
40#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */
41#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */
42#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */
43#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */
44#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */
45#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */
46#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */
47#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */
48#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */
49#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */
50#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */
51#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */
52#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */
53#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */
54#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
55#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
56#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */
57#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */
58#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */
59#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */
60#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */
61#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */
62#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */
63#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */
64#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */
65#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */
66#define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */
67#define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */
68
69/****************************\
70 GENERIC DRIVER DEFINITIONS
71\****************************/
72
73#define ATH5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__)
74
75#define ATH5K_PRINTK(_sc, _level, _fmt, ...) \
76 printk(_level "ath5k %s: " _fmt, \
77 ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \
78 ##__VA_ARGS__)
79
80#define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \
81 if (net_ratelimit()) \
82 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \
83 } while (0)
84
85#define ATH5K_INFO(_sc, _fmt, ...) \
86 ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__)
87
88#define ATH5K_WARN(_sc, _fmt, ...) \
89 ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__)
90
91#define ATH5K_ERR(_sc, _fmt, ...) \
92 ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__)
93
c6e387a2
NK		 94/*
95 * AR5K REGISTER ACCESS
96 */
97
98/* Some macros to read/write fields */
99
100/* First shift, then mask */
101#define AR5K_REG_SM(_val, _flags) \
102 (((_val) << _flags##_S) & (_flags))
103
104/* First mask, then shift */
105#define AR5K_REG_MS(_val, _flags) \
106 (((_val) & (_flags)) >> _flags##_S)
107
108/* Some registers can hold multiple values of interest. For this
109 * reason when we want to write to these registers we must first
110 * retrieve the values which we do not want to clear (lets call this
111 * old_data) and then set the register with this and our new_value:
112 * ( old_data | new_value) */
113#define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \
114 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
115 (((_val) << _flags##_S) & (_flags)), _reg)
116
117#define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \
118 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \
119 (_mask)) | (_flags), _reg)
120
121#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \
122 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
123
124#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \
125 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
126
127/* Access to PHY registers */
128#define AR5K_PHY_READ(ah, _reg) \
129 ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2))
130
131#define AR5K_PHY_WRITE(ah, _reg, _val) \
132 ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2))
133
134/* Access QCU registers per queue */
135#define AR5K_REG_READ_Q(ah, _reg, _queue) \
136 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \
137
138#define AR5K_REG_WRITE_Q(ah, _reg, _queue) \
139 ath5k_hw_reg_write(ah, (1 << _queue), _reg)
140
141#define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \
142 _reg |= 1 << _queue; \
143} while (0)
144
145#define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \
146 _reg &= ~(1 << _queue); \
147} while (0)
148
149/* Used while writing initvals */
150#define AR5K_REG_WAIT(_i) do { \
151 if (_i % 64) \
152 udelay(1); \
153} while (0)
154
155/* Register dumps are done per operation mode */
156#define AR5K_INI_RFGAIN_5GHZ 0
157#define AR5K_INI_RFGAIN_2GHZ 1
158
159/* TODO: Clean this up */
160#define AR5K_INI_VAL_11A 0
161#define AR5K_INI_VAL_11A_TURBO 1
162#define AR5K_INI_VAL_11B 2
163#define AR5K_INI_VAL_11G 3
164#define AR5K_INI_VAL_11G_TURBO 4
165#define AR5K_INI_VAL_XR 0
166#define AR5K_INI_VAL_MAX 5
167
c6e387a2
NK		 168/* Used for BSSID etc manipulation */
169#define AR5K_LOW_ID(_a)( \
170(_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24 \
171)
172
173#define AR5K_HIGH_ID(_a) ((_a)[4] | (_a)[5] << 8)
174
fa1c114f
JS		 175/*
176 * Some tuneable values (these should be changeable by the user)
c6e387a2 177 * TODO: Make use of them and add more options OR use debug/configfs
fa1c114f
JS		 178 */
179#define AR5K_TUNE_DMA_BEACON_RESP 2
180#define AR5K_TUNE_SW_BEACON_RESP 10
181#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0
182#define AR5K_TUNE_RADAR_ALERT false
183#define AR5K_TUNE_MIN_TX_FIFO_THRES 1
184#define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_LEN / 64) + 1)
185#define AR5K_TUNE_REGISTER_TIMEOUT 20000
186/* Register for RSSI threshold has a mask of 0xff, so 255 seems to
187 * be the max value. */
c6e387a2 188#define AR5K_TUNE_RSSI_THRES 129
fa1c114f
JS		 189/* This must be set when setting the RSSI threshold otherwise it can
190 * prevent a reset. If AR5K_RSSI_THR is read after writing to it
191 * the BMISS_THRES will be seen as 0, seems harware doesn't keep
192 * track of it. Max value depends on harware. For AR5210 this is just 7.
193 * For AR5211+ this seems to be up to 255. */
c6e387a2 194#define AR5K_TUNE_BMISS_THRES 7
fa1c114f
JS		 195#define AR5K_TUNE_REGISTER_DWELL_TIME 20000
196#define AR5K_TUNE_BEACON_INTERVAL 100
197#define AR5K_TUNE_AIFS 2
198#define AR5K_TUNE_AIFS_11B 2
199#define AR5K_TUNE_AIFS_XR 0
200#define AR5K_TUNE_CWMIN 15
201#define AR5K_TUNE_CWMIN_11B 31
202#define AR5K_TUNE_CWMIN_XR 3
203#define AR5K_TUNE_CWMAX 1023
204#define AR5K_TUNE_CWMAX_11B 1023
205#define AR5K_TUNE_CWMAX_XR 7
206#define AR5K_TUNE_NOISE_FLOOR -72
8f655dde
NK		 207#define AR5K_TUNE_MAX_TXPOWER 63
208#define AR5K_TUNE_DEFAULT_TXPOWER 25
209#define AR5K_TUNE_TPC_TXPOWER false
fa1c114f
JS		 210#define AR5K_TUNE_ANT_DIVERSITY true
211#define AR5K_TUNE_HWTXTRIES 4
212
c6e387a2
NK		 213#define AR5K_INIT_CARR_SENSE_EN 1
214
215/*Swap RX/TX Descriptor for big endian archs*/
216#if defined(__BIG_ENDIAN)
217#define AR5K_INIT_CFG ( \
218 AR5K_CFG_SWTD | AR5K_CFG_SWRD \
219)
220#else
221#define AR5K_INIT_CFG 0x00000000
222#endif
223
224/* Initial values */
e8f055f0 225#define AR5K_INIT_CYCRSSI_THR1 2
c6e387a2
NK		 226#define AR5K_INIT_TX_LATENCY 502
227#define AR5K_INIT_USEC 39
228#define AR5K_INIT_USEC_TURBO 79
229#define AR5K_INIT_USEC_32 31
230#define AR5K_INIT_SLOT_TIME 396
231#define AR5K_INIT_SLOT_TIME_TURBO 480
232#define AR5K_INIT_ACK_CTS_TIMEOUT 1024
233#define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800
234#define AR5K_INIT_PROG_IFS 920
235#define AR5K_INIT_PROG_IFS_TURBO 960
236#define AR5K_INIT_EIFS 3440
237#define AR5K_INIT_EIFS_TURBO 6880
238#define AR5K_INIT_SIFS 560
239#define AR5K_INIT_SIFS_TURBO 480
240#define AR5K_INIT_SH_RETRY 10
241#define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY
242#define AR5K_INIT_SSH_RETRY 32
243#define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY
244#define AR5K_INIT_TX_RETRY 10
245
246#define AR5K_INIT_TRANSMIT_LATENCY ( \
247 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
248 (AR5K_INIT_USEC) \
249)
250#define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \
251 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
252 (AR5K_INIT_USEC_TURBO) \
253)
254#define AR5K_INIT_PROTO_TIME_CNTRL ( \
255 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \
256 (AR5K_INIT_PROG_IFS) \
257)
258#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \
259 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \
260 (AR5K_INIT_PROG_IFS_TURBO) \
261)
262
fa1c114f
JS		 263/* token to use for aifs, cwmin, cwmax in MadWiFi */
264#define AR5K_TXQ_USEDEFAULT ((u32) -1)
265
266/* GENERIC CHIPSET DEFINITIONS */
267
268/* MAC Chips */
269enum ath5k_version {
270 AR5K_AR5210 = 0,
271 AR5K_AR5211 = 1,
272 AR5K_AR5212 = 2,
273};
274
275/* PHY Chips */
276enum ath5k_radio {
277 AR5K_RF5110 = 0,
278 AR5K_RF5111 = 1,
279 AR5K_RF5112 = 2,
8daeef97
NK		 280 AR5K_RF2413 = 3,
281 AR5K_RF5413 = 4,
1bef016a
NK		 282 AR5K_RF2316 = 5,
283 AR5K_RF2317 = 6,
284 AR5K_RF2425 = 7,
fa1c114f
JS		 285};
286
287/*
288 * Common silicon revision/version values
289 */
290
291enum ath5k_srev_type {
1bef016a 292 AR5K_VERSION_MAC,
fa1c114f
JS		 293 AR5K_VERSION_RAD,
294};
295
296struct ath5k_srev_name {
297 const char *sr_name;
298 enum ath5k_srev_type sr_type;
299 u_int sr_val;
300};
301
302#define AR5K_SREV_UNKNOWN 0xffff
303
1bef016a
NK		 304#define AR5K_SREV_AR5210 0x00 /* Crete */
305#define AR5K_SREV_AR5311 0x10 /* Maui 1 */
306#define AR5K_SREV_AR5311A 0x20 /* Maui 2 */
307#define AR5K_SREV_AR5311B 0x30 /* Spirit */
308#define AR5K_SREV_AR5211 0x40 /* Oahu */
309#define AR5K_SREV_AR5212 0x50 /* Venice */
310#define AR5K_SREV_AR5213 0x55 /* ??? */
311#define AR5K_SREV_AR5213A 0x59 /* Hainan */
312#define AR5K_SREV_AR2413 0x78 /* Griffin lite */
313#define AR5K_SREV_AR2414 0x70 /* Griffin */
314#define AR5K_SREV_AR5424 0x90 /* Condor */
315#define AR5K_SREV_AR5413 0xa4 /* Eagle lite */
316#define AR5K_SREV_AR5414 0xa0 /* Eagle */
e8f055f0 317#define AR5K_SREV_AR2415 0xb0 /* Talon */
1bef016a
NK		 318#define AR5K_SREV_AR5416 0xc0 /* PCI-E */
319#define AR5K_SREV_AR5418 0xca /* PCI-E */
320#define AR5K_SREV_AR2425 0xe0 /* Swan */
321#define AR5K_SREV_AR2417 0xf0 /* Nala */
fa1c114f
JS		 322
323#define AR5K_SREV_RAD_5110 0x00
324#define AR5K_SREV_RAD_5111 0x10
325#define AR5K_SREV_RAD_5111A 0x15
326#define AR5K_SREV_RAD_2111 0x20
327#define AR5K_SREV_RAD_5112 0x30
328#define AR5K_SREV_RAD_5112A 0x35
e5a4ad0d 329#define AR5K_SREV_RAD_5112B 0x36
fa1c114f
JS		 330#define AR5K_SREV_RAD_2112 0x40
331#define AR5K_SREV_RAD_2112A 0x45
e5a4ad0d 332#define AR5K_SREV_RAD_2112B 0x46
1bef016a
NK		 333#define AR5K_SREV_RAD_2413 0x50
334#define AR5K_SREV_RAD_5413 0x60
e8f055f0 335#define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */
1bef016a
NK		 336#define AR5K_SREV_RAD_2317 0x80
337#define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */
338#define AR5K_SREV_RAD_2425 0xa2
339#define AR5K_SREV_RAD_5133 0xc0
340
341#define AR5K_SREV_PHY_5211 0x30
342#define AR5K_SREV_PHY_5212 0x41
8892e4ec 343#define AR5K_SREV_PHY_5212A 0x42
e8f055f0 344#define AR5K_SREV_PHY_5212B 0x43
1bef016a
NK		 345#define AR5K_SREV_PHY_2413 0x45
346#define AR5K_SREV_PHY_5413 0x61
347#define AR5K_SREV_PHY_2425 0x70
fa1c114f
JS		 348
349/* IEEE defs */
fa1c114f
JS		 350#define IEEE80211_MAX_LEN 2500
351
352/* TODO add support to mac80211 for vendor-specific rates and modes */
353
354/*
355 * Some of this information is based on Documentation from:
356 *
357 * http://madwifi.org/wiki/ChipsetFeatures/SuperAG
358 *
359 * Modulation for Atheros' eXtended Range - range enhancing extension that is
360 * supposed to double the distance an Atheros client device can keep a
361 * connection with an Atheros access point. This is achieved by increasing
362 * the receiver sensitivity up to, -105dBm, which is about 20dB above what
363 * the 802.11 specifications demand. In addition, new (proprietary) data rates
364 * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
365 *
366 * Please note that can you either use XR or TURBO but you cannot use both,
367 * they are exclusive.
368 *
369 */
370#define MODULATION_XR 0x00000200
371/*
372 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a
373 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s
374 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g
375 * channels. To use this feature your Access Point must also suport it.
376 * There is also a distinction between "static" and "dynamic" turbo modes:
377 *
378 * - Static: is the dumb version: devices set to this mode stick to it until
379 * the mode is turned off.
380 * - Dynamic: is the intelligent version, the network decides itself if it
381 * is ok to use turbo. As soon as traffic is detected on adjacent channels
382 * (which would get used in turbo mode), or when a non-turbo station joins
383 * the network, turbo mode won't be used until the situation changes again.
384 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which
385 * monitors the used radio band in order to decide whether turbo mode may
386 * be used or not.
387 *
388 * This article claims Super G sticks to bonding of channels 5 and 6 for
389 * USA:
390 *
391 * http://www.pcworld.com/article/id,113428-page,1/article.html
392 *
393 * The channel bonding seems to be driver specific though. In addition to
394 * deciding what channels will be used, these "Turbo" modes are accomplished
395 * by also enabling the following features:
396 *
397 * - Bursting: allows multiple frames to be sent at once, rather than pausing
398 * after each frame. Bursting is a standards-compliant feature that can be
399 * used with any Access Point.
400 * - Fast frames: increases the amount of information that can be sent per
401 * frame, also resulting in a reduction of transmission overhead. It is a
402 * proprietary feature that needs to be supported by the Access Point.
403 * - Compression: data frames are compressed in real time using a Lempel Ziv
404 * algorithm. This is done transparently. Once this feature is enabled,
405 * compression and decompression takes place inside the chipset, without
406 * putting additional load on the host CPU.
407 *
408 */
409#define MODULATION_TURBO 0x00000080
410
d8ee398d
LR		 411enum ath5k_driver_mode {
412 AR5K_MODE_11A = 0,
413 AR5K_MODE_11A_TURBO = 1,
414 AR5K_MODE_11B = 2,
415 AR5K_MODE_11G = 3,
416 AR5K_MODE_11G_TURBO = 4,
417 AR5K_MODE_XR = 0,
418 AR5K_MODE_MAX = 5
fa1c114f
JS		 419};
420
19fd6e55 421
fa1c114f
JS		 422/****************\
423 TX DEFINITIONS
424\****************/
425
426/*
c6e387a2 427 * TX Status descriptor
fa1c114f
JS		 428 */
429struct ath5k_tx_status {
430 u16 ts_seqnum;
431 u16 ts_tstamp;
432 u8 ts_status;
2f7fe870
FF		 433 u8 ts_rate[4];
434 u8 ts_retry[4];
435 u8 ts_final_idx;
fa1c114f
JS		 436 s8 ts_rssi;
437 u8 ts_shortretry;
438 u8 ts_longretry;
439 u8 ts_virtcol;
440 u8 ts_antenna;
441};
442
443#define AR5K_TXSTAT_ALTRATE 0x80
444#define AR5K_TXERR_XRETRY 0x01
445#define AR5K_TXERR_FILT 0x02
446#define AR5K_TXERR_FIFO 0x04
447
448/**
449 * enum ath5k_tx_queue - Queue types used to classify tx queues.
450 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
451 * @AR5K_TX_QUEUE_DATA: A normal data queue
452 * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue
453 * @AR5K_TX_QUEUE_BEACON: The beacon queue
454 * @AR5K_TX_QUEUE_CAB: The after-beacon queue
455 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
456 */
457enum ath5k_tx_queue {
458 AR5K_TX_QUEUE_INACTIVE = 0,
459 AR5K_TX_QUEUE_DATA,
460 AR5K_TX_QUEUE_XR_DATA,
461 AR5K_TX_QUEUE_BEACON,
462 AR5K_TX_QUEUE_CAB,
463 AR5K_TX_QUEUE_UAPSD,
464};
465
466#define AR5K_NUM_TX_QUEUES 10
467#define AR5K_NUM_TX_QUEUES_NOQCU 2
468
469/*
470 * Queue syb-types to classify normal data queues.
471 * These are the 4 Access Categories as defined in
472 * WME spec. 0 is the lowest priority and 4 is the
473 * highest. Normal data that hasn't been classified
474 * goes to the Best Effort AC.
475 */
476enum ath5k_tx_queue_subtype {
477 AR5K_WME_AC_BK = 0, /*Background traffic*/
478 AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/
479 AR5K_WME_AC_VI, /*Video traffic*/
480 AR5K_WME_AC_VO, /*Voice traffic*/
481};
482
483/*
484 * Queue ID numbers as returned by the hw functions, each number
485 * represents a hw queue. If hw does not support hw queues
486 * (eg 5210) all data goes in one queue. These match
487 * d80211 definitions (net80211/MadWiFi don't use them).
488 */
489enum ath5k_tx_queue_id {
490 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0,
491 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1,
492 AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/
493 AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/
494 AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/
495 AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/
496 AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/
497 AR5K_TX_QUEUE_ID_UAPSD = 8,
498 AR5K_TX_QUEUE_ID_XR_DATA = 9,
499};
500
fa1c114f
JS		 501/*
502 * Flags to set hw queue's parameters...
503 */
504#define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */
505#define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */
506#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */
507#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */
508#define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */
4c674c60
NK		 509#define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */
510#define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */
511#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */
512#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */
513#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */
514#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/
515#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */
516#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */
517#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/
fa1c114f
JS		 518
519/*
520 * A struct to hold tx queue's parameters
521 */
522struct ath5k_txq_info {
523 enum ath5k_tx_queue tqi_type;
524 enum ath5k_tx_queue_subtype tqi_subtype;
525 u16 tqi_flags; /* Tx queue flags (see above) */
526 u32 tqi_aifs; /* Arbitrated Interframe Space */
527 s32 tqi_cw_min; /* Minimum Contention Window */
528 s32 tqi_cw_max; /* Maximum Contention Window */
529 u32 tqi_cbr_period; /* Constant bit rate period */
530 u32 tqi_cbr_overflow_limit;
531 u32 tqi_burst_time;
532 u32 tqi_ready_time; /* Not used */
533};
534
535/*
536 * Transmit packet types.
c6e387a2
NK		 537 * used on tx control descriptor
538 * TODO: Use them inside base.c corectly
fa1c114f
JS		 539 */
540enum ath5k_pkt_type {
541 AR5K_PKT_TYPE_NORMAL = 0,
542 AR5K_PKT_TYPE_ATIM = 1,
543 AR5K_PKT_TYPE_PSPOLL = 2,
544 AR5K_PKT_TYPE_BEACON = 3,
545 AR5K_PKT_TYPE_PROBE_RESP = 4,
546 AR5K_PKT_TYPE_PIFS = 5,
547};
548
549/*
550 * TX power and TPC settings
551 */
552#define AR5K_TXPOWER_OFDM(_r, _v) ( \
553 ((0 & 1) << ((_v) + 6)) | \
8f655dde 554 (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \
fa1c114f
JS		 555)
556
557#define AR5K_TXPOWER_CCK(_r, _v) ( \
8f655dde 558 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \
fa1c114f
JS		 559)
560
561/*
562 * DMA size definitions (2^n+2)
563 */
564enum ath5k_dmasize {
565 AR5K_DMASIZE_4B = 0,
566 AR5K_DMASIZE_8B,
567 AR5K_DMASIZE_16B,
568 AR5K_DMASIZE_32B,
569 AR5K_DMASIZE_64B,
570 AR5K_DMASIZE_128B,
571 AR5K_DMASIZE_256B,
572 AR5K_DMASIZE_512B
573};
574
575
576/****************\
577 RX DEFINITIONS
578\****************/
579
580/*
c6e387a2 581 * RX Status descriptor
fa1c114f
JS		 582 */
583struct ath5k_rx_status {
584 u16 rs_datalen;
585 u16 rs_tstamp;
586 u8 rs_status;
587 u8 rs_phyerr;
588 s8 rs_rssi;
589 u8 rs_keyix;
590 u8 rs_rate;
591 u8 rs_antenna;
592 u8 rs_more;
593};
594
595#define AR5K_RXERR_CRC 0x01
596#define AR5K_RXERR_PHY 0x02
597#define AR5K_RXERR_FIFO 0x04
598#define AR5K_RXERR_DECRYPT 0x08
599#define AR5K_RXERR_MIC 0x10
600#define AR5K_RXKEYIX_INVALID ((u8) - 1)
601#define AR5K_TXKEYIX_INVALID ((u32) - 1)
602
fa1c114f 603
fa1c114f
JS		 604/**************************\
605 BEACON TIMERS DEFINITIONS
606\**************************/
607
608#define AR5K_BEACON_PERIOD 0x0000ffff
609#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/
610#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/
611
612#if 0
613/**
614 * struct ath5k_beacon_state - Per-station beacon timer state.
615 * @bs_interval: in TU's, can also include the above flags
616 * @bs_cfp_max_duration: if non-zero hw is setup to coexist with a
617 * Point Coordination Function capable AP
618 */
619struct ath5k_beacon_state {
620 u32 bs_next_beacon;
621 u32 bs_next_dtim;
622 u32 bs_interval;
623 u8 bs_dtim_period;
624 u8 bs_cfp_period;
625 u16 bs_cfp_max_duration;
626 u16 bs_cfp_du_remain;
627 u16 bs_tim_offset;
628 u16 bs_sleep_duration;
629 u16 bs_bmiss_threshold;
630 u32 bs_cfp_next;
631};
632#endif
633
634
635/*
636 * TSF to TU conversion:
637 *
638 * TSF is a 64bit value in usec (microseconds).
e535c1ac
BR		 639 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
640 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
fa1c114f
JS		 641 */
642#define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
643
644
c6e387a2
NK		 645/*******************************\
646 GAIN OPTIMIZATION DEFINITIONS
647\*******************************/
648
649enum ath5k_rfgain {
650 AR5K_RFGAIN_INACTIVE = 0,
6f3b414a 651 AR5K_RFGAIN_ACTIVE,
c6e387a2
NK		 652 AR5K_RFGAIN_READ_REQUESTED,
653 AR5K_RFGAIN_NEED_CHANGE,
654};
655
c6e387a2 656struct ath5k_gain {
6f3b414a
NK		 657 u8 g_step_idx;
658 u8 g_current;
659 u8 g_target;
660 u8 g_low;
661 u8 g_high;
662 u8 g_f_corr;
663 u8 g_state;
c6e387a2
NK		 664};
665
fa1c114f
JS		 666/********************\
667 COMMON DEFINITIONS
668\********************/
669
fa1c114f
JS		 670#define AR5K_SLOT_TIME_9 396
671#define AR5K_SLOT_TIME_20 880
672#define AR5K_SLOT_TIME_MAX 0xffff
673
674/* channel_flags */
675#define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */
676#define CHANNEL_TURBO 0x0010 /* Turbo Channel */
677#define CHANNEL_CCK 0x0020 /* CCK channel */
678#define CHANNEL_OFDM 0x0040 /* OFDM channel */
679#define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */
680#define CHANNEL_5GHZ 0x0100 /* 5GHz channel */
681#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */
682#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */
683#define CHANNEL_XR 0x0800 /* XR channel */
684
685#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
686#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
687#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
688#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
689#define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
690#define CHANNEL_108A CHANNEL_T
691#define CHANNEL_108G CHANNEL_TG
692#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
693
694#define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \
695 CHANNEL_TURBO)
696
697#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL & ~CHANNEL_TURBO)
698#define CHANNEL_MODES CHANNEL_ALL
699
700/*
c6e387a2
NK		 701 * Used internaly for reset_tx_queue).
702 * Also see struct struct ieee80211_channel.
fa1c114f 703 */
d8ee398d
LR		 704#define IS_CHAN_XR(_c) ((_c.hw_value & CHANNEL_XR) != 0)
705#define IS_CHAN_B(_c) ((_c.hw_value & CHANNEL_B) != 0)
fa1c114f
JS		 706
707/*
c6e387a2 708 * The following structure is used to map 2GHz channels to
fa1c114f 709 * 5GHz Atheros channels.
c6e387a2 710 * TODO: Clean up
fa1c114f
JS		 711 */
712struct ath5k_athchan_2ghz {
713 u32 a2_flags;
714 u16 a2_athchan;
715};
716
63266a65 717
c6e387a2
NK		 718/******************\
719 RATE DEFINITIONS
720\******************/
fa1c114f 721
fa1c114f 722/**
63266a65 723 * Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32.
fa1c114f 724 *
63266a65 725 * The rate code is used to get the RX rate or set the TX rate on the
fa1c114f
JS		 726 * hardware descriptors. It is also used for internal modulation control
727 * and settings.
728 *
63266a65 729 * This is the hardware rate map we are aware of:
fa1c114f 730 *
63266a65 731 * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08
fa1c114f
JS		 732 * rate_kbps 3000 1000 ? ? ? 2000 500 48000
733 *
63266a65 734 * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10
fa1c114f
JS		 735 * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ?
736 *
737 * rate_code 17 18 19 20 21 22 23 24
738 * rate_kbps ? ? ? ? ? ? ? 11000
739 *
740 * rate_code 25 26 27 28 29 30 31 32
63266a65
BR		 741 * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ?
742 *
743 * "S" indicates CCK rates with short preamble.
fa1c114f 744 *
63266a65
BR		 745 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the
746 * lowest 4 bits, so they are the same as below with a 0xF mask.
747 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M).
748 * We handle this in ath5k_setup_bands().
fa1c114f 749 */
63266a65 750#define AR5K_MAX_RATES 32
fa1c114f 751
63266a65
BR		 752/* B */
753#define ATH5K_RATE_CODE_1M 0x1B
754#define ATH5K_RATE_CODE_2M 0x1A
755#define ATH5K_RATE_CODE_5_5M 0x19
756#define ATH5K_RATE_CODE_11M 0x18
757/* A and G */
758#define ATH5K_RATE_CODE_6M 0x0B
759#define ATH5K_RATE_CODE_9M 0x0F
760#define ATH5K_RATE_CODE_12M 0x0A
761#define ATH5K_RATE_CODE_18M 0x0E
762#define ATH5K_RATE_CODE_24M 0x09
763#define ATH5K_RATE_CODE_36M 0x0D
764#define ATH5K_RATE_CODE_48M 0x08
765#define ATH5K_RATE_CODE_54M 0x0C
766/* XR */
767#define ATH5K_RATE_CODE_XR_500K 0x07
768#define ATH5K_RATE_CODE_XR_1M 0x02
769#define ATH5K_RATE_CODE_XR_2M 0x06
770#define ATH5K_RATE_CODE_XR_3M 0x01
fa1c114f 771
c6e387a2
NK		 772/* adding this flag to rate_code enables short preamble */
773#define AR5K_SET_SHORT_PREAMBLE 0x04
fa1c114f
JS		 774
775/*
776 * Crypto definitions
777 */
778
779#define AR5K_KEYCACHE_SIZE 8
780
781/***********************\
782 HW RELATED DEFINITIONS
783\***********************/
784
785/*
786 * Misc definitions
787 */
788#define AR5K_RSSI_EP_MULTIPLIER (1<<7)
789
790#define AR5K_ASSERT_ENTRY(_e, _s) do { \
791 if (_e >= _s) \
792 return (false); \
793} while (0)
794
fa1c114f
JS		 795/*
796 * Hardware interrupt abstraction
797 */
798
799/**
800 * enum ath5k_int - Hardware interrupt masks helpers
801 *
802 * @AR5K_INT_RX: mask to identify received frame interrupts, of type
803 * AR5K_ISR_RXOK or AR5K_ISR_RXERR
804 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?)
805 * @AR5K_INT_RXNOFRM: No frame received (?)
806 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The
807 * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's
808 * LinkPtr is NULL. For more details, refer to:
809 * http://www.freepatentsonline.com/20030225739.html
810 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors).
811 * Note that Rx overrun is not always fatal, on some chips we can continue
812 * operation without reseting the card, that's why int_fatal is not
813 * common for all chips.
814 * @AR5K_INT_TX: mask to identify received frame interrupts, of type
815 * AR5K_ISR_TXOK or AR5K_ISR_TXERR
816 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?)
817 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold
818 * We currently do increments on interrupt by
819 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
820 * @AR5K_INT_MIB: Indicates the Management Information Base counters should be
821 * checked. We should do this with ath5k_hw_update_mib_counters() but
822 * it seems we should also then do some noise immunity work.
823 * @AR5K_INT_RXPHY: RX PHY Error
4c674c60 824 * @AR5K_INT_RXKCM: RX Key cache miss
fa1c114f
JS		 825 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
826 * beacon that must be handled in software. The alternative is if you
827 * have VEOL support, in that case you let the hardware deal with things.
828 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
829 * beacons from the AP have associated with, we should probably try to
830 * reassociate. When in IBSS mode this might mean we have not received
831 * any beacons from any local stations. Note that every station in an
832 * IBSS schedules to send beacons at the Target Beacon Transmission Time
833 * (TBTT) with a random backoff.
834 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ??
835 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now
836 * until properly handled
837 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA
838 * errors. These types of errors we can enable seem to be of type
839 * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR.
4c674c60 840 * @AR5K_INT_GLOBAL: Used to clear and set the IER
fa1c114f
JS		 841 * @AR5K_INT_NOCARD: signals the card has been removed
842 * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same
843 * bit value
844 *
845 * These are mapped to take advantage of some common bits
846 * between the MACs, to be able to set intr properties
847 * easier. Some of them are not used yet inside hw.c. Most map
848 * to the respective hw interrupt value as they are common amogst different
849 * MACs.
850 */
851enum ath5k_int {
4c674c60 852 AR5K_INT_RXOK = 0x00000001,
fa1c114f 853 AR5K_INT_RXDESC = 0x00000002,
4c674c60 854 AR5K_INT_RXERR = 0x00000004,
fa1c114f
JS		 855 AR5K_INT_RXNOFRM = 0x00000008,
856 AR5K_INT_RXEOL = 0x00000010,
857 AR5K_INT_RXORN = 0x00000020,
4c674c60 858 AR5K_INT_TXOK = 0x00000040,
fa1c114f 859 AR5K_INT_TXDESC = 0x00000080,
4c674c60
NK		 860 AR5K_INT_TXERR = 0x00000100,
861 AR5K_INT_TXNOFRM = 0x00000200,
862 AR5K_INT_TXEOL = 0x00000400,
fa1c114f
JS		 863 AR5K_INT_TXURN = 0x00000800,
864 AR5K_INT_MIB = 0x00001000,
4c674c60 865 AR5K_INT_SWI = 0x00002000,
fa1c114f
JS		 866 AR5K_INT_RXPHY = 0x00004000,
867 AR5K_INT_RXKCM = 0x00008000,
868 AR5K_INT_SWBA = 0x00010000,
4c674c60 869 AR5K_INT_BRSSI = 0x00020000,
fa1c114f 870 AR5K_INT_BMISS = 0x00040000,
4c674c60
NK		 871 AR5K_INT_FATAL = 0x00080000, /* Non common */
872 AR5K_INT_BNR = 0x00100000, /* Non common */
873 AR5K_INT_TIM = 0x00200000, /* Non common */
874 AR5K_INT_DTIM = 0x00400000, /* Non common */
875 AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */
876 AR5K_INT_GPIO = 0x01000000,
877 AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */
878 AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */
879 AR5K_INT_RX_DOPPLER = 0x08000000, /* Non common */
880 AR5K_INT_QCBRORN = 0x10000000, /* Non common */
881 AR5K_INT_QCBRURN = 0x20000000, /* Non common */
882 AR5K_INT_QTRIG = 0x40000000, /* Non common */
883 AR5K_INT_GLOBAL = 0x80000000,
884
885 AR5K_INT_COMMON = AR5K_INT_RXOK
886 | AR5K_INT_RXDESC
887 | AR5K_INT_RXERR
888 | AR5K_INT_RXNOFRM
889 | AR5K_INT_RXEOL
890 | AR5K_INT_RXORN
891 | AR5K_INT_TXOK
892 | AR5K_INT_TXDESC
893 | AR5K_INT_TXERR
894 | AR5K_INT_TXNOFRM
895 | AR5K_INT_TXEOL
896 | AR5K_INT_TXURN
897 | AR5K_INT_MIB
898 | AR5K_INT_SWI
899 | AR5K_INT_RXPHY
900 | AR5K_INT_RXKCM
901 | AR5K_INT_SWBA
902 | AR5K_INT_BRSSI
903 | AR5K_INT_BMISS
904 | AR5K_INT_GPIO
905 | AR5K_INT_GLOBAL,
906
fa1c114f
JS		 907 AR5K_INT_NOCARD = 0xffffffff
908};
909
910/*
911 * Power management
912 */
913enum ath5k_power_mode {
914 AR5K_PM_UNDEFINED = 0,
915 AR5K_PM_AUTO,
916 AR5K_PM_AWAKE,
917 AR5K_PM_FULL_SLEEP,
918 AR5K_PM_NETWORK_SLEEP,
919};
920
921/*
922 * These match net80211 definitions (not used in
c6e387a2
NK		 923 * mac80211).
924 * TODO: Clean this up
fa1c114f
JS		 925 */
926#define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/
927#define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/
928#define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/
929#define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/
930#define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/
931
932/* GPIO-controlled software LED */
933#define AR5K_SOFTLED_PIN 0
934#define AR5K_SOFTLED_ON 0
935#define AR5K_SOFTLED_OFF 1
936
937/*
938 * Chipset capabilities -see ath5k_hw_get_capability-
939 * get_capability function is not yet fully implemented
c6e387a2
NK		 940 * in ath5k so most of these don't work yet...
941 * TODO: Implement these & merge with _TUNE_ stuff above
fa1c114f
JS		 942 */
943enum ath5k_capability_type {
944 AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */
945 AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */
946 AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */
947 AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */
948 AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */
949 AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */
950 AR5K_CAP_VEOL = 7, /* Supports virtual EOL */
951 AR5K_CAP_COMPRESSION = 8, /* Supports compression */
952 AR5K_CAP_BURST = 9, /* Supports packet bursting */
953 AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */
954 AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */
955 AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */
956 AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */
957 AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */
958 AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */
959 AR5K_CAP_XR = 16, /* Supports XR mode */
960 AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */
961 AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */
962 AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */
963 AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */
964};
965
400ec45a
LR		 966
967/* XXX: we *may* move cap_range stuff to struct wiphy */
fa1c114f
JS		 968struct ath5k_capabilities {
969 /*
970 * Supported PHY modes
971 * (ie. CHANNEL_A, CHANNEL_B, ...)
972 */
d8ee398d 973 DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX);
fa1c114f
JS		 974
975 /*
976 * Frequency range (without regulation restrictions)
977 */
978 struct {
979 u16 range_2ghz_min;
980 u16 range_2ghz_max;
981 u16 range_5ghz_min;
982 u16 range_5ghz_max;
983 } cap_range;
984
fa1c114f
JS		 985 /*
986 * Values stored in the EEPROM (some of them...)
987 */
988 struct ath5k_eeprom_info cap_eeprom;
989
990 /*
991 * Queue information
992 */
993 struct {
994 u8 q_tx_num;
995 } cap_queues;
996};
997
998
999/***************************************\
1000 HARDWARE ABSTRACTION LAYER STRUCTURE
1001\***************************************/
1002
1003/*
1004 * Misc defines
1005 */
1006
1007#define AR5K_MAX_GPIO 10
1008#define AR5K_MAX_RF_BANKS 8
1009
c6e387a2 1010/* TODO: Clean up and merge with ath5k_softc */
fa1c114f
JS		 1011struct ath5k_hw {
1012 u32 ah_magic;
1013
1014 struct ath5k_softc *ah_sc;
1015 void __iomem *ah_iobase;
1016
1017 enum ath5k_int ah_imr;
1018
05c914fe 1019 enum nl80211_iftype ah_op_mode;
fa1c114f
JS		 1020 enum ath5k_power_mode ah_power_mode;
1021 struct ieee80211_channel ah_current_channel;
1022 bool ah_turbo;
1023 bool ah_calibration;
1024 bool ah_running;
1025 bool ah_single_chip;
f650470a 1026 bool ah_combined_mic;
fa1c114f
JS		 1027
1028 u32 ah_mac_srev;
1029 u16 ah_mac_version;
1030 u16 ah_mac_revision;
1031 u16 ah_phy_revision;
1032 u16 ah_radio_5ghz_revision;
1033 u16 ah_radio_2ghz_revision;
1034
1035 enum ath5k_version ah_version;
1036 enum ath5k_radio ah_radio;
1037 u32 ah_phy;
1038
1039 bool ah_5ghz;
1040 bool ah_2ghz;
1041
1042#define ah_regdomain ah_capabilities.cap_regdomain.reg_current
1043#define ah_regdomain_hw ah_capabilities.cap_regdomain.reg_hw
1044#define ah_modes ah_capabilities.cap_mode
1045#define ah_ee_version ah_capabilities.cap_eeprom.ee_version
1046
1047 u32 ah_atim_window;
1048 u32 ah_aifs;
1049 u32 ah_cw_min;
1050 u32 ah_cw_max;
1051 bool ah_software_retry;
1052 u32 ah_limit_tx_retries;
1053
1054 u32 ah_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
1055 bool ah_ant_diversity;
1056
1057 u8 ah_sta_id[ETH_ALEN];
1058
f07a6c49 1059 /* Current BSSID we are trying to assoc to / create.
fa1c114f
JS		 1060 * This is passed by mac80211 on config_interface() and cached here for
1061 * use in resets */
1062 u8 ah_bssid[ETH_ALEN];
f07a6c49 1063 u8 ah_bssid_mask[ETH_ALEN];
fa1c114f
JS		 1064
1065 u32 ah_gpio[AR5K_MAX_GPIO];
1066 int ah_gpio_npins;
1067
1068 struct ath5k_capabilities ah_capabilities;
1069
1070 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES];
1071 u32 ah_txq_status;
1072 u32 ah_txq_imr_txok;
1073 u32 ah_txq_imr_txerr;
1074 u32 ah_txq_imr_txurn;
1075 u32 ah_txq_imr_txdesc;
1076 u32 ah_txq_imr_txeol;
4c674c60
NK		 1077 u32 ah_txq_imr_cbrorn;
1078 u32 ah_txq_imr_cbrurn;
1079 u32 ah_txq_imr_qtrig;
1080 u32 ah_txq_imr_nofrm;
1081 u32 ah_txq_isr;
fa1c114f
JS		 1082 u32 *ah_rf_banks;
1083 size_t ah_rf_banks_size;
8892e4ec 1084 size_t ah_rf_regs_count;
fa1c114f 1085 struct ath5k_gain ah_gain;
8892e4ec 1086 u8 ah_offset[AR5K_MAX_RF_BANKS];
fa1c114f 1087
8f655dde 1088
fa1c114f 1089 struct {
8f655dde
NK		 1090 /* Temporary tables used for interpolation */
1091 u8 tmpL[AR5K_EEPROM_N_PD_GAINS]
1092 [AR5K_EEPROM_POWER_TABLE_SIZE];
1093 u8 tmpR[AR5K_EEPROM_N_PD_GAINS]
1094 [AR5K_EEPROM_POWER_TABLE_SIZE];
1095 u8 txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2];
1096 u16 txp_rates_power_table[AR5K_MAX_RATES];
1097 u8 txp_min_idx;
fa1c114f 1098 bool txp_tpc;
8f655dde
NK		 1099 /* Values in 0.25dB units */
1100 s16 txp_min_pwr;
1101 s16 txp_max_pwr;
1102 s16 txp_offset;
fa1c114f 1103 s16 txp_ofdm;
8f655dde
NK		 1104 /* Values in dB units */
1105 s16 txp_cck_ofdm_pwr_delta;
1106 s16 txp_cck_ofdm_gainf_delta;
fa1c114f
JS		 1107 } ah_txpower;
1108
1109 struct {
1110 bool r_enabled;
1111 int r_last_alert;
1112 struct ieee80211_channel r_last_channel;
1113 } ah_radar;
1114
1115 /* noise floor from last periodic calibration */
1116 s32 ah_noise_floor;
1117
1118 /*
1119 * Function pointers
1120 */
c6e387a2
NK		 1121 int (*ah_setup_rx_desc)(struct ath5k_hw *ah, struct ath5k_desc *desc,
1122 u32 size, unsigned int flags);
fa1c114f
JS		 1123 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1124 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
1125 unsigned int, unsigned int, unsigned int, unsigned int,
1126 unsigned int, unsigned int, unsigned int);
c6e387a2 1127 int (*ah_setup_mrr_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
fa1c114f
JS		 1128 unsigned int, unsigned int, unsigned int, unsigned int,
1129 unsigned int, unsigned int);
b47f407b
BR		 1130 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1131 struct ath5k_tx_status *);
1132 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1133 struct ath5k_rx_status *);
fa1c114f
JS		 1134};
1135
1136/*
1137 * Prototypes
1138 */
1139
fa1c114f
JS		 1140/* Attach/Detach Functions */
1141extern struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version);
fa1c114f 1142extern void ath5k_hw_detach(struct ath5k_hw *ah);
c6e387a2 1143
0ed4548f
BC		 1144/* LED functions */
1145extern int ath5k_init_leds(struct ath5k_softc *sc);
1146extern void ath5k_led_enable(struct ath5k_softc *sc);
1147extern void ath5k_led_off(struct ath5k_softc *sc);
1148extern void ath5k_unregister_leds(struct ath5k_softc *sc);
1149
fa1c114f 1150/* Reset Functions */
c6e387a2 1151extern int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial);
05c914fe 1152extern int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, struct ieee80211_channel *channel, bool change_channel);
fa1c114f
JS		 1153/* Power management functions */
1154extern int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration);
c6e387a2 1155
fa1c114f 1156/* DMA Related Functions */
c6e387a2 1157extern void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);
fa1c114f 1158extern int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah);
c6e387a2
NK		 1159extern u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);
1160extern void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
1161extern int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);
fa1c114f 1162extern int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue);
c6e387a2
NK		 1163extern u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);
1164extern int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,
1165 u32 phys_addr);
fa1c114f
JS		 1166extern int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
1167/* Interrupt handling */
1168extern bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
1169extern int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
c6e387a2
NK		 1170extern enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum
1171ath5k_int new_mask);
194828a2 1172extern void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, struct ieee80211_low_level_stats *stats);
c6e387a2 1173
fa1c114f 1174/* EEPROM access functions */
c6e387a2 1175extern int ath5k_eeprom_init(struct ath5k_hw *ah);
8f655dde 1176extern void ath5k_eeprom_detach(struct ath5k_hw *ah);
c6e387a2 1177extern int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac);
e8f055f0 1178extern bool ath5k_eeprom_is_hb63(struct ath5k_hw *ah);
c6e387a2 1179
fa1c114f
JS		 1180/* Protocol Control Unit Functions */
1181extern int ath5k_hw_set_opmode(struct ath5k_hw *ah);
1182/* BSSID Functions */
1183extern void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac);
1184extern int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
1185extern void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id);
1186extern int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
1187/* Receive start/stop functions */
1188extern void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
c6e387a2 1189extern void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
fa1c114f
JS		 1190/* RX Filter functions */
1191extern void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
c6e387a2 1192extern int ath5k_hw_set_mcast_filter_idx(struct ath5k_hw *ah, u32 index);
fa1c114f
JS		 1193extern int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index);
1194extern u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
1195extern void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
c6e387a2 1196/* Beacon control functions */
fa1c114f
JS		 1197extern u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah);
1198extern u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
8cab7581 1199extern void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64);
fa1c114f
JS		 1200extern void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
1201extern void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval);
1202#if 0
1203extern int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah, const struct ath5k_beacon_state *state);
1204extern void ath5k_hw_reset_beacon(struct ath5k_hw *ah);
1205extern int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr);
1206#endif
fa1c114f
JS		 1207/* ACK bit rate */
1208void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high);
1209/* ACK/CTS Timeouts */
1210extern int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout);
1211extern unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah);
1212extern int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout);
1213extern unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah);
1214/* Key table (WEP) functions */
1215extern int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry);
1216extern int ath5k_hw_is_key_valid(struct ath5k_hw *ah, u16 entry);
1217extern int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry, const struct ieee80211_key_conf *key, const u8 *mac);
1218extern int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac);
c6e387a2 1219
fa1c114f 1220/* Queue Control Unit, DFS Control Unit Functions */
fa1c114f 1221extern int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, struct ath5k_txq_info *queue_info);
c6e387a2
NK		 1222extern int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
1223 const struct ath5k_txq_info *queue_info);
1224extern int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
1225 enum ath5k_tx_queue queue_type,
1226 struct ath5k_txq_info *queue_info);
1227extern u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);
fa1c114f
JS		 1228extern void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1229extern int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);
fa1c114f 1230extern unsigned int ath5k_hw_get_slot_time(struct ath5k_hw *ah);
c6e387a2
NK		 1231extern int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time);
1232
fa1c114f 1233/* Hardware Descriptor Functions */
c6e387a2
NK		 1234extern int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
1235
fa1c114f
JS		 1236/* GPIO Functions */
1237extern void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
fa1c114f 1238extern int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
c6e387a2 1239extern int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
fa1c114f
JS		 1240extern u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
1241extern int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
1242extern void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level);
c6e387a2 1243
fa1c114f 1244/* Misc functions */
c6e387a2 1245int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
fa1c114f 1246extern int ath5k_hw_get_capability(struct ath5k_hw *ah, enum ath5k_capability_type cap_type, u32 capability, u32 *result);
c6e387a2
NK		 1247extern int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
1248extern int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
fa1c114f
JS		 1249
1250/* Initial register settings functions */
1251extern int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
c6e387a2 1252
fa1c114f 1253/* Initialize RF */
8892e4ec
NK		 1254extern int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
1255 struct ieee80211_channel *channel,
1256 unsigned int mode);
6f3b414a
NK		 1257extern int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq);
1258extern enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);
1259extern int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);
fa1c114f
JS		 1260/* PHY/RF channel functions */
1261extern bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags);
1262extern int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel);
1263/* PHY calibration */
1264extern int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, struct ieee80211_channel *channel);
c6e387a2 1265extern int ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq);
fa1c114f
JS		 1266/* Misc PHY functions */
1267extern u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan);
1268extern void ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant);
1269extern unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah);
c6e387a2 1270extern int ath5k_hw_phy_disable(struct ath5k_hw *ah);
fa1c114f 1271/* TX power setup */
8f655dde
NK		 1272extern int ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, u8 ee_mode, u8 txpower);
1273extern int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 ee_mode, u8 txpower);
fa1c114f 1274
c6e387a2
NK		 1275/*
1276 * Functions used internaly
1277 */
1278
1279/*
1280 * Translate usec to hw clock units
e8f055f0 1281 * TODO: Half/quarter rate
c6e387a2
NK		 1282 */
1283static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo)
1284{
1285 return turbo ? (usec * 80) : (usec * 40);
1286}
fa1c114f 1287
c6e387a2
NK		 1288/*
1289 * Translate hw clock units to usec
e8f055f0 1290 * TODO: Half/quarter rate
c6e387a2
NK		 1291 */
1292static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo)
1293{
1294 return turbo ? (clock / 80) : (clock / 40);
1295}
1296
1297/*
1298 * Read from a register
1299 */
fa1c114f
JS		 1300static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
1301{
1302 return ioread32(ah->ah_iobase + reg);
1303}
1304
c6e387a2
NK		 1305/*
1306 * Write to a register
1307 */
fa1c114f
JS		 1308static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1309{
1310 iowrite32(val, ah->ah_iobase + reg);
1311}
1312
c6e387a2
NK		 1313#if defined(_ATH5K_RESET) || defined(_ATH5K_PHY)
1314/*
1315 * Check if a register write has been completed
1316 */
1317static int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag,
1318 u32 val, bool is_set)
1319{
1320 int i;
1321 u32 data;
1322
1323 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
1324 data = ath5k_hw_reg_read(ah, reg);
1325 if (is_set && (data & flag))
1326 break;
1327 else if ((data & flag) == val)
1328 break;
1329 udelay(15);
1330 }
1331
1332 return (i <= 0) ? -EAGAIN : 0;
1333}
1334#endif
1335
1336static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
1337{
1338 u32 retval = 0, bit, i;
1339
1340 for (i = 0; i < bits; i++) {
1341 bit = (val >> i) & 1;
1342 retval = (retval << 1) | bit;
1343 }
1344
1345 return retval;
1346}
1347
fd6effca
BC		 1348static inline int ath5k_pad_size(int hdrlen)
1349{
1350 return (hdrlen < 24) ? 0 : hdrlen & 3;
1351}
1352
fa1c114f 1353#endif
Linux kernel - Deliverables
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