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[deliverable/linux.git] / drivers / net / wireless / ath5k / ath5k.h
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fa1c114f
JS		 1/*
2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#ifndef _ATH5K_H
19#define _ATH5K_H
20
c6e387a2
NK		 21/* TODO: Clean up channel debuging -doesn't work anyway- and start
22 * working on reg. control code using all available eeprom information
23 * -rev. engineering needed- */
fa1c114f
JS		 24#define CHAN_DEBUG 0
25
26#include <linux/io.h>
27#include <linux/types.h>
28#include <net/mac80211.h>
29
c6e387a2
NK		 30/* RX/TX descriptor hw structs
31 * TODO: Driver part should only see sw structs */
32#include "desc.h"
33
34/* EEPROM structs/offsets
35 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities)
36 * and clean up common bits, then introduce set/get functions in eeprom.c */
37#include "eeprom.h"
fa1c114f
JS		 38
39/* PCI IDs */
40#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */
41#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */
42#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */
43#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */
44#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */
45#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */
46#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */
47#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */
48#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */
49#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */
50#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */
51#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */
52#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */
53#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */
54#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
55#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
56#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */
57#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */
58#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */
59#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */
60#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */
61#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */
62#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */
63#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */
64#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */
65#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */
66#define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */
67#define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */
68
69/****************************\
70 GENERIC DRIVER DEFINITIONS
71\****************************/
72
73#define ATH5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__)
74
75#define ATH5K_PRINTK(_sc, _level, _fmt, ...) \
76 printk(_level "ath5k %s: " _fmt, \
77 ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \
78 ##__VA_ARGS__)
79
80#define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \
81 if (net_ratelimit()) \
82 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \
83 } while (0)
84
85#define ATH5K_INFO(_sc, _fmt, ...) \
86 ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__)
87
88#define ATH5K_WARN(_sc, _fmt, ...) \
89 ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__)
90
91#define ATH5K_ERR(_sc, _fmt, ...) \
92 ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__)
93
c6e387a2
NK		 94/*
95 * AR5K REGISTER ACCESS
96 */
97
98/* Some macros to read/write fields */
99
100/* First shift, then mask */
101#define AR5K_REG_SM(_val, _flags) \
102 (((_val) << _flags##_S) & (_flags))
103
104/* First mask, then shift */
105#define AR5K_REG_MS(_val, _flags) \
106 (((_val) & (_flags)) >> _flags##_S)
107
108/* Some registers can hold multiple values of interest. For this
109 * reason when we want to write to these registers we must first
110 * retrieve the values which we do not want to clear (lets call this
111 * old_data) and then set the register with this and our new_value:
112 * ( old_data | new_value) */
113#define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \
114 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
115 (((_val) << _flags##_S) & (_flags)), _reg)
116
117#define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \
118 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \
119 (_mask)) | (_flags), _reg)
120
121#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \
122 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
123
124#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \
125 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
126
127/* Access to PHY registers */
128#define AR5K_PHY_READ(ah, _reg) \
129 ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2))
130
131#define AR5K_PHY_WRITE(ah, _reg, _val) \
132 ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2))
133
134/* Access QCU registers per queue */
135#define AR5K_REG_READ_Q(ah, _reg, _queue) \
136 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \
137
138#define AR5K_REG_WRITE_Q(ah, _reg, _queue) \
139 ath5k_hw_reg_write(ah, (1 << _queue), _reg)
140
141#define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \
142 _reg |= 1 << _queue; \
143} while (0)
144
145#define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \
146 _reg &= ~(1 << _queue); \
147} while (0)
148
149/* Used while writing initvals */
150#define AR5K_REG_WAIT(_i) do { \
151 if (_i % 64) \
152 udelay(1); \
153} while (0)
154
155/* Register dumps are done per operation mode */
156#define AR5K_INI_RFGAIN_5GHZ 0
157#define AR5K_INI_RFGAIN_2GHZ 1
158
159/* TODO: Clean this up */
160#define AR5K_INI_VAL_11A 0
161#define AR5K_INI_VAL_11A_TURBO 1
162#define AR5K_INI_VAL_11B 2
163#define AR5K_INI_VAL_11G 3
164#define AR5K_INI_VAL_11G_TURBO 4
165#define AR5K_INI_VAL_XR 0
166#define AR5K_INI_VAL_MAX 5
167
168#define AR5K_RF5111_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS
169#define AR5K_RF5112_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS
170
171/* Used for BSSID etc manipulation */
172#define AR5K_LOW_ID(_a)( \
173(_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24 \
174)
175
176#define AR5K_HIGH_ID(_a) ((_a)[4] | (_a)[5] << 8)
177
fa1c114f
JS		 178/*
179 * Some tuneable values (these should be changeable by the user)
c6e387a2 180 * TODO: Make use of them and add more options OR use debug/configfs
fa1c114f
JS		 181 */
182#define AR5K_TUNE_DMA_BEACON_RESP 2
183#define AR5K_TUNE_SW_BEACON_RESP 10
184#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0
185#define AR5K_TUNE_RADAR_ALERT false
186#define AR5K_TUNE_MIN_TX_FIFO_THRES 1
187#define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_LEN / 64) + 1)
188#define AR5K_TUNE_REGISTER_TIMEOUT 20000
189/* Register for RSSI threshold has a mask of 0xff, so 255 seems to
190 * be the max value. */
c6e387a2 191#define AR5K_TUNE_RSSI_THRES 129
fa1c114f
JS		 192/* This must be set when setting the RSSI threshold otherwise it can
193 * prevent a reset. If AR5K_RSSI_THR is read after writing to it
194 * the BMISS_THRES will be seen as 0, seems harware doesn't keep
195 * track of it. Max value depends on harware. For AR5210 this is just 7.
196 * For AR5211+ this seems to be up to 255. */
c6e387a2 197#define AR5K_TUNE_BMISS_THRES 7
fa1c114f
JS		 198#define AR5K_TUNE_REGISTER_DWELL_TIME 20000
199#define AR5K_TUNE_BEACON_INTERVAL 100
200#define AR5K_TUNE_AIFS 2
201#define AR5K_TUNE_AIFS_11B 2
202#define AR5K_TUNE_AIFS_XR 0
203#define AR5K_TUNE_CWMIN 15
204#define AR5K_TUNE_CWMIN_11B 31
205#define AR5K_TUNE_CWMIN_XR 3
206#define AR5K_TUNE_CWMAX 1023
207#define AR5K_TUNE_CWMAX_11B 1023
208#define AR5K_TUNE_CWMAX_XR 7
209#define AR5K_TUNE_NOISE_FLOOR -72
210#define AR5K_TUNE_MAX_TXPOWER 60
211#define AR5K_TUNE_DEFAULT_TXPOWER 30
212#define AR5K_TUNE_TPC_TXPOWER true
213#define AR5K_TUNE_ANT_DIVERSITY true
214#define AR5K_TUNE_HWTXTRIES 4
215
c6e387a2
NK		 216#define AR5K_INIT_CARR_SENSE_EN 1
217
218/*Swap RX/TX Descriptor for big endian archs*/
219#if defined(__BIG_ENDIAN)
220#define AR5K_INIT_CFG ( \
221 AR5K_CFG_SWTD | AR5K_CFG_SWRD \
222)
223#else
224#define AR5K_INIT_CFG 0x00000000
225#endif
226
227/* Initial values */
228#define AR5K_INIT_TX_LATENCY 502
229#define AR5K_INIT_USEC 39
230#define AR5K_INIT_USEC_TURBO 79
231#define AR5K_INIT_USEC_32 31
232#define AR5K_INIT_SLOT_TIME 396
233#define AR5K_INIT_SLOT_TIME_TURBO 480
234#define AR5K_INIT_ACK_CTS_TIMEOUT 1024
235#define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800
236#define AR5K_INIT_PROG_IFS 920
237#define AR5K_INIT_PROG_IFS_TURBO 960
238#define AR5K_INIT_EIFS 3440
239#define AR5K_INIT_EIFS_TURBO 6880
240#define AR5K_INIT_SIFS 560
241#define AR5K_INIT_SIFS_TURBO 480
242#define AR5K_INIT_SH_RETRY 10
243#define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY
244#define AR5K_INIT_SSH_RETRY 32
245#define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY
246#define AR5K_INIT_TX_RETRY 10
247
248#define AR5K_INIT_TRANSMIT_LATENCY ( \
249 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
250 (AR5K_INIT_USEC) \
251)
252#define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \
253 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
254 (AR5K_INIT_USEC_TURBO) \
255)
256#define AR5K_INIT_PROTO_TIME_CNTRL ( \
257 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \
258 (AR5K_INIT_PROG_IFS) \
259)
260#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \
261 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \
262 (AR5K_INIT_PROG_IFS_TURBO) \
263)
264
fa1c114f
JS		 265/* token to use for aifs, cwmin, cwmax in MadWiFi */
266#define AR5K_TXQ_USEDEFAULT ((u32) -1)
267
268/* GENERIC CHIPSET DEFINITIONS */
269
270/* MAC Chips */
271enum ath5k_version {
272 AR5K_AR5210 = 0,
273 AR5K_AR5211 = 1,
274 AR5K_AR5212 = 2,
275};
276
277/* PHY Chips */
278enum ath5k_radio {
279 AR5K_RF5110 = 0,
280 AR5K_RF5111 = 1,
281 AR5K_RF5112 = 2,
8daeef97
NK		 282 AR5K_RF2413 = 3,
283 AR5K_RF5413 = 4,
1bef016a
NK		 284 AR5K_RF2316 = 5,
285 AR5K_RF2317 = 6,
286 AR5K_RF2425 = 7,
fa1c114f
JS		 287};
288
289/*
290 * Common silicon revision/version values
291 */
292
293enum ath5k_srev_type {
1bef016a 294 AR5K_VERSION_MAC,
fa1c114f
JS		 295 AR5K_VERSION_RAD,
296};
297
298struct ath5k_srev_name {
299 const char *sr_name;
300 enum ath5k_srev_type sr_type;
301 u_int sr_val;
302};
303
304#define AR5K_SREV_UNKNOWN 0xffff
305
1bef016a
NK		 306#define AR5K_SREV_AR5210 0x00 /* Crete */
307#define AR5K_SREV_AR5311 0x10 /* Maui 1 */
308#define AR5K_SREV_AR5311A 0x20 /* Maui 2 */
309#define AR5K_SREV_AR5311B 0x30 /* Spirit */
310#define AR5K_SREV_AR5211 0x40 /* Oahu */
311#define AR5K_SREV_AR5212 0x50 /* Venice */
312#define AR5K_SREV_AR5213 0x55 /* ??? */
313#define AR5K_SREV_AR5213A 0x59 /* Hainan */
314#define AR5K_SREV_AR2413 0x78 /* Griffin lite */
315#define AR5K_SREV_AR2414 0x70 /* Griffin */
316#define AR5K_SREV_AR5424 0x90 /* Condor */
317#define AR5K_SREV_AR5413 0xa4 /* Eagle lite */
318#define AR5K_SREV_AR5414 0xa0 /* Eagle */
319#define AR5K_SREV_AR2415 0xb0 /* Cobra */
320#define AR5K_SREV_AR5416 0xc0 /* PCI-E */
321#define AR5K_SREV_AR5418 0xca /* PCI-E */
322#define AR5K_SREV_AR2425 0xe0 /* Swan */
323#define AR5K_SREV_AR2417 0xf0 /* Nala */
fa1c114f
JS		 324
325#define AR5K_SREV_RAD_5110 0x00
326#define AR5K_SREV_RAD_5111 0x10
327#define AR5K_SREV_RAD_5111A 0x15
328#define AR5K_SREV_RAD_2111 0x20
329#define AR5K_SREV_RAD_5112 0x30
330#define AR5K_SREV_RAD_5112A 0x35
e5a4ad0d 331#define AR5K_SREV_RAD_5112B 0x36
fa1c114f
JS		 332#define AR5K_SREV_RAD_2112 0x40
333#define AR5K_SREV_RAD_2112A 0x45
e5a4ad0d 334#define AR5K_SREV_RAD_2112B 0x46
1bef016a
NK		 335#define AR5K_SREV_RAD_2413 0x50
336#define AR5K_SREV_RAD_5413 0x60
337#define AR5K_SREV_RAD_2316 0x70
338#define AR5K_SREV_RAD_2317 0x80
339#define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */
340#define AR5K_SREV_RAD_2425 0xa2
341#define AR5K_SREV_RAD_5133 0xc0
342
343#define AR5K_SREV_PHY_5211 0x30
344#define AR5K_SREV_PHY_5212 0x41
345#define AR5K_SREV_PHY_2112B 0x43
346#define AR5K_SREV_PHY_2413 0x45
347#define AR5K_SREV_PHY_5413 0x61
348#define AR5K_SREV_PHY_2425 0x70
fa1c114f
JS		 349
350/* IEEE defs */
fa1c114f
JS		 351#define IEEE80211_MAX_LEN 2500
352
353/* TODO add support to mac80211 for vendor-specific rates and modes */
354
355/*
356 * Some of this information is based on Documentation from:
357 *
358 * http://madwifi.org/wiki/ChipsetFeatures/SuperAG
359 *
360 * Modulation for Atheros' eXtended Range - range enhancing extension that is
361 * supposed to double the distance an Atheros client device can keep a
362 * connection with an Atheros access point. This is achieved by increasing
363 * the receiver sensitivity up to, -105dBm, which is about 20dB above what
364 * the 802.11 specifications demand. In addition, new (proprietary) data rates
365 * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
366 *
367 * Please note that can you either use XR or TURBO but you cannot use both,
368 * they are exclusive.
369 *
370 */
371#define MODULATION_XR 0x00000200
372/*
373 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a
374 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s
375 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g
376 * channels. To use this feature your Access Point must also suport it.
377 * There is also a distinction between "static" and "dynamic" turbo modes:
378 *
379 * - Static: is the dumb version: devices set to this mode stick to it until
380 * the mode is turned off.
381 * - Dynamic: is the intelligent version, the network decides itself if it
382 * is ok to use turbo. As soon as traffic is detected on adjacent channels
383 * (which would get used in turbo mode), or when a non-turbo station joins
384 * the network, turbo mode won't be used until the situation changes again.
385 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which
386 * monitors the used radio band in order to decide whether turbo mode may
387 * be used or not.
388 *
389 * This article claims Super G sticks to bonding of channels 5 and 6 for
390 * USA:
391 *
392 * http://www.pcworld.com/article/id,113428-page,1/article.html
393 *
394 * The channel bonding seems to be driver specific though. In addition to
395 * deciding what channels will be used, these "Turbo" modes are accomplished
396 * by also enabling the following features:
397 *
398 * - Bursting: allows multiple frames to be sent at once, rather than pausing
399 * after each frame. Bursting is a standards-compliant feature that can be
400 * used with any Access Point.
401 * - Fast frames: increases the amount of information that can be sent per
402 * frame, also resulting in a reduction of transmission overhead. It is a
403 * proprietary feature that needs to be supported by the Access Point.
404 * - Compression: data frames are compressed in real time using a Lempel Ziv
405 * algorithm. This is done transparently. Once this feature is enabled,
406 * compression and decompression takes place inside the chipset, without
407 * putting additional load on the host CPU.
408 *
409 */
410#define MODULATION_TURBO 0x00000080
411
d8ee398d
LR		 412enum ath5k_driver_mode {
413 AR5K_MODE_11A = 0,
414 AR5K_MODE_11A_TURBO = 1,
415 AR5K_MODE_11B = 2,
416 AR5K_MODE_11G = 3,
417 AR5K_MODE_11G_TURBO = 4,
418 AR5K_MODE_XR = 0,
419 AR5K_MODE_MAX = 5
fa1c114f
JS		 420};
421
19fd6e55 422
fa1c114f
JS		 423/****************\
424 TX DEFINITIONS
425\****************/
426
427/*
c6e387a2 428 * TX Status descriptor
fa1c114f
JS		 429 */
430struct ath5k_tx_status {
431 u16 ts_seqnum;
432 u16 ts_tstamp;
433 u8 ts_status;
2f7fe870
FF		 434 u8 ts_rate[4];
435 u8 ts_retry[4];
436 u8 ts_final_idx;
fa1c114f
JS		 437 s8 ts_rssi;
438 u8 ts_shortretry;
439 u8 ts_longretry;
440 u8 ts_virtcol;
441 u8 ts_antenna;
442};
443
444#define AR5K_TXSTAT_ALTRATE 0x80
445#define AR5K_TXERR_XRETRY 0x01
446#define AR5K_TXERR_FILT 0x02
447#define AR5K_TXERR_FIFO 0x04
448
449/**
450 * enum ath5k_tx_queue - Queue types used to classify tx queues.
451 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
452 * @AR5K_TX_QUEUE_DATA: A normal data queue
453 * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue
454 * @AR5K_TX_QUEUE_BEACON: The beacon queue
455 * @AR5K_TX_QUEUE_CAB: The after-beacon queue
456 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
457 */
458enum ath5k_tx_queue {
459 AR5K_TX_QUEUE_INACTIVE = 0,
460 AR5K_TX_QUEUE_DATA,
461 AR5K_TX_QUEUE_XR_DATA,
462 AR5K_TX_QUEUE_BEACON,
463 AR5K_TX_QUEUE_CAB,
464 AR5K_TX_QUEUE_UAPSD,
465};
466
467#define AR5K_NUM_TX_QUEUES 10
468#define AR5K_NUM_TX_QUEUES_NOQCU 2
469
470/*
471 * Queue syb-types to classify normal data queues.
472 * These are the 4 Access Categories as defined in
473 * WME spec. 0 is the lowest priority and 4 is the
474 * highest. Normal data that hasn't been classified
475 * goes to the Best Effort AC.
476 */
477enum ath5k_tx_queue_subtype {
478 AR5K_WME_AC_BK = 0, /*Background traffic*/
479 AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/
480 AR5K_WME_AC_VI, /*Video traffic*/
481 AR5K_WME_AC_VO, /*Voice traffic*/
482};
483
484/*
485 * Queue ID numbers as returned by the hw functions, each number
486 * represents a hw queue. If hw does not support hw queues
487 * (eg 5210) all data goes in one queue. These match
488 * d80211 definitions (net80211/MadWiFi don't use them).
489 */
490enum ath5k_tx_queue_id {
491 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0,
492 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1,
493 AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/
494 AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/
495 AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/
496 AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/
497 AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/
498 AR5K_TX_QUEUE_ID_UAPSD = 8,
499 AR5K_TX_QUEUE_ID_XR_DATA = 9,
500};
501
fa1c114f
JS		 502/*
503 * Flags to set hw queue's parameters...
504 */
505#define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */
506#define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */
507#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */
508#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */
509#define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */
510#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0020 /* Disable random post-backoff */
511#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0040 /* Enable ready time expiry policy (?)*/
512#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0080 /* Enable backoff while bursting */
513#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x0100 /* Disable backoff while bursting */
514#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x0200 /* Enable hw compression -not implemented-*/
515
516/*
517 * A struct to hold tx queue's parameters
518 */
519struct ath5k_txq_info {
520 enum ath5k_tx_queue tqi_type;
521 enum ath5k_tx_queue_subtype tqi_subtype;
522 u16 tqi_flags; /* Tx queue flags (see above) */
523 u32 tqi_aifs; /* Arbitrated Interframe Space */
524 s32 tqi_cw_min; /* Minimum Contention Window */
525 s32 tqi_cw_max; /* Maximum Contention Window */
526 u32 tqi_cbr_period; /* Constant bit rate period */
527 u32 tqi_cbr_overflow_limit;
528 u32 tqi_burst_time;
529 u32 tqi_ready_time; /* Not used */
530};
531
532/*
533 * Transmit packet types.
c6e387a2
NK		 534 * used on tx control descriptor
535 * TODO: Use them inside base.c corectly
fa1c114f
JS		 536 */
537enum ath5k_pkt_type {
538 AR5K_PKT_TYPE_NORMAL = 0,
539 AR5K_PKT_TYPE_ATIM = 1,
540 AR5K_PKT_TYPE_PSPOLL = 2,
541 AR5K_PKT_TYPE_BEACON = 3,
542 AR5K_PKT_TYPE_PROBE_RESP = 4,
543 AR5K_PKT_TYPE_PIFS = 5,
544};
545
546/*
547 * TX power and TPC settings
548 */
549#define AR5K_TXPOWER_OFDM(_r, _v) ( \
550 ((0 & 1) << ((_v) + 6)) | \
551 (((ah->ah_txpower.txp_rates[(_r)]) & 0x3f) << (_v)) \
552)
553
554#define AR5K_TXPOWER_CCK(_r, _v) ( \
555 (ah->ah_txpower.txp_rates[(_r)] & 0x3f) << (_v) \
556)
557
558/*
559 * DMA size definitions (2^n+2)
560 */
561enum ath5k_dmasize {
562 AR5K_DMASIZE_4B = 0,
563 AR5K_DMASIZE_8B,
564 AR5K_DMASIZE_16B,
565 AR5K_DMASIZE_32B,
566 AR5K_DMASIZE_64B,
567 AR5K_DMASIZE_128B,
568 AR5K_DMASIZE_256B,
569 AR5K_DMASIZE_512B
570};
571
572
573/****************\
574 RX DEFINITIONS
575\****************/
576
577/*
c6e387a2 578 * RX Status descriptor
fa1c114f
JS		 579 */
580struct ath5k_rx_status {
581 u16 rs_datalen;
582 u16 rs_tstamp;
583 u8 rs_status;
584 u8 rs_phyerr;
585 s8 rs_rssi;
586 u8 rs_keyix;
587 u8 rs_rate;
588 u8 rs_antenna;
589 u8 rs_more;
590};
591
592#define AR5K_RXERR_CRC 0x01
593#define AR5K_RXERR_PHY 0x02
594#define AR5K_RXERR_FIFO 0x04
595#define AR5K_RXERR_DECRYPT 0x08
596#define AR5K_RXERR_MIC 0x10
597#define AR5K_RXKEYIX_INVALID ((u8) - 1)
598#define AR5K_TXKEYIX_INVALID ((u32) - 1)
599
fa1c114f 600
fa1c114f
JS		 601/**************************\
602 BEACON TIMERS DEFINITIONS
603\**************************/
604
605#define AR5K_BEACON_PERIOD 0x0000ffff
606#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/
607#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/
608
609#if 0
610/**
611 * struct ath5k_beacon_state - Per-station beacon timer state.
612 * @bs_interval: in TU's, can also include the above flags
613 * @bs_cfp_max_duration: if non-zero hw is setup to coexist with a
614 * Point Coordination Function capable AP
615 */
616struct ath5k_beacon_state {
617 u32 bs_next_beacon;
618 u32 bs_next_dtim;
619 u32 bs_interval;
620 u8 bs_dtim_period;
621 u8 bs_cfp_period;
622 u16 bs_cfp_max_duration;
623 u16 bs_cfp_du_remain;
624 u16 bs_tim_offset;
625 u16 bs_sleep_duration;
626 u16 bs_bmiss_threshold;
627 u32 bs_cfp_next;
628};
629#endif
630
631
632/*
633 * TSF to TU conversion:
634 *
635 * TSF is a 64bit value in usec (microseconds).
e535c1ac
BR		 636 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
637 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
fa1c114f
JS		 638 */
639#define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
640
641
c6e387a2
NK		 642/*******************************\
643 GAIN OPTIMIZATION DEFINITIONS
644\*******************************/
645
646enum ath5k_rfgain {
647 AR5K_RFGAIN_INACTIVE = 0,
648 AR5K_RFGAIN_READ_REQUESTED,
649 AR5K_RFGAIN_NEED_CHANGE,
650};
651
652#define AR5K_GAIN_CRN_FIX_BITS_5111 4
653#define AR5K_GAIN_CRN_FIX_BITS_5112 7
654#define AR5K_GAIN_CRN_MAX_FIX_BITS AR5K_GAIN_CRN_FIX_BITS_5112
655#define AR5K_GAIN_DYN_ADJUST_HI_MARGIN 15
656#define AR5K_GAIN_DYN_ADJUST_LO_MARGIN 20
657#define AR5K_GAIN_CCK_PROBE_CORR 5
658#define AR5K_GAIN_CCK_OFDM_GAIN_DELTA 15
659#define AR5K_GAIN_STEP_COUNT 10
660#define AR5K_GAIN_PARAM_TX_CLIP 0
661#define AR5K_GAIN_PARAM_PD_90 1
662#define AR5K_GAIN_PARAM_PD_84 2
663#define AR5K_GAIN_PARAM_GAIN_SEL 3
664#define AR5K_GAIN_PARAM_MIX_ORN 0
665#define AR5K_GAIN_PARAM_PD_138 1
666#define AR5K_GAIN_PARAM_PD_137 2
667#define AR5K_GAIN_PARAM_PD_136 3
668#define AR5K_GAIN_PARAM_PD_132 4
669#define AR5K_GAIN_PARAM_PD_131 5
670#define AR5K_GAIN_PARAM_PD_130 6
671#define AR5K_GAIN_CHECK_ADJUST(_g) \
672 ((_g)->g_current <= (_g)->g_low || (_g)->g_current >= (_g)->g_high)
673
674struct ath5k_gain_opt_step {
675 s16 gos_param[AR5K_GAIN_CRN_MAX_FIX_BITS];
676 s32 gos_gain;
677};
678
679struct ath5k_gain {
680 u32 g_step_idx;
681 u32 g_current;
682 u32 g_target;
683 u32 g_low;
684 u32 g_high;
685 u32 g_f_corr;
686 u32 g_active;
687 const struct ath5k_gain_opt_step *g_step;
688};
689
690
fa1c114f
JS		 691/********************\
692 COMMON DEFINITIONS
693\********************/
694
fa1c114f
JS		 695#define AR5K_SLOT_TIME_9 396
696#define AR5K_SLOT_TIME_20 880
697#define AR5K_SLOT_TIME_MAX 0xffff
698
699/* channel_flags */
700#define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */
701#define CHANNEL_TURBO 0x0010 /* Turbo Channel */
702#define CHANNEL_CCK 0x0020 /* CCK channel */
703#define CHANNEL_OFDM 0x0040 /* OFDM channel */
704#define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */
705#define CHANNEL_5GHZ 0x0100 /* 5GHz channel */
706#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */
707#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */
708#define CHANNEL_XR 0x0800 /* XR channel */
709
710#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
711#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
712#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
713#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
714#define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
715#define CHANNEL_108A CHANNEL_T
716#define CHANNEL_108G CHANNEL_TG
717#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
718
719#define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \
720 CHANNEL_TURBO)
721
722#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL & ~CHANNEL_TURBO)
723#define CHANNEL_MODES CHANNEL_ALL
724
725/*
c6e387a2
NK		 726 * Used internaly for reset_tx_queue).
727 * Also see struct struct ieee80211_channel.
fa1c114f 728 */
d8ee398d
LR		 729#define IS_CHAN_XR(_c) ((_c.hw_value & CHANNEL_XR) != 0)
730#define IS_CHAN_B(_c) ((_c.hw_value & CHANNEL_B) != 0)
fa1c114f
JS		 731
732/*
c6e387a2 733 * The following structure is used to map 2GHz channels to
fa1c114f 734 * 5GHz Atheros channels.
c6e387a2 735 * TODO: Clean up
fa1c114f
JS		 736 */
737struct ath5k_athchan_2ghz {
738 u32 a2_flags;
739 u16 a2_athchan;
740};
741
63266a65 742
c6e387a2
NK		 743/******************\
744 RATE DEFINITIONS
745\******************/
fa1c114f 746
fa1c114f 747/**
63266a65 748 * Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32.
fa1c114f 749 *
63266a65 750 * The rate code is used to get the RX rate or set the TX rate on the
fa1c114f
JS		 751 * hardware descriptors. It is also used for internal modulation control
752 * and settings.
753 *
63266a65 754 * This is the hardware rate map we are aware of:
fa1c114f 755 *
63266a65 756 * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08
fa1c114f
JS		 757 * rate_kbps 3000 1000 ? ? ? 2000 500 48000
758 *
63266a65 759 * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10
fa1c114f
JS		 760 * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ?
761 *
762 * rate_code 17 18 19 20 21 22 23 24
763 * rate_kbps ? ? ? ? ? ? ? 11000
764 *
765 * rate_code 25 26 27 28 29 30 31 32
63266a65
BR		 766 * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ?
767 *
768 * "S" indicates CCK rates with short preamble.
fa1c114f 769 *
63266a65
BR		 770 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the
771 * lowest 4 bits, so they are the same as below with a 0xF mask.
772 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M).
773 * We handle this in ath5k_setup_bands().
fa1c114f 774 */
63266a65 775#define AR5K_MAX_RATES 32
fa1c114f 776
63266a65
BR		 777/* B */
778#define ATH5K_RATE_CODE_1M 0x1B
779#define ATH5K_RATE_CODE_2M 0x1A
780#define ATH5K_RATE_CODE_5_5M 0x19
781#define ATH5K_RATE_CODE_11M 0x18
782/* A and G */
783#define ATH5K_RATE_CODE_6M 0x0B
784#define ATH5K_RATE_CODE_9M 0x0F
785#define ATH5K_RATE_CODE_12M 0x0A
786#define ATH5K_RATE_CODE_18M 0x0E
787#define ATH5K_RATE_CODE_24M 0x09
788#define ATH5K_RATE_CODE_36M 0x0D
789#define ATH5K_RATE_CODE_48M 0x08
790#define ATH5K_RATE_CODE_54M 0x0C
791/* XR */
792#define ATH5K_RATE_CODE_XR_500K 0x07
793#define ATH5K_RATE_CODE_XR_1M 0x02
794#define ATH5K_RATE_CODE_XR_2M 0x06
795#define ATH5K_RATE_CODE_XR_3M 0x01
fa1c114f 796
c6e387a2
NK		 797/* adding this flag to rate_code enables short preamble */
798#define AR5K_SET_SHORT_PREAMBLE 0x04
fa1c114f
JS		 799
800/*
801 * Crypto definitions
802 */
803
804#define AR5K_KEYCACHE_SIZE 8
805
806/***********************\
807 HW RELATED DEFINITIONS
808\***********************/
809
810/*
811 * Misc definitions
812 */
813#define AR5K_RSSI_EP_MULTIPLIER (1<<7)
814
815#define AR5K_ASSERT_ENTRY(_e, _s) do { \
816 if (_e >= _s) \
817 return (false); \
818} while (0)
819
fa1c114f
JS		 820enum ath5k_ant_setting {
821 AR5K_ANT_VARIABLE = 0, /* variable by programming */
822 AR5K_ANT_FIXED_A = 1, /* fixed to 11a frequencies */
823 AR5K_ANT_FIXED_B = 2, /* fixed to 11b frequencies */
824 AR5K_ANT_MAX = 3,
825};
826
827/*
828 * Hardware interrupt abstraction
829 */
830
831/**
832 * enum ath5k_int - Hardware interrupt masks helpers
833 *
834 * @AR5K_INT_RX: mask to identify received frame interrupts, of type
835 * AR5K_ISR_RXOK or AR5K_ISR_RXERR
836 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?)
837 * @AR5K_INT_RXNOFRM: No frame received (?)
838 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The
839 * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's
840 * LinkPtr is NULL. For more details, refer to:
841 * http://www.freepatentsonline.com/20030225739.html
842 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors).
843 * Note that Rx overrun is not always fatal, on some chips we can continue
844 * operation without reseting the card, that's why int_fatal is not
845 * common for all chips.
846 * @AR5K_INT_TX: mask to identify received frame interrupts, of type
847 * AR5K_ISR_TXOK or AR5K_ISR_TXERR
848 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?)
849 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold
850 * We currently do increments on interrupt by
851 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
852 * @AR5K_INT_MIB: Indicates the Management Information Base counters should be
853 * checked. We should do this with ath5k_hw_update_mib_counters() but
854 * it seems we should also then do some noise immunity work.
855 * @AR5K_INT_RXPHY: RX PHY Error
856 * @AR5K_INT_RXKCM: ??
857 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
858 * beacon that must be handled in software. The alternative is if you
859 * have VEOL support, in that case you let the hardware deal with things.
860 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
861 * beacons from the AP have associated with, we should probably try to
862 * reassociate. When in IBSS mode this might mean we have not received
863 * any beacons from any local stations. Note that every station in an
864 * IBSS schedules to send beacons at the Target Beacon Transmission Time
865 * (TBTT) with a random backoff.
866 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ??
867 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now
868 * until properly handled
869 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA
870 * errors. These types of errors we can enable seem to be of type
871 * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR.
872 * @AR5K_INT_GLOBAL: Seems to be used to clear and set the IER
873 * @AR5K_INT_NOCARD: signals the card has been removed
874 * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same
875 * bit value
876 *
877 * These are mapped to take advantage of some common bits
878 * between the MACs, to be able to set intr properties
879 * easier. Some of them are not used yet inside hw.c. Most map
880 * to the respective hw interrupt value as they are common amogst different
881 * MACs.
882 */
883enum ath5k_int {
884 AR5K_INT_RX = 0x00000001, /* Not common */
885 AR5K_INT_RXDESC = 0x00000002,
886 AR5K_INT_RXNOFRM = 0x00000008,
887 AR5K_INT_RXEOL = 0x00000010,
888 AR5K_INT_RXORN = 0x00000020,
889 AR5K_INT_TX = 0x00000040, /* Not common */
890 AR5K_INT_TXDESC = 0x00000080,
891 AR5K_INT_TXURN = 0x00000800,
892 AR5K_INT_MIB = 0x00001000,
893 AR5K_INT_RXPHY = 0x00004000,
894 AR5K_INT_RXKCM = 0x00008000,
895 AR5K_INT_SWBA = 0x00010000,
896 AR5K_INT_BMISS = 0x00040000,
897 AR5K_INT_BNR = 0x00100000, /* Not common */
898 AR5K_INT_GPIO = 0x01000000,
899 AR5K_INT_FATAL = 0x40000000, /* Not common */
900 AR5K_INT_GLOBAL = 0x80000000,
901
902 AR5K_INT_COMMON = AR5K_INT_RXNOFRM
903 | AR5K_INT_RXDESC
904 | AR5K_INT_RXEOL
905 | AR5K_INT_RXORN
906 | AR5K_INT_TXURN
907 | AR5K_INT_TXDESC
908 | AR5K_INT_MIB
909 | AR5K_INT_RXPHY
910 | AR5K_INT_RXKCM
911 | AR5K_INT_SWBA
912 | AR5K_INT_BMISS
913 | AR5K_INT_GPIO,
914 AR5K_INT_NOCARD = 0xffffffff
915};
916
917/*
918 * Power management
919 */
920enum ath5k_power_mode {
921 AR5K_PM_UNDEFINED = 0,
922 AR5K_PM_AUTO,
923 AR5K_PM_AWAKE,
924 AR5K_PM_FULL_SLEEP,
925 AR5K_PM_NETWORK_SLEEP,
926};
927
928/*
929 * These match net80211 definitions (not used in
c6e387a2
NK		 930 * mac80211).
931 * TODO: Clean this up
fa1c114f
JS		 932 */
933#define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/
934#define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/
935#define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/
936#define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/
937#define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/
938
939/* GPIO-controlled software LED */
940#define AR5K_SOFTLED_PIN 0
941#define AR5K_SOFTLED_ON 0
942#define AR5K_SOFTLED_OFF 1
943
944/*
945 * Chipset capabilities -see ath5k_hw_get_capability-
946 * get_capability function is not yet fully implemented
c6e387a2
NK		 947 * in ath5k so most of these don't work yet...
948 * TODO: Implement these & merge with _TUNE_ stuff above
fa1c114f
JS		 949 */
950enum ath5k_capability_type {
951 AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */
952 AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */
953 AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */
954 AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */
955 AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */
956 AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */
957 AR5K_CAP_VEOL = 7, /* Supports virtual EOL */
958 AR5K_CAP_COMPRESSION = 8, /* Supports compression */
959 AR5K_CAP_BURST = 9, /* Supports packet bursting */
960 AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */
961 AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */
962 AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */
963 AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */
964 AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */
965 AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */
966 AR5K_CAP_XR = 16, /* Supports XR mode */
967 AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */
968 AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */
969 AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */
970 AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */
971};
972
400ec45a
LR		 973
974/* XXX: we *may* move cap_range stuff to struct wiphy */
fa1c114f
JS		 975struct ath5k_capabilities {
976 /*
977 * Supported PHY modes
978 * (ie. CHANNEL_A, CHANNEL_B, ...)
979 */
d8ee398d 980 DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX);
fa1c114f
JS		 981
982 /*
983 * Frequency range (without regulation restrictions)
984 */
985 struct {
986 u16 range_2ghz_min;
987 u16 range_2ghz_max;
988 u16 range_5ghz_min;
989 u16 range_5ghz_max;
990 } cap_range;
991
fa1c114f
JS		 992 /*
993 * Values stored in the EEPROM (some of them...)
994 */
995 struct ath5k_eeprom_info cap_eeprom;
996
997 /*
998 * Queue information
999 */
1000 struct {
1001 u8 q_tx_num;
1002 } cap_queues;
1003};
1004
1005
1006/***************************************\
1007 HARDWARE ABSTRACTION LAYER STRUCTURE
1008\***************************************/
1009
1010/*
1011 * Misc defines
1012 */
1013
1014#define AR5K_MAX_GPIO 10
1015#define AR5K_MAX_RF_BANKS 8
1016
c6e387a2 1017/* TODO: Clean up and merge with ath5k_softc */
fa1c114f
JS		 1018struct ath5k_hw {
1019 u32 ah_magic;
1020
1021 struct ath5k_softc *ah_sc;
1022 void __iomem *ah_iobase;
1023
1024 enum ath5k_int ah_imr;
1025
05c914fe 1026 enum nl80211_iftype ah_op_mode;
fa1c114f
JS		 1027 enum ath5k_power_mode ah_power_mode;
1028 struct ieee80211_channel ah_current_channel;
1029 bool ah_turbo;
1030 bool ah_calibration;
1031 bool ah_running;
1032 bool ah_single_chip;
1033 enum ath5k_rfgain ah_rf_gain;
1034
1035 u32 ah_mac_srev;
1036 u16 ah_mac_version;
1037 u16 ah_mac_revision;
1038 u16 ah_phy_revision;
1039 u16 ah_radio_5ghz_revision;
1040 u16 ah_radio_2ghz_revision;
0af22563 1041 u32 ah_phy_spending;
fa1c114f
JS		 1042
1043 enum ath5k_version ah_version;
1044 enum ath5k_radio ah_radio;
1045 u32 ah_phy;
1046
1047 bool ah_5ghz;
1048 bool ah_2ghz;
1049
1050#define ah_regdomain ah_capabilities.cap_regdomain.reg_current
1051#define ah_regdomain_hw ah_capabilities.cap_regdomain.reg_hw
1052#define ah_modes ah_capabilities.cap_mode
1053#define ah_ee_version ah_capabilities.cap_eeprom.ee_version
1054
1055 u32 ah_atim_window;
1056 u32 ah_aifs;
1057 u32 ah_cw_min;
1058 u32 ah_cw_max;
1059 bool ah_software_retry;
1060 u32 ah_limit_tx_retries;
1061
1062 u32 ah_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
1063 bool ah_ant_diversity;
1064
1065 u8 ah_sta_id[ETH_ALEN];
1066
1067 /* Current BSSID we are trying to assoc to / creating.
1068 * This is passed by mac80211 on config_interface() and cached here for
1069 * use in resets */
1070 u8 ah_bssid[ETH_ALEN];
1071
1072 u32 ah_gpio[AR5K_MAX_GPIO];
1073 int ah_gpio_npins;
1074
1075 struct ath5k_capabilities ah_capabilities;
1076
1077 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES];
1078 u32 ah_txq_status;
1079 u32 ah_txq_imr_txok;
1080 u32 ah_txq_imr_txerr;
1081 u32 ah_txq_imr_txurn;
1082 u32 ah_txq_imr_txdesc;
1083 u32 ah_txq_imr_txeol;
1084 u32 *ah_rf_banks;
1085 size_t ah_rf_banks_size;
1086 struct ath5k_gain ah_gain;
1087 u32 ah_offset[AR5K_MAX_RF_BANKS];
1088
1089 struct {
1090 u16 txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE];
1091 u16 txp_rates[AR5K_MAX_RATES];
1092 s16 txp_min;
1093 s16 txp_max;
1094 bool txp_tpc;
1095 s16 txp_ofdm;
1096 } ah_txpower;
1097
1098 struct {
1099 bool r_enabled;
1100 int r_last_alert;
1101 struct ieee80211_channel r_last_channel;
1102 } ah_radar;
1103
1104 /* noise floor from last periodic calibration */
1105 s32 ah_noise_floor;
1106
1107 /*
1108 * Function pointers
1109 */
c6e387a2
NK		 1110 int (*ah_setup_rx_desc)(struct ath5k_hw *ah, struct ath5k_desc *desc,
1111 u32 size, unsigned int flags);
fa1c114f
JS		 1112 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1113 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
1114 unsigned int, unsigned int, unsigned int, unsigned int,
1115 unsigned int, unsigned int, unsigned int);
c6e387a2 1116 int (*ah_setup_mrr_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
fa1c114f
JS		 1117 unsigned int, unsigned int, unsigned int, unsigned int,
1118 unsigned int, unsigned int);
b47f407b
BR		 1119 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1120 struct ath5k_tx_status *);
1121 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1122 struct ath5k_rx_status *);
fa1c114f
JS		 1123};
1124
1125/*
1126 * Prototypes
1127 */
1128
fa1c114f
JS		 1129/* Attach/Detach Functions */
1130extern struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version);
fa1c114f 1131extern void ath5k_hw_detach(struct ath5k_hw *ah);
c6e387a2 1132
fa1c114f 1133/* Reset Functions */
c6e387a2 1134extern int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial);
05c914fe 1135extern int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, struct ieee80211_channel *channel, bool change_channel);
fa1c114f
JS		 1136/* Power management functions */
1137extern int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration);
c6e387a2 1138
fa1c114f 1139/* DMA Related Functions */
c6e387a2 1140extern void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);
fa1c114f 1141extern int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah);
c6e387a2
NK		 1142extern u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);
1143extern void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
1144extern int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);
fa1c114f 1145extern int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue);
c6e387a2
NK		 1146extern u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);
1147extern int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,
1148 u32 phys_addr);
fa1c114f
JS		 1149extern int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
1150/* Interrupt handling */
1151extern bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
1152extern int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
c6e387a2
NK		 1153extern enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum
1154ath5k_int new_mask);
194828a2 1155extern void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, struct ieee80211_low_level_stats *stats);
c6e387a2 1156
fa1c114f 1157/* EEPROM access functions */
c6e387a2
NK		 1158extern int ath5k_eeprom_init(struct ath5k_hw *ah);
1159extern int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac);
1160
fa1c114f
JS		 1161/* Protocol Control Unit Functions */
1162extern int ath5k_hw_set_opmode(struct ath5k_hw *ah);
1163/* BSSID Functions */
1164extern void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac);
1165extern int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
1166extern void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id);
1167extern int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
1168/* Receive start/stop functions */
1169extern void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
c6e387a2 1170extern void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
fa1c114f
JS		 1171/* RX Filter functions */
1172extern void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
c6e387a2 1173extern int ath5k_hw_set_mcast_filter_idx(struct ath5k_hw *ah, u32 index);
fa1c114f
JS		 1174extern int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index);
1175extern u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
1176extern void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
c6e387a2 1177/* Beacon control functions */
fa1c114f
JS		 1178extern u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah);
1179extern u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
1180extern void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
1181extern void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval);
1182#if 0
1183extern int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah, const struct ath5k_beacon_state *state);
1184extern void ath5k_hw_reset_beacon(struct ath5k_hw *ah);
1185extern int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr);
1186#endif
fa1c114f
JS		 1187/* ACK bit rate */
1188void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high);
1189/* ACK/CTS Timeouts */
1190extern int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout);
1191extern unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah);
1192extern int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout);
1193extern unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah);
1194/* Key table (WEP) functions */
1195extern int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry);
1196extern int ath5k_hw_is_key_valid(struct ath5k_hw *ah, u16 entry);
1197extern int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry, const struct ieee80211_key_conf *key, const u8 *mac);
1198extern int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac);
c6e387a2 1199
fa1c114f 1200/* Queue Control Unit, DFS Control Unit Functions */
fa1c114f 1201extern int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, struct ath5k_txq_info *queue_info);
c6e387a2
NK		 1202extern int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
1203 const struct ath5k_txq_info *queue_info);
1204extern int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
1205 enum ath5k_tx_queue queue_type,
1206 struct ath5k_txq_info *queue_info);
1207extern u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);
fa1c114f
JS		 1208extern void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1209extern int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);
fa1c114f 1210extern unsigned int ath5k_hw_get_slot_time(struct ath5k_hw *ah);
c6e387a2
NK		 1211extern int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time);
1212
fa1c114f 1213/* Hardware Descriptor Functions */
c6e387a2
NK		 1214extern int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
1215
fa1c114f
JS		 1216/* GPIO Functions */
1217extern void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
fa1c114f 1218extern int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
c6e387a2 1219extern int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
fa1c114f
JS		 1220extern u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
1221extern int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
1222extern void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level);
c6e387a2 1223
fa1c114f 1224/* Misc functions */
c6e387a2 1225int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
fa1c114f 1226extern int ath5k_hw_get_capability(struct ath5k_hw *ah, enum ath5k_capability_type cap_type, u32 capability, u32 *result);
c6e387a2
NK		 1227extern int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
1228extern int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
fa1c114f
JS		 1229
1230/* Initial register settings functions */
1231extern int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
c6e387a2 1232
fa1c114f
JS		 1233/* Initialize RF */
1234extern int ath5k_hw_rfregs(struct ath5k_hw *ah, struct ieee80211_channel *channel, unsigned int mode);
1235extern int ath5k_hw_rfgain(struct ath5k_hw *ah, unsigned int freq);
1236extern enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath5k_hw *ah);
1237extern int ath5k_hw_set_rfgain_opt(struct ath5k_hw *ah);
fa1c114f
JS		 1238/* PHY/RF channel functions */
1239extern bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags);
1240extern int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel);
1241/* PHY calibration */
1242extern int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, struct ieee80211_channel *channel);
c6e387a2 1243extern int ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq);
fa1c114f
JS		 1244/* Misc PHY functions */
1245extern u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan);
1246extern void ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant);
1247extern unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah);
c6e387a2 1248extern int ath5k_hw_phy_disable(struct ath5k_hw *ah);
fa1c114f
JS		 1249/* TX power setup */
1250extern int ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, unsigned int txpower);
1251extern int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, unsigned int power);
1252
c6e387a2
NK		 1253/*
1254 * Functions used internaly
1255 */
1256
1257/*
1258 * Translate usec to hw clock units
1259 */
1260static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo)
1261{
1262 return turbo ? (usec * 80) : (usec * 40);
1263}
fa1c114f 1264
c6e387a2
NK		 1265/*
1266 * Translate hw clock units to usec
1267 */
1268static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo)
1269{
1270 return turbo ? (clock / 80) : (clock / 40);
1271}
1272
1273/*
1274 * Read from a register
1275 */
fa1c114f
JS		 1276static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
1277{
1278 return ioread32(ah->ah_iobase + reg);
1279}
1280
c6e387a2
NK		 1281/*
1282 * Write to a register
1283 */
fa1c114f
JS		 1284static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1285{
1286 iowrite32(val, ah->ah_iobase + reg);
1287}
1288
c6e387a2
NK		 1289#if defined(_ATH5K_RESET) || defined(_ATH5K_PHY)
1290/*
1291 * Check if a register write has been completed
1292 */
1293static int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag,
1294 u32 val, bool is_set)
1295{
1296 int i;
1297 u32 data;
1298
1299 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
1300 data = ath5k_hw_reg_read(ah, reg);
1301 if (is_set && (data & flag))
1302 break;
1303 else if ((data & flag) == val)
1304 break;
1305 udelay(15);
1306 }
1307
1308 return (i <= 0) ? -EAGAIN : 0;
1309}
1310#endif
1311
1312static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
1313{
1314 u32 retval = 0, bit, i;
1315
1316 for (i = 0; i < bits; i++) {
1317 bit = (val >> i) & 1;
1318 retval = (retval << 1) | bit;
1319 }
1320
1321 return retval;
1322}
1323
fa1c114f 1324#endif
Linux kernel - Deliverables
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