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Ath5k: lock beacons
[deliverable/linux.git] / drivers / net / wireless / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
51#include <linux/ethtool.h>
52#include <linux/uaccess.h>
53
54#include <net/ieee80211_radiotap.h>
55
56#include <asm/unaligned.h>
57
58#include "base.h"
59#include "reg.h"
60#include "debug.h"
61
fa1c114f
JS		 62static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
63
64
65/******************\
66* Internal defines *
67\******************/
68
69/* Module info */
70MODULE_AUTHOR("Jiri Slaby");
71MODULE_AUTHOR("Nick Kossifidis");
72MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
73MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
74MODULE_LICENSE("Dual BSD/GPL");
400ec45a 75MODULE_VERSION("0.5.0 (EXPERIMENTAL)");
fa1c114f
JS		 76
77
78/* Known PCI ids */
79static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
80 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
81 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
82 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
83 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
84 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
85 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
86 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
87 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
88 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
89 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
90 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
91 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
95 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
96 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/
fa1c114f
JS		 97 { 0 }
98};
99MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
100
101/* Known SREVs */
102static struct ath5k_srev_name srev_names[] = {
103 { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 },
104 { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 },
105 { "5311A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },
106 { "5311B", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },
107 { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 },
108 { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 },
109 { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 },
110 { "5213A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213A },
bb0c9dc2
NK		 111 { "2413", AR5K_VERSION_VER, AR5K_SREV_VER_AR2413 },
112 { "2414", AR5K_VERSION_VER, AR5K_SREV_VER_AR2414 },
fa1c114f
JS		 113 { "2424", AR5K_VERSION_VER, AR5K_SREV_VER_AR2424 },
114 { "5424", AR5K_VERSION_VER, AR5K_SREV_VER_AR5424 },
115 { "5413", AR5K_VERSION_VER, AR5K_SREV_VER_AR5413 },
116 { "5414", AR5K_VERSION_VER, AR5K_SREV_VER_AR5414 },
117 { "5416", AR5K_VERSION_VER, AR5K_SREV_VER_AR5416 },
118 { "5418", AR5K_VERSION_VER, AR5K_SREV_VER_AR5418 },
136bfc79 119 { "2425", AR5K_VERSION_VER, AR5K_SREV_VER_AR2425 },
fa1c114f
JS		 120 { "xxxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN },
121 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
122 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
123 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
124 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
125 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
126 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
127 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
bb0c9dc2 128 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC0 },
fa1c114f
JS		 129 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC1 },
130 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC2 },
131 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
132 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
133};
134
135/*
136 * Prototypes - PCI stack related functions
137 */
138static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
139 const struct pci_device_id *id);
140static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
141#ifdef CONFIG_PM
142static int ath5k_pci_suspend(struct pci_dev *pdev,
143 pm_message_t state);
144static int ath5k_pci_resume(struct pci_dev *pdev);
145#else
146#define ath5k_pci_suspend NULL
147#define ath5k_pci_resume NULL
148#endif /* CONFIG_PM */
149
04a9e451 150static struct pci_driver ath5k_pci_driver = {
fa1c114f
JS		 151 .name = "ath5k_pci",
152 .id_table = ath5k_pci_id_table,
153 .probe = ath5k_pci_probe,
154 .remove = __devexit_p(ath5k_pci_remove),
155 .suspend = ath5k_pci_suspend,
156 .resume = ath5k_pci_resume,
157};
158
159
160
161/*
162 * Prototypes - MAC 802.11 stack related functions
163 */
e039fa4a 164static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
fa1c114f
JS		 165static int ath5k_reset(struct ieee80211_hw *hw);
166static int ath5k_start(struct ieee80211_hw *hw);
167static void ath5k_stop(struct ieee80211_hw *hw);
168static int ath5k_add_interface(struct ieee80211_hw *hw,
169 struct ieee80211_if_init_conf *conf);
170static void ath5k_remove_interface(struct ieee80211_hw *hw,
171 struct ieee80211_if_init_conf *conf);
172static int ath5k_config(struct ieee80211_hw *hw,
173 struct ieee80211_conf *conf);
32bfd35d
JB		 174static int ath5k_config_interface(struct ieee80211_hw *hw,
175 struct ieee80211_vif *vif,
fa1c114f
JS		 176 struct ieee80211_if_conf *conf);
177static void ath5k_configure_filter(struct ieee80211_hw *hw,
178 unsigned int changed_flags,
179 unsigned int *new_flags,
180 int mc_count, struct dev_mc_list *mclist);
181static int ath5k_set_key(struct ieee80211_hw *hw,
182 enum set_key_cmd cmd,
183 const u8 *local_addr, const u8 *addr,
184 struct ieee80211_key_conf *key);
185static int ath5k_get_stats(struct ieee80211_hw *hw,
186 struct ieee80211_low_level_stats *stats);
187static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
188 struct ieee80211_tx_queue_stats *stats);
189static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
190static void ath5k_reset_tsf(struct ieee80211_hw *hw);
191static int ath5k_beacon_update(struct ieee80211_hw *hw,
e039fa4a 192 struct sk_buff *skb);
fa1c114f
JS		 193
194static struct ieee80211_ops ath5k_hw_ops = {
195 .tx = ath5k_tx,
196 .start = ath5k_start,
197 .stop = ath5k_stop,
198 .add_interface = ath5k_add_interface,
199 .remove_interface = ath5k_remove_interface,
200 .config = ath5k_config,
201 .config_interface = ath5k_config_interface,
202 .configure_filter = ath5k_configure_filter,
203 .set_key = ath5k_set_key,
204 .get_stats = ath5k_get_stats,
205 .conf_tx = NULL,
206 .get_tx_stats = ath5k_get_tx_stats,
207 .get_tsf = ath5k_get_tsf,
208 .reset_tsf = ath5k_reset_tsf,
fa1c114f
JS		 209};
210
211/*
212 * Prototypes - Internal functions
213 */
214/* Attach detach */
215static int ath5k_attach(struct pci_dev *pdev,
216 struct ieee80211_hw *hw);
217static void ath5k_detach(struct pci_dev *pdev,
218 struct ieee80211_hw *hw);
219/* Channel/mode setup */
220static inline short ath5k_ieee2mhz(short chan);
221static unsigned int ath5k_copy_rates(struct ieee80211_rate *rates,
222 const struct ath5k_rate_table *rt,
223 unsigned int max);
224static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
225 struct ieee80211_channel *channels,
226 unsigned int mode,
227 unsigned int max);
228static int ath5k_getchannels(struct ieee80211_hw *hw);
229static int ath5k_chan_set(struct ath5k_softc *sc,
230 struct ieee80211_channel *chan);
231static void ath5k_setcurmode(struct ath5k_softc *sc,
232 unsigned int mode);
233static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d
LR		 234static void ath5k_set_total_hw_rates(struct ath5k_softc *sc);
235
fa1c114f
JS		 236/* Descriptor setup */
237static int ath5k_desc_alloc(struct ath5k_softc *sc,
238 struct pci_dev *pdev);
239static void ath5k_desc_free(struct ath5k_softc *sc,
240 struct pci_dev *pdev);
241/* Buffers setup */
242static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
243 struct ath5k_buf *bf);
244static int ath5k_txbuf_setup(struct ath5k_softc *sc,
e039fa4a 245 struct ath5k_buf *bf);
fa1c114f
JS		 246static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
247 struct ath5k_buf *bf)
248{
249 BUG_ON(!bf);
250 if (!bf->skb)
251 return;
252 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
253 PCI_DMA_TODEVICE);
00482973 254 dev_kfree_skb_any(bf->skb);
fa1c114f
JS		 255 bf->skb = NULL;
256}
257
258/* Queues setup */
259static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
260 int qtype, int subtype);
261static int ath5k_beaconq_setup(struct ath5k_hw *ah);
262static int ath5k_beaconq_config(struct ath5k_softc *sc);
263static void ath5k_txq_drainq(struct ath5k_softc *sc,
264 struct ath5k_txq *txq);
265static void ath5k_txq_cleanup(struct ath5k_softc *sc);
266static void ath5k_txq_release(struct ath5k_softc *sc);
267/* Rx handling */
268static int ath5k_rx_start(struct ath5k_softc *sc);
269static void ath5k_rx_stop(struct ath5k_softc *sc);
270static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
271 struct ath5k_desc *ds,
b47f407b
BR		 272 struct sk_buff *skb,
273 struct ath5k_rx_status *rs);
fa1c114f
JS		 274static void ath5k_tasklet_rx(unsigned long data);
275/* Tx handling */
276static void ath5k_tx_processq(struct ath5k_softc *sc,
277 struct ath5k_txq *txq);
278static void ath5k_tasklet_tx(unsigned long data);
279/* Beacon handling */
280static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 281 struct ath5k_buf *bf);
fa1c114f
JS		 282static void ath5k_beacon_send(struct ath5k_softc *sc);
283static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 284static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f
JS		 285
286static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
287{
288 u64 tsf = ath5k_hw_get_tsf64(ah);
289
290 if ((tsf & 0x7fff) < rstamp)
291 tsf -= 0x8000;
292
293 return (tsf & ~0x7fff) | rstamp;
294}
295
296/* Interrupt handling */
297static int ath5k_init(struct ath5k_softc *sc);
298static int ath5k_stop_locked(struct ath5k_softc *sc);
299static int ath5k_stop_hw(struct ath5k_softc *sc);
300static irqreturn_t ath5k_intr(int irq, void *dev_id);
301static void ath5k_tasklet_reset(unsigned long data);
302
303static void ath5k_calibrate(unsigned long data);
304/* LED functions */
3a078876
BC		 305static int ath5k_init_leds(struct ath5k_softc *sc);
306static void ath5k_led_enable(struct ath5k_softc *sc);
307static void ath5k_led_off(struct ath5k_softc *sc);
308static void ath5k_unregister_leds(struct ath5k_softc *sc);
fa1c114f
JS		 309
310/*
311 * Module init/exit functions
312 */
313static int __init
314init_ath5k_pci(void)
315{
316 int ret;
317
318 ath5k_debug_init();
319
04a9e451 320 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 321 if (ret) {
322 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
323 return ret;
324 }
325
326 return 0;
327}
328
329static void __exit
330exit_ath5k_pci(void)
331{
04a9e451 332 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 333
334 ath5k_debug_finish();
335}
336
337module_init(init_ath5k_pci);
338module_exit(exit_ath5k_pci);
339
340
341/********************\
342* PCI Initialization *
343\********************/
344
345static const char *
346ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
347{
348 const char *name = "xxxxx";
349 unsigned int i;
350
351 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
352 if (srev_names[i].sr_type != type)
353 continue;
354 if ((val & 0xff) < srev_names[i + 1].sr_val) {
355 name = srev_names[i].sr_name;
356 break;
357 }
358 }
359
360 return name;
361}
362
363static int __devinit
364ath5k_pci_probe(struct pci_dev *pdev,
365 const struct pci_device_id *id)
366{
367 void __iomem *mem;
368 struct ath5k_softc *sc;
369 struct ieee80211_hw *hw;
370 int ret;
371 u8 csz;
372
373 ret = pci_enable_device(pdev);
374 if (ret) {
375 dev_err(&pdev->dev, "can't enable device\n");
376 goto err;
377 }
378
379 /* XXX 32-bit addressing only */
380 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
381 if (ret) {
382 dev_err(&pdev->dev, "32-bit DMA not available\n");
383 goto err_dis;
384 }
385
386 /*
387 * Cache line size is used to size and align various
388 * structures used to communicate with the hardware.
389 */
390 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
391 if (csz == 0) {
392 /*
393 * Linux 2.4.18 (at least) writes the cache line size
394 * register as a 16-bit wide register which is wrong.
395 * We must have this setup properly for rx buffer
396 * DMA to work so force a reasonable value here if it
397 * comes up zero.
398 */
399 csz = L1_CACHE_BYTES / sizeof(u32);
400 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
401 }
402 /*
403 * The default setting of latency timer yields poor results,
404 * set it to the value used by other systems. It may be worth
405 * tweaking this setting more.
406 */
407 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
408
409 /* Enable bus mastering */
410 pci_set_master(pdev);
411
412 /*
413 * Disable the RETRY_TIMEOUT register (0x41) to keep
414 * PCI Tx retries from interfering with C3 CPU state.
415 */
416 pci_write_config_byte(pdev, 0x41, 0);
417
418 ret = pci_request_region(pdev, 0, "ath5k");
419 if (ret) {
420 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
421 goto err_dis;
422 }
423
424 mem = pci_iomap(pdev, 0, 0);
425 if (!mem) {
426 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
427 ret = -EIO;
428 goto err_reg;
429 }
430
431 /*
432 * Allocate hw (mac80211 main struct)
433 * and hw->priv (driver private data)
434 */
435 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
436 if (hw == NULL) {
437 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
438 ret = -ENOMEM;
439 goto err_map;
440 }
441
442 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
443
444 /* Initialize driver private data */
445 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a
BR		 446 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
447 IEEE80211_HW_SIGNAL_DBM |
448 IEEE80211_HW_NOISE_DBM;
fa1c114f
JS		 449 hw->extra_tx_headroom = 2;
450 hw->channel_change_time = 5000;
fa1c114f
JS		 451 sc = hw->priv;
452 sc->hw = hw;
453 sc->pdev = pdev;
454
455 ath5k_debug_init_device(sc);
456
457 /*
458 * Mark the device as detached to avoid processing
459 * interrupts until setup is complete.
460 */
461 __set_bit(ATH_STAT_INVALID, sc->status);
462
463 sc->iobase = mem; /* So we can unmap it on detach */
464 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
465 sc->opmode = IEEE80211_IF_TYPE_STA;
466 mutex_init(&sc->lock);
467 spin_lock_init(&sc->rxbuflock);
468 spin_lock_init(&sc->txbuflock);
00482973 469 spin_lock_init(&sc->block);
fa1c114f
JS		 470
471 /* Set private data */
472 pci_set_drvdata(pdev, hw);
473
fa1c114f
JS		 474 /* Setup interrupt handler */
475 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
476 if (ret) {
477 ATH5K_ERR(sc, "request_irq failed\n");
478 goto err_free;
479 }
480
481 /* Initialize device */
482 sc->ah = ath5k_hw_attach(sc, id->driver_data);
483 if (IS_ERR(sc->ah)) {
484 ret = PTR_ERR(sc->ah);
485 goto err_irq;
486 }
487
488 /* Finish private driver data initialization */
489 ret = ath5k_attach(pdev, hw);
490 if (ret)
491 goto err_ah;
492
493 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
494 ath5k_chip_name(AR5K_VERSION_VER,sc->ah->ah_mac_srev),
495 sc->ah->ah_mac_srev,
496 sc->ah->ah_phy_revision);
497
400ec45a 498 if (!sc->ah->ah_single_chip) {
fa1c114f 499 /* Single chip radio (!RF5111) */
400ec45a
LR		 500 if (sc->ah->ah_radio_5ghz_revision &&
501 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 502 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 503 if (!test_bit(AR5K_MODE_11A,
504 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 505 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 506 ath5k_chip_name(AR5K_VERSION_RAD,
507 sc->ah->ah_radio_5ghz_revision),
508 sc->ah->ah_radio_5ghz_revision);
509 /* No 2GHz support (5110 and some
510 * 5Ghz only cards) -> report 5Ghz radio */
511 } else if (!test_bit(AR5K_MODE_11B,
512 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 513 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 514 ath5k_chip_name(AR5K_VERSION_RAD,
515 sc->ah->ah_radio_5ghz_revision),
516 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 517 /* Multiband radio */
518 } else {
519 ATH5K_INFO(sc, "RF%s multiband radio found"
520 " (0x%x)\n",
400ec45a
LR		 521 ath5k_chip_name(AR5K_VERSION_RAD,
522 sc->ah->ah_radio_5ghz_revision),
523 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 524 }
525 }
400ec45a
LR		 526 /* Multi chip radio (RF5111 - RF2111) ->
527 * report both 2GHz/5GHz radios */
528 else if (sc->ah->ah_radio_5ghz_revision &&
529 sc->ah->ah_radio_2ghz_revision){
fa1c114f 530 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 531 ath5k_chip_name(AR5K_VERSION_RAD,
532 sc->ah->ah_radio_5ghz_revision),
533 sc->ah->ah_radio_5ghz_revision);
fa1c114f 534 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 535 ath5k_chip_name(AR5K_VERSION_RAD,
536 sc->ah->ah_radio_2ghz_revision),
537 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 538 }
539 }
540
541
542 /* ready to process interrupts */
543 __clear_bit(ATH_STAT_INVALID, sc->status);
544
545 return 0;
546err_ah:
547 ath5k_hw_detach(sc->ah);
548err_irq:
549 free_irq(pdev->irq, sc);
550err_free:
fa1c114f
JS		 551 ieee80211_free_hw(hw);
552err_map:
553 pci_iounmap(pdev, mem);
554err_reg:
555 pci_release_region(pdev, 0);
556err_dis:
557 pci_disable_device(pdev);
558err:
559 return ret;
560}
561
562static void __devexit
563ath5k_pci_remove(struct pci_dev *pdev)
564{
565 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
566 struct ath5k_softc *sc = hw->priv;
567
568 ath5k_debug_finish_device(sc);
569 ath5k_detach(pdev, hw);
570 ath5k_hw_detach(sc->ah);
571 free_irq(pdev->irq, sc);
fa1c114f
JS		 572 pci_iounmap(pdev, sc->iobase);
573 pci_release_region(pdev, 0);
574 pci_disable_device(pdev);
575 ieee80211_free_hw(hw);
576}
577
578#ifdef CONFIG_PM
579static int
580ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
581{
582 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
583 struct ath5k_softc *sc = hw->priv;
584
3a078876 585 ath5k_led_off(sc);
fa1c114f
JS		 586
587 ath5k_stop_hw(sc);
3e4242b9
JS		 588
589 free_irq(pdev->irq, sc);
fa1c114f
JS		 590 pci_save_state(pdev);
591 pci_disable_device(pdev);
592 pci_set_power_state(pdev, PCI_D3hot);
593
594 return 0;
595}
596
597static int
598ath5k_pci_resume(struct pci_dev *pdev)
599{
600 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
601 struct ath5k_softc *sc = hw->priv;
247ae449
JL		 602 struct ath5k_hw *ah = sc->ah;
603 int i, err;
fa1c114f 604
3e4242b9 605 pci_restore_state(pdev);
fa1c114f
JS		 606
607 err = pci_enable_device(pdev);
608 if (err)
609 return err;
610
fa1c114f
JS		 611 /*
612 * Suspend/Resume resets the PCI configuration space, so we have to
613 * re-disable the RETRY_TIMEOUT register (0x41) to keep
614 * PCI Tx retries from interfering with C3 CPU state
615 */
616 pci_write_config_byte(pdev, 0x41, 0);
617
3e4242b9
JS		 618 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
619 if (err) {
620 ATH5K_ERR(sc, "request_irq failed\n");
37465c8a 621 goto err_no_irq;
3e4242b9
JS		 622 }
623
624 err = ath5k_init(sc);
625 if (err)
626 goto err_irq;
3a078876 627 ath5k_led_enable(sc);
fa1c114f 628
247ae449
JL		 629 /*
630 * Reset the key cache since some parts do not
631 * reset the contents on initial power up or resume.
632 *
633 * FIXME: This may need to be revisited when mac80211 becomes
634 * aware of suspend/resume.
635 */
636 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
637 ath5k_hw_reset_key(ah, i);
638
fa1c114f 639 return 0;
3e4242b9
JS		 640err_irq:
641 free_irq(pdev->irq, sc);
37465c8a 642err_no_irq:
3e4242b9
JS		 643 pci_disable_device(pdev);
644 return err;
fa1c114f
JS		 645}
646#endif /* CONFIG_PM */
647
648
649
650/***********************\
651* Driver Initialization *
652\***********************/
653
654static int
655ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
656{
657 struct ath5k_softc *sc = hw->priv;
658 struct ath5k_hw *ah = sc->ah;
659 u8 mac[ETH_ALEN];
660 unsigned int i;
661 int ret;
662
663 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
664
665 /*
666 * Check if the MAC has multi-rate retry support.
667 * We do this by trying to setup a fake extended
668 * descriptor. MAC's that don't have support will
669 * return false w/o doing anything. MAC's that do
670 * support it will return true w/o doing anything.
671 */
b9887638
JS		 672 ret = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
673 if (ret < 0)
674 goto err;
675 if (ret > 0)
fa1c114f
JS		 676 __set_bit(ATH_STAT_MRRETRY, sc->status);
677
678 /*
679 * Reset the key cache since some parts do not
680 * reset the contents on initial power up.
681 */
c65638a7 682 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
fa1c114f
JS		 683 ath5k_hw_reset_key(ah, i);
684
685 /*
686 * Collect the channel list. The 802.11 layer
687 * is resposible for filtering this list based
688 * on settings like the phy mode and regulatory
689 * domain restrictions.
690 */
691 ret = ath5k_getchannels(hw);
692 if (ret) {
693 ATH5K_ERR(sc, "can't get channels\n");
694 goto err;
695 }
696
d8ee398d
LR		 697 /* Set *_rates so we can map hw rate index */
698 ath5k_set_total_hw_rates(sc);
699
fa1c114f 700 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 701 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
702 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 703 else
d8ee398d 704 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 705
706 /*
707 * Allocate tx+rx descriptors and populate the lists.
708 */
709 ret = ath5k_desc_alloc(sc, pdev);
710 if (ret) {
711 ATH5K_ERR(sc, "can't allocate descriptors\n");
712 goto err;
713 }
714
715 /*
716 * Allocate hardware transmit queues: one queue for
717 * beacon frames and one data queue for each QoS
718 * priority. Note that hw functions handle reseting
719 * these queues at the needed time.
720 */
721 ret = ath5k_beaconq_setup(ah);
722 if (ret < 0) {
723 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
724 goto err_desc;
725 }
726 sc->bhalq = ret;
727
728 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
729 if (IS_ERR(sc->txq)) {
730 ATH5K_ERR(sc, "can't setup xmit queue\n");
731 ret = PTR_ERR(sc->txq);
732 goto err_bhal;
733 }
734
735 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
736 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
737 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
738 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
fa1c114f
JS		 739
740 ath5k_hw_get_lladdr(ah, mac);
741 SET_IEEE80211_PERM_ADDR(hw, mac);
742 /* All MAC address bits matter for ACKs */
743 memset(sc->bssidmask, 0xff, ETH_ALEN);
744 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
745
746 ret = ieee80211_register_hw(hw);
747 if (ret) {
748 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
749 goto err_queues;
750 }
751
3a078876
BC		 752 ath5k_init_leds(sc);
753
fa1c114f
JS		 754 return 0;
755err_queues:
756 ath5k_txq_release(sc);
757err_bhal:
758 ath5k_hw_release_tx_queue(ah, sc->bhalq);
759err_desc:
760 ath5k_desc_free(sc, pdev);
761err:
762 return ret;
763}
764
765static void
766ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
767{
768 struct ath5k_softc *sc = hw->priv;
769
770 /*
771 * NB: the order of these is important:
772 * o call the 802.11 layer before detaching ath5k_hw to
773 * insure callbacks into the driver to delete global
774 * key cache entries can be handled
775 * o reclaim the tx queue data structures after calling
776 * the 802.11 layer as we'll get called back to reclaim
777 * node state and potentially want to use them
778 * o to cleanup the tx queues the hal is called, so detach
779 * it last
780 * XXX: ??? detach ath5k_hw ???
781 * Other than that, it's straightforward...
782 */
783 ieee80211_unregister_hw(hw);
784 ath5k_desc_free(sc, pdev);
785 ath5k_txq_release(sc);
786 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 787 ath5k_unregister_leds(sc);
fa1c114f
JS		 788
789 /*
790 * NB: can't reclaim these until after ieee80211_ifdetach
791 * returns because we'll get called back to reclaim node
792 * state and potentially want to use them.
793 */
794}
795
796
797
798
799/********************\
800* Channel/mode setup *
801\********************/
802
803/*
804 * Convert IEEE channel number to MHz frequency.
805 */
806static inline short
807ath5k_ieee2mhz(short chan)
808{
809 if (chan <= 14 || chan >= 27)
810 return ieee80211chan2mhz(chan);
811 else
812 return 2212 + chan * 20;
813}
814
815static unsigned int
816ath5k_copy_rates(struct ieee80211_rate *rates,
817 const struct ath5k_rate_table *rt,
818 unsigned int max)
819{
820 unsigned int i, count;
821
822 if (rt == NULL)
823 return 0;
824
825 for (i = 0, count = 0; i < rt->rate_count && max > 0; i++) {
d8ee398d
LR		 826 rates[count].bitrate = rt->rates[i].rate_kbps / 100;
827 rates[count].hw_value = rt->rates[i].rate_code;
828 rates[count].flags = rt->rates[i].modulation;
fa1c114f
JS		 829 count++;
830 max--;
831 }
832
833 return count;
834}
835
836static unsigned int
837ath5k_copy_channels(struct ath5k_hw *ah,
838 struct ieee80211_channel *channels,
839 unsigned int mode,
840 unsigned int max)
841{
d8ee398d 842 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 843
844 if (!test_bit(mode, ah->ah_modes))
845 return 0;
846
fa1c114f 847 switch (mode) {
d8ee398d
LR		 848 case AR5K_MODE_11A:
849 case AR5K_MODE_11A_TURBO:
fa1c114f 850 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 851 size = 220 ;
fa1c114f
JS		 852 chfreq = CHANNEL_5GHZ;
853 break;
d8ee398d
LR		 854 case AR5K_MODE_11B:
855 case AR5K_MODE_11G:
856 case AR5K_MODE_11G_TURBO:
857 size = 26;
fa1c114f
JS		 858 chfreq = CHANNEL_2GHZ;
859 break;
860 default:
861 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
862 return 0;
863 }
864
865 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 866 ch = i + 1 ;
867 freq = ath5k_ieee2mhz(ch);
fa1c114f 868
d8ee398d
LR		 869 /* Check if channel is supported by the chipset */
870 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 871 continue;
872
d8ee398d
LR		 873 /* Write channel info and increment counter */
874 channels[count].center_freq = freq;
a3f4b914
LR		 875 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
876 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 877 switch (mode) {
878 case AR5K_MODE_11A:
879 case AR5K_MODE_11G:
880 channels[count].hw_value = chfreq | CHANNEL_OFDM;
881 break;
882 case AR5K_MODE_11A_TURBO:
883 case AR5K_MODE_11G_TURBO:
884 channels[count].hw_value = chfreq |
885 CHANNEL_OFDM | CHANNEL_TURBO;
886 break;
887 case AR5K_MODE_11B:
d8ee398d
LR		 888 channels[count].hw_value = CHANNEL_B;
889 }
fa1c114f 890
fa1c114f
JS		 891 count++;
892 max--;
893 }
894
895 return count;
896}
897
d8ee398d
LR		 898static int
899ath5k_getchannels(struct ieee80211_hw *hw)
fa1c114f
JS		 900{
901 struct ath5k_softc *sc = hw->priv;
d8ee398d
LR		 902 struct ath5k_hw *ah = sc->ah;
903 struct ieee80211_supported_band *sbands = sc->sbands;
904 const struct ath5k_rate_table *hw_rates;
905 unsigned int max_r, max_c, count_r, count_c;
906 int mode2g = AR5K_MODE_11G;
fa1c114f 907
d8ee398d 908 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
fa1c114f 909
d8ee398d
LR		 910 max_r = ARRAY_SIZE(sc->rates);
911 max_c = ARRAY_SIZE(sc->channels);
912 count_r = count_c = 0;
913
914 /* 2GHz band */
400ec45a 915 if (!test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
d8ee398d 916 mode2g = AR5K_MODE_11B;
400ec45a
LR		 917 if (!test_bit(AR5K_MODE_11B,
918 sc->ah->ah_capabilities.cap_mode))
d8ee398d 919 mode2g = -1;
fa1c114f 920 }
fa1c114f 921
400ec45a
LR		 922 if (mode2g > 0) {
923 struct ieee80211_supported_band *sband =
924 &sbands[IEEE80211_BAND_2GHZ];
fa1c114f 925
d8ee398d
LR		 926 sband->bitrates = sc->rates;
927 sband->channels = sc->channels;
fa1c114f 928
d8ee398d
LR		 929 sband->band = IEEE80211_BAND_2GHZ;
930 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
931 mode2g, max_c);
fa1c114f 932
d8ee398d
LR		 933 hw_rates = ath5k_hw_get_rate_table(ah, mode2g);
934 sband->n_bitrates = ath5k_copy_rates(sband->bitrates,
400ec45a 935 hw_rates, max_r);
fa1c114f 936
d8ee398d
LR		 937 count_c = sband->n_channels;
938 count_r = sband->n_bitrates;
fa1c114f 939
d8ee398d
LR		 940 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
941
942 max_r -= count_r;
943 max_c -= count_c;
fa1c114f 944
fa1c114f
JS		 945 }
946
d8ee398d 947 /* 5GHz band */
fa1c114f 948
400ec45a
LR		 949 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
950 struct ieee80211_supported_band *sband =
951 &sbands[IEEE80211_BAND_5GHZ];
fa1c114f 952
d8ee398d
LR		 953 sband->bitrates = &sc->rates[count_r];
954 sband->channels = &sc->channels[count_c];
fa1c114f 955
d8ee398d
LR		 956 sband->band = IEEE80211_BAND_5GHZ;
957 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
958 AR5K_MODE_11A, max_c);
959
960 hw_rates = ath5k_hw_get_rate_table(ah, AR5K_MODE_11A);
961 sband->n_bitrates = ath5k_copy_rates(sband->bitrates,
400ec45a 962 hw_rates, max_r);
d8ee398d
LR		 963
964 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
965 }
966
b446197c 967 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 968
969 return 0;
fa1c114f
JS		 970}
971
972/*
973 * Set/change channels. If the channel is really being changed,
974 * it's done by reseting the chip. To accomplish this we must
975 * first cleanup any pending DMA, then restart stuff after a la
976 * ath5k_init.
977 */
978static int
979ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
980{
981 struct ath5k_hw *ah = sc->ah;
982 int ret;
983
d8ee398d
LR		 984 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
985 sc->curchan->center_freq, chan->center_freq);
986
987 if (chan->center_freq != sc->curchan->center_freq ||
988 chan->hw_value != sc->curchan->hw_value) {
989
990 sc->curchan = chan;
991 sc->curband = &sc->sbands[chan->band];
fa1c114f 992
fa1c114f
JS		 993 /*
994 * To switch channels clear any pending DMA operations;
995 * wait long enough for the RX fifo to drain, reset the
996 * hardware at the new frequency, and then re-enable
997 * the relevant bits of the h/w.
998 */
999 ath5k_hw_set_intr(ah, 0); /* disable interrupts */
1000 ath5k_txq_cleanup(sc); /* clear pending tx frames */
1001 ath5k_rx_stop(sc); /* turn off frame recv */
d8ee398d 1002 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
fa1c114f 1003 if (ret) {
d8ee398d
LR		 1004 ATH5K_ERR(sc, "%s: unable to reset channel "
1005 "(%u Mhz)\n", __func__, chan->center_freq);
fa1c114f
JS		 1006 return ret;
1007 }
d8ee398d 1008
fa1c114f
JS		 1009 ath5k_hw_set_txpower_limit(sc->ah, 0);
1010
1011 /*
1012 * Re-enable rx framework.
1013 */
1014 ret = ath5k_rx_start(sc);
1015 if (ret) {
1016 ATH5K_ERR(sc, "%s: unable to restart recv logic\n",
1017 __func__);
1018 return ret;
1019 }
1020
1021 /*
1022 * Change channels and update the h/w rate map
1023 * if we're switching; e.g. 11a to 11b/g.
1024 *
1025 * XXX needed?
1026 */
1027/* ath5k_chan_change(sc, chan); */
1028
1029 ath5k_beacon_config(sc);
1030 /*
1031 * Re-enable interrupts.
1032 */
1033 ath5k_hw_set_intr(ah, sc->imask);
1034 }
1035
1036 return 0;
1037}
1038
1039static void
1040ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1041{
fa1c114f 1042 sc->curmode = mode;
d8ee398d 1043
400ec45a 1044 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1045 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1046 } else {
1047 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1048 }
fa1c114f
JS		 1049}
1050
1051static void
1052ath5k_mode_setup(struct ath5k_softc *sc)
1053{
1054 struct ath5k_hw *ah = sc->ah;
1055 u32 rfilt;
1056
1057 /* configure rx filter */
1058 rfilt = sc->filter_flags;
1059 ath5k_hw_set_rx_filter(ah, rfilt);
1060
1061 if (ath5k_hw_hasbssidmask(ah))
1062 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1063
1064 /* configure operational mode */
1065 ath5k_hw_set_opmode(ah);
1066
1067 ath5k_hw_set_mcast_filter(ah, 0, 0);
1068 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1069}
1070
d8ee398d
LR		 1071/*
1072 * Match the hw provided rate index (through descriptors)
1073 * to an index for sc->curband->bitrates, so it can be used
1074 * by the stack.
1075 *
1076 * This one is a little bit tricky but i think i'm right
1077 * about this...
1078 *
1079 * We have 4 rate tables in the following order:
1080 * XR (4 rates)
1081 * 802.11a (8 rates)
1082 * 802.11b (4 rates)
1083 * 802.11g (12 rates)
1084 * that make the hw rate table.
1085 *
1086 * Lets take a 5211 for example that supports a and b modes only.
1087 * First comes the 802.11a table and then 802.11b (total 12 rates).
1088 * When hw returns eg. 11 it points to the last 802.11b rate (11Mbit),
1089 * if it returns 2 it points to the second 802.11a rate etc.
1090 *
1091 * Same goes for 5212 who has xr/a/b/g support (total 28 rates).
1092 * First comes the XR table, then 802.11a, 802.11b and 802.11g.
1093 * When hw returns eg. 27 it points to the last 802.11g rate (54Mbits) etc
1094 */
1095static void
400ec45a 1096ath5k_set_total_hw_rates(struct ath5k_softc *sc) {
d8ee398d
LR		 1097
1098 struct ath5k_hw *ah = sc->ah;
1099
400ec45a 1100 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
d8ee398d
LR		 1101 sc->a_rates = 8;
1102
400ec45a 1103 if (test_bit(AR5K_MODE_11B, ah->ah_modes))
d8ee398d
LR		 1104 sc->b_rates = 4;
1105
400ec45a 1106 if (test_bit(AR5K_MODE_11G, ah->ah_modes))
d8ee398d
LR		 1107 sc->g_rates = 12;
1108
1109 /* XXX: Need to see what what happens when
1110 xr disable bits in eeprom are set */
400ec45a 1111 if (ah->ah_version >= AR5K_AR5212)
d8ee398d
LR		 1112 sc->xr_rates = 4;
1113
1114}
1115
1116static inline int
400ec45a 1117ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix) {
d8ee398d
LR		 1118
1119 int mac80211_rix;
1120
400ec45a 1121 if(sc->curband->band == IEEE80211_BAND_2GHZ) {
d8ee398d 1122 /* We setup a g ratetable for both b/g modes */
400ec45a
LR		 1123 mac80211_rix =
1124 hw_rix - sc->b_rates - sc->a_rates - sc->xr_rates;
d8ee398d
LR		 1125 } else {
1126 mac80211_rix = hw_rix - sc->xr_rates;
1127 }
1128
1129 /* Something went wrong, fallback to basic rate for this band */
400ec45a
LR		 1130 if ((mac80211_rix >= sc->curband->n_bitrates) ||
1131 (mac80211_rix <= 0 ))
d8ee398d 1132 mac80211_rix = 1;
d8ee398d
LR		 1133
1134 return mac80211_rix;
1135}
1136
fa1c114f
JS		 1137
1138
1139
1140/***************\
1141* Buffers setup *
1142\***************/
1143
1144static int
1145ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1146{
1147 struct ath5k_hw *ah = sc->ah;
1148 struct sk_buff *skb = bf->skb;
1149 struct ath5k_desc *ds;
1150
1151 if (likely(skb == NULL)) {
1152 unsigned int off;
1153
1154 /*
1155 * Allocate buffer with headroom_needed space for the
1156 * fake physical layer header at the start.
1157 */
1158 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1159 if (unlikely(skb == NULL)) {
1160 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1161 sc->rxbufsize + sc->cachelsz - 1);
1162 return -ENOMEM;
1163 }
1164 /*
1165 * Cache-line-align. This is important (for the
1166 * 5210 at least) as not doing so causes bogus data
1167 * in rx'd frames.
1168 */
1169 off = ((unsigned long)skb->data) % sc->cachelsz;
1170 if (off != 0)
1171 skb_reserve(skb, sc->cachelsz - off);
1172
1173 bf->skb = skb;
1174 bf->skbaddr = pci_map_single(sc->pdev,
1175 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
8d8bb39b 1176 if (unlikely(pci_dma_mapping_error(sc->pdev, bf->skbaddr))) {
fa1c114f
JS		 1177 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1178 dev_kfree_skb(skb);
1179 bf->skb = NULL;
1180 return -ENOMEM;
1181 }
1182 }
1183
1184 /*
1185 * Setup descriptors. For receive we always terminate
1186 * the descriptor list with a self-linked entry so we'll
1187 * not get overrun under high load (as can happen with a
1188 * 5212 when ANI processing enables PHY error frames).
1189 *
1190 * To insure the last descriptor is self-linked we create
1191 * each descriptor as self-linked and add it to the end. As
1192 * each additional descriptor is added the previous self-linked
1193 * entry is ``fixed'' naturally. This should be safe even
1194 * if DMA is happening. When processing RX interrupts we
1195 * never remove/process the last, self-linked, entry on the
1196 * descriptor list. This insures the hardware always has
1197 * someplace to write a new frame.
1198 */
1199 ds = bf->desc;
1200 ds->ds_link = bf->daddr; /* link to self */
1201 ds->ds_data = bf->skbaddr;
1202 ath5k_hw_setup_rx_desc(ah, ds,
1203 skb_tailroom(skb), /* buffer size */
1204 0);
1205
1206 if (sc->rxlink != NULL)
1207 *sc->rxlink = bf->daddr;
1208 sc->rxlink = &ds->ds_link;
1209 return 0;
1210}
1211
1212static int
e039fa4a 1213ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1214{
1215 struct ath5k_hw *ah = sc->ah;
1216 struct ath5k_txq *txq = sc->txq;
1217 struct ath5k_desc *ds = bf->desc;
1218 struct sk_buff *skb = bf->skb;
a888d52d 1219 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1220 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1221 int ret;
1222
1223 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1224
fa1c114f
JS		 1225 /* XXX endianness */
1226 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1227 PCI_DMA_TODEVICE);
1228
e039fa4a 1229 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1230 flags |= AR5K_TXDESC_NOACK;
1231
281c56dd 1232 pktlen = skb->len;
fa1c114f 1233
d0f09804 1234 if (info->control.hw_key) {
e039fa4a
JB		 1235 keyidx = info->control.hw_key->hw_key_idx;
1236 pktlen += info->control.icv_len;
fa1c114f 1237 }
fa1c114f
JS		 1238 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1239 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
2e92e6f2 1240 (sc->power_level * 2),
e039fa4a
JB		 1241 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1242 info->control.retry_limit, keyidx, 0, flags, 0, 0);
fa1c114f
JS		 1243 if (ret)
1244 goto err_unmap;
1245
1246 ds->ds_link = 0;
1247 ds->ds_data = bf->skbaddr;
1248
1249 spin_lock_bh(&txq->lock);
1250 list_add_tail(&bf->list, &txq->q);
57ffc589 1251 sc->tx_stats[txq->qnum].len++;
fa1c114f
JS		 1252 if (txq->link == NULL) /* is this first packet? */
1253 ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr);
1254 else /* no, so only link it */
1255 *txq->link = bf->daddr;
1256
1257 txq->link = &ds->ds_link;
1258 ath5k_hw_tx_start(ah, txq->qnum);
274c7c36 1259 mmiowb();
fa1c114f
JS		 1260 spin_unlock_bh(&txq->lock);
1261
1262 return 0;
1263err_unmap:
1264 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1265 return ret;
1266}
1267
1268/*******************\
1269* Descriptors setup *
1270\*******************/
1271
1272static int
1273ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1274{
1275 struct ath5k_desc *ds;
1276 struct ath5k_buf *bf;
1277 dma_addr_t da;
1278 unsigned int i;
1279 int ret;
1280
1281 /* allocate descriptors */
1282 sc->desc_len = sizeof(struct ath5k_desc) *
1283 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1284 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1285 if (sc->desc == NULL) {
1286 ATH5K_ERR(sc, "can't allocate descriptors\n");
1287 ret = -ENOMEM;
1288 goto err;
1289 }
1290 ds = sc->desc;
1291 da = sc->desc_daddr;
1292 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1293 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1294
1295 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1296 sizeof(struct ath5k_buf), GFP_KERNEL);
1297 if (bf == NULL) {
1298 ATH5K_ERR(sc, "can't allocate bufptr\n");
1299 ret = -ENOMEM;
1300 goto err_free;
1301 }
1302 sc->bufptr = bf;
1303
1304 INIT_LIST_HEAD(&sc->rxbuf);
1305 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1306 bf->desc = ds;
1307 bf->daddr = da;
1308 list_add_tail(&bf->list, &sc->rxbuf);
1309 }
1310
1311 INIT_LIST_HEAD(&sc->txbuf);
1312 sc->txbuf_len = ATH_TXBUF;
1313 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1314 da += sizeof(*ds)) {
1315 bf->desc = ds;
1316 bf->daddr = da;
1317 list_add_tail(&bf->list, &sc->txbuf);
1318 }
1319
1320 /* beacon buffer */
1321 bf->desc = ds;
1322 bf->daddr = da;
1323 sc->bbuf = bf;
1324
1325 return 0;
1326err_free:
1327 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1328err:
1329 sc->desc = NULL;
1330 return ret;
1331}
1332
1333static void
1334ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1335{
1336 struct ath5k_buf *bf;
1337
1338 ath5k_txbuf_free(sc, sc->bbuf);
1339 list_for_each_entry(bf, &sc->txbuf, list)
1340 ath5k_txbuf_free(sc, bf);
1341 list_for_each_entry(bf, &sc->rxbuf, list)
1342 ath5k_txbuf_free(sc, bf);
1343
1344 /* Free memory associated with all descriptors */
1345 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1346
1347 kfree(sc->bufptr);
1348 sc->bufptr = NULL;
1349}
1350
1351
1352
1353
1354
1355/**************\
1356* Queues setup *
1357\**************/
1358
1359static struct ath5k_txq *
1360ath5k_txq_setup(struct ath5k_softc *sc,
1361 int qtype, int subtype)
1362{
1363 struct ath5k_hw *ah = sc->ah;
1364 struct ath5k_txq *txq;
1365 struct ath5k_txq_info qi = {
1366 .tqi_subtype = subtype,
1367 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1368 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1369 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1370 };
1371 int qnum;
1372
1373 /*
1374 * Enable interrupts only for EOL and DESC conditions.
1375 * We mark tx descriptors to receive a DESC interrupt
1376 * when a tx queue gets deep; otherwise waiting for the
1377 * EOL to reap descriptors. Note that this is done to
1378 * reduce interrupt load and this only defers reaping
1379 * descriptors, never transmitting frames. Aside from
1380 * reducing interrupts this also permits more concurrency.
1381 * The only potential downside is if the tx queue backs
1382 * up in which case the top half of the kernel may backup
1383 * due to a lack of tx descriptors.
1384 */
1385 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1386 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1387 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1388 if (qnum < 0) {
1389 /*
1390 * NB: don't print a message, this happens
1391 * normally on parts with too few tx queues
1392 */
1393 return ERR_PTR(qnum);
1394 }
1395 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1396 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1397 qnum, ARRAY_SIZE(sc->txqs));
1398 ath5k_hw_release_tx_queue(ah, qnum);
1399 return ERR_PTR(-EINVAL);
1400 }
1401 txq = &sc->txqs[qnum];
1402 if (!txq->setup) {
1403 txq->qnum = qnum;
1404 txq->link = NULL;
1405 INIT_LIST_HEAD(&txq->q);
1406 spin_lock_init(&txq->lock);
1407 txq->setup = true;
1408 }
1409 return &sc->txqs[qnum];
1410}
1411
1412static int
1413ath5k_beaconq_setup(struct ath5k_hw *ah)
1414{
1415 struct ath5k_txq_info qi = {
1416 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1417 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1418 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1419 /* NB: for dynamic turbo, don't enable any other interrupts */
1420 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1421 };
1422
1423 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1424}
1425
1426static int
1427ath5k_beaconq_config(struct ath5k_softc *sc)
1428{
1429 struct ath5k_hw *ah = sc->ah;
1430 struct ath5k_txq_info qi;
1431 int ret;
1432
1433 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1434 if (ret)
1435 return ret;
6d91e1d8 1436 if (sc->opmode == IEEE80211_IF_TYPE_AP) {
fa1c114f
JS		 1437 /*
1438 * Always burst out beacon and CAB traffic
1439 * (aifs = cwmin = cwmax = 0)
1440 */
1441 qi.tqi_aifs = 0;
1442 qi.tqi_cw_min = 0;
1443 qi.tqi_cw_max = 0;
6d91e1d8
BR		 1444 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
1445 /*
1446 * Adhoc mode; backoff between 0 and (2 * cw_min).
1447 */
1448 qi.tqi_aifs = 0;
1449 qi.tqi_cw_min = 0;
1450 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1451 }
1452
6d91e1d8
BR		 1453 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1454 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1455 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1456
fa1c114f
JS		 1457 ret = ath5k_hw_setup_tx_queueprops(ah, sc->bhalq, &qi);
1458 if (ret) {
1459 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1460 "hardware queue!\n", __func__);
1461 return ret;
1462 }
1463
1464 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1465}
1466
1467static void
1468ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1469{
1470 struct ath5k_buf *bf, *bf0;
1471
1472 /*
1473 * NB: this assumes output has been stopped and
1474 * we do not need to block ath5k_tx_tasklet
1475 */
1476 spin_lock_bh(&txq->lock);
1477 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1478 ath5k_debug_printtxbuf(sc, bf);
fa1c114f
JS		 1479
1480 ath5k_txbuf_free(sc, bf);
1481
1482 spin_lock_bh(&sc->txbuflock);
57ffc589 1483 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1484 list_move_tail(&bf->list, &sc->txbuf);
1485 sc->txbuf_len++;
1486 spin_unlock_bh(&sc->txbuflock);
1487 }
1488 txq->link = NULL;
1489 spin_unlock_bh(&txq->lock);
1490}
1491
1492/*
1493 * Drain the transmit queues and reclaim resources.
1494 */
1495static void
1496ath5k_txq_cleanup(struct ath5k_softc *sc)
1497{
1498 struct ath5k_hw *ah = sc->ah;
1499 unsigned int i;
1500
1501 /* XXX return value */
1502 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1503 /* don't touch the hardware if marked invalid */
1504 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1505 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1506 ath5k_hw_get_tx_buf(ah, sc->bhalq));
1507 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1508 if (sc->txqs[i].setup) {
1509 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1510 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1511 "link %p\n",
1512 sc->txqs[i].qnum,
1513 ath5k_hw_get_tx_buf(ah,
1514 sc->txqs[i].qnum),
1515 sc->txqs[i].link);
1516 }
1517 }
36d6825b 1518 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
fa1c114f
JS		 1519
1520 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1521 if (sc->txqs[i].setup)
1522 ath5k_txq_drainq(sc, &sc->txqs[i]);
1523}
1524
1525static void
1526ath5k_txq_release(struct ath5k_softc *sc)
1527{
1528 struct ath5k_txq *txq = sc->txqs;
1529 unsigned int i;
1530
1531 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1532 if (txq->setup) {
1533 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1534 txq->setup = false;
1535 }
1536}
1537
1538
1539
1540
1541/*************\
1542* RX Handling *
1543\*************/
1544
1545/*
1546 * Enable the receive h/w following a reset.
1547 */
1548static int
1549ath5k_rx_start(struct ath5k_softc *sc)
1550{
1551 struct ath5k_hw *ah = sc->ah;
1552 struct ath5k_buf *bf;
1553 int ret;
1554
1555 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1556
1557 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1558 sc->cachelsz, sc->rxbufsize);
1559
1560 sc->rxlink = NULL;
1561
1562 spin_lock_bh(&sc->rxbuflock);
1563 list_for_each_entry(bf, &sc->rxbuf, list) {
1564 ret = ath5k_rxbuf_setup(sc, bf);
1565 if (ret != 0) {
1566 spin_unlock_bh(&sc->rxbuflock);
1567 goto err;
1568 }
1569 }
1570 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1571 spin_unlock_bh(&sc->rxbuflock);
1572
1573 ath5k_hw_put_rx_buf(ah, bf->daddr);
1574 ath5k_hw_start_rx(ah); /* enable recv descriptors */
1575 ath5k_mode_setup(sc); /* set filters, etc. */
1576 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1577
1578 return 0;
1579err:
1580 return ret;
1581}
1582
1583/*
1584 * Disable the receive h/w in preparation for a reset.
1585 */
1586static void
1587ath5k_rx_stop(struct ath5k_softc *sc)
1588{
1589 struct ath5k_hw *ah = sc->ah;
1590
1591 ath5k_hw_stop_pcu_recv(ah); /* disable PCU */
1592 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1593 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f
JS		 1594
1595 ath5k_debug_printrxbuffs(sc, ah);
1596
1597 sc->rxlink = NULL; /* just in case */
1598}
1599
1600static unsigned int
1601ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1602 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f
JS		 1603{
1604 struct ieee80211_hdr *hdr = (void *)skb->data;
1605 unsigned int keyix, hlen = ieee80211_get_hdrlen_from_skb(skb);
1606
b47f407b
BR		 1607 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1608 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1609 return RX_FLAG_DECRYPTED;
1610
1611 /* Apparently when a default key is used to decrypt the packet
1612 the hw does not set the index used to decrypt. In such cases
1613 get the index from the packet. */
24b56e70
HH		 1614 if (ieee80211_has_protected(hdr->frame_control) &&
1615 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1616 skb->len >= hlen + 4) {
fa1c114f
JS		 1617 keyix = skb->data[hlen + 3] >> 6;
1618
1619 if (test_bit(keyix, sc->keymap))
1620 return RX_FLAG_DECRYPTED;
1621 }
1622
1623 return 0;
1624}
1625
036cd1ec
BR		 1626
1627static void
6ba81c2c
BR		 1628ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1629 struct ieee80211_rx_status *rxs)
036cd1ec 1630{
6ba81c2c 1631 u64 tsf, bc_tstamp;
036cd1ec
BR		 1632 u32 hw_tu;
1633 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1634
24b56e70 1635 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1636 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
036cd1ec
BR		 1637 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1638 /*
6ba81c2c
BR		 1639 * Received an IBSS beacon with the same BSSID. Hardware *must*
1640 * have updated the local TSF. We have to work around various
1641 * hardware bugs, though...
036cd1ec 1642 */
6ba81c2c
BR		 1643 tsf = ath5k_hw_get_tsf64(sc->ah);
1644 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1645 hw_tu = TSF_TO_TU(tsf);
1646
1647 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1648 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1649 (unsigned long long)bc_tstamp,
1650 (unsigned long long)rxs->mactime,
1651 (unsigned long long)(rxs->mactime - bc_tstamp),
1652 (unsigned long long)tsf);
6ba81c2c
BR		 1653
1654 /*
1655 * Sometimes the HW will give us a wrong tstamp in the rx
1656 * status, causing the timestamp extension to go wrong.
1657 * (This seems to happen especially with beacon frames bigger
1658 * than 78 byte (incl. FCS))
1659 * But we know that the receive timestamp must be later than the
1660 * timestamp of the beacon since HW must have synced to that.
1661 *
1662 * NOTE: here we assume mactime to be after the frame was
1663 * received, not like mac80211 which defines it at the start.
1664 */
1665 if (bc_tstamp > rxs->mactime) {
036cd1ec 1666 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1667 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1668 (unsigned long long)rxs->mactime,
1669 (unsigned long long)tsf);
6ba81c2c 1670 rxs->mactime = tsf;
036cd1ec 1671 }
6ba81c2c
BR		 1672
1673 /*
1674 * Local TSF might have moved higher than our beacon timers,
1675 * in that case we have to update them to continue sending
1676 * beacons. This also takes care of synchronizing beacon sending
1677 * times with other stations.
1678 */
1679 if (hw_tu >= sc->nexttbtt)
1680 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1681 }
1682}
1683
1684
fa1c114f
JS		 1685static void
1686ath5k_tasklet_rx(unsigned long data)
1687{
1688 struct ieee80211_rx_status rxs = {};
b47f407b 1689 struct ath5k_rx_status rs = {};
fa1c114f
JS		 1690 struct sk_buff *skb;
1691 struct ath5k_softc *sc = (void *)data;
3a0f2c87 1692 struct ath5k_buf *bf, *bf_last;
fa1c114f 1693 struct ath5k_desc *ds;
fa1c114f
JS		 1694 int ret;
1695 int hdrlen;
1696 int pad;
1697
1698 spin_lock(&sc->rxbuflock);
3a0f2c87
JS		 1699 if (list_empty(&sc->rxbuf)) {
1700 ATH5K_WARN(sc, "empty rx buf pool\n");
1701 goto unlock;
1702 }
1703 bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
fa1c114f 1704 do {
d6894b5b
BC		 1705 rxs.flag = 0;
1706
fa1c114f
JS		 1707 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1708 BUG_ON(bf->skb == NULL);
1709 skb = bf->skb;
1710 ds = bf->desc;
1711
3a0f2c87
JS		 1712 /*
1713 * last buffer must not be freed to ensure proper hardware
1714 * function. When the hardware finishes also a packet next to
1715 * it, we are sure, it doesn't use it anymore and we can go on.
1716 */
1717 if (bf_last == bf)
1718 bf->flags |= 1;
1719 if (bf->flags) {
1720 struct ath5k_buf *bf_next = list_entry(bf->list.next,
1721 struct ath5k_buf, list);
1722 ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1723 &rs);
1724 if (ret)
1725 break;
1726 bf->flags &= ~1;
1727 /* skip the overwritten one (even status is martian) */
1728 goto next;
1729 }
fa1c114f 1730
b47f407b 1731 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1732 if (unlikely(ret == -EINPROGRESS))
1733 break;
1734 else if (unlikely(ret)) {
1735 ATH5K_ERR(sc, "error in processing rx descriptor\n");
65872e6b 1736 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1737 return;
1738 }
1739
b47f407b 1740 if (unlikely(rs.rs_more)) {
fa1c114f
JS		 1741 ATH5K_WARN(sc, "unsupported jumbo\n");
1742 goto next;
1743 }
1744
b47f407b
BR		 1745 if (unlikely(rs.rs_status)) {
1746 if (rs.rs_status & AR5K_RXERR_PHY)
fa1c114f 1747 goto next;
b47f407b 1748 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1749 /*
1750 * Decrypt error. If the error occurred
1751 * because there was no hardware key, then
1752 * let the frame through so the upper layers
1753 * can process it. This is necessary for 5210
1754 * parts which have no way to setup a ``clear''
1755 * key cache entry.
1756 *
1757 * XXX do key cache faulting
1758 */
b47f407b
BR		 1759 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1760 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1761 goto accept;
1762 }
b47f407b 1763 if (rs.rs_status & AR5K_RXERR_MIC) {
fa1c114f
JS		 1764 rxs.flag |= RX_FLAG_MMIC_ERROR;
1765 goto accept;
1766 }
1767
1768 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1769 if ((rs.rs_status &
1770 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
fa1c114f
JS		 1771 sc->opmode != IEEE80211_IF_TYPE_MNTR)
1772 goto next;
1773 }
1774accept:
fa1c114f
JS		 1775 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1776 PCI_DMA_FROMDEVICE);
1777 bf->skb = NULL;
1778
b47f407b 1779 skb_put(skb, rs.rs_datalen);
fa1c114f
JS		 1780
1781 /*
1782 * the hardware adds a padding to 4 byte boundaries between
1783 * the header and the payload data if the header length is
1784 * not multiples of 4 - remove it
1785 */
1786 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1787 if (hdrlen & 3) {
1788 pad = hdrlen % 4;
1789 memmove(skb->data + pad, skb->data, hdrlen);
1790 skb_pull(skb, pad);
1791 }
1792
c0e1899b
BR		 1793 /*
1794 * always extend the mac timestamp, since this information is
1795 * also needed for proper IBSS merging.
1796 *
1797 * XXX: it might be too late to do it here, since rs_tstamp is
1798 * 15bit only. that means TSF extension has to be done within
1799 * 32768usec (about 32ms). it might be necessary to move this to
1800 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 1801 *
1802 * Unfortunately we don't know when the hardware takes the rx
1803 * timestamp (beginning of phy frame, data frame, end of rx?).
1804 * The only thing we know is that it is hardware specific...
1805 * On AR5213 it seems the rx timestamp is at the end of the
1806 * frame, but i'm not sure.
1807 *
1808 * NOTE: mac80211 defines mactime at the beginning of the first
1809 * data symbol. Since we don't have any time references it's
1810 * impossible to comply to that. This affects IBSS merge only
1811 * right now, so it's not too bad...
c0e1899b 1812 */
b47f407b 1813 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
c0e1899b
BR		 1814 rxs.flag |= RX_FLAG_TSFT;
1815
d8ee398d
LR		 1816 rxs.freq = sc->curchan->center_freq;
1817 rxs.band = sc->curband->band;
fa1c114f 1818
fa1c114f 1819 rxs.noise = sc->ah->ah_noise_floor;
566bfe5a
BR		 1820 rxs.signal = rxs.noise + rs.rs_rssi;
1821 rxs.qual = rs.rs_rssi * 100 / 64;
fa1c114f 1822
b47f407b
BR		 1823 rxs.antenna = rs.rs_antenna;
1824 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1825 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f
JS		 1826
1827 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1828
036cd1ec
BR		 1829 /* check beacons in IBSS mode */
1830 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
6ba81c2c 1831 ath5k_check_ibss_tsf(sc, skb, &rxs);
036cd1ec 1832
fa1c114f 1833 __ieee80211_rx(sc->hw, skb, &rxs);
fa1c114f
JS		 1834next:
1835 list_move_tail(&bf->list, &sc->rxbuf);
1836 } while (ath5k_rxbuf_setup(sc, bf) == 0);
3a0f2c87 1837unlock:
fa1c114f
JS		 1838 spin_unlock(&sc->rxbuflock);
1839}
1840
1841
1842
1843
1844/*************\
1845* TX Handling *
1846\*************/
1847
1848static void
1849ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1850{
b47f407b 1851 struct ath5k_tx_status ts = {};
fa1c114f
JS		 1852 struct ath5k_buf *bf, *bf0;
1853 struct ath5k_desc *ds;
1854 struct sk_buff *skb;
e039fa4a 1855 struct ieee80211_tx_info *info;
fa1c114f
JS		 1856 int ret;
1857
1858 spin_lock(&txq->lock);
1859 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1860 ds = bf->desc;
1861
b47f407b 1862 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 1863 if (unlikely(ret == -EINPROGRESS))
1864 break;
1865 else if (unlikely(ret)) {
1866 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1867 ret, txq->qnum);
1868 break;
1869 }
1870
1871 skb = bf->skb;
a888d52d 1872 info = IEEE80211_SKB_CB(skb);
fa1c114f 1873 bf->skb = NULL;
e039fa4a 1874
fa1c114f
JS		 1875 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1876 PCI_DMA_TODEVICE);
1877
e039fa4a 1878 info->status.retry_count = ts.ts_shortretry + ts.ts_longretry / 6;
b47f407b 1879 if (unlikely(ts.ts_status)) {
fa1c114f 1880 sc->ll_stats.dot11ACKFailureCount++;
b47f407b 1881 if (ts.ts_status & AR5K_TXERR_XRETRY)
e039fa4a 1882 info->status.excessive_retries = 1;
b47f407b 1883 else if (ts.ts_status & AR5K_TXERR_FILT)
e039fa4a 1884 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
fa1c114f 1885 } else {
e039fa4a
JB		 1886 info->flags |= IEEE80211_TX_STAT_ACK;
1887 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 1888 }
1889
e039fa4a 1890 ieee80211_tx_status(sc->hw, skb);
57ffc589 1891 sc->tx_stats[txq->qnum].count++;
fa1c114f
JS		 1892
1893 spin_lock(&sc->txbuflock);
57ffc589 1894 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1895 list_move_tail(&bf->list, &sc->txbuf);
1896 sc->txbuf_len++;
1897 spin_unlock(&sc->txbuflock);
1898 }
1899 if (likely(list_empty(&txq->q)))
1900 txq->link = NULL;
1901 spin_unlock(&txq->lock);
1902 if (sc->txbuf_len > ATH_TXBUF / 5)
1903 ieee80211_wake_queues(sc->hw);
1904}
1905
1906static void
1907ath5k_tasklet_tx(unsigned long data)
1908{
1909 struct ath5k_softc *sc = (void *)data;
1910
1911 ath5k_tx_processq(sc, sc->txq);
fa1c114f
JS		 1912}
1913
1914
fa1c114f
JS		 1915/*****************\
1916* Beacon handling *
1917\*****************/
1918
1919/*
1920 * Setup the beacon frame for transmit.
1921 */
1922static int
e039fa4a 1923ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1924{
1925 struct sk_buff *skb = bf->skb;
a888d52d 1926 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1927 struct ath5k_hw *ah = sc->ah;
1928 struct ath5k_desc *ds;
1929 int ret, antenna = 0;
1930 u32 flags;
1931
1932 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1933 PCI_DMA_TODEVICE);
1934 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1935 "skbaddr %llx\n", skb, skb->data, skb->len,
1936 (unsigned long long)bf->skbaddr);
8d8bb39b 1937 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 1938 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1939 return -EIO;
1940 }
1941
1942 ds = bf->desc;
1943
1944 flags = AR5K_TXDESC_NOACK;
1945 if (sc->opmode == IEEE80211_IF_TYPE_IBSS && ath5k_hw_hasveol(ah)) {
1946 ds->ds_link = bf->daddr; /* self-linked */
1947 flags |= AR5K_TXDESC_VEOL;
1948 /*
1949 * Let hardware handle antenna switching if txantenna is not set
1950 */
1951 } else {
1952 ds->ds_link = 0;
1953 /*
1954 * Switch antenna every 4 beacons if txantenna is not set
1955 * XXX assumes two antennas
1956 */
1957 if (antenna == 0)
1958 antenna = sc->bsent & 4 ? 2 : 1;
1959 }
1960
1961 ds->ds_data = bf->skbaddr;
281c56dd 1962 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
fa1c114f 1963 ieee80211_get_hdrlen_from_skb(skb),
400ec45a 1964 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 1965 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 1966 1, AR5K_TXKEYIX_INVALID,
400ec45a 1967 antenna, flags, 0, 0);
fa1c114f
JS		 1968 if (ret)
1969 goto err_unmap;
1970
1971 return 0;
1972err_unmap:
1973 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1974 return ret;
1975}
1976
1977/*
1978 * Transmit a beacon frame at SWBA. Dynamic updates to the
1979 * frame contents are done as needed and the slot time is
1980 * also adjusted based on current state.
1981 *
1982 * this is usually called from interrupt context (ath5k_intr())
1983 * but also from ath5k_beacon_config() in IBSS mode which in turn
1984 * can be called from a tasklet and user context
1985 */
1986static void
1987ath5k_beacon_send(struct ath5k_softc *sc)
1988{
1989 struct ath5k_buf *bf = sc->bbuf;
1990 struct ath5k_hw *ah = sc->ah;
1991
be9b7259 1992 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f
JS		 1993
1994 if (unlikely(bf->skb == NULL || sc->opmode == IEEE80211_IF_TYPE_STA ||
1995 sc->opmode == IEEE80211_IF_TYPE_MNTR)) {
1996 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1997 return;
1998 }
1999 /*
2000 * Check if the previous beacon has gone out. If
2001 * not don't don't try to post another, skip this
2002 * period and wait for the next. Missed beacons
2003 * indicate a problem and should not occur. If we
2004 * miss too many consecutive beacons reset the device.
2005 */
2006 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2007 sc->bmisscount++;
be9b7259 2008 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2009 "missed %u consecutive beacons\n", sc->bmisscount);
2010 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
be9b7259 2011 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2012 "stuck beacon time (%u missed)\n",
2013 sc->bmisscount);
2014 tasklet_schedule(&sc->restq);
2015 }
2016 return;
2017 }
2018 if (unlikely(sc->bmisscount != 0)) {
be9b7259 2019 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2020 "resume beacon xmit after %u misses\n",
2021 sc->bmisscount);
2022 sc->bmisscount = 0;
2023 }
2024
2025 /*
2026 * Stop any current dma and put the new frame on the queue.
2027 * This should never fail since we check above that no frames
2028 * are still pending on the queue.
2029 */
2030 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2031 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2032 /* NB: hw still stops DMA, so proceed */
2033 }
fa1c114f
JS		 2034
2035 ath5k_hw_put_tx_buf(ah, sc->bhalq, bf->daddr);
2036 ath5k_hw_tx_start(ah, sc->bhalq);
be9b7259 2037 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2038 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2039
2040 sc->bsent++;
2041}
2042
2043
9804b98d
BR		 2044/**
2045 * ath5k_beacon_update_timers - update beacon timers
2046 *
2047 * @sc: struct ath5k_softc pointer we are operating on
2048 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2049 * beacon timer update based on the current HW TSF.
2050 *
2051 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2052 * of a received beacon or the current local hardware TSF and write it to the
2053 * beacon timer registers.
2054 *
2055 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2056 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2057 * when we otherwise know we have to update the timers, but we keep it in this
2058 * function to have it all together in one place.
2059 */
fa1c114f 2060static void
9804b98d 2061ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2062{
2063 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2064 u32 nexttbtt, intval, hw_tu, bc_tu;
2065 u64 hw_tsf;
fa1c114f
JS		 2066
2067 intval = sc->bintval & AR5K_BEACON_PERIOD;
2068 if (WARN_ON(!intval))
2069 return;
2070
9804b98d
BR		 2071 /* beacon TSF converted to TU */
2072 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2073
9804b98d
BR		 2074 /* current TSF converted to TU */
2075 hw_tsf = ath5k_hw_get_tsf64(ah);
2076 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2077
9804b98d
BR		 2078#define FUDGE 3
2079 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2080 if (bc_tsf == -1) {
2081 /*
2082 * no beacons received, called internally.
2083 * just need to refresh timers based on HW TSF.
2084 */
2085 nexttbtt = roundup(hw_tu + FUDGE, intval);
2086 } else if (bc_tsf == 0) {
2087 /*
2088 * no beacon received, probably called by ath5k_reset_tsf().
2089 * reset TSF to start with 0.
2090 */
2091 nexttbtt = intval;
2092 intval |= AR5K_BEACON_RESET_TSF;
2093 } else if (bc_tsf > hw_tsf) {
2094 /*
2095 * beacon received, SW merge happend but HW TSF not yet updated.
2096 * not possible to reconfigure timers yet, but next time we
2097 * receive a beacon with the same BSSID, the hardware will
2098 * automatically update the TSF and then we need to reconfigure
2099 * the timers.
2100 */
2101 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2102 "need to wait for HW TSF sync\n");
2103 return;
2104 } else {
2105 /*
2106 * most important case for beacon synchronization between STA.
2107 *
2108 * beacon received and HW TSF has been already updated by HW.
2109 * update next TBTT based on the TSF of the beacon, but make
2110 * sure it is ahead of our local TSF timer.
2111 */
2112 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2113 }
2114#undef FUDGE
fa1c114f 2115
036cd1ec
BR		 2116 sc->nexttbtt = nexttbtt;
2117
fa1c114f 2118 intval |= AR5K_BEACON_ENA;
fa1c114f 2119 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2120
2121 /*
2122 * debugging output last in order to preserve the time critical aspect
2123 * of this function
2124 */
2125 if (bc_tsf == -1)
2126 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2127 "reconfigured timers based on HW TSF\n");
2128 else if (bc_tsf == 0)
2129 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2130 "reset HW TSF and timers\n");
2131 else
2132 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2133 "updated timers based on beacon TSF\n");
2134
2135 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2136 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2137 (unsigned long long) bc_tsf,
2138 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2139 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2140 intval & AR5K_BEACON_PERIOD,
2141 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2142 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2143}
2144
2145
036cd1ec
BR		 2146/**
2147 * ath5k_beacon_config - Configure the beacon queues and interrupts
2148 *
2149 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f
JS		 2150 *
2151 * When operating in station mode we want to receive a BMISS interrupt when we
2152 * stop seeing beacons from the AP we've associated with so we can look for
2153 * another AP to associate with.
2154 *
036cd1ec 2155 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2156 * interrupts to detect TSF updates only.
036cd1ec
BR		 2157 *
2158 * AP mode is missing.
fa1c114f
JS		 2159 */
2160static void
2161ath5k_beacon_config(struct ath5k_softc *sc)
2162{
2163 struct ath5k_hw *ah = sc->ah;
2164
2165 ath5k_hw_set_intr(ah, 0);
2166 sc->bmisscount = 0;
dc1968e7 2167 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f
JS		 2168
2169 if (sc->opmode == IEEE80211_IF_TYPE_STA) {
2170 sc->imask |= AR5K_INT_BMISS;
2171 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2172 /*
036cd1ec
BR		 2173 * In IBSS mode we use a self-linked tx descriptor and let the
2174 * hardware send the beacons automatically. We have to load it
fa1c114f 2175 * only once here.
036cd1ec 2176 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2177 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2178 */
2179 ath5k_beaconq_config(sc);
fa1c114f 2180
036cd1ec
BR		 2181 sc->imask |= AR5K_INT_SWBA;
2182
00482973
JS		 2183 if (ath5k_hw_hasveol(ah)) {
2184 spin_lock(&sc->block);
fa1c114f 2185 ath5k_beacon_send(sc);
00482973
JS		 2186 spin_unlock(&sc->block);
2187 }
fa1c114f
JS		 2188 }
2189 /* TODO else AP */
2190
2191 ath5k_hw_set_intr(ah, sc->imask);
2192}
2193
2194
2195/********************\
2196* Interrupt handling *
2197\********************/
2198
2199static int
2200ath5k_init(struct ath5k_softc *sc)
2201{
2202 int ret;
2203
2204 mutex_lock(&sc->lock);
2205
2206 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2207
2208 /*
2209 * Stop anything previously setup. This is safe
2210 * no matter this is the first time through or not.
2211 */
2212 ath5k_stop_locked(sc);
2213
2214 /*
2215 * The basic interface to setting the hardware in a good
2216 * state is ``reset''. On return the hardware is known to
2217 * be powered up and with interrupts disabled. This must
2218 * be followed by initialization of the appropriate bits
2219 * and then setup of the interrupt mask.
2220 */
d8ee398d
LR		 2221 sc->curchan = sc->hw->conf.channel;
2222 sc->curband = &sc->sbands[sc->curchan->band];
fa1c114f
JS		 2223 ret = ath5k_hw_reset(sc->ah, sc->opmode, sc->curchan, false);
2224 if (ret) {
2225 ATH5K_ERR(sc, "unable to reset hardware: %d\n", ret);
2226 goto done;
2227 }
2228 /*
2229 * This is needed only to setup initial state
2230 * but it's best done after a reset.
2231 */
2232 ath5k_hw_set_txpower_limit(sc->ah, 0);
2233
2234 /*
2235 * Setup the hardware after reset: the key cache
2236 * is filled as needed and the receive engine is
2237 * set going. Frame transmit is handled entirely
2238 * in the frame output path; there's nothing to do
2239 * here except setup the interrupt mask.
2240 */
2241 ret = ath5k_rx_start(sc);
2242 if (ret)
2243 goto done;
2244
2245 /*
2246 * Enable interrupts.
2247 */
2248 sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
194828a2
NK		 2249 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL |
2250 AR5K_INT_MIB;
fa1c114f
JS		 2251
2252 ath5k_hw_set_intr(sc->ah, sc->imask);
2253 /* Set ack to be sent at low bit-rates */
2254 ath5k_hw_set_ack_bitrate_high(sc->ah, false);
2255
2256 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2257 msecs_to_jiffies(ath5k_calinterval * 1000)));
2258
2259 ret = 0;
2260done:
274c7c36 2261 mmiowb();
fa1c114f
JS		 2262 mutex_unlock(&sc->lock);
2263 return ret;
2264}
2265
2266static int
2267ath5k_stop_locked(struct ath5k_softc *sc)
2268{
2269 struct ath5k_hw *ah = sc->ah;
2270
2271 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2272 test_bit(ATH_STAT_INVALID, sc->status));
2273
2274 /*
2275 * Shutdown the hardware and driver:
2276 * stop output from above
2277 * disable interrupts
2278 * turn off timers
2279 * turn off the radio
2280 * clear transmit machinery
2281 * clear receive machinery
2282 * drain and release tx queues
2283 * reclaim beacon resources
2284 * power down hardware
2285 *
2286 * Note that some of this work is not possible if the
2287 * hardware is gone (invalid).
2288 */
2289 ieee80211_stop_queues(sc->hw);
2290
2291 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2292 ath5k_led_off(sc);
fa1c114f 2293 ath5k_hw_set_intr(ah, 0);
274c7c36 2294 synchronize_irq(sc->pdev->irq);
fa1c114f
JS		 2295 }
2296 ath5k_txq_cleanup(sc);
2297 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2298 ath5k_rx_stop(sc);
2299 ath5k_hw_phy_disable(ah);
2300 } else
2301 sc->rxlink = NULL;
2302
2303 return 0;
2304}
2305
2306/*
2307 * Stop the device, grabbing the top-level lock to protect
2308 * against concurrent entry through ath5k_init (which can happen
2309 * if another thread does a system call and the thread doing the
2310 * stop is preempted).
2311 */
2312static int
2313ath5k_stop_hw(struct ath5k_softc *sc)
2314{
2315 int ret;
2316
2317 mutex_lock(&sc->lock);
2318 ret = ath5k_stop_locked(sc);
2319 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2320 /*
2321 * Set the chip in full sleep mode. Note that we are
2322 * careful to do this only when bringing the interface
2323 * completely to a stop. When the chip is in this state
2324 * it must be carefully woken up or references to
2325 * registers in the PCI clock domain may freeze the bus
2326 * (and system). This varies by chip and is mostly an
2327 * issue with newer parts that go to sleep more quickly.
2328 */
2329 if (sc->ah->ah_mac_srev >= 0x78) {
2330 /*
2331 * XXX
2332 * don't put newer MAC revisions > 7.8 to sleep because
2333 * of the above mentioned problems
2334 */
2335 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2336 "not putting device to sleep\n");
2337 } else {
2338 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2339 "putting device to full sleep\n");
2340 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2341 }
2342 }
2343 ath5k_txbuf_free(sc, sc->bbuf);
274c7c36 2344 mmiowb();
fa1c114f
JS		 2345 mutex_unlock(&sc->lock);
2346
2347 del_timer_sync(&sc->calib_tim);
10488f8a
JS		 2348 tasklet_kill(&sc->rxtq);
2349 tasklet_kill(&sc->txtq);
2350 tasklet_kill(&sc->restq);
fa1c114f
JS		 2351
2352 return ret;
2353}
2354
2355static irqreturn_t
2356ath5k_intr(int irq, void *dev_id)
2357{
2358 struct ath5k_softc *sc = dev_id;
2359 struct ath5k_hw *ah = sc->ah;
2360 enum ath5k_int status;
2361 unsigned int counter = 1000;
2362
2363 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2364 !ath5k_hw_is_intr_pending(ah)))
2365 return IRQ_NONE;
2366
2367 do {
2368 /*
2369 * Figure out the reason(s) for the interrupt. Note
2370 * that get_isr returns a pseudo-ISR that may include
2371 * bits we haven't explicitly enabled so we mask the
2372 * value to insure we only process bits we requested.
2373 */
2374 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2375 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2376 status, sc->imask);
2377 status &= sc->imask; /* discard unasked for bits */
2378 if (unlikely(status & AR5K_INT_FATAL)) {
2379 /*
2380 * Fatal errors are unrecoverable.
2381 * Typically these are caused by DMA errors.
2382 */
2383 tasklet_schedule(&sc->restq);
2384 } else if (unlikely(status & AR5K_INT_RXORN)) {
2385 tasklet_schedule(&sc->restq);
2386 } else {
2387 if (status & AR5K_INT_SWBA) {
2388 /*
2389 * Software beacon alert--time to send a beacon.
2390 * Handle beacon transmission directly; deferring
2391 * this is too slow to meet timing constraints
2392 * under load.
036cd1ec
BR		 2393 *
2394 * In IBSS mode we use this interrupt just to
2395 * keep track of the next TBTT (target beacon
6ba81c2c
BR		 2396 * transmission time) in order to detect wether
2397 * automatic TSF updates happened.
fa1c114f 2398 */
036cd1ec
BR		 2399 if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2400 /* XXX: only if VEOL suppported */
2401 u64 tsf = ath5k_hw_get_tsf64(ah);
2402 sc->nexttbtt += sc->bintval;
2403 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2404 "SWBA nexttbtt: %x hw_tu: %x "
2405 "TSF: %llx\n",
2406 sc->nexttbtt,
2407 TSF_TO_TU(tsf),
2408 (unsigned long long) tsf);
036cd1ec 2409 } else {
00482973 2410 spin_lock(&sc->block);
036cd1ec 2411 ath5k_beacon_send(sc);
00482973 2412 spin_unlock(&sc->block);
036cd1ec 2413 }
fa1c114f
JS		 2414 }
2415 if (status & AR5K_INT_RXEOL) {
2416 /*
2417 * NB: the hardware should re-read the link when
2418 * RXE bit is written, but it doesn't work at
2419 * least on older hardware revs.
2420 */
2421 sc->rxlink = NULL;
2422 }
2423 if (status & AR5K_INT_TXURN) {
2424 /* bump tx trigger level */
2425 ath5k_hw_update_tx_triglevel(ah, true);
2426 }
2427 if (status & AR5K_INT_RX)
2428 tasklet_schedule(&sc->rxtq);
2429 if (status & AR5K_INT_TX)
2430 tasklet_schedule(&sc->txtq);
2431 if (status & AR5K_INT_BMISS) {
2432 }
2433 if (status & AR5K_INT_MIB) {
194828a2
NK		 2434 /*
2435 * These stats are also used for ANI i think
2436 * so how about updating them more often ?
2437 */
2438 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2439 }
2440 }
2441 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2442
2443 if (unlikely(!counter))
2444 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2445
2446 return IRQ_HANDLED;
2447}
2448
2449static void
2450ath5k_tasklet_reset(unsigned long data)
2451{
2452 struct ath5k_softc *sc = (void *)data;
2453
2454 ath5k_reset(sc->hw);
2455}
2456
2457/*
2458 * Periodically recalibrate the PHY to account
2459 * for temperature/environment changes.
2460 */
2461static void
2462ath5k_calibrate(unsigned long data)
2463{
2464 struct ath5k_softc *sc = (void *)data;
2465 struct ath5k_hw *ah = sc->ah;
2466
2467 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2468 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2469 sc->curchan->hw_value);
fa1c114f
JS		 2470
2471 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2472 /*
2473 * Rfgain is out of bounds, reset the chip
2474 * to load new gain values.
2475 */
2476 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2477 ath5k_reset(sc->hw);
2478 }
2479 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2480 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2481 ieee80211_frequency_to_channel(
2482 sc->curchan->center_freq));
fa1c114f
JS		 2483
2484 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2485 msecs_to_jiffies(ath5k_calinterval * 1000)));
2486}
2487
2488
2489
2490/***************\
2491* LED functions *
2492\***************/
2493
2494static void
3a078876 2495ath5k_led_enable(struct ath5k_softc *sc)
fa1c114f 2496{
3a078876
BC		 2497 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2498 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2499 ath5k_led_off(sc);
fa1c114f
JS		 2500 }
2501}
2502
fa1c114f 2503static void
3a078876 2504ath5k_led_on(struct ath5k_softc *sc)
fa1c114f 2505{
3a078876
BC		 2506 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2507 return;
fa1c114f 2508 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
fa1c114f
JS		 2509}
2510
2511static void
3a078876 2512ath5k_led_off(struct ath5k_softc *sc)
fa1c114f 2513{
3a078876 2514 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
fa1c114f 2515 return;
3a078876
BC		 2516 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2517}
2518
2519static void
2520ath5k_led_brightness_set(struct led_classdev *led_dev,
2521 enum led_brightness brightness)
2522{
2523 struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2524 led_dev);
2525
2526 if (brightness == LED_OFF)
2527 ath5k_led_off(led->sc);
2528 else
2529 ath5k_led_on(led->sc);
2530}
2531
2532static int
2533ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2534 const char *name, char *trigger)
2535{
2536 int err;
2537
2538 led->sc = sc;
2539 strncpy(led->name, name, sizeof(led->name));
2540 led->led_dev.name = led->name;
2541 led->led_dev.default_trigger = trigger;
2542 led->led_dev.brightness_set = ath5k_led_brightness_set;
2543
2544 err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
2545 if (err)
2546 {
2547 ATH5K_WARN(sc, "could not register LED %s\n", name);
2548 led->sc = NULL;
fa1c114f 2549 }
3a078876 2550 return err;
fa1c114f
JS		 2551}
2552
3a078876
BC		 2553static void
2554ath5k_unregister_led(struct ath5k_led *led)
2555{
2556 if (!led->sc)
2557 return;
2558 led_classdev_unregister(&led->led_dev);
2559 ath5k_led_off(led->sc);
2560 led->sc = NULL;
2561}
2562
2563static void
2564ath5k_unregister_leds(struct ath5k_softc *sc)
2565{
2566 ath5k_unregister_led(&sc->rx_led);
2567 ath5k_unregister_led(&sc->tx_led);
2568}
2569
2570
2571static int
2572ath5k_init_leds(struct ath5k_softc *sc)
2573{
2574 int ret = 0;
2575 struct ieee80211_hw *hw = sc->hw;
2576 struct pci_dev *pdev = sc->pdev;
2577 char name[ATH5K_LED_MAX_NAME_LEN + 1];
2578
3a078876
BC		 2579 /*
2580 * Auto-enable soft led processing for IBM cards and for
2581 * 5211 minipci cards.
2582 */
2583 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2584 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2585 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2586 sc->led_pin = 0;
734b5aa9 2587 sc->led_on = 0; /* active low */
3a078876
BC		 2588 }
2589 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2590 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2591 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2592 sc->led_pin = 1;
734b5aa9 2593 sc->led_on = 1; /* active high */
3a078876
BC		 2594 }
2595 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2596 goto out;
2597
2598 ath5k_led_enable(sc);
2599
2600 snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2601 ret = ath5k_register_led(sc, &sc->rx_led, name,
2602 ieee80211_get_rx_led_name(hw));
2603 if (ret)
2604 goto out;
2605
2606 snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2607 ret = ath5k_register_led(sc, &sc->tx_led, name,
2608 ieee80211_get_tx_led_name(hw));
2609out:
2610 return ret;
2611}
fa1c114f
JS		 2612
2613
2614/********************\
2615* Mac80211 functions *
2616\********************/
2617
2618static int
e039fa4a 2619ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f
JS		 2620{
2621 struct ath5k_softc *sc = hw->priv;
2622 struct ath5k_buf *bf;
2623 unsigned long flags;
2624 int hdrlen;
2625 int pad;
2626
2627 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2628
2629 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2630 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2631
2632 /*
2633 * the hardware expects the header padded to 4 byte boundaries
2634 * if this is not the case we add the padding after the header
2635 */
2636 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2637 if (hdrlen & 3) {
2638 pad = hdrlen % 4;
2639 if (skb_headroom(skb) < pad) {
2640 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2641 " headroom to pad %d\n", hdrlen, pad);
2642 return -1;
2643 }
2644 skb_push(skb, pad);
2645 memmove(skb->data, skb->data+pad, hdrlen);
2646 }
2647
fa1c114f
JS		 2648 spin_lock_irqsave(&sc->txbuflock, flags);
2649 if (list_empty(&sc->txbuf)) {
2650 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2651 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2652 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
fa1c114f
JS		 2653 return -1;
2654 }
2655 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2656 list_del(&bf->list);
2657 sc->txbuf_len--;
2658 if (list_empty(&sc->txbuf))
2659 ieee80211_stop_queues(hw);
2660 spin_unlock_irqrestore(&sc->txbuflock, flags);
2661
2662 bf->skb = skb;
2663
e039fa4a 2664 if (ath5k_txbuf_setup(sc, bf)) {
fa1c114f
JS		 2665 bf->skb = NULL;
2666 spin_lock_irqsave(&sc->txbuflock, flags);
2667 list_add_tail(&bf->list, &sc->txbuf);
2668 sc->txbuf_len++;
2669 spin_unlock_irqrestore(&sc->txbuflock, flags);
2670 dev_kfree_skb_any(skb);
2671 return 0;
2672 }
2673
2674 return 0;
2675}
2676
2677static int
2678ath5k_reset(struct ieee80211_hw *hw)
2679{
2680 struct ath5k_softc *sc = hw->priv;
2681 struct ath5k_hw *ah = sc->ah;
2682 int ret;
2683
2684 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f
JS		 2685
2686 ath5k_hw_set_intr(ah, 0);
2687 ath5k_txq_cleanup(sc);
2688 ath5k_rx_stop(sc);
2689
2690 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2691 if (unlikely(ret)) {
2692 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2693 goto err;
2694 }
2695 ath5k_hw_set_txpower_limit(sc->ah, 0);
2696
2697 ret = ath5k_rx_start(sc);
2698 if (unlikely(ret)) {
2699 ATH5K_ERR(sc, "can't start recv logic\n");
2700 goto err;
2701 }
2702 /*
2703 * We may be doing a reset in response to an ioctl
2704 * that changes the channel so update any state that
2705 * might change as a result.
2706 *
2707 * XXX needed?
2708 */
2709/* ath5k_chan_change(sc, c); */
2710 ath5k_beacon_config(sc);
2711 /* intrs are started by ath5k_beacon_config */
2712
2713 ieee80211_wake_queues(hw);
2714
2715 return 0;
2716err:
2717 return ret;
2718}
2719
2720static int ath5k_start(struct ieee80211_hw *hw)
2721{
2722 return ath5k_init(hw->priv);
2723}
2724
2725static void ath5k_stop(struct ieee80211_hw *hw)
2726{
2727 ath5k_stop_hw(hw->priv);
2728}
2729
2730static int ath5k_add_interface(struct ieee80211_hw *hw,
2731 struct ieee80211_if_init_conf *conf)
2732{
2733 struct ath5k_softc *sc = hw->priv;
2734 int ret;
2735
2736 mutex_lock(&sc->lock);
32bfd35d 2737 if (sc->vif) {
fa1c114f
JS		 2738 ret = 0;
2739 goto end;
2740 }
2741
32bfd35d 2742 sc->vif = conf->vif;
fa1c114f
JS		 2743
2744 switch (conf->type) {
2745 case IEEE80211_IF_TYPE_STA:
2746 case IEEE80211_IF_TYPE_IBSS:
2747 case IEEE80211_IF_TYPE_MNTR:
2748 sc->opmode = conf->type;
2749 break;
2750 default:
2751 ret = -EOPNOTSUPP;
2752 goto end;
2753 }
2754 ret = 0;
2755end:
2756 mutex_unlock(&sc->lock);
2757 return ret;
2758}
2759
2760static void
2761ath5k_remove_interface(struct ieee80211_hw *hw,
2762 struct ieee80211_if_init_conf *conf)
2763{
2764 struct ath5k_softc *sc = hw->priv;
2765
2766 mutex_lock(&sc->lock);
32bfd35d 2767 if (sc->vif != conf->vif)
fa1c114f
JS		 2768 goto end;
2769
32bfd35d 2770 sc->vif = NULL;
fa1c114f
JS		 2771end:
2772 mutex_unlock(&sc->lock);
2773}
2774
d8ee398d
LR		 2775/*
2776 * TODO: Phy disable/diversity etc
2777 */
fa1c114f
JS		 2778static int
2779ath5k_config(struct ieee80211_hw *hw,
2780 struct ieee80211_conf *conf)
2781{
2782 struct ath5k_softc *sc = hw->priv;
2783
e535c1ac 2784 sc->bintval = conf->beacon_int;
d8ee398d 2785 sc->power_level = conf->power_level;
fa1c114f 2786
d8ee398d 2787 return ath5k_chan_set(sc, conf->channel);
fa1c114f
JS		 2788}
2789
2790static int
32bfd35d 2791ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
fa1c114f
JS		 2792 struct ieee80211_if_conf *conf)
2793{
2794 struct ath5k_softc *sc = hw->priv;
2795 struct ath5k_hw *ah = sc->ah;
2796 int ret;
2797
2798 /* Set to a reasonable value. Note that this will
2799 * be set to mac80211's value at ath5k_config(). */
e535c1ac 2800 sc->bintval = 1000;
fa1c114f 2801 mutex_lock(&sc->lock);
32bfd35d 2802 if (sc->vif != vif) {
fa1c114f
JS		 2803 ret = -EIO;
2804 goto unlock;
2805 }
2806 if (conf->bssid) {
2807 /* Cache for later use during resets */
2808 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2809 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2810 * a clean way of letting us retrieve this yet. */
2811 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
274c7c36 2812 mmiowb();
fa1c114f 2813 }
9d139c81
JB		 2814
2815 if (conf->changed & IEEE80211_IFCC_BEACON &&
2816 vif->type == IEEE80211_IF_TYPE_IBSS) {
2817 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2818 if (!beacon) {
2819 ret = -ENOMEM;
2820 goto unlock;
2821 }
2822 /* call old handler for now */
2823 ath5k_beacon_update(hw, beacon);
2824 }
2825
fa1c114f
JS		 2826 mutex_unlock(&sc->lock);
2827
2828 return ath5k_reset(hw);
2829unlock:
2830 mutex_unlock(&sc->lock);
2831 return ret;
2832}
2833
2834#define SUPPORTED_FIF_FLAGS \
2835 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2836 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2837 FIF_BCN_PRBRESP_PROMISC
2838/*
2839 * o always accept unicast, broadcast, and multicast traffic
2840 * o multicast traffic for all BSSIDs will be enabled if mac80211
2841 * says it should be
2842 * o maintain current state of phy ofdm or phy cck error reception.
2843 * If the hardware detects any of these type of errors then
2844 * ath5k_hw_get_rx_filter() will pass to us the respective
2845 * hardware filters to be able to receive these type of frames.
2846 * o probe request frames are accepted only when operating in
2847 * hostap, adhoc, or monitor modes
2848 * o enable promiscuous mode according to the interface state
2849 * o accept beacons:
2850 * - when operating in adhoc mode so the 802.11 layer creates
2851 * node table entries for peers,
2852 * - when operating in station mode for collecting rssi data when
2853 * the station is otherwise quiet, or
2854 * - when scanning
2855 */
2856static void ath5k_configure_filter(struct ieee80211_hw *hw,
2857 unsigned int changed_flags,
2858 unsigned int *new_flags,
2859 int mc_count, struct dev_mc_list *mclist)
2860{
2861 struct ath5k_softc *sc = hw->priv;
2862 struct ath5k_hw *ah = sc->ah;
2863 u32 mfilt[2], val, rfilt;
2864 u8 pos;
2865 int i;
2866
2867 mfilt[0] = 0;
2868 mfilt[1] = 0;
2869
2870 /* Only deal with supported flags */
2871 changed_flags &= SUPPORTED_FIF_FLAGS;
2872 *new_flags &= SUPPORTED_FIF_FLAGS;
2873
2874 /* If HW detects any phy or radar errors, leave those filters on.
2875 * Also, always enable Unicast, Broadcasts and Multicast
2876 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2877 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2878 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2879 AR5K_RX_FILTER_MCAST);
2880
2881 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2882 if (*new_flags & FIF_PROMISC_IN_BSS) {
2883 rfilt |= AR5K_RX_FILTER_PROM;
2884 __set_bit(ATH_STAT_PROMISC, sc->status);
2885 }
2886 else
2887 __clear_bit(ATH_STAT_PROMISC, sc->status);
2888 }
2889
2890 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2891 if (*new_flags & FIF_ALLMULTI) {
2892 mfilt[0] = ~0;
2893 mfilt[1] = ~0;
2894 } else {
2895 for (i = 0; i < mc_count; i++) {
2896 if (!mclist)
2897 break;
2898 /* calculate XOR of eight 6-bit values */
533dd1b0 2899 val = get_unaligned_le32(mclist->dmi_addr + 0);
fa1c114f 2900 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
533dd1b0 2901 val = get_unaligned_le32(mclist->dmi_addr + 3);
fa1c114f
JS		 2902 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2903 pos &= 0x3f;
2904 mfilt[pos / 32] |= (1 << (pos % 32));
2905 /* XXX: we might be able to just do this instead,
2906 * but not sure, needs testing, if we do use this we'd
2907 * neet to inform below to not reset the mcast */
2908 /* ath5k_hw_set_mcast_filterindex(ah,
2909 * mclist->dmi_addr[5]); */
2910 mclist = mclist->next;
2911 }
2912 }
2913
2914 /* This is the best we can do */
2915 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2916 rfilt |= AR5K_RX_FILTER_PHYERR;
2917
2918 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2919 * and probes for any BSSID, this needs testing */
2920 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2921 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2922
2923 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2924 * set we should only pass on control frames for this
2925 * station. This needs testing. I believe right now this
2926 * enables *all* control frames, which is OK.. but
2927 * but we should see if we can improve on granularity */
2928 if (*new_flags & FIF_CONTROL)
2929 rfilt |= AR5K_RX_FILTER_CONTROL;
2930
2931 /* Additional settings per mode -- this is per ath5k */
2932
2933 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2934
2935 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2936 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2937 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2938 if (sc->opmode != IEEE80211_IF_TYPE_STA)
2939 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2940 if (sc->opmode != IEEE80211_IF_TYPE_AP &&
2941 test_bit(ATH_STAT_PROMISC, sc->status))
2942 rfilt |= AR5K_RX_FILTER_PROM;
2943 if (sc->opmode == IEEE80211_IF_TYPE_STA ||
2944 sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2945 rfilt |= AR5K_RX_FILTER_BEACON;
2946 }
2947
2948 /* Set filters */
2949 ath5k_hw_set_rx_filter(ah,rfilt);
2950
2951 /* Set multicast bits */
2952 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2953 /* Set the cached hw filter flags, this will alter actually
2954 * be set in HW */
2955 sc->filter_flags = rfilt;
2956}
2957
2958static int
2959ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2960 const u8 *local_addr, const u8 *addr,
2961 struct ieee80211_key_conf *key)
2962{
2963 struct ath5k_softc *sc = hw->priv;
2964 int ret = 0;
2965
2966 switch(key->alg) {
2967 case ALG_WEP:
6844e63a
LR		 2968 /* XXX: fix hardware encryption, its not working. For now
2969 * allow software encryption */
2970 /* break; */
fa1c114f
JS		 2971 case ALG_TKIP:
2972 case ALG_CCMP:
2973 return -EOPNOTSUPP;
2974 default:
2975 WARN_ON(1);
2976 return -EINVAL;
2977 }
2978
2979 mutex_lock(&sc->lock);
2980
2981 switch (cmd) {
2982 case SET_KEY:
2983 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2984 if (ret) {
2985 ATH5K_ERR(sc, "can't set the key\n");
2986 goto unlock;
2987 }
2988 __set_bit(key->keyidx, sc->keymap);
2989 key->hw_key_idx = key->keyidx;
2990 break;
2991 case DISABLE_KEY:
2992 ath5k_hw_reset_key(sc->ah, key->keyidx);
2993 __clear_bit(key->keyidx, sc->keymap);
2994 break;
2995 default:
2996 ret = -EINVAL;
2997 goto unlock;
2998 }
2999
3000unlock:
274c7c36 3001 mmiowb();
fa1c114f
JS		 3002 mutex_unlock(&sc->lock);
3003 return ret;
3004}
3005
3006static int
3007ath5k_get_stats(struct ieee80211_hw *hw,
3008 struct ieee80211_low_level_stats *stats)
3009{
3010 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 3011 struct ath5k_hw *ah = sc->ah;
3012
3013 /* Force update */
3014 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 3015
3016 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3017
3018 return 0;
3019}
3020
3021static int
3022ath5k_get_tx_stats(struct ieee80211_hw *hw,
3023 struct ieee80211_tx_queue_stats *stats)
3024{
3025 struct ath5k_softc *sc = hw->priv;
3026
3027 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3028
3029 return 0;
3030}
3031
3032static u64
3033ath5k_get_tsf(struct ieee80211_hw *hw)
3034{
3035 struct ath5k_softc *sc = hw->priv;
3036
3037 return ath5k_hw_get_tsf64(sc->ah);
3038}
3039
3040static void
3041ath5k_reset_tsf(struct ieee80211_hw *hw)
3042{
3043 struct ath5k_softc *sc = hw->priv;
3044
9804b98d
BR		 3045 /*
3046 * in IBSS mode we need to update the beacon timers too.
3047 * this will also reset the TSF if we call it with 0
3048 */
3049 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
3050 ath5k_beacon_update_timers(sc, 0);
3051 else
3052 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3053}
3054
3055static int
e039fa4a 3056ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f
JS		 3057{
3058 struct ath5k_softc *sc = hw->priv;
00482973 3059 unsigned long flags;
fa1c114f
JS		 3060 int ret;
3061
3062 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3063
fa1c114f
JS		 3064 if (sc->opmode != IEEE80211_IF_TYPE_IBSS) {
3065 ret = -EIO;
3066 goto end;
3067 }
3068
00482973 3069 spin_lock_irqsave(&sc->block, flags);
fa1c114f
JS		 3070 ath5k_txbuf_free(sc, sc->bbuf);
3071 sc->bbuf->skb = skb;
e039fa4a 3072 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3073 if (ret)
3074 sc->bbuf->skb = NULL;
00482973
JS		 3075 spin_unlock_irqrestore(&sc->block, flags);
3076 if (!ret) {
fa1c114f 3077 ath5k_beacon_config(sc);
274c7c36
JS		 3078 mmiowb();
3079 }
fa1c114f
JS		 3080
3081end:
fa1c114f
JS		 3082 return ret;
3083}
3084
Linux kernel - Deliverables
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