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mac80211: use rate index in TX control
[deliverable/linux.git] / drivers / net / wireless / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
43#include <linux/version.h>
44#include <linux/module.h>
45#include <linux/delay.h>
46#include <linux/if.h>
47#include <linux/netdevice.h>
48#include <linux/cache.h>
49#include <linux/pci.h>
50#include <linux/ethtool.h>
51#include <linux/uaccess.h>
52
53#include <net/ieee80211_radiotap.h>
54
55#include <asm/unaligned.h>
56
57#include "base.h"
58#include "reg.h"
59#include "debug.h"
60
fa1c114f
JS		 61enum {
62 ATH_LED_TX,
63 ATH_LED_RX,
64};
65
66static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
67
68
69/******************\
70* Internal defines *
71\******************/
72
73/* Module info */
74MODULE_AUTHOR("Jiri Slaby");
75MODULE_AUTHOR("Nick Kossifidis");
76MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
77MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
78MODULE_LICENSE("Dual BSD/GPL");
400ec45a 79MODULE_VERSION("0.5.0 (EXPERIMENTAL)");
fa1c114f
JS		 80
81
82/* Known PCI ids */
83static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
84 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
85 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
86 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
87 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
88 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
89 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
90 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
91 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
92 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
95 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
99 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
100 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/
101 { PCI_VDEVICE(ATHEROS, 0x0023), .driver_data = AR5K_AR5212 }, /* 5416 */
102 { PCI_VDEVICE(ATHEROS, 0x0024), .driver_data = AR5K_AR5212 }, /* 5418 */
103 { 0 }
104};
105MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
106
107/* Known SREVs */
108static struct ath5k_srev_name srev_names[] = {
109 { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 },
110 { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 },
111 { "5311A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },
112 { "5311B", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },
113 { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 },
114 { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 },
115 { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 },
116 { "5213A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213A },
bb0c9dc2
NK		 117 { "2413", AR5K_VERSION_VER, AR5K_SREV_VER_AR2413 },
118 { "2414", AR5K_VERSION_VER, AR5K_SREV_VER_AR2414 },
fa1c114f
JS		 119 { "2424", AR5K_VERSION_VER, AR5K_SREV_VER_AR2424 },
120 { "5424", AR5K_VERSION_VER, AR5K_SREV_VER_AR5424 },
121 { "5413", AR5K_VERSION_VER, AR5K_SREV_VER_AR5413 },
122 { "5414", AR5K_VERSION_VER, AR5K_SREV_VER_AR5414 },
123 { "5416", AR5K_VERSION_VER, AR5K_SREV_VER_AR5416 },
124 { "5418", AR5K_VERSION_VER, AR5K_SREV_VER_AR5418 },
136bfc79 125 { "2425", AR5K_VERSION_VER, AR5K_SREV_VER_AR2425 },
fa1c114f
JS		 126 { "xxxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN },
127 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
128 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
129 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
130 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
131 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
132 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
133 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
bb0c9dc2 134 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC0 },
fa1c114f
JS		 135 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC1 },
136 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC2 },
137 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
138 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
139};
140
141/*
142 * Prototypes - PCI stack related functions
143 */
144static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
145 const struct pci_device_id *id);
146static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
147#ifdef CONFIG_PM
148static int ath5k_pci_suspend(struct pci_dev *pdev,
149 pm_message_t state);
150static int ath5k_pci_resume(struct pci_dev *pdev);
151#else
152#define ath5k_pci_suspend NULL
153#define ath5k_pci_resume NULL
154#endif /* CONFIG_PM */
155
04a9e451 156static struct pci_driver ath5k_pci_driver = {
fa1c114f
JS		 157 .name = "ath5k_pci",
158 .id_table = ath5k_pci_id_table,
159 .probe = ath5k_pci_probe,
160 .remove = __devexit_p(ath5k_pci_remove),
161 .suspend = ath5k_pci_suspend,
162 .resume = ath5k_pci_resume,
163};
164
165
166
167/*
168 * Prototypes - MAC 802.11 stack related functions
169 */
170static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
171 struct ieee80211_tx_control *ctl);
172static int ath5k_reset(struct ieee80211_hw *hw);
173static int ath5k_start(struct ieee80211_hw *hw);
174static void ath5k_stop(struct ieee80211_hw *hw);
175static int ath5k_add_interface(struct ieee80211_hw *hw,
176 struct ieee80211_if_init_conf *conf);
177static void ath5k_remove_interface(struct ieee80211_hw *hw,
178 struct ieee80211_if_init_conf *conf);
179static int ath5k_config(struct ieee80211_hw *hw,
180 struct ieee80211_conf *conf);
32bfd35d
JB		 181static int ath5k_config_interface(struct ieee80211_hw *hw,
182 struct ieee80211_vif *vif,
fa1c114f
JS		 183 struct ieee80211_if_conf *conf);
184static void ath5k_configure_filter(struct ieee80211_hw *hw,
185 unsigned int changed_flags,
186 unsigned int *new_flags,
187 int mc_count, struct dev_mc_list *mclist);
188static int ath5k_set_key(struct ieee80211_hw *hw,
189 enum set_key_cmd cmd,
190 const u8 *local_addr, const u8 *addr,
191 struct ieee80211_key_conf *key);
192static int ath5k_get_stats(struct ieee80211_hw *hw,
193 struct ieee80211_low_level_stats *stats);
194static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
195 struct ieee80211_tx_queue_stats *stats);
196static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
197static void ath5k_reset_tsf(struct ieee80211_hw *hw);
198static int ath5k_beacon_update(struct ieee80211_hw *hw,
199 struct sk_buff *skb,
200 struct ieee80211_tx_control *ctl);
201
202static struct ieee80211_ops ath5k_hw_ops = {
203 .tx = ath5k_tx,
204 .start = ath5k_start,
205 .stop = ath5k_stop,
206 .add_interface = ath5k_add_interface,
207 .remove_interface = ath5k_remove_interface,
208 .config = ath5k_config,
209 .config_interface = ath5k_config_interface,
210 .configure_filter = ath5k_configure_filter,
211 .set_key = ath5k_set_key,
212 .get_stats = ath5k_get_stats,
213 .conf_tx = NULL,
214 .get_tx_stats = ath5k_get_tx_stats,
215 .get_tsf = ath5k_get_tsf,
216 .reset_tsf = ath5k_reset_tsf,
217 .beacon_update = ath5k_beacon_update,
218};
219
220/*
221 * Prototypes - Internal functions
222 */
223/* Attach detach */
224static int ath5k_attach(struct pci_dev *pdev,
225 struct ieee80211_hw *hw);
226static void ath5k_detach(struct pci_dev *pdev,
227 struct ieee80211_hw *hw);
228/* Channel/mode setup */
229static inline short ath5k_ieee2mhz(short chan);
230static unsigned int ath5k_copy_rates(struct ieee80211_rate *rates,
231 const struct ath5k_rate_table *rt,
232 unsigned int max);
233static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
234 struct ieee80211_channel *channels,
235 unsigned int mode,
236 unsigned int max);
237static int ath5k_getchannels(struct ieee80211_hw *hw);
238static int ath5k_chan_set(struct ath5k_softc *sc,
239 struct ieee80211_channel *chan);
240static void ath5k_setcurmode(struct ath5k_softc *sc,
241 unsigned int mode);
242static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d
LR		 243static void ath5k_set_total_hw_rates(struct ath5k_softc *sc);
244
fa1c114f
JS		 245/* Descriptor setup */
246static int ath5k_desc_alloc(struct ath5k_softc *sc,
247 struct pci_dev *pdev);
248static void ath5k_desc_free(struct ath5k_softc *sc,
249 struct pci_dev *pdev);
250/* Buffers setup */
251static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
252 struct ath5k_buf *bf);
253static int ath5k_txbuf_setup(struct ath5k_softc *sc,
254 struct ath5k_buf *bf,
255 struct ieee80211_tx_control *ctl);
256
257static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
258 struct ath5k_buf *bf)
259{
260 BUG_ON(!bf);
261 if (!bf->skb)
262 return;
263 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
264 PCI_DMA_TODEVICE);
265 dev_kfree_skb(bf->skb);
266 bf->skb = NULL;
267}
268
269/* Queues setup */
270static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
271 int qtype, int subtype);
272static int ath5k_beaconq_setup(struct ath5k_hw *ah);
273static int ath5k_beaconq_config(struct ath5k_softc *sc);
274static void ath5k_txq_drainq(struct ath5k_softc *sc,
275 struct ath5k_txq *txq);
276static void ath5k_txq_cleanup(struct ath5k_softc *sc);
277static void ath5k_txq_release(struct ath5k_softc *sc);
278/* Rx handling */
279static int ath5k_rx_start(struct ath5k_softc *sc);
280static void ath5k_rx_stop(struct ath5k_softc *sc);
281static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
282 struct ath5k_desc *ds,
b47f407b
BR		 283 struct sk_buff *skb,
284 struct ath5k_rx_status *rs);
fa1c114f
JS		 285static void ath5k_tasklet_rx(unsigned long data);
286/* Tx handling */
287static void ath5k_tx_processq(struct ath5k_softc *sc,
288 struct ath5k_txq *txq);
289static void ath5k_tasklet_tx(unsigned long data);
290/* Beacon handling */
291static int ath5k_beacon_setup(struct ath5k_softc *sc,
292 struct ath5k_buf *bf,
293 struct ieee80211_tx_control *ctl);
294static void ath5k_beacon_send(struct ath5k_softc *sc);
295static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 296static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f
JS		 297
298static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
299{
300 u64 tsf = ath5k_hw_get_tsf64(ah);
301
302 if ((tsf & 0x7fff) < rstamp)
303 tsf -= 0x8000;
304
305 return (tsf & ~0x7fff) | rstamp;
306}
307
308/* Interrupt handling */
309static int ath5k_init(struct ath5k_softc *sc);
310static int ath5k_stop_locked(struct ath5k_softc *sc);
311static int ath5k_stop_hw(struct ath5k_softc *sc);
312static irqreturn_t ath5k_intr(int irq, void *dev_id);
313static void ath5k_tasklet_reset(unsigned long data);
314
315static void ath5k_calibrate(unsigned long data);
316/* LED functions */
317static void ath5k_led_off(unsigned long data);
318static void ath5k_led_blink(struct ath5k_softc *sc,
319 unsigned int on,
320 unsigned int off);
321static void ath5k_led_event(struct ath5k_softc *sc,
322 int event);
323
324
325/*
326 * Module init/exit functions
327 */
328static int __init
329init_ath5k_pci(void)
330{
331 int ret;
332
333 ath5k_debug_init();
334
04a9e451 335 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 336 if (ret) {
337 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
338 return ret;
339 }
340
341 return 0;
342}
343
344static void __exit
345exit_ath5k_pci(void)
346{
04a9e451 347 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 348
349 ath5k_debug_finish();
350}
351
352module_init(init_ath5k_pci);
353module_exit(exit_ath5k_pci);
354
355
356/********************\
357* PCI Initialization *
358\********************/
359
360static const char *
361ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
362{
363 const char *name = "xxxxx";
364 unsigned int i;
365
366 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
367 if (srev_names[i].sr_type != type)
368 continue;
369 if ((val & 0xff) < srev_names[i + 1].sr_val) {
370 name = srev_names[i].sr_name;
371 break;
372 }
373 }
374
375 return name;
376}
377
378static int __devinit
379ath5k_pci_probe(struct pci_dev *pdev,
380 const struct pci_device_id *id)
381{
382 void __iomem *mem;
383 struct ath5k_softc *sc;
384 struct ieee80211_hw *hw;
385 int ret;
386 u8 csz;
387
388 ret = pci_enable_device(pdev);
389 if (ret) {
390 dev_err(&pdev->dev, "can't enable device\n");
391 goto err;
392 }
393
394 /* XXX 32-bit addressing only */
395 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
396 if (ret) {
397 dev_err(&pdev->dev, "32-bit DMA not available\n");
398 goto err_dis;
399 }
400
401 /*
402 * Cache line size is used to size and align various
403 * structures used to communicate with the hardware.
404 */
405 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
406 if (csz == 0) {
407 /*
408 * Linux 2.4.18 (at least) writes the cache line size
409 * register as a 16-bit wide register which is wrong.
410 * We must have this setup properly for rx buffer
411 * DMA to work so force a reasonable value here if it
412 * comes up zero.
413 */
414 csz = L1_CACHE_BYTES / sizeof(u32);
415 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
416 }
417 /*
418 * The default setting of latency timer yields poor results,
419 * set it to the value used by other systems. It may be worth
420 * tweaking this setting more.
421 */
422 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
423
424 /* Enable bus mastering */
425 pci_set_master(pdev);
426
427 /*
428 * Disable the RETRY_TIMEOUT register (0x41) to keep
429 * PCI Tx retries from interfering with C3 CPU state.
430 */
431 pci_write_config_byte(pdev, 0x41, 0);
432
433 ret = pci_request_region(pdev, 0, "ath5k");
434 if (ret) {
435 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
436 goto err_dis;
437 }
438
439 mem = pci_iomap(pdev, 0, 0);
440 if (!mem) {
441 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
442 ret = -EIO;
443 goto err_reg;
444 }
445
446 /*
447 * Allocate hw (mac80211 main struct)
448 * and hw->priv (driver private data)
449 */
450 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
451 if (hw == NULL) {
452 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
453 ret = -ENOMEM;
454 goto err_map;
455 }
456
457 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
458
459 /* Initialize driver private data */
460 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a
BR		 461 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
462 IEEE80211_HW_SIGNAL_DBM |
463 IEEE80211_HW_NOISE_DBM;
fa1c114f
JS		 464 hw->extra_tx_headroom = 2;
465 hw->channel_change_time = 5000;
fa1c114f
JS		 466 sc = hw->priv;
467 sc->hw = hw;
468 sc->pdev = pdev;
469
470 ath5k_debug_init_device(sc);
471
472 /*
473 * Mark the device as detached to avoid processing
474 * interrupts until setup is complete.
475 */
476 __set_bit(ATH_STAT_INVALID, sc->status);
477
478 sc->iobase = mem; /* So we can unmap it on detach */
479 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
480 sc->opmode = IEEE80211_IF_TYPE_STA;
481 mutex_init(&sc->lock);
482 spin_lock_init(&sc->rxbuflock);
483 spin_lock_init(&sc->txbuflock);
484
485 /* Set private data */
486 pci_set_drvdata(pdev, hw);
487
488 /* Enable msi for devices that support it */
489 pci_enable_msi(pdev);
490
491 /* Setup interrupt handler */
492 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
493 if (ret) {
494 ATH5K_ERR(sc, "request_irq failed\n");
495 goto err_free;
496 }
497
498 /* Initialize device */
499 sc->ah = ath5k_hw_attach(sc, id->driver_data);
500 if (IS_ERR(sc->ah)) {
501 ret = PTR_ERR(sc->ah);
502 goto err_irq;
503 }
504
505 /* Finish private driver data initialization */
506 ret = ath5k_attach(pdev, hw);
507 if (ret)
508 goto err_ah;
509
510 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
511 ath5k_chip_name(AR5K_VERSION_VER,sc->ah->ah_mac_srev),
512 sc->ah->ah_mac_srev,
513 sc->ah->ah_phy_revision);
514
400ec45a 515 if (!sc->ah->ah_single_chip) {
fa1c114f 516 /* Single chip radio (!RF5111) */
400ec45a
LR		 517 if (sc->ah->ah_radio_5ghz_revision &&
518 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 519 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 520 if (!test_bit(AR5K_MODE_11A,
521 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 522 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 523 ath5k_chip_name(AR5K_VERSION_RAD,
524 sc->ah->ah_radio_5ghz_revision),
525 sc->ah->ah_radio_5ghz_revision);
526 /* No 2GHz support (5110 and some
527 * 5Ghz only cards) -> report 5Ghz radio */
528 } else if (!test_bit(AR5K_MODE_11B,
529 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 530 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 531 ath5k_chip_name(AR5K_VERSION_RAD,
532 sc->ah->ah_radio_5ghz_revision),
533 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 534 /* Multiband radio */
535 } else {
536 ATH5K_INFO(sc, "RF%s multiband radio found"
537 " (0x%x)\n",
400ec45a
LR		 538 ath5k_chip_name(AR5K_VERSION_RAD,
539 sc->ah->ah_radio_5ghz_revision),
540 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 541 }
542 }
400ec45a
LR		 543 /* Multi chip radio (RF5111 - RF2111) ->
544 * report both 2GHz/5GHz radios */
545 else if (sc->ah->ah_radio_5ghz_revision &&
546 sc->ah->ah_radio_2ghz_revision){
fa1c114f 547 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 548 ath5k_chip_name(AR5K_VERSION_RAD,
549 sc->ah->ah_radio_5ghz_revision),
550 sc->ah->ah_radio_5ghz_revision);
fa1c114f 551 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 552 ath5k_chip_name(AR5K_VERSION_RAD,
553 sc->ah->ah_radio_2ghz_revision),
554 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 555 }
556 }
557
558
559 /* ready to process interrupts */
560 __clear_bit(ATH_STAT_INVALID, sc->status);
561
562 return 0;
563err_ah:
564 ath5k_hw_detach(sc->ah);
565err_irq:
566 free_irq(pdev->irq, sc);
567err_free:
568 pci_disable_msi(pdev);
569 ieee80211_free_hw(hw);
570err_map:
571 pci_iounmap(pdev, mem);
572err_reg:
573 pci_release_region(pdev, 0);
574err_dis:
575 pci_disable_device(pdev);
576err:
577 return ret;
578}
579
580static void __devexit
581ath5k_pci_remove(struct pci_dev *pdev)
582{
583 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
584 struct ath5k_softc *sc = hw->priv;
585
586 ath5k_debug_finish_device(sc);
587 ath5k_detach(pdev, hw);
588 ath5k_hw_detach(sc->ah);
589 free_irq(pdev->irq, sc);
590 pci_disable_msi(pdev);
591 pci_iounmap(pdev, sc->iobase);
592 pci_release_region(pdev, 0);
593 pci_disable_device(pdev);
594 ieee80211_free_hw(hw);
595}
596
597#ifdef CONFIG_PM
598static int
599ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
600{
601 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
602 struct ath5k_softc *sc = hw->priv;
603
604 if (test_bit(ATH_STAT_LEDSOFT, sc->status))
605 ath5k_hw_set_gpio(sc->ah, sc->led_pin, 1);
606
607 ath5k_stop_hw(sc);
608 pci_save_state(pdev);
609 pci_disable_device(pdev);
610 pci_set_power_state(pdev, PCI_D3hot);
611
612 return 0;
613}
614
615static int
616ath5k_pci_resume(struct pci_dev *pdev)
617{
618 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
619 struct ath5k_softc *sc = hw->priv;
247ae449
JL		 620 struct ath5k_hw *ah = sc->ah;
621 int i, err;
fa1c114f
JS		 622
623 err = pci_set_power_state(pdev, PCI_D0);
624 if (err)
625 return err;
626
627 err = pci_enable_device(pdev);
628 if (err)
629 return err;
630
631 pci_restore_state(pdev);
632 /*
633 * Suspend/Resume resets the PCI configuration space, so we have to
634 * re-disable the RETRY_TIMEOUT register (0x41) to keep
635 * PCI Tx retries from interfering with C3 CPU state
636 */
637 pci_write_config_byte(pdev, 0x41, 0);
638
639 ath5k_init(sc);
640 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
247ae449
JL		 641 ath5k_hw_set_gpio_output(ah, sc->led_pin);
642 ath5k_hw_set_gpio(ah, sc->led_pin, 0);
fa1c114f
JS		 643 }
644
247ae449
JL		 645 /*
646 * Reset the key cache since some parts do not
647 * reset the contents on initial power up or resume.
648 *
649 * FIXME: This may need to be revisited when mac80211 becomes
650 * aware of suspend/resume.
651 */
652 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
653 ath5k_hw_reset_key(ah, i);
654
fa1c114f
JS		 655 return 0;
656}
657#endif /* CONFIG_PM */
658
659
660
661/***********************\
662* Driver Initialization *
663\***********************/
664
665static int
666ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
667{
668 struct ath5k_softc *sc = hw->priv;
669 struct ath5k_hw *ah = sc->ah;
670 u8 mac[ETH_ALEN];
671 unsigned int i;
672 int ret;
673
674 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
675
676 /*
677 * Check if the MAC has multi-rate retry support.
678 * We do this by trying to setup a fake extended
679 * descriptor. MAC's that don't have support will
680 * return false w/o doing anything. MAC's that do
681 * support it will return true w/o doing anything.
682 */
b9887638
JS		 683 ret = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
684 if (ret < 0)
685 goto err;
686 if (ret > 0)
fa1c114f
JS		 687 __set_bit(ATH_STAT_MRRETRY, sc->status);
688
689 /*
690 * Reset the key cache since some parts do not
691 * reset the contents on initial power up.
692 */
c65638a7 693 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
fa1c114f
JS		 694 ath5k_hw_reset_key(ah, i);
695
696 /*
697 * Collect the channel list. The 802.11 layer
698 * is resposible for filtering this list based
699 * on settings like the phy mode and regulatory
700 * domain restrictions.
701 */
702 ret = ath5k_getchannels(hw);
703 if (ret) {
704 ATH5K_ERR(sc, "can't get channels\n");
705 goto err;
706 }
707
d8ee398d
LR		 708 /* Set *_rates so we can map hw rate index */
709 ath5k_set_total_hw_rates(sc);
710
fa1c114f 711 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 712 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
713 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 714 else
d8ee398d 715 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 716
717 /*
718 * Allocate tx+rx descriptors and populate the lists.
719 */
720 ret = ath5k_desc_alloc(sc, pdev);
721 if (ret) {
722 ATH5K_ERR(sc, "can't allocate descriptors\n");
723 goto err;
724 }
725
726 /*
727 * Allocate hardware transmit queues: one queue for
728 * beacon frames and one data queue for each QoS
729 * priority. Note that hw functions handle reseting
730 * these queues at the needed time.
731 */
732 ret = ath5k_beaconq_setup(ah);
733 if (ret < 0) {
734 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
735 goto err_desc;
736 }
737 sc->bhalq = ret;
738
739 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
740 if (IS_ERR(sc->txq)) {
741 ATH5K_ERR(sc, "can't setup xmit queue\n");
742 ret = PTR_ERR(sc->txq);
743 goto err_bhal;
744 }
745
746 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
747 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
748 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
749 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
750 setup_timer(&sc->led_tim, ath5k_led_off, (unsigned long)sc);
751
752 sc->led_on = 0; /* low true */
753 /*
754 * Auto-enable soft led processing for IBM cards and for
755 * 5211 minipci cards.
756 */
757 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
758 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
759 __set_bit(ATH_STAT_LEDSOFT, sc->status);
760 sc->led_pin = 0;
761 }
762 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
763 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
764 __set_bit(ATH_STAT_LEDSOFT, sc->status);
765 sc->led_pin = 0;
766 }
767 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
768 ath5k_hw_set_gpio_output(ah, sc->led_pin);
769 ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on);
770 }
771
772 ath5k_hw_get_lladdr(ah, mac);
773 SET_IEEE80211_PERM_ADDR(hw, mac);
774 /* All MAC address bits matter for ACKs */
775 memset(sc->bssidmask, 0xff, ETH_ALEN);
776 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
777
778 ret = ieee80211_register_hw(hw);
779 if (ret) {
780 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
781 goto err_queues;
782 }
783
784 return 0;
785err_queues:
786 ath5k_txq_release(sc);
787err_bhal:
788 ath5k_hw_release_tx_queue(ah, sc->bhalq);
789err_desc:
790 ath5k_desc_free(sc, pdev);
791err:
792 return ret;
793}
794
795static void
796ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
797{
798 struct ath5k_softc *sc = hw->priv;
799
800 /*
801 * NB: the order of these is important:
802 * o call the 802.11 layer before detaching ath5k_hw to
803 * insure callbacks into the driver to delete global
804 * key cache entries can be handled
805 * o reclaim the tx queue data structures after calling
806 * the 802.11 layer as we'll get called back to reclaim
807 * node state and potentially want to use them
808 * o to cleanup the tx queues the hal is called, so detach
809 * it last
810 * XXX: ??? detach ath5k_hw ???
811 * Other than that, it's straightforward...
812 */
813 ieee80211_unregister_hw(hw);
814 ath5k_desc_free(sc, pdev);
815 ath5k_txq_release(sc);
816 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
817
818 /*
819 * NB: can't reclaim these until after ieee80211_ifdetach
820 * returns because we'll get called back to reclaim node
821 * state and potentially want to use them.
822 */
823}
824
825
826
827
828/********************\
829* Channel/mode setup *
830\********************/
831
832/*
833 * Convert IEEE channel number to MHz frequency.
834 */
835static inline short
836ath5k_ieee2mhz(short chan)
837{
838 if (chan <= 14 || chan >= 27)
839 return ieee80211chan2mhz(chan);
840 else
841 return 2212 + chan * 20;
842}
843
844static unsigned int
845ath5k_copy_rates(struct ieee80211_rate *rates,
846 const struct ath5k_rate_table *rt,
847 unsigned int max)
848{
849 unsigned int i, count;
850
851 if (rt == NULL)
852 return 0;
853
854 for (i = 0, count = 0; i < rt->rate_count && max > 0; i++) {
d8ee398d
LR		 855 rates[count].bitrate = rt->rates[i].rate_kbps / 100;
856 rates[count].hw_value = rt->rates[i].rate_code;
857 rates[count].flags = rt->rates[i].modulation;
fa1c114f
JS		 858 count++;
859 max--;
860 }
861
862 return count;
863}
864
865static unsigned int
866ath5k_copy_channels(struct ath5k_hw *ah,
867 struct ieee80211_channel *channels,
868 unsigned int mode,
869 unsigned int max)
870{
d8ee398d 871 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 872
873 if (!test_bit(mode, ah->ah_modes))
874 return 0;
875
fa1c114f 876 switch (mode) {
d8ee398d
LR		 877 case AR5K_MODE_11A:
878 case AR5K_MODE_11A_TURBO:
fa1c114f 879 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 880 size = 220 ;
fa1c114f
JS		 881 chfreq = CHANNEL_5GHZ;
882 break;
d8ee398d
LR		 883 case AR5K_MODE_11B:
884 case AR5K_MODE_11G:
885 case AR5K_MODE_11G_TURBO:
886 size = 26;
fa1c114f
JS		 887 chfreq = CHANNEL_2GHZ;
888 break;
889 default:
890 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
891 return 0;
892 }
893
894 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 895 ch = i + 1 ;
896 freq = ath5k_ieee2mhz(ch);
fa1c114f 897
d8ee398d
LR		 898 /* Check if channel is supported by the chipset */
899 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 900 continue;
901
d8ee398d
LR		 902 /* Write channel info and increment counter */
903 channels[count].center_freq = freq;
a3f4b914
LR		 904 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
905 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 906 switch (mode) {
907 case AR5K_MODE_11A:
908 case AR5K_MODE_11G:
909 channels[count].hw_value = chfreq | CHANNEL_OFDM;
910 break;
911 case AR5K_MODE_11A_TURBO:
912 case AR5K_MODE_11G_TURBO:
913 channels[count].hw_value = chfreq |
914 CHANNEL_OFDM | CHANNEL_TURBO;
915 break;
916 case AR5K_MODE_11B:
d8ee398d
LR		 917 channels[count].hw_value = CHANNEL_B;
918 }
fa1c114f 919
fa1c114f
JS		 920 count++;
921 max--;
922 }
923
924 return count;
925}
926
d8ee398d
LR		 927static int
928ath5k_getchannels(struct ieee80211_hw *hw)
fa1c114f
JS		 929{
930 struct ath5k_softc *sc = hw->priv;
d8ee398d
LR		 931 struct ath5k_hw *ah = sc->ah;
932 struct ieee80211_supported_band *sbands = sc->sbands;
933 const struct ath5k_rate_table *hw_rates;
934 unsigned int max_r, max_c, count_r, count_c;
935 int mode2g = AR5K_MODE_11G;
fa1c114f 936
d8ee398d 937 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
fa1c114f 938
d8ee398d
LR		 939 max_r = ARRAY_SIZE(sc->rates);
940 max_c = ARRAY_SIZE(sc->channels);
941 count_r = count_c = 0;
942
943 /* 2GHz band */
400ec45a 944 if (!test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
d8ee398d 945 mode2g = AR5K_MODE_11B;
400ec45a
LR		 946 if (!test_bit(AR5K_MODE_11B,
947 sc->ah->ah_capabilities.cap_mode))
d8ee398d 948 mode2g = -1;
fa1c114f 949 }
fa1c114f 950
400ec45a
LR		 951 if (mode2g > 0) {
952 struct ieee80211_supported_band *sband =
953 &sbands[IEEE80211_BAND_2GHZ];
fa1c114f 954
d8ee398d
LR		 955 sband->bitrates = sc->rates;
956 sband->channels = sc->channels;
fa1c114f 957
d8ee398d
LR		 958 sband->band = IEEE80211_BAND_2GHZ;
959 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
960 mode2g, max_c);
fa1c114f 961
d8ee398d
LR		 962 hw_rates = ath5k_hw_get_rate_table(ah, mode2g);
963 sband->n_bitrates = ath5k_copy_rates(sband->bitrates,
400ec45a 964 hw_rates, max_r);
fa1c114f 965
d8ee398d
LR		 966 count_c = sband->n_channels;
967 count_r = sband->n_bitrates;
fa1c114f 968
d8ee398d
LR		 969 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
970
971 max_r -= count_r;
972 max_c -= count_c;
fa1c114f 973
fa1c114f
JS		 974 }
975
d8ee398d 976 /* 5GHz band */
fa1c114f 977
400ec45a
LR		 978 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
979 struct ieee80211_supported_band *sband =
980 &sbands[IEEE80211_BAND_5GHZ];
fa1c114f 981
d8ee398d
LR		 982 sband->bitrates = &sc->rates[count_r];
983 sband->channels = &sc->channels[count_c];
fa1c114f 984
d8ee398d
LR		 985 sband->band = IEEE80211_BAND_5GHZ;
986 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
987 AR5K_MODE_11A, max_c);
988
989 hw_rates = ath5k_hw_get_rate_table(ah, AR5K_MODE_11A);
990 sband->n_bitrates = ath5k_copy_rates(sband->bitrates,
400ec45a 991 hw_rates, max_r);
d8ee398d
LR		 992
993 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
994 }
995
b446197c 996 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 997
998 return 0;
fa1c114f
JS		 999}
1000
1001/*
1002 * Set/change channels. If the channel is really being changed,
1003 * it's done by reseting the chip. To accomplish this we must
1004 * first cleanup any pending DMA, then restart stuff after a la
1005 * ath5k_init.
1006 */
1007static int
1008ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1009{
1010 struct ath5k_hw *ah = sc->ah;
1011 int ret;
1012
d8ee398d
LR		 1013 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1014 sc->curchan->center_freq, chan->center_freq);
1015
1016 if (chan->center_freq != sc->curchan->center_freq ||
1017 chan->hw_value != sc->curchan->hw_value) {
1018
1019 sc->curchan = chan;
1020 sc->curband = &sc->sbands[chan->band];
fa1c114f 1021
fa1c114f
JS		 1022 /*
1023 * To switch channels clear any pending DMA operations;
1024 * wait long enough for the RX fifo to drain, reset the
1025 * hardware at the new frequency, and then re-enable
1026 * the relevant bits of the h/w.
1027 */
1028 ath5k_hw_set_intr(ah, 0); /* disable interrupts */
1029 ath5k_txq_cleanup(sc); /* clear pending tx frames */
1030 ath5k_rx_stop(sc); /* turn off frame recv */
d8ee398d 1031 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
fa1c114f 1032 if (ret) {
d8ee398d
LR		 1033 ATH5K_ERR(sc, "%s: unable to reset channel "
1034 "(%u Mhz)\n", __func__, chan->center_freq);
fa1c114f
JS		 1035 return ret;
1036 }
d8ee398d 1037
fa1c114f
JS		 1038 ath5k_hw_set_txpower_limit(sc->ah, 0);
1039
1040 /*
1041 * Re-enable rx framework.
1042 */
1043 ret = ath5k_rx_start(sc);
1044 if (ret) {
1045 ATH5K_ERR(sc, "%s: unable to restart recv logic\n",
1046 __func__);
1047 return ret;
1048 }
1049
1050 /*
1051 * Change channels and update the h/w rate map
1052 * if we're switching; e.g. 11a to 11b/g.
1053 *
1054 * XXX needed?
1055 */
1056/* ath5k_chan_change(sc, chan); */
1057
1058 ath5k_beacon_config(sc);
1059 /*
1060 * Re-enable interrupts.
1061 */
1062 ath5k_hw_set_intr(ah, sc->imask);
1063 }
1064
1065 return 0;
1066}
1067
d8ee398d
LR		 1068/*
1069 * TODO: CLEAN THIS !!!
1070 */
fa1c114f
JS		 1071static void
1072ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1073{
1074 if (unlikely(test_bit(ATH_STAT_LEDSOFT, sc->status))) {
1075 /* from Atheros NDIS driver, w/ permission */
1076 static const struct {
1077 u16 rate; /* tx/rx 802.11 rate */
1078 u16 timeOn; /* LED on time (ms) */
1079 u16 timeOff; /* LED off time (ms) */
1080 } blinkrates[] = {
1081 { 108, 40, 10 },
1082 { 96, 44, 11 },
1083 { 72, 50, 13 },
1084 { 48, 57, 14 },
1085 { 36, 67, 16 },
1086 { 24, 80, 20 },
1087 { 22, 100, 25 },
1088 { 18, 133, 34 },
1089 { 12, 160, 40 },
1090 { 10, 200, 50 },
1091 { 6, 240, 58 },
1092 { 4, 267, 66 },
1093 { 2, 400, 100 },
1094 { 0, 500, 130 }
1095 };
1096 const struct ath5k_rate_table *rt =
1097 ath5k_hw_get_rate_table(sc->ah, mode);
1098 unsigned int i, j;
1099
1100 BUG_ON(rt == NULL);
1101
1102 memset(sc->hwmap, 0, sizeof(sc->hwmap));
1103 for (i = 0; i < 32; i++) {
1104 u8 ix = rt->rate_code_to_index[i];
1105 if (ix == 0xff) {
1106 sc->hwmap[i].ledon = msecs_to_jiffies(500);
1107 sc->hwmap[i].ledoff = msecs_to_jiffies(130);
1108 continue;
1109 }
1110 sc->hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
fa1c114f
JS		 1111 /* receive frames include FCS */
1112 sc->hwmap[i].rxflags = sc->hwmap[i].txflags |
1113 IEEE80211_RADIOTAP_F_FCS;
1114 /* setup blink rate table to avoid per-packet lookup */
1115 for (j = 0; j < ARRAY_SIZE(blinkrates) - 1; j++)
1116 if (blinkrates[j].rate == /* XXX why 7f? */
1117 (rt->rates[ix].dot11_rate&0x7f))
1118 break;
1119
1120 sc->hwmap[i].ledon = msecs_to_jiffies(blinkrates[j].
1121 timeOn);
1122 sc->hwmap[i].ledoff = msecs_to_jiffies(blinkrates[j].
1123 timeOff);
1124 }
1125 }
1126
1127 sc->curmode = mode;
d8ee398d 1128
400ec45a 1129 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1130 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1131 } else {
1132 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1133 }
fa1c114f
JS		 1134}
1135
1136static void
1137ath5k_mode_setup(struct ath5k_softc *sc)
1138{
1139 struct ath5k_hw *ah = sc->ah;
1140 u32 rfilt;
1141
1142 /* configure rx filter */
1143 rfilt = sc->filter_flags;
1144 ath5k_hw_set_rx_filter(ah, rfilt);
1145
1146 if (ath5k_hw_hasbssidmask(ah))
1147 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1148
1149 /* configure operational mode */
1150 ath5k_hw_set_opmode(ah);
1151
1152 ath5k_hw_set_mcast_filter(ah, 0, 0);
1153 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1154}
1155
d8ee398d
LR		 1156/*
1157 * Match the hw provided rate index (through descriptors)
1158 * to an index for sc->curband->bitrates, so it can be used
1159 * by the stack.
1160 *
1161 * This one is a little bit tricky but i think i'm right
1162 * about this...
1163 *
1164 * We have 4 rate tables in the following order:
1165 * XR (4 rates)
1166 * 802.11a (8 rates)
1167 * 802.11b (4 rates)
1168 * 802.11g (12 rates)
1169 * that make the hw rate table.
1170 *
1171 * Lets take a 5211 for example that supports a and b modes only.
1172 * First comes the 802.11a table and then 802.11b (total 12 rates).
1173 * When hw returns eg. 11 it points to the last 802.11b rate (11Mbit),
1174 * if it returns 2 it points to the second 802.11a rate etc.
1175 *
1176 * Same goes for 5212 who has xr/a/b/g support (total 28 rates).
1177 * First comes the XR table, then 802.11a, 802.11b and 802.11g.
1178 * When hw returns eg. 27 it points to the last 802.11g rate (54Mbits) etc
1179 */
1180static void
400ec45a 1181ath5k_set_total_hw_rates(struct ath5k_softc *sc) {
d8ee398d
LR		 1182
1183 struct ath5k_hw *ah = sc->ah;
1184
400ec45a 1185 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
d8ee398d
LR		 1186 sc->a_rates = 8;
1187
400ec45a 1188 if (test_bit(AR5K_MODE_11B, ah->ah_modes))
d8ee398d
LR		 1189 sc->b_rates = 4;
1190
400ec45a 1191 if (test_bit(AR5K_MODE_11G, ah->ah_modes))
d8ee398d
LR		 1192 sc->g_rates = 12;
1193
1194 /* XXX: Need to see what what happens when
1195 xr disable bits in eeprom are set */
400ec45a 1196 if (ah->ah_version >= AR5K_AR5212)
d8ee398d
LR		 1197 sc->xr_rates = 4;
1198
1199}
1200
1201static inline int
400ec45a 1202ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix) {
d8ee398d
LR		 1203
1204 int mac80211_rix;
1205
400ec45a 1206 if(sc->curband->band == IEEE80211_BAND_2GHZ) {
d8ee398d 1207 /* We setup a g ratetable for both b/g modes */
400ec45a
LR		 1208 mac80211_rix =
1209 hw_rix - sc->b_rates - sc->a_rates - sc->xr_rates;
d8ee398d
LR		 1210 } else {
1211 mac80211_rix = hw_rix - sc->xr_rates;
1212 }
1213
1214 /* Something went wrong, fallback to basic rate for this band */
400ec45a
LR		 1215 if ((mac80211_rix >= sc->curband->n_bitrates) ||
1216 (mac80211_rix <= 0 ))
d8ee398d 1217 mac80211_rix = 1;
d8ee398d
LR		 1218
1219 return mac80211_rix;
1220}
1221
fa1c114f
JS		 1222
1223
1224
1225/***************\
1226* Buffers setup *
1227\***************/
1228
1229static int
1230ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1231{
1232 struct ath5k_hw *ah = sc->ah;
1233 struct sk_buff *skb = bf->skb;
1234 struct ath5k_desc *ds;
1235
1236 if (likely(skb == NULL)) {
1237 unsigned int off;
1238
1239 /*
1240 * Allocate buffer with headroom_needed space for the
1241 * fake physical layer header at the start.
1242 */
1243 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1244 if (unlikely(skb == NULL)) {
1245 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1246 sc->rxbufsize + sc->cachelsz - 1);
1247 return -ENOMEM;
1248 }
1249 /*
1250 * Cache-line-align. This is important (for the
1251 * 5210 at least) as not doing so causes bogus data
1252 * in rx'd frames.
1253 */
1254 off = ((unsigned long)skb->data) % sc->cachelsz;
1255 if (off != 0)
1256 skb_reserve(skb, sc->cachelsz - off);
1257
1258 bf->skb = skb;
1259 bf->skbaddr = pci_map_single(sc->pdev,
1260 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1261 if (unlikely(pci_dma_mapping_error(bf->skbaddr))) {
1262 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1263 dev_kfree_skb(skb);
1264 bf->skb = NULL;
1265 return -ENOMEM;
1266 }
1267 }
1268
1269 /*
1270 * Setup descriptors. For receive we always terminate
1271 * the descriptor list with a self-linked entry so we'll
1272 * not get overrun under high load (as can happen with a
1273 * 5212 when ANI processing enables PHY error frames).
1274 *
1275 * To insure the last descriptor is self-linked we create
1276 * each descriptor as self-linked and add it to the end. As
1277 * each additional descriptor is added the previous self-linked
1278 * entry is ``fixed'' naturally. This should be safe even
1279 * if DMA is happening. When processing RX interrupts we
1280 * never remove/process the last, self-linked, entry on the
1281 * descriptor list. This insures the hardware always has
1282 * someplace to write a new frame.
1283 */
1284 ds = bf->desc;
1285 ds->ds_link = bf->daddr; /* link to self */
1286 ds->ds_data = bf->skbaddr;
1287 ath5k_hw_setup_rx_desc(ah, ds,
1288 skb_tailroom(skb), /* buffer size */
1289 0);
1290
1291 if (sc->rxlink != NULL)
1292 *sc->rxlink = bf->daddr;
1293 sc->rxlink = &ds->ds_link;
1294 return 0;
1295}
1296
1297static int
1298ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1299 struct ieee80211_tx_control *ctl)
1300{
1301 struct ath5k_hw *ah = sc->ah;
1302 struct ath5k_txq *txq = sc->txq;
1303 struct ath5k_desc *ds = bf->desc;
1304 struct sk_buff *skb = bf->skb;
1305 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1306 int ret;
1307
1308 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1309 bf->ctl = *ctl;
1310 /* XXX endianness */
1311 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1312 PCI_DMA_TODEVICE);
1313
1314 if (ctl->flags & IEEE80211_TXCTL_NO_ACK)
1315 flags |= AR5K_TXDESC_NOACK;
1316
281c56dd 1317 pktlen = skb->len;
fa1c114f
JS		 1318
1319 if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT)) {
1c014420 1320 keyidx = ctl->hw_key->hw_key_idx;
fa1c114f
JS		 1321 pktlen += ctl->icv_len;
1322 }
1323
1324 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1325 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
2e92e6f2
JB		 1326 (sc->power_level * 2),
1327 ieee80211_get_tx_rate(sc->hw, ctl)->hw_value,
400ec45a 1328 ctl->retry_limit, keyidx, 0, flags, 0, 0);
fa1c114f
JS		 1329 if (ret)
1330 goto err_unmap;
1331
1332 ds->ds_link = 0;
1333 ds->ds_data = bf->skbaddr;
1334
1335 spin_lock_bh(&txq->lock);
1336 list_add_tail(&bf->list, &txq->q);
57ffc589 1337 sc->tx_stats[txq->qnum].len++;
fa1c114f
JS		 1338 if (txq->link == NULL) /* is this first packet? */
1339 ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr);
1340 else /* no, so only link it */
1341 *txq->link = bf->daddr;
1342
1343 txq->link = &ds->ds_link;
1344 ath5k_hw_tx_start(ah, txq->qnum);
1345 spin_unlock_bh(&txq->lock);
1346
1347 return 0;
1348err_unmap:
1349 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1350 return ret;
1351}
1352
1353/*******************\
1354* Descriptors setup *
1355\*******************/
1356
1357static int
1358ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1359{
1360 struct ath5k_desc *ds;
1361 struct ath5k_buf *bf;
1362 dma_addr_t da;
1363 unsigned int i;
1364 int ret;
1365
1366 /* allocate descriptors */
1367 sc->desc_len = sizeof(struct ath5k_desc) *
1368 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1369 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1370 if (sc->desc == NULL) {
1371 ATH5K_ERR(sc, "can't allocate descriptors\n");
1372 ret = -ENOMEM;
1373 goto err;
1374 }
1375 ds = sc->desc;
1376 da = sc->desc_daddr;
1377 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1378 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1379
1380 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1381 sizeof(struct ath5k_buf), GFP_KERNEL);
1382 if (bf == NULL) {
1383 ATH5K_ERR(sc, "can't allocate bufptr\n");
1384 ret = -ENOMEM;
1385 goto err_free;
1386 }
1387 sc->bufptr = bf;
1388
1389 INIT_LIST_HEAD(&sc->rxbuf);
1390 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1391 bf->desc = ds;
1392 bf->daddr = da;
1393 list_add_tail(&bf->list, &sc->rxbuf);
1394 }
1395
1396 INIT_LIST_HEAD(&sc->txbuf);
1397 sc->txbuf_len = ATH_TXBUF;
1398 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1399 da += sizeof(*ds)) {
1400 bf->desc = ds;
1401 bf->daddr = da;
1402 list_add_tail(&bf->list, &sc->txbuf);
1403 }
1404
1405 /* beacon buffer */
1406 bf->desc = ds;
1407 bf->daddr = da;
1408 sc->bbuf = bf;
1409
1410 return 0;
1411err_free:
1412 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1413err:
1414 sc->desc = NULL;
1415 return ret;
1416}
1417
1418static void
1419ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1420{
1421 struct ath5k_buf *bf;
1422
1423 ath5k_txbuf_free(sc, sc->bbuf);
1424 list_for_each_entry(bf, &sc->txbuf, list)
1425 ath5k_txbuf_free(sc, bf);
1426 list_for_each_entry(bf, &sc->rxbuf, list)
1427 ath5k_txbuf_free(sc, bf);
1428
1429 /* Free memory associated with all descriptors */
1430 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1431
1432 kfree(sc->bufptr);
1433 sc->bufptr = NULL;
1434}
1435
1436
1437
1438
1439
1440/**************\
1441* Queues setup *
1442\**************/
1443
1444static struct ath5k_txq *
1445ath5k_txq_setup(struct ath5k_softc *sc,
1446 int qtype, int subtype)
1447{
1448 struct ath5k_hw *ah = sc->ah;
1449 struct ath5k_txq *txq;
1450 struct ath5k_txq_info qi = {
1451 .tqi_subtype = subtype,
1452 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1453 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1454 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1455 };
1456 int qnum;
1457
1458 /*
1459 * Enable interrupts only for EOL and DESC conditions.
1460 * We mark tx descriptors to receive a DESC interrupt
1461 * when a tx queue gets deep; otherwise waiting for the
1462 * EOL to reap descriptors. Note that this is done to
1463 * reduce interrupt load and this only defers reaping
1464 * descriptors, never transmitting frames. Aside from
1465 * reducing interrupts this also permits more concurrency.
1466 * The only potential downside is if the tx queue backs
1467 * up in which case the top half of the kernel may backup
1468 * due to a lack of tx descriptors.
1469 */
1470 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1471 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1472 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1473 if (qnum < 0) {
1474 /*
1475 * NB: don't print a message, this happens
1476 * normally on parts with too few tx queues
1477 */
1478 return ERR_PTR(qnum);
1479 }
1480 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1481 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1482 qnum, ARRAY_SIZE(sc->txqs));
1483 ath5k_hw_release_tx_queue(ah, qnum);
1484 return ERR_PTR(-EINVAL);
1485 }
1486 txq = &sc->txqs[qnum];
1487 if (!txq->setup) {
1488 txq->qnum = qnum;
1489 txq->link = NULL;
1490 INIT_LIST_HEAD(&txq->q);
1491 spin_lock_init(&txq->lock);
1492 txq->setup = true;
1493 }
1494 return &sc->txqs[qnum];
1495}
1496
1497static int
1498ath5k_beaconq_setup(struct ath5k_hw *ah)
1499{
1500 struct ath5k_txq_info qi = {
1501 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1502 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1503 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1504 /* NB: for dynamic turbo, don't enable any other interrupts */
1505 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1506 };
1507
1508 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1509}
1510
1511static int
1512ath5k_beaconq_config(struct ath5k_softc *sc)
1513{
1514 struct ath5k_hw *ah = sc->ah;
1515 struct ath5k_txq_info qi;
1516 int ret;
1517
1518 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1519 if (ret)
1520 return ret;
6d91e1d8 1521 if (sc->opmode == IEEE80211_IF_TYPE_AP) {
fa1c114f
JS		 1522 /*
1523 * Always burst out beacon and CAB traffic
1524 * (aifs = cwmin = cwmax = 0)
1525 */
1526 qi.tqi_aifs = 0;
1527 qi.tqi_cw_min = 0;
1528 qi.tqi_cw_max = 0;
6d91e1d8
BR		 1529 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
1530 /*
1531 * Adhoc mode; backoff between 0 and (2 * cw_min).
1532 */
1533 qi.tqi_aifs = 0;
1534 qi.tqi_cw_min = 0;
1535 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1536 }
1537
6d91e1d8
BR		 1538 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1539 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1540 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1541
fa1c114f
JS		 1542 ret = ath5k_hw_setup_tx_queueprops(ah, sc->bhalq, &qi);
1543 if (ret) {
1544 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1545 "hardware queue!\n", __func__);
1546 return ret;
1547 }
1548
1549 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1550}
1551
1552static void
1553ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1554{
1555 struct ath5k_buf *bf, *bf0;
1556
1557 /*
1558 * NB: this assumes output has been stopped and
1559 * we do not need to block ath5k_tx_tasklet
1560 */
1561 spin_lock_bh(&txq->lock);
1562 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1563 ath5k_debug_printtxbuf(sc, bf);
fa1c114f
JS		 1564
1565 ath5k_txbuf_free(sc, bf);
1566
1567 spin_lock_bh(&sc->txbuflock);
57ffc589 1568 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1569 list_move_tail(&bf->list, &sc->txbuf);
1570 sc->txbuf_len++;
1571 spin_unlock_bh(&sc->txbuflock);
1572 }
1573 txq->link = NULL;
1574 spin_unlock_bh(&txq->lock);
1575}
1576
1577/*
1578 * Drain the transmit queues and reclaim resources.
1579 */
1580static void
1581ath5k_txq_cleanup(struct ath5k_softc *sc)
1582{
1583 struct ath5k_hw *ah = sc->ah;
1584 unsigned int i;
1585
1586 /* XXX return value */
1587 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1588 /* don't touch the hardware if marked invalid */
1589 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1590 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1591 ath5k_hw_get_tx_buf(ah, sc->bhalq));
1592 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1593 if (sc->txqs[i].setup) {
1594 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1595 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1596 "link %p\n",
1597 sc->txqs[i].qnum,
1598 ath5k_hw_get_tx_buf(ah,
1599 sc->txqs[i].qnum),
1600 sc->txqs[i].link);
1601 }
1602 }
36d6825b 1603 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
fa1c114f
JS		 1604
1605 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1606 if (sc->txqs[i].setup)
1607 ath5k_txq_drainq(sc, &sc->txqs[i]);
1608}
1609
1610static void
1611ath5k_txq_release(struct ath5k_softc *sc)
1612{
1613 struct ath5k_txq *txq = sc->txqs;
1614 unsigned int i;
1615
1616 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1617 if (txq->setup) {
1618 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1619 txq->setup = false;
1620 }
1621}
1622
1623
1624
1625
1626/*************\
1627* RX Handling *
1628\*************/
1629
1630/*
1631 * Enable the receive h/w following a reset.
1632 */
1633static int
1634ath5k_rx_start(struct ath5k_softc *sc)
1635{
1636 struct ath5k_hw *ah = sc->ah;
1637 struct ath5k_buf *bf;
1638 int ret;
1639
1640 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1641
1642 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1643 sc->cachelsz, sc->rxbufsize);
1644
1645 sc->rxlink = NULL;
1646
1647 spin_lock_bh(&sc->rxbuflock);
1648 list_for_each_entry(bf, &sc->rxbuf, list) {
1649 ret = ath5k_rxbuf_setup(sc, bf);
1650 if (ret != 0) {
1651 spin_unlock_bh(&sc->rxbuflock);
1652 goto err;
1653 }
1654 }
1655 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1656 spin_unlock_bh(&sc->rxbuflock);
1657
1658 ath5k_hw_put_rx_buf(ah, bf->daddr);
1659 ath5k_hw_start_rx(ah); /* enable recv descriptors */
1660 ath5k_mode_setup(sc); /* set filters, etc. */
1661 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1662
1663 return 0;
1664err:
1665 return ret;
1666}
1667
1668/*
1669 * Disable the receive h/w in preparation for a reset.
1670 */
1671static void
1672ath5k_rx_stop(struct ath5k_softc *sc)
1673{
1674 struct ath5k_hw *ah = sc->ah;
1675
1676 ath5k_hw_stop_pcu_recv(ah); /* disable PCU */
1677 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1678 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1679 mdelay(3); /* 3ms is long enough for 1 frame */
1680
1681 ath5k_debug_printrxbuffs(sc, ah);
1682
1683 sc->rxlink = NULL; /* just in case */
1684}
1685
1686static unsigned int
1687ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1688 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f
JS		 1689{
1690 struct ieee80211_hdr *hdr = (void *)skb->data;
1691 unsigned int keyix, hlen = ieee80211_get_hdrlen_from_skb(skb);
1692
b47f407b
BR		 1693 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1694 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1695 return RX_FLAG_DECRYPTED;
1696
1697 /* Apparently when a default key is used to decrypt the packet
1698 the hw does not set the index used to decrypt. In such cases
1699 get the index from the packet. */
1700 if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED) &&
b47f407b 1701 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
fa1c114f
JS		 1702 skb->len >= hlen + 4) {
1703 keyix = skb->data[hlen + 3] >> 6;
1704
1705 if (test_bit(keyix, sc->keymap))
1706 return RX_FLAG_DECRYPTED;
1707 }
1708
1709 return 0;
1710}
1711
036cd1ec
BR		 1712
1713static void
6ba81c2c
BR		 1714ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1715 struct ieee80211_rx_status *rxs)
036cd1ec 1716{
6ba81c2c 1717 u64 tsf, bc_tstamp;
036cd1ec
BR		 1718 u32 hw_tu;
1719 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1720
38c07b43 1721 if ((le16_to_cpu(mgmt->frame_control) & IEEE80211_FCTL_FTYPE) ==
036cd1ec 1722 IEEE80211_FTYPE_MGMT &&
38c07b43 1723 (le16_to_cpu(mgmt->frame_control) & IEEE80211_FCTL_STYPE) ==
036cd1ec 1724 IEEE80211_STYPE_BEACON &&
38c07b43 1725 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
036cd1ec
BR		 1726 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1727 /*
6ba81c2c
BR		 1728 * Received an IBSS beacon with the same BSSID. Hardware *must*
1729 * have updated the local TSF. We have to work around various
1730 * hardware bugs, though...
036cd1ec 1731 */
6ba81c2c
BR		 1732 tsf = ath5k_hw_get_tsf64(sc->ah);
1733 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1734 hw_tu = TSF_TO_TU(tsf);
1735
1736 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1737 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1738 (unsigned long long)bc_tstamp,
1739 (unsigned long long)rxs->mactime,
1740 (unsigned long long)(rxs->mactime - bc_tstamp),
1741 (unsigned long long)tsf);
6ba81c2c
BR		 1742
1743 /*
1744 * Sometimes the HW will give us a wrong tstamp in the rx
1745 * status, causing the timestamp extension to go wrong.
1746 * (This seems to happen especially with beacon frames bigger
1747 * than 78 byte (incl. FCS))
1748 * But we know that the receive timestamp must be later than the
1749 * timestamp of the beacon since HW must have synced to that.
1750 *
1751 * NOTE: here we assume mactime to be after the frame was
1752 * received, not like mac80211 which defines it at the start.
1753 */
1754 if (bc_tstamp > rxs->mactime) {
036cd1ec 1755 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1756 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1757 (unsigned long long)rxs->mactime,
1758 (unsigned long long)tsf);
6ba81c2c 1759 rxs->mactime = tsf;
036cd1ec 1760 }
6ba81c2c
BR		 1761
1762 /*
1763 * Local TSF might have moved higher than our beacon timers,
1764 * in that case we have to update them to continue sending
1765 * beacons. This also takes care of synchronizing beacon sending
1766 * times with other stations.
1767 */
1768 if (hw_tu >= sc->nexttbtt)
1769 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1770 }
1771}
1772
1773
fa1c114f
JS		 1774static void
1775ath5k_tasklet_rx(unsigned long data)
1776{
1777 struct ieee80211_rx_status rxs = {};
b47f407b 1778 struct ath5k_rx_status rs = {};
fa1c114f
JS		 1779 struct sk_buff *skb;
1780 struct ath5k_softc *sc = (void *)data;
1781 struct ath5k_buf *bf;
1782 struct ath5k_desc *ds;
fa1c114f
JS		 1783 int ret;
1784 int hdrlen;
1785 int pad;
1786
1787 spin_lock(&sc->rxbuflock);
1788 do {
d6894b5b
BC		 1789 rxs.flag = 0;
1790
fa1c114f
JS		 1791 if (unlikely(list_empty(&sc->rxbuf))) {
1792 ATH5K_WARN(sc, "empty rx buf pool\n");
1793 break;
1794 }
1795 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1796 BUG_ON(bf->skb == NULL);
1797 skb = bf->skb;
1798 ds = bf->desc;
1799
1800 /* TODO only one segment */
1801 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1802 sc->desc_len, PCI_DMA_FROMDEVICE);
1803
1804 if (unlikely(ds->ds_link == bf->daddr)) /* this is the end */
1805 break;
1806
b47f407b 1807 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1808 if (unlikely(ret == -EINPROGRESS))
1809 break;
1810 else if (unlikely(ret)) {
1811 ATH5K_ERR(sc, "error in processing rx descriptor\n");
65872e6b 1812 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1813 return;
1814 }
1815
b47f407b 1816 if (unlikely(rs.rs_more)) {
fa1c114f
JS		 1817 ATH5K_WARN(sc, "unsupported jumbo\n");
1818 goto next;
1819 }
1820
b47f407b
BR		 1821 if (unlikely(rs.rs_status)) {
1822 if (rs.rs_status & AR5K_RXERR_PHY)
fa1c114f 1823 goto next;
b47f407b 1824 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1825 /*
1826 * Decrypt error. If the error occurred
1827 * because there was no hardware key, then
1828 * let the frame through so the upper layers
1829 * can process it. This is necessary for 5210
1830 * parts which have no way to setup a ``clear''
1831 * key cache entry.
1832 *
1833 * XXX do key cache faulting
1834 */
b47f407b
BR		 1835 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1836 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1837 goto accept;
1838 }
b47f407b 1839 if (rs.rs_status & AR5K_RXERR_MIC) {
fa1c114f
JS		 1840 rxs.flag |= RX_FLAG_MMIC_ERROR;
1841 goto accept;
1842 }
1843
1844 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1845 if ((rs.rs_status &
1846 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
fa1c114f
JS		 1847 sc->opmode != IEEE80211_IF_TYPE_MNTR)
1848 goto next;
1849 }
1850accept:
b47f407b
BR		 1851 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr,
1852 rs.rs_datalen, PCI_DMA_FROMDEVICE);
fa1c114f
JS		 1853 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1854 PCI_DMA_FROMDEVICE);
1855 bf->skb = NULL;
1856
b47f407b 1857 skb_put(skb, rs.rs_datalen);
fa1c114f
JS		 1858
1859 /*
1860 * the hardware adds a padding to 4 byte boundaries between
1861 * the header and the payload data if the header length is
1862 * not multiples of 4 - remove it
1863 */
1864 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1865 if (hdrlen & 3) {
1866 pad = hdrlen % 4;
1867 memmove(skb->data + pad, skb->data, hdrlen);
1868 skb_pull(skb, pad);
1869 }
1870
c0e1899b
BR		 1871 /*
1872 * always extend the mac timestamp, since this information is
1873 * also needed for proper IBSS merging.
1874 *
1875 * XXX: it might be too late to do it here, since rs_tstamp is
1876 * 15bit only. that means TSF extension has to be done within
1877 * 32768usec (about 32ms). it might be necessary to move this to
1878 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 1879 *
1880 * Unfortunately we don't know when the hardware takes the rx
1881 * timestamp (beginning of phy frame, data frame, end of rx?).
1882 * The only thing we know is that it is hardware specific...
1883 * On AR5213 it seems the rx timestamp is at the end of the
1884 * frame, but i'm not sure.
1885 *
1886 * NOTE: mac80211 defines mactime at the beginning of the first
1887 * data symbol. Since we don't have any time references it's
1888 * impossible to comply to that. This affects IBSS merge only
1889 * right now, so it's not too bad...
c0e1899b 1890 */
b47f407b 1891 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
c0e1899b
BR		 1892 rxs.flag |= RX_FLAG_TSFT;
1893
d8ee398d
LR		 1894 rxs.freq = sc->curchan->center_freq;
1895 rxs.band = sc->curband->band;
fa1c114f 1896
fa1c114f 1897 rxs.noise = sc->ah->ah_noise_floor;
566bfe5a
BR		 1898 rxs.signal = rxs.noise + rs.rs_rssi;
1899 rxs.qual = rs.rs_rssi * 100 / 64;
fa1c114f 1900
b47f407b
BR		 1901 rxs.antenna = rs.rs_antenna;
1902 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1903 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f
JS		 1904
1905 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1906
036cd1ec
BR		 1907 /* check beacons in IBSS mode */
1908 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
6ba81c2c 1909 ath5k_check_ibss_tsf(sc, skb, &rxs);
036cd1ec 1910
fa1c114f 1911 __ieee80211_rx(sc->hw, skb, &rxs);
b47f407b 1912 sc->led_rxrate = rs.rs_rate;
fa1c114f
JS		 1913 ath5k_led_event(sc, ATH_LED_RX);
1914next:
1915 list_move_tail(&bf->list, &sc->rxbuf);
1916 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1917 spin_unlock(&sc->rxbuflock);
1918}
1919
1920
1921
1922
1923/*************\
1924* TX Handling *
1925\*************/
1926
1927static void
1928ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1929{
1930 struct ieee80211_tx_status txs = {};
b47f407b 1931 struct ath5k_tx_status ts = {};
fa1c114f
JS		 1932 struct ath5k_buf *bf, *bf0;
1933 struct ath5k_desc *ds;
1934 struct sk_buff *skb;
1935 int ret;
1936
1937 spin_lock(&txq->lock);
1938 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1939 ds = bf->desc;
1940
1941 /* TODO only one segment */
1942 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1943 sc->desc_len, PCI_DMA_FROMDEVICE);
b47f407b 1944 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 1945 if (unlikely(ret == -EINPROGRESS))
1946 break;
1947 else if (unlikely(ret)) {
1948 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1949 ret, txq->qnum);
1950 break;
1951 }
1952
1953 skb = bf->skb;
1954 bf->skb = NULL;
1955 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1956 PCI_DMA_TODEVICE);
1957
1958 txs.control = bf->ctl;
b47f407b
BR		 1959 txs.retry_count = ts.ts_shortretry + ts.ts_longretry / 6;
1960 if (unlikely(ts.ts_status)) {
fa1c114f 1961 sc->ll_stats.dot11ACKFailureCount++;
b47f407b 1962 if (ts.ts_status & AR5K_TXERR_XRETRY)
fa1c114f 1963 txs.excessive_retries = 1;
b47f407b 1964 else if (ts.ts_status & AR5K_TXERR_FILT)
fa1c114f
JS		 1965 txs.flags |= IEEE80211_TX_STATUS_TX_FILTERED;
1966 } else {
1967 txs.flags |= IEEE80211_TX_STATUS_ACK;
b47f407b 1968 txs.ack_signal = ts.ts_rssi;
fa1c114f
JS		 1969 }
1970
1971 ieee80211_tx_status(sc->hw, skb, &txs);
57ffc589 1972 sc->tx_stats[txq->qnum].count++;
fa1c114f
JS		 1973
1974 spin_lock(&sc->txbuflock);
57ffc589 1975 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1976 list_move_tail(&bf->list, &sc->txbuf);
1977 sc->txbuf_len++;
1978 spin_unlock(&sc->txbuflock);
1979 }
1980 if (likely(list_empty(&txq->q)))
1981 txq->link = NULL;
1982 spin_unlock(&txq->lock);
1983 if (sc->txbuf_len > ATH_TXBUF / 5)
1984 ieee80211_wake_queues(sc->hw);
1985}
1986
1987static void
1988ath5k_tasklet_tx(unsigned long data)
1989{
1990 struct ath5k_softc *sc = (void *)data;
1991
1992 ath5k_tx_processq(sc, sc->txq);
1993
1994 ath5k_led_event(sc, ATH_LED_TX);
1995}
1996
1997
1998
1999
2000/*****************\
2001* Beacon handling *
2002\*****************/
2003
2004/*
2005 * Setup the beacon frame for transmit.
2006 */
2007static int
2008ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
2009 struct ieee80211_tx_control *ctl)
2010{
2011 struct sk_buff *skb = bf->skb;
2012 struct ath5k_hw *ah = sc->ah;
2013 struct ath5k_desc *ds;
2014 int ret, antenna = 0;
2015 u32 flags;
2016
2017 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2018 PCI_DMA_TODEVICE);
2019 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2020 "skbaddr %llx\n", skb, skb->data, skb->len,
2021 (unsigned long long)bf->skbaddr);
2022 if (pci_dma_mapping_error(bf->skbaddr)) {
2023 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2024 return -EIO;
2025 }
2026
2027 ds = bf->desc;
2028
2029 flags = AR5K_TXDESC_NOACK;
2030 if (sc->opmode == IEEE80211_IF_TYPE_IBSS && ath5k_hw_hasveol(ah)) {
2031 ds->ds_link = bf->daddr; /* self-linked */
2032 flags |= AR5K_TXDESC_VEOL;
2033 /*
2034 * Let hardware handle antenna switching if txantenna is not set
2035 */
2036 } else {
2037 ds->ds_link = 0;
2038 /*
2039 * Switch antenna every 4 beacons if txantenna is not set
2040 * XXX assumes two antennas
2041 */
2042 if (antenna == 0)
2043 antenna = sc->bsent & 4 ? 2 : 1;
2044 }
2045
2046 ds->ds_data = bf->skbaddr;
281c56dd 2047 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
fa1c114f 2048 ieee80211_get_hdrlen_from_skb(skb),
400ec45a 2049 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2e92e6f2
JB		 2050 ieee80211_get_tx_rate(sc->hw, ctl)->hw_value,
2051 1, AR5K_TXKEYIX_INVALID,
400ec45a 2052 antenna, flags, 0, 0);
fa1c114f
JS		 2053 if (ret)
2054 goto err_unmap;
2055
2056 return 0;
2057err_unmap:
2058 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2059 return ret;
2060}
2061
2062/*
2063 * Transmit a beacon frame at SWBA. Dynamic updates to the
2064 * frame contents are done as needed and the slot time is
2065 * also adjusted based on current state.
2066 *
2067 * this is usually called from interrupt context (ath5k_intr())
2068 * but also from ath5k_beacon_config() in IBSS mode which in turn
2069 * can be called from a tasklet and user context
2070 */
2071static void
2072ath5k_beacon_send(struct ath5k_softc *sc)
2073{
2074 struct ath5k_buf *bf = sc->bbuf;
2075 struct ath5k_hw *ah = sc->ah;
2076
be9b7259 2077 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f
JS		 2078
2079 if (unlikely(bf->skb == NULL || sc->opmode == IEEE80211_IF_TYPE_STA ||
2080 sc->opmode == IEEE80211_IF_TYPE_MNTR)) {
2081 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2082 return;
2083 }
2084 /*
2085 * Check if the previous beacon has gone out. If
2086 * not don't don't try to post another, skip this
2087 * period and wait for the next. Missed beacons
2088 * indicate a problem and should not occur. If we
2089 * miss too many consecutive beacons reset the device.
2090 */
2091 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2092 sc->bmisscount++;
be9b7259 2093 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2094 "missed %u consecutive beacons\n", sc->bmisscount);
2095 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
be9b7259 2096 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2097 "stuck beacon time (%u missed)\n",
2098 sc->bmisscount);
2099 tasklet_schedule(&sc->restq);
2100 }
2101 return;
2102 }
2103 if (unlikely(sc->bmisscount != 0)) {
be9b7259 2104 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2105 "resume beacon xmit after %u misses\n",
2106 sc->bmisscount);
2107 sc->bmisscount = 0;
2108 }
2109
2110 /*
2111 * Stop any current dma and put the new frame on the queue.
2112 * This should never fail since we check above that no frames
2113 * are still pending on the queue.
2114 */
2115 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2116 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2117 /* NB: hw still stops DMA, so proceed */
2118 }
2119 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, bf->skb->len,
2120 PCI_DMA_TODEVICE);
2121
2122 ath5k_hw_put_tx_buf(ah, sc->bhalq, bf->daddr);
2123 ath5k_hw_tx_start(ah, sc->bhalq);
be9b7259 2124 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2125 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2126
2127 sc->bsent++;
2128}
2129
2130
9804b98d
BR		 2131/**
2132 * ath5k_beacon_update_timers - update beacon timers
2133 *
2134 * @sc: struct ath5k_softc pointer we are operating on
2135 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2136 * beacon timer update based on the current HW TSF.
2137 *
2138 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2139 * of a received beacon or the current local hardware TSF and write it to the
2140 * beacon timer registers.
2141 *
2142 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2143 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2144 * when we otherwise know we have to update the timers, but we keep it in this
2145 * function to have it all together in one place.
2146 */
fa1c114f 2147static void
9804b98d 2148ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2149{
2150 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2151 u32 nexttbtt, intval, hw_tu, bc_tu;
2152 u64 hw_tsf;
fa1c114f
JS		 2153
2154 intval = sc->bintval & AR5K_BEACON_PERIOD;
2155 if (WARN_ON(!intval))
2156 return;
2157
9804b98d
BR		 2158 /* beacon TSF converted to TU */
2159 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2160
9804b98d
BR		 2161 /* current TSF converted to TU */
2162 hw_tsf = ath5k_hw_get_tsf64(ah);
2163 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2164
9804b98d
BR		 2165#define FUDGE 3
2166 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2167 if (bc_tsf == -1) {
2168 /*
2169 * no beacons received, called internally.
2170 * just need to refresh timers based on HW TSF.
2171 */
2172 nexttbtt = roundup(hw_tu + FUDGE, intval);
2173 } else if (bc_tsf == 0) {
2174 /*
2175 * no beacon received, probably called by ath5k_reset_tsf().
2176 * reset TSF to start with 0.
2177 */
2178 nexttbtt = intval;
2179 intval |= AR5K_BEACON_RESET_TSF;
2180 } else if (bc_tsf > hw_tsf) {
2181 /*
2182 * beacon received, SW merge happend but HW TSF not yet updated.
2183 * not possible to reconfigure timers yet, but next time we
2184 * receive a beacon with the same BSSID, the hardware will
2185 * automatically update the TSF and then we need to reconfigure
2186 * the timers.
2187 */
2188 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2189 "need to wait for HW TSF sync\n");
2190 return;
2191 } else {
2192 /*
2193 * most important case for beacon synchronization between STA.
2194 *
2195 * beacon received and HW TSF has been already updated by HW.
2196 * update next TBTT based on the TSF of the beacon, but make
2197 * sure it is ahead of our local TSF timer.
2198 */
2199 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2200 }
2201#undef FUDGE
fa1c114f 2202
036cd1ec
BR		 2203 sc->nexttbtt = nexttbtt;
2204
fa1c114f 2205 intval |= AR5K_BEACON_ENA;
fa1c114f 2206 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2207
2208 /*
2209 * debugging output last in order to preserve the time critical aspect
2210 * of this function
2211 */
2212 if (bc_tsf == -1)
2213 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2214 "reconfigured timers based on HW TSF\n");
2215 else if (bc_tsf == 0)
2216 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2217 "reset HW TSF and timers\n");
2218 else
2219 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2220 "updated timers based on beacon TSF\n");
2221
2222 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2223 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2224 (unsigned long long) bc_tsf,
2225 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2226 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2227 intval & AR5K_BEACON_PERIOD,
2228 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2229 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2230}
2231
2232
036cd1ec
BR		 2233/**
2234 * ath5k_beacon_config - Configure the beacon queues and interrupts
2235 *
2236 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f
JS		 2237 *
2238 * When operating in station mode we want to receive a BMISS interrupt when we
2239 * stop seeing beacons from the AP we've associated with so we can look for
2240 * another AP to associate with.
2241 *
036cd1ec 2242 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2243 * interrupts to detect TSF updates only.
036cd1ec
BR		 2244 *
2245 * AP mode is missing.
fa1c114f
JS		 2246 */
2247static void
2248ath5k_beacon_config(struct ath5k_softc *sc)
2249{
2250 struct ath5k_hw *ah = sc->ah;
2251
2252 ath5k_hw_set_intr(ah, 0);
2253 sc->bmisscount = 0;
2254
2255 if (sc->opmode == IEEE80211_IF_TYPE_STA) {
2256 sc->imask |= AR5K_INT_BMISS;
2257 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2258 /*
036cd1ec
BR		 2259 * In IBSS mode we use a self-linked tx descriptor and let the
2260 * hardware send the beacons automatically. We have to load it
fa1c114f 2261 * only once here.
036cd1ec 2262 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2263 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2264 */
2265 ath5k_beaconq_config(sc);
fa1c114f 2266
036cd1ec
BR		 2267 sc->imask |= AR5K_INT_SWBA;
2268
2269 if (ath5k_hw_hasveol(ah))
fa1c114f
JS		 2270 ath5k_beacon_send(sc);
2271 }
2272 /* TODO else AP */
2273
2274 ath5k_hw_set_intr(ah, sc->imask);
2275}
2276
2277
2278/********************\
2279* Interrupt handling *
2280\********************/
2281
2282static int
2283ath5k_init(struct ath5k_softc *sc)
2284{
2285 int ret;
2286
2287 mutex_lock(&sc->lock);
2288
2289 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2290
2291 /*
2292 * Stop anything previously setup. This is safe
2293 * no matter this is the first time through or not.
2294 */
2295 ath5k_stop_locked(sc);
2296
2297 /*
2298 * The basic interface to setting the hardware in a good
2299 * state is ``reset''. On return the hardware is known to
2300 * be powered up and with interrupts disabled. This must
2301 * be followed by initialization of the appropriate bits
2302 * and then setup of the interrupt mask.
2303 */
d8ee398d
LR		 2304 sc->curchan = sc->hw->conf.channel;
2305 sc->curband = &sc->sbands[sc->curchan->band];
fa1c114f
JS		 2306 ret = ath5k_hw_reset(sc->ah, sc->opmode, sc->curchan, false);
2307 if (ret) {
2308 ATH5K_ERR(sc, "unable to reset hardware: %d\n", ret);
2309 goto done;
2310 }
2311 /*
2312 * This is needed only to setup initial state
2313 * but it's best done after a reset.
2314 */
2315 ath5k_hw_set_txpower_limit(sc->ah, 0);
2316
2317 /*
2318 * Setup the hardware after reset: the key cache
2319 * is filled as needed and the receive engine is
2320 * set going. Frame transmit is handled entirely
2321 * in the frame output path; there's nothing to do
2322 * here except setup the interrupt mask.
2323 */
2324 ret = ath5k_rx_start(sc);
2325 if (ret)
2326 goto done;
2327
2328 /*
2329 * Enable interrupts.
2330 */
2331 sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
194828a2
NK		 2332 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL |
2333 AR5K_INT_MIB;
fa1c114f
JS		 2334
2335 ath5k_hw_set_intr(sc->ah, sc->imask);
2336 /* Set ack to be sent at low bit-rates */
2337 ath5k_hw_set_ack_bitrate_high(sc->ah, false);
2338
2339 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2340 msecs_to_jiffies(ath5k_calinterval * 1000)));
2341
2342 ret = 0;
2343done:
2344 mutex_unlock(&sc->lock);
2345 return ret;
2346}
2347
2348static int
2349ath5k_stop_locked(struct ath5k_softc *sc)
2350{
2351 struct ath5k_hw *ah = sc->ah;
2352
2353 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2354 test_bit(ATH_STAT_INVALID, sc->status));
2355
2356 /*
2357 * Shutdown the hardware and driver:
2358 * stop output from above
2359 * disable interrupts
2360 * turn off timers
2361 * turn off the radio
2362 * clear transmit machinery
2363 * clear receive machinery
2364 * drain and release tx queues
2365 * reclaim beacon resources
2366 * power down hardware
2367 *
2368 * Note that some of this work is not possible if the
2369 * hardware is gone (invalid).
2370 */
2371 ieee80211_stop_queues(sc->hw);
2372
2373 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2374 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2375 del_timer_sync(&sc->led_tim);
2376 ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on);
2377 __clear_bit(ATH_STAT_LEDBLINKING, sc->status);
2378 }
2379 ath5k_hw_set_intr(ah, 0);
2380 }
2381 ath5k_txq_cleanup(sc);
2382 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2383 ath5k_rx_stop(sc);
2384 ath5k_hw_phy_disable(ah);
2385 } else
2386 sc->rxlink = NULL;
2387
2388 return 0;
2389}
2390
2391/*
2392 * Stop the device, grabbing the top-level lock to protect
2393 * against concurrent entry through ath5k_init (which can happen
2394 * if another thread does a system call and the thread doing the
2395 * stop is preempted).
2396 */
2397static int
2398ath5k_stop_hw(struct ath5k_softc *sc)
2399{
2400 int ret;
2401
2402 mutex_lock(&sc->lock);
2403 ret = ath5k_stop_locked(sc);
2404 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2405 /*
2406 * Set the chip in full sleep mode. Note that we are
2407 * careful to do this only when bringing the interface
2408 * completely to a stop. When the chip is in this state
2409 * it must be carefully woken up or references to
2410 * registers in the PCI clock domain may freeze the bus
2411 * (and system). This varies by chip and is mostly an
2412 * issue with newer parts that go to sleep more quickly.
2413 */
2414 if (sc->ah->ah_mac_srev >= 0x78) {
2415 /*
2416 * XXX
2417 * don't put newer MAC revisions > 7.8 to sleep because
2418 * of the above mentioned problems
2419 */
2420 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2421 "not putting device to sleep\n");
2422 } else {
2423 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2424 "putting device to full sleep\n");
2425 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2426 }
2427 }
2428 ath5k_txbuf_free(sc, sc->bbuf);
2429 mutex_unlock(&sc->lock);
2430
2431 del_timer_sync(&sc->calib_tim);
2432
2433 return ret;
2434}
2435
2436static irqreturn_t
2437ath5k_intr(int irq, void *dev_id)
2438{
2439 struct ath5k_softc *sc = dev_id;
2440 struct ath5k_hw *ah = sc->ah;
2441 enum ath5k_int status;
2442 unsigned int counter = 1000;
2443
2444 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2445 !ath5k_hw_is_intr_pending(ah)))
2446 return IRQ_NONE;
2447
2448 do {
2449 /*
2450 * Figure out the reason(s) for the interrupt. Note
2451 * that get_isr returns a pseudo-ISR that may include
2452 * bits we haven't explicitly enabled so we mask the
2453 * value to insure we only process bits we requested.
2454 */
2455 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2456 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2457 status, sc->imask);
2458 status &= sc->imask; /* discard unasked for bits */
2459 if (unlikely(status & AR5K_INT_FATAL)) {
2460 /*
2461 * Fatal errors are unrecoverable.
2462 * Typically these are caused by DMA errors.
2463 */
2464 tasklet_schedule(&sc->restq);
2465 } else if (unlikely(status & AR5K_INT_RXORN)) {
2466 tasklet_schedule(&sc->restq);
2467 } else {
2468 if (status & AR5K_INT_SWBA) {
2469 /*
2470 * Software beacon alert--time to send a beacon.
2471 * Handle beacon transmission directly; deferring
2472 * this is too slow to meet timing constraints
2473 * under load.
036cd1ec
BR		 2474 *
2475 * In IBSS mode we use this interrupt just to
2476 * keep track of the next TBTT (target beacon
6ba81c2c
BR		 2477 * transmission time) in order to detect wether
2478 * automatic TSF updates happened.
fa1c114f 2479 */
036cd1ec
BR		 2480 if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2481 /* XXX: only if VEOL suppported */
2482 u64 tsf = ath5k_hw_get_tsf64(ah);
2483 sc->nexttbtt += sc->bintval;
2484 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2485 "SWBA nexttbtt: %x hw_tu: %x "
2486 "TSF: %llx\n",
2487 sc->nexttbtt,
2488 TSF_TO_TU(tsf),
2489 (unsigned long long) tsf);
036cd1ec
BR		 2490 } else {
2491 ath5k_beacon_send(sc);
2492 }
fa1c114f
JS		 2493 }
2494 if (status & AR5K_INT_RXEOL) {
2495 /*
2496 * NB: the hardware should re-read the link when
2497 * RXE bit is written, but it doesn't work at
2498 * least on older hardware revs.
2499 */
2500 sc->rxlink = NULL;
2501 }
2502 if (status & AR5K_INT_TXURN) {
2503 /* bump tx trigger level */
2504 ath5k_hw_update_tx_triglevel(ah, true);
2505 }
2506 if (status & AR5K_INT_RX)
2507 tasklet_schedule(&sc->rxtq);
2508 if (status & AR5K_INT_TX)
2509 tasklet_schedule(&sc->txtq);
2510 if (status & AR5K_INT_BMISS) {
2511 }
2512 if (status & AR5K_INT_MIB) {
194828a2
NK		 2513 /*
2514 * These stats are also used for ANI i think
2515 * so how about updating them more often ?
2516 */
2517 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2518 }
2519 }
2520 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2521
2522 if (unlikely(!counter))
2523 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2524
2525 return IRQ_HANDLED;
2526}
2527
2528static void
2529ath5k_tasklet_reset(unsigned long data)
2530{
2531 struct ath5k_softc *sc = (void *)data;
2532
2533 ath5k_reset(sc->hw);
2534}
2535
2536/*
2537 * Periodically recalibrate the PHY to account
2538 * for temperature/environment changes.
2539 */
2540static void
2541ath5k_calibrate(unsigned long data)
2542{
2543 struct ath5k_softc *sc = (void *)data;
2544 struct ath5k_hw *ah = sc->ah;
2545
2546 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2547 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2548 sc->curchan->hw_value);
fa1c114f
JS		 2549
2550 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2551 /*
2552 * Rfgain is out of bounds, reset the chip
2553 * to load new gain values.
2554 */
2555 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2556 ath5k_reset(sc->hw);
2557 }
2558 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2559 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2560 ieee80211_frequency_to_channel(
2561 sc->curchan->center_freq));
fa1c114f
JS		 2562
2563 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2564 msecs_to_jiffies(ath5k_calinterval * 1000)));
2565}
2566
2567
2568
2569/***************\
2570* LED functions *
2571\***************/
2572
2573static void
2574ath5k_led_off(unsigned long data)
2575{
2576 struct ath5k_softc *sc = (void *)data;
2577
2578 if (test_bit(ATH_STAT_LEDENDBLINK, sc->status))
2579 __clear_bit(ATH_STAT_LEDBLINKING, sc->status);
2580 else {
2581 __set_bit(ATH_STAT_LEDENDBLINK, sc->status);
2582 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2583 mod_timer(&sc->led_tim, jiffies + sc->led_off);
2584 }
2585}
2586
2587/*
2588 * Blink the LED according to the specified on/off times.
2589 */
2590static void
2591ath5k_led_blink(struct ath5k_softc *sc, unsigned int on,
2592 unsigned int off)
2593{
2594 ATH5K_DBG(sc, ATH5K_DEBUG_LED, "on %u off %u\n", on, off);
2595 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2596 __set_bit(ATH_STAT_LEDBLINKING, sc->status);
2597 __clear_bit(ATH_STAT_LEDENDBLINK, sc->status);
2598 sc->led_off = off;
2599 mod_timer(&sc->led_tim, jiffies + on);
2600}
2601
2602static void
2603ath5k_led_event(struct ath5k_softc *sc, int event)
2604{
2605 if (likely(!test_bit(ATH_STAT_LEDSOFT, sc->status)))
2606 return;
2607 if (unlikely(test_bit(ATH_STAT_LEDBLINKING, sc->status)))
2608 return; /* don't interrupt active blink */
2609 switch (event) {
2610 case ATH_LED_TX:
2611 ath5k_led_blink(sc, sc->hwmap[sc->led_txrate].ledon,
2612 sc->hwmap[sc->led_txrate].ledoff);
2613 break;
2614 case ATH_LED_RX:
2615 ath5k_led_blink(sc, sc->hwmap[sc->led_rxrate].ledon,
2616 sc->hwmap[sc->led_rxrate].ledoff);
2617 break;
2618 }
2619}
2620
2621
2622
2623
2624/********************\
2625* Mac80211 functions *
2626\********************/
2627
2628static int
2629ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2630 struct ieee80211_tx_control *ctl)
2631{
2632 struct ath5k_softc *sc = hw->priv;
2633 struct ath5k_buf *bf;
2634 unsigned long flags;
2635 int hdrlen;
2636 int pad;
2637
2638 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2639
2640 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2641 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2642
2643 /*
2644 * the hardware expects the header padded to 4 byte boundaries
2645 * if this is not the case we add the padding after the header
2646 */
2647 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2648 if (hdrlen & 3) {
2649 pad = hdrlen % 4;
2650 if (skb_headroom(skb) < pad) {
2651 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2652 " headroom to pad %d\n", hdrlen, pad);
2653 return -1;
2654 }
2655 skb_push(skb, pad);
2656 memmove(skb->data, skb->data+pad, hdrlen);
2657 }
2658
2e92e6f2 2659 sc->led_txrate = ieee80211_get_tx_rate(hw, ctl)->hw_value;
fa1c114f
JS		 2660
2661 spin_lock_irqsave(&sc->txbuflock, flags);
2662 if (list_empty(&sc->txbuf)) {
2663 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2664 spin_unlock_irqrestore(&sc->txbuflock, flags);
2665 ieee80211_stop_queue(hw, ctl->queue);
2666 return -1;
2667 }
2668 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2669 list_del(&bf->list);
2670 sc->txbuf_len--;
2671 if (list_empty(&sc->txbuf))
2672 ieee80211_stop_queues(hw);
2673 spin_unlock_irqrestore(&sc->txbuflock, flags);
2674
2675 bf->skb = skb;
2676
2677 if (ath5k_txbuf_setup(sc, bf, ctl)) {
2678 bf->skb = NULL;
2679 spin_lock_irqsave(&sc->txbuflock, flags);
2680 list_add_tail(&bf->list, &sc->txbuf);
2681 sc->txbuf_len++;
2682 spin_unlock_irqrestore(&sc->txbuflock, flags);
2683 dev_kfree_skb_any(skb);
2684 return 0;
2685 }
2686
2687 return 0;
2688}
2689
2690static int
2691ath5k_reset(struct ieee80211_hw *hw)
2692{
2693 struct ath5k_softc *sc = hw->priv;
2694 struct ath5k_hw *ah = sc->ah;
2695 int ret;
2696
2697 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f
JS		 2698
2699 ath5k_hw_set_intr(ah, 0);
2700 ath5k_txq_cleanup(sc);
2701 ath5k_rx_stop(sc);
2702
2703 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2704 if (unlikely(ret)) {
2705 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2706 goto err;
2707 }
2708 ath5k_hw_set_txpower_limit(sc->ah, 0);
2709
2710 ret = ath5k_rx_start(sc);
2711 if (unlikely(ret)) {
2712 ATH5K_ERR(sc, "can't start recv logic\n");
2713 goto err;
2714 }
2715 /*
2716 * We may be doing a reset in response to an ioctl
2717 * that changes the channel so update any state that
2718 * might change as a result.
2719 *
2720 * XXX needed?
2721 */
2722/* ath5k_chan_change(sc, c); */
2723 ath5k_beacon_config(sc);
2724 /* intrs are started by ath5k_beacon_config */
2725
2726 ieee80211_wake_queues(hw);
2727
2728 return 0;
2729err:
2730 return ret;
2731}
2732
2733static int ath5k_start(struct ieee80211_hw *hw)
2734{
2735 return ath5k_init(hw->priv);
2736}
2737
2738static void ath5k_stop(struct ieee80211_hw *hw)
2739{
2740 ath5k_stop_hw(hw->priv);
2741}
2742
2743static int ath5k_add_interface(struct ieee80211_hw *hw,
2744 struct ieee80211_if_init_conf *conf)
2745{
2746 struct ath5k_softc *sc = hw->priv;
2747 int ret;
2748
2749 mutex_lock(&sc->lock);
32bfd35d 2750 if (sc->vif) {
fa1c114f
JS		 2751 ret = 0;
2752 goto end;
2753 }
2754
32bfd35d 2755 sc->vif = conf->vif;
fa1c114f
JS		 2756
2757 switch (conf->type) {
2758 case IEEE80211_IF_TYPE_STA:
2759 case IEEE80211_IF_TYPE_IBSS:
2760 case IEEE80211_IF_TYPE_MNTR:
2761 sc->opmode = conf->type;
2762 break;
2763 default:
2764 ret = -EOPNOTSUPP;
2765 goto end;
2766 }
2767 ret = 0;
2768end:
2769 mutex_unlock(&sc->lock);
2770 return ret;
2771}
2772
2773static void
2774ath5k_remove_interface(struct ieee80211_hw *hw,
2775 struct ieee80211_if_init_conf *conf)
2776{
2777 struct ath5k_softc *sc = hw->priv;
2778
2779 mutex_lock(&sc->lock);
32bfd35d 2780 if (sc->vif != conf->vif)
fa1c114f
JS		 2781 goto end;
2782
32bfd35d 2783 sc->vif = NULL;
fa1c114f
JS		 2784end:
2785 mutex_unlock(&sc->lock);
2786}
2787
d8ee398d
LR		 2788/*
2789 * TODO: Phy disable/diversity etc
2790 */
fa1c114f
JS		 2791static int
2792ath5k_config(struct ieee80211_hw *hw,
2793 struct ieee80211_conf *conf)
2794{
2795 struct ath5k_softc *sc = hw->priv;
2796
e535c1ac 2797 sc->bintval = conf->beacon_int;
d8ee398d 2798 sc->power_level = conf->power_level;
fa1c114f 2799
d8ee398d 2800 return ath5k_chan_set(sc, conf->channel);
fa1c114f
JS		 2801}
2802
2803static int
32bfd35d 2804ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
fa1c114f
JS		 2805 struct ieee80211_if_conf *conf)
2806{
2807 struct ath5k_softc *sc = hw->priv;
2808 struct ath5k_hw *ah = sc->ah;
2809 int ret;
2810
2811 /* Set to a reasonable value. Note that this will
2812 * be set to mac80211's value at ath5k_config(). */
e535c1ac 2813 sc->bintval = 1000;
fa1c114f 2814 mutex_lock(&sc->lock);
32bfd35d 2815 if (sc->vif != vif) {
fa1c114f
JS		 2816 ret = -EIO;
2817 goto unlock;
2818 }
2819 if (conf->bssid) {
2820 /* Cache for later use during resets */
2821 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2822 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2823 * a clean way of letting us retrieve this yet. */
2824 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2825 }
2826 mutex_unlock(&sc->lock);
2827
2828 return ath5k_reset(hw);
2829unlock:
2830 mutex_unlock(&sc->lock);
2831 return ret;
2832}
2833
2834#define SUPPORTED_FIF_FLAGS \
2835 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2836 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2837 FIF_BCN_PRBRESP_PROMISC
2838/*
2839 * o always accept unicast, broadcast, and multicast traffic
2840 * o multicast traffic for all BSSIDs will be enabled if mac80211
2841 * says it should be
2842 * o maintain current state of phy ofdm or phy cck error reception.
2843 * If the hardware detects any of these type of errors then
2844 * ath5k_hw_get_rx_filter() will pass to us the respective
2845 * hardware filters to be able to receive these type of frames.
2846 * o probe request frames are accepted only when operating in
2847 * hostap, adhoc, or monitor modes
2848 * o enable promiscuous mode according to the interface state
2849 * o accept beacons:
2850 * - when operating in adhoc mode so the 802.11 layer creates
2851 * node table entries for peers,
2852 * - when operating in station mode for collecting rssi data when
2853 * the station is otherwise quiet, or
2854 * - when scanning
2855 */
2856static void ath5k_configure_filter(struct ieee80211_hw *hw,
2857 unsigned int changed_flags,
2858 unsigned int *new_flags,
2859 int mc_count, struct dev_mc_list *mclist)
2860{
2861 struct ath5k_softc *sc = hw->priv;
2862 struct ath5k_hw *ah = sc->ah;
2863 u32 mfilt[2], val, rfilt;
2864 u8 pos;
2865 int i;
2866
2867 mfilt[0] = 0;
2868 mfilt[1] = 0;
2869
2870 /* Only deal with supported flags */
2871 changed_flags &= SUPPORTED_FIF_FLAGS;
2872 *new_flags &= SUPPORTED_FIF_FLAGS;
2873
2874 /* If HW detects any phy or radar errors, leave those filters on.
2875 * Also, always enable Unicast, Broadcasts and Multicast
2876 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2877 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2878 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2879 AR5K_RX_FILTER_MCAST);
2880
2881 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2882 if (*new_flags & FIF_PROMISC_IN_BSS) {
2883 rfilt |= AR5K_RX_FILTER_PROM;
2884 __set_bit(ATH_STAT_PROMISC, sc->status);
2885 }
2886 else
2887 __clear_bit(ATH_STAT_PROMISC, sc->status);
2888 }
2889
2890 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2891 if (*new_flags & FIF_ALLMULTI) {
2892 mfilt[0] = ~0;
2893 mfilt[1] = ~0;
2894 } else {
2895 for (i = 0; i < mc_count; i++) {
2896 if (!mclist)
2897 break;
2898 /* calculate XOR of eight 6-bit values */
533dd1b0 2899 val = get_unaligned_le32(mclist->dmi_addr + 0);
fa1c114f 2900 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
533dd1b0 2901 val = get_unaligned_le32(mclist->dmi_addr + 3);
fa1c114f
JS		 2902 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2903 pos &= 0x3f;
2904 mfilt[pos / 32] |= (1 << (pos % 32));
2905 /* XXX: we might be able to just do this instead,
2906 * but not sure, needs testing, if we do use this we'd
2907 * neet to inform below to not reset the mcast */
2908 /* ath5k_hw_set_mcast_filterindex(ah,
2909 * mclist->dmi_addr[5]); */
2910 mclist = mclist->next;
2911 }
2912 }
2913
2914 /* This is the best we can do */
2915 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2916 rfilt |= AR5K_RX_FILTER_PHYERR;
2917
2918 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2919 * and probes for any BSSID, this needs testing */
2920 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2921 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2922
2923 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2924 * set we should only pass on control frames for this
2925 * station. This needs testing. I believe right now this
2926 * enables *all* control frames, which is OK.. but
2927 * but we should see if we can improve on granularity */
2928 if (*new_flags & FIF_CONTROL)
2929 rfilt |= AR5K_RX_FILTER_CONTROL;
2930
2931 /* Additional settings per mode -- this is per ath5k */
2932
2933 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2934
2935 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2936 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2937 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2938 if (sc->opmode != IEEE80211_IF_TYPE_STA)
2939 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2940 if (sc->opmode != IEEE80211_IF_TYPE_AP &&
2941 test_bit(ATH_STAT_PROMISC, sc->status))
2942 rfilt |= AR5K_RX_FILTER_PROM;
2943 if (sc->opmode == IEEE80211_IF_TYPE_STA ||
2944 sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2945 rfilt |= AR5K_RX_FILTER_BEACON;
2946 }
2947
2948 /* Set filters */
2949 ath5k_hw_set_rx_filter(ah,rfilt);
2950
2951 /* Set multicast bits */
2952 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2953 /* Set the cached hw filter flags, this will alter actually
2954 * be set in HW */
2955 sc->filter_flags = rfilt;
2956}
2957
2958static int
2959ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2960 const u8 *local_addr, const u8 *addr,
2961 struct ieee80211_key_conf *key)
2962{
2963 struct ath5k_softc *sc = hw->priv;
2964 int ret = 0;
2965
2966 switch(key->alg) {
2967 case ALG_WEP:
6844e63a
LR		 2968 /* XXX: fix hardware encryption, its not working. For now
2969 * allow software encryption */
2970 /* break; */
fa1c114f
JS		 2971 case ALG_TKIP:
2972 case ALG_CCMP:
2973 return -EOPNOTSUPP;
2974 default:
2975 WARN_ON(1);
2976 return -EINVAL;
2977 }
2978
2979 mutex_lock(&sc->lock);
2980
2981 switch (cmd) {
2982 case SET_KEY:
2983 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2984 if (ret) {
2985 ATH5K_ERR(sc, "can't set the key\n");
2986 goto unlock;
2987 }
2988 __set_bit(key->keyidx, sc->keymap);
2989 key->hw_key_idx = key->keyidx;
2990 break;
2991 case DISABLE_KEY:
2992 ath5k_hw_reset_key(sc->ah, key->keyidx);
2993 __clear_bit(key->keyidx, sc->keymap);
2994 break;
2995 default:
2996 ret = -EINVAL;
2997 goto unlock;
2998 }
2999
3000unlock:
3001 mutex_unlock(&sc->lock);
3002 return ret;
3003}
3004
3005static int
3006ath5k_get_stats(struct ieee80211_hw *hw,
3007 struct ieee80211_low_level_stats *stats)
3008{
3009 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 3010 struct ath5k_hw *ah = sc->ah;
3011
3012 /* Force update */
3013 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 3014
3015 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3016
3017 return 0;
3018}
3019
3020static int
3021ath5k_get_tx_stats(struct ieee80211_hw *hw,
3022 struct ieee80211_tx_queue_stats *stats)
3023{
3024 struct ath5k_softc *sc = hw->priv;
3025
3026 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3027
3028 return 0;
3029}
3030
3031static u64
3032ath5k_get_tsf(struct ieee80211_hw *hw)
3033{
3034 struct ath5k_softc *sc = hw->priv;
3035
3036 return ath5k_hw_get_tsf64(sc->ah);
3037}
3038
3039static void
3040ath5k_reset_tsf(struct ieee80211_hw *hw)
3041{
3042 struct ath5k_softc *sc = hw->priv;
3043
9804b98d
BR		 3044 /*
3045 * in IBSS mode we need to update the beacon timers too.
3046 * this will also reset the TSF if we call it with 0
3047 */
3048 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
3049 ath5k_beacon_update_timers(sc, 0);
3050 else
3051 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3052}
3053
3054static int
3055ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
3056 struct ieee80211_tx_control *ctl)
3057{
3058 struct ath5k_softc *sc = hw->priv;
3059 int ret;
3060
3061 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3062
3063 mutex_lock(&sc->lock);
3064
3065 if (sc->opmode != IEEE80211_IF_TYPE_IBSS) {
3066 ret = -EIO;
3067 goto end;
3068 }
3069
3070 ath5k_txbuf_free(sc, sc->bbuf);
3071 sc->bbuf->skb = skb;
3072 ret = ath5k_beacon_setup(sc, sc->bbuf, ctl);
3073 if (ret)
3074 sc->bbuf->skb = NULL;
3075 else
3076 ath5k_beacon_config(sc);
3077
3078end:
3079 mutex_unlock(&sc->lock);
3080 return ret;
3081}
3082
Linux kernel - Deliverables
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