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mac80211: dont use interface indices in drivers
[deliverable/linux.git] / drivers / net / wireless / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
43#include <linux/version.h>
44#include <linux/module.h>
45#include <linux/delay.h>
46#include <linux/if.h>
47#include <linux/netdevice.h>
48#include <linux/cache.h>
49#include <linux/pci.h>
50#include <linux/ethtool.h>
51#include <linux/uaccess.h>
52
53#include <net/ieee80211_radiotap.h>
54
55#include <asm/unaligned.h>
56
57#include "base.h"
58#include "reg.h"
59#include "debug.h"
60
61/* unaligned little endian access */
62#define LE_READ_2(_p) (le16_to_cpu(get_unaligned((__le16 *)(_p))))
63#define LE_READ_4(_p) (le32_to_cpu(get_unaligned((__le32 *)(_p))))
64
65enum {
66 ATH_LED_TX,
67 ATH_LED_RX,
68};
69
70static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
71
72
73/******************\
74* Internal defines *
75\******************/
76
77/* Module info */
78MODULE_AUTHOR("Jiri Slaby");
79MODULE_AUTHOR("Nick Kossifidis");
80MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
81MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
82MODULE_LICENSE("Dual BSD/GPL");
83MODULE_VERSION("0.1.1 (EXPERIMENTAL)");
84
85
86/* Known PCI ids */
87static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
88 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
89 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
90 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
91 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
92 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
93 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
94 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
96 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
103 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
104 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/
105 { PCI_VDEVICE(ATHEROS, 0x0023), .driver_data = AR5K_AR5212 }, /* 5416 */
106 { PCI_VDEVICE(ATHEROS, 0x0024), .driver_data = AR5K_AR5212 }, /* 5418 */
107 { 0 }
108};
109MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
110
111/* Known SREVs */
112static struct ath5k_srev_name srev_names[] = {
113 { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 },
114 { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 },
115 { "5311A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },
116 { "5311B", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },
117 { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 },
118 { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 },
119 { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 },
120 { "5213A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213A },
121 { "2424", AR5K_VERSION_VER, AR5K_SREV_VER_AR2424 },
122 { "5424", AR5K_VERSION_VER, AR5K_SREV_VER_AR5424 },
123 { "5413", AR5K_VERSION_VER, AR5K_SREV_VER_AR5413 },
124 { "5414", AR5K_VERSION_VER, AR5K_SREV_VER_AR5414 },
125 { "5416", AR5K_VERSION_VER, AR5K_SREV_VER_AR5416 },
126 { "5418", AR5K_VERSION_VER, AR5K_SREV_VER_AR5418 },
127 { "xxxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN },
128 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
129 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
130 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
131 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
132 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
133 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
134 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
135 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC1 },
136 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC2 },
137 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
138 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
139};
140
141/*
142 * Prototypes - PCI stack related functions
143 */
144static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
145 const struct pci_device_id *id);
146static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
147#ifdef CONFIG_PM
148static int ath5k_pci_suspend(struct pci_dev *pdev,
149 pm_message_t state);
150static int ath5k_pci_resume(struct pci_dev *pdev);
151#else
152#define ath5k_pci_suspend NULL
153#define ath5k_pci_resume NULL
154#endif /* CONFIG_PM */
155
156static struct pci_driver ath5k_pci_drv_id = {
157 .name = "ath5k_pci",
158 .id_table = ath5k_pci_id_table,
159 .probe = ath5k_pci_probe,
160 .remove = __devexit_p(ath5k_pci_remove),
161 .suspend = ath5k_pci_suspend,
162 .resume = ath5k_pci_resume,
163};
164
165
166
167/*
168 * Prototypes - MAC 802.11 stack related functions
169 */
170static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
171 struct ieee80211_tx_control *ctl);
172static int ath5k_reset(struct ieee80211_hw *hw);
173static int ath5k_start(struct ieee80211_hw *hw);
174static void ath5k_stop(struct ieee80211_hw *hw);
175static int ath5k_add_interface(struct ieee80211_hw *hw,
176 struct ieee80211_if_init_conf *conf);
177static void ath5k_remove_interface(struct ieee80211_hw *hw,
178 struct ieee80211_if_init_conf *conf);
179static int ath5k_config(struct ieee80211_hw *hw,
180 struct ieee80211_conf *conf);
32bfd35d
JB		 181static int ath5k_config_interface(struct ieee80211_hw *hw,
182 struct ieee80211_vif *vif,
fa1c114f
JS		 183 struct ieee80211_if_conf *conf);
184static void ath5k_configure_filter(struct ieee80211_hw *hw,
185 unsigned int changed_flags,
186 unsigned int *new_flags,
187 int mc_count, struct dev_mc_list *mclist);
188static int ath5k_set_key(struct ieee80211_hw *hw,
189 enum set_key_cmd cmd,
190 const u8 *local_addr, const u8 *addr,
191 struct ieee80211_key_conf *key);
192static int ath5k_get_stats(struct ieee80211_hw *hw,
193 struct ieee80211_low_level_stats *stats);
194static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
195 struct ieee80211_tx_queue_stats *stats);
196static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
197static void ath5k_reset_tsf(struct ieee80211_hw *hw);
198static int ath5k_beacon_update(struct ieee80211_hw *hw,
199 struct sk_buff *skb,
200 struct ieee80211_tx_control *ctl);
201
202static struct ieee80211_ops ath5k_hw_ops = {
203 .tx = ath5k_tx,
204 .start = ath5k_start,
205 .stop = ath5k_stop,
206 .add_interface = ath5k_add_interface,
207 .remove_interface = ath5k_remove_interface,
208 .config = ath5k_config,
209 .config_interface = ath5k_config_interface,
210 .configure_filter = ath5k_configure_filter,
211 .set_key = ath5k_set_key,
212 .get_stats = ath5k_get_stats,
213 .conf_tx = NULL,
214 .get_tx_stats = ath5k_get_tx_stats,
215 .get_tsf = ath5k_get_tsf,
216 .reset_tsf = ath5k_reset_tsf,
217 .beacon_update = ath5k_beacon_update,
218};
219
220/*
221 * Prototypes - Internal functions
222 */
223/* Attach detach */
224static int ath5k_attach(struct pci_dev *pdev,
225 struct ieee80211_hw *hw);
226static void ath5k_detach(struct pci_dev *pdev,
227 struct ieee80211_hw *hw);
228/* Channel/mode setup */
229static inline short ath5k_ieee2mhz(short chan);
230static unsigned int ath5k_copy_rates(struct ieee80211_rate *rates,
231 const struct ath5k_rate_table *rt,
232 unsigned int max);
233static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
234 struct ieee80211_channel *channels,
235 unsigned int mode,
236 unsigned int max);
237static int ath5k_getchannels(struct ieee80211_hw *hw);
238static int ath5k_chan_set(struct ath5k_softc *sc,
239 struct ieee80211_channel *chan);
240static void ath5k_setcurmode(struct ath5k_softc *sc,
241 unsigned int mode);
242static void ath5k_mode_setup(struct ath5k_softc *sc);
243/* Descriptor setup */
244static int ath5k_desc_alloc(struct ath5k_softc *sc,
245 struct pci_dev *pdev);
246static void ath5k_desc_free(struct ath5k_softc *sc,
247 struct pci_dev *pdev);
248/* Buffers setup */
249static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
250 struct ath5k_buf *bf);
251static int ath5k_txbuf_setup(struct ath5k_softc *sc,
252 struct ath5k_buf *bf,
253 struct ieee80211_tx_control *ctl);
254
255static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
256 struct ath5k_buf *bf)
257{
258 BUG_ON(!bf);
259 if (!bf->skb)
260 return;
261 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
262 PCI_DMA_TODEVICE);
263 dev_kfree_skb(bf->skb);
264 bf->skb = NULL;
265}
266
267/* Queues setup */
268static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
269 int qtype, int subtype);
270static int ath5k_beaconq_setup(struct ath5k_hw *ah);
271static int ath5k_beaconq_config(struct ath5k_softc *sc);
272static void ath5k_txq_drainq(struct ath5k_softc *sc,
273 struct ath5k_txq *txq);
274static void ath5k_txq_cleanup(struct ath5k_softc *sc);
275static void ath5k_txq_release(struct ath5k_softc *sc);
276/* Rx handling */
277static int ath5k_rx_start(struct ath5k_softc *sc);
278static void ath5k_rx_stop(struct ath5k_softc *sc);
279static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
280 struct ath5k_desc *ds,
281 struct sk_buff *skb);
282static void ath5k_tasklet_rx(unsigned long data);
283/* Tx handling */
284static void ath5k_tx_processq(struct ath5k_softc *sc,
285 struct ath5k_txq *txq);
286static void ath5k_tasklet_tx(unsigned long data);
287/* Beacon handling */
288static int ath5k_beacon_setup(struct ath5k_softc *sc,
289 struct ath5k_buf *bf,
290 struct ieee80211_tx_control *ctl);
291static void ath5k_beacon_send(struct ath5k_softc *sc);
292static void ath5k_beacon_config(struct ath5k_softc *sc);
293
294static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
295{
296 u64 tsf = ath5k_hw_get_tsf64(ah);
297
298 if ((tsf & 0x7fff) < rstamp)
299 tsf -= 0x8000;
300
301 return (tsf & ~0x7fff) | rstamp;
302}
303
304/* Interrupt handling */
305static int ath5k_init(struct ath5k_softc *sc);
306static int ath5k_stop_locked(struct ath5k_softc *sc);
307static int ath5k_stop_hw(struct ath5k_softc *sc);
308static irqreturn_t ath5k_intr(int irq, void *dev_id);
309static void ath5k_tasklet_reset(unsigned long data);
310
311static void ath5k_calibrate(unsigned long data);
312/* LED functions */
313static void ath5k_led_off(unsigned long data);
314static void ath5k_led_blink(struct ath5k_softc *sc,
315 unsigned int on,
316 unsigned int off);
317static void ath5k_led_event(struct ath5k_softc *sc,
318 int event);
319
320
321/*
322 * Module init/exit functions
323 */
324static int __init
325init_ath5k_pci(void)
326{
327 int ret;
328
329 ath5k_debug_init();
330
331 ret = pci_register_driver(&ath5k_pci_drv_id);
332 if (ret) {
333 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
334 return ret;
335 }
336
337 return 0;
338}
339
340static void __exit
341exit_ath5k_pci(void)
342{
343 pci_unregister_driver(&ath5k_pci_drv_id);
344
345 ath5k_debug_finish();
346}
347
348module_init(init_ath5k_pci);
349module_exit(exit_ath5k_pci);
350
351
352/********************\
353* PCI Initialization *
354\********************/
355
356static const char *
357ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
358{
359 const char *name = "xxxxx";
360 unsigned int i;
361
362 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
363 if (srev_names[i].sr_type != type)
364 continue;
365 if ((val & 0xff) < srev_names[i + 1].sr_val) {
366 name = srev_names[i].sr_name;
367 break;
368 }
369 }
370
371 return name;
372}
373
374static int __devinit
375ath5k_pci_probe(struct pci_dev *pdev,
376 const struct pci_device_id *id)
377{
378 void __iomem *mem;
379 struct ath5k_softc *sc;
380 struct ieee80211_hw *hw;
381 int ret;
382 u8 csz;
383
384 ret = pci_enable_device(pdev);
385 if (ret) {
386 dev_err(&pdev->dev, "can't enable device\n");
387 goto err;
388 }
389
390 /* XXX 32-bit addressing only */
391 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
392 if (ret) {
393 dev_err(&pdev->dev, "32-bit DMA not available\n");
394 goto err_dis;
395 }
396
397 /*
398 * Cache line size is used to size and align various
399 * structures used to communicate with the hardware.
400 */
401 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
402 if (csz == 0) {
403 /*
404 * Linux 2.4.18 (at least) writes the cache line size
405 * register as a 16-bit wide register which is wrong.
406 * We must have this setup properly for rx buffer
407 * DMA to work so force a reasonable value here if it
408 * comes up zero.
409 */
410 csz = L1_CACHE_BYTES / sizeof(u32);
411 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
412 }
413 /*
414 * The default setting of latency timer yields poor results,
415 * set it to the value used by other systems. It may be worth
416 * tweaking this setting more.
417 */
418 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
419
420 /* Enable bus mastering */
421 pci_set_master(pdev);
422
423 /*
424 * Disable the RETRY_TIMEOUT register (0x41) to keep
425 * PCI Tx retries from interfering with C3 CPU state.
426 */
427 pci_write_config_byte(pdev, 0x41, 0);
428
429 ret = pci_request_region(pdev, 0, "ath5k");
430 if (ret) {
431 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
432 goto err_dis;
433 }
434
435 mem = pci_iomap(pdev, 0, 0);
436 if (!mem) {
437 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
438 ret = -EIO;
439 goto err_reg;
440 }
441
442 /*
443 * Allocate hw (mac80211 main struct)
444 * and hw->priv (driver private data)
445 */
446 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
447 if (hw == NULL) {
448 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
449 ret = -ENOMEM;
450 goto err_map;
451 }
452
453 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
454
455 /* Initialize driver private data */
456 SET_IEEE80211_DEV(hw, &pdev->dev);
457 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS;
458 hw->extra_tx_headroom = 2;
459 hw->channel_change_time = 5000;
460 /* these names are misleading */
461 hw->max_rssi = -110; /* signal in dBm */
462 hw->max_noise = -110; /* noise in dBm */
463 hw->max_signal = 100; /* we will provide a percentage based on rssi */
464 sc = hw->priv;
465 sc->hw = hw;
466 sc->pdev = pdev;
467
468 ath5k_debug_init_device(sc);
469
470 /*
471 * Mark the device as detached to avoid processing
472 * interrupts until setup is complete.
473 */
474 __set_bit(ATH_STAT_INVALID, sc->status);
475
476 sc->iobase = mem; /* So we can unmap it on detach */
477 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
478 sc->opmode = IEEE80211_IF_TYPE_STA;
479 mutex_init(&sc->lock);
480 spin_lock_init(&sc->rxbuflock);
481 spin_lock_init(&sc->txbuflock);
482
483 /* Set private data */
484 pci_set_drvdata(pdev, hw);
485
486 /* Enable msi for devices that support it */
487 pci_enable_msi(pdev);
488
489 /* Setup interrupt handler */
490 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
491 if (ret) {
492 ATH5K_ERR(sc, "request_irq failed\n");
493 goto err_free;
494 }
495
496 /* Initialize device */
497 sc->ah = ath5k_hw_attach(sc, id->driver_data);
498 if (IS_ERR(sc->ah)) {
499 ret = PTR_ERR(sc->ah);
500 goto err_irq;
501 }
502
503 /* Finish private driver data initialization */
504 ret = ath5k_attach(pdev, hw);
505 if (ret)
506 goto err_ah;
507
508 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
509 ath5k_chip_name(AR5K_VERSION_VER,sc->ah->ah_mac_srev),
510 sc->ah->ah_mac_srev,
511 sc->ah->ah_phy_revision);
512
513 if(!sc->ah->ah_single_chip){
514 /* Single chip radio (!RF5111) */
515 if(sc->ah->ah_radio_5ghz_revision && !sc->ah->ah_radio_2ghz_revision) {
516 /* No 5GHz support -> report 2GHz radio */
517 if(!test_bit(MODE_IEEE80211A, sc->ah->ah_capabilities.cap_mode)){
518 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
519 ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_5ghz_revision),
520 sc->ah->ah_radio_5ghz_revision);
521 /* No 2GHz support (5110 and some 5Ghz only cards) -> report 5Ghz radio */
522 } else if(!test_bit(MODE_IEEE80211B, sc->ah->ah_capabilities.cap_mode)){
523 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
524 ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_5ghz_revision),
525 sc->ah->ah_radio_5ghz_revision);
526 /* Multiband radio */
527 } else {
528 ATH5K_INFO(sc, "RF%s multiband radio found"
529 " (0x%x)\n",
530 ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_5ghz_revision),
531 sc->ah->ah_radio_5ghz_revision);
532 }
533 }
534 /* Multi chip radio (RF5111 - RF2111) -> report both 2GHz/5GHz radios */
535 else if(sc->ah->ah_radio_5ghz_revision && sc->ah->ah_radio_2ghz_revision){
536 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
537 ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_5ghz_revision),
538 sc->ah->ah_radio_5ghz_revision);
539 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
540 ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_2ghz_revision),
541 sc->ah->ah_radio_2ghz_revision);
542 }
543 }
544
545
546 /* ready to process interrupts */
547 __clear_bit(ATH_STAT_INVALID, sc->status);
548
549 return 0;
550err_ah:
551 ath5k_hw_detach(sc->ah);
552err_irq:
553 free_irq(pdev->irq, sc);
554err_free:
555 pci_disable_msi(pdev);
556 ieee80211_free_hw(hw);
557err_map:
558 pci_iounmap(pdev, mem);
559err_reg:
560 pci_release_region(pdev, 0);
561err_dis:
562 pci_disable_device(pdev);
563err:
564 return ret;
565}
566
567static void __devexit
568ath5k_pci_remove(struct pci_dev *pdev)
569{
570 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
571 struct ath5k_softc *sc = hw->priv;
572
573 ath5k_debug_finish_device(sc);
574 ath5k_detach(pdev, hw);
575 ath5k_hw_detach(sc->ah);
576 free_irq(pdev->irq, sc);
577 pci_disable_msi(pdev);
578 pci_iounmap(pdev, sc->iobase);
579 pci_release_region(pdev, 0);
580 pci_disable_device(pdev);
581 ieee80211_free_hw(hw);
582}
583
584#ifdef CONFIG_PM
585static int
586ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
587{
588 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
589 struct ath5k_softc *sc = hw->priv;
590
591 if (test_bit(ATH_STAT_LEDSOFT, sc->status))
592 ath5k_hw_set_gpio(sc->ah, sc->led_pin, 1);
593
594 ath5k_stop_hw(sc);
595 pci_save_state(pdev);
596 pci_disable_device(pdev);
597 pci_set_power_state(pdev, PCI_D3hot);
598
599 return 0;
600}
601
602static int
603ath5k_pci_resume(struct pci_dev *pdev)
604{
605 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
606 struct ath5k_softc *sc = hw->priv;
607 int err;
608
609 err = pci_set_power_state(pdev, PCI_D0);
610 if (err)
611 return err;
612
613 err = pci_enable_device(pdev);
614 if (err)
615 return err;
616
617 pci_restore_state(pdev);
618 /*
619 * Suspend/Resume resets the PCI configuration space, so we have to
620 * re-disable the RETRY_TIMEOUT register (0x41) to keep
621 * PCI Tx retries from interfering with C3 CPU state
622 */
623 pci_write_config_byte(pdev, 0x41, 0);
624
625 ath5k_init(sc);
626 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
627 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
628 ath5k_hw_set_gpio(sc->ah, sc->led_pin, 0);
629 }
630
631 return 0;
632}
633#endif /* CONFIG_PM */
634
635
636
637/***********************\
638* Driver Initialization *
639\***********************/
640
641static int
642ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
643{
644 struct ath5k_softc *sc = hw->priv;
645 struct ath5k_hw *ah = sc->ah;
646 u8 mac[ETH_ALEN];
647 unsigned int i;
648 int ret;
649
650 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
651
652 /*
653 * Check if the MAC has multi-rate retry support.
654 * We do this by trying to setup a fake extended
655 * descriptor. MAC's that don't have support will
656 * return false w/o doing anything. MAC's that do
657 * support it will return true w/o doing anything.
658 */
659 if (ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0))
660 __set_bit(ATH_STAT_MRRETRY, sc->status);
661
662 /*
663 * Reset the key cache since some parts do not
664 * reset the contents on initial power up.
665 */
666 for (i = 0; i < AR5K_KEYCACHE_SIZE; i++)
667 ath5k_hw_reset_key(ah, i);
668
669 /*
670 * Collect the channel list. The 802.11 layer
671 * is resposible for filtering this list based
672 * on settings like the phy mode and regulatory
673 * domain restrictions.
674 */
675 ret = ath5k_getchannels(hw);
676 if (ret) {
677 ATH5K_ERR(sc, "can't get channels\n");
678 goto err;
679 }
680
681 /* NB: setup here so ath5k_rate_update is happy */
682 if (test_bit(MODE_IEEE80211A, ah->ah_modes))
683 ath5k_setcurmode(sc, MODE_IEEE80211A);
684 else
685 ath5k_setcurmode(sc, MODE_IEEE80211B);
686
687 /*
688 * Allocate tx+rx descriptors and populate the lists.
689 */
690 ret = ath5k_desc_alloc(sc, pdev);
691 if (ret) {
692 ATH5K_ERR(sc, "can't allocate descriptors\n");
693 goto err;
694 }
695
696 /*
697 * Allocate hardware transmit queues: one queue for
698 * beacon frames and one data queue for each QoS
699 * priority. Note that hw functions handle reseting
700 * these queues at the needed time.
701 */
702 ret = ath5k_beaconq_setup(ah);
703 if (ret < 0) {
704 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
705 goto err_desc;
706 }
707 sc->bhalq = ret;
708
709 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
710 if (IS_ERR(sc->txq)) {
711 ATH5K_ERR(sc, "can't setup xmit queue\n");
712 ret = PTR_ERR(sc->txq);
713 goto err_bhal;
714 }
715
716 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
717 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
718 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
719 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
720 setup_timer(&sc->led_tim, ath5k_led_off, (unsigned long)sc);
721
722 sc->led_on = 0; /* low true */
723 /*
724 * Auto-enable soft led processing for IBM cards and for
725 * 5211 minipci cards.
726 */
727 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
728 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
729 __set_bit(ATH_STAT_LEDSOFT, sc->status);
730 sc->led_pin = 0;
731 }
732 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
733 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
734 __set_bit(ATH_STAT_LEDSOFT, sc->status);
735 sc->led_pin = 0;
736 }
737 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
738 ath5k_hw_set_gpio_output(ah, sc->led_pin);
739 ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on);
740 }
741
742 ath5k_hw_get_lladdr(ah, mac);
743 SET_IEEE80211_PERM_ADDR(hw, mac);
744 /* All MAC address bits matter for ACKs */
745 memset(sc->bssidmask, 0xff, ETH_ALEN);
746 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
747
748 ret = ieee80211_register_hw(hw);
749 if (ret) {
750 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
751 goto err_queues;
752 }
753
754 return 0;
755err_queues:
756 ath5k_txq_release(sc);
757err_bhal:
758 ath5k_hw_release_tx_queue(ah, sc->bhalq);
759err_desc:
760 ath5k_desc_free(sc, pdev);
761err:
762 return ret;
763}
764
765static void
766ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
767{
768 struct ath5k_softc *sc = hw->priv;
769
770 /*
771 * NB: the order of these is important:
772 * o call the 802.11 layer before detaching ath5k_hw to
773 * insure callbacks into the driver to delete global
774 * key cache entries can be handled
775 * o reclaim the tx queue data structures after calling
776 * the 802.11 layer as we'll get called back to reclaim
777 * node state and potentially want to use them
778 * o to cleanup the tx queues the hal is called, so detach
779 * it last
780 * XXX: ??? detach ath5k_hw ???
781 * Other than that, it's straightforward...
782 */
783 ieee80211_unregister_hw(hw);
784 ath5k_desc_free(sc, pdev);
785 ath5k_txq_release(sc);
786 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
787
788 /*
789 * NB: can't reclaim these until after ieee80211_ifdetach
790 * returns because we'll get called back to reclaim node
791 * state and potentially want to use them.
792 */
793}
794
795
796
797
798/********************\
799* Channel/mode setup *
800\********************/
801
802/*
803 * Convert IEEE channel number to MHz frequency.
804 */
805static inline short
806ath5k_ieee2mhz(short chan)
807{
808 if (chan <= 14 || chan >= 27)
809 return ieee80211chan2mhz(chan);
810 else
811 return 2212 + chan * 20;
812}
813
814static unsigned int
815ath5k_copy_rates(struct ieee80211_rate *rates,
816 const struct ath5k_rate_table *rt,
817 unsigned int max)
818{
819 unsigned int i, count;
820
821 if (rt == NULL)
822 return 0;
823
824 for (i = 0, count = 0; i < rt->rate_count && max > 0; i++) {
825 if (!rt->rates[i].valid)
826 continue;
827 rates->rate = rt->rates[i].rate_kbps / 100;
828 rates->val = rt->rates[i].rate_code;
829 rates->flags = rt->rates[i].modulation;
830 rates++;
831 count++;
832 max--;
833 }
834
835 return count;
836}
837
838static unsigned int
839ath5k_copy_channels(struct ath5k_hw *ah,
840 struct ieee80211_channel *channels,
841 unsigned int mode,
842 unsigned int max)
843{
844 static const struct { unsigned int mode, mask, chan; } map[] = {
845 [MODE_IEEE80211A] = { CHANNEL_OFDM, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_A },
846 [MODE_ATHEROS_TURBO] = { CHANNEL_OFDM|CHANNEL_TURBO, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_T },
847 [MODE_IEEE80211B] = { CHANNEL_CCK, CHANNEL_CCK, CHANNEL_B },
848 [MODE_IEEE80211G] = { CHANNEL_OFDM, CHANNEL_OFDM, CHANNEL_G },
849 [MODE_ATHEROS_TURBOG] = { CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_TG },
850 };
851 static const struct ath5k_regchannel chans_2ghz[] =
852 IEEE80211_CHANNELS_2GHZ;
853 static const struct ath5k_regchannel chans_5ghz[] =
854 IEEE80211_CHANNELS_5GHZ;
855 const struct ath5k_regchannel *chans;
856 enum ath5k_regdom dmn;
857 unsigned int i, count, size, chfreq, all, f, ch;
858
859 if (!test_bit(mode, ah->ah_modes))
860 return 0;
861
862 all = ah->ah_regdomain == DMN_DEFAULT || CHAN_DEBUG == 1;
863
864 switch (mode) {
865 case MODE_IEEE80211A:
866 case MODE_ATHEROS_TURBO:
867 /* 1..220, but 2GHz frequencies are filtered by check_channel */
868 size = all ? 220 : ARRAY_SIZE(chans_5ghz);
869 chans = chans_5ghz;
870 dmn = ath5k_regdom2flag(ah->ah_regdomain,
871 IEEE80211_CHANNELS_5GHZ_MIN);
872 chfreq = CHANNEL_5GHZ;
873 break;
874 case MODE_IEEE80211B:
875 case MODE_IEEE80211G:
876 case MODE_ATHEROS_TURBOG:
877 size = all ? 26 : ARRAY_SIZE(chans_2ghz);
878 chans = chans_2ghz;
879 dmn = ath5k_regdom2flag(ah->ah_regdomain,
880 IEEE80211_CHANNELS_2GHZ_MIN);
881 chfreq = CHANNEL_2GHZ;
882 break;
883 default:
884 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
885 return 0;
886 }
887
888 for (i = 0, count = 0; i < size && max > 0; i++) {
889 ch = all ? i + 1 : chans[i].chan;
890 f = ath5k_ieee2mhz(ch);
891 /* Check if channel is supported by the chipset */
892 if (!ath5k_channel_ok(ah, f, chfreq))
893 continue;
894
895 /* Match regulation domain */
896 if (!all && !(IEEE80211_DMN(chans[i].domain) &
897 IEEE80211_DMN(dmn)))
898 continue;
899
900 if (!all && (chans[i].mode & map[mode].mask) != map[mode].mode)
901 continue;
902
903 /* Write channel and increment counter */
904 channels->chan = ch;
905 channels->freq = f;
906 channels->val = map[mode].chan;
907 channels++;
908 count++;
909 max--;
910 }
911
912 return count;
913}
914
915/* Only tries to register modes our EEPROM says it can support */
916#define REGISTER_MODE(m) do { \
917 ret = ath5k_register_mode(hw, m); \
918 if (ret) \
919 return ret; \
920} while (0) \
921
922static inline int
923ath5k_register_mode(struct ieee80211_hw *hw, u8 m)
924{
925 struct ath5k_softc *sc = hw->priv;
926 struct ieee80211_hw_mode *modes = sc->modes;
927 unsigned int i;
928 int ret;
929
930 if (!test_bit(m, sc->ah->ah_capabilities.cap_mode))
931 return 0;
932
933 for (i = 0; i < NUM_DRIVER_MODES; i++) {
934 if (modes[i].mode != m || !modes[i].num_channels)
935 continue;
936 ret = ieee80211_register_hwmode(hw, &modes[i]);
937 if (ret) {
938 ATH5K_ERR(sc, "can't register hwmode %u\n", m);
939 return ret;
940 }
941 return 0;
942 }
943 BUG();
944}
945
946static int
947ath5k_getchannels(struct ieee80211_hw *hw)
948{
949 struct ath5k_softc *sc = hw->priv;
950 struct ath5k_hw *ah = sc->ah;
951 struct ieee80211_hw_mode *modes = sc->modes;
952 unsigned int i, max_r, max_c;
953 int ret;
954
955 BUILD_BUG_ON(ARRAY_SIZE(sc->modes) < 3);
956
957 /* The order here does not matter */
958 modes[0].mode = MODE_IEEE80211G;
959 modes[1].mode = MODE_IEEE80211B;
960 modes[2].mode = MODE_IEEE80211A;
961
962 max_r = ARRAY_SIZE(sc->rates);
963 max_c = ARRAY_SIZE(sc->channels);
964
965 for (i = 0; i < NUM_DRIVER_MODES; i++) {
966 struct ieee80211_hw_mode *mode = &modes[i];
967 const struct ath5k_rate_table *hw_rates;
968
969 if (i == 0) {
970 modes[0].rates = sc->rates;
971 modes->channels = sc->channels;
972 } else {
973 struct ieee80211_hw_mode *prev_mode = &modes[i-1];
974 int prev_num_r = prev_mode->num_rates;
975 int prev_num_c = prev_mode->num_channels;
976 mode->rates = &prev_mode->rates[prev_num_r];
977 mode->channels = &prev_mode->channels[prev_num_c];
978 }
979
980 hw_rates = ath5k_hw_get_rate_table(ah, mode->mode);
981 mode->num_rates = ath5k_copy_rates(mode->rates, hw_rates,
982 max_r);
983 mode->num_channels = ath5k_copy_channels(ah, mode->channels,
984 mode->mode, max_c);
985 max_r -= mode->num_rates;
986 max_c -= mode->num_channels;
987 }
988
989 /* We try to register all modes this driver supports. We don't bother
990 * with MODE_IEEE80211B for AR5212 as MODE_IEEE80211G already accounts
991 * for that as per mac80211. Then, REGISTER_MODE() will will actually
992 * check the eeprom reading for more reliable capability information.
993 * Order matters here as per mac80211's latest preference. This will
994 * all hopefullly soon go away. */
995
996 REGISTER_MODE(MODE_IEEE80211G);
997 if (ah->ah_version != AR5K_AR5212)
998 REGISTER_MODE(MODE_IEEE80211B);
999 REGISTER_MODE(MODE_IEEE80211A);
1000
1001 ath5k_debug_dump_modes(sc, modes);
1002
1003 return ret;
1004}
1005
1006/*
1007 * Set/change channels. If the channel is really being changed,
1008 * it's done by reseting the chip. To accomplish this we must
1009 * first cleanup any pending DMA, then restart stuff after a la
1010 * ath5k_init.
1011 */
1012static int
1013ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1014{
1015 struct ath5k_hw *ah = sc->ah;
1016 int ret;
1017
1018 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "%u (%u MHz) -> %u (%u MHz)\n",
1019 sc->curchan->chan, sc->curchan->freq,
1020 chan->chan, chan->freq);
1021
1022 if (chan->freq != sc->curchan->freq || chan->val != sc->curchan->val) {
1023 /*
1024 * To switch channels clear any pending DMA operations;
1025 * wait long enough for the RX fifo to drain, reset the
1026 * hardware at the new frequency, and then re-enable
1027 * the relevant bits of the h/w.
1028 */
1029 ath5k_hw_set_intr(ah, 0); /* disable interrupts */
1030 ath5k_txq_cleanup(sc); /* clear pending tx frames */
1031 ath5k_rx_stop(sc); /* turn off frame recv */
1032 ret = ath5k_hw_reset(ah, sc->opmode, chan, true);
1033 if (ret) {
1034 ATH5K_ERR(sc, "%s: unable to reset channel %u "
1035 "(%u Mhz)\n", __func__, chan->chan, chan->freq);
1036 return ret;
1037 }
1038 sc->curchan = chan;
1039 ath5k_hw_set_txpower_limit(sc->ah, 0);
1040
1041 /*
1042 * Re-enable rx framework.
1043 */
1044 ret = ath5k_rx_start(sc);
1045 if (ret) {
1046 ATH5K_ERR(sc, "%s: unable to restart recv logic\n",
1047 __func__);
1048 return ret;
1049 }
1050
1051 /*
1052 * Change channels and update the h/w rate map
1053 * if we're switching; e.g. 11a to 11b/g.
1054 *
1055 * XXX needed?
1056 */
1057/* ath5k_chan_change(sc, chan); */
1058
1059 ath5k_beacon_config(sc);
1060 /*
1061 * Re-enable interrupts.
1062 */
1063 ath5k_hw_set_intr(ah, sc->imask);
1064 }
1065
1066 return 0;
1067}
1068
1069static void
1070ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1071{
1072 if (unlikely(test_bit(ATH_STAT_LEDSOFT, sc->status))) {
1073 /* from Atheros NDIS driver, w/ permission */
1074 static const struct {
1075 u16 rate; /* tx/rx 802.11 rate */
1076 u16 timeOn; /* LED on time (ms) */
1077 u16 timeOff; /* LED off time (ms) */
1078 } blinkrates[] = {
1079 { 108, 40, 10 },
1080 { 96, 44, 11 },
1081 { 72, 50, 13 },
1082 { 48, 57, 14 },
1083 { 36, 67, 16 },
1084 { 24, 80, 20 },
1085 { 22, 100, 25 },
1086 { 18, 133, 34 },
1087 { 12, 160, 40 },
1088 { 10, 200, 50 },
1089 { 6, 240, 58 },
1090 { 4, 267, 66 },
1091 { 2, 400, 100 },
1092 { 0, 500, 130 }
1093 };
1094 const struct ath5k_rate_table *rt =
1095 ath5k_hw_get_rate_table(sc->ah, mode);
1096 unsigned int i, j;
1097
1098 BUG_ON(rt == NULL);
1099
1100 memset(sc->hwmap, 0, sizeof(sc->hwmap));
1101 for (i = 0; i < 32; i++) {
1102 u8 ix = rt->rate_code_to_index[i];
1103 if (ix == 0xff) {
1104 sc->hwmap[i].ledon = msecs_to_jiffies(500);
1105 sc->hwmap[i].ledoff = msecs_to_jiffies(130);
1106 continue;
1107 }
1108 sc->hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
1109 if (SHPREAMBLE_FLAG(ix) || rt->rates[ix].modulation ==
1110 IEEE80211_RATE_OFDM)
1111 sc->hwmap[i].txflags |=
1112 IEEE80211_RADIOTAP_F_SHORTPRE;
1113 /* receive frames include FCS */
1114 sc->hwmap[i].rxflags = sc->hwmap[i].txflags |
1115 IEEE80211_RADIOTAP_F_FCS;
1116 /* setup blink rate table to avoid per-packet lookup */
1117 for (j = 0; j < ARRAY_SIZE(blinkrates) - 1; j++)
1118 if (blinkrates[j].rate == /* XXX why 7f? */
1119 (rt->rates[ix].dot11_rate&0x7f))
1120 break;
1121
1122 sc->hwmap[i].ledon = msecs_to_jiffies(blinkrates[j].
1123 timeOn);
1124 sc->hwmap[i].ledoff = msecs_to_jiffies(blinkrates[j].
1125 timeOff);
1126 }
1127 }
1128
1129 sc->curmode = mode;
1130}
1131
1132static void
1133ath5k_mode_setup(struct ath5k_softc *sc)
1134{
1135 struct ath5k_hw *ah = sc->ah;
1136 u32 rfilt;
1137
1138 /* configure rx filter */
1139 rfilt = sc->filter_flags;
1140 ath5k_hw_set_rx_filter(ah, rfilt);
1141
1142 if (ath5k_hw_hasbssidmask(ah))
1143 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1144
1145 /* configure operational mode */
1146 ath5k_hw_set_opmode(ah);
1147
1148 ath5k_hw_set_mcast_filter(ah, 0, 0);
1149 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1150}
1151
1152
1153
1154
1155/***************\
1156* Buffers setup *
1157\***************/
1158
1159static int
1160ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1161{
1162 struct ath5k_hw *ah = sc->ah;
1163 struct sk_buff *skb = bf->skb;
1164 struct ath5k_desc *ds;
1165
1166 if (likely(skb == NULL)) {
1167 unsigned int off;
1168
1169 /*
1170 * Allocate buffer with headroom_needed space for the
1171 * fake physical layer header at the start.
1172 */
1173 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1174 if (unlikely(skb == NULL)) {
1175 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1176 sc->rxbufsize + sc->cachelsz - 1);
1177 return -ENOMEM;
1178 }
1179 /*
1180 * Cache-line-align. This is important (for the
1181 * 5210 at least) as not doing so causes bogus data
1182 * in rx'd frames.
1183 */
1184 off = ((unsigned long)skb->data) % sc->cachelsz;
1185 if (off != 0)
1186 skb_reserve(skb, sc->cachelsz - off);
1187
1188 bf->skb = skb;
1189 bf->skbaddr = pci_map_single(sc->pdev,
1190 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1191 if (unlikely(pci_dma_mapping_error(bf->skbaddr))) {
1192 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1193 dev_kfree_skb(skb);
1194 bf->skb = NULL;
1195 return -ENOMEM;
1196 }
1197 }
1198
1199 /*
1200 * Setup descriptors. For receive we always terminate
1201 * the descriptor list with a self-linked entry so we'll
1202 * not get overrun under high load (as can happen with a
1203 * 5212 when ANI processing enables PHY error frames).
1204 *
1205 * To insure the last descriptor is self-linked we create
1206 * each descriptor as self-linked and add it to the end. As
1207 * each additional descriptor is added the previous self-linked
1208 * entry is ``fixed'' naturally. This should be safe even
1209 * if DMA is happening. When processing RX interrupts we
1210 * never remove/process the last, self-linked, entry on the
1211 * descriptor list. This insures the hardware always has
1212 * someplace to write a new frame.
1213 */
1214 ds = bf->desc;
1215 ds->ds_link = bf->daddr; /* link to self */
1216 ds->ds_data = bf->skbaddr;
1217 ath5k_hw_setup_rx_desc(ah, ds,
1218 skb_tailroom(skb), /* buffer size */
1219 0);
1220
1221 if (sc->rxlink != NULL)
1222 *sc->rxlink = bf->daddr;
1223 sc->rxlink = &ds->ds_link;
1224 return 0;
1225}
1226
1227static int
1228ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1229 struct ieee80211_tx_control *ctl)
1230{
1231 struct ath5k_hw *ah = sc->ah;
1232 struct ath5k_txq *txq = sc->txq;
1233 struct ath5k_desc *ds = bf->desc;
1234 struct sk_buff *skb = bf->skb;
1235 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1236 int ret;
1237
1238 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1239 bf->ctl = *ctl;
1240 /* XXX endianness */
1241 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1242 PCI_DMA_TODEVICE);
1243
1244 if (ctl->flags & IEEE80211_TXCTL_NO_ACK)
1245 flags |= AR5K_TXDESC_NOACK;
1246
1247 pktlen = skb->len + FCS_LEN;
1248
1249 if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT)) {
1250 keyidx = ctl->key_idx;
1251 pktlen += ctl->icv_len;
1252 }
1253
1254 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1255 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1256 (ctl->power_level * 2), ctl->tx_rate, ctl->retry_limit, keyidx, 0, flags, 0, 0);
1257 if (ret)
1258 goto err_unmap;
1259
1260 ds->ds_link = 0;
1261 ds->ds_data = bf->skbaddr;
1262
1263 spin_lock_bh(&txq->lock);
1264 list_add_tail(&bf->list, &txq->q);
1265 sc->tx_stats.data[txq->qnum].len++;
1266 if (txq->link == NULL) /* is this first packet? */
1267 ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr);
1268 else /* no, so only link it */
1269 *txq->link = bf->daddr;
1270
1271 txq->link = &ds->ds_link;
1272 ath5k_hw_tx_start(ah, txq->qnum);
1273 spin_unlock_bh(&txq->lock);
1274
1275 return 0;
1276err_unmap:
1277 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1278 return ret;
1279}
1280
1281/*******************\
1282* Descriptors setup *
1283\*******************/
1284
1285static int
1286ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1287{
1288 struct ath5k_desc *ds;
1289 struct ath5k_buf *bf;
1290 dma_addr_t da;
1291 unsigned int i;
1292 int ret;
1293
1294 /* allocate descriptors */
1295 sc->desc_len = sizeof(struct ath5k_desc) *
1296 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1297 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1298 if (sc->desc == NULL) {
1299 ATH5K_ERR(sc, "can't allocate descriptors\n");
1300 ret = -ENOMEM;
1301 goto err;
1302 }
1303 ds = sc->desc;
1304 da = sc->desc_daddr;
1305 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1306 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1307
1308 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1309 sizeof(struct ath5k_buf), GFP_KERNEL);
1310 if (bf == NULL) {
1311 ATH5K_ERR(sc, "can't allocate bufptr\n");
1312 ret = -ENOMEM;
1313 goto err_free;
1314 }
1315 sc->bufptr = bf;
1316
1317 INIT_LIST_HEAD(&sc->rxbuf);
1318 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1319 bf->desc = ds;
1320 bf->daddr = da;
1321 list_add_tail(&bf->list, &sc->rxbuf);
1322 }
1323
1324 INIT_LIST_HEAD(&sc->txbuf);
1325 sc->txbuf_len = ATH_TXBUF;
1326 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1327 da += sizeof(*ds)) {
1328 bf->desc = ds;
1329 bf->daddr = da;
1330 list_add_tail(&bf->list, &sc->txbuf);
1331 }
1332
1333 /* beacon buffer */
1334 bf->desc = ds;
1335 bf->daddr = da;
1336 sc->bbuf = bf;
1337
1338 return 0;
1339err_free:
1340 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1341err:
1342 sc->desc = NULL;
1343 return ret;
1344}
1345
1346static void
1347ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1348{
1349 struct ath5k_buf *bf;
1350
1351 ath5k_txbuf_free(sc, sc->bbuf);
1352 list_for_each_entry(bf, &sc->txbuf, list)
1353 ath5k_txbuf_free(sc, bf);
1354 list_for_each_entry(bf, &sc->rxbuf, list)
1355 ath5k_txbuf_free(sc, bf);
1356
1357 /* Free memory associated with all descriptors */
1358 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1359
1360 kfree(sc->bufptr);
1361 sc->bufptr = NULL;
1362}
1363
1364
1365
1366
1367
1368/**************\
1369* Queues setup *
1370\**************/
1371
1372static struct ath5k_txq *
1373ath5k_txq_setup(struct ath5k_softc *sc,
1374 int qtype, int subtype)
1375{
1376 struct ath5k_hw *ah = sc->ah;
1377 struct ath5k_txq *txq;
1378 struct ath5k_txq_info qi = {
1379 .tqi_subtype = subtype,
1380 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1381 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1382 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1383 };
1384 int qnum;
1385
1386 /*
1387 * Enable interrupts only for EOL and DESC conditions.
1388 * We mark tx descriptors to receive a DESC interrupt
1389 * when a tx queue gets deep; otherwise waiting for the
1390 * EOL to reap descriptors. Note that this is done to
1391 * reduce interrupt load and this only defers reaping
1392 * descriptors, never transmitting frames. Aside from
1393 * reducing interrupts this also permits more concurrency.
1394 * The only potential downside is if the tx queue backs
1395 * up in which case the top half of the kernel may backup
1396 * due to a lack of tx descriptors.
1397 */
1398 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1399 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1400 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1401 if (qnum < 0) {
1402 /*
1403 * NB: don't print a message, this happens
1404 * normally on parts with too few tx queues
1405 */
1406 return ERR_PTR(qnum);
1407 }
1408 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1409 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1410 qnum, ARRAY_SIZE(sc->txqs));
1411 ath5k_hw_release_tx_queue(ah, qnum);
1412 return ERR_PTR(-EINVAL);
1413 }
1414 txq = &sc->txqs[qnum];
1415 if (!txq->setup) {
1416 txq->qnum = qnum;
1417 txq->link = NULL;
1418 INIT_LIST_HEAD(&txq->q);
1419 spin_lock_init(&txq->lock);
1420 txq->setup = true;
1421 }
1422 return &sc->txqs[qnum];
1423}
1424
1425static int
1426ath5k_beaconq_setup(struct ath5k_hw *ah)
1427{
1428 struct ath5k_txq_info qi = {
1429 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1430 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1431 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1432 /* NB: for dynamic turbo, don't enable any other interrupts */
1433 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1434 };
1435
1436 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1437}
1438
1439static int
1440ath5k_beaconq_config(struct ath5k_softc *sc)
1441{
1442 struct ath5k_hw *ah = sc->ah;
1443 struct ath5k_txq_info qi;
1444 int ret;
1445
1446 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1447 if (ret)
1448 return ret;
1449 if (sc->opmode == IEEE80211_IF_TYPE_AP ||
1450 sc->opmode == IEEE80211_IF_TYPE_IBSS) {
1451 /*
1452 * Always burst out beacon and CAB traffic
1453 * (aifs = cwmin = cwmax = 0)
1454 */
1455 qi.tqi_aifs = 0;
1456 qi.tqi_cw_min = 0;
1457 qi.tqi_cw_max = 0;
1458 }
1459
1460 ret = ath5k_hw_setup_tx_queueprops(ah, sc->bhalq, &qi);
1461 if (ret) {
1462 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1463 "hardware queue!\n", __func__);
1464 return ret;
1465 }
1466
1467 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1468}
1469
1470static void
1471ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1472{
1473 struct ath5k_buf *bf, *bf0;
1474
1475 /*
1476 * NB: this assumes output has been stopped and
1477 * we do not need to block ath5k_tx_tasklet
1478 */
1479 spin_lock_bh(&txq->lock);
1480 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1481 ath5k_debug_printtxbuf(sc, bf, !sc->ah->ah_proc_tx_desc(sc->ah,
1482 bf->desc));
1483
1484 ath5k_txbuf_free(sc, bf);
1485
1486 spin_lock_bh(&sc->txbuflock);
1487 sc->tx_stats.data[txq->qnum].len--;
1488 list_move_tail(&bf->list, &sc->txbuf);
1489 sc->txbuf_len++;
1490 spin_unlock_bh(&sc->txbuflock);
1491 }
1492 txq->link = NULL;
1493 spin_unlock_bh(&txq->lock);
1494}
1495
1496/*
1497 * Drain the transmit queues and reclaim resources.
1498 */
1499static void
1500ath5k_txq_cleanup(struct ath5k_softc *sc)
1501{
1502 struct ath5k_hw *ah = sc->ah;
1503 unsigned int i;
1504
1505 /* XXX return value */
1506 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1507 /* don't touch the hardware if marked invalid */
1508 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1509 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1510 ath5k_hw_get_tx_buf(ah, sc->bhalq));
1511 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1512 if (sc->txqs[i].setup) {
1513 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1514 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1515 "link %p\n",
1516 sc->txqs[i].qnum,
1517 ath5k_hw_get_tx_buf(ah,
1518 sc->txqs[i].qnum),
1519 sc->txqs[i].link);
1520 }
1521 }
1522 ieee80211_start_queues(sc->hw); /* XXX move to callers */
1523
1524 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1525 if (sc->txqs[i].setup)
1526 ath5k_txq_drainq(sc, &sc->txqs[i]);
1527}
1528
1529static void
1530ath5k_txq_release(struct ath5k_softc *sc)
1531{
1532 struct ath5k_txq *txq = sc->txqs;
1533 unsigned int i;
1534
1535 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1536 if (txq->setup) {
1537 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1538 txq->setup = false;
1539 }
1540}
1541
1542
1543
1544
1545/*************\
1546* RX Handling *
1547\*************/
1548
1549/*
1550 * Enable the receive h/w following a reset.
1551 */
1552static int
1553ath5k_rx_start(struct ath5k_softc *sc)
1554{
1555 struct ath5k_hw *ah = sc->ah;
1556 struct ath5k_buf *bf;
1557 int ret;
1558
1559 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1560
1561 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1562 sc->cachelsz, sc->rxbufsize);
1563
1564 sc->rxlink = NULL;
1565
1566 spin_lock_bh(&sc->rxbuflock);
1567 list_for_each_entry(bf, &sc->rxbuf, list) {
1568 ret = ath5k_rxbuf_setup(sc, bf);
1569 if (ret != 0) {
1570 spin_unlock_bh(&sc->rxbuflock);
1571 goto err;
1572 }
1573 }
1574 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1575 spin_unlock_bh(&sc->rxbuflock);
1576
1577 ath5k_hw_put_rx_buf(ah, bf->daddr);
1578 ath5k_hw_start_rx(ah); /* enable recv descriptors */
1579 ath5k_mode_setup(sc); /* set filters, etc. */
1580 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1581
1582 return 0;
1583err:
1584 return ret;
1585}
1586
1587/*
1588 * Disable the receive h/w in preparation for a reset.
1589 */
1590static void
1591ath5k_rx_stop(struct ath5k_softc *sc)
1592{
1593 struct ath5k_hw *ah = sc->ah;
1594
1595 ath5k_hw_stop_pcu_recv(ah); /* disable PCU */
1596 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1597 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1598 mdelay(3); /* 3ms is long enough for 1 frame */
1599
1600 ath5k_debug_printrxbuffs(sc, ah);
1601
1602 sc->rxlink = NULL; /* just in case */
1603}
1604
1605static unsigned int
1606ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1607 struct sk_buff *skb)
1608{
1609 struct ieee80211_hdr *hdr = (void *)skb->data;
1610 unsigned int keyix, hlen = ieee80211_get_hdrlen_from_skb(skb);
1611
1612 if (!(ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) &&
1613 ds->ds_rxstat.rs_keyix != AR5K_RXKEYIX_INVALID)
1614 return RX_FLAG_DECRYPTED;
1615
1616 /* Apparently when a default key is used to decrypt the packet
1617 the hw does not set the index used to decrypt. In such cases
1618 get the index from the packet. */
1619 if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED) &&
1620 !(ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) &&
1621 skb->len >= hlen + 4) {
1622 keyix = skb->data[hlen + 3] >> 6;
1623
1624 if (test_bit(keyix, sc->keymap))
1625 return RX_FLAG_DECRYPTED;
1626 }
1627
1628 return 0;
1629}
1630
1631static void
1632ath5k_tasklet_rx(unsigned long data)
1633{
1634 struct ieee80211_rx_status rxs = {};
1635 struct sk_buff *skb;
1636 struct ath5k_softc *sc = (void *)data;
1637 struct ath5k_buf *bf;
1638 struct ath5k_desc *ds;
1639 u16 len;
1640 u8 stat;
1641 int ret;
1642 int hdrlen;
1643 int pad;
1644
1645 spin_lock(&sc->rxbuflock);
1646 do {
1647 if (unlikely(list_empty(&sc->rxbuf))) {
1648 ATH5K_WARN(sc, "empty rx buf pool\n");
1649 break;
1650 }
1651 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1652 BUG_ON(bf->skb == NULL);
1653 skb = bf->skb;
1654 ds = bf->desc;
1655
1656 /* TODO only one segment */
1657 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1658 sc->desc_len, PCI_DMA_FROMDEVICE);
1659
1660 if (unlikely(ds->ds_link == bf->daddr)) /* this is the end */
1661 break;
1662
1663 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds);
1664 if (unlikely(ret == -EINPROGRESS))
1665 break;
1666 else if (unlikely(ret)) {
1667 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1668 return;
1669 }
1670
1671 if (unlikely(ds->ds_rxstat.rs_more)) {
1672 ATH5K_WARN(sc, "unsupported jumbo\n");
1673 goto next;
1674 }
1675
1676 stat = ds->ds_rxstat.rs_status;
1677 if (unlikely(stat)) {
1678 if (stat & AR5K_RXERR_PHY)
1679 goto next;
1680 if (stat & AR5K_RXERR_DECRYPT) {
1681 /*
1682 * Decrypt error. If the error occurred
1683 * because there was no hardware key, then
1684 * let the frame through so the upper layers
1685 * can process it. This is necessary for 5210
1686 * parts which have no way to setup a ``clear''
1687 * key cache entry.
1688 *
1689 * XXX do key cache faulting
1690 */
1691 if (ds->ds_rxstat.rs_keyix ==
1692 AR5K_RXKEYIX_INVALID &&
1693 !(stat & AR5K_RXERR_CRC))
1694 goto accept;
1695 }
1696 if (stat & AR5K_RXERR_MIC) {
1697 rxs.flag |= RX_FLAG_MMIC_ERROR;
1698 goto accept;
1699 }
1700
1701 /* let crypto-error packets fall through in MNTR */
1702 if ((stat & ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1703 sc->opmode != IEEE80211_IF_TYPE_MNTR)
1704 goto next;
1705 }
1706accept:
1707 len = ds->ds_rxstat.rs_datalen;
1708 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, len,
1709 PCI_DMA_FROMDEVICE);
1710 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1711 PCI_DMA_FROMDEVICE);
1712 bf->skb = NULL;
1713
1714 skb_put(skb, len);
1715
1716 /*
1717 * the hardware adds a padding to 4 byte boundaries between
1718 * the header and the payload data if the header length is
1719 * not multiples of 4 - remove it
1720 */
1721 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1722 if (hdrlen & 3) {
1723 pad = hdrlen % 4;
1724 memmove(skb->data + pad, skb->data, hdrlen);
1725 skb_pull(skb, pad);
1726 }
1727
1728 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
1729 rxs.mactime = ath5k_extend_tsf(sc->ah,
1730 ds->ds_rxstat.rs_tstamp);
1731 else
1732 rxs.mactime = ds->ds_rxstat.rs_tstamp;
1733 rxs.freq = sc->curchan->freq;
1734 rxs.channel = sc->curchan->chan;
1735 rxs.phymode = sc->curmode;
1736
1737 /*
1738 * signal quality:
1739 * the names here are misleading and the usage of these
1740 * values by iwconfig makes it even worse
1741 */
1742 /* noise floor in dBm, from the last noise calibration */
1743 rxs.noise = sc->ah->ah_noise_floor;
1744 /* signal level in dBm */
1745 rxs.ssi = rxs.noise + ds->ds_rxstat.rs_rssi;
1746 /*
1747 * "signal" is actually displayed as Link Quality by iwconfig
1748 * we provide a percentage based on rssi (assuming max rssi 64)
1749 */
1750 rxs.signal = ds->ds_rxstat.rs_rssi * 100 / 64;
1751
1752 rxs.antenna = ds->ds_rxstat.rs_antenna;
1753 rxs.rate = ds->ds_rxstat.rs_rate;
1754 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb);
1755
1756 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1757
1758 __ieee80211_rx(sc->hw, skb, &rxs);
1759 sc->led_rxrate = ds->ds_rxstat.rs_rate;
1760 ath5k_led_event(sc, ATH_LED_RX);
1761next:
1762 list_move_tail(&bf->list, &sc->rxbuf);
1763 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1764 spin_unlock(&sc->rxbuflock);
1765}
1766
1767
1768
1769
1770/*************\
1771* TX Handling *
1772\*************/
1773
1774static void
1775ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1776{
1777 struct ieee80211_tx_status txs = {};
1778 struct ath5k_buf *bf, *bf0;
1779 struct ath5k_desc *ds;
1780 struct sk_buff *skb;
1781 int ret;
1782
1783 spin_lock(&txq->lock);
1784 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1785 ds = bf->desc;
1786
1787 /* TODO only one segment */
1788 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1789 sc->desc_len, PCI_DMA_FROMDEVICE);
1790 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds);
1791 if (unlikely(ret == -EINPROGRESS))
1792 break;
1793 else if (unlikely(ret)) {
1794 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1795 ret, txq->qnum);
1796 break;
1797 }
1798
1799 skb = bf->skb;
1800 bf->skb = NULL;
1801 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1802 PCI_DMA_TODEVICE);
1803
1804 txs.control = bf->ctl;
1805 txs.retry_count = ds->ds_txstat.ts_shortretry +
1806 ds->ds_txstat.ts_longretry / 6;
1807 if (unlikely(ds->ds_txstat.ts_status)) {
1808 sc->ll_stats.dot11ACKFailureCount++;
1809 if (ds->ds_txstat.ts_status & AR5K_TXERR_XRETRY)
1810 txs.excessive_retries = 1;
1811 else if (ds->ds_txstat.ts_status & AR5K_TXERR_FILT)
1812 txs.flags |= IEEE80211_TX_STATUS_TX_FILTERED;
1813 } else {
1814 txs.flags |= IEEE80211_TX_STATUS_ACK;
1815 txs.ack_signal = ds->ds_txstat.ts_rssi;
1816 }
1817
1818 ieee80211_tx_status(sc->hw, skb, &txs);
1819 sc->tx_stats.data[txq->qnum].count++;
1820
1821 spin_lock(&sc->txbuflock);
1822 sc->tx_stats.data[txq->qnum].len--;
1823 list_move_tail(&bf->list, &sc->txbuf);
1824 sc->txbuf_len++;
1825 spin_unlock(&sc->txbuflock);
1826 }
1827 if (likely(list_empty(&txq->q)))
1828 txq->link = NULL;
1829 spin_unlock(&txq->lock);
1830 if (sc->txbuf_len > ATH_TXBUF / 5)
1831 ieee80211_wake_queues(sc->hw);
1832}
1833
1834static void
1835ath5k_tasklet_tx(unsigned long data)
1836{
1837 struct ath5k_softc *sc = (void *)data;
1838
1839 ath5k_tx_processq(sc, sc->txq);
1840
1841 ath5k_led_event(sc, ATH_LED_TX);
1842}
1843
1844
1845
1846
1847/*****************\
1848* Beacon handling *
1849\*****************/
1850
1851/*
1852 * Setup the beacon frame for transmit.
1853 */
1854static int
1855ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1856 struct ieee80211_tx_control *ctl)
1857{
1858 struct sk_buff *skb = bf->skb;
1859 struct ath5k_hw *ah = sc->ah;
1860 struct ath5k_desc *ds;
1861 int ret, antenna = 0;
1862 u32 flags;
1863
1864 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1865 PCI_DMA_TODEVICE);
1866 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1867 "skbaddr %llx\n", skb, skb->data, skb->len,
1868 (unsigned long long)bf->skbaddr);
1869 if (pci_dma_mapping_error(bf->skbaddr)) {
1870 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1871 return -EIO;
1872 }
1873
1874 ds = bf->desc;
1875
1876 flags = AR5K_TXDESC_NOACK;
1877 if (sc->opmode == IEEE80211_IF_TYPE_IBSS && ath5k_hw_hasveol(ah)) {
1878 ds->ds_link = bf->daddr; /* self-linked */
1879 flags |= AR5K_TXDESC_VEOL;
1880 /*
1881 * Let hardware handle antenna switching if txantenna is not set
1882 */
1883 } else {
1884 ds->ds_link = 0;
1885 /*
1886 * Switch antenna every 4 beacons if txantenna is not set
1887 * XXX assumes two antennas
1888 */
1889 if (antenna == 0)
1890 antenna = sc->bsent & 4 ? 2 : 1;
1891 }
1892
1893 ds->ds_data = bf->skbaddr;
1894 ret = ah->ah_setup_tx_desc(ah, ds, skb->len + FCS_LEN,
1895 ieee80211_get_hdrlen_from_skb(skb),
1896 AR5K_PKT_TYPE_BEACON, (ctl->power_level * 2), ctl->tx_rate, 1,
1897 AR5K_TXKEYIX_INVALID, antenna, flags, 0, 0);
1898 if (ret)
1899 goto err_unmap;
1900
1901 return 0;
1902err_unmap:
1903 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1904 return ret;
1905}
1906
1907/*
1908 * Transmit a beacon frame at SWBA. Dynamic updates to the
1909 * frame contents are done as needed and the slot time is
1910 * also adjusted based on current state.
1911 *
1912 * this is usually called from interrupt context (ath5k_intr())
1913 * but also from ath5k_beacon_config() in IBSS mode which in turn
1914 * can be called from a tasklet and user context
1915 */
1916static void
1917ath5k_beacon_send(struct ath5k_softc *sc)
1918{
1919 struct ath5k_buf *bf = sc->bbuf;
1920 struct ath5k_hw *ah = sc->ah;
1921
1922 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON_PROC, "in beacon_send\n");
1923
1924 if (unlikely(bf->skb == NULL || sc->opmode == IEEE80211_IF_TYPE_STA ||
1925 sc->opmode == IEEE80211_IF_TYPE_MNTR)) {
1926 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1927 return;
1928 }
1929 /*
1930 * Check if the previous beacon has gone out. If
1931 * not don't don't try to post another, skip this
1932 * period and wait for the next. Missed beacons
1933 * indicate a problem and should not occur. If we
1934 * miss too many consecutive beacons reset the device.
1935 */
1936 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1937 sc->bmisscount++;
1938 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON_PROC,
1939 "missed %u consecutive beacons\n", sc->bmisscount);
1940 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
1941 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON_PROC,
1942 "stuck beacon time (%u missed)\n",
1943 sc->bmisscount);
1944 tasklet_schedule(&sc->restq);
1945 }
1946 return;
1947 }
1948 if (unlikely(sc->bmisscount != 0)) {
1949 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON_PROC,
1950 "resume beacon xmit after %u misses\n",
1951 sc->bmisscount);
1952 sc->bmisscount = 0;
1953 }
1954
1955 /*
1956 * Stop any current dma and put the new frame on the queue.
1957 * This should never fail since we check above that no frames
1958 * are still pending on the queue.
1959 */
1960 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
1961 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
1962 /* NB: hw still stops DMA, so proceed */
1963 }
1964 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, bf->skb->len,
1965 PCI_DMA_TODEVICE);
1966
1967 ath5k_hw_put_tx_buf(ah, sc->bhalq, bf->daddr);
1968 ath5k_hw_tx_start(ah, sc->bhalq);
1969 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON_PROC, "TXDP[%u] = %llx (%p)\n",
1970 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
1971
1972 sc->bsent++;
1973}
1974
1975
1976static void
1977ath5k_beacon_update_timers(struct ath5k_softc *sc)
1978{
1979 struct ath5k_hw *ah = sc->ah;
1980 u32 uninitialized_var(nexttbtt), intval, tsftu;
1981 u64 tsf;
1982
1983 intval = sc->bintval & AR5K_BEACON_PERIOD;
1984 if (WARN_ON(!intval))
1985 return;
1986
1987 /* current TSF converted to TU */
1988 tsf = ath5k_hw_get_tsf64(ah);
1989 tsftu = TSF_TO_TU(tsf);
1990
1991 /*
1992 * Pull nexttbtt forward to reflect the current
1993 * TSF. Add one intval otherwise the timespan
1994 * can be too short for ibss merges.
1995 */
1996 nexttbtt = tsftu + 2 * intval;
1997
1998 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1999 "hw tsftu %u nexttbtt %u intval %u\n", tsftu, nexttbtt, intval);
2000
2001 intval |= AR5K_BEACON_ENA;
2002
2003 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2004}
2005
2006
2007/*
2008 * Configure the beacon timers and interrupts based on the operating mode
2009 *
2010 * When operating in station mode we want to receive a BMISS interrupt when we
2011 * stop seeing beacons from the AP we've associated with so we can look for
2012 * another AP to associate with.
2013 *
2014 * In IBSS mode we need to configure the beacon timers and use a self-linked tx
2015 * descriptor if possible. If the hardware cannot deal with that we enable SWBA
2016 * interrupts to send the beacons from the interrupt handler.
2017 */
2018static void
2019ath5k_beacon_config(struct ath5k_softc *sc)
2020{
2021 struct ath5k_hw *ah = sc->ah;
2022
2023 ath5k_hw_set_intr(ah, 0);
2024 sc->bmisscount = 0;
2025
2026 if (sc->opmode == IEEE80211_IF_TYPE_STA) {
2027 sc->imask |= AR5K_INT_BMISS;
2028 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2029 /*
2030 * In IBSS mode enable the beacon timers but only enable SWBA
2031 * interrupts if we need to manually prepare beacon frames.
2032 * Otherwise we use a self-linked tx descriptor and let the
2033 * hardware deal with things. In that case we have to load it
2034 * only once here.
2035 */
2036 ath5k_beaconq_config(sc);
2037 ath5k_beacon_update_timers(sc);
2038
2039 if (!ath5k_hw_hasveol(ah))
2040 sc->imask |= AR5K_INT_SWBA;
2041 else
2042 ath5k_beacon_send(sc);
2043 }
2044 /* TODO else AP */
2045
2046 ath5k_hw_set_intr(ah, sc->imask);
2047}
2048
2049
2050/********************\
2051* Interrupt handling *
2052\********************/
2053
2054static int
2055ath5k_init(struct ath5k_softc *sc)
2056{
2057 int ret;
2058
2059 mutex_lock(&sc->lock);
2060
2061 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2062
2063 /*
2064 * Stop anything previously setup. This is safe
2065 * no matter this is the first time through or not.
2066 */
2067 ath5k_stop_locked(sc);
2068
2069 /*
2070 * The basic interface to setting the hardware in a good
2071 * state is ``reset''. On return the hardware is known to
2072 * be powered up and with interrupts disabled. This must
2073 * be followed by initialization of the appropriate bits
2074 * and then setup of the interrupt mask.
2075 */
2076 sc->curchan = sc->hw->conf.chan;
2077 ret = ath5k_hw_reset(sc->ah, sc->opmode, sc->curchan, false);
2078 if (ret) {
2079 ATH5K_ERR(sc, "unable to reset hardware: %d\n", ret);
2080 goto done;
2081 }
2082 /*
2083 * This is needed only to setup initial state
2084 * but it's best done after a reset.
2085 */
2086 ath5k_hw_set_txpower_limit(sc->ah, 0);
2087
2088 /*
2089 * Setup the hardware after reset: the key cache
2090 * is filled as needed and the receive engine is
2091 * set going. Frame transmit is handled entirely
2092 * in the frame output path; there's nothing to do
2093 * here except setup the interrupt mask.
2094 */
2095 ret = ath5k_rx_start(sc);
2096 if (ret)
2097 goto done;
2098
2099 /*
2100 * Enable interrupts.
2101 */
2102 sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
2103 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL;
2104
2105 ath5k_hw_set_intr(sc->ah, sc->imask);
2106 /* Set ack to be sent at low bit-rates */
2107 ath5k_hw_set_ack_bitrate_high(sc->ah, false);
2108
2109 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2110 msecs_to_jiffies(ath5k_calinterval * 1000)));
2111
2112 ret = 0;
2113done:
2114 mutex_unlock(&sc->lock);
2115 return ret;
2116}
2117
2118static int
2119ath5k_stop_locked(struct ath5k_softc *sc)
2120{
2121 struct ath5k_hw *ah = sc->ah;
2122
2123 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2124 test_bit(ATH_STAT_INVALID, sc->status));
2125
2126 /*
2127 * Shutdown the hardware and driver:
2128 * stop output from above
2129 * disable interrupts
2130 * turn off timers
2131 * turn off the radio
2132 * clear transmit machinery
2133 * clear receive machinery
2134 * drain and release tx queues
2135 * reclaim beacon resources
2136 * power down hardware
2137 *
2138 * Note that some of this work is not possible if the
2139 * hardware is gone (invalid).
2140 */
2141 ieee80211_stop_queues(sc->hw);
2142
2143 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2144 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2145 del_timer_sync(&sc->led_tim);
2146 ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on);
2147 __clear_bit(ATH_STAT_LEDBLINKING, sc->status);
2148 }
2149 ath5k_hw_set_intr(ah, 0);
2150 }
2151 ath5k_txq_cleanup(sc);
2152 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2153 ath5k_rx_stop(sc);
2154 ath5k_hw_phy_disable(ah);
2155 } else
2156 sc->rxlink = NULL;
2157
2158 return 0;
2159}
2160
2161/*
2162 * Stop the device, grabbing the top-level lock to protect
2163 * against concurrent entry through ath5k_init (which can happen
2164 * if another thread does a system call and the thread doing the
2165 * stop is preempted).
2166 */
2167static int
2168ath5k_stop_hw(struct ath5k_softc *sc)
2169{
2170 int ret;
2171
2172 mutex_lock(&sc->lock);
2173 ret = ath5k_stop_locked(sc);
2174 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2175 /*
2176 * Set the chip in full sleep mode. Note that we are
2177 * careful to do this only when bringing the interface
2178 * completely to a stop. When the chip is in this state
2179 * it must be carefully woken up or references to
2180 * registers in the PCI clock domain may freeze the bus
2181 * (and system). This varies by chip and is mostly an
2182 * issue with newer parts that go to sleep more quickly.
2183 */
2184 if (sc->ah->ah_mac_srev >= 0x78) {
2185 /*
2186 * XXX
2187 * don't put newer MAC revisions > 7.8 to sleep because
2188 * of the above mentioned problems
2189 */
2190 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2191 "not putting device to sleep\n");
2192 } else {
2193 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2194 "putting device to full sleep\n");
2195 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2196 }
2197 }
2198 ath5k_txbuf_free(sc, sc->bbuf);
2199 mutex_unlock(&sc->lock);
2200
2201 del_timer_sync(&sc->calib_tim);
2202
2203 return ret;
2204}
2205
2206static irqreturn_t
2207ath5k_intr(int irq, void *dev_id)
2208{
2209 struct ath5k_softc *sc = dev_id;
2210 struct ath5k_hw *ah = sc->ah;
2211 enum ath5k_int status;
2212 unsigned int counter = 1000;
2213
2214 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2215 !ath5k_hw_is_intr_pending(ah)))
2216 return IRQ_NONE;
2217
2218 do {
2219 /*
2220 * Figure out the reason(s) for the interrupt. Note
2221 * that get_isr returns a pseudo-ISR that may include
2222 * bits we haven't explicitly enabled so we mask the
2223 * value to insure we only process bits we requested.
2224 */
2225 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2226 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2227 status, sc->imask);
2228 status &= sc->imask; /* discard unasked for bits */
2229 if (unlikely(status & AR5K_INT_FATAL)) {
2230 /*
2231 * Fatal errors are unrecoverable.
2232 * Typically these are caused by DMA errors.
2233 */
2234 tasklet_schedule(&sc->restq);
2235 } else if (unlikely(status & AR5K_INT_RXORN)) {
2236 tasklet_schedule(&sc->restq);
2237 } else {
2238 if (status & AR5K_INT_SWBA) {
2239 /*
2240 * Software beacon alert--time to send a beacon.
2241 * Handle beacon transmission directly; deferring
2242 * this is too slow to meet timing constraints
2243 * under load.
2244 */
2245 ath5k_beacon_send(sc);
2246 }
2247 if (status & AR5K_INT_RXEOL) {
2248 /*
2249 * NB: the hardware should re-read the link when
2250 * RXE bit is written, but it doesn't work at
2251 * least on older hardware revs.
2252 */
2253 sc->rxlink = NULL;
2254 }
2255 if (status & AR5K_INT_TXURN) {
2256 /* bump tx trigger level */
2257 ath5k_hw_update_tx_triglevel(ah, true);
2258 }
2259 if (status & AR5K_INT_RX)
2260 tasklet_schedule(&sc->rxtq);
2261 if (status & AR5K_INT_TX)
2262 tasklet_schedule(&sc->txtq);
2263 if (status & AR5K_INT_BMISS) {
2264 }
2265 if (status & AR5K_INT_MIB) {
2266 /* TODO */
2267 }
2268 }
2269 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2270
2271 if (unlikely(!counter))
2272 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2273
2274 return IRQ_HANDLED;
2275}
2276
2277static void
2278ath5k_tasklet_reset(unsigned long data)
2279{
2280 struct ath5k_softc *sc = (void *)data;
2281
2282 ath5k_reset(sc->hw);
2283}
2284
2285/*
2286 * Periodically recalibrate the PHY to account
2287 * for temperature/environment changes.
2288 */
2289static void
2290ath5k_calibrate(unsigned long data)
2291{
2292 struct ath5k_softc *sc = (void *)data;
2293 struct ath5k_hw *ah = sc->ah;
2294
2295 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2296 sc->curchan->chan, sc->curchan->val);
2297
2298 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2299 /*
2300 * Rfgain is out of bounds, reset the chip
2301 * to load new gain values.
2302 */
2303 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2304 ath5k_reset(sc->hw);
2305 }
2306 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2307 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2308 sc->curchan->chan);
2309
2310 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2311 msecs_to_jiffies(ath5k_calinterval * 1000)));
2312}
2313
2314
2315
2316/***************\
2317* LED functions *
2318\***************/
2319
2320static void
2321ath5k_led_off(unsigned long data)
2322{
2323 struct ath5k_softc *sc = (void *)data;
2324
2325 if (test_bit(ATH_STAT_LEDENDBLINK, sc->status))
2326 __clear_bit(ATH_STAT_LEDBLINKING, sc->status);
2327 else {
2328 __set_bit(ATH_STAT_LEDENDBLINK, sc->status);
2329 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2330 mod_timer(&sc->led_tim, jiffies + sc->led_off);
2331 }
2332}
2333
2334/*
2335 * Blink the LED according to the specified on/off times.
2336 */
2337static void
2338ath5k_led_blink(struct ath5k_softc *sc, unsigned int on,
2339 unsigned int off)
2340{
2341 ATH5K_DBG(sc, ATH5K_DEBUG_LED, "on %u off %u\n", on, off);
2342 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2343 __set_bit(ATH_STAT_LEDBLINKING, sc->status);
2344 __clear_bit(ATH_STAT_LEDENDBLINK, sc->status);
2345 sc->led_off = off;
2346 mod_timer(&sc->led_tim, jiffies + on);
2347}
2348
2349static void
2350ath5k_led_event(struct ath5k_softc *sc, int event)
2351{
2352 if (likely(!test_bit(ATH_STAT_LEDSOFT, sc->status)))
2353 return;
2354 if (unlikely(test_bit(ATH_STAT_LEDBLINKING, sc->status)))
2355 return; /* don't interrupt active blink */
2356 switch (event) {
2357 case ATH_LED_TX:
2358 ath5k_led_blink(sc, sc->hwmap[sc->led_txrate].ledon,
2359 sc->hwmap[sc->led_txrate].ledoff);
2360 break;
2361 case ATH_LED_RX:
2362 ath5k_led_blink(sc, sc->hwmap[sc->led_rxrate].ledon,
2363 sc->hwmap[sc->led_rxrate].ledoff);
2364 break;
2365 }
2366}
2367
2368
2369
2370
2371/********************\
2372* Mac80211 functions *
2373\********************/
2374
2375static int
2376ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2377 struct ieee80211_tx_control *ctl)
2378{
2379 struct ath5k_softc *sc = hw->priv;
2380 struct ath5k_buf *bf;
2381 unsigned long flags;
2382 int hdrlen;
2383 int pad;
2384
2385 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2386
2387 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2388 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2389
2390 /*
2391 * the hardware expects the header padded to 4 byte boundaries
2392 * if this is not the case we add the padding after the header
2393 */
2394 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2395 if (hdrlen & 3) {
2396 pad = hdrlen % 4;
2397 if (skb_headroom(skb) < pad) {
2398 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2399 " headroom to pad %d\n", hdrlen, pad);
2400 return -1;
2401 }
2402 skb_push(skb, pad);
2403 memmove(skb->data, skb->data+pad, hdrlen);
2404 }
2405
2406 sc->led_txrate = ctl->tx_rate;
2407
2408 spin_lock_irqsave(&sc->txbuflock, flags);
2409 if (list_empty(&sc->txbuf)) {
2410 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2411 spin_unlock_irqrestore(&sc->txbuflock, flags);
2412 ieee80211_stop_queue(hw, ctl->queue);
2413 return -1;
2414 }
2415 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2416 list_del(&bf->list);
2417 sc->txbuf_len--;
2418 if (list_empty(&sc->txbuf))
2419 ieee80211_stop_queues(hw);
2420 spin_unlock_irqrestore(&sc->txbuflock, flags);
2421
2422 bf->skb = skb;
2423
2424 if (ath5k_txbuf_setup(sc, bf, ctl)) {
2425 bf->skb = NULL;
2426 spin_lock_irqsave(&sc->txbuflock, flags);
2427 list_add_tail(&bf->list, &sc->txbuf);
2428 sc->txbuf_len++;
2429 spin_unlock_irqrestore(&sc->txbuflock, flags);
2430 dev_kfree_skb_any(skb);
2431 return 0;
2432 }
2433
2434 return 0;
2435}
2436
2437static int
2438ath5k_reset(struct ieee80211_hw *hw)
2439{
2440 struct ath5k_softc *sc = hw->priv;
2441 struct ath5k_hw *ah = sc->ah;
2442 int ret;
2443
2444 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2445 /*
2446 * Convert to a hw channel description with the flags
2447 * constrained to reflect the current operating mode.
2448 */
2449 sc->curchan = hw->conf.chan;
2450
2451 ath5k_hw_set_intr(ah, 0);
2452 ath5k_txq_cleanup(sc);
2453 ath5k_rx_stop(sc);
2454
2455 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2456 if (unlikely(ret)) {
2457 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2458 goto err;
2459 }
2460 ath5k_hw_set_txpower_limit(sc->ah, 0);
2461
2462 ret = ath5k_rx_start(sc);
2463 if (unlikely(ret)) {
2464 ATH5K_ERR(sc, "can't start recv logic\n");
2465 goto err;
2466 }
2467 /*
2468 * We may be doing a reset in response to an ioctl
2469 * that changes the channel so update any state that
2470 * might change as a result.
2471 *
2472 * XXX needed?
2473 */
2474/* ath5k_chan_change(sc, c); */
2475 ath5k_beacon_config(sc);
2476 /* intrs are started by ath5k_beacon_config */
2477
2478 ieee80211_wake_queues(hw);
2479
2480 return 0;
2481err:
2482 return ret;
2483}
2484
2485static int ath5k_start(struct ieee80211_hw *hw)
2486{
2487 return ath5k_init(hw->priv);
2488}
2489
2490static void ath5k_stop(struct ieee80211_hw *hw)
2491{
2492 ath5k_stop_hw(hw->priv);
2493}
2494
2495static int ath5k_add_interface(struct ieee80211_hw *hw,
2496 struct ieee80211_if_init_conf *conf)
2497{
2498 struct ath5k_softc *sc = hw->priv;
2499 int ret;
2500
2501 mutex_lock(&sc->lock);
32bfd35d 2502 if (sc->vif) {
fa1c114f
JS		 2503 ret = 0;
2504 goto end;
2505 }
2506
32bfd35d 2507 sc->vif = conf->vif;
fa1c114f
JS		 2508
2509 switch (conf->type) {
2510 case IEEE80211_IF_TYPE_STA:
2511 case IEEE80211_IF_TYPE_IBSS:
2512 case IEEE80211_IF_TYPE_MNTR:
2513 sc->opmode = conf->type;
2514 break;
2515 default:
2516 ret = -EOPNOTSUPP;
2517 goto end;
2518 }
2519 ret = 0;
2520end:
2521 mutex_unlock(&sc->lock);
2522 return ret;
2523}
2524
2525static void
2526ath5k_remove_interface(struct ieee80211_hw *hw,
2527 struct ieee80211_if_init_conf *conf)
2528{
2529 struct ath5k_softc *sc = hw->priv;
2530
2531 mutex_lock(&sc->lock);
32bfd35d 2532 if (sc->vif != conf->vif)
fa1c114f
JS		 2533 goto end;
2534
32bfd35d 2535 sc->vif = NULL;
fa1c114f
JS		 2536end:
2537 mutex_unlock(&sc->lock);
2538}
2539
2540static int
2541ath5k_config(struct ieee80211_hw *hw,
2542 struct ieee80211_conf *conf)
2543{
2544 struct ath5k_softc *sc = hw->priv;
2545
2546 sc->bintval = conf->beacon_int * 1000 / 1024;
2547 ath5k_setcurmode(sc, conf->phymode);
2548
2549 return ath5k_chan_set(sc, conf->chan);
2550}
2551
2552static int
32bfd35d 2553ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
fa1c114f
JS		 2554 struct ieee80211_if_conf *conf)
2555{
2556 struct ath5k_softc *sc = hw->priv;
2557 struct ath5k_hw *ah = sc->ah;
2558 int ret;
2559
2560 /* Set to a reasonable value. Note that this will
2561 * be set to mac80211's value at ath5k_config(). */
2562 sc->bintval = 1000 * 1000 / 1024;
2563 mutex_lock(&sc->lock);
32bfd35d 2564 if (sc->vif != vif) {
fa1c114f
JS		 2565 ret = -EIO;
2566 goto unlock;
2567 }
2568 if (conf->bssid) {
2569 /* Cache for later use during resets */
2570 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2571 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2572 * a clean way of letting us retrieve this yet. */
2573 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2574 }
2575 mutex_unlock(&sc->lock);
2576
2577 return ath5k_reset(hw);
2578unlock:
2579 mutex_unlock(&sc->lock);
2580 return ret;
2581}
2582
2583#define SUPPORTED_FIF_FLAGS \
2584 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2585 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2586 FIF_BCN_PRBRESP_PROMISC
2587/*
2588 * o always accept unicast, broadcast, and multicast traffic
2589 * o multicast traffic for all BSSIDs will be enabled if mac80211
2590 * says it should be
2591 * o maintain current state of phy ofdm or phy cck error reception.
2592 * If the hardware detects any of these type of errors then
2593 * ath5k_hw_get_rx_filter() will pass to us the respective
2594 * hardware filters to be able to receive these type of frames.
2595 * o probe request frames are accepted only when operating in
2596 * hostap, adhoc, or monitor modes
2597 * o enable promiscuous mode according to the interface state
2598 * o accept beacons:
2599 * - when operating in adhoc mode so the 802.11 layer creates
2600 * node table entries for peers,
2601 * - when operating in station mode for collecting rssi data when
2602 * the station is otherwise quiet, or
2603 * - when scanning
2604 */
2605static void ath5k_configure_filter(struct ieee80211_hw *hw,
2606 unsigned int changed_flags,
2607 unsigned int *new_flags,
2608 int mc_count, struct dev_mc_list *mclist)
2609{
2610 struct ath5k_softc *sc = hw->priv;
2611 struct ath5k_hw *ah = sc->ah;
2612 u32 mfilt[2], val, rfilt;
2613 u8 pos;
2614 int i;
2615
2616 mfilt[0] = 0;
2617 mfilt[1] = 0;
2618
2619 /* Only deal with supported flags */
2620 changed_flags &= SUPPORTED_FIF_FLAGS;
2621 *new_flags &= SUPPORTED_FIF_FLAGS;
2622
2623 /* If HW detects any phy or radar errors, leave those filters on.
2624 * Also, always enable Unicast, Broadcasts and Multicast
2625 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2626 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2627 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2628 AR5K_RX_FILTER_MCAST);
2629
2630 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2631 if (*new_flags & FIF_PROMISC_IN_BSS) {
2632 rfilt |= AR5K_RX_FILTER_PROM;
2633 __set_bit(ATH_STAT_PROMISC, sc->status);
2634 }
2635 else
2636 __clear_bit(ATH_STAT_PROMISC, sc->status);
2637 }
2638
2639 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2640 if (*new_flags & FIF_ALLMULTI) {
2641 mfilt[0] = ~0;
2642 mfilt[1] = ~0;
2643 } else {
2644 for (i = 0; i < mc_count; i++) {
2645 if (!mclist)
2646 break;
2647 /* calculate XOR of eight 6-bit values */
2648 val = LE_READ_4(mclist->dmi_addr + 0);
2649 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2650 val = LE_READ_4(mclist->dmi_addr + 3);
2651 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2652 pos &= 0x3f;
2653 mfilt[pos / 32] |= (1 << (pos % 32));
2654 /* XXX: we might be able to just do this instead,
2655 * but not sure, needs testing, if we do use this we'd
2656 * neet to inform below to not reset the mcast */
2657 /* ath5k_hw_set_mcast_filterindex(ah,
2658 * mclist->dmi_addr[5]); */
2659 mclist = mclist->next;
2660 }
2661 }
2662
2663 /* This is the best we can do */
2664 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2665 rfilt |= AR5K_RX_FILTER_PHYERR;
2666
2667 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2668 * and probes for any BSSID, this needs testing */
2669 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2670 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2671
2672 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2673 * set we should only pass on control frames for this
2674 * station. This needs testing. I believe right now this
2675 * enables *all* control frames, which is OK.. but
2676 * but we should see if we can improve on granularity */
2677 if (*new_flags & FIF_CONTROL)
2678 rfilt |= AR5K_RX_FILTER_CONTROL;
2679
2680 /* Additional settings per mode -- this is per ath5k */
2681
2682 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2683
2684 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2685 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2686 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2687 if (sc->opmode != IEEE80211_IF_TYPE_STA)
2688 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2689 if (sc->opmode != IEEE80211_IF_TYPE_AP &&
2690 test_bit(ATH_STAT_PROMISC, sc->status))
2691 rfilt |= AR5K_RX_FILTER_PROM;
2692 if (sc->opmode == IEEE80211_IF_TYPE_STA ||
2693 sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2694 rfilt |= AR5K_RX_FILTER_BEACON;
2695 }
2696
2697 /* Set filters */
2698 ath5k_hw_set_rx_filter(ah,rfilt);
2699
2700 /* Set multicast bits */
2701 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2702 /* Set the cached hw filter flags, this will alter actually
2703 * be set in HW */
2704 sc->filter_flags = rfilt;
2705}
2706
2707static int
2708ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2709 const u8 *local_addr, const u8 *addr,
2710 struct ieee80211_key_conf *key)
2711{
2712 struct ath5k_softc *sc = hw->priv;
2713 int ret = 0;
2714
2715 switch(key->alg) {
2716 case ALG_WEP:
2717 break;
2718 case ALG_TKIP:
2719 case ALG_CCMP:
2720 return -EOPNOTSUPP;
2721 default:
2722 WARN_ON(1);
2723 return -EINVAL;
2724 }
2725
2726 mutex_lock(&sc->lock);
2727
2728 switch (cmd) {
2729 case SET_KEY:
2730 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2731 if (ret) {
2732 ATH5K_ERR(sc, "can't set the key\n");
2733 goto unlock;
2734 }
2735 __set_bit(key->keyidx, sc->keymap);
2736 key->hw_key_idx = key->keyidx;
2737 break;
2738 case DISABLE_KEY:
2739 ath5k_hw_reset_key(sc->ah, key->keyidx);
2740 __clear_bit(key->keyidx, sc->keymap);
2741 break;
2742 default:
2743 ret = -EINVAL;
2744 goto unlock;
2745 }
2746
2747unlock:
2748 mutex_unlock(&sc->lock);
2749 return ret;
2750}
2751
2752static int
2753ath5k_get_stats(struct ieee80211_hw *hw,
2754 struct ieee80211_low_level_stats *stats)
2755{
2756 struct ath5k_softc *sc = hw->priv;
2757
2758 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
2759
2760 return 0;
2761}
2762
2763static int
2764ath5k_get_tx_stats(struct ieee80211_hw *hw,
2765 struct ieee80211_tx_queue_stats *stats)
2766{
2767 struct ath5k_softc *sc = hw->priv;
2768
2769 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
2770
2771 return 0;
2772}
2773
2774static u64
2775ath5k_get_tsf(struct ieee80211_hw *hw)
2776{
2777 struct ath5k_softc *sc = hw->priv;
2778
2779 return ath5k_hw_get_tsf64(sc->ah);
2780}
2781
2782static void
2783ath5k_reset_tsf(struct ieee80211_hw *hw)
2784{
2785 struct ath5k_softc *sc = hw->priv;
2786
2787 ath5k_hw_reset_tsf(sc->ah);
2788}
2789
2790static int
2791ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
2792 struct ieee80211_tx_control *ctl)
2793{
2794 struct ath5k_softc *sc = hw->priv;
2795 int ret;
2796
2797 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
2798
2799 mutex_lock(&sc->lock);
2800
2801 if (sc->opmode != IEEE80211_IF_TYPE_IBSS) {
2802 ret = -EIO;
2803 goto end;
2804 }
2805
2806 ath5k_txbuf_free(sc, sc->bbuf);
2807 sc->bbuf->skb = skb;
2808 ret = ath5k_beacon_setup(sc, sc->bbuf, ctl);
2809 if (ret)
2810 sc->bbuf->skb = NULL;
2811 else
2812 ath5k_beacon_config(sc);
2813
2814end:
2815 mutex_unlock(&sc->lock);
2816 return ret;
2817}
2818
Linux kernel - Deliverables
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