Commit | Line | Data |
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fa1c114f JS |
1 | /*- |
2 | * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting | |
3 | * Copyright (c) 2004-2005 Atheros Communications, Inc. | |
4 | * Copyright (c) 2006 Devicescape Software, Inc. | |
5 | * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com> | |
6 | * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu> | |
7 | * | |
8 | * All rights reserved. | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or without | |
11 | * modification, are permitted provided that the following conditions | |
12 | * are met: | |
13 | * 1. Redistributions of source code must retain the above copyright | |
14 | * notice, this list of conditions and the following disclaimer, | |
15 | * without modification. | |
16 | * 2. Redistributions in binary form must reproduce at minimum a disclaimer | |
17 | * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any | |
18 | * redistribution must be conditioned upon including a substantially | |
19 | * similar Disclaimer requirement for further binary redistribution. | |
20 | * 3. Neither the names of the above-listed copyright holders nor the names | |
21 | * of any contributors may be used to endorse or promote products derived | |
22 | * from this software without specific prior written permission. | |
23 | * | |
24 | * Alternatively, this software may be distributed under the terms of the | |
25 | * GNU General Public License ("GPL") version 2 as published by the Free | |
26 | * Software Foundation. | |
27 | * | |
28 | * NO WARRANTY | |
29 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
30 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
31 | * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY | |
32 | * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL | |
33 | * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, | |
34 | * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
35 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
36 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER | |
37 | * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
38 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF | |
39 | * THE POSSIBILITY OF SUCH DAMAGES. | |
40 | * | |
41 | */ | |
42 | ||
43 | #include <linux/version.h> | |
44 | #include <linux/module.h> | |
45 | #include <linux/delay.h> | |
46 | #include <linux/if.h> | |
47 | #include <linux/netdevice.h> | |
48 | #include <linux/cache.h> | |
49 | #include <linux/pci.h> | |
50 | #include <linux/ethtool.h> | |
51 | #include <linux/uaccess.h> | |
52 | ||
53 | #include <net/ieee80211_radiotap.h> | |
54 | ||
55 | #include <asm/unaligned.h> | |
56 | ||
57 | #include "base.h" | |
58 | #include "reg.h" | |
59 | #include "debug.h" | |
60 | ||
61 | /* unaligned little endian access */ | |
62 | #define LE_READ_2(_p) (le16_to_cpu(get_unaligned((__le16 *)(_p)))) | |
63 | #define LE_READ_4(_p) (le32_to_cpu(get_unaligned((__le32 *)(_p)))) | |
64 | ||
65 | enum { | |
66 | ATH_LED_TX, | |
67 | ATH_LED_RX, | |
68 | }; | |
69 | ||
70 | static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */ | |
71 | ||
72 | ||
73 | /******************\ | |
74 | * Internal defines * | |
75 | \******************/ | |
76 | ||
77 | /* Module info */ | |
78 | MODULE_AUTHOR("Jiri Slaby"); | |
79 | MODULE_AUTHOR("Nick Kossifidis"); | |
80 | MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards."); | |
81 | MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards"); | |
82 | MODULE_LICENSE("Dual BSD/GPL"); | |
400ec45a | 83 | MODULE_VERSION("0.5.0 (EXPERIMENTAL)"); |
fa1c114f JS |
84 | |
85 | ||
86 | /* Known PCI ids */ | |
87 | static struct pci_device_id ath5k_pci_id_table[] __devinitdata = { | |
88 | { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */ | |
89 | { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */ | |
90 | { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/ | |
91 | { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */ | |
92 | { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */ | |
93 | { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */ | |
94 | { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */ | |
95 | { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */ | |
96 | { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */ | |
97 | { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */ | |
98 | { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */ | |
99 | { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */ | |
100 | { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */ | |
101 | { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */ | |
102 | { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */ | |
103 | { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */ | |
104 | { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/ | |
105 | { PCI_VDEVICE(ATHEROS, 0x0023), .driver_data = AR5K_AR5212 }, /* 5416 */ | |
106 | { PCI_VDEVICE(ATHEROS, 0x0024), .driver_data = AR5K_AR5212 }, /* 5418 */ | |
107 | { 0 } | |
108 | }; | |
109 | MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table); | |
110 | ||
111 | /* Known SREVs */ | |
112 | static struct ath5k_srev_name srev_names[] = { | |
113 | { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 }, | |
114 | { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 }, | |
115 | { "5311A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A }, | |
116 | { "5311B", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B }, | |
117 | { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 }, | |
118 | { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 }, | |
119 | { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 }, | |
120 | { "5213A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213A }, | |
121 | { "2424", AR5K_VERSION_VER, AR5K_SREV_VER_AR2424 }, | |
122 | { "5424", AR5K_VERSION_VER, AR5K_SREV_VER_AR5424 }, | |
123 | { "5413", AR5K_VERSION_VER, AR5K_SREV_VER_AR5413 }, | |
124 | { "5414", AR5K_VERSION_VER, AR5K_SREV_VER_AR5414 }, | |
125 | { "5416", AR5K_VERSION_VER, AR5K_SREV_VER_AR5416 }, | |
126 | { "5418", AR5K_VERSION_VER, AR5K_SREV_VER_AR5418 }, | |
127 | { "xxxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN }, | |
128 | { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, | |
129 | { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, | |
130 | { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, | |
131 | { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, | |
132 | { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, | |
133 | { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, | |
134 | { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, | |
135 | { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC1 }, | |
136 | { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC2 }, | |
137 | { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 }, | |
138 | { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, | |
139 | }; | |
140 | ||
141 | /* | |
142 | * Prototypes - PCI stack related functions | |
143 | */ | |
144 | static int __devinit ath5k_pci_probe(struct pci_dev *pdev, | |
145 | const struct pci_device_id *id); | |
146 | static void __devexit ath5k_pci_remove(struct pci_dev *pdev); | |
147 | #ifdef CONFIG_PM | |
148 | static int ath5k_pci_suspend(struct pci_dev *pdev, | |
149 | pm_message_t state); | |
150 | static int ath5k_pci_resume(struct pci_dev *pdev); | |
151 | #else | |
152 | #define ath5k_pci_suspend NULL | |
153 | #define ath5k_pci_resume NULL | |
154 | #endif /* CONFIG_PM */ | |
155 | ||
04a9e451 | 156 | static struct pci_driver ath5k_pci_driver = { |
fa1c114f JS |
157 | .name = "ath5k_pci", |
158 | .id_table = ath5k_pci_id_table, | |
159 | .probe = ath5k_pci_probe, | |
160 | .remove = __devexit_p(ath5k_pci_remove), | |
161 | .suspend = ath5k_pci_suspend, | |
162 | .resume = ath5k_pci_resume, | |
163 | }; | |
164 | ||
165 | ||
166 | ||
167 | /* | |
168 | * Prototypes - MAC 802.11 stack related functions | |
169 | */ | |
170 | static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb, | |
171 | struct ieee80211_tx_control *ctl); | |
172 | static int ath5k_reset(struct ieee80211_hw *hw); | |
173 | static int ath5k_start(struct ieee80211_hw *hw); | |
174 | static void ath5k_stop(struct ieee80211_hw *hw); | |
175 | static int ath5k_add_interface(struct ieee80211_hw *hw, | |
176 | struct ieee80211_if_init_conf *conf); | |
177 | static void ath5k_remove_interface(struct ieee80211_hw *hw, | |
178 | struct ieee80211_if_init_conf *conf); | |
179 | static int ath5k_config(struct ieee80211_hw *hw, | |
180 | struct ieee80211_conf *conf); | |
32bfd35d JB |
181 | static int ath5k_config_interface(struct ieee80211_hw *hw, |
182 | struct ieee80211_vif *vif, | |
fa1c114f JS |
183 | struct ieee80211_if_conf *conf); |
184 | static void ath5k_configure_filter(struct ieee80211_hw *hw, | |
185 | unsigned int changed_flags, | |
186 | unsigned int *new_flags, | |
187 | int mc_count, struct dev_mc_list *mclist); | |
188 | static int ath5k_set_key(struct ieee80211_hw *hw, | |
189 | enum set_key_cmd cmd, | |
190 | const u8 *local_addr, const u8 *addr, | |
191 | struct ieee80211_key_conf *key); | |
192 | static int ath5k_get_stats(struct ieee80211_hw *hw, | |
193 | struct ieee80211_low_level_stats *stats); | |
194 | static int ath5k_get_tx_stats(struct ieee80211_hw *hw, | |
195 | struct ieee80211_tx_queue_stats *stats); | |
196 | static u64 ath5k_get_tsf(struct ieee80211_hw *hw); | |
197 | static void ath5k_reset_tsf(struct ieee80211_hw *hw); | |
198 | static int ath5k_beacon_update(struct ieee80211_hw *hw, | |
199 | struct sk_buff *skb, | |
200 | struct ieee80211_tx_control *ctl); | |
201 | ||
202 | static struct ieee80211_ops ath5k_hw_ops = { | |
203 | .tx = ath5k_tx, | |
204 | .start = ath5k_start, | |
205 | .stop = ath5k_stop, | |
206 | .add_interface = ath5k_add_interface, | |
207 | .remove_interface = ath5k_remove_interface, | |
208 | .config = ath5k_config, | |
209 | .config_interface = ath5k_config_interface, | |
210 | .configure_filter = ath5k_configure_filter, | |
211 | .set_key = ath5k_set_key, | |
212 | .get_stats = ath5k_get_stats, | |
213 | .conf_tx = NULL, | |
214 | .get_tx_stats = ath5k_get_tx_stats, | |
215 | .get_tsf = ath5k_get_tsf, | |
216 | .reset_tsf = ath5k_reset_tsf, | |
217 | .beacon_update = ath5k_beacon_update, | |
218 | }; | |
219 | ||
220 | /* | |
221 | * Prototypes - Internal functions | |
222 | */ | |
223 | /* Attach detach */ | |
224 | static int ath5k_attach(struct pci_dev *pdev, | |
225 | struct ieee80211_hw *hw); | |
226 | static void ath5k_detach(struct pci_dev *pdev, | |
227 | struct ieee80211_hw *hw); | |
228 | /* Channel/mode setup */ | |
229 | static inline short ath5k_ieee2mhz(short chan); | |
230 | static unsigned int ath5k_copy_rates(struct ieee80211_rate *rates, | |
231 | const struct ath5k_rate_table *rt, | |
232 | unsigned int max); | |
233 | static unsigned int ath5k_copy_channels(struct ath5k_hw *ah, | |
234 | struct ieee80211_channel *channels, | |
235 | unsigned int mode, | |
236 | unsigned int max); | |
237 | static int ath5k_getchannels(struct ieee80211_hw *hw); | |
238 | static int ath5k_chan_set(struct ath5k_softc *sc, | |
239 | struct ieee80211_channel *chan); | |
240 | static void ath5k_setcurmode(struct ath5k_softc *sc, | |
241 | unsigned int mode); | |
242 | static void ath5k_mode_setup(struct ath5k_softc *sc); | |
d8ee398d LR |
243 | static void ath5k_set_total_hw_rates(struct ath5k_softc *sc); |
244 | ||
fa1c114f JS |
245 | /* Descriptor setup */ |
246 | static int ath5k_desc_alloc(struct ath5k_softc *sc, | |
247 | struct pci_dev *pdev); | |
248 | static void ath5k_desc_free(struct ath5k_softc *sc, | |
249 | struct pci_dev *pdev); | |
250 | /* Buffers setup */ | |
251 | static int ath5k_rxbuf_setup(struct ath5k_softc *sc, | |
252 | struct ath5k_buf *bf); | |
253 | static int ath5k_txbuf_setup(struct ath5k_softc *sc, | |
254 | struct ath5k_buf *bf, | |
255 | struct ieee80211_tx_control *ctl); | |
256 | ||
257 | static inline void ath5k_txbuf_free(struct ath5k_softc *sc, | |
258 | struct ath5k_buf *bf) | |
259 | { | |
260 | BUG_ON(!bf); | |
261 | if (!bf->skb) | |
262 | return; | |
263 | pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len, | |
264 | PCI_DMA_TODEVICE); | |
265 | dev_kfree_skb(bf->skb); | |
266 | bf->skb = NULL; | |
267 | } | |
268 | ||
269 | /* Queues setup */ | |
270 | static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc, | |
271 | int qtype, int subtype); | |
272 | static int ath5k_beaconq_setup(struct ath5k_hw *ah); | |
273 | static int ath5k_beaconq_config(struct ath5k_softc *sc); | |
274 | static void ath5k_txq_drainq(struct ath5k_softc *sc, | |
275 | struct ath5k_txq *txq); | |
276 | static void ath5k_txq_cleanup(struct ath5k_softc *sc); | |
277 | static void ath5k_txq_release(struct ath5k_softc *sc); | |
278 | /* Rx handling */ | |
279 | static int ath5k_rx_start(struct ath5k_softc *sc); | |
280 | static void ath5k_rx_stop(struct ath5k_softc *sc); | |
281 | static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc, | |
282 | struct ath5k_desc *ds, | |
283 | struct sk_buff *skb); | |
284 | static void ath5k_tasklet_rx(unsigned long data); | |
285 | /* Tx handling */ | |
286 | static void ath5k_tx_processq(struct ath5k_softc *sc, | |
287 | struct ath5k_txq *txq); | |
288 | static void ath5k_tasklet_tx(unsigned long data); | |
289 | /* Beacon handling */ | |
290 | static int ath5k_beacon_setup(struct ath5k_softc *sc, | |
291 | struct ath5k_buf *bf, | |
292 | struct ieee80211_tx_control *ctl); | |
293 | static void ath5k_beacon_send(struct ath5k_softc *sc); | |
294 | static void ath5k_beacon_config(struct ath5k_softc *sc); | |
9804b98d | 295 | static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf); |
fa1c114f JS |
296 | |
297 | static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp) | |
298 | { | |
299 | u64 tsf = ath5k_hw_get_tsf64(ah); | |
300 | ||
301 | if ((tsf & 0x7fff) < rstamp) | |
302 | tsf -= 0x8000; | |
303 | ||
304 | return (tsf & ~0x7fff) | rstamp; | |
305 | } | |
306 | ||
307 | /* Interrupt handling */ | |
308 | static int ath5k_init(struct ath5k_softc *sc); | |
309 | static int ath5k_stop_locked(struct ath5k_softc *sc); | |
310 | static int ath5k_stop_hw(struct ath5k_softc *sc); | |
311 | static irqreturn_t ath5k_intr(int irq, void *dev_id); | |
312 | static void ath5k_tasklet_reset(unsigned long data); | |
313 | ||
314 | static void ath5k_calibrate(unsigned long data); | |
315 | /* LED functions */ | |
316 | static void ath5k_led_off(unsigned long data); | |
317 | static void ath5k_led_blink(struct ath5k_softc *sc, | |
318 | unsigned int on, | |
319 | unsigned int off); | |
320 | static void ath5k_led_event(struct ath5k_softc *sc, | |
321 | int event); | |
322 | ||
323 | ||
324 | /* | |
325 | * Module init/exit functions | |
326 | */ | |
327 | static int __init | |
328 | init_ath5k_pci(void) | |
329 | { | |
330 | int ret; | |
331 | ||
332 | ath5k_debug_init(); | |
333 | ||
04a9e451 | 334 | ret = pci_register_driver(&ath5k_pci_driver); |
fa1c114f JS |
335 | if (ret) { |
336 | printk(KERN_ERR "ath5k_pci: can't register pci driver\n"); | |
337 | return ret; | |
338 | } | |
339 | ||
340 | return 0; | |
341 | } | |
342 | ||
343 | static void __exit | |
344 | exit_ath5k_pci(void) | |
345 | { | |
04a9e451 | 346 | pci_unregister_driver(&ath5k_pci_driver); |
fa1c114f JS |
347 | |
348 | ath5k_debug_finish(); | |
349 | } | |
350 | ||
351 | module_init(init_ath5k_pci); | |
352 | module_exit(exit_ath5k_pci); | |
353 | ||
354 | ||
355 | /********************\ | |
356 | * PCI Initialization * | |
357 | \********************/ | |
358 | ||
359 | static const char * | |
360 | ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val) | |
361 | { | |
362 | const char *name = "xxxxx"; | |
363 | unsigned int i; | |
364 | ||
365 | for (i = 0; i < ARRAY_SIZE(srev_names); i++) { | |
366 | if (srev_names[i].sr_type != type) | |
367 | continue; | |
368 | if ((val & 0xff) < srev_names[i + 1].sr_val) { | |
369 | name = srev_names[i].sr_name; | |
370 | break; | |
371 | } | |
372 | } | |
373 | ||
374 | return name; | |
375 | } | |
376 | ||
377 | static int __devinit | |
378 | ath5k_pci_probe(struct pci_dev *pdev, | |
379 | const struct pci_device_id *id) | |
380 | { | |
381 | void __iomem *mem; | |
382 | struct ath5k_softc *sc; | |
383 | struct ieee80211_hw *hw; | |
384 | int ret; | |
385 | u8 csz; | |
386 | ||
387 | ret = pci_enable_device(pdev); | |
388 | if (ret) { | |
389 | dev_err(&pdev->dev, "can't enable device\n"); | |
390 | goto err; | |
391 | } | |
392 | ||
393 | /* XXX 32-bit addressing only */ | |
394 | ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
395 | if (ret) { | |
396 | dev_err(&pdev->dev, "32-bit DMA not available\n"); | |
397 | goto err_dis; | |
398 | } | |
399 | ||
400 | /* | |
401 | * Cache line size is used to size and align various | |
402 | * structures used to communicate with the hardware. | |
403 | */ | |
404 | pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); | |
405 | if (csz == 0) { | |
406 | /* | |
407 | * Linux 2.4.18 (at least) writes the cache line size | |
408 | * register as a 16-bit wide register which is wrong. | |
409 | * We must have this setup properly for rx buffer | |
410 | * DMA to work so force a reasonable value here if it | |
411 | * comes up zero. | |
412 | */ | |
413 | csz = L1_CACHE_BYTES / sizeof(u32); | |
414 | pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); | |
415 | } | |
416 | /* | |
417 | * The default setting of latency timer yields poor results, | |
418 | * set it to the value used by other systems. It may be worth | |
419 | * tweaking this setting more. | |
420 | */ | |
421 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); | |
422 | ||
423 | /* Enable bus mastering */ | |
424 | pci_set_master(pdev); | |
425 | ||
426 | /* | |
427 | * Disable the RETRY_TIMEOUT register (0x41) to keep | |
428 | * PCI Tx retries from interfering with C3 CPU state. | |
429 | */ | |
430 | pci_write_config_byte(pdev, 0x41, 0); | |
431 | ||
432 | ret = pci_request_region(pdev, 0, "ath5k"); | |
433 | if (ret) { | |
434 | dev_err(&pdev->dev, "cannot reserve PCI memory region\n"); | |
435 | goto err_dis; | |
436 | } | |
437 | ||
438 | mem = pci_iomap(pdev, 0, 0); | |
439 | if (!mem) { | |
440 | dev_err(&pdev->dev, "cannot remap PCI memory region\n") ; | |
441 | ret = -EIO; | |
442 | goto err_reg; | |
443 | } | |
444 | ||
445 | /* | |
446 | * Allocate hw (mac80211 main struct) | |
447 | * and hw->priv (driver private data) | |
448 | */ | |
449 | hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops); | |
450 | if (hw == NULL) { | |
451 | dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n"); | |
452 | ret = -ENOMEM; | |
453 | goto err_map; | |
454 | } | |
455 | ||
456 | dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy)); | |
457 | ||
458 | /* Initialize driver private data */ | |
459 | SET_IEEE80211_DEV(hw, &pdev->dev); | |
460 | hw->flags = IEEE80211_HW_RX_INCLUDES_FCS; | |
461 | hw->extra_tx_headroom = 2; | |
462 | hw->channel_change_time = 5000; | |
463 | /* these names are misleading */ | |
464 | hw->max_rssi = -110; /* signal in dBm */ | |
465 | hw->max_noise = -110; /* noise in dBm */ | |
466 | hw->max_signal = 100; /* we will provide a percentage based on rssi */ | |
467 | sc = hw->priv; | |
468 | sc->hw = hw; | |
469 | sc->pdev = pdev; | |
470 | ||
471 | ath5k_debug_init_device(sc); | |
472 | ||
473 | /* | |
474 | * Mark the device as detached to avoid processing | |
475 | * interrupts until setup is complete. | |
476 | */ | |
477 | __set_bit(ATH_STAT_INVALID, sc->status); | |
478 | ||
479 | sc->iobase = mem; /* So we can unmap it on detach */ | |
480 | sc->cachelsz = csz * sizeof(u32); /* convert to bytes */ | |
481 | sc->opmode = IEEE80211_IF_TYPE_STA; | |
482 | mutex_init(&sc->lock); | |
483 | spin_lock_init(&sc->rxbuflock); | |
484 | spin_lock_init(&sc->txbuflock); | |
485 | ||
486 | /* Set private data */ | |
487 | pci_set_drvdata(pdev, hw); | |
488 | ||
489 | /* Enable msi for devices that support it */ | |
490 | pci_enable_msi(pdev); | |
491 | ||
492 | /* Setup interrupt handler */ | |
493 | ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc); | |
494 | if (ret) { | |
495 | ATH5K_ERR(sc, "request_irq failed\n"); | |
496 | goto err_free; | |
497 | } | |
498 | ||
499 | /* Initialize device */ | |
500 | sc->ah = ath5k_hw_attach(sc, id->driver_data); | |
501 | if (IS_ERR(sc->ah)) { | |
502 | ret = PTR_ERR(sc->ah); | |
503 | goto err_irq; | |
504 | } | |
505 | ||
506 | /* Finish private driver data initialization */ | |
507 | ret = ath5k_attach(pdev, hw); | |
508 | if (ret) | |
509 | goto err_ah; | |
510 | ||
511 | ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n", | |
512 | ath5k_chip_name(AR5K_VERSION_VER,sc->ah->ah_mac_srev), | |
513 | sc->ah->ah_mac_srev, | |
514 | sc->ah->ah_phy_revision); | |
515 | ||
400ec45a | 516 | if (!sc->ah->ah_single_chip) { |
fa1c114f | 517 | /* Single chip radio (!RF5111) */ |
400ec45a LR |
518 | if (sc->ah->ah_radio_5ghz_revision && |
519 | !sc->ah->ah_radio_2ghz_revision) { | |
fa1c114f | 520 | /* No 5GHz support -> report 2GHz radio */ |
400ec45a LR |
521 | if (!test_bit(AR5K_MODE_11A, |
522 | sc->ah->ah_capabilities.cap_mode)) { | |
fa1c114f | 523 | ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n", |
400ec45a LR |
524 | ath5k_chip_name(AR5K_VERSION_RAD, |
525 | sc->ah->ah_radio_5ghz_revision), | |
526 | sc->ah->ah_radio_5ghz_revision); | |
527 | /* No 2GHz support (5110 and some | |
528 | * 5Ghz only cards) -> report 5Ghz radio */ | |
529 | } else if (!test_bit(AR5K_MODE_11B, | |
530 | sc->ah->ah_capabilities.cap_mode)) { | |
fa1c114f | 531 | ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n", |
400ec45a LR |
532 | ath5k_chip_name(AR5K_VERSION_RAD, |
533 | sc->ah->ah_radio_5ghz_revision), | |
534 | sc->ah->ah_radio_5ghz_revision); | |
fa1c114f JS |
535 | /* Multiband radio */ |
536 | } else { | |
537 | ATH5K_INFO(sc, "RF%s multiband radio found" | |
538 | " (0x%x)\n", | |
400ec45a LR |
539 | ath5k_chip_name(AR5K_VERSION_RAD, |
540 | sc->ah->ah_radio_5ghz_revision), | |
541 | sc->ah->ah_radio_5ghz_revision); | |
fa1c114f JS |
542 | } |
543 | } | |
400ec45a LR |
544 | /* Multi chip radio (RF5111 - RF2111) -> |
545 | * report both 2GHz/5GHz radios */ | |
546 | else if (sc->ah->ah_radio_5ghz_revision && | |
547 | sc->ah->ah_radio_2ghz_revision){ | |
fa1c114f | 548 | ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n", |
400ec45a LR |
549 | ath5k_chip_name(AR5K_VERSION_RAD, |
550 | sc->ah->ah_radio_5ghz_revision), | |
551 | sc->ah->ah_radio_5ghz_revision); | |
fa1c114f | 552 | ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n", |
400ec45a LR |
553 | ath5k_chip_name(AR5K_VERSION_RAD, |
554 | sc->ah->ah_radio_2ghz_revision), | |
555 | sc->ah->ah_radio_2ghz_revision); | |
fa1c114f JS |
556 | } |
557 | } | |
558 | ||
559 | ||
560 | /* ready to process interrupts */ | |
561 | __clear_bit(ATH_STAT_INVALID, sc->status); | |
562 | ||
563 | return 0; | |
564 | err_ah: | |
565 | ath5k_hw_detach(sc->ah); | |
566 | err_irq: | |
567 | free_irq(pdev->irq, sc); | |
568 | err_free: | |
569 | pci_disable_msi(pdev); | |
570 | ieee80211_free_hw(hw); | |
571 | err_map: | |
572 | pci_iounmap(pdev, mem); | |
573 | err_reg: | |
574 | pci_release_region(pdev, 0); | |
575 | err_dis: | |
576 | pci_disable_device(pdev); | |
577 | err: | |
578 | return ret; | |
579 | } | |
580 | ||
581 | static void __devexit | |
582 | ath5k_pci_remove(struct pci_dev *pdev) | |
583 | { | |
584 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); | |
585 | struct ath5k_softc *sc = hw->priv; | |
586 | ||
587 | ath5k_debug_finish_device(sc); | |
588 | ath5k_detach(pdev, hw); | |
589 | ath5k_hw_detach(sc->ah); | |
590 | free_irq(pdev->irq, sc); | |
591 | pci_disable_msi(pdev); | |
592 | pci_iounmap(pdev, sc->iobase); | |
593 | pci_release_region(pdev, 0); | |
594 | pci_disable_device(pdev); | |
595 | ieee80211_free_hw(hw); | |
596 | } | |
597 | ||
598 | #ifdef CONFIG_PM | |
599 | static int | |
600 | ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state) | |
601 | { | |
602 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); | |
603 | struct ath5k_softc *sc = hw->priv; | |
604 | ||
605 | if (test_bit(ATH_STAT_LEDSOFT, sc->status)) | |
606 | ath5k_hw_set_gpio(sc->ah, sc->led_pin, 1); | |
607 | ||
608 | ath5k_stop_hw(sc); | |
609 | pci_save_state(pdev); | |
610 | pci_disable_device(pdev); | |
611 | pci_set_power_state(pdev, PCI_D3hot); | |
612 | ||
613 | return 0; | |
614 | } | |
615 | ||
616 | static int | |
617 | ath5k_pci_resume(struct pci_dev *pdev) | |
618 | { | |
619 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); | |
620 | struct ath5k_softc *sc = hw->priv; | |
247ae449 JL |
621 | struct ath5k_hw *ah = sc->ah; |
622 | int i, err; | |
fa1c114f JS |
623 | |
624 | err = pci_set_power_state(pdev, PCI_D0); | |
625 | if (err) | |
626 | return err; | |
627 | ||
628 | err = pci_enable_device(pdev); | |
629 | if (err) | |
630 | return err; | |
631 | ||
632 | pci_restore_state(pdev); | |
633 | /* | |
634 | * Suspend/Resume resets the PCI configuration space, so we have to | |
635 | * re-disable the RETRY_TIMEOUT register (0x41) to keep | |
636 | * PCI Tx retries from interfering with C3 CPU state | |
637 | */ | |
638 | pci_write_config_byte(pdev, 0x41, 0); | |
639 | ||
640 | ath5k_init(sc); | |
641 | if (test_bit(ATH_STAT_LEDSOFT, sc->status)) { | |
247ae449 JL |
642 | ath5k_hw_set_gpio_output(ah, sc->led_pin); |
643 | ath5k_hw_set_gpio(ah, sc->led_pin, 0); | |
fa1c114f JS |
644 | } |
645 | ||
247ae449 JL |
646 | /* |
647 | * Reset the key cache since some parts do not | |
648 | * reset the contents on initial power up or resume. | |
649 | * | |
650 | * FIXME: This may need to be revisited when mac80211 becomes | |
651 | * aware of suspend/resume. | |
652 | */ | |
653 | for (i = 0; i < AR5K_KEYTABLE_SIZE; i++) | |
654 | ath5k_hw_reset_key(ah, i); | |
655 | ||
fa1c114f JS |
656 | return 0; |
657 | } | |
658 | #endif /* CONFIG_PM */ | |
659 | ||
660 | ||
661 | ||
662 | /***********************\ | |
663 | * Driver Initialization * | |
664 | \***********************/ | |
665 | ||
666 | static int | |
667 | ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) | |
668 | { | |
669 | struct ath5k_softc *sc = hw->priv; | |
670 | struct ath5k_hw *ah = sc->ah; | |
671 | u8 mac[ETH_ALEN]; | |
672 | unsigned int i; | |
673 | int ret; | |
674 | ||
675 | ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device); | |
676 | ||
677 | /* | |
678 | * Check if the MAC has multi-rate retry support. | |
679 | * We do this by trying to setup a fake extended | |
680 | * descriptor. MAC's that don't have support will | |
681 | * return false w/o doing anything. MAC's that do | |
682 | * support it will return true w/o doing anything. | |
683 | */ | |
b9887638 JS |
684 | ret = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0); |
685 | if (ret < 0) | |
686 | goto err; | |
687 | if (ret > 0) | |
fa1c114f JS |
688 | __set_bit(ATH_STAT_MRRETRY, sc->status); |
689 | ||
690 | /* | |
691 | * Reset the key cache since some parts do not | |
692 | * reset the contents on initial power up. | |
693 | */ | |
c65638a7 | 694 | for (i = 0; i < AR5K_KEYTABLE_SIZE; i++) |
fa1c114f JS |
695 | ath5k_hw_reset_key(ah, i); |
696 | ||
697 | /* | |
698 | * Collect the channel list. The 802.11 layer | |
699 | * is resposible for filtering this list based | |
700 | * on settings like the phy mode and regulatory | |
701 | * domain restrictions. | |
702 | */ | |
703 | ret = ath5k_getchannels(hw); | |
704 | if (ret) { | |
705 | ATH5K_ERR(sc, "can't get channels\n"); | |
706 | goto err; | |
707 | } | |
708 | ||
d8ee398d LR |
709 | /* Set *_rates so we can map hw rate index */ |
710 | ath5k_set_total_hw_rates(sc); | |
711 | ||
fa1c114f | 712 | /* NB: setup here so ath5k_rate_update is happy */ |
d8ee398d LR |
713 | if (test_bit(AR5K_MODE_11A, ah->ah_modes)) |
714 | ath5k_setcurmode(sc, AR5K_MODE_11A); | |
fa1c114f | 715 | else |
d8ee398d | 716 | ath5k_setcurmode(sc, AR5K_MODE_11B); |
fa1c114f JS |
717 | |
718 | /* | |
719 | * Allocate tx+rx descriptors and populate the lists. | |
720 | */ | |
721 | ret = ath5k_desc_alloc(sc, pdev); | |
722 | if (ret) { | |
723 | ATH5K_ERR(sc, "can't allocate descriptors\n"); | |
724 | goto err; | |
725 | } | |
726 | ||
727 | /* | |
728 | * Allocate hardware transmit queues: one queue for | |
729 | * beacon frames and one data queue for each QoS | |
730 | * priority. Note that hw functions handle reseting | |
731 | * these queues at the needed time. | |
732 | */ | |
733 | ret = ath5k_beaconq_setup(ah); | |
734 | if (ret < 0) { | |
735 | ATH5K_ERR(sc, "can't setup a beacon xmit queue\n"); | |
736 | goto err_desc; | |
737 | } | |
738 | sc->bhalq = ret; | |
739 | ||
740 | sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); | |
741 | if (IS_ERR(sc->txq)) { | |
742 | ATH5K_ERR(sc, "can't setup xmit queue\n"); | |
743 | ret = PTR_ERR(sc->txq); | |
744 | goto err_bhal; | |
745 | } | |
746 | ||
747 | tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc); | |
748 | tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc); | |
749 | tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc); | |
750 | setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc); | |
751 | setup_timer(&sc->led_tim, ath5k_led_off, (unsigned long)sc); | |
752 | ||
753 | sc->led_on = 0; /* low true */ | |
754 | /* | |
755 | * Auto-enable soft led processing for IBM cards and for | |
756 | * 5211 minipci cards. | |
757 | */ | |
758 | if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM || | |
759 | pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) { | |
760 | __set_bit(ATH_STAT_LEDSOFT, sc->status); | |
761 | sc->led_pin = 0; | |
762 | } | |
763 | /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */ | |
764 | if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) { | |
765 | __set_bit(ATH_STAT_LEDSOFT, sc->status); | |
766 | sc->led_pin = 0; | |
767 | } | |
768 | if (test_bit(ATH_STAT_LEDSOFT, sc->status)) { | |
769 | ath5k_hw_set_gpio_output(ah, sc->led_pin); | |
770 | ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on); | |
771 | } | |
772 | ||
773 | ath5k_hw_get_lladdr(ah, mac); | |
774 | SET_IEEE80211_PERM_ADDR(hw, mac); | |
775 | /* All MAC address bits matter for ACKs */ | |
776 | memset(sc->bssidmask, 0xff, ETH_ALEN); | |
777 | ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask); | |
778 | ||
779 | ret = ieee80211_register_hw(hw); | |
780 | if (ret) { | |
781 | ATH5K_ERR(sc, "can't register ieee80211 hw\n"); | |
782 | goto err_queues; | |
783 | } | |
784 | ||
785 | return 0; | |
786 | err_queues: | |
787 | ath5k_txq_release(sc); | |
788 | err_bhal: | |
789 | ath5k_hw_release_tx_queue(ah, sc->bhalq); | |
790 | err_desc: | |
791 | ath5k_desc_free(sc, pdev); | |
792 | err: | |
793 | return ret; | |
794 | } | |
795 | ||
796 | static void | |
797 | ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw) | |
798 | { | |
799 | struct ath5k_softc *sc = hw->priv; | |
800 | ||
801 | /* | |
802 | * NB: the order of these is important: | |
803 | * o call the 802.11 layer before detaching ath5k_hw to | |
804 | * insure callbacks into the driver to delete global | |
805 | * key cache entries can be handled | |
806 | * o reclaim the tx queue data structures after calling | |
807 | * the 802.11 layer as we'll get called back to reclaim | |
808 | * node state and potentially want to use them | |
809 | * o to cleanup the tx queues the hal is called, so detach | |
810 | * it last | |
811 | * XXX: ??? detach ath5k_hw ??? | |
812 | * Other than that, it's straightforward... | |
813 | */ | |
814 | ieee80211_unregister_hw(hw); | |
815 | ath5k_desc_free(sc, pdev); | |
816 | ath5k_txq_release(sc); | |
817 | ath5k_hw_release_tx_queue(sc->ah, sc->bhalq); | |
818 | ||
819 | /* | |
820 | * NB: can't reclaim these until after ieee80211_ifdetach | |
821 | * returns because we'll get called back to reclaim node | |
822 | * state and potentially want to use them. | |
823 | */ | |
824 | } | |
825 | ||
826 | ||
827 | ||
828 | ||
829 | /********************\ | |
830 | * Channel/mode setup * | |
831 | \********************/ | |
832 | ||
833 | /* | |
834 | * Convert IEEE channel number to MHz frequency. | |
835 | */ | |
836 | static inline short | |
837 | ath5k_ieee2mhz(short chan) | |
838 | { | |
839 | if (chan <= 14 || chan >= 27) | |
840 | return ieee80211chan2mhz(chan); | |
841 | else | |
842 | return 2212 + chan * 20; | |
843 | } | |
844 | ||
845 | static unsigned int | |
846 | ath5k_copy_rates(struct ieee80211_rate *rates, | |
847 | const struct ath5k_rate_table *rt, | |
848 | unsigned int max) | |
849 | { | |
850 | unsigned int i, count; | |
851 | ||
852 | if (rt == NULL) | |
853 | return 0; | |
854 | ||
855 | for (i = 0, count = 0; i < rt->rate_count && max > 0; i++) { | |
d8ee398d LR |
856 | rates[count].bitrate = rt->rates[i].rate_kbps / 100; |
857 | rates[count].hw_value = rt->rates[i].rate_code; | |
858 | rates[count].flags = rt->rates[i].modulation; | |
fa1c114f JS |
859 | count++; |
860 | max--; | |
861 | } | |
862 | ||
863 | return count; | |
864 | } | |
865 | ||
866 | static unsigned int | |
867 | ath5k_copy_channels(struct ath5k_hw *ah, | |
868 | struct ieee80211_channel *channels, | |
869 | unsigned int mode, | |
870 | unsigned int max) | |
871 | { | |
d8ee398d | 872 | unsigned int i, count, size, chfreq, freq, ch; |
fa1c114f JS |
873 | |
874 | if (!test_bit(mode, ah->ah_modes)) | |
875 | return 0; | |
876 | ||
fa1c114f | 877 | switch (mode) { |
d8ee398d LR |
878 | case AR5K_MODE_11A: |
879 | case AR5K_MODE_11A_TURBO: | |
fa1c114f | 880 | /* 1..220, but 2GHz frequencies are filtered by check_channel */ |
d8ee398d | 881 | size = 220 ; |
fa1c114f JS |
882 | chfreq = CHANNEL_5GHZ; |
883 | break; | |
d8ee398d LR |
884 | case AR5K_MODE_11B: |
885 | case AR5K_MODE_11G: | |
886 | case AR5K_MODE_11G_TURBO: | |
887 | size = 26; | |
fa1c114f JS |
888 | chfreq = CHANNEL_2GHZ; |
889 | break; | |
890 | default: | |
891 | ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n"); | |
892 | return 0; | |
893 | } | |
894 | ||
895 | for (i = 0, count = 0; i < size && max > 0; i++) { | |
d8ee398d LR |
896 | ch = i + 1 ; |
897 | freq = ath5k_ieee2mhz(ch); | |
fa1c114f | 898 | |
d8ee398d LR |
899 | /* Check if channel is supported by the chipset */ |
900 | if (!ath5k_channel_ok(ah, freq, chfreq)) | |
fa1c114f JS |
901 | continue; |
902 | ||
d8ee398d LR |
903 | /* Write channel info and increment counter */ |
904 | channels[count].center_freq = freq; | |
a3f4b914 LR |
905 | channels[count].band = (chfreq == CHANNEL_2GHZ) ? |
906 | IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ; | |
400ec45a LR |
907 | switch (mode) { |
908 | case AR5K_MODE_11A: | |
909 | case AR5K_MODE_11G: | |
910 | channels[count].hw_value = chfreq | CHANNEL_OFDM; | |
911 | break; | |
912 | case AR5K_MODE_11A_TURBO: | |
913 | case AR5K_MODE_11G_TURBO: | |
914 | channels[count].hw_value = chfreq | | |
915 | CHANNEL_OFDM | CHANNEL_TURBO; | |
916 | break; | |
917 | case AR5K_MODE_11B: | |
d8ee398d LR |
918 | channels[count].hw_value = CHANNEL_B; |
919 | } | |
fa1c114f | 920 | |
fa1c114f JS |
921 | count++; |
922 | max--; | |
923 | } | |
924 | ||
925 | return count; | |
926 | } | |
927 | ||
d8ee398d LR |
928 | static int |
929 | ath5k_getchannels(struct ieee80211_hw *hw) | |
fa1c114f JS |
930 | { |
931 | struct ath5k_softc *sc = hw->priv; | |
d8ee398d LR |
932 | struct ath5k_hw *ah = sc->ah; |
933 | struct ieee80211_supported_band *sbands = sc->sbands; | |
934 | const struct ath5k_rate_table *hw_rates; | |
935 | unsigned int max_r, max_c, count_r, count_c; | |
936 | int mode2g = AR5K_MODE_11G; | |
fa1c114f | 937 | |
d8ee398d | 938 | BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS); |
fa1c114f | 939 | |
d8ee398d LR |
940 | max_r = ARRAY_SIZE(sc->rates); |
941 | max_c = ARRAY_SIZE(sc->channels); | |
942 | count_r = count_c = 0; | |
943 | ||
944 | /* 2GHz band */ | |
400ec45a | 945 | if (!test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) { |
d8ee398d | 946 | mode2g = AR5K_MODE_11B; |
400ec45a LR |
947 | if (!test_bit(AR5K_MODE_11B, |
948 | sc->ah->ah_capabilities.cap_mode)) | |
d8ee398d | 949 | mode2g = -1; |
fa1c114f | 950 | } |
fa1c114f | 951 | |
400ec45a LR |
952 | if (mode2g > 0) { |
953 | struct ieee80211_supported_band *sband = | |
954 | &sbands[IEEE80211_BAND_2GHZ]; | |
fa1c114f | 955 | |
d8ee398d LR |
956 | sband->bitrates = sc->rates; |
957 | sband->channels = sc->channels; | |
fa1c114f | 958 | |
d8ee398d LR |
959 | sband->band = IEEE80211_BAND_2GHZ; |
960 | sband->n_channels = ath5k_copy_channels(ah, sband->channels, | |
961 | mode2g, max_c); | |
fa1c114f | 962 | |
d8ee398d LR |
963 | hw_rates = ath5k_hw_get_rate_table(ah, mode2g); |
964 | sband->n_bitrates = ath5k_copy_rates(sband->bitrates, | |
400ec45a | 965 | hw_rates, max_r); |
fa1c114f | 966 | |
d8ee398d LR |
967 | count_c = sband->n_channels; |
968 | count_r = sband->n_bitrates; | |
fa1c114f | 969 | |
d8ee398d LR |
970 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; |
971 | ||
972 | max_r -= count_r; | |
973 | max_c -= count_c; | |
fa1c114f | 974 | |
fa1c114f JS |
975 | } |
976 | ||
d8ee398d | 977 | /* 5GHz band */ |
fa1c114f | 978 | |
400ec45a LR |
979 | if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) { |
980 | struct ieee80211_supported_band *sband = | |
981 | &sbands[IEEE80211_BAND_5GHZ]; | |
fa1c114f | 982 | |
d8ee398d LR |
983 | sband->bitrates = &sc->rates[count_r]; |
984 | sband->channels = &sc->channels[count_c]; | |
fa1c114f | 985 | |
d8ee398d LR |
986 | sband->band = IEEE80211_BAND_5GHZ; |
987 | sband->n_channels = ath5k_copy_channels(ah, sband->channels, | |
988 | AR5K_MODE_11A, max_c); | |
989 | ||
990 | hw_rates = ath5k_hw_get_rate_table(ah, AR5K_MODE_11A); | |
991 | sband->n_bitrates = ath5k_copy_rates(sband->bitrates, | |
400ec45a | 992 | hw_rates, max_r); |
d8ee398d LR |
993 | |
994 | hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband; | |
995 | } | |
996 | ||
b446197c | 997 | ath5k_debug_dump_bands(sc); |
d8ee398d LR |
998 | |
999 | return 0; | |
fa1c114f JS |
1000 | } |
1001 | ||
1002 | /* | |
1003 | * Set/change channels. If the channel is really being changed, | |
1004 | * it's done by reseting the chip. To accomplish this we must | |
1005 | * first cleanup any pending DMA, then restart stuff after a la | |
1006 | * ath5k_init. | |
1007 | */ | |
1008 | static int | |
1009 | ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan) | |
1010 | { | |
1011 | struct ath5k_hw *ah = sc->ah; | |
1012 | int ret; | |
1013 | ||
d8ee398d LR |
1014 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n", |
1015 | sc->curchan->center_freq, chan->center_freq); | |
1016 | ||
1017 | if (chan->center_freq != sc->curchan->center_freq || | |
1018 | chan->hw_value != sc->curchan->hw_value) { | |
1019 | ||
1020 | sc->curchan = chan; | |
1021 | sc->curband = &sc->sbands[chan->band]; | |
fa1c114f | 1022 | |
fa1c114f JS |
1023 | /* |
1024 | * To switch channels clear any pending DMA operations; | |
1025 | * wait long enough for the RX fifo to drain, reset the | |
1026 | * hardware at the new frequency, and then re-enable | |
1027 | * the relevant bits of the h/w. | |
1028 | */ | |
1029 | ath5k_hw_set_intr(ah, 0); /* disable interrupts */ | |
1030 | ath5k_txq_cleanup(sc); /* clear pending tx frames */ | |
1031 | ath5k_rx_stop(sc); /* turn off frame recv */ | |
d8ee398d | 1032 | ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true); |
fa1c114f | 1033 | if (ret) { |
d8ee398d LR |
1034 | ATH5K_ERR(sc, "%s: unable to reset channel " |
1035 | "(%u Mhz)\n", __func__, chan->center_freq); | |
fa1c114f JS |
1036 | return ret; |
1037 | } | |
d8ee398d | 1038 | |
fa1c114f JS |
1039 | ath5k_hw_set_txpower_limit(sc->ah, 0); |
1040 | ||
1041 | /* | |
1042 | * Re-enable rx framework. | |
1043 | */ | |
1044 | ret = ath5k_rx_start(sc); | |
1045 | if (ret) { | |
1046 | ATH5K_ERR(sc, "%s: unable to restart recv logic\n", | |
1047 | __func__); | |
1048 | return ret; | |
1049 | } | |
1050 | ||
1051 | /* | |
1052 | * Change channels and update the h/w rate map | |
1053 | * if we're switching; e.g. 11a to 11b/g. | |
1054 | * | |
1055 | * XXX needed? | |
1056 | */ | |
1057 | /* ath5k_chan_change(sc, chan); */ | |
1058 | ||
1059 | ath5k_beacon_config(sc); | |
1060 | /* | |
1061 | * Re-enable interrupts. | |
1062 | */ | |
1063 | ath5k_hw_set_intr(ah, sc->imask); | |
1064 | } | |
1065 | ||
1066 | return 0; | |
1067 | } | |
1068 | ||
d8ee398d LR |
1069 | /* |
1070 | * TODO: CLEAN THIS !!! | |
1071 | */ | |
fa1c114f JS |
1072 | static void |
1073 | ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode) | |
1074 | { | |
1075 | if (unlikely(test_bit(ATH_STAT_LEDSOFT, sc->status))) { | |
1076 | /* from Atheros NDIS driver, w/ permission */ | |
1077 | static const struct { | |
1078 | u16 rate; /* tx/rx 802.11 rate */ | |
1079 | u16 timeOn; /* LED on time (ms) */ | |
1080 | u16 timeOff; /* LED off time (ms) */ | |
1081 | } blinkrates[] = { | |
1082 | { 108, 40, 10 }, | |
1083 | { 96, 44, 11 }, | |
1084 | { 72, 50, 13 }, | |
1085 | { 48, 57, 14 }, | |
1086 | { 36, 67, 16 }, | |
1087 | { 24, 80, 20 }, | |
1088 | { 22, 100, 25 }, | |
1089 | { 18, 133, 34 }, | |
1090 | { 12, 160, 40 }, | |
1091 | { 10, 200, 50 }, | |
1092 | { 6, 240, 58 }, | |
1093 | { 4, 267, 66 }, | |
1094 | { 2, 400, 100 }, | |
1095 | { 0, 500, 130 } | |
1096 | }; | |
1097 | const struct ath5k_rate_table *rt = | |
1098 | ath5k_hw_get_rate_table(sc->ah, mode); | |
1099 | unsigned int i, j; | |
1100 | ||
1101 | BUG_ON(rt == NULL); | |
1102 | ||
1103 | memset(sc->hwmap, 0, sizeof(sc->hwmap)); | |
1104 | for (i = 0; i < 32; i++) { | |
1105 | u8 ix = rt->rate_code_to_index[i]; | |
1106 | if (ix == 0xff) { | |
1107 | sc->hwmap[i].ledon = msecs_to_jiffies(500); | |
1108 | sc->hwmap[i].ledoff = msecs_to_jiffies(130); | |
1109 | continue; | |
1110 | } | |
1111 | sc->hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; | |
fa1c114f JS |
1112 | /* receive frames include FCS */ |
1113 | sc->hwmap[i].rxflags = sc->hwmap[i].txflags | | |
1114 | IEEE80211_RADIOTAP_F_FCS; | |
1115 | /* setup blink rate table to avoid per-packet lookup */ | |
1116 | for (j = 0; j < ARRAY_SIZE(blinkrates) - 1; j++) | |
1117 | if (blinkrates[j].rate == /* XXX why 7f? */ | |
1118 | (rt->rates[ix].dot11_rate&0x7f)) | |
1119 | break; | |
1120 | ||
1121 | sc->hwmap[i].ledon = msecs_to_jiffies(blinkrates[j]. | |
1122 | timeOn); | |
1123 | sc->hwmap[i].ledoff = msecs_to_jiffies(blinkrates[j]. | |
1124 | timeOff); | |
1125 | } | |
1126 | } | |
1127 | ||
1128 | sc->curmode = mode; | |
d8ee398d | 1129 | |
400ec45a | 1130 | if (mode == AR5K_MODE_11A) { |
d8ee398d LR |
1131 | sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ]; |
1132 | } else { | |
1133 | sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ]; | |
1134 | } | |
fa1c114f JS |
1135 | } |
1136 | ||
1137 | static void | |
1138 | ath5k_mode_setup(struct ath5k_softc *sc) | |
1139 | { | |
1140 | struct ath5k_hw *ah = sc->ah; | |
1141 | u32 rfilt; | |
1142 | ||
1143 | /* configure rx filter */ | |
1144 | rfilt = sc->filter_flags; | |
1145 | ath5k_hw_set_rx_filter(ah, rfilt); | |
1146 | ||
1147 | if (ath5k_hw_hasbssidmask(ah)) | |
1148 | ath5k_hw_set_bssid_mask(ah, sc->bssidmask); | |
1149 | ||
1150 | /* configure operational mode */ | |
1151 | ath5k_hw_set_opmode(ah); | |
1152 | ||
1153 | ath5k_hw_set_mcast_filter(ah, 0, 0); | |
1154 | ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt); | |
1155 | } | |
1156 | ||
d8ee398d LR |
1157 | /* |
1158 | * Match the hw provided rate index (through descriptors) | |
1159 | * to an index for sc->curband->bitrates, so it can be used | |
1160 | * by the stack. | |
1161 | * | |
1162 | * This one is a little bit tricky but i think i'm right | |
1163 | * about this... | |
1164 | * | |
1165 | * We have 4 rate tables in the following order: | |
1166 | * XR (4 rates) | |
1167 | * 802.11a (8 rates) | |
1168 | * 802.11b (4 rates) | |
1169 | * 802.11g (12 rates) | |
1170 | * that make the hw rate table. | |
1171 | * | |
1172 | * Lets take a 5211 for example that supports a and b modes only. | |
1173 | * First comes the 802.11a table and then 802.11b (total 12 rates). | |
1174 | * When hw returns eg. 11 it points to the last 802.11b rate (11Mbit), | |
1175 | * if it returns 2 it points to the second 802.11a rate etc. | |
1176 | * | |
1177 | * Same goes for 5212 who has xr/a/b/g support (total 28 rates). | |
1178 | * First comes the XR table, then 802.11a, 802.11b and 802.11g. | |
1179 | * When hw returns eg. 27 it points to the last 802.11g rate (54Mbits) etc | |
1180 | */ | |
1181 | static void | |
400ec45a | 1182 | ath5k_set_total_hw_rates(struct ath5k_softc *sc) { |
d8ee398d LR |
1183 | |
1184 | struct ath5k_hw *ah = sc->ah; | |
1185 | ||
400ec45a | 1186 | if (test_bit(AR5K_MODE_11A, ah->ah_modes)) |
d8ee398d LR |
1187 | sc->a_rates = 8; |
1188 | ||
400ec45a | 1189 | if (test_bit(AR5K_MODE_11B, ah->ah_modes)) |
d8ee398d LR |
1190 | sc->b_rates = 4; |
1191 | ||
400ec45a | 1192 | if (test_bit(AR5K_MODE_11G, ah->ah_modes)) |
d8ee398d LR |
1193 | sc->g_rates = 12; |
1194 | ||
1195 | /* XXX: Need to see what what happens when | |
1196 | xr disable bits in eeprom are set */ | |
400ec45a | 1197 | if (ah->ah_version >= AR5K_AR5212) |
d8ee398d LR |
1198 | sc->xr_rates = 4; |
1199 | ||
1200 | } | |
1201 | ||
1202 | static inline int | |
400ec45a | 1203 | ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix) { |
d8ee398d LR |
1204 | |
1205 | int mac80211_rix; | |
1206 | ||
400ec45a | 1207 | if(sc->curband->band == IEEE80211_BAND_2GHZ) { |
d8ee398d | 1208 | /* We setup a g ratetable for both b/g modes */ |
400ec45a LR |
1209 | mac80211_rix = |
1210 | hw_rix - sc->b_rates - sc->a_rates - sc->xr_rates; | |
d8ee398d LR |
1211 | } else { |
1212 | mac80211_rix = hw_rix - sc->xr_rates; | |
1213 | } | |
1214 | ||
1215 | /* Something went wrong, fallback to basic rate for this band */ | |
400ec45a LR |
1216 | if ((mac80211_rix >= sc->curband->n_bitrates) || |
1217 | (mac80211_rix <= 0 )) | |
d8ee398d | 1218 | mac80211_rix = 1; |
d8ee398d LR |
1219 | |
1220 | return mac80211_rix; | |
1221 | } | |
1222 | ||
fa1c114f JS |
1223 | |
1224 | ||
1225 | ||
1226 | /***************\ | |
1227 | * Buffers setup * | |
1228 | \***************/ | |
1229 | ||
1230 | static int | |
1231 | ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf) | |
1232 | { | |
1233 | struct ath5k_hw *ah = sc->ah; | |
1234 | struct sk_buff *skb = bf->skb; | |
1235 | struct ath5k_desc *ds; | |
1236 | ||
1237 | if (likely(skb == NULL)) { | |
1238 | unsigned int off; | |
1239 | ||
1240 | /* | |
1241 | * Allocate buffer with headroom_needed space for the | |
1242 | * fake physical layer header at the start. | |
1243 | */ | |
1244 | skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1); | |
1245 | if (unlikely(skb == NULL)) { | |
1246 | ATH5K_ERR(sc, "can't alloc skbuff of size %u\n", | |
1247 | sc->rxbufsize + sc->cachelsz - 1); | |
1248 | return -ENOMEM; | |
1249 | } | |
1250 | /* | |
1251 | * Cache-line-align. This is important (for the | |
1252 | * 5210 at least) as not doing so causes bogus data | |
1253 | * in rx'd frames. | |
1254 | */ | |
1255 | off = ((unsigned long)skb->data) % sc->cachelsz; | |
1256 | if (off != 0) | |
1257 | skb_reserve(skb, sc->cachelsz - off); | |
1258 | ||
1259 | bf->skb = skb; | |
1260 | bf->skbaddr = pci_map_single(sc->pdev, | |
1261 | skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE); | |
1262 | if (unlikely(pci_dma_mapping_error(bf->skbaddr))) { | |
1263 | ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__); | |
1264 | dev_kfree_skb(skb); | |
1265 | bf->skb = NULL; | |
1266 | return -ENOMEM; | |
1267 | } | |
1268 | } | |
1269 | ||
1270 | /* | |
1271 | * Setup descriptors. For receive we always terminate | |
1272 | * the descriptor list with a self-linked entry so we'll | |
1273 | * not get overrun under high load (as can happen with a | |
1274 | * 5212 when ANI processing enables PHY error frames). | |
1275 | * | |
1276 | * To insure the last descriptor is self-linked we create | |
1277 | * each descriptor as self-linked and add it to the end. As | |
1278 | * each additional descriptor is added the previous self-linked | |
1279 | * entry is ``fixed'' naturally. This should be safe even | |
1280 | * if DMA is happening. When processing RX interrupts we | |
1281 | * never remove/process the last, self-linked, entry on the | |
1282 | * descriptor list. This insures the hardware always has | |
1283 | * someplace to write a new frame. | |
1284 | */ | |
1285 | ds = bf->desc; | |
1286 | ds->ds_link = bf->daddr; /* link to self */ | |
1287 | ds->ds_data = bf->skbaddr; | |
1288 | ath5k_hw_setup_rx_desc(ah, ds, | |
1289 | skb_tailroom(skb), /* buffer size */ | |
1290 | 0); | |
1291 | ||
1292 | if (sc->rxlink != NULL) | |
1293 | *sc->rxlink = bf->daddr; | |
1294 | sc->rxlink = &ds->ds_link; | |
1295 | return 0; | |
1296 | } | |
1297 | ||
1298 | static int | |
1299 | ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf, | |
1300 | struct ieee80211_tx_control *ctl) | |
1301 | { | |
1302 | struct ath5k_hw *ah = sc->ah; | |
1303 | struct ath5k_txq *txq = sc->txq; | |
1304 | struct ath5k_desc *ds = bf->desc; | |
1305 | struct sk_buff *skb = bf->skb; | |
1306 | unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID; | |
1307 | int ret; | |
1308 | ||
1309 | flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK; | |
1310 | bf->ctl = *ctl; | |
1311 | /* XXX endianness */ | |
1312 | bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len, | |
1313 | PCI_DMA_TODEVICE); | |
1314 | ||
1315 | if (ctl->flags & IEEE80211_TXCTL_NO_ACK) | |
1316 | flags |= AR5K_TXDESC_NOACK; | |
1317 | ||
281c56dd | 1318 | pktlen = skb->len; |
fa1c114f JS |
1319 | |
1320 | if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT)) { | |
1321 | keyidx = ctl->key_idx; | |
1322 | pktlen += ctl->icv_len; | |
1323 | } | |
1324 | ||
1325 | ret = ah->ah_setup_tx_desc(ah, ds, pktlen, | |
1326 | ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL, | |
400ec45a LR |
1327 | (sc->power_level * 2), ctl->tx_rate->hw_value, |
1328 | ctl->retry_limit, keyidx, 0, flags, 0, 0); | |
fa1c114f JS |
1329 | if (ret) |
1330 | goto err_unmap; | |
1331 | ||
1332 | ds->ds_link = 0; | |
1333 | ds->ds_data = bf->skbaddr; | |
1334 | ||
1335 | spin_lock_bh(&txq->lock); | |
1336 | list_add_tail(&bf->list, &txq->q); | |
1337 | sc->tx_stats.data[txq->qnum].len++; | |
1338 | if (txq->link == NULL) /* is this first packet? */ | |
1339 | ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr); | |
1340 | else /* no, so only link it */ | |
1341 | *txq->link = bf->daddr; | |
1342 | ||
1343 | txq->link = &ds->ds_link; | |
1344 | ath5k_hw_tx_start(ah, txq->qnum); | |
1345 | spin_unlock_bh(&txq->lock); | |
1346 | ||
1347 | return 0; | |
1348 | err_unmap: | |
1349 | pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE); | |
1350 | return ret; | |
1351 | } | |
1352 | ||
1353 | /*******************\ | |
1354 | * Descriptors setup * | |
1355 | \*******************/ | |
1356 | ||
1357 | static int | |
1358 | ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev) | |
1359 | { | |
1360 | struct ath5k_desc *ds; | |
1361 | struct ath5k_buf *bf; | |
1362 | dma_addr_t da; | |
1363 | unsigned int i; | |
1364 | int ret; | |
1365 | ||
1366 | /* allocate descriptors */ | |
1367 | sc->desc_len = sizeof(struct ath5k_desc) * | |
1368 | (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1); | |
1369 | sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr); | |
1370 | if (sc->desc == NULL) { | |
1371 | ATH5K_ERR(sc, "can't allocate descriptors\n"); | |
1372 | ret = -ENOMEM; | |
1373 | goto err; | |
1374 | } | |
1375 | ds = sc->desc; | |
1376 | da = sc->desc_daddr; | |
1377 | ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n", | |
1378 | ds, sc->desc_len, (unsigned long long)sc->desc_daddr); | |
1379 | ||
1380 | bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF, | |
1381 | sizeof(struct ath5k_buf), GFP_KERNEL); | |
1382 | if (bf == NULL) { | |
1383 | ATH5K_ERR(sc, "can't allocate bufptr\n"); | |
1384 | ret = -ENOMEM; | |
1385 | goto err_free; | |
1386 | } | |
1387 | sc->bufptr = bf; | |
1388 | ||
1389 | INIT_LIST_HEAD(&sc->rxbuf); | |
1390 | for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) { | |
1391 | bf->desc = ds; | |
1392 | bf->daddr = da; | |
1393 | list_add_tail(&bf->list, &sc->rxbuf); | |
1394 | } | |
1395 | ||
1396 | INIT_LIST_HEAD(&sc->txbuf); | |
1397 | sc->txbuf_len = ATH_TXBUF; | |
1398 | for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, | |
1399 | da += sizeof(*ds)) { | |
1400 | bf->desc = ds; | |
1401 | bf->daddr = da; | |
1402 | list_add_tail(&bf->list, &sc->txbuf); | |
1403 | } | |
1404 | ||
1405 | /* beacon buffer */ | |
1406 | bf->desc = ds; | |
1407 | bf->daddr = da; | |
1408 | sc->bbuf = bf; | |
1409 | ||
1410 | return 0; | |
1411 | err_free: | |
1412 | pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr); | |
1413 | err: | |
1414 | sc->desc = NULL; | |
1415 | return ret; | |
1416 | } | |
1417 | ||
1418 | static void | |
1419 | ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev) | |
1420 | { | |
1421 | struct ath5k_buf *bf; | |
1422 | ||
1423 | ath5k_txbuf_free(sc, sc->bbuf); | |
1424 | list_for_each_entry(bf, &sc->txbuf, list) | |
1425 | ath5k_txbuf_free(sc, bf); | |
1426 | list_for_each_entry(bf, &sc->rxbuf, list) | |
1427 | ath5k_txbuf_free(sc, bf); | |
1428 | ||
1429 | /* Free memory associated with all descriptors */ | |
1430 | pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr); | |
1431 | ||
1432 | kfree(sc->bufptr); | |
1433 | sc->bufptr = NULL; | |
1434 | } | |
1435 | ||
1436 | ||
1437 | ||
1438 | ||
1439 | ||
1440 | /**************\ | |
1441 | * Queues setup * | |
1442 | \**************/ | |
1443 | ||
1444 | static struct ath5k_txq * | |
1445 | ath5k_txq_setup(struct ath5k_softc *sc, | |
1446 | int qtype, int subtype) | |
1447 | { | |
1448 | struct ath5k_hw *ah = sc->ah; | |
1449 | struct ath5k_txq *txq; | |
1450 | struct ath5k_txq_info qi = { | |
1451 | .tqi_subtype = subtype, | |
1452 | .tqi_aifs = AR5K_TXQ_USEDEFAULT, | |
1453 | .tqi_cw_min = AR5K_TXQ_USEDEFAULT, | |
1454 | .tqi_cw_max = AR5K_TXQ_USEDEFAULT | |
1455 | }; | |
1456 | int qnum; | |
1457 | ||
1458 | /* | |
1459 | * Enable interrupts only for EOL and DESC conditions. | |
1460 | * We mark tx descriptors to receive a DESC interrupt | |
1461 | * when a tx queue gets deep; otherwise waiting for the | |
1462 | * EOL to reap descriptors. Note that this is done to | |
1463 | * reduce interrupt load and this only defers reaping | |
1464 | * descriptors, never transmitting frames. Aside from | |
1465 | * reducing interrupts this also permits more concurrency. | |
1466 | * The only potential downside is if the tx queue backs | |
1467 | * up in which case the top half of the kernel may backup | |
1468 | * due to a lack of tx descriptors. | |
1469 | */ | |
1470 | qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE | | |
1471 | AR5K_TXQ_FLAG_TXDESCINT_ENABLE; | |
1472 | qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi); | |
1473 | if (qnum < 0) { | |
1474 | /* | |
1475 | * NB: don't print a message, this happens | |
1476 | * normally on parts with too few tx queues | |
1477 | */ | |
1478 | return ERR_PTR(qnum); | |
1479 | } | |
1480 | if (qnum >= ARRAY_SIZE(sc->txqs)) { | |
1481 | ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n", | |
1482 | qnum, ARRAY_SIZE(sc->txqs)); | |
1483 | ath5k_hw_release_tx_queue(ah, qnum); | |
1484 | return ERR_PTR(-EINVAL); | |
1485 | } | |
1486 | txq = &sc->txqs[qnum]; | |
1487 | if (!txq->setup) { | |
1488 | txq->qnum = qnum; | |
1489 | txq->link = NULL; | |
1490 | INIT_LIST_HEAD(&txq->q); | |
1491 | spin_lock_init(&txq->lock); | |
1492 | txq->setup = true; | |
1493 | } | |
1494 | return &sc->txqs[qnum]; | |
1495 | } | |
1496 | ||
1497 | static int | |
1498 | ath5k_beaconq_setup(struct ath5k_hw *ah) | |
1499 | { | |
1500 | struct ath5k_txq_info qi = { | |
1501 | .tqi_aifs = AR5K_TXQ_USEDEFAULT, | |
1502 | .tqi_cw_min = AR5K_TXQ_USEDEFAULT, | |
1503 | .tqi_cw_max = AR5K_TXQ_USEDEFAULT, | |
1504 | /* NB: for dynamic turbo, don't enable any other interrupts */ | |
1505 | .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE | |
1506 | }; | |
1507 | ||
1508 | return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi); | |
1509 | } | |
1510 | ||
1511 | static int | |
1512 | ath5k_beaconq_config(struct ath5k_softc *sc) | |
1513 | { | |
1514 | struct ath5k_hw *ah = sc->ah; | |
1515 | struct ath5k_txq_info qi; | |
1516 | int ret; | |
1517 | ||
1518 | ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi); | |
1519 | if (ret) | |
1520 | return ret; | |
6d91e1d8 | 1521 | if (sc->opmode == IEEE80211_IF_TYPE_AP) { |
fa1c114f JS |
1522 | /* |
1523 | * Always burst out beacon and CAB traffic | |
1524 | * (aifs = cwmin = cwmax = 0) | |
1525 | */ | |
1526 | qi.tqi_aifs = 0; | |
1527 | qi.tqi_cw_min = 0; | |
1528 | qi.tqi_cw_max = 0; | |
6d91e1d8 BR |
1529 | } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) { |
1530 | /* | |
1531 | * Adhoc mode; backoff between 0 and (2 * cw_min). | |
1532 | */ | |
1533 | qi.tqi_aifs = 0; | |
1534 | qi.tqi_cw_min = 0; | |
1535 | qi.tqi_cw_max = 2 * ah->ah_cw_min; | |
fa1c114f JS |
1536 | } |
1537 | ||
6d91e1d8 BR |
1538 | ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, |
1539 | "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n", | |
1540 | qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max); | |
1541 | ||
fa1c114f JS |
1542 | ret = ath5k_hw_setup_tx_queueprops(ah, sc->bhalq, &qi); |
1543 | if (ret) { | |
1544 | ATH5K_ERR(sc, "%s: unable to update parameters for beacon " | |
1545 | "hardware queue!\n", __func__); | |
1546 | return ret; | |
1547 | } | |
1548 | ||
1549 | return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */; | |
1550 | } | |
1551 | ||
1552 | static void | |
1553 | ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq) | |
1554 | { | |
1555 | struct ath5k_buf *bf, *bf0; | |
1556 | ||
1557 | /* | |
1558 | * NB: this assumes output has been stopped and | |
1559 | * we do not need to block ath5k_tx_tasklet | |
1560 | */ | |
1561 | spin_lock_bh(&txq->lock); | |
1562 | list_for_each_entry_safe(bf, bf0, &txq->q, list) { | |
1563 | ath5k_debug_printtxbuf(sc, bf, !sc->ah->ah_proc_tx_desc(sc->ah, | |
1564 | bf->desc)); | |
1565 | ||
1566 | ath5k_txbuf_free(sc, bf); | |
1567 | ||
1568 | spin_lock_bh(&sc->txbuflock); | |
1569 | sc->tx_stats.data[txq->qnum].len--; | |
1570 | list_move_tail(&bf->list, &sc->txbuf); | |
1571 | sc->txbuf_len++; | |
1572 | spin_unlock_bh(&sc->txbuflock); | |
1573 | } | |
1574 | txq->link = NULL; | |
1575 | spin_unlock_bh(&txq->lock); | |
1576 | } | |
1577 | ||
1578 | /* | |
1579 | * Drain the transmit queues and reclaim resources. | |
1580 | */ | |
1581 | static void | |
1582 | ath5k_txq_cleanup(struct ath5k_softc *sc) | |
1583 | { | |
1584 | struct ath5k_hw *ah = sc->ah; | |
1585 | unsigned int i; | |
1586 | ||
1587 | /* XXX return value */ | |
1588 | if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) { | |
1589 | /* don't touch the hardware if marked invalid */ | |
1590 | ath5k_hw_stop_tx_dma(ah, sc->bhalq); | |
1591 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n", | |
1592 | ath5k_hw_get_tx_buf(ah, sc->bhalq)); | |
1593 | for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) | |
1594 | if (sc->txqs[i].setup) { | |
1595 | ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum); | |
1596 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, " | |
1597 | "link %p\n", | |
1598 | sc->txqs[i].qnum, | |
1599 | ath5k_hw_get_tx_buf(ah, | |
1600 | sc->txqs[i].qnum), | |
1601 | sc->txqs[i].link); | |
1602 | } | |
1603 | } | |
1604 | ieee80211_start_queues(sc->hw); /* XXX move to callers */ | |
1605 | ||
1606 | for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) | |
1607 | if (sc->txqs[i].setup) | |
1608 | ath5k_txq_drainq(sc, &sc->txqs[i]); | |
1609 | } | |
1610 | ||
1611 | static void | |
1612 | ath5k_txq_release(struct ath5k_softc *sc) | |
1613 | { | |
1614 | struct ath5k_txq *txq = sc->txqs; | |
1615 | unsigned int i; | |
1616 | ||
1617 | for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++) | |
1618 | if (txq->setup) { | |
1619 | ath5k_hw_release_tx_queue(sc->ah, txq->qnum); | |
1620 | txq->setup = false; | |
1621 | } | |
1622 | } | |
1623 | ||
1624 | ||
1625 | ||
1626 | ||
1627 | /*************\ | |
1628 | * RX Handling * | |
1629 | \*************/ | |
1630 | ||
1631 | /* | |
1632 | * Enable the receive h/w following a reset. | |
1633 | */ | |
1634 | static int | |
1635 | ath5k_rx_start(struct ath5k_softc *sc) | |
1636 | { | |
1637 | struct ath5k_hw *ah = sc->ah; | |
1638 | struct ath5k_buf *bf; | |
1639 | int ret; | |
1640 | ||
1641 | sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz); | |
1642 | ||
1643 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n", | |
1644 | sc->cachelsz, sc->rxbufsize); | |
1645 | ||
1646 | sc->rxlink = NULL; | |
1647 | ||
1648 | spin_lock_bh(&sc->rxbuflock); | |
1649 | list_for_each_entry(bf, &sc->rxbuf, list) { | |
1650 | ret = ath5k_rxbuf_setup(sc, bf); | |
1651 | if (ret != 0) { | |
1652 | spin_unlock_bh(&sc->rxbuflock); | |
1653 | goto err; | |
1654 | } | |
1655 | } | |
1656 | bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list); | |
1657 | spin_unlock_bh(&sc->rxbuflock); | |
1658 | ||
1659 | ath5k_hw_put_rx_buf(ah, bf->daddr); | |
1660 | ath5k_hw_start_rx(ah); /* enable recv descriptors */ | |
1661 | ath5k_mode_setup(sc); /* set filters, etc. */ | |
1662 | ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ | |
1663 | ||
1664 | return 0; | |
1665 | err: | |
1666 | return ret; | |
1667 | } | |
1668 | ||
1669 | /* | |
1670 | * Disable the receive h/w in preparation for a reset. | |
1671 | */ | |
1672 | static void | |
1673 | ath5k_rx_stop(struct ath5k_softc *sc) | |
1674 | { | |
1675 | struct ath5k_hw *ah = sc->ah; | |
1676 | ||
1677 | ath5k_hw_stop_pcu_recv(ah); /* disable PCU */ | |
1678 | ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ | |
1679 | ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */ | |
1680 | mdelay(3); /* 3ms is long enough for 1 frame */ | |
1681 | ||
1682 | ath5k_debug_printrxbuffs(sc, ah); | |
1683 | ||
1684 | sc->rxlink = NULL; /* just in case */ | |
1685 | } | |
1686 | ||
1687 | static unsigned int | |
1688 | ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds, | |
1689 | struct sk_buff *skb) | |
1690 | { | |
1691 | struct ieee80211_hdr *hdr = (void *)skb->data; | |
1692 | unsigned int keyix, hlen = ieee80211_get_hdrlen_from_skb(skb); | |
1693 | ||
1694 | if (!(ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) && | |
1695 | ds->ds_rxstat.rs_keyix != AR5K_RXKEYIX_INVALID) | |
1696 | return RX_FLAG_DECRYPTED; | |
1697 | ||
1698 | /* Apparently when a default key is used to decrypt the packet | |
1699 | the hw does not set the index used to decrypt. In such cases | |
1700 | get the index from the packet. */ | |
1701 | if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED) && | |
1702 | !(ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) && | |
1703 | skb->len >= hlen + 4) { | |
1704 | keyix = skb->data[hlen + 3] >> 6; | |
1705 | ||
1706 | if (test_bit(keyix, sc->keymap)) | |
1707 | return RX_FLAG_DECRYPTED; | |
1708 | } | |
1709 | ||
1710 | return 0; | |
1711 | } | |
1712 | ||
036cd1ec BR |
1713 | |
1714 | static void | |
1715 | ath5k_check_ibss_hw_merge(struct ath5k_softc *sc, struct sk_buff *skb) | |
1716 | { | |
1717 | u32 hw_tu; | |
1718 | struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; | |
1719 | ||
38c07b43 | 1720 | if ((le16_to_cpu(mgmt->frame_control) & IEEE80211_FCTL_FTYPE) == |
036cd1ec | 1721 | IEEE80211_FTYPE_MGMT && |
38c07b43 | 1722 | (le16_to_cpu(mgmt->frame_control) & IEEE80211_FCTL_STYPE) == |
036cd1ec | 1723 | IEEE80211_STYPE_BEACON && |
38c07b43 | 1724 | le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS && |
036cd1ec BR |
1725 | memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) { |
1726 | /* | |
1727 | * Received an IBSS beacon with the same BSSID. Hardware might | |
1728 | * have updated the TSF, check if we need to update timers. | |
1729 | */ | |
1730 | hw_tu = TSF_TO_TU(ath5k_hw_get_tsf64(sc->ah)); | |
1731 | if (hw_tu >= sc->nexttbtt) { | |
1732 | ath5k_beacon_update_timers(sc, | |
38c07b43 | 1733 | le64_to_cpu(mgmt->u.beacon.timestamp)); |
036cd1ec BR |
1734 | ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, |
1735 | "detected HW merge from received beacon\n"); | |
1736 | } | |
1737 | } | |
1738 | } | |
1739 | ||
1740 | ||
fa1c114f JS |
1741 | static void |
1742 | ath5k_tasklet_rx(unsigned long data) | |
1743 | { | |
1744 | struct ieee80211_rx_status rxs = {}; | |
1745 | struct sk_buff *skb; | |
1746 | struct ath5k_softc *sc = (void *)data; | |
1747 | struct ath5k_buf *bf; | |
1748 | struct ath5k_desc *ds; | |
1749 | u16 len; | |
1750 | u8 stat; | |
1751 | int ret; | |
1752 | int hdrlen; | |
1753 | int pad; | |
1754 | ||
1755 | spin_lock(&sc->rxbuflock); | |
1756 | do { | |
1757 | if (unlikely(list_empty(&sc->rxbuf))) { | |
1758 | ATH5K_WARN(sc, "empty rx buf pool\n"); | |
1759 | break; | |
1760 | } | |
1761 | bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list); | |
1762 | BUG_ON(bf->skb == NULL); | |
1763 | skb = bf->skb; | |
1764 | ds = bf->desc; | |
1765 | ||
1766 | /* TODO only one segment */ | |
1767 | pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr, | |
1768 | sc->desc_len, PCI_DMA_FROMDEVICE); | |
1769 | ||
1770 | if (unlikely(ds->ds_link == bf->daddr)) /* this is the end */ | |
1771 | break; | |
1772 | ||
1773 | ret = sc->ah->ah_proc_rx_desc(sc->ah, ds); | |
1774 | if (unlikely(ret == -EINPROGRESS)) | |
1775 | break; | |
1776 | else if (unlikely(ret)) { | |
1777 | ATH5K_ERR(sc, "error in processing rx descriptor\n"); | |
65872e6b | 1778 | spin_unlock(&sc->rxbuflock); |
fa1c114f JS |
1779 | return; |
1780 | } | |
1781 | ||
1782 | if (unlikely(ds->ds_rxstat.rs_more)) { | |
1783 | ATH5K_WARN(sc, "unsupported jumbo\n"); | |
1784 | goto next; | |
1785 | } | |
1786 | ||
1787 | stat = ds->ds_rxstat.rs_status; | |
1788 | if (unlikely(stat)) { | |
1789 | if (stat & AR5K_RXERR_PHY) | |
1790 | goto next; | |
1791 | if (stat & AR5K_RXERR_DECRYPT) { | |
1792 | /* | |
1793 | * Decrypt error. If the error occurred | |
1794 | * because there was no hardware key, then | |
1795 | * let the frame through so the upper layers | |
1796 | * can process it. This is necessary for 5210 | |
1797 | * parts which have no way to setup a ``clear'' | |
1798 | * key cache entry. | |
1799 | * | |
1800 | * XXX do key cache faulting | |
1801 | */ | |
1802 | if (ds->ds_rxstat.rs_keyix == | |
1803 | AR5K_RXKEYIX_INVALID && | |
1804 | !(stat & AR5K_RXERR_CRC)) | |
1805 | goto accept; | |
1806 | } | |
1807 | if (stat & AR5K_RXERR_MIC) { | |
1808 | rxs.flag |= RX_FLAG_MMIC_ERROR; | |
1809 | goto accept; | |
1810 | } | |
1811 | ||
1812 | /* let crypto-error packets fall through in MNTR */ | |
1813 | if ((stat & ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) || | |
1814 | sc->opmode != IEEE80211_IF_TYPE_MNTR) | |
1815 | goto next; | |
1816 | } | |
1817 | accept: | |
1818 | len = ds->ds_rxstat.rs_datalen; | |
1819 | pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, len, | |
1820 | PCI_DMA_FROMDEVICE); | |
1821 | pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize, | |
1822 | PCI_DMA_FROMDEVICE); | |
1823 | bf->skb = NULL; | |
1824 | ||
1825 | skb_put(skb, len); | |
1826 | ||
1827 | /* | |
1828 | * the hardware adds a padding to 4 byte boundaries between | |
1829 | * the header and the payload data if the header length is | |
1830 | * not multiples of 4 - remove it | |
1831 | */ | |
1832 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); | |
1833 | if (hdrlen & 3) { | |
1834 | pad = hdrlen % 4; | |
1835 | memmove(skb->data + pad, skb->data, hdrlen); | |
1836 | skb_pull(skb, pad); | |
1837 | } | |
1838 | ||
c0e1899b BR |
1839 | /* |
1840 | * always extend the mac timestamp, since this information is | |
1841 | * also needed for proper IBSS merging. | |
1842 | * | |
1843 | * XXX: it might be too late to do it here, since rs_tstamp is | |
1844 | * 15bit only. that means TSF extension has to be done within | |
1845 | * 32768usec (about 32ms). it might be necessary to move this to | |
1846 | * the interrupt handler, like it is done in madwifi. | |
1847 | */ | |
1848 | rxs.mactime = ath5k_extend_tsf(sc->ah, ds->ds_rxstat.rs_tstamp); | |
1849 | rxs.flag |= RX_FLAG_TSFT; | |
1850 | ||
d8ee398d LR |
1851 | rxs.freq = sc->curchan->center_freq; |
1852 | rxs.band = sc->curband->band; | |
fa1c114f JS |
1853 | |
1854 | /* | |
1855 | * signal quality: | |
1856 | * the names here are misleading and the usage of these | |
1857 | * values by iwconfig makes it even worse | |
1858 | */ | |
1859 | /* noise floor in dBm, from the last noise calibration */ | |
1860 | rxs.noise = sc->ah->ah_noise_floor; | |
1861 | /* signal level in dBm */ | |
1862 | rxs.ssi = rxs.noise + ds->ds_rxstat.rs_rssi; | |
1863 | /* | |
1864 | * "signal" is actually displayed as Link Quality by iwconfig | |
1865 | * we provide a percentage based on rssi (assuming max rssi 64) | |
1866 | */ | |
1867 | rxs.signal = ds->ds_rxstat.rs_rssi * 100 / 64; | |
1868 | ||
1869 | rxs.antenna = ds->ds_rxstat.rs_antenna; | |
400ec45a LR |
1870 | rxs.rate_idx = ath5k_hw_to_driver_rix(sc, |
1871 | ds->ds_rxstat.rs_rate); | |
fa1c114f JS |
1872 | rxs.flag |= ath5k_rx_decrypted(sc, ds, skb); |
1873 | ||
1874 | ath5k_debug_dump_skb(sc, skb, "RX ", 0); | |
1875 | ||
036cd1ec BR |
1876 | /* check beacons in IBSS mode */ |
1877 | if (sc->opmode == IEEE80211_IF_TYPE_IBSS) | |
1878 | ath5k_check_ibss_hw_merge(sc, skb); | |
1879 | ||
fa1c114f JS |
1880 | __ieee80211_rx(sc->hw, skb, &rxs); |
1881 | sc->led_rxrate = ds->ds_rxstat.rs_rate; | |
1882 | ath5k_led_event(sc, ATH_LED_RX); | |
1883 | next: | |
1884 | list_move_tail(&bf->list, &sc->rxbuf); | |
1885 | } while (ath5k_rxbuf_setup(sc, bf) == 0); | |
1886 | spin_unlock(&sc->rxbuflock); | |
1887 | } | |
1888 | ||
1889 | ||
1890 | ||
1891 | ||
1892 | /*************\ | |
1893 | * TX Handling * | |
1894 | \*************/ | |
1895 | ||
1896 | static void | |
1897 | ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq) | |
1898 | { | |
1899 | struct ieee80211_tx_status txs = {}; | |
1900 | struct ath5k_buf *bf, *bf0; | |
1901 | struct ath5k_desc *ds; | |
1902 | struct sk_buff *skb; | |
1903 | int ret; | |
1904 | ||
1905 | spin_lock(&txq->lock); | |
1906 | list_for_each_entry_safe(bf, bf0, &txq->q, list) { | |
1907 | ds = bf->desc; | |
1908 | ||
1909 | /* TODO only one segment */ | |
1910 | pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr, | |
1911 | sc->desc_len, PCI_DMA_FROMDEVICE); | |
1912 | ret = sc->ah->ah_proc_tx_desc(sc->ah, ds); | |
1913 | if (unlikely(ret == -EINPROGRESS)) | |
1914 | break; | |
1915 | else if (unlikely(ret)) { | |
1916 | ATH5K_ERR(sc, "error %d while processing queue %u\n", | |
1917 | ret, txq->qnum); | |
1918 | break; | |
1919 | } | |
1920 | ||
1921 | skb = bf->skb; | |
1922 | bf->skb = NULL; | |
1923 | pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, | |
1924 | PCI_DMA_TODEVICE); | |
1925 | ||
1926 | txs.control = bf->ctl; | |
1927 | txs.retry_count = ds->ds_txstat.ts_shortretry + | |
1928 | ds->ds_txstat.ts_longretry / 6; | |
1929 | if (unlikely(ds->ds_txstat.ts_status)) { | |
1930 | sc->ll_stats.dot11ACKFailureCount++; | |
1931 | if (ds->ds_txstat.ts_status & AR5K_TXERR_XRETRY) | |
1932 | txs.excessive_retries = 1; | |
1933 | else if (ds->ds_txstat.ts_status & AR5K_TXERR_FILT) | |
1934 | txs.flags |= IEEE80211_TX_STATUS_TX_FILTERED; | |
1935 | } else { | |
1936 | txs.flags |= IEEE80211_TX_STATUS_ACK; | |
1937 | txs.ack_signal = ds->ds_txstat.ts_rssi; | |
1938 | } | |
1939 | ||
1940 | ieee80211_tx_status(sc->hw, skb, &txs); | |
1941 | sc->tx_stats.data[txq->qnum].count++; | |
1942 | ||
1943 | spin_lock(&sc->txbuflock); | |
1944 | sc->tx_stats.data[txq->qnum].len--; | |
1945 | list_move_tail(&bf->list, &sc->txbuf); | |
1946 | sc->txbuf_len++; | |
1947 | spin_unlock(&sc->txbuflock); | |
1948 | } | |
1949 | if (likely(list_empty(&txq->q))) | |
1950 | txq->link = NULL; | |
1951 | spin_unlock(&txq->lock); | |
1952 | if (sc->txbuf_len > ATH_TXBUF / 5) | |
1953 | ieee80211_wake_queues(sc->hw); | |
1954 | } | |
1955 | ||
1956 | static void | |
1957 | ath5k_tasklet_tx(unsigned long data) | |
1958 | { | |
1959 | struct ath5k_softc *sc = (void *)data; | |
1960 | ||
1961 | ath5k_tx_processq(sc, sc->txq); | |
1962 | ||
1963 | ath5k_led_event(sc, ATH_LED_TX); | |
1964 | } | |
1965 | ||
1966 | ||
1967 | ||
1968 | ||
1969 | /*****************\ | |
1970 | * Beacon handling * | |
1971 | \*****************/ | |
1972 | ||
1973 | /* | |
1974 | * Setup the beacon frame for transmit. | |
1975 | */ | |
1976 | static int | |
1977 | ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf, | |
1978 | struct ieee80211_tx_control *ctl) | |
1979 | { | |
1980 | struct sk_buff *skb = bf->skb; | |
1981 | struct ath5k_hw *ah = sc->ah; | |
1982 | struct ath5k_desc *ds; | |
1983 | int ret, antenna = 0; | |
1984 | u32 flags; | |
1985 | ||
1986 | bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len, | |
1987 | PCI_DMA_TODEVICE); | |
1988 | ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] " | |
1989 | "skbaddr %llx\n", skb, skb->data, skb->len, | |
1990 | (unsigned long long)bf->skbaddr); | |
1991 | if (pci_dma_mapping_error(bf->skbaddr)) { | |
1992 | ATH5K_ERR(sc, "beacon DMA mapping failed\n"); | |
1993 | return -EIO; | |
1994 | } | |
1995 | ||
1996 | ds = bf->desc; | |
1997 | ||
1998 | flags = AR5K_TXDESC_NOACK; | |
1999 | if (sc->opmode == IEEE80211_IF_TYPE_IBSS && ath5k_hw_hasveol(ah)) { | |
2000 | ds->ds_link = bf->daddr; /* self-linked */ | |
2001 | flags |= AR5K_TXDESC_VEOL; | |
2002 | /* | |
2003 | * Let hardware handle antenna switching if txantenna is not set | |
2004 | */ | |
2005 | } else { | |
2006 | ds->ds_link = 0; | |
2007 | /* | |
2008 | * Switch antenna every 4 beacons if txantenna is not set | |
2009 | * XXX assumes two antennas | |
2010 | */ | |
2011 | if (antenna == 0) | |
2012 | antenna = sc->bsent & 4 ? 2 : 1; | |
2013 | } | |
2014 | ||
2015 | ds->ds_data = bf->skbaddr; | |
281c56dd | 2016 | ret = ah->ah_setup_tx_desc(ah, ds, skb->len, |
fa1c114f | 2017 | ieee80211_get_hdrlen_from_skb(skb), |
400ec45a LR |
2018 | AR5K_PKT_TYPE_BEACON, (sc->power_level * 2), |
2019 | ctl->tx_rate->hw_value, 1, AR5K_TXKEYIX_INVALID, | |
2020 | antenna, flags, 0, 0); | |
fa1c114f JS |
2021 | if (ret) |
2022 | goto err_unmap; | |
2023 | ||
2024 | return 0; | |
2025 | err_unmap: | |
2026 | pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE); | |
2027 | return ret; | |
2028 | } | |
2029 | ||
2030 | /* | |
2031 | * Transmit a beacon frame at SWBA. Dynamic updates to the | |
2032 | * frame contents are done as needed and the slot time is | |
2033 | * also adjusted based on current state. | |
2034 | * | |
2035 | * this is usually called from interrupt context (ath5k_intr()) | |
2036 | * but also from ath5k_beacon_config() in IBSS mode which in turn | |
2037 | * can be called from a tasklet and user context | |
2038 | */ | |
2039 | static void | |
2040 | ath5k_beacon_send(struct ath5k_softc *sc) | |
2041 | { | |
2042 | struct ath5k_buf *bf = sc->bbuf; | |
2043 | struct ath5k_hw *ah = sc->ah; | |
2044 | ||
be9b7259 | 2045 | ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n"); |
fa1c114f JS |
2046 | |
2047 | if (unlikely(bf->skb == NULL || sc->opmode == IEEE80211_IF_TYPE_STA || | |
2048 | sc->opmode == IEEE80211_IF_TYPE_MNTR)) { | |
2049 | ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL); | |
2050 | return; | |
2051 | } | |
2052 | /* | |
2053 | * Check if the previous beacon has gone out. If | |
2054 | * not don't don't try to post another, skip this | |
2055 | * period and wait for the next. Missed beacons | |
2056 | * indicate a problem and should not occur. If we | |
2057 | * miss too many consecutive beacons reset the device. | |
2058 | */ | |
2059 | if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) { | |
2060 | sc->bmisscount++; | |
be9b7259 | 2061 | ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, |
fa1c114f JS |
2062 | "missed %u consecutive beacons\n", sc->bmisscount); |
2063 | if (sc->bmisscount > 3) { /* NB: 3 is a guess */ | |
be9b7259 | 2064 | ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, |
fa1c114f JS |
2065 | "stuck beacon time (%u missed)\n", |
2066 | sc->bmisscount); | |
2067 | tasklet_schedule(&sc->restq); | |
2068 | } | |
2069 | return; | |
2070 | } | |
2071 | if (unlikely(sc->bmisscount != 0)) { | |
be9b7259 | 2072 | ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, |
fa1c114f JS |
2073 | "resume beacon xmit after %u misses\n", |
2074 | sc->bmisscount); | |
2075 | sc->bmisscount = 0; | |
2076 | } | |
2077 | ||
2078 | /* | |
2079 | * Stop any current dma and put the new frame on the queue. | |
2080 | * This should never fail since we check above that no frames | |
2081 | * are still pending on the queue. | |
2082 | */ | |
2083 | if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) { | |
2084 | ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq); | |
2085 | /* NB: hw still stops DMA, so proceed */ | |
2086 | } | |
2087 | pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, bf->skb->len, | |
2088 | PCI_DMA_TODEVICE); | |
2089 | ||
2090 | ath5k_hw_put_tx_buf(ah, sc->bhalq, bf->daddr); | |
2091 | ath5k_hw_tx_start(ah, sc->bhalq); | |
be9b7259 | 2092 | ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n", |
fa1c114f JS |
2093 | sc->bhalq, (unsigned long long)bf->daddr, bf->desc); |
2094 | ||
2095 | sc->bsent++; | |
2096 | } | |
2097 | ||
2098 | ||
9804b98d BR |
2099 | /** |
2100 | * ath5k_beacon_update_timers - update beacon timers | |
2101 | * | |
2102 | * @sc: struct ath5k_softc pointer we are operating on | |
2103 | * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a | |
2104 | * beacon timer update based on the current HW TSF. | |
2105 | * | |
2106 | * Calculate the next target beacon transmit time (TBTT) based on the timestamp | |
2107 | * of a received beacon or the current local hardware TSF and write it to the | |
2108 | * beacon timer registers. | |
2109 | * | |
2110 | * This is called in a variety of situations, e.g. when a beacon is received, | |
2111 | * when a HW merge has been detected, but also when an new IBSS is created or | |
2112 | * when we otherwise know we have to update the timers, but we keep it in this | |
2113 | * function to have it all together in one place. | |
2114 | */ | |
fa1c114f | 2115 | static void |
9804b98d | 2116 | ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf) |
fa1c114f JS |
2117 | { |
2118 | struct ath5k_hw *ah = sc->ah; | |
9804b98d BR |
2119 | u32 nexttbtt, intval, hw_tu, bc_tu; |
2120 | u64 hw_tsf; | |
fa1c114f JS |
2121 | |
2122 | intval = sc->bintval & AR5K_BEACON_PERIOD; | |
2123 | if (WARN_ON(!intval)) | |
2124 | return; | |
2125 | ||
9804b98d BR |
2126 | /* beacon TSF converted to TU */ |
2127 | bc_tu = TSF_TO_TU(bc_tsf); | |
fa1c114f | 2128 | |
9804b98d BR |
2129 | /* current TSF converted to TU */ |
2130 | hw_tsf = ath5k_hw_get_tsf64(ah); | |
2131 | hw_tu = TSF_TO_TU(hw_tsf); | |
fa1c114f | 2132 | |
9804b98d BR |
2133 | #define FUDGE 3 |
2134 | /* we use FUDGE to make sure the next TBTT is ahead of the current TU */ | |
2135 | if (bc_tsf == -1) { | |
2136 | /* | |
2137 | * no beacons received, called internally. | |
2138 | * just need to refresh timers based on HW TSF. | |
2139 | */ | |
2140 | nexttbtt = roundup(hw_tu + FUDGE, intval); | |
2141 | } else if (bc_tsf == 0) { | |
2142 | /* | |
2143 | * no beacon received, probably called by ath5k_reset_tsf(). | |
2144 | * reset TSF to start with 0. | |
2145 | */ | |
2146 | nexttbtt = intval; | |
2147 | intval |= AR5K_BEACON_RESET_TSF; | |
2148 | } else if (bc_tsf > hw_tsf) { | |
2149 | /* | |
2150 | * beacon received, SW merge happend but HW TSF not yet updated. | |
2151 | * not possible to reconfigure timers yet, but next time we | |
2152 | * receive a beacon with the same BSSID, the hardware will | |
2153 | * automatically update the TSF and then we need to reconfigure | |
2154 | * the timers. | |
2155 | */ | |
2156 | ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, | |
2157 | "need to wait for HW TSF sync\n"); | |
2158 | return; | |
2159 | } else { | |
2160 | /* | |
2161 | * most important case for beacon synchronization between STA. | |
2162 | * | |
2163 | * beacon received and HW TSF has been already updated by HW. | |
2164 | * update next TBTT based on the TSF of the beacon, but make | |
2165 | * sure it is ahead of our local TSF timer. | |
2166 | */ | |
2167 | nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval); | |
2168 | } | |
2169 | #undef FUDGE | |
fa1c114f | 2170 | |
036cd1ec BR |
2171 | sc->nexttbtt = nexttbtt; |
2172 | ||
fa1c114f | 2173 | intval |= AR5K_BEACON_ENA; |
fa1c114f | 2174 | ath5k_hw_init_beacon(ah, nexttbtt, intval); |
9804b98d BR |
2175 | |
2176 | /* | |
2177 | * debugging output last in order to preserve the time critical aspect | |
2178 | * of this function | |
2179 | */ | |
2180 | if (bc_tsf == -1) | |
2181 | ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, | |
2182 | "reconfigured timers based on HW TSF\n"); | |
2183 | else if (bc_tsf == 0) | |
2184 | ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, | |
2185 | "reset HW TSF and timers\n"); | |
2186 | else | |
2187 | ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, | |
2188 | "updated timers based on beacon TSF\n"); | |
2189 | ||
2190 | ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, | |
04f93a87 DM |
2191 | "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n", |
2192 | (unsigned long long) bc_tsf, | |
2193 | (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt); | |
9804b98d BR |
2194 | ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n", |
2195 | intval & AR5K_BEACON_PERIOD, | |
2196 | intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "", | |
2197 | intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : ""); | |
fa1c114f JS |
2198 | } |
2199 | ||
2200 | ||
036cd1ec BR |
2201 | /** |
2202 | * ath5k_beacon_config - Configure the beacon queues and interrupts | |
2203 | * | |
2204 | * @sc: struct ath5k_softc pointer we are operating on | |
fa1c114f JS |
2205 | * |
2206 | * When operating in station mode we want to receive a BMISS interrupt when we | |
2207 | * stop seeing beacons from the AP we've associated with so we can look for | |
2208 | * another AP to associate with. | |
2209 | * | |
036cd1ec BR |
2210 | * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA |
2211 | * interrupts to detect HW merges only. | |
2212 | * | |
2213 | * AP mode is missing. | |
fa1c114f JS |
2214 | */ |
2215 | static void | |
2216 | ath5k_beacon_config(struct ath5k_softc *sc) | |
2217 | { | |
2218 | struct ath5k_hw *ah = sc->ah; | |
2219 | ||
2220 | ath5k_hw_set_intr(ah, 0); | |
2221 | sc->bmisscount = 0; | |
2222 | ||
2223 | if (sc->opmode == IEEE80211_IF_TYPE_STA) { | |
2224 | sc->imask |= AR5K_INT_BMISS; | |
2225 | } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) { | |
2226 | /* | |
036cd1ec BR |
2227 | * In IBSS mode we use a self-linked tx descriptor and let the |
2228 | * hardware send the beacons automatically. We have to load it | |
fa1c114f | 2229 | * only once here. |
036cd1ec BR |
2230 | * We use the SWBA interrupt only to keep track of the beacon |
2231 | * timers in order to detect HW merges (automatic TSF updates). | |
fa1c114f JS |
2232 | */ |
2233 | ath5k_beaconq_config(sc); | |
fa1c114f | 2234 | |
036cd1ec BR |
2235 | sc->imask |= AR5K_INT_SWBA; |
2236 | ||
2237 | if (ath5k_hw_hasveol(ah)) | |
fa1c114f JS |
2238 | ath5k_beacon_send(sc); |
2239 | } | |
2240 | /* TODO else AP */ | |
2241 | ||
2242 | ath5k_hw_set_intr(ah, sc->imask); | |
2243 | } | |
2244 | ||
2245 | ||
2246 | /********************\ | |
2247 | * Interrupt handling * | |
2248 | \********************/ | |
2249 | ||
2250 | static int | |
2251 | ath5k_init(struct ath5k_softc *sc) | |
2252 | { | |
2253 | int ret; | |
2254 | ||
2255 | mutex_lock(&sc->lock); | |
2256 | ||
2257 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode); | |
2258 | ||
2259 | /* | |
2260 | * Stop anything previously setup. This is safe | |
2261 | * no matter this is the first time through or not. | |
2262 | */ | |
2263 | ath5k_stop_locked(sc); | |
2264 | ||
2265 | /* | |
2266 | * The basic interface to setting the hardware in a good | |
2267 | * state is ``reset''. On return the hardware is known to | |
2268 | * be powered up and with interrupts disabled. This must | |
2269 | * be followed by initialization of the appropriate bits | |
2270 | * and then setup of the interrupt mask. | |
2271 | */ | |
d8ee398d LR |
2272 | sc->curchan = sc->hw->conf.channel; |
2273 | sc->curband = &sc->sbands[sc->curchan->band]; | |
fa1c114f JS |
2274 | ret = ath5k_hw_reset(sc->ah, sc->opmode, sc->curchan, false); |
2275 | if (ret) { | |
2276 | ATH5K_ERR(sc, "unable to reset hardware: %d\n", ret); | |
2277 | goto done; | |
2278 | } | |
2279 | /* | |
2280 | * This is needed only to setup initial state | |
2281 | * but it's best done after a reset. | |
2282 | */ | |
2283 | ath5k_hw_set_txpower_limit(sc->ah, 0); | |
2284 | ||
2285 | /* | |
2286 | * Setup the hardware after reset: the key cache | |
2287 | * is filled as needed and the receive engine is | |
2288 | * set going. Frame transmit is handled entirely | |
2289 | * in the frame output path; there's nothing to do | |
2290 | * here except setup the interrupt mask. | |
2291 | */ | |
2292 | ret = ath5k_rx_start(sc); | |
2293 | if (ret) | |
2294 | goto done; | |
2295 | ||
2296 | /* | |
2297 | * Enable interrupts. | |
2298 | */ | |
2299 | sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL | | |
2300 | AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL; | |
2301 | ||
2302 | ath5k_hw_set_intr(sc->ah, sc->imask); | |
2303 | /* Set ack to be sent at low bit-rates */ | |
2304 | ath5k_hw_set_ack_bitrate_high(sc->ah, false); | |
2305 | ||
2306 | mod_timer(&sc->calib_tim, round_jiffies(jiffies + | |
2307 | msecs_to_jiffies(ath5k_calinterval * 1000))); | |
2308 | ||
2309 | ret = 0; | |
2310 | done: | |
2311 | mutex_unlock(&sc->lock); | |
2312 | return ret; | |
2313 | } | |
2314 | ||
2315 | static int | |
2316 | ath5k_stop_locked(struct ath5k_softc *sc) | |
2317 | { | |
2318 | struct ath5k_hw *ah = sc->ah; | |
2319 | ||
2320 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n", | |
2321 | test_bit(ATH_STAT_INVALID, sc->status)); | |
2322 | ||
2323 | /* | |
2324 | * Shutdown the hardware and driver: | |
2325 | * stop output from above | |
2326 | * disable interrupts | |
2327 | * turn off timers | |
2328 | * turn off the radio | |
2329 | * clear transmit machinery | |
2330 | * clear receive machinery | |
2331 | * drain and release tx queues | |
2332 | * reclaim beacon resources | |
2333 | * power down hardware | |
2334 | * | |
2335 | * Note that some of this work is not possible if the | |
2336 | * hardware is gone (invalid). | |
2337 | */ | |
2338 | ieee80211_stop_queues(sc->hw); | |
2339 | ||
2340 | if (!test_bit(ATH_STAT_INVALID, sc->status)) { | |
2341 | if (test_bit(ATH_STAT_LEDSOFT, sc->status)) { | |
2342 | del_timer_sync(&sc->led_tim); | |
2343 | ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on); | |
2344 | __clear_bit(ATH_STAT_LEDBLINKING, sc->status); | |
2345 | } | |
2346 | ath5k_hw_set_intr(ah, 0); | |
2347 | } | |
2348 | ath5k_txq_cleanup(sc); | |
2349 | if (!test_bit(ATH_STAT_INVALID, sc->status)) { | |
2350 | ath5k_rx_stop(sc); | |
2351 | ath5k_hw_phy_disable(ah); | |
2352 | } else | |
2353 | sc->rxlink = NULL; | |
2354 | ||
2355 | return 0; | |
2356 | } | |
2357 | ||
2358 | /* | |
2359 | * Stop the device, grabbing the top-level lock to protect | |
2360 | * against concurrent entry through ath5k_init (which can happen | |
2361 | * if another thread does a system call and the thread doing the | |
2362 | * stop is preempted). | |
2363 | */ | |
2364 | static int | |
2365 | ath5k_stop_hw(struct ath5k_softc *sc) | |
2366 | { | |
2367 | int ret; | |
2368 | ||
2369 | mutex_lock(&sc->lock); | |
2370 | ret = ath5k_stop_locked(sc); | |
2371 | if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) { | |
2372 | /* | |
2373 | * Set the chip in full sleep mode. Note that we are | |
2374 | * careful to do this only when bringing the interface | |
2375 | * completely to a stop. When the chip is in this state | |
2376 | * it must be carefully woken up or references to | |
2377 | * registers in the PCI clock domain may freeze the bus | |
2378 | * (and system). This varies by chip and is mostly an | |
2379 | * issue with newer parts that go to sleep more quickly. | |
2380 | */ | |
2381 | if (sc->ah->ah_mac_srev >= 0x78) { | |
2382 | /* | |
2383 | * XXX | |
2384 | * don't put newer MAC revisions > 7.8 to sleep because | |
2385 | * of the above mentioned problems | |
2386 | */ | |
2387 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, " | |
2388 | "not putting device to sleep\n"); | |
2389 | } else { | |
2390 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, | |
2391 | "putting device to full sleep\n"); | |
2392 | ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0); | |
2393 | } | |
2394 | } | |
2395 | ath5k_txbuf_free(sc, sc->bbuf); | |
2396 | mutex_unlock(&sc->lock); | |
2397 | ||
2398 | del_timer_sync(&sc->calib_tim); | |
2399 | ||
2400 | return ret; | |
2401 | } | |
2402 | ||
2403 | static irqreturn_t | |
2404 | ath5k_intr(int irq, void *dev_id) | |
2405 | { | |
2406 | struct ath5k_softc *sc = dev_id; | |
2407 | struct ath5k_hw *ah = sc->ah; | |
2408 | enum ath5k_int status; | |
2409 | unsigned int counter = 1000; | |
2410 | ||
2411 | if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) || | |
2412 | !ath5k_hw_is_intr_pending(ah))) | |
2413 | return IRQ_NONE; | |
2414 | ||
2415 | do { | |
2416 | /* | |
2417 | * Figure out the reason(s) for the interrupt. Note | |
2418 | * that get_isr returns a pseudo-ISR that may include | |
2419 | * bits we haven't explicitly enabled so we mask the | |
2420 | * value to insure we only process bits we requested. | |
2421 | */ | |
2422 | ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */ | |
2423 | ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n", | |
2424 | status, sc->imask); | |
2425 | status &= sc->imask; /* discard unasked for bits */ | |
2426 | if (unlikely(status & AR5K_INT_FATAL)) { | |
2427 | /* | |
2428 | * Fatal errors are unrecoverable. | |
2429 | * Typically these are caused by DMA errors. | |
2430 | */ | |
2431 | tasklet_schedule(&sc->restq); | |
2432 | } else if (unlikely(status & AR5K_INT_RXORN)) { | |
2433 | tasklet_schedule(&sc->restq); | |
2434 | } else { | |
2435 | if (status & AR5K_INT_SWBA) { | |
2436 | /* | |
2437 | * Software beacon alert--time to send a beacon. | |
2438 | * Handle beacon transmission directly; deferring | |
2439 | * this is too slow to meet timing constraints | |
2440 | * under load. | |
036cd1ec BR |
2441 | * |
2442 | * In IBSS mode we use this interrupt just to | |
2443 | * keep track of the next TBTT (target beacon | |
2444 | * transmission time) in order to detect hardware | |
2445 | * merges (TSF updates). | |
fa1c114f | 2446 | */ |
036cd1ec BR |
2447 | if (sc->opmode == IEEE80211_IF_TYPE_IBSS) { |
2448 | /* XXX: only if VEOL suppported */ | |
2449 | u64 tsf = ath5k_hw_get_tsf64(ah); | |
2450 | sc->nexttbtt += sc->bintval; | |
2451 | ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, | |
04f93a87 DM |
2452 | "SWBA nexttbtt: %x hw_tu: %x " |
2453 | "TSF: %llx\n", | |
2454 | sc->nexttbtt, | |
2455 | TSF_TO_TU(tsf), | |
2456 | (unsigned long long) tsf); | |
036cd1ec BR |
2457 | } else { |
2458 | ath5k_beacon_send(sc); | |
2459 | } | |
fa1c114f JS |
2460 | } |
2461 | if (status & AR5K_INT_RXEOL) { | |
2462 | /* | |
2463 | * NB: the hardware should re-read the link when | |
2464 | * RXE bit is written, but it doesn't work at | |
2465 | * least on older hardware revs. | |
2466 | */ | |
2467 | sc->rxlink = NULL; | |
2468 | } | |
2469 | if (status & AR5K_INT_TXURN) { | |
2470 | /* bump tx trigger level */ | |
2471 | ath5k_hw_update_tx_triglevel(ah, true); | |
2472 | } | |
2473 | if (status & AR5K_INT_RX) | |
2474 | tasklet_schedule(&sc->rxtq); | |
2475 | if (status & AR5K_INT_TX) | |
2476 | tasklet_schedule(&sc->txtq); | |
2477 | if (status & AR5K_INT_BMISS) { | |
2478 | } | |
2479 | if (status & AR5K_INT_MIB) { | |
2480 | /* TODO */ | |
2481 | } | |
2482 | } | |
2483 | } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0); | |
2484 | ||
2485 | if (unlikely(!counter)) | |
2486 | ATH5K_WARN(sc, "too many interrupts, giving up for now\n"); | |
2487 | ||
2488 | return IRQ_HANDLED; | |
2489 | } | |
2490 | ||
2491 | static void | |
2492 | ath5k_tasklet_reset(unsigned long data) | |
2493 | { | |
2494 | struct ath5k_softc *sc = (void *)data; | |
2495 | ||
2496 | ath5k_reset(sc->hw); | |
2497 | } | |
2498 | ||
2499 | /* | |
2500 | * Periodically recalibrate the PHY to account | |
2501 | * for temperature/environment changes. | |
2502 | */ | |
2503 | static void | |
2504 | ath5k_calibrate(unsigned long data) | |
2505 | { | |
2506 | struct ath5k_softc *sc = (void *)data; | |
2507 | struct ath5k_hw *ah = sc->ah; | |
2508 | ||
2509 | ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n", | |
400ec45a LR |
2510 | ieee80211_frequency_to_channel(sc->curchan->center_freq), |
2511 | sc->curchan->hw_value); | |
fa1c114f JS |
2512 | |
2513 | if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) { | |
2514 | /* | |
2515 | * Rfgain is out of bounds, reset the chip | |
2516 | * to load new gain values. | |
2517 | */ | |
2518 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n"); | |
2519 | ath5k_reset(sc->hw); | |
2520 | } | |
2521 | if (ath5k_hw_phy_calibrate(ah, sc->curchan)) | |
2522 | ATH5K_ERR(sc, "calibration of channel %u failed\n", | |
400ec45a LR |
2523 | ieee80211_frequency_to_channel( |
2524 | sc->curchan->center_freq)); | |
fa1c114f JS |
2525 | |
2526 | mod_timer(&sc->calib_tim, round_jiffies(jiffies + | |
2527 | msecs_to_jiffies(ath5k_calinterval * 1000))); | |
2528 | } | |
2529 | ||
2530 | ||
2531 | ||
2532 | /***************\ | |
2533 | * LED functions * | |
2534 | \***************/ | |
2535 | ||
2536 | static void | |
2537 | ath5k_led_off(unsigned long data) | |
2538 | { | |
2539 | struct ath5k_softc *sc = (void *)data; | |
2540 | ||
2541 | if (test_bit(ATH_STAT_LEDENDBLINK, sc->status)) | |
2542 | __clear_bit(ATH_STAT_LEDBLINKING, sc->status); | |
2543 | else { | |
2544 | __set_bit(ATH_STAT_LEDENDBLINK, sc->status); | |
2545 | ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on); | |
2546 | mod_timer(&sc->led_tim, jiffies + sc->led_off); | |
2547 | } | |
2548 | } | |
2549 | ||
2550 | /* | |
2551 | * Blink the LED according to the specified on/off times. | |
2552 | */ | |
2553 | static void | |
2554 | ath5k_led_blink(struct ath5k_softc *sc, unsigned int on, | |
2555 | unsigned int off) | |
2556 | { | |
2557 | ATH5K_DBG(sc, ATH5K_DEBUG_LED, "on %u off %u\n", on, off); | |
2558 | ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on); | |
2559 | __set_bit(ATH_STAT_LEDBLINKING, sc->status); | |
2560 | __clear_bit(ATH_STAT_LEDENDBLINK, sc->status); | |
2561 | sc->led_off = off; | |
2562 | mod_timer(&sc->led_tim, jiffies + on); | |
2563 | } | |
2564 | ||
2565 | static void | |
2566 | ath5k_led_event(struct ath5k_softc *sc, int event) | |
2567 | { | |
2568 | if (likely(!test_bit(ATH_STAT_LEDSOFT, sc->status))) | |
2569 | return; | |
2570 | if (unlikely(test_bit(ATH_STAT_LEDBLINKING, sc->status))) | |
2571 | return; /* don't interrupt active blink */ | |
2572 | switch (event) { | |
2573 | case ATH_LED_TX: | |
2574 | ath5k_led_blink(sc, sc->hwmap[sc->led_txrate].ledon, | |
2575 | sc->hwmap[sc->led_txrate].ledoff); | |
2576 | break; | |
2577 | case ATH_LED_RX: | |
2578 | ath5k_led_blink(sc, sc->hwmap[sc->led_rxrate].ledon, | |
2579 | sc->hwmap[sc->led_rxrate].ledoff); | |
2580 | break; | |
2581 | } | |
2582 | } | |
2583 | ||
2584 | ||
2585 | ||
2586 | ||
2587 | /********************\ | |
2588 | * Mac80211 functions * | |
2589 | \********************/ | |
2590 | ||
2591 | static int | |
2592 | ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb, | |
2593 | struct ieee80211_tx_control *ctl) | |
2594 | { | |
2595 | struct ath5k_softc *sc = hw->priv; | |
2596 | struct ath5k_buf *bf; | |
2597 | unsigned long flags; | |
2598 | int hdrlen; | |
2599 | int pad; | |
2600 | ||
2601 | ath5k_debug_dump_skb(sc, skb, "TX ", 1); | |
2602 | ||
2603 | if (sc->opmode == IEEE80211_IF_TYPE_MNTR) | |
2604 | ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n"); | |
2605 | ||
2606 | /* | |
2607 | * the hardware expects the header padded to 4 byte boundaries | |
2608 | * if this is not the case we add the padding after the header | |
2609 | */ | |
2610 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); | |
2611 | if (hdrlen & 3) { | |
2612 | pad = hdrlen % 4; | |
2613 | if (skb_headroom(skb) < pad) { | |
2614 | ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough" | |
2615 | " headroom to pad %d\n", hdrlen, pad); | |
2616 | return -1; | |
2617 | } | |
2618 | skb_push(skb, pad); | |
2619 | memmove(skb->data, skb->data+pad, hdrlen); | |
2620 | } | |
2621 | ||
d8ee398d | 2622 | sc->led_txrate = ctl->tx_rate->hw_value; |
fa1c114f JS |
2623 | |
2624 | spin_lock_irqsave(&sc->txbuflock, flags); | |
2625 | if (list_empty(&sc->txbuf)) { | |
2626 | ATH5K_ERR(sc, "no further txbuf available, dropping packet\n"); | |
2627 | spin_unlock_irqrestore(&sc->txbuflock, flags); | |
2628 | ieee80211_stop_queue(hw, ctl->queue); | |
2629 | return -1; | |
2630 | } | |
2631 | bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list); | |
2632 | list_del(&bf->list); | |
2633 | sc->txbuf_len--; | |
2634 | if (list_empty(&sc->txbuf)) | |
2635 | ieee80211_stop_queues(hw); | |
2636 | spin_unlock_irqrestore(&sc->txbuflock, flags); | |
2637 | ||
2638 | bf->skb = skb; | |
2639 | ||
2640 | if (ath5k_txbuf_setup(sc, bf, ctl)) { | |
2641 | bf->skb = NULL; | |
2642 | spin_lock_irqsave(&sc->txbuflock, flags); | |
2643 | list_add_tail(&bf->list, &sc->txbuf); | |
2644 | sc->txbuf_len++; | |
2645 | spin_unlock_irqrestore(&sc->txbuflock, flags); | |
2646 | dev_kfree_skb_any(skb); | |
2647 | return 0; | |
2648 | } | |
2649 | ||
2650 | return 0; | |
2651 | } | |
2652 | ||
2653 | static int | |
2654 | ath5k_reset(struct ieee80211_hw *hw) | |
2655 | { | |
2656 | struct ath5k_softc *sc = hw->priv; | |
2657 | struct ath5k_hw *ah = sc->ah; | |
2658 | int ret; | |
2659 | ||
2660 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n"); | |
fa1c114f JS |
2661 | |
2662 | ath5k_hw_set_intr(ah, 0); | |
2663 | ath5k_txq_cleanup(sc); | |
2664 | ath5k_rx_stop(sc); | |
2665 | ||
2666 | ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true); | |
2667 | if (unlikely(ret)) { | |
2668 | ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret); | |
2669 | goto err; | |
2670 | } | |
2671 | ath5k_hw_set_txpower_limit(sc->ah, 0); | |
2672 | ||
2673 | ret = ath5k_rx_start(sc); | |
2674 | if (unlikely(ret)) { | |
2675 | ATH5K_ERR(sc, "can't start recv logic\n"); | |
2676 | goto err; | |
2677 | } | |
2678 | /* | |
2679 | * We may be doing a reset in response to an ioctl | |
2680 | * that changes the channel so update any state that | |
2681 | * might change as a result. | |
2682 | * | |
2683 | * XXX needed? | |
2684 | */ | |
2685 | /* ath5k_chan_change(sc, c); */ | |
2686 | ath5k_beacon_config(sc); | |
2687 | /* intrs are started by ath5k_beacon_config */ | |
2688 | ||
2689 | ieee80211_wake_queues(hw); | |
2690 | ||
2691 | return 0; | |
2692 | err: | |
2693 | return ret; | |
2694 | } | |
2695 | ||
2696 | static int ath5k_start(struct ieee80211_hw *hw) | |
2697 | { | |
2698 | return ath5k_init(hw->priv); | |
2699 | } | |
2700 | ||
2701 | static void ath5k_stop(struct ieee80211_hw *hw) | |
2702 | { | |
2703 | ath5k_stop_hw(hw->priv); | |
2704 | } | |
2705 | ||
2706 | static int ath5k_add_interface(struct ieee80211_hw *hw, | |
2707 | struct ieee80211_if_init_conf *conf) | |
2708 | { | |
2709 | struct ath5k_softc *sc = hw->priv; | |
2710 | int ret; | |
2711 | ||
2712 | mutex_lock(&sc->lock); | |
32bfd35d | 2713 | if (sc->vif) { |
fa1c114f JS |
2714 | ret = 0; |
2715 | goto end; | |
2716 | } | |
2717 | ||
32bfd35d | 2718 | sc->vif = conf->vif; |
fa1c114f JS |
2719 | |
2720 | switch (conf->type) { | |
2721 | case IEEE80211_IF_TYPE_STA: | |
2722 | case IEEE80211_IF_TYPE_IBSS: | |
2723 | case IEEE80211_IF_TYPE_MNTR: | |
2724 | sc->opmode = conf->type; | |
2725 | break; | |
2726 | default: | |
2727 | ret = -EOPNOTSUPP; | |
2728 | goto end; | |
2729 | } | |
2730 | ret = 0; | |
2731 | end: | |
2732 | mutex_unlock(&sc->lock); | |
2733 | return ret; | |
2734 | } | |
2735 | ||
2736 | static void | |
2737 | ath5k_remove_interface(struct ieee80211_hw *hw, | |
2738 | struct ieee80211_if_init_conf *conf) | |
2739 | { | |
2740 | struct ath5k_softc *sc = hw->priv; | |
2741 | ||
2742 | mutex_lock(&sc->lock); | |
32bfd35d | 2743 | if (sc->vif != conf->vif) |
fa1c114f JS |
2744 | goto end; |
2745 | ||
32bfd35d | 2746 | sc->vif = NULL; |
fa1c114f JS |
2747 | end: |
2748 | mutex_unlock(&sc->lock); | |
2749 | } | |
2750 | ||
d8ee398d LR |
2751 | /* |
2752 | * TODO: Phy disable/diversity etc | |
2753 | */ | |
fa1c114f JS |
2754 | static int |
2755 | ath5k_config(struct ieee80211_hw *hw, | |
2756 | struct ieee80211_conf *conf) | |
2757 | { | |
2758 | struct ath5k_softc *sc = hw->priv; | |
2759 | ||
e535c1ac | 2760 | sc->bintval = conf->beacon_int; |
d8ee398d | 2761 | sc->power_level = conf->power_level; |
fa1c114f | 2762 | |
d8ee398d | 2763 | return ath5k_chan_set(sc, conf->channel); |
fa1c114f JS |
2764 | } |
2765 | ||
2766 | static int | |
32bfd35d | 2767 | ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
fa1c114f JS |
2768 | struct ieee80211_if_conf *conf) |
2769 | { | |
2770 | struct ath5k_softc *sc = hw->priv; | |
2771 | struct ath5k_hw *ah = sc->ah; | |
2772 | int ret; | |
2773 | ||
2774 | /* Set to a reasonable value. Note that this will | |
2775 | * be set to mac80211's value at ath5k_config(). */ | |
e535c1ac | 2776 | sc->bintval = 1000; |
fa1c114f | 2777 | mutex_lock(&sc->lock); |
32bfd35d | 2778 | if (sc->vif != vif) { |
fa1c114f JS |
2779 | ret = -EIO; |
2780 | goto unlock; | |
2781 | } | |
2782 | if (conf->bssid) { | |
2783 | /* Cache for later use during resets */ | |
2784 | memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN); | |
2785 | /* XXX: assoc id is set to 0 for now, mac80211 doesn't have | |
2786 | * a clean way of letting us retrieve this yet. */ | |
2787 | ath5k_hw_set_associd(ah, ah->ah_bssid, 0); | |
2788 | } | |
2789 | mutex_unlock(&sc->lock); | |
2790 | ||
2791 | return ath5k_reset(hw); | |
2792 | unlock: | |
2793 | mutex_unlock(&sc->lock); | |
2794 | return ret; | |
2795 | } | |
2796 | ||
2797 | #define SUPPORTED_FIF_FLAGS \ | |
2798 | FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \ | |
2799 | FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \ | |
2800 | FIF_BCN_PRBRESP_PROMISC | |
2801 | /* | |
2802 | * o always accept unicast, broadcast, and multicast traffic | |
2803 | * o multicast traffic for all BSSIDs will be enabled if mac80211 | |
2804 | * says it should be | |
2805 | * o maintain current state of phy ofdm or phy cck error reception. | |
2806 | * If the hardware detects any of these type of errors then | |
2807 | * ath5k_hw_get_rx_filter() will pass to us the respective | |
2808 | * hardware filters to be able to receive these type of frames. | |
2809 | * o probe request frames are accepted only when operating in | |
2810 | * hostap, adhoc, or monitor modes | |
2811 | * o enable promiscuous mode according to the interface state | |
2812 | * o accept beacons: | |
2813 | * - when operating in adhoc mode so the 802.11 layer creates | |
2814 | * node table entries for peers, | |
2815 | * - when operating in station mode for collecting rssi data when | |
2816 | * the station is otherwise quiet, or | |
2817 | * - when scanning | |
2818 | */ | |
2819 | static void ath5k_configure_filter(struct ieee80211_hw *hw, | |
2820 | unsigned int changed_flags, | |
2821 | unsigned int *new_flags, | |
2822 | int mc_count, struct dev_mc_list *mclist) | |
2823 | { | |
2824 | struct ath5k_softc *sc = hw->priv; | |
2825 | struct ath5k_hw *ah = sc->ah; | |
2826 | u32 mfilt[2], val, rfilt; | |
2827 | u8 pos; | |
2828 | int i; | |
2829 | ||
2830 | mfilt[0] = 0; | |
2831 | mfilt[1] = 0; | |
2832 | ||
2833 | /* Only deal with supported flags */ | |
2834 | changed_flags &= SUPPORTED_FIF_FLAGS; | |
2835 | *new_flags &= SUPPORTED_FIF_FLAGS; | |
2836 | ||
2837 | /* If HW detects any phy or radar errors, leave those filters on. | |
2838 | * Also, always enable Unicast, Broadcasts and Multicast | |
2839 | * XXX: move unicast, bssid broadcasts and multicast to mac80211 */ | |
2840 | rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) | | |
2841 | (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST | | |
2842 | AR5K_RX_FILTER_MCAST); | |
2843 | ||
2844 | if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) { | |
2845 | if (*new_flags & FIF_PROMISC_IN_BSS) { | |
2846 | rfilt |= AR5K_RX_FILTER_PROM; | |
2847 | __set_bit(ATH_STAT_PROMISC, sc->status); | |
2848 | } | |
2849 | else | |
2850 | __clear_bit(ATH_STAT_PROMISC, sc->status); | |
2851 | } | |
2852 | ||
2853 | /* Note, AR5K_RX_FILTER_MCAST is already enabled */ | |
2854 | if (*new_flags & FIF_ALLMULTI) { | |
2855 | mfilt[0] = ~0; | |
2856 | mfilt[1] = ~0; | |
2857 | } else { | |
2858 | for (i = 0; i < mc_count; i++) { | |
2859 | if (!mclist) | |
2860 | break; | |
2861 | /* calculate XOR of eight 6-bit values */ | |
2862 | val = LE_READ_4(mclist->dmi_addr + 0); | |
2863 | pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; | |
2864 | val = LE_READ_4(mclist->dmi_addr + 3); | |
2865 | pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; | |
2866 | pos &= 0x3f; | |
2867 | mfilt[pos / 32] |= (1 << (pos % 32)); | |
2868 | /* XXX: we might be able to just do this instead, | |
2869 | * but not sure, needs testing, if we do use this we'd | |
2870 | * neet to inform below to not reset the mcast */ | |
2871 | /* ath5k_hw_set_mcast_filterindex(ah, | |
2872 | * mclist->dmi_addr[5]); */ | |
2873 | mclist = mclist->next; | |
2874 | } | |
2875 | } | |
2876 | ||
2877 | /* This is the best we can do */ | |
2878 | if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL)) | |
2879 | rfilt |= AR5K_RX_FILTER_PHYERR; | |
2880 | ||
2881 | /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons | |
2882 | * and probes for any BSSID, this needs testing */ | |
2883 | if (*new_flags & FIF_BCN_PRBRESP_PROMISC) | |
2884 | rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ; | |
2885 | ||
2886 | /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not | |
2887 | * set we should only pass on control frames for this | |
2888 | * station. This needs testing. I believe right now this | |
2889 | * enables *all* control frames, which is OK.. but | |
2890 | * but we should see if we can improve on granularity */ | |
2891 | if (*new_flags & FIF_CONTROL) | |
2892 | rfilt |= AR5K_RX_FILTER_CONTROL; | |
2893 | ||
2894 | /* Additional settings per mode -- this is per ath5k */ | |
2895 | ||
2896 | /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */ | |
2897 | ||
2898 | if (sc->opmode == IEEE80211_IF_TYPE_MNTR) | |
2899 | rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON | | |
2900 | AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM; | |
2901 | if (sc->opmode != IEEE80211_IF_TYPE_STA) | |
2902 | rfilt |= AR5K_RX_FILTER_PROBEREQ; | |
2903 | if (sc->opmode != IEEE80211_IF_TYPE_AP && | |
2904 | test_bit(ATH_STAT_PROMISC, sc->status)) | |
2905 | rfilt |= AR5K_RX_FILTER_PROM; | |
2906 | if (sc->opmode == IEEE80211_IF_TYPE_STA || | |
2907 | sc->opmode == IEEE80211_IF_TYPE_IBSS) { | |
2908 | rfilt |= AR5K_RX_FILTER_BEACON; | |
2909 | } | |
2910 | ||
2911 | /* Set filters */ | |
2912 | ath5k_hw_set_rx_filter(ah,rfilt); | |
2913 | ||
2914 | /* Set multicast bits */ | |
2915 | ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]); | |
2916 | /* Set the cached hw filter flags, this will alter actually | |
2917 | * be set in HW */ | |
2918 | sc->filter_flags = rfilt; | |
2919 | } | |
2920 | ||
2921 | static int | |
2922 | ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, | |
2923 | const u8 *local_addr, const u8 *addr, | |
2924 | struct ieee80211_key_conf *key) | |
2925 | { | |
2926 | struct ath5k_softc *sc = hw->priv; | |
2927 | int ret = 0; | |
2928 | ||
2929 | switch(key->alg) { | |
2930 | case ALG_WEP: | |
6844e63a LR |
2931 | /* XXX: fix hardware encryption, its not working. For now |
2932 | * allow software encryption */ | |
2933 | /* break; */ | |
fa1c114f JS |
2934 | case ALG_TKIP: |
2935 | case ALG_CCMP: | |
2936 | return -EOPNOTSUPP; | |
2937 | default: | |
2938 | WARN_ON(1); | |
2939 | return -EINVAL; | |
2940 | } | |
2941 | ||
2942 | mutex_lock(&sc->lock); | |
2943 | ||
2944 | switch (cmd) { | |
2945 | case SET_KEY: | |
2946 | ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr); | |
2947 | if (ret) { | |
2948 | ATH5K_ERR(sc, "can't set the key\n"); | |
2949 | goto unlock; | |
2950 | } | |
2951 | __set_bit(key->keyidx, sc->keymap); | |
2952 | key->hw_key_idx = key->keyidx; | |
2953 | break; | |
2954 | case DISABLE_KEY: | |
2955 | ath5k_hw_reset_key(sc->ah, key->keyidx); | |
2956 | __clear_bit(key->keyidx, sc->keymap); | |
2957 | break; | |
2958 | default: | |
2959 | ret = -EINVAL; | |
2960 | goto unlock; | |
2961 | } | |
2962 | ||
2963 | unlock: | |
2964 | mutex_unlock(&sc->lock); | |
2965 | return ret; | |
2966 | } | |
2967 | ||
2968 | static int | |
2969 | ath5k_get_stats(struct ieee80211_hw *hw, | |
2970 | struct ieee80211_low_level_stats *stats) | |
2971 | { | |
2972 | struct ath5k_softc *sc = hw->priv; | |
2973 | ||
2974 | memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats)); | |
2975 | ||
2976 | return 0; | |
2977 | } | |
2978 | ||
2979 | static int | |
2980 | ath5k_get_tx_stats(struct ieee80211_hw *hw, | |
2981 | struct ieee80211_tx_queue_stats *stats) | |
2982 | { | |
2983 | struct ath5k_softc *sc = hw->priv; | |
2984 | ||
2985 | memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats)); | |
2986 | ||
2987 | return 0; | |
2988 | } | |
2989 | ||
2990 | static u64 | |
2991 | ath5k_get_tsf(struct ieee80211_hw *hw) | |
2992 | { | |
2993 | struct ath5k_softc *sc = hw->priv; | |
2994 | ||
2995 | return ath5k_hw_get_tsf64(sc->ah); | |
2996 | } | |
2997 | ||
2998 | static void | |
2999 | ath5k_reset_tsf(struct ieee80211_hw *hw) | |
3000 | { | |
3001 | struct ath5k_softc *sc = hw->priv; | |
3002 | ||
9804b98d BR |
3003 | /* |
3004 | * in IBSS mode we need to update the beacon timers too. | |
3005 | * this will also reset the TSF if we call it with 0 | |
3006 | */ | |
3007 | if (sc->opmode == IEEE80211_IF_TYPE_IBSS) | |
3008 | ath5k_beacon_update_timers(sc, 0); | |
3009 | else | |
3010 | ath5k_hw_reset_tsf(sc->ah); | |
fa1c114f JS |
3011 | } |
3012 | ||
3013 | static int | |
3014 | ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb, | |
3015 | struct ieee80211_tx_control *ctl) | |
3016 | { | |
3017 | struct ath5k_softc *sc = hw->priv; | |
3018 | int ret; | |
3019 | ||
3020 | ath5k_debug_dump_skb(sc, skb, "BC ", 1); | |
3021 | ||
3022 | mutex_lock(&sc->lock); | |
3023 | ||
3024 | if (sc->opmode != IEEE80211_IF_TYPE_IBSS) { | |
3025 | ret = -EIO; | |
3026 | goto end; | |
3027 | } | |
3028 | ||
3029 | ath5k_txbuf_free(sc, sc->bbuf); | |
3030 | sc->bbuf->skb = skb; | |
3031 | ret = ath5k_beacon_setup(sc, sc->bbuf, ctl); | |
3032 | if (ret) | |
3033 | sc->bbuf->skb = NULL; | |
3034 | else | |
3035 | ath5k_beacon_config(sc); | |
3036 | ||
3037 | end: | |
3038 | mutex_unlock(&sc->lock); | |
3039 | return ret; | |
3040 | } | |
3041 |