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ath5k: Port to new bitrate/channel API
[deliverable/linux.git] / drivers / net / wireless / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
43#include <linux/version.h>
44#include <linux/module.h>
45#include <linux/delay.h>
46#include <linux/if.h>
47#include <linux/netdevice.h>
48#include <linux/cache.h>
49#include <linux/pci.h>
50#include <linux/ethtool.h>
51#include <linux/uaccess.h>
52
53#include <net/ieee80211_radiotap.h>
54
55#include <asm/unaligned.h>
56
57#include "base.h"
58#include "reg.h"
59#include "debug.h"
60
61/* unaligned little endian access */
62#define LE_READ_2(_p) (le16_to_cpu(get_unaligned((__le16 *)(_p))))
63#define LE_READ_4(_p) (le32_to_cpu(get_unaligned((__le32 *)(_p))))
64
65enum {
66 ATH_LED_TX,
67 ATH_LED_RX,
68};
69
70static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
71
72
73/******************\
74* Internal defines *
75\******************/
76
77/* Module info */
78MODULE_AUTHOR("Jiri Slaby");
79MODULE_AUTHOR("Nick Kossifidis");
80MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
81MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
82MODULE_LICENSE("Dual BSD/GPL");
83MODULE_VERSION("0.1.1 (EXPERIMENTAL)");
84
85
86/* Known PCI ids */
87static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
88 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
89 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
90 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
91 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
92 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
93 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
94 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
96 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
103 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
104 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/
105 { PCI_VDEVICE(ATHEROS, 0x0023), .driver_data = AR5K_AR5212 }, /* 5416 */
106 { PCI_VDEVICE(ATHEROS, 0x0024), .driver_data = AR5K_AR5212 }, /* 5418 */
107 { 0 }
108};
109MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
110
111/* Known SREVs */
112static struct ath5k_srev_name srev_names[] = {
113 { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 },
114 { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 },
115 { "5311A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },
116 { "5311B", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },
117 { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 },
118 { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 },
119 { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 },
120 { "5213A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213A },
121 { "2424", AR5K_VERSION_VER, AR5K_SREV_VER_AR2424 },
122 { "5424", AR5K_VERSION_VER, AR5K_SREV_VER_AR5424 },
123 { "5413", AR5K_VERSION_VER, AR5K_SREV_VER_AR5413 },
124 { "5414", AR5K_VERSION_VER, AR5K_SREV_VER_AR5414 },
125 { "5416", AR5K_VERSION_VER, AR5K_SREV_VER_AR5416 },
126 { "5418", AR5K_VERSION_VER, AR5K_SREV_VER_AR5418 },
127 { "xxxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN },
128 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
129 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
130 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
131 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
132 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
133 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
134 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
135 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC1 },
136 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC2 },
137 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
138 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
139};
140
141/*
142 * Prototypes - PCI stack related functions
143 */
144static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
145 const struct pci_device_id *id);
146static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
147#ifdef CONFIG_PM
148static int ath5k_pci_suspend(struct pci_dev *pdev,
149 pm_message_t state);
150static int ath5k_pci_resume(struct pci_dev *pdev);
151#else
152#define ath5k_pci_suspend NULL
153#define ath5k_pci_resume NULL
154#endif /* CONFIG_PM */
155
04a9e451 156static struct pci_driver ath5k_pci_driver = {
fa1c114f
JS		 157 .name = "ath5k_pci",
158 .id_table = ath5k_pci_id_table,
159 .probe = ath5k_pci_probe,
160 .remove = __devexit_p(ath5k_pci_remove),
161 .suspend = ath5k_pci_suspend,
162 .resume = ath5k_pci_resume,
163};
164
165
166
167/*
168 * Prototypes - MAC 802.11 stack related functions
169 */
170static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
171 struct ieee80211_tx_control *ctl);
172static int ath5k_reset(struct ieee80211_hw *hw);
173static int ath5k_start(struct ieee80211_hw *hw);
174static void ath5k_stop(struct ieee80211_hw *hw);
175static int ath5k_add_interface(struct ieee80211_hw *hw,
176 struct ieee80211_if_init_conf *conf);
177static void ath5k_remove_interface(struct ieee80211_hw *hw,
178 struct ieee80211_if_init_conf *conf);
179static int ath5k_config(struct ieee80211_hw *hw,
180 struct ieee80211_conf *conf);
32bfd35d
JB		 181static int ath5k_config_interface(struct ieee80211_hw *hw,
182 struct ieee80211_vif *vif,
fa1c114f
JS		 183 struct ieee80211_if_conf *conf);
184static void ath5k_configure_filter(struct ieee80211_hw *hw,
185 unsigned int changed_flags,
186 unsigned int *new_flags,
187 int mc_count, struct dev_mc_list *mclist);
188static int ath5k_set_key(struct ieee80211_hw *hw,
189 enum set_key_cmd cmd,
190 const u8 *local_addr, const u8 *addr,
191 struct ieee80211_key_conf *key);
192static int ath5k_get_stats(struct ieee80211_hw *hw,
193 struct ieee80211_low_level_stats *stats);
194static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
195 struct ieee80211_tx_queue_stats *stats);
196static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
197static void ath5k_reset_tsf(struct ieee80211_hw *hw);
198static int ath5k_beacon_update(struct ieee80211_hw *hw,
199 struct sk_buff *skb,
200 struct ieee80211_tx_control *ctl);
201
202static struct ieee80211_ops ath5k_hw_ops = {
203 .tx = ath5k_tx,
204 .start = ath5k_start,
205 .stop = ath5k_stop,
206 .add_interface = ath5k_add_interface,
207 .remove_interface = ath5k_remove_interface,
208 .config = ath5k_config,
209 .config_interface = ath5k_config_interface,
210 .configure_filter = ath5k_configure_filter,
211 .set_key = ath5k_set_key,
212 .get_stats = ath5k_get_stats,
213 .conf_tx = NULL,
214 .get_tx_stats = ath5k_get_tx_stats,
215 .get_tsf = ath5k_get_tsf,
216 .reset_tsf = ath5k_reset_tsf,
217 .beacon_update = ath5k_beacon_update,
218};
219
220/*
221 * Prototypes - Internal functions
222 */
223/* Attach detach */
224static int ath5k_attach(struct pci_dev *pdev,
225 struct ieee80211_hw *hw);
226static void ath5k_detach(struct pci_dev *pdev,
227 struct ieee80211_hw *hw);
228/* Channel/mode setup */
229static inline short ath5k_ieee2mhz(short chan);
230static unsigned int ath5k_copy_rates(struct ieee80211_rate *rates,
231 const struct ath5k_rate_table *rt,
232 unsigned int max);
233static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
234 struct ieee80211_channel *channels,
235 unsigned int mode,
236 unsigned int max);
237static int ath5k_getchannels(struct ieee80211_hw *hw);
238static int ath5k_chan_set(struct ath5k_softc *sc,
239 struct ieee80211_channel *chan);
240static void ath5k_setcurmode(struct ath5k_softc *sc,
241 unsigned int mode);
242static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d
LR		 243static void ath5k_set_total_hw_rates(struct ath5k_softc *sc);
244
fa1c114f
JS		 245/* Descriptor setup */
246static int ath5k_desc_alloc(struct ath5k_softc *sc,
247 struct pci_dev *pdev);
248static void ath5k_desc_free(struct ath5k_softc *sc,
249 struct pci_dev *pdev);
250/* Buffers setup */
251static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
252 struct ath5k_buf *bf);
253static int ath5k_txbuf_setup(struct ath5k_softc *sc,
254 struct ath5k_buf *bf,
255 struct ieee80211_tx_control *ctl);
256
257static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
258 struct ath5k_buf *bf)
259{
260 BUG_ON(!bf);
261 if (!bf->skb)
262 return;
263 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
264 PCI_DMA_TODEVICE);
265 dev_kfree_skb(bf->skb);
266 bf->skb = NULL;
267}
268
269/* Queues setup */
270static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
271 int qtype, int subtype);
272static int ath5k_beaconq_setup(struct ath5k_hw *ah);
273static int ath5k_beaconq_config(struct ath5k_softc *sc);
274static void ath5k_txq_drainq(struct ath5k_softc *sc,
275 struct ath5k_txq *txq);
276static void ath5k_txq_cleanup(struct ath5k_softc *sc);
277static void ath5k_txq_release(struct ath5k_softc *sc);
278/* Rx handling */
279static int ath5k_rx_start(struct ath5k_softc *sc);
280static void ath5k_rx_stop(struct ath5k_softc *sc);
281static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
282 struct ath5k_desc *ds,
283 struct sk_buff *skb);
284static void ath5k_tasklet_rx(unsigned long data);
285/* Tx handling */
286static void ath5k_tx_processq(struct ath5k_softc *sc,
287 struct ath5k_txq *txq);
288static void ath5k_tasklet_tx(unsigned long data);
289/* Beacon handling */
290static int ath5k_beacon_setup(struct ath5k_softc *sc,
291 struct ath5k_buf *bf,
292 struct ieee80211_tx_control *ctl);
293static void ath5k_beacon_send(struct ath5k_softc *sc);
294static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 295static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f
JS		 296
297static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
298{
299 u64 tsf = ath5k_hw_get_tsf64(ah);
300
301 if ((tsf & 0x7fff) < rstamp)
302 tsf -= 0x8000;
303
304 return (tsf & ~0x7fff) | rstamp;
305}
306
307/* Interrupt handling */
308static int ath5k_init(struct ath5k_softc *sc);
309static int ath5k_stop_locked(struct ath5k_softc *sc);
310static int ath5k_stop_hw(struct ath5k_softc *sc);
311static irqreturn_t ath5k_intr(int irq, void *dev_id);
312static void ath5k_tasklet_reset(unsigned long data);
313
314static void ath5k_calibrate(unsigned long data);
315/* LED functions */
316static void ath5k_led_off(unsigned long data);
317static void ath5k_led_blink(struct ath5k_softc *sc,
318 unsigned int on,
319 unsigned int off);
320static void ath5k_led_event(struct ath5k_softc *sc,
321 int event);
322
323
324/*
325 * Module init/exit functions
326 */
327static int __init
328init_ath5k_pci(void)
329{
330 int ret;
331
332 ath5k_debug_init();
333
04a9e451 334 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 335 if (ret) {
336 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
337 return ret;
338 }
339
340 return 0;
341}
342
343static void __exit
344exit_ath5k_pci(void)
345{
04a9e451 346 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 347
348 ath5k_debug_finish();
349}
350
351module_init(init_ath5k_pci);
352module_exit(exit_ath5k_pci);
353
354
355/********************\
356* PCI Initialization *
357\********************/
358
359static const char *
360ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
361{
362 const char *name = "xxxxx";
363 unsigned int i;
364
365 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
366 if (srev_names[i].sr_type != type)
367 continue;
368 if ((val & 0xff) < srev_names[i + 1].sr_val) {
369 name = srev_names[i].sr_name;
370 break;
371 }
372 }
373
374 return name;
375}
376
377static int __devinit
378ath5k_pci_probe(struct pci_dev *pdev,
379 const struct pci_device_id *id)
380{
381 void __iomem *mem;
382 struct ath5k_softc *sc;
383 struct ieee80211_hw *hw;
384 int ret;
385 u8 csz;
386
387 ret = pci_enable_device(pdev);
388 if (ret) {
389 dev_err(&pdev->dev, "can't enable device\n");
390 goto err;
391 }
392
393 /* XXX 32-bit addressing only */
394 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
395 if (ret) {
396 dev_err(&pdev->dev, "32-bit DMA not available\n");
397 goto err_dis;
398 }
399
400 /*
401 * Cache line size is used to size and align various
402 * structures used to communicate with the hardware.
403 */
404 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
405 if (csz == 0) {
406 /*
407 * Linux 2.4.18 (at least) writes the cache line size
408 * register as a 16-bit wide register which is wrong.
409 * We must have this setup properly for rx buffer
410 * DMA to work so force a reasonable value here if it
411 * comes up zero.
412 */
413 csz = L1_CACHE_BYTES / sizeof(u32);
414 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
415 }
416 /*
417 * The default setting of latency timer yields poor results,
418 * set it to the value used by other systems. It may be worth
419 * tweaking this setting more.
420 */
421 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
422
423 /* Enable bus mastering */
424 pci_set_master(pdev);
425
426 /*
427 * Disable the RETRY_TIMEOUT register (0x41) to keep
428 * PCI Tx retries from interfering with C3 CPU state.
429 */
430 pci_write_config_byte(pdev, 0x41, 0);
431
432 ret = pci_request_region(pdev, 0, "ath5k");
433 if (ret) {
434 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
435 goto err_dis;
436 }
437
438 mem = pci_iomap(pdev, 0, 0);
439 if (!mem) {
440 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
441 ret = -EIO;
442 goto err_reg;
443 }
444
445 /*
446 * Allocate hw (mac80211 main struct)
447 * and hw->priv (driver private data)
448 */
449 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
450 if (hw == NULL) {
451 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
452 ret = -ENOMEM;
453 goto err_map;
454 }
455
456 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
457
458 /* Initialize driver private data */
459 SET_IEEE80211_DEV(hw, &pdev->dev);
460 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS;
461 hw->extra_tx_headroom = 2;
462 hw->channel_change_time = 5000;
463 /* these names are misleading */
464 hw->max_rssi = -110; /* signal in dBm */
465 hw->max_noise = -110; /* noise in dBm */
466 hw->max_signal = 100; /* we will provide a percentage based on rssi */
467 sc = hw->priv;
468 sc->hw = hw;
469 sc->pdev = pdev;
470
471 ath5k_debug_init_device(sc);
472
473 /*
474 * Mark the device as detached to avoid processing
475 * interrupts until setup is complete.
476 */
477 __set_bit(ATH_STAT_INVALID, sc->status);
478
479 sc->iobase = mem; /* So we can unmap it on detach */
480 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
481 sc->opmode = IEEE80211_IF_TYPE_STA;
482 mutex_init(&sc->lock);
483 spin_lock_init(&sc->rxbuflock);
484 spin_lock_init(&sc->txbuflock);
485
486 /* Set private data */
487 pci_set_drvdata(pdev, hw);
488
489 /* Enable msi for devices that support it */
490 pci_enable_msi(pdev);
491
492 /* Setup interrupt handler */
493 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
494 if (ret) {
495 ATH5K_ERR(sc, "request_irq failed\n");
496 goto err_free;
497 }
498
499 /* Initialize device */
500 sc->ah = ath5k_hw_attach(sc, id->driver_data);
501 if (IS_ERR(sc->ah)) {
502 ret = PTR_ERR(sc->ah);
503 goto err_irq;
504 }
505
506 /* Finish private driver data initialization */
507 ret = ath5k_attach(pdev, hw);
508 if (ret)
509 goto err_ah;
510
511 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
512 ath5k_chip_name(AR5K_VERSION_VER,sc->ah->ah_mac_srev),
513 sc->ah->ah_mac_srev,
514 sc->ah->ah_phy_revision);
515
516 if(!sc->ah->ah_single_chip){
517 /* Single chip radio (!RF5111) */
518 if(sc->ah->ah_radio_5ghz_revision && !sc->ah->ah_radio_2ghz_revision) {
519 /* No 5GHz support -> report 2GHz radio */
d8ee398d 520 if(!test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)){
fa1c114f
JS		 521 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
522 ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_5ghz_revision),
523 sc->ah->ah_radio_5ghz_revision);
524 /* No 2GHz support (5110 and some 5Ghz only cards) -> report 5Ghz radio */
d8ee398d 525 } else if(!test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)){
fa1c114f
JS		 526 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
527 ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_5ghz_revision),
528 sc->ah->ah_radio_5ghz_revision);
529 /* Multiband radio */
530 } else {
531 ATH5K_INFO(sc, "RF%s multiband radio found"
532 " (0x%x)\n",
533 ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_5ghz_revision),
534 sc->ah->ah_radio_5ghz_revision);
535 }
536 }
537 /* Multi chip radio (RF5111 - RF2111) -> report both 2GHz/5GHz radios */
538 else if(sc->ah->ah_radio_5ghz_revision && sc->ah->ah_radio_2ghz_revision){
539 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
540 ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_5ghz_revision),
541 sc->ah->ah_radio_5ghz_revision);
542 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
543 ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_2ghz_revision),
544 sc->ah->ah_radio_2ghz_revision);
545 }
546 }
547
548
549 /* ready to process interrupts */
550 __clear_bit(ATH_STAT_INVALID, sc->status);
551
552 return 0;
553err_ah:
554 ath5k_hw_detach(sc->ah);
555err_irq:
556 free_irq(pdev->irq, sc);
557err_free:
558 pci_disable_msi(pdev);
559 ieee80211_free_hw(hw);
560err_map:
561 pci_iounmap(pdev, mem);
562err_reg:
563 pci_release_region(pdev, 0);
564err_dis:
565 pci_disable_device(pdev);
566err:
567 return ret;
568}
569
570static void __devexit
571ath5k_pci_remove(struct pci_dev *pdev)
572{
573 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
574 struct ath5k_softc *sc = hw->priv;
575
576 ath5k_debug_finish_device(sc);
577 ath5k_detach(pdev, hw);
578 ath5k_hw_detach(sc->ah);
579 free_irq(pdev->irq, sc);
580 pci_disable_msi(pdev);
581 pci_iounmap(pdev, sc->iobase);
582 pci_release_region(pdev, 0);
583 pci_disable_device(pdev);
584 ieee80211_free_hw(hw);
585}
586
587#ifdef CONFIG_PM
588static int
589ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
590{
591 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
592 struct ath5k_softc *sc = hw->priv;
593
594 if (test_bit(ATH_STAT_LEDSOFT, sc->status))
595 ath5k_hw_set_gpio(sc->ah, sc->led_pin, 1);
596
597 ath5k_stop_hw(sc);
598 pci_save_state(pdev);
599 pci_disable_device(pdev);
600 pci_set_power_state(pdev, PCI_D3hot);
601
602 return 0;
603}
604
605static int
606ath5k_pci_resume(struct pci_dev *pdev)
607{
608 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
609 struct ath5k_softc *sc = hw->priv;
247ae449
JL		 610 struct ath5k_hw *ah = sc->ah;
611 int i, err;
fa1c114f
JS		 612
613 err = pci_set_power_state(pdev, PCI_D0);
614 if (err)
615 return err;
616
617 err = pci_enable_device(pdev);
618 if (err)
619 return err;
620
621 pci_restore_state(pdev);
622 /*
623 * Suspend/Resume resets the PCI configuration space, so we have to
624 * re-disable the RETRY_TIMEOUT register (0x41) to keep
625 * PCI Tx retries from interfering with C3 CPU state
626 */
627 pci_write_config_byte(pdev, 0x41, 0);
628
629 ath5k_init(sc);
630 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
247ae449
JL		 631 ath5k_hw_set_gpio_output(ah, sc->led_pin);
632 ath5k_hw_set_gpio(ah, sc->led_pin, 0);
fa1c114f
JS		 633 }
634
247ae449
JL		 635 /*
636 * Reset the key cache since some parts do not
637 * reset the contents on initial power up or resume.
638 *
639 * FIXME: This may need to be revisited when mac80211 becomes
640 * aware of suspend/resume.
641 */
642 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
643 ath5k_hw_reset_key(ah, i);
644
fa1c114f
JS		 645 return 0;
646}
647#endif /* CONFIG_PM */
648
649
650
651/***********************\
652* Driver Initialization *
653\***********************/
654
655static int
656ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
657{
658 struct ath5k_softc *sc = hw->priv;
659 struct ath5k_hw *ah = sc->ah;
660 u8 mac[ETH_ALEN];
661 unsigned int i;
662 int ret;
663
664 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
665
666 /*
667 * Check if the MAC has multi-rate retry support.
668 * We do this by trying to setup a fake extended
669 * descriptor. MAC's that don't have support will
670 * return false w/o doing anything. MAC's that do
671 * support it will return true w/o doing anything.
672 */
b9887638
JS		 673 ret = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
674 if (ret < 0)
675 goto err;
676 if (ret > 0)
fa1c114f
JS		 677 __set_bit(ATH_STAT_MRRETRY, sc->status);
678
679 /*
680 * Reset the key cache since some parts do not
681 * reset the contents on initial power up.
682 */
c65638a7 683 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
fa1c114f
JS		 684 ath5k_hw_reset_key(ah, i);
685
686 /*
687 * Collect the channel list. The 802.11 layer
688 * is resposible for filtering this list based
689 * on settings like the phy mode and regulatory
690 * domain restrictions.
691 */
692 ret = ath5k_getchannels(hw);
693 if (ret) {
694 ATH5K_ERR(sc, "can't get channels\n");
695 goto err;
696 }
697
d8ee398d
LR		 698 /* Set *_rates so we can map hw rate index */
699 ath5k_set_total_hw_rates(sc);
700
fa1c114f 701 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 702 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
703 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 704 else
d8ee398d 705 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 706
707 /*
708 * Allocate tx+rx descriptors and populate the lists.
709 */
710 ret = ath5k_desc_alloc(sc, pdev);
711 if (ret) {
712 ATH5K_ERR(sc, "can't allocate descriptors\n");
713 goto err;
714 }
715
716 /*
717 * Allocate hardware transmit queues: one queue for
718 * beacon frames and one data queue for each QoS
719 * priority. Note that hw functions handle reseting
720 * these queues at the needed time.
721 */
722 ret = ath5k_beaconq_setup(ah);
723 if (ret < 0) {
724 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
725 goto err_desc;
726 }
727 sc->bhalq = ret;
728
729 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
730 if (IS_ERR(sc->txq)) {
731 ATH5K_ERR(sc, "can't setup xmit queue\n");
732 ret = PTR_ERR(sc->txq);
733 goto err_bhal;
734 }
735
736 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
737 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
738 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
739 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
740 setup_timer(&sc->led_tim, ath5k_led_off, (unsigned long)sc);
741
742 sc->led_on = 0; /* low true */
743 /*
744 * Auto-enable soft led processing for IBM cards and for
745 * 5211 minipci cards.
746 */
747 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
748 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
749 __set_bit(ATH_STAT_LEDSOFT, sc->status);
750 sc->led_pin = 0;
751 }
752 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
753 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
754 __set_bit(ATH_STAT_LEDSOFT, sc->status);
755 sc->led_pin = 0;
756 }
757 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
758 ath5k_hw_set_gpio_output(ah, sc->led_pin);
759 ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on);
760 }
761
762 ath5k_hw_get_lladdr(ah, mac);
763 SET_IEEE80211_PERM_ADDR(hw, mac);
764 /* All MAC address bits matter for ACKs */
765 memset(sc->bssidmask, 0xff, ETH_ALEN);
766 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
767
768 ret = ieee80211_register_hw(hw);
769 if (ret) {
770 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
771 goto err_queues;
772 }
773
774 return 0;
775err_queues:
776 ath5k_txq_release(sc);
777err_bhal:
778 ath5k_hw_release_tx_queue(ah, sc->bhalq);
779err_desc:
780 ath5k_desc_free(sc, pdev);
781err:
782 return ret;
783}
784
785static void
786ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
787{
788 struct ath5k_softc *sc = hw->priv;
789
790 /*
791 * NB: the order of these is important:
792 * o call the 802.11 layer before detaching ath5k_hw to
793 * insure callbacks into the driver to delete global
794 * key cache entries can be handled
795 * o reclaim the tx queue data structures after calling
796 * the 802.11 layer as we'll get called back to reclaim
797 * node state and potentially want to use them
798 * o to cleanup the tx queues the hal is called, so detach
799 * it last
800 * XXX: ??? detach ath5k_hw ???
801 * Other than that, it's straightforward...
802 */
803 ieee80211_unregister_hw(hw);
804 ath5k_desc_free(sc, pdev);
805 ath5k_txq_release(sc);
806 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
807
808 /*
809 * NB: can't reclaim these until after ieee80211_ifdetach
810 * returns because we'll get called back to reclaim node
811 * state and potentially want to use them.
812 */
813}
814
815
816
817
818/********************\
819* Channel/mode setup *
820\********************/
821
822/*
823 * Convert IEEE channel number to MHz frequency.
824 */
825static inline short
826ath5k_ieee2mhz(short chan)
827{
828 if (chan <= 14 || chan >= 27)
829 return ieee80211chan2mhz(chan);
830 else
831 return 2212 + chan * 20;
832}
833
834static unsigned int
835ath5k_copy_rates(struct ieee80211_rate *rates,
836 const struct ath5k_rate_table *rt,
837 unsigned int max)
838{
839 unsigned int i, count;
840
841 if (rt == NULL)
842 return 0;
843
844 for (i = 0, count = 0; i < rt->rate_count && max > 0; i++) {
d8ee398d
LR		 845 rates[count].bitrate = rt->rates[i].rate_kbps / 100;
846 rates[count].hw_value = rt->rates[i].rate_code;
847 rates[count].flags = rt->rates[i].modulation;
fa1c114f
JS		 848 count++;
849 max--;
850 }
851
852 return count;
853}
854
855static unsigned int
856ath5k_copy_channels(struct ath5k_hw *ah,
857 struct ieee80211_channel *channels,
858 unsigned int mode,
859 unsigned int max)
860{
d8ee398d 861 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 862
863 if (!test_bit(mode, ah->ah_modes))
864 return 0;
865
fa1c114f 866 switch (mode) {
d8ee398d
LR		 867 case AR5K_MODE_11A:
868 case AR5K_MODE_11A_TURBO:
fa1c114f 869 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 870 size = 220 ;
fa1c114f
JS		 871 chfreq = CHANNEL_5GHZ;
872 break;
d8ee398d
LR		 873 case AR5K_MODE_11B:
874 case AR5K_MODE_11G:
875 case AR5K_MODE_11G_TURBO:
876 size = 26;
fa1c114f
JS		 877 chfreq = CHANNEL_2GHZ;
878 break;
879 default:
880 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
881 return 0;
882 }
883
884 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 885 ch = i + 1 ;
886 freq = ath5k_ieee2mhz(ch);
fa1c114f 887
d8ee398d
LR		 888 /* Check if channel is supported by the chipset */
889 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 890 continue;
891
d8ee398d
LR		 892 /* Write channel info and increment counter */
893 channels[count].center_freq = freq;
894
895 if((mode == AR5K_MODE_11A) ||
896 (mode == AR5K_MODE_11G)){
897 channels[count].hw_value = chfreq|CHANNEL_OFDM;
898 } else if((mode == AR5K_MODE_11A_TURBO) ||
899 (mode == AR5K_MODE_11G_TURBO)){
900 channels[count].hw_value = chfreq|CHANNEL_OFDM|CHANNEL_TURBO;
901 }if(mode == AR5K_MODE_11B) {
902 channels[count].hw_value = CHANNEL_B;
903 }
fa1c114f 904
fa1c114f
JS		 905 count++;
906 max--;
907 }
908
909 return count;
910}
911
d8ee398d
LR		 912static int
913ath5k_getchannels(struct ieee80211_hw *hw)
fa1c114f
JS		 914{
915 struct ath5k_softc *sc = hw->priv;
d8ee398d
LR		 916 struct ath5k_hw *ah = sc->ah;
917 struct ieee80211_supported_band *sbands = sc->sbands;
918 const struct ath5k_rate_table *hw_rates;
919 unsigned int max_r, max_c, count_r, count_c;
920 int mode2g = AR5K_MODE_11G;
fa1c114f 921
d8ee398d 922 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
fa1c114f 923
d8ee398d
LR		 924 max_r = ARRAY_SIZE(sc->rates);
925 max_c = ARRAY_SIZE(sc->channels);
926 count_r = count_c = 0;
927
928 /* 2GHz band */
929 if(!test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)){
930 mode2g = AR5K_MODE_11B;
931 if(!test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)){
932 mode2g = -1;
fa1c114f 933 }
fa1c114f 934 }
fa1c114f 935
d8ee398d
LR		 936 if(mode2g > 0){
937 struct ieee80211_supported_band *sband = &sbands[IEEE80211_BAND_2GHZ];
fa1c114f 938
d8ee398d
LR		 939 sband->bitrates = sc->rates;
940 sband->channels = sc->channels;
fa1c114f 941
d8ee398d
LR		 942 sband->band = IEEE80211_BAND_2GHZ;
943 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
944 mode2g, max_c);
fa1c114f 945
d8ee398d
LR		 946 hw_rates = ath5k_hw_get_rate_table(ah, mode2g);
947 sband->n_bitrates = ath5k_copy_rates(sband->bitrates,
948 hw_rates,max_r);
fa1c114f 949
d8ee398d
LR		 950 count_c = sband->n_channels;
951 count_r = sband->n_bitrates;
fa1c114f 952
d8ee398d
LR		 953 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
954
955 max_r -= count_r;
956 max_c -= count_c;
fa1c114f 957
fa1c114f
JS		 958 }
959
d8ee398d 960 /* 5GHz band */
fa1c114f 961
d8ee398d
LR		 962 if(test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)){
963 struct ieee80211_supported_band *sband = &sbands[IEEE80211_BAND_5GHZ];
fa1c114f 964
d8ee398d
LR		 965 sband->bitrates = &sc->rates[count_r];
966 sband->channels = &sc->channels[count_c];
fa1c114f 967
d8ee398d
LR		 968 sband->band = IEEE80211_BAND_5GHZ;
969 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
970 AR5K_MODE_11A, max_c);
971
972 hw_rates = ath5k_hw_get_rate_table(ah, AR5K_MODE_11A);
973 sband->n_bitrates = ath5k_copy_rates(sband->bitrates,
974 hw_rates,max_r);
975
976 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
977 }
978
979/* FIXME: ath5k_debug_dump_modes(sc, modes); */
980
981 return 0;
fa1c114f
JS		 982}
983
984/*
985 * Set/change channels. If the channel is really being changed,
986 * it's done by reseting the chip. To accomplish this we must
987 * first cleanup any pending DMA, then restart stuff after a la
988 * ath5k_init.
989 */
990static int
991ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
992{
993 struct ath5k_hw *ah = sc->ah;
994 int ret;
995
d8ee398d
LR		 996 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
997 sc->curchan->center_freq, chan->center_freq);
998
999 if (chan->center_freq != sc->curchan->center_freq ||
1000 chan->hw_value != sc->curchan->hw_value) {
1001
1002 sc->curchan = chan;
1003 sc->curband = &sc->sbands[chan->band];
fa1c114f 1004
fa1c114f
JS		 1005 /*
1006 * To switch channels clear any pending DMA operations;
1007 * wait long enough for the RX fifo to drain, reset the
1008 * hardware at the new frequency, and then re-enable
1009 * the relevant bits of the h/w.
1010 */
1011 ath5k_hw_set_intr(ah, 0); /* disable interrupts */
1012 ath5k_txq_cleanup(sc); /* clear pending tx frames */
1013 ath5k_rx_stop(sc); /* turn off frame recv */
d8ee398d 1014 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
fa1c114f 1015 if (ret) {
d8ee398d
LR		 1016 ATH5K_ERR(sc, "%s: unable to reset channel "
1017 "(%u Mhz)\n", __func__, chan->center_freq);
fa1c114f
JS		 1018 return ret;
1019 }
d8ee398d 1020
fa1c114f
JS		 1021 ath5k_hw_set_txpower_limit(sc->ah, 0);
1022
1023 /*
1024 * Re-enable rx framework.
1025 */
1026 ret = ath5k_rx_start(sc);
1027 if (ret) {
1028 ATH5K_ERR(sc, "%s: unable to restart recv logic\n",
1029 __func__);
1030 return ret;
1031 }
1032
1033 /*
1034 * Change channels and update the h/w rate map
1035 * if we're switching; e.g. 11a to 11b/g.
1036 *
1037 * XXX needed?
1038 */
1039/* ath5k_chan_change(sc, chan); */
1040
1041 ath5k_beacon_config(sc);
1042 /*
1043 * Re-enable interrupts.
1044 */
1045 ath5k_hw_set_intr(ah, sc->imask);
1046 }
1047
1048 return 0;
1049}
1050
d8ee398d
LR		 1051/*
1052 * TODO: CLEAN THIS !!!
1053 */
fa1c114f
JS		 1054static void
1055ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1056{
1057 if (unlikely(test_bit(ATH_STAT_LEDSOFT, sc->status))) {
1058 /* from Atheros NDIS driver, w/ permission */
1059 static const struct {
1060 u16 rate; /* tx/rx 802.11 rate */
1061 u16 timeOn; /* LED on time (ms) */
1062 u16 timeOff; /* LED off time (ms) */
1063 } blinkrates[] = {
1064 { 108, 40, 10 },
1065 { 96, 44, 11 },
1066 { 72, 50, 13 },
1067 { 48, 57, 14 },
1068 { 36, 67, 16 },
1069 { 24, 80, 20 },
1070 { 22, 100, 25 },
1071 { 18, 133, 34 },
1072 { 12, 160, 40 },
1073 { 10, 200, 50 },
1074 { 6, 240, 58 },
1075 { 4, 267, 66 },
1076 { 2, 400, 100 },
1077 { 0, 500, 130 }
1078 };
1079 const struct ath5k_rate_table *rt =
1080 ath5k_hw_get_rate_table(sc->ah, mode);
1081 unsigned int i, j;
1082
1083 BUG_ON(rt == NULL);
1084
1085 memset(sc->hwmap, 0, sizeof(sc->hwmap));
1086 for (i = 0; i < 32; i++) {
1087 u8 ix = rt->rate_code_to_index[i];
1088 if (ix == 0xff) {
1089 sc->hwmap[i].ledon = msecs_to_jiffies(500);
1090 sc->hwmap[i].ledoff = msecs_to_jiffies(130);
1091 continue;
1092 }
1093 sc->hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
fa1c114f
JS		 1094 /* receive frames include FCS */
1095 sc->hwmap[i].rxflags = sc->hwmap[i].txflags |
1096 IEEE80211_RADIOTAP_F_FCS;
1097 /* setup blink rate table to avoid per-packet lookup */
1098 for (j = 0; j < ARRAY_SIZE(blinkrates) - 1; j++)
1099 if (blinkrates[j].rate == /* XXX why 7f? */
1100 (rt->rates[ix].dot11_rate&0x7f))
1101 break;
1102
1103 sc->hwmap[i].ledon = msecs_to_jiffies(blinkrates[j].
1104 timeOn);
1105 sc->hwmap[i].ledoff = msecs_to_jiffies(blinkrates[j].
1106 timeOff);
1107 }
1108 }
1109
1110 sc->curmode = mode;
d8ee398d
LR		 1111
1112 if(mode == AR5K_MODE_11A){
1113 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1114 } else {
1115 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1116 }
fa1c114f
JS		 1117}
1118
1119static void
1120ath5k_mode_setup(struct ath5k_softc *sc)
1121{
1122 struct ath5k_hw *ah = sc->ah;
1123 u32 rfilt;
1124
1125 /* configure rx filter */
1126 rfilt = sc->filter_flags;
1127 ath5k_hw_set_rx_filter(ah, rfilt);
1128
1129 if (ath5k_hw_hasbssidmask(ah))
1130 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1131
1132 /* configure operational mode */
1133 ath5k_hw_set_opmode(ah);
1134
1135 ath5k_hw_set_mcast_filter(ah, 0, 0);
1136 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1137}
1138
d8ee398d
LR		 1139/*
1140 * Match the hw provided rate index (through descriptors)
1141 * to an index for sc->curband->bitrates, so it can be used
1142 * by the stack.
1143 *
1144 * This one is a little bit tricky but i think i'm right
1145 * about this...
1146 *
1147 * We have 4 rate tables in the following order:
1148 * XR (4 rates)
1149 * 802.11a (8 rates)
1150 * 802.11b (4 rates)
1151 * 802.11g (12 rates)
1152 * that make the hw rate table.
1153 *
1154 * Lets take a 5211 for example that supports a and b modes only.
1155 * First comes the 802.11a table and then 802.11b (total 12 rates).
1156 * When hw returns eg. 11 it points to the last 802.11b rate (11Mbit),
1157 * if it returns 2 it points to the second 802.11a rate etc.
1158 *
1159 * Same goes for 5212 who has xr/a/b/g support (total 28 rates).
1160 * First comes the XR table, then 802.11a, 802.11b and 802.11g.
1161 * When hw returns eg. 27 it points to the last 802.11g rate (54Mbits) etc
1162 */
1163static void
1164ath5k_set_total_hw_rates(struct ath5k_softc *sc){
1165
1166 struct ath5k_hw *ah = sc->ah;
1167
1168 if(test_bit(AR5K_MODE_11A, ah->ah_modes))
1169 sc->a_rates = 8;
1170
1171 if(test_bit(AR5K_MODE_11B, ah->ah_modes))
1172 sc->b_rates = 4;
1173
1174 if(test_bit(AR5K_MODE_11G, ah->ah_modes))
1175 sc->g_rates = 12;
1176
1177 /* XXX: Need to see what what happens when
1178 xr disable bits in eeprom are set */
1179 if(ah->ah_version >= AR5K_AR5212)
1180 sc->xr_rates = 4;
1181
1182}
1183
1184static inline int
1185ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix){
1186
1187 int mac80211_rix;
1188
1189 if(sc->curband->band == IEEE80211_BAND_2GHZ){
1190 /* We setup a g ratetable for both b/g modes */
1191 mac80211_rix = hw_rix - sc->b_rates - sc->a_rates - sc->xr_rates;
1192 } else {
1193 mac80211_rix = hw_rix - sc->xr_rates;
1194 }
1195
1196 /* Something went wrong, fallback to basic rate for this band */
1197 if((mac80211_rix >= sc->curband->n_bitrates) ||
1198 (mac80211_rix <= 0 )){
1199 mac80211_rix = 1;
1200 }
1201
1202 return mac80211_rix;
1203}
1204
fa1c114f
JS		 1205
1206
1207
1208/***************\
1209* Buffers setup *
1210\***************/
1211
1212static int
1213ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1214{
1215 struct ath5k_hw *ah = sc->ah;
1216 struct sk_buff *skb = bf->skb;
1217 struct ath5k_desc *ds;
1218
1219 if (likely(skb == NULL)) {
1220 unsigned int off;
1221
1222 /*
1223 * Allocate buffer with headroom_needed space for the
1224 * fake physical layer header at the start.
1225 */
1226 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1227 if (unlikely(skb == NULL)) {
1228 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1229 sc->rxbufsize + sc->cachelsz - 1);
1230 return -ENOMEM;
1231 }
1232 /*
1233 * Cache-line-align. This is important (for the
1234 * 5210 at least) as not doing so causes bogus data
1235 * in rx'd frames.
1236 */
1237 off = ((unsigned long)skb->data) % sc->cachelsz;
1238 if (off != 0)
1239 skb_reserve(skb, sc->cachelsz - off);
1240
1241 bf->skb = skb;
1242 bf->skbaddr = pci_map_single(sc->pdev,
1243 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1244 if (unlikely(pci_dma_mapping_error(bf->skbaddr))) {
1245 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1246 dev_kfree_skb(skb);
1247 bf->skb = NULL;
1248 return -ENOMEM;
1249 }
1250 }
1251
1252 /*
1253 * Setup descriptors. For receive we always terminate
1254 * the descriptor list with a self-linked entry so we'll
1255 * not get overrun under high load (as can happen with a
1256 * 5212 when ANI processing enables PHY error frames).
1257 *
1258 * To insure the last descriptor is self-linked we create
1259 * each descriptor as self-linked and add it to the end. As
1260 * each additional descriptor is added the previous self-linked
1261 * entry is ``fixed'' naturally. This should be safe even
1262 * if DMA is happening. When processing RX interrupts we
1263 * never remove/process the last, self-linked, entry on the
1264 * descriptor list. This insures the hardware always has
1265 * someplace to write a new frame.
1266 */
1267 ds = bf->desc;
1268 ds->ds_link = bf->daddr; /* link to self */
1269 ds->ds_data = bf->skbaddr;
1270 ath5k_hw_setup_rx_desc(ah, ds,
1271 skb_tailroom(skb), /* buffer size */
1272 0);
1273
1274 if (sc->rxlink != NULL)
1275 *sc->rxlink = bf->daddr;
1276 sc->rxlink = &ds->ds_link;
1277 return 0;
1278}
1279
1280static int
1281ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1282 struct ieee80211_tx_control *ctl)
1283{
1284 struct ath5k_hw *ah = sc->ah;
1285 struct ath5k_txq *txq = sc->txq;
1286 struct ath5k_desc *ds = bf->desc;
1287 struct sk_buff *skb = bf->skb;
1288 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1289 int ret;
1290
1291 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1292 bf->ctl = *ctl;
1293 /* XXX endianness */
1294 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1295 PCI_DMA_TODEVICE);
1296
1297 if (ctl->flags & IEEE80211_TXCTL_NO_ACK)
1298 flags |= AR5K_TXDESC_NOACK;
1299
281c56dd 1300 pktlen = skb->len;
fa1c114f
JS		 1301
1302 if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT)) {
1303 keyidx = ctl->key_idx;
1304 pktlen += ctl->icv_len;
1305 }
1306
1307 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1308 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
d8ee398d 1309 (sc->power_level * 2), ctl->tx_rate->hw_value, ctl->retry_limit, keyidx, 0, flags, 0, 0);
fa1c114f
JS		 1310 if (ret)
1311 goto err_unmap;
1312
1313 ds->ds_link = 0;
1314 ds->ds_data = bf->skbaddr;
1315
1316 spin_lock_bh(&txq->lock);
1317 list_add_tail(&bf->list, &txq->q);
1318 sc->tx_stats.data[txq->qnum].len++;
1319 if (txq->link == NULL) /* is this first packet? */
1320 ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr);
1321 else /* no, so only link it */
1322 *txq->link = bf->daddr;
1323
1324 txq->link = &ds->ds_link;
1325 ath5k_hw_tx_start(ah, txq->qnum);
1326 spin_unlock_bh(&txq->lock);
1327
1328 return 0;
1329err_unmap:
1330 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1331 return ret;
1332}
1333
1334/*******************\
1335* Descriptors setup *
1336\*******************/
1337
1338static int
1339ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1340{
1341 struct ath5k_desc *ds;
1342 struct ath5k_buf *bf;
1343 dma_addr_t da;
1344 unsigned int i;
1345 int ret;
1346
1347 /* allocate descriptors */
1348 sc->desc_len = sizeof(struct ath5k_desc) *
1349 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1350 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1351 if (sc->desc == NULL) {
1352 ATH5K_ERR(sc, "can't allocate descriptors\n");
1353 ret = -ENOMEM;
1354 goto err;
1355 }
1356 ds = sc->desc;
1357 da = sc->desc_daddr;
1358 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1359 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1360
1361 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1362 sizeof(struct ath5k_buf), GFP_KERNEL);
1363 if (bf == NULL) {
1364 ATH5K_ERR(sc, "can't allocate bufptr\n");
1365 ret = -ENOMEM;
1366 goto err_free;
1367 }
1368 sc->bufptr = bf;
1369
1370 INIT_LIST_HEAD(&sc->rxbuf);
1371 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1372 bf->desc = ds;
1373 bf->daddr = da;
1374 list_add_tail(&bf->list, &sc->rxbuf);
1375 }
1376
1377 INIT_LIST_HEAD(&sc->txbuf);
1378 sc->txbuf_len = ATH_TXBUF;
1379 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1380 da += sizeof(*ds)) {
1381 bf->desc = ds;
1382 bf->daddr = da;
1383 list_add_tail(&bf->list, &sc->txbuf);
1384 }
1385
1386 /* beacon buffer */
1387 bf->desc = ds;
1388 bf->daddr = da;
1389 sc->bbuf = bf;
1390
1391 return 0;
1392err_free:
1393 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1394err:
1395 sc->desc = NULL;
1396 return ret;
1397}
1398
1399static void
1400ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1401{
1402 struct ath5k_buf *bf;
1403
1404 ath5k_txbuf_free(sc, sc->bbuf);
1405 list_for_each_entry(bf, &sc->txbuf, list)
1406 ath5k_txbuf_free(sc, bf);
1407 list_for_each_entry(bf, &sc->rxbuf, list)
1408 ath5k_txbuf_free(sc, bf);
1409
1410 /* Free memory associated with all descriptors */
1411 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1412
1413 kfree(sc->bufptr);
1414 sc->bufptr = NULL;
1415}
1416
1417
1418
1419
1420
1421/**************\
1422* Queues setup *
1423\**************/
1424
1425static struct ath5k_txq *
1426ath5k_txq_setup(struct ath5k_softc *sc,
1427 int qtype, int subtype)
1428{
1429 struct ath5k_hw *ah = sc->ah;
1430 struct ath5k_txq *txq;
1431 struct ath5k_txq_info qi = {
1432 .tqi_subtype = subtype,
1433 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1434 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1435 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1436 };
1437 int qnum;
1438
1439 /*
1440 * Enable interrupts only for EOL and DESC conditions.
1441 * We mark tx descriptors to receive a DESC interrupt
1442 * when a tx queue gets deep; otherwise waiting for the
1443 * EOL to reap descriptors. Note that this is done to
1444 * reduce interrupt load and this only defers reaping
1445 * descriptors, never transmitting frames. Aside from
1446 * reducing interrupts this also permits more concurrency.
1447 * The only potential downside is if the tx queue backs
1448 * up in which case the top half of the kernel may backup
1449 * due to a lack of tx descriptors.
1450 */
1451 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1452 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1453 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1454 if (qnum < 0) {
1455 /*
1456 * NB: don't print a message, this happens
1457 * normally on parts with too few tx queues
1458 */
1459 return ERR_PTR(qnum);
1460 }
1461 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1462 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1463 qnum, ARRAY_SIZE(sc->txqs));
1464 ath5k_hw_release_tx_queue(ah, qnum);
1465 return ERR_PTR(-EINVAL);
1466 }
1467 txq = &sc->txqs[qnum];
1468 if (!txq->setup) {
1469 txq->qnum = qnum;
1470 txq->link = NULL;
1471 INIT_LIST_HEAD(&txq->q);
1472 spin_lock_init(&txq->lock);
1473 txq->setup = true;
1474 }
1475 return &sc->txqs[qnum];
1476}
1477
1478static int
1479ath5k_beaconq_setup(struct ath5k_hw *ah)
1480{
1481 struct ath5k_txq_info qi = {
1482 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1483 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1484 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1485 /* NB: for dynamic turbo, don't enable any other interrupts */
1486 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1487 };
1488
1489 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1490}
1491
1492static int
1493ath5k_beaconq_config(struct ath5k_softc *sc)
1494{
1495 struct ath5k_hw *ah = sc->ah;
1496 struct ath5k_txq_info qi;
1497 int ret;
1498
1499 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1500 if (ret)
1501 return ret;
6d91e1d8 1502 if (sc->opmode == IEEE80211_IF_TYPE_AP) {
fa1c114f
JS		 1503 /*
1504 * Always burst out beacon and CAB traffic
1505 * (aifs = cwmin = cwmax = 0)
1506 */
1507 qi.tqi_aifs = 0;
1508 qi.tqi_cw_min = 0;
1509 qi.tqi_cw_max = 0;
6d91e1d8
BR		 1510 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
1511 /*
1512 * Adhoc mode; backoff between 0 and (2 * cw_min).
1513 */
1514 qi.tqi_aifs = 0;
1515 qi.tqi_cw_min = 0;
1516 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1517 }
1518
6d91e1d8
BR		 1519 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1520 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1521 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1522
fa1c114f
JS		 1523 ret = ath5k_hw_setup_tx_queueprops(ah, sc->bhalq, &qi);
1524 if (ret) {
1525 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1526 "hardware queue!\n", __func__);
1527 return ret;
1528 }
1529
1530 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1531}
1532
1533static void
1534ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1535{
1536 struct ath5k_buf *bf, *bf0;
1537
1538 /*
1539 * NB: this assumes output has been stopped and
1540 * we do not need to block ath5k_tx_tasklet
1541 */
1542 spin_lock_bh(&txq->lock);
1543 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1544 ath5k_debug_printtxbuf(sc, bf, !sc->ah->ah_proc_tx_desc(sc->ah,
1545 bf->desc));
1546
1547 ath5k_txbuf_free(sc, bf);
1548
1549 spin_lock_bh(&sc->txbuflock);
1550 sc->tx_stats.data[txq->qnum].len--;
1551 list_move_tail(&bf->list, &sc->txbuf);
1552 sc->txbuf_len++;
1553 spin_unlock_bh(&sc->txbuflock);
1554 }
1555 txq->link = NULL;
1556 spin_unlock_bh(&txq->lock);
1557}
1558
1559/*
1560 * Drain the transmit queues and reclaim resources.
1561 */
1562static void
1563ath5k_txq_cleanup(struct ath5k_softc *sc)
1564{
1565 struct ath5k_hw *ah = sc->ah;
1566 unsigned int i;
1567
1568 /* XXX return value */
1569 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1570 /* don't touch the hardware if marked invalid */
1571 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1572 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1573 ath5k_hw_get_tx_buf(ah, sc->bhalq));
1574 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1575 if (sc->txqs[i].setup) {
1576 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1577 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1578 "link %p\n",
1579 sc->txqs[i].qnum,
1580 ath5k_hw_get_tx_buf(ah,
1581 sc->txqs[i].qnum),
1582 sc->txqs[i].link);
1583 }
1584 }
1585 ieee80211_start_queues(sc->hw); /* XXX move to callers */
1586
1587 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1588 if (sc->txqs[i].setup)
1589 ath5k_txq_drainq(sc, &sc->txqs[i]);
1590}
1591
1592static void
1593ath5k_txq_release(struct ath5k_softc *sc)
1594{
1595 struct ath5k_txq *txq = sc->txqs;
1596 unsigned int i;
1597
1598 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1599 if (txq->setup) {
1600 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1601 txq->setup = false;
1602 }
1603}
1604
1605
1606
1607
1608/*************\
1609* RX Handling *
1610\*************/
1611
1612/*
1613 * Enable the receive h/w following a reset.
1614 */
1615static int
1616ath5k_rx_start(struct ath5k_softc *sc)
1617{
1618 struct ath5k_hw *ah = sc->ah;
1619 struct ath5k_buf *bf;
1620 int ret;
1621
1622 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1623
1624 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1625 sc->cachelsz, sc->rxbufsize);
1626
1627 sc->rxlink = NULL;
1628
1629 spin_lock_bh(&sc->rxbuflock);
1630 list_for_each_entry(bf, &sc->rxbuf, list) {
1631 ret = ath5k_rxbuf_setup(sc, bf);
1632 if (ret != 0) {
1633 spin_unlock_bh(&sc->rxbuflock);
1634 goto err;
1635 }
1636 }
1637 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1638 spin_unlock_bh(&sc->rxbuflock);
1639
1640 ath5k_hw_put_rx_buf(ah, bf->daddr);
1641 ath5k_hw_start_rx(ah); /* enable recv descriptors */
1642 ath5k_mode_setup(sc); /* set filters, etc. */
1643 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1644
1645 return 0;
1646err:
1647 return ret;
1648}
1649
1650/*
1651 * Disable the receive h/w in preparation for a reset.
1652 */
1653static void
1654ath5k_rx_stop(struct ath5k_softc *sc)
1655{
1656 struct ath5k_hw *ah = sc->ah;
1657
1658 ath5k_hw_stop_pcu_recv(ah); /* disable PCU */
1659 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1660 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1661 mdelay(3); /* 3ms is long enough for 1 frame */
1662
1663 ath5k_debug_printrxbuffs(sc, ah);
1664
1665 sc->rxlink = NULL; /* just in case */
1666}
1667
1668static unsigned int
1669ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1670 struct sk_buff *skb)
1671{
1672 struct ieee80211_hdr *hdr = (void *)skb->data;
1673 unsigned int keyix, hlen = ieee80211_get_hdrlen_from_skb(skb);
1674
1675 if (!(ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) &&
1676 ds->ds_rxstat.rs_keyix != AR5K_RXKEYIX_INVALID)
1677 return RX_FLAG_DECRYPTED;
1678
1679 /* Apparently when a default key is used to decrypt the packet
1680 the hw does not set the index used to decrypt. In such cases
1681 get the index from the packet. */
1682 if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED) &&
1683 !(ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) &&
1684 skb->len >= hlen + 4) {
1685 keyix = skb->data[hlen + 3] >> 6;
1686
1687 if (test_bit(keyix, sc->keymap))
1688 return RX_FLAG_DECRYPTED;
1689 }
1690
1691 return 0;
1692}
1693
036cd1ec
BR		 1694
1695static void
1696ath5k_check_ibss_hw_merge(struct ath5k_softc *sc, struct sk_buff *skb)
1697{
1698 u32 hw_tu;
1699 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1700
1701 if ((mgmt->frame_control & IEEE80211_FCTL_FTYPE) ==
1702 IEEE80211_FTYPE_MGMT &&
1703 (mgmt->frame_control & IEEE80211_FCTL_STYPE) ==
1704 IEEE80211_STYPE_BEACON &&
1705 mgmt->u.beacon.capab_info & WLAN_CAPABILITY_IBSS &&
1706 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1707 /*
1708 * Received an IBSS beacon with the same BSSID. Hardware might
1709 * have updated the TSF, check if we need to update timers.
1710 */
1711 hw_tu = TSF_TO_TU(ath5k_hw_get_tsf64(sc->ah));
1712 if (hw_tu >= sc->nexttbtt) {
1713 ath5k_beacon_update_timers(sc,
1714 mgmt->u.beacon.timestamp);
1715 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1716 "detected HW merge from received beacon\n");
1717 }
1718 }
1719}
1720
1721
fa1c114f
JS		 1722static void
1723ath5k_tasklet_rx(unsigned long data)
1724{
1725 struct ieee80211_rx_status rxs = {};
1726 struct sk_buff *skb;
1727 struct ath5k_softc *sc = (void *)data;
1728 struct ath5k_buf *bf;
1729 struct ath5k_desc *ds;
1730 u16 len;
1731 u8 stat;
1732 int ret;
1733 int hdrlen;
1734 int pad;
1735
1736 spin_lock(&sc->rxbuflock);
1737 do {
1738 if (unlikely(list_empty(&sc->rxbuf))) {
1739 ATH5K_WARN(sc, "empty rx buf pool\n");
1740 break;
1741 }
1742 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1743 BUG_ON(bf->skb == NULL);
1744 skb = bf->skb;
1745 ds = bf->desc;
1746
1747 /* TODO only one segment */
1748 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1749 sc->desc_len, PCI_DMA_FROMDEVICE);
1750
1751 if (unlikely(ds->ds_link == bf->daddr)) /* this is the end */
1752 break;
1753
1754 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds);
1755 if (unlikely(ret == -EINPROGRESS))
1756 break;
1757 else if (unlikely(ret)) {
1758 ATH5K_ERR(sc, "error in processing rx descriptor\n");
65872e6b 1759 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1760 return;
1761 }
1762
1763 if (unlikely(ds->ds_rxstat.rs_more)) {
1764 ATH5K_WARN(sc, "unsupported jumbo\n");
1765 goto next;
1766 }
1767
1768 stat = ds->ds_rxstat.rs_status;
1769 if (unlikely(stat)) {
1770 if (stat & AR5K_RXERR_PHY)
1771 goto next;
1772 if (stat & AR5K_RXERR_DECRYPT) {
1773 /*
1774 * Decrypt error. If the error occurred
1775 * because there was no hardware key, then
1776 * let the frame through so the upper layers
1777 * can process it. This is necessary for 5210
1778 * parts which have no way to setup a ``clear''
1779 * key cache entry.
1780 *
1781 * XXX do key cache faulting
1782 */
1783 if (ds->ds_rxstat.rs_keyix ==
1784 AR5K_RXKEYIX_INVALID &&
1785 !(stat & AR5K_RXERR_CRC))
1786 goto accept;
1787 }
1788 if (stat & AR5K_RXERR_MIC) {
1789 rxs.flag |= RX_FLAG_MMIC_ERROR;
1790 goto accept;
1791 }
1792
1793 /* let crypto-error packets fall through in MNTR */
1794 if ((stat & ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1795 sc->opmode != IEEE80211_IF_TYPE_MNTR)
1796 goto next;
1797 }
1798accept:
1799 len = ds->ds_rxstat.rs_datalen;
1800 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, len,
1801 PCI_DMA_FROMDEVICE);
1802 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1803 PCI_DMA_FROMDEVICE);
1804 bf->skb = NULL;
1805
1806 skb_put(skb, len);
1807
1808 /*
1809 * the hardware adds a padding to 4 byte boundaries between
1810 * the header and the payload data if the header length is
1811 * not multiples of 4 - remove it
1812 */
1813 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1814 if (hdrlen & 3) {
1815 pad = hdrlen % 4;
1816 memmove(skb->data + pad, skb->data, hdrlen);
1817 skb_pull(skb, pad);
1818 }
1819
c0e1899b
BR		 1820 /*
1821 * always extend the mac timestamp, since this information is
1822 * also needed for proper IBSS merging.
1823 *
1824 * XXX: it might be too late to do it here, since rs_tstamp is
1825 * 15bit only. that means TSF extension has to be done within
1826 * 32768usec (about 32ms). it might be necessary to move this to
1827 * the interrupt handler, like it is done in madwifi.
1828 */
1829 rxs.mactime = ath5k_extend_tsf(sc->ah, ds->ds_rxstat.rs_tstamp);
1830 rxs.flag |= RX_FLAG_TSFT;
1831
d8ee398d
LR		 1832 rxs.freq = sc->curchan->center_freq;
1833 rxs.band = sc->curband->band;
fa1c114f
JS		 1834
1835 /*
1836 * signal quality:
1837 * the names here are misleading and the usage of these
1838 * values by iwconfig makes it even worse
1839 */
1840 /* noise floor in dBm, from the last noise calibration */
1841 rxs.noise = sc->ah->ah_noise_floor;
1842 /* signal level in dBm */
1843 rxs.ssi = rxs.noise + ds->ds_rxstat.rs_rssi;
1844 /*
1845 * "signal" is actually displayed as Link Quality by iwconfig
1846 * we provide a percentage based on rssi (assuming max rssi 64)
1847 */
1848 rxs.signal = ds->ds_rxstat.rs_rssi * 100 / 64;
1849
1850 rxs.antenna = ds->ds_rxstat.rs_antenna;
d8ee398d 1851 rxs.rate_idx = ath5k_hw_to_driver_rix(sc,ds->ds_rxstat.rs_rate);
fa1c114f
JS		 1852 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb);
1853
1854 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1855
036cd1ec
BR		 1856 /* check beacons in IBSS mode */
1857 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
1858 ath5k_check_ibss_hw_merge(sc, skb);
1859
fa1c114f
JS		 1860 __ieee80211_rx(sc->hw, skb, &rxs);
1861 sc->led_rxrate = ds->ds_rxstat.rs_rate;
1862 ath5k_led_event(sc, ATH_LED_RX);
1863next:
1864 list_move_tail(&bf->list, &sc->rxbuf);
1865 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1866 spin_unlock(&sc->rxbuflock);
1867}
1868
1869
1870
1871
1872/*************\
1873* TX Handling *
1874\*************/
1875
1876static void
1877ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1878{
1879 struct ieee80211_tx_status txs = {};
1880 struct ath5k_buf *bf, *bf0;
1881 struct ath5k_desc *ds;
1882 struct sk_buff *skb;
1883 int ret;
1884
1885 spin_lock(&txq->lock);
1886 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1887 ds = bf->desc;
1888
1889 /* TODO only one segment */
1890 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1891 sc->desc_len, PCI_DMA_FROMDEVICE);
1892 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds);
1893 if (unlikely(ret == -EINPROGRESS))
1894 break;
1895 else if (unlikely(ret)) {
1896 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1897 ret, txq->qnum);
1898 break;
1899 }
1900
1901 skb = bf->skb;
1902 bf->skb = NULL;
1903 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1904 PCI_DMA_TODEVICE);
1905
1906 txs.control = bf->ctl;
1907 txs.retry_count = ds->ds_txstat.ts_shortretry +
1908 ds->ds_txstat.ts_longretry / 6;
1909 if (unlikely(ds->ds_txstat.ts_status)) {
1910 sc->ll_stats.dot11ACKFailureCount++;
1911 if (ds->ds_txstat.ts_status & AR5K_TXERR_XRETRY)
1912 txs.excessive_retries = 1;
1913 else if (ds->ds_txstat.ts_status & AR5K_TXERR_FILT)
1914 txs.flags |= IEEE80211_TX_STATUS_TX_FILTERED;
1915 } else {
1916 txs.flags |= IEEE80211_TX_STATUS_ACK;
1917 txs.ack_signal = ds->ds_txstat.ts_rssi;
1918 }
1919
1920 ieee80211_tx_status(sc->hw, skb, &txs);
1921 sc->tx_stats.data[txq->qnum].count++;
1922
1923 spin_lock(&sc->txbuflock);
1924 sc->tx_stats.data[txq->qnum].len--;
1925 list_move_tail(&bf->list, &sc->txbuf);
1926 sc->txbuf_len++;
1927 spin_unlock(&sc->txbuflock);
1928 }
1929 if (likely(list_empty(&txq->q)))
1930 txq->link = NULL;
1931 spin_unlock(&txq->lock);
1932 if (sc->txbuf_len > ATH_TXBUF / 5)
1933 ieee80211_wake_queues(sc->hw);
1934}
1935
1936static void
1937ath5k_tasklet_tx(unsigned long data)
1938{
1939 struct ath5k_softc *sc = (void *)data;
1940
1941 ath5k_tx_processq(sc, sc->txq);
1942
1943 ath5k_led_event(sc, ATH_LED_TX);
1944}
1945
1946
1947
1948
1949/*****************\
1950* Beacon handling *
1951\*****************/
1952
1953/*
1954 * Setup the beacon frame for transmit.
1955 */
1956static int
1957ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1958 struct ieee80211_tx_control *ctl)
1959{
1960 struct sk_buff *skb = bf->skb;
1961 struct ath5k_hw *ah = sc->ah;
1962 struct ath5k_desc *ds;
1963 int ret, antenna = 0;
1964 u32 flags;
1965
1966 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1967 PCI_DMA_TODEVICE);
1968 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1969 "skbaddr %llx\n", skb, skb->data, skb->len,
1970 (unsigned long long)bf->skbaddr);
1971 if (pci_dma_mapping_error(bf->skbaddr)) {
1972 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1973 return -EIO;
1974 }
1975
1976 ds = bf->desc;
1977
1978 flags = AR5K_TXDESC_NOACK;
1979 if (sc->opmode == IEEE80211_IF_TYPE_IBSS && ath5k_hw_hasveol(ah)) {
1980 ds->ds_link = bf->daddr; /* self-linked */
1981 flags |= AR5K_TXDESC_VEOL;
1982 /*
1983 * Let hardware handle antenna switching if txantenna is not set
1984 */
1985 } else {
1986 ds->ds_link = 0;
1987 /*
1988 * Switch antenna every 4 beacons if txantenna is not set
1989 * XXX assumes two antennas
1990 */
1991 if (antenna == 0)
1992 antenna = sc->bsent & 4 ? 2 : 1;
1993 }
1994
1995 ds->ds_data = bf->skbaddr;
281c56dd 1996 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
fa1c114f 1997 ieee80211_get_hdrlen_from_skb(skb),
d8ee398d 1998 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2), ctl->tx_rate->hw_value, 1,
fa1c114f
JS		 1999 AR5K_TXKEYIX_INVALID, antenna, flags, 0, 0);
2000 if (ret)
2001 goto err_unmap;
2002
2003 return 0;
2004err_unmap:
2005 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2006 return ret;
2007}
2008
2009/*
2010 * Transmit a beacon frame at SWBA. Dynamic updates to the
2011 * frame contents are done as needed and the slot time is
2012 * also adjusted based on current state.
2013 *
2014 * this is usually called from interrupt context (ath5k_intr())
2015 * but also from ath5k_beacon_config() in IBSS mode which in turn
2016 * can be called from a tasklet and user context
2017 */
2018static void
2019ath5k_beacon_send(struct ath5k_softc *sc)
2020{
2021 struct ath5k_buf *bf = sc->bbuf;
2022 struct ath5k_hw *ah = sc->ah;
2023
be9b7259 2024 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f
JS		 2025
2026 if (unlikely(bf->skb == NULL || sc->opmode == IEEE80211_IF_TYPE_STA ||
2027 sc->opmode == IEEE80211_IF_TYPE_MNTR)) {
2028 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2029 return;
2030 }
2031 /*
2032 * Check if the previous beacon has gone out. If
2033 * not don't don't try to post another, skip this
2034 * period and wait for the next. Missed beacons
2035 * indicate a problem and should not occur. If we
2036 * miss too many consecutive beacons reset the device.
2037 */
2038 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2039 sc->bmisscount++;
be9b7259 2040 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2041 "missed %u consecutive beacons\n", sc->bmisscount);
2042 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
be9b7259 2043 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2044 "stuck beacon time (%u missed)\n",
2045 sc->bmisscount);
2046 tasklet_schedule(&sc->restq);
2047 }
2048 return;
2049 }
2050 if (unlikely(sc->bmisscount != 0)) {
be9b7259 2051 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2052 "resume beacon xmit after %u misses\n",
2053 sc->bmisscount);
2054 sc->bmisscount = 0;
2055 }
2056
2057 /*
2058 * Stop any current dma and put the new frame on the queue.
2059 * This should never fail since we check above that no frames
2060 * are still pending on the queue.
2061 */
2062 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2063 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2064 /* NB: hw still stops DMA, so proceed */
2065 }
2066 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, bf->skb->len,
2067 PCI_DMA_TODEVICE);
2068
2069 ath5k_hw_put_tx_buf(ah, sc->bhalq, bf->daddr);
2070 ath5k_hw_tx_start(ah, sc->bhalq);
be9b7259 2071 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2072 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2073
2074 sc->bsent++;
2075}
2076
2077
9804b98d
BR		 2078/**
2079 * ath5k_beacon_update_timers - update beacon timers
2080 *
2081 * @sc: struct ath5k_softc pointer we are operating on
2082 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2083 * beacon timer update based on the current HW TSF.
2084 *
2085 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2086 * of a received beacon or the current local hardware TSF and write it to the
2087 * beacon timer registers.
2088 *
2089 * This is called in a variety of situations, e.g. when a beacon is received,
2090 * when a HW merge has been detected, but also when an new IBSS is created or
2091 * when we otherwise know we have to update the timers, but we keep it in this
2092 * function to have it all together in one place.
2093 */
fa1c114f 2094static void
9804b98d 2095ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2096{
2097 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2098 u32 nexttbtt, intval, hw_tu, bc_tu;
2099 u64 hw_tsf;
fa1c114f
JS		 2100
2101 intval = sc->bintval & AR5K_BEACON_PERIOD;
2102 if (WARN_ON(!intval))
2103 return;
2104
9804b98d
BR		 2105 /* beacon TSF converted to TU */
2106 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2107
9804b98d
BR		 2108 /* current TSF converted to TU */
2109 hw_tsf = ath5k_hw_get_tsf64(ah);
2110 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2111
9804b98d
BR		 2112#define FUDGE 3
2113 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2114 if (bc_tsf == -1) {
2115 /*
2116 * no beacons received, called internally.
2117 * just need to refresh timers based on HW TSF.
2118 */
2119 nexttbtt = roundup(hw_tu + FUDGE, intval);
2120 } else if (bc_tsf == 0) {
2121 /*
2122 * no beacon received, probably called by ath5k_reset_tsf().
2123 * reset TSF to start with 0.
2124 */
2125 nexttbtt = intval;
2126 intval |= AR5K_BEACON_RESET_TSF;
2127 } else if (bc_tsf > hw_tsf) {
2128 /*
2129 * beacon received, SW merge happend but HW TSF not yet updated.
2130 * not possible to reconfigure timers yet, but next time we
2131 * receive a beacon with the same BSSID, the hardware will
2132 * automatically update the TSF and then we need to reconfigure
2133 * the timers.
2134 */
2135 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2136 "need to wait for HW TSF sync\n");
2137 return;
2138 } else {
2139 /*
2140 * most important case for beacon synchronization between STA.
2141 *
2142 * beacon received and HW TSF has been already updated by HW.
2143 * update next TBTT based on the TSF of the beacon, but make
2144 * sure it is ahead of our local TSF timer.
2145 */
2146 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2147 }
2148#undef FUDGE
fa1c114f 2149
036cd1ec
BR		 2150 sc->nexttbtt = nexttbtt;
2151
fa1c114f 2152 intval |= AR5K_BEACON_ENA;
fa1c114f 2153 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2154
2155 /*
2156 * debugging output last in order to preserve the time critical aspect
2157 * of this function
2158 */
2159 if (bc_tsf == -1)
2160 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2161 "reconfigured timers based on HW TSF\n");
2162 else if (bc_tsf == 0)
2163 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2164 "reset HW TSF and timers\n");
2165 else
2166 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2167 "updated timers based on beacon TSF\n");
2168
2169 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2170 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2171 (unsigned long long) bc_tsf,
2172 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2173 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2174 intval & AR5K_BEACON_PERIOD,
2175 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2176 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2177}
2178
2179
036cd1ec
BR		 2180/**
2181 * ath5k_beacon_config - Configure the beacon queues and interrupts
2182 *
2183 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f
JS		 2184 *
2185 * When operating in station mode we want to receive a BMISS interrupt when we
2186 * stop seeing beacons from the AP we've associated with so we can look for
2187 * another AP to associate with.
2188 *
036cd1ec
BR		 2189 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2190 * interrupts to detect HW merges only.
2191 *
2192 * AP mode is missing.
fa1c114f
JS		 2193 */
2194static void
2195ath5k_beacon_config(struct ath5k_softc *sc)
2196{
2197 struct ath5k_hw *ah = sc->ah;
2198
2199 ath5k_hw_set_intr(ah, 0);
2200 sc->bmisscount = 0;
2201
2202 if (sc->opmode == IEEE80211_IF_TYPE_STA) {
2203 sc->imask |= AR5K_INT_BMISS;
2204 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2205 /*
036cd1ec
BR		 2206 * In IBSS mode we use a self-linked tx descriptor and let the
2207 * hardware send the beacons automatically. We have to load it
fa1c114f 2208 * only once here.
036cd1ec
BR		 2209 * We use the SWBA interrupt only to keep track of the beacon
2210 * timers in order to detect HW merges (automatic TSF updates).
fa1c114f
JS		 2211 */
2212 ath5k_beaconq_config(sc);
fa1c114f 2213
036cd1ec
BR		 2214 sc->imask |= AR5K_INT_SWBA;
2215
2216 if (ath5k_hw_hasveol(ah))
fa1c114f
JS		 2217 ath5k_beacon_send(sc);
2218 }
2219 /* TODO else AP */
2220
2221 ath5k_hw_set_intr(ah, sc->imask);
2222}
2223
2224
2225/********************\
2226* Interrupt handling *
2227\********************/
2228
2229static int
2230ath5k_init(struct ath5k_softc *sc)
2231{
2232 int ret;
2233
2234 mutex_lock(&sc->lock);
2235
2236 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2237
2238 /*
2239 * Stop anything previously setup. This is safe
2240 * no matter this is the first time through or not.
2241 */
2242 ath5k_stop_locked(sc);
2243
2244 /*
2245 * The basic interface to setting the hardware in a good
2246 * state is ``reset''. On return the hardware is known to
2247 * be powered up and with interrupts disabled. This must
2248 * be followed by initialization of the appropriate bits
2249 * and then setup of the interrupt mask.
2250 */
d8ee398d
LR		 2251 sc->curchan = sc->hw->conf.channel;
2252 sc->curband = &sc->sbands[sc->curchan->band];
fa1c114f
JS		 2253 ret = ath5k_hw_reset(sc->ah, sc->opmode, sc->curchan, false);
2254 if (ret) {
2255 ATH5K_ERR(sc, "unable to reset hardware: %d\n", ret);
2256 goto done;
2257 }
2258 /*
2259 * This is needed only to setup initial state
2260 * but it's best done after a reset.
2261 */
2262 ath5k_hw_set_txpower_limit(sc->ah, 0);
2263
2264 /*
2265 * Setup the hardware after reset: the key cache
2266 * is filled as needed and the receive engine is
2267 * set going. Frame transmit is handled entirely
2268 * in the frame output path; there's nothing to do
2269 * here except setup the interrupt mask.
2270 */
2271 ret = ath5k_rx_start(sc);
2272 if (ret)
2273 goto done;
2274
2275 /*
2276 * Enable interrupts.
2277 */
2278 sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
2279 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL;
2280
2281 ath5k_hw_set_intr(sc->ah, sc->imask);
2282 /* Set ack to be sent at low bit-rates */
2283 ath5k_hw_set_ack_bitrate_high(sc->ah, false);
2284
2285 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2286 msecs_to_jiffies(ath5k_calinterval * 1000)));
2287
2288 ret = 0;
2289done:
2290 mutex_unlock(&sc->lock);
2291 return ret;
2292}
2293
2294static int
2295ath5k_stop_locked(struct ath5k_softc *sc)
2296{
2297 struct ath5k_hw *ah = sc->ah;
2298
2299 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2300 test_bit(ATH_STAT_INVALID, sc->status));
2301
2302 /*
2303 * Shutdown the hardware and driver:
2304 * stop output from above
2305 * disable interrupts
2306 * turn off timers
2307 * turn off the radio
2308 * clear transmit machinery
2309 * clear receive machinery
2310 * drain and release tx queues
2311 * reclaim beacon resources
2312 * power down hardware
2313 *
2314 * Note that some of this work is not possible if the
2315 * hardware is gone (invalid).
2316 */
2317 ieee80211_stop_queues(sc->hw);
2318
2319 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2320 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2321 del_timer_sync(&sc->led_tim);
2322 ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on);
2323 __clear_bit(ATH_STAT_LEDBLINKING, sc->status);
2324 }
2325 ath5k_hw_set_intr(ah, 0);
2326 }
2327 ath5k_txq_cleanup(sc);
2328 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2329 ath5k_rx_stop(sc);
2330 ath5k_hw_phy_disable(ah);
2331 } else
2332 sc->rxlink = NULL;
2333
2334 return 0;
2335}
2336
2337/*
2338 * Stop the device, grabbing the top-level lock to protect
2339 * against concurrent entry through ath5k_init (which can happen
2340 * if another thread does a system call and the thread doing the
2341 * stop is preempted).
2342 */
2343static int
2344ath5k_stop_hw(struct ath5k_softc *sc)
2345{
2346 int ret;
2347
2348 mutex_lock(&sc->lock);
2349 ret = ath5k_stop_locked(sc);
2350 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2351 /*
2352 * Set the chip in full sleep mode. Note that we are
2353 * careful to do this only when bringing the interface
2354 * completely to a stop. When the chip is in this state
2355 * it must be carefully woken up or references to
2356 * registers in the PCI clock domain may freeze the bus
2357 * (and system). This varies by chip and is mostly an
2358 * issue with newer parts that go to sleep more quickly.
2359 */
2360 if (sc->ah->ah_mac_srev >= 0x78) {
2361 /*
2362 * XXX
2363 * don't put newer MAC revisions > 7.8 to sleep because
2364 * of the above mentioned problems
2365 */
2366 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2367 "not putting device to sleep\n");
2368 } else {
2369 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2370 "putting device to full sleep\n");
2371 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2372 }
2373 }
2374 ath5k_txbuf_free(sc, sc->bbuf);
2375 mutex_unlock(&sc->lock);
2376
2377 del_timer_sync(&sc->calib_tim);
2378
2379 return ret;
2380}
2381
2382static irqreturn_t
2383ath5k_intr(int irq, void *dev_id)
2384{
2385 struct ath5k_softc *sc = dev_id;
2386 struct ath5k_hw *ah = sc->ah;
2387 enum ath5k_int status;
2388 unsigned int counter = 1000;
2389
2390 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2391 !ath5k_hw_is_intr_pending(ah)))
2392 return IRQ_NONE;
2393
2394 do {
2395 /*
2396 * Figure out the reason(s) for the interrupt. Note
2397 * that get_isr returns a pseudo-ISR that may include
2398 * bits we haven't explicitly enabled so we mask the
2399 * value to insure we only process bits we requested.
2400 */
2401 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2402 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2403 status, sc->imask);
2404 status &= sc->imask; /* discard unasked for bits */
2405 if (unlikely(status & AR5K_INT_FATAL)) {
2406 /*
2407 * Fatal errors are unrecoverable.
2408 * Typically these are caused by DMA errors.
2409 */
2410 tasklet_schedule(&sc->restq);
2411 } else if (unlikely(status & AR5K_INT_RXORN)) {
2412 tasklet_schedule(&sc->restq);
2413 } else {
2414 if (status & AR5K_INT_SWBA) {
2415 /*
2416 * Software beacon alert--time to send a beacon.
2417 * Handle beacon transmission directly; deferring
2418 * this is too slow to meet timing constraints
2419 * under load.
036cd1ec
BR		 2420 *
2421 * In IBSS mode we use this interrupt just to
2422 * keep track of the next TBTT (target beacon
2423 * transmission time) in order to detect hardware
2424 * merges (TSF updates).
fa1c114f 2425 */
036cd1ec
BR		 2426 if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2427 /* XXX: only if VEOL suppported */
2428 u64 tsf = ath5k_hw_get_tsf64(ah);
2429 sc->nexttbtt += sc->bintval;
2430 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2431 "SWBA nexttbtt: %x hw_tu: %x "
2432 "TSF: %llx\n",
2433 sc->nexttbtt,
2434 TSF_TO_TU(tsf),
2435 (unsigned long long) tsf);
036cd1ec
BR		 2436 } else {
2437 ath5k_beacon_send(sc);
2438 }
fa1c114f
JS		 2439 }
2440 if (status & AR5K_INT_RXEOL) {
2441 /*
2442 * NB: the hardware should re-read the link when
2443 * RXE bit is written, but it doesn't work at
2444 * least on older hardware revs.
2445 */
2446 sc->rxlink = NULL;
2447 }
2448 if (status & AR5K_INT_TXURN) {
2449 /* bump tx trigger level */
2450 ath5k_hw_update_tx_triglevel(ah, true);
2451 }
2452 if (status & AR5K_INT_RX)
2453 tasklet_schedule(&sc->rxtq);
2454 if (status & AR5K_INT_TX)
2455 tasklet_schedule(&sc->txtq);
2456 if (status & AR5K_INT_BMISS) {
2457 }
2458 if (status & AR5K_INT_MIB) {
2459 /* TODO */
2460 }
2461 }
2462 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2463
2464 if (unlikely(!counter))
2465 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2466
2467 return IRQ_HANDLED;
2468}
2469
2470static void
2471ath5k_tasklet_reset(unsigned long data)
2472{
2473 struct ath5k_softc *sc = (void *)data;
2474
2475 ath5k_reset(sc->hw);
2476}
2477
2478/*
2479 * Periodically recalibrate the PHY to account
2480 * for temperature/environment changes.
2481 */
2482static void
2483ath5k_calibrate(unsigned long data)
2484{
2485 struct ath5k_softc *sc = (void *)data;
2486 struct ath5k_hw *ah = sc->ah;
2487
2488 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
d8ee398d 2489 ieee80211_frequency_to_channel(sc->curchan->center_freq), sc->curchan->hw_value);
fa1c114f
JS		 2490
2491 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2492 /*
2493 * Rfgain is out of bounds, reset the chip
2494 * to load new gain values.
2495 */
2496 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2497 ath5k_reset(sc->hw);
2498 }
2499 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2500 ATH5K_ERR(sc, "calibration of channel %u failed\n",
d8ee398d 2501 ieee80211_frequency_to_channel(sc->curchan->center_freq));
fa1c114f
JS		 2502
2503 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2504 msecs_to_jiffies(ath5k_calinterval * 1000)));
2505}
2506
2507
2508
2509/***************\
2510* LED functions *
2511\***************/
2512
2513static void
2514ath5k_led_off(unsigned long data)
2515{
2516 struct ath5k_softc *sc = (void *)data;
2517
2518 if (test_bit(ATH_STAT_LEDENDBLINK, sc->status))
2519 __clear_bit(ATH_STAT_LEDBLINKING, sc->status);
2520 else {
2521 __set_bit(ATH_STAT_LEDENDBLINK, sc->status);
2522 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2523 mod_timer(&sc->led_tim, jiffies + sc->led_off);
2524 }
2525}
2526
2527/*
2528 * Blink the LED according to the specified on/off times.
2529 */
2530static void
2531ath5k_led_blink(struct ath5k_softc *sc, unsigned int on,
2532 unsigned int off)
2533{
2534 ATH5K_DBG(sc, ATH5K_DEBUG_LED, "on %u off %u\n", on, off);
2535 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2536 __set_bit(ATH_STAT_LEDBLINKING, sc->status);
2537 __clear_bit(ATH_STAT_LEDENDBLINK, sc->status);
2538 sc->led_off = off;
2539 mod_timer(&sc->led_tim, jiffies + on);
2540}
2541
2542static void
2543ath5k_led_event(struct ath5k_softc *sc, int event)
2544{
2545 if (likely(!test_bit(ATH_STAT_LEDSOFT, sc->status)))
2546 return;
2547 if (unlikely(test_bit(ATH_STAT_LEDBLINKING, sc->status)))
2548 return; /* don't interrupt active blink */
2549 switch (event) {
2550 case ATH_LED_TX:
2551 ath5k_led_blink(sc, sc->hwmap[sc->led_txrate].ledon,
2552 sc->hwmap[sc->led_txrate].ledoff);
2553 break;
2554 case ATH_LED_RX:
2555 ath5k_led_blink(sc, sc->hwmap[sc->led_rxrate].ledon,
2556 sc->hwmap[sc->led_rxrate].ledoff);
2557 break;
2558 }
2559}
2560
2561
2562
2563
2564/********************\
2565* Mac80211 functions *
2566\********************/
2567
2568static int
2569ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2570 struct ieee80211_tx_control *ctl)
2571{
2572 struct ath5k_softc *sc = hw->priv;
2573 struct ath5k_buf *bf;
2574 unsigned long flags;
2575 int hdrlen;
2576 int pad;
2577
2578 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2579
2580 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2581 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2582
2583 /*
2584 * the hardware expects the header padded to 4 byte boundaries
2585 * if this is not the case we add the padding after the header
2586 */
2587 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2588 if (hdrlen & 3) {
2589 pad = hdrlen % 4;
2590 if (skb_headroom(skb) < pad) {
2591 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2592 " headroom to pad %d\n", hdrlen, pad);
2593 return -1;
2594 }
2595 skb_push(skb, pad);
2596 memmove(skb->data, skb->data+pad, hdrlen);
2597 }
2598
d8ee398d 2599 sc->led_txrate = ctl->tx_rate->hw_value;
fa1c114f
JS		 2600
2601 spin_lock_irqsave(&sc->txbuflock, flags);
2602 if (list_empty(&sc->txbuf)) {
2603 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2604 spin_unlock_irqrestore(&sc->txbuflock, flags);
2605 ieee80211_stop_queue(hw, ctl->queue);
2606 return -1;
2607 }
2608 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2609 list_del(&bf->list);
2610 sc->txbuf_len--;
2611 if (list_empty(&sc->txbuf))
2612 ieee80211_stop_queues(hw);
2613 spin_unlock_irqrestore(&sc->txbuflock, flags);
2614
2615 bf->skb = skb;
2616
2617 if (ath5k_txbuf_setup(sc, bf, ctl)) {
2618 bf->skb = NULL;
2619 spin_lock_irqsave(&sc->txbuflock, flags);
2620 list_add_tail(&bf->list, &sc->txbuf);
2621 sc->txbuf_len++;
2622 spin_unlock_irqrestore(&sc->txbuflock, flags);
2623 dev_kfree_skb_any(skb);
2624 return 0;
2625 }
2626
2627 return 0;
2628}
2629
2630static int
2631ath5k_reset(struct ieee80211_hw *hw)
2632{
2633 struct ath5k_softc *sc = hw->priv;
2634 struct ath5k_hw *ah = sc->ah;
2635 int ret;
2636
2637 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f
JS		 2638
2639 ath5k_hw_set_intr(ah, 0);
2640 ath5k_txq_cleanup(sc);
2641 ath5k_rx_stop(sc);
2642
2643 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2644 if (unlikely(ret)) {
2645 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2646 goto err;
2647 }
2648 ath5k_hw_set_txpower_limit(sc->ah, 0);
2649
2650 ret = ath5k_rx_start(sc);
2651 if (unlikely(ret)) {
2652 ATH5K_ERR(sc, "can't start recv logic\n");
2653 goto err;
2654 }
2655 /*
2656 * We may be doing a reset in response to an ioctl
2657 * that changes the channel so update any state that
2658 * might change as a result.
2659 *
2660 * XXX needed?
2661 */
2662/* ath5k_chan_change(sc, c); */
2663 ath5k_beacon_config(sc);
2664 /* intrs are started by ath5k_beacon_config */
2665
2666 ieee80211_wake_queues(hw);
2667
2668 return 0;
2669err:
2670 return ret;
2671}
2672
2673static int ath5k_start(struct ieee80211_hw *hw)
2674{
2675 return ath5k_init(hw->priv);
2676}
2677
2678static void ath5k_stop(struct ieee80211_hw *hw)
2679{
2680 ath5k_stop_hw(hw->priv);
2681}
2682
2683static int ath5k_add_interface(struct ieee80211_hw *hw,
2684 struct ieee80211_if_init_conf *conf)
2685{
2686 struct ath5k_softc *sc = hw->priv;
2687 int ret;
2688
2689 mutex_lock(&sc->lock);
32bfd35d 2690 if (sc->vif) {
fa1c114f
JS		 2691 ret = 0;
2692 goto end;
2693 }
2694
32bfd35d 2695 sc->vif = conf->vif;
fa1c114f
JS		 2696
2697 switch (conf->type) {
2698 case IEEE80211_IF_TYPE_STA:
2699 case IEEE80211_IF_TYPE_IBSS:
2700 case IEEE80211_IF_TYPE_MNTR:
2701 sc->opmode = conf->type;
2702 break;
2703 default:
2704 ret = -EOPNOTSUPP;
2705 goto end;
2706 }
2707 ret = 0;
2708end:
2709 mutex_unlock(&sc->lock);
2710 return ret;
2711}
2712
2713static void
2714ath5k_remove_interface(struct ieee80211_hw *hw,
2715 struct ieee80211_if_init_conf *conf)
2716{
2717 struct ath5k_softc *sc = hw->priv;
2718
2719 mutex_lock(&sc->lock);
32bfd35d 2720 if (sc->vif != conf->vif)
fa1c114f
JS		 2721 goto end;
2722
32bfd35d 2723 sc->vif = NULL;
fa1c114f
JS		 2724end:
2725 mutex_unlock(&sc->lock);
2726}
2727
d8ee398d
LR		 2728/*
2729 * TODO: Phy disable/diversity etc
2730 */
fa1c114f
JS		 2731static int
2732ath5k_config(struct ieee80211_hw *hw,
2733 struct ieee80211_conf *conf)
2734{
2735 struct ath5k_softc *sc = hw->priv;
2736
e535c1ac 2737 sc->bintval = conf->beacon_int;
d8ee398d 2738 sc->power_level = conf->power_level;
fa1c114f 2739
d8ee398d 2740 return ath5k_chan_set(sc, conf->channel);
fa1c114f
JS		 2741}
2742
2743static int
32bfd35d 2744ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
fa1c114f
JS		 2745 struct ieee80211_if_conf *conf)
2746{
2747 struct ath5k_softc *sc = hw->priv;
2748 struct ath5k_hw *ah = sc->ah;
2749 int ret;
2750
2751 /* Set to a reasonable value. Note that this will
2752 * be set to mac80211's value at ath5k_config(). */
e535c1ac 2753 sc->bintval = 1000;
fa1c114f 2754 mutex_lock(&sc->lock);
32bfd35d 2755 if (sc->vif != vif) {
fa1c114f
JS		 2756 ret = -EIO;
2757 goto unlock;
2758 }
2759 if (conf->bssid) {
2760 /* Cache for later use during resets */
2761 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2762 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2763 * a clean way of letting us retrieve this yet. */
2764 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2765 }
2766 mutex_unlock(&sc->lock);
2767
2768 return ath5k_reset(hw);
2769unlock:
2770 mutex_unlock(&sc->lock);
2771 return ret;
2772}
2773
2774#define SUPPORTED_FIF_FLAGS \
2775 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2776 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2777 FIF_BCN_PRBRESP_PROMISC
2778/*
2779 * o always accept unicast, broadcast, and multicast traffic
2780 * o multicast traffic for all BSSIDs will be enabled if mac80211
2781 * says it should be
2782 * o maintain current state of phy ofdm or phy cck error reception.
2783 * If the hardware detects any of these type of errors then
2784 * ath5k_hw_get_rx_filter() will pass to us the respective
2785 * hardware filters to be able to receive these type of frames.
2786 * o probe request frames are accepted only when operating in
2787 * hostap, adhoc, or monitor modes
2788 * o enable promiscuous mode according to the interface state
2789 * o accept beacons:
2790 * - when operating in adhoc mode so the 802.11 layer creates
2791 * node table entries for peers,
2792 * - when operating in station mode for collecting rssi data when
2793 * the station is otherwise quiet, or
2794 * - when scanning
2795 */
2796static void ath5k_configure_filter(struct ieee80211_hw *hw,
2797 unsigned int changed_flags,
2798 unsigned int *new_flags,
2799 int mc_count, struct dev_mc_list *mclist)
2800{
2801 struct ath5k_softc *sc = hw->priv;
2802 struct ath5k_hw *ah = sc->ah;
2803 u32 mfilt[2], val, rfilt;
2804 u8 pos;
2805 int i;
2806
2807 mfilt[0] = 0;
2808 mfilt[1] = 0;
2809
2810 /* Only deal with supported flags */
2811 changed_flags &= SUPPORTED_FIF_FLAGS;
2812 *new_flags &= SUPPORTED_FIF_FLAGS;
2813
2814 /* If HW detects any phy or radar errors, leave those filters on.
2815 * Also, always enable Unicast, Broadcasts and Multicast
2816 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2817 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2818 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2819 AR5K_RX_FILTER_MCAST);
2820
2821 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2822 if (*new_flags & FIF_PROMISC_IN_BSS) {
2823 rfilt |= AR5K_RX_FILTER_PROM;
2824 __set_bit(ATH_STAT_PROMISC, sc->status);
2825 }
2826 else
2827 __clear_bit(ATH_STAT_PROMISC, sc->status);
2828 }
2829
2830 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2831 if (*new_flags & FIF_ALLMULTI) {
2832 mfilt[0] = ~0;
2833 mfilt[1] = ~0;
2834 } else {
2835 for (i = 0; i < mc_count; i++) {
2836 if (!mclist)
2837 break;
2838 /* calculate XOR of eight 6-bit values */
2839 val = LE_READ_4(mclist->dmi_addr + 0);
2840 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2841 val = LE_READ_4(mclist->dmi_addr + 3);
2842 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2843 pos &= 0x3f;
2844 mfilt[pos / 32] |= (1 << (pos % 32));
2845 /* XXX: we might be able to just do this instead,
2846 * but not sure, needs testing, if we do use this we'd
2847 * neet to inform below to not reset the mcast */
2848 /* ath5k_hw_set_mcast_filterindex(ah,
2849 * mclist->dmi_addr[5]); */
2850 mclist = mclist->next;
2851 }
2852 }
2853
2854 /* This is the best we can do */
2855 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2856 rfilt |= AR5K_RX_FILTER_PHYERR;
2857
2858 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2859 * and probes for any BSSID, this needs testing */
2860 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2861 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2862
2863 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2864 * set we should only pass on control frames for this
2865 * station. This needs testing. I believe right now this
2866 * enables *all* control frames, which is OK.. but
2867 * but we should see if we can improve on granularity */
2868 if (*new_flags & FIF_CONTROL)
2869 rfilt |= AR5K_RX_FILTER_CONTROL;
2870
2871 /* Additional settings per mode -- this is per ath5k */
2872
2873 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2874
2875 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2876 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2877 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2878 if (sc->opmode != IEEE80211_IF_TYPE_STA)
2879 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2880 if (sc->opmode != IEEE80211_IF_TYPE_AP &&
2881 test_bit(ATH_STAT_PROMISC, sc->status))
2882 rfilt |= AR5K_RX_FILTER_PROM;
2883 if (sc->opmode == IEEE80211_IF_TYPE_STA ||
2884 sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2885 rfilt |= AR5K_RX_FILTER_BEACON;
2886 }
2887
2888 /* Set filters */
2889 ath5k_hw_set_rx_filter(ah,rfilt);
2890
2891 /* Set multicast bits */
2892 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2893 /* Set the cached hw filter flags, this will alter actually
2894 * be set in HW */
2895 sc->filter_flags = rfilt;
2896}
2897
2898static int
2899ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2900 const u8 *local_addr, const u8 *addr,
2901 struct ieee80211_key_conf *key)
2902{
2903 struct ath5k_softc *sc = hw->priv;
2904 int ret = 0;
2905
2906 switch(key->alg) {
2907 case ALG_WEP:
2908 break;
2909 case ALG_TKIP:
2910 case ALG_CCMP:
2911 return -EOPNOTSUPP;
2912 default:
2913 WARN_ON(1);
2914 return -EINVAL;
2915 }
2916
2917 mutex_lock(&sc->lock);
2918
2919 switch (cmd) {
2920 case SET_KEY:
2921 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2922 if (ret) {
2923 ATH5K_ERR(sc, "can't set the key\n");
2924 goto unlock;
2925 }
2926 __set_bit(key->keyidx, sc->keymap);
2927 key->hw_key_idx = key->keyidx;
2928 break;
2929 case DISABLE_KEY:
2930 ath5k_hw_reset_key(sc->ah, key->keyidx);
2931 __clear_bit(key->keyidx, sc->keymap);
2932 break;
2933 default:
2934 ret = -EINVAL;
2935 goto unlock;
2936 }
2937
2938unlock:
2939 mutex_unlock(&sc->lock);
2940 return ret;
2941}
2942
2943static int
2944ath5k_get_stats(struct ieee80211_hw *hw,
2945 struct ieee80211_low_level_stats *stats)
2946{
2947 struct ath5k_softc *sc = hw->priv;
2948
2949 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
2950
2951 return 0;
2952}
2953
2954static int
2955ath5k_get_tx_stats(struct ieee80211_hw *hw,
2956 struct ieee80211_tx_queue_stats *stats)
2957{
2958 struct ath5k_softc *sc = hw->priv;
2959
2960 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
2961
2962 return 0;
2963}
2964
2965static u64
2966ath5k_get_tsf(struct ieee80211_hw *hw)
2967{
2968 struct ath5k_softc *sc = hw->priv;
2969
2970 return ath5k_hw_get_tsf64(sc->ah);
2971}
2972
2973static void
2974ath5k_reset_tsf(struct ieee80211_hw *hw)
2975{
2976 struct ath5k_softc *sc = hw->priv;
2977
9804b98d
BR		 2978 /*
2979 * in IBSS mode we need to update the beacon timers too.
2980 * this will also reset the TSF if we call it with 0
2981 */
2982 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
2983 ath5k_beacon_update_timers(sc, 0);
2984 else
2985 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 2986}
2987
2988static int
2989ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
2990 struct ieee80211_tx_control *ctl)
2991{
2992 struct ath5k_softc *sc = hw->priv;
2993 int ret;
2994
2995 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
2996
2997 mutex_lock(&sc->lock);
2998
2999 if (sc->opmode != IEEE80211_IF_TYPE_IBSS) {
3000 ret = -EIO;
3001 goto end;
3002 }
3003
3004 ath5k_txbuf_free(sc, sc->bbuf);
3005 sc->bbuf->skb = skb;
3006 ret = ath5k_beacon_setup(sc, sc->bbuf, ctl);
3007 if (ret)
3008 sc->bbuf->skb = NULL;
3009 else
3010 ath5k_beacon_config(sc);
3011
3012end:
3013 mutex_unlock(&sc->lock);
3014 return ret;
3015}
3016
Linux kernel - Deliverables
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