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f078f209 LR |
1 | /* |
2 | * Copyright (c) 2008 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | /* Implementation of beacon processing. */ | |
18 | ||
19 | #include <asm/unaligned.h> | |
20 | #include "core.h" | |
21 | ||
22 | /* | |
23 | * Configure parameters for the beacon queue | |
24 | * | |
25 | * This function will modify certain transmit queue properties depending on | |
26 | * the operating mode of the station (AP or AdHoc). Parameters are AIFS | |
27 | * settings and channel width min/max | |
28 | */ | |
29 | ||
30 | static int ath_beaconq_config(struct ath_softc *sc) | |
31 | { | |
32 | struct ath_hal *ah = sc->sc_ah; | |
ea9880fb | 33 | struct ath9k_tx_queue_info qi; |
f078f209 | 34 | |
ea9880fb | 35 | ath9k_hw_get_txq_props(ah, sc->sc_bhalq, &qi); |
b4696c8b | 36 | if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP) { |
f078f209 LR |
37 | /* Always burst out beacon and CAB traffic. */ |
38 | qi.tqi_aifs = 1; | |
39 | qi.tqi_cwmin = 0; | |
40 | qi.tqi_cwmax = 0; | |
41 | } else { | |
42 | /* Adhoc mode; important thing is to use 2x cwmin. */ | |
43 | qi.tqi_aifs = sc->sc_beacon_qi.tqi_aifs; | |
44 | qi.tqi_cwmin = 2*sc->sc_beacon_qi.tqi_cwmin; | |
45 | qi.tqi_cwmax = sc->sc_beacon_qi.tqi_cwmax; | |
46 | } | |
47 | ||
ea9880fb | 48 | if (!ath9k_hw_set_txq_props(ah, sc->sc_bhalq, &qi)) { |
f078f209 LR |
49 | DPRINTF(sc, ATH_DBG_FATAL, |
50 | "%s: unable to update h/w beacon queue parameters\n", | |
51 | __func__); | |
52 | return 0; | |
53 | } else { | |
54 | ath9k_hw_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ | |
55 | return 1; | |
56 | } | |
57 | } | |
58 | ||
59 | /* | |
60 | * Setup the beacon frame for transmit. | |
61 | * | |
62 | * Associates the beacon frame buffer with a transmit descriptor. Will set | |
63 | * up all required antenna switch parameters, rate codes, and channel flags. | |
64 | * Beacons are always sent out at the lowest rate, and are not retried. | |
65 | */ | |
66 | ||
67 | static void ath_beacon_setup(struct ath_softc *sc, | |
68 | struct ath_vap *avp, struct ath_buf *bf) | |
69 | { | |
70 | struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu; | |
71 | struct ath_hal *ah = sc->sc_ah; | |
72 | struct ath_desc *ds; | |
73 | int flags, antenna; | |
74 | const struct ath9k_rate_table *rt; | |
75 | u8 rix, rate; | |
76 | int ctsrate = 0; | |
77 | int ctsduration = 0; | |
78 | struct ath9k_11n_rate_series series[4]; | |
79 | ||
80 | DPRINTF(sc, ATH_DBG_BEACON, "%s: m %p len %u\n", | |
81 | __func__, skb, skb->len); | |
82 | ||
83 | /* setup descriptors */ | |
84 | ds = bf->bf_desc; | |
85 | ||
86 | flags = ATH9K_TXDESC_NOACK; | |
87 | ||
b4696c8b | 88 | if (sc->sc_ah->ah_opmode == ATH9K_M_IBSS && |
60b67f51 | 89 | (ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) { |
f078f209 LR |
90 | ds->ds_link = bf->bf_daddr; /* self-linked */ |
91 | flags |= ATH9K_TXDESC_VEOL; | |
92 | /* Let hardware handle antenna switching. */ | |
93 | antenna = 0; | |
94 | } else { | |
95 | ds->ds_link = 0; | |
96 | /* | |
97 | * Switch antenna every beacon. | |
98 | * Should only switch every beacon period, not for every | |
99 | * SWBA's | |
100 | * XXX assumes two antenna | |
101 | */ | |
102 | antenna = ((sc->ast_be_xmit / sc->sc_nbcnvaps) & 1 ? 2 : 1); | |
103 | } | |
104 | ||
105 | ds->ds_data = bf->bf_buf_addr; | |
106 | ||
107 | /* | |
108 | * Calculate rate code. | |
109 | * XXX everything at min xmit rate | |
110 | */ | |
86b89eed | 111 | rix = 0; |
f078f209 LR |
112 | rt = sc->sc_currates; |
113 | rate = rt->info[rix].rateCode; | |
672840ac | 114 | if (sc->sc_flags & SC_OP_PREAMBLE_SHORT) |
f078f209 LR |
115 | rate |= rt->info[rix].shortPreamble; |
116 | ||
117 | ath9k_hw_set11n_txdesc(ah, ds | |
118 | , skb->len + FCS_LEN /* frame length */ | |
119 | , ATH9K_PKT_TYPE_BEACON /* Atheros packet type */ | |
120 | , avp->av_btxctl.txpower /* txpower XXX */ | |
121 | , ATH9K_TXKEYIX_INVALID /* no encryption */ | |
122 | , ATH9K_KEY_TYPE_CLEAR /* no encryption */ | |
123 | , flags /* no ack, veol for beacons */ | |
124 | ); | |
125 | ||
126 | /* NB: beacon's BufLen must be a multiple of 4 bytes */ | |
127 | ath9k_hw_filltxdesc(ah, ds | |
128 | , roundup(skb->len, 4) /* buffer length */ | |
129 | , true /* first segment */ | |
130 | , true /* last segment */ | |
131 | , ds /* first descriptor */ | |
132 | ); | |
133 | ||
134 | memzero(series, sizeof(struct ath9k_11n_rate_series) * 4); | |
135 | series[0].Tries = 1; | |
136 | series[0].Rate = rate; | |
137 | series[0].ChSel = sc->sc_tx_chainmask; | |
138 | series[0].RateFlags = (ctsrate) ? ATH9K_RATESERIES_RTS_CTS : 0; | |
139 | ath9k_hw_set11n_ratescenario(ah, ds, ds, 0, | |
140 | ctsrate, ctsduration, series, 4, 0); | |
141 | } | |
142 | ||
143 | /* Move everything from the vap's mcast queue to the hardware cab queue. | |
144 | * Caller must hold mcasq lock and cabq lock | |
145 | * XXX MORE_DATA bit? | |
146 | */ | |
147 | static void empty_mcastq_into_cabq(struct ath_hal *ah, | |
148 | struct ath_txq *mcastq, struct ath_txq *cabq) | |
149 | { | |
150 | struct ath_buf *bfmcast; | |
151 | ||
152 | BUG_ON(list_empty(&mcastq->axq_q)); | |
153 | ||
154 | bfmcast = list_first_entry(&mcastq->axq_q, struct ath_buf, list); | |
155 | ||
156 | /* link the descriptors */ | |
157 | if (!cabq->axq_link) | |
158 | ath9k_hw_puttxbuf(ah, cabq->axq_qnum, bfmcast->bf_daddr); | |
159 | else | |
160 | *cabq->axq_link = bfmcast->bf_daddr; | |
161 | ||
162 | /* append the private vap mcast list to the cabq */ | |
163 | ||
164 | cabq->axq_depth += mcastq->axq_depth; | |
165 | cabq->axq_totalqueued += mcastq->axq_totalqueued; | |
166 | cabq->axq_linkbuf = mcastq->axq_linkbuf; | |
167 | cabq->axq_link = mcastq->axq_link; | |
168 | list_splice_tail_init(&mcastq->axq_q, &cabq->axq_q); | |
169 | mcastq->axq_depth = 0; | |
170 | mcastq->axq_totalqueued = 0; | |
171 | mcastq->axq_linkbuf = NULL; | |
172 | mcastq->axq_link = NULL; | |
173 | } | |
174 | ||
a8fff50e | 175 | /* TODO: use ieee80211_get_buffered_bc() to fetch power saved mcast frames */ |
f078f209 LR |
176 | /* This is only run at DTIM. We move everything from the vap's mcast queue |
177 | * to the hardware cab queue. Caller must hold the mcastq lock. */ | |
178 | static void trigger_mcastq(struct ath_hal *ah, | |
179 | struct ath_txq *mcastq, struct ath_txq *cabq) | |
180 | { | |
181 | spin_lock_bh(&cabq->axq_lock); | |
182 | ||
183 | if (!list_empty(&mcastq->axq_q)) | |
184 | empty_mcastq_into_cabq(ah, mcastq, cabq); | |
185 | ||
186 | /* cabq is gated by beacon so it is safe to start here */ | |
187 | if (!list_empty(&cabq->axq_q)) | |
188 | ath9k_hw_txstart(ah, cabq->axq_qnum); | |
189 | ||
190 | spin_unlock_bh(&cabq->axq_lock); | |
191 | } | |
192 | ||
193 | /* | |
194 | * Generate beacon frame and queue cab data for a vap. | |
195 | * | |
196 | * Updates the contents of the beacon frame. It is assumed that the buffer for | |
197 | * the beacon frame has been allocated in the ATH object, and simply needs to | |
198 | * be filled for this cycle. Also, any CAB (crap after beacon?) traffic will | |
199 | * be added to the beacon frame at this point. | |
200 | */ | |
201 | static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id) | |
202 | { | |
203 | struct ath_hal *ah = sc->sc_ah; | |
204 | struct ath_buf *bf; | |
205 | struct ath_vap *avp; | |
206 | struct sk_buff *skb; | |
207 | int cabq_depth; | |
208 | int mcastq_depth; | |
209 | int is_beacon_dtim = 0; | |
f078f209 LR |
210 | struct ath_txq *cabq; |
211 | struct ath_txq *mcastq; | |
212 | avp = sc->sc_vaps[if_id]; | |
213 | ||
214 | mcastq = &avp->av_mcastq; | |
215 | cabq = sc->sc_cabq; | |
216 | ||
217 | ASSERT(avp); | |
218 | ||
219 | if (avp->av_bcbuf == NULL) { | |
220 | DPRINTF(sc, ATH_DBG_BEACON, "%s: avp=%p av_bcbuf=%p\n", | |
221 | __func__, avp, avp->av_bcbuf); | |
222 | return NULL; | |
223 | } | |
224 | bf = avp->av_bcbuf; | |
225 | skb = (struct sk_buff *) bf->bf_mpdu; | |
a8fff50e JM |
226 | if (skb) { |
227 | pci_unmap_single(sc->pdev, bf->bf_dmacontext, | |
228 | skb_end_pointer(skb) - skb->head, | |
229 | PCI_DMA_TODEVICE); | |
230 | } | |
f078f209 | 231 | |
a8fff50e JM |
232 | skb = ieee80211_beacon_get(sc->hw, avp->av_if_data); |
233 | bf->bf_mpdu = skb; | |
234 | if (skb == NULL) | |
235 | return NULL; | |
236 | bf->bf_buf_addr = bf->bf_dmacontext = | |
237 | pci_map_single(sc->pdev, skb->data, | |
238 | skb_end_pointer(skb) - skb->head, | |
239 | PCI_DMA_TODEVICE); | |
f078f209 | 240 | |
a8fff50e | 241 | /* TODO: convert to use ieee80211_get_buffered_bc() */ |
f078f209 LR |
242 | /* XXX: spin_lock_bh should not be used here, but sparse bitches |
243 | * otherwise. We should fix sparse :) */ | |
244 | spin_lock_bh(&mcastq->axq_lock); | |
245 | mcastq_depth = avp->av_mcastq.axq_depth; | |
246 | ||
f078f209 LR |
247 | /* |
248 | * if the CABQ traffic from previous DTIM is pending and the current | |
249 | * beacon is also a DTIM. | |
250 | * 1) if there is only one vap let the cab traffic continue. | |
251 | * 2) if there are more than one vap and we are using staggered | |
252 | * beacons, then drain the cabq by dropping all the frames in | |
253 | * the cabq so that the current vaps cab traffic can be scheduled. | |
254 | */ | |
255 | spin_lock_bh(&cabq->axq_lock); | |
256 | cabq_depth = cabq->axq_depth; | |
257 | spin_unlock_bh(&cabq->axq_lock); | |
258 | ||
a8fff50e JM |
259 | if (avp->av_boff.bo_tim) |
260 | is_beacon_dtim = avp->av_boff.bo_tim[4] & 1; | |
f078f209 LR |
261 | |
262 | if (mcastq_depth && is_beacon_dtim && cabq_depth) { | |
263 | /* | |
264 | * Unlock the cabq lock as ath_tx_draintxq acquires | |
265 | * the lock again which is a common function and that | |
266 | * acquires txq lock inside. | |
267 | */ | |
268 | if (sc->sc_nvaps > 1) { | |
269 | ath_tx_draintxq(sc, cabq, false); | |
270 | DPRINTF(sc, ATH_DBG_BEACON, | |
271 | "%s: flush previous cabq traffic\n", __func__); | |
272 | } | |
273 | } | |
274 | ||
275 | /* Construct tx descriptor. */ | |
276 | ath_beacon_setup(sc, avp, bf); | |
277 | ||
278 | /* | |
279 | * Enable the CAB queue before the beacon queue to | |
280 | * insure cab frames are triggered by this beacon. | |
281 | */ | |
282 | if (is_beacon_dtim) | |
283 | trigger_mcastq(ah, mcastq, cabq); | |
284 | ||
285 | spin_unlock_bh(&mcastq->axq_lock); | |
286 | return bf; | |
287 | } | |
288 | ||
289 | /* | |
290 | * Startup beacon transmission for adhoc mode when they are sent entirely | |
291 | * by the hardware using the self-linked descriptor + veol trick. | |
292 | */ | |
293 | ||
294 | static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id) | |
295 | { | |
296 | struct ath_hal *ah = sc->sc_ah; | |
297 | struct ath_buf *bf; | |
298 | struct ath_vap *avp; | |
299 | struct sk_buff *skb; | |
300 | ||
301 | avp = sc->sc_vaps[if_id]; | |
302 | ASSERT(avp); | |
303 | ||
304 | if (avp->av_bcbuf == NULL) { | |
305 | DPRINTF(sc, ATH_DBG_BEACON, "%s: avp=%p av_bcbuf=%p\n", | |
306 | __func__, avp, avp != NULL ? avp->av_bcbuf : NULL); | |
307 | return; | |
308 | } | |
309 | bf = avp->av_bcbuf; | |
310 | skb = (struct sk_buff *) bf->bf_mpdu; | |
311 | ||
312 | /* Construct tx descriptor. */ | |
313 | ath_beacon_setup(sc, avp, bf); | |
314 | ||
315 | /* NB: caller is known to have already stopped tx dma */ | |
316 | ath9k_hw_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); | |
317 | ath9k_hw_txstart(ah, sc->sc_bhalq); | |
318 | DPRINTF(sc, ATH_DBG_BEACON, "%s: TXDP%u = %llx (%p)\n", __func__, | |
319 | sc->sc_bhalq, ito64(bf->bf_daddr), bf->bf_desc); | |
320 | } | |
321 | ||
322 | /* | |
323 | * Setup a h/w transmit queue for beacons. | |
324 | * | |
325 | * This function allocates an information structure (struct ath9k_txq_info) | |
326 | * on the stack, sets some specific parameters (zero out channel width | |
327 | * min/max, and enable aifs). The info structure does not need to be | |
328 | * persistant. | |
329 | */ | |
330 | ||
331 | int ath_beaconq_setup(struct ath_hal *ah) | |
332 | { | |
ea9880fb | 333 | struct ath9k_tx_queue_info qi; |
f078f209 LR |
334 | |
335 | memzero(&qi, sizeof(qi)); | |
336 | qi.tqi_aifs = 1; | |
337 | qi.tqi_cwmin = 0; | |
338 | qi.tqi_cwmax = 0; | |
339 | /* NB: don't enable any interrupts */ | |
340 | return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi); | |
341 | } | |
342 | ||
343 | ||
344 | /* | |
345 | * Allocate and setup an initial beacon frame. | |
346 | * | |
347 | * Allocate a beacon state variable for a specific VAP instance created on | |
348 | * the ATH interface. This routine also calculates the beacon "slot" for | |
349 | * staggared beacons in the mBSSID case. | |
350 | */ | |
351 | ||
352 | int ath_beacon_alloc(struct ath_softc *sc, int if_id) | |
353 | { | |
354 | struct ath_vap *avp; | |
355 | struct ieee80211_hdr *wh; | |
356 | struct ath_buf *bf; | |
357 | struct sk_buff *skb; | |
358 | ||
359 | avp = sc->sc_vaps[if_id]; | |
360 | ASSERT(avp); | |
361 | ||
362 | /* Allocate a beacon descriptor if we haven't done so. */ | |
363 | if (!avp->av_bcbuf) { | |
364 | /* | |
365 | * Allocate beacon state for hostap/ibss. We know | |
366 | * a buffer is available. | |
367 | */ | |
368 | ||
369 | avp->av_bcbuf = list_first_entry(&sc->sc_bbuf, | |
370 | struct ath_buf, list); | |
371 | list_del(&avp->av_bcbuf->list); | |
372 | ||
b4696c8b | 373 | if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP || |
60b67f51 | 374 | !(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) { |
f078f209 LR |
375 | int slot; |
376 | /* | |
377 | * Assign the vap to a beacon xmit slot. As | |
378 | * above, this cannot fail to find one. | |
379 | */ | |
380 | avp->av_bslot = 0; | |
381 | for (slot = 0; slot < ATH_BCBUF; slot++) | |
382 | if (sc->sc_bslot[slot] == ATH_IF_ID_ANY) { | |
383 | /* | |
384 | * XXX hack, space out slots to better | |
385 | * deal with misses | |
386 | */ | |
387 | if (slot+1 < ATH_BCBUF && | |
388 | sc->sc_bslot[slot+1] == | |
389 | ATH_IF_ID_ANY) { | |
390 | avp->av_bslot = slot+1; | |
391 | break; | |
392 | } | |
393 | avp->av_bslot = slot; | |
394 | /* NB: keep looking for a double slot */ | |
395 | } | |
396 | BUG_ON(sc->sc_bslot[avp->av_bslot] != ATH_IF_ID_ANY); | |
397 | sc->sc_bslot[avp->av_bslot] = if_id; | |
398 | sc->sc_nbcnvaps++; | |
399 | } | |
400 | } | |
401 | ||
402 | /* release the previous beacon frame , if it already exists. */ | |
403 | bf = avp->av_bcbuf; | |
404 | if (bf->bf_mpdu != NULL) { | |
405 | skb = (struct sk_buff *)bf->bf_mpdu; | |
a8fff50e JM |
406 | pci_unmap_single(sc->pdev, bf->bf_dmacontext, |
407 | skb_end_pointer(skb) - skb->head, | |
408 | PCI_DMA_TODEVICE); | |
f078f209 LR |
409 | dev_kfree_skb_any(skb); |
410 | bf->bf_mpdu = NULL; | |
411 | } | |
412 | ||
413 | /* | |
414 | * NB: the beacon data buffer must be 32-bit aligned; | |
415 | * we assume the wbuf routines will return us something | |
416 | * with this alignment (perhaps should assert). | |
417 | * FIXME: Fill avp->av_boff.bo_tim,avp->av_btxctl.txpower and | |
418 | * avp->av_btxctl.shortPreamble | |
419 | */ | |
420 | skb = ieee80211_beacon_get(sc->hw, avp->av_if_data); | |
421 | if (skb == NULL) { | |
422 | DPRINTF(sc, ATH_DBG_BEACON, "%s: cannot get skb\n", | |
423 | __func__); | |
424 | return -ENOMEM; | |
425 | } | |
426 | ||
427 | /* | |
428 | * Calculate a TSF adjustment factor required for | |
429 | * staggered beacons. Note that we assume the format | |
430 | * of the beacon frame leaves the tstamp field immediately | |
431 | * following the header. | |
432 | */ | |
433 | if (avp->av_bslot > 0) { | |
434 | u64 tsfadjust; | |
435 | __le64 val; | |
436 | int intval; | |
437 | ||
a8fff50e JM |
438 | intval = sc->hw->conf.beacon_int ? |
439 | sc->hw->conf.beacon_int : ATH_DEFAULT_BINTVAL; | |
f078f209 LR |
440 | |
441 | /* | |
442 | * The beacon interval is in TU's; the TSF in usecs. | |
443 | * We figure out how many TU's to add to align the | |
444 | * timestamp then convert to TSF units and handle | |
445 | * byte swapping before writing it in the frame. | |
446 | * The hardware will then add this each time a beacon | |
447 | * frame is sent. Note that we align vap's 1..N | |
448 | * and leave vap 0 untouched. This means vap 0 | |
449 | * has a timestamp in one beacon interval while the | |
450 | * others get a timestamp aligned to the next interval. | |
451 | */ | |
452 | tsfadjust = (intval * (ATH_BCBUF - avp->av_bslot)) / ATH_BCBUF; | |
453 | val = cpu_to_le64(tsfadjust << 10); /* TU->TSF */ | |
454 | ||
455 | DPRINTF(sc, ATH_DBG_BEACON, | |
456 | "%s: %s beacons, bslot %d intval %u tsfadjust %llu\n", | |
457 | __func__, "stagger", | |
458 | avp->av_bslot, intval, (unsigned long long)tsfadjust); | |
459 | ||
460 | wh = (struct ieee80211_hdr *)skb->data; | |
461 | memcpy(&wh[1], &val, sizeof(val)); | |
462 | } | |
463 | ||
a8fff50e JM |
464 | bf->bf_buf_addr = bf->bf_dmacontext = |
465 | pci_map_single(sc->pdev, skb->data, | |
466 | skb_end_pointer(skb) - skb->head, | |
467 | PCI_DMA_TODEVICE); | |
f078f209 LR |
468 | bf->bf_mpdu = skb; |
469 | ||
470 | return 0; | |
471 | } | |
472 | ||
473 | /* | |
474 | * Reclaim beacon resources and return buffer to the pool. | |
475 | * | |
476 | * Checks the VAP to put the beacon frame buffer back to the ATH object | |
477 | * queue, and de-allocates any wbuf frames that were sent as CAB traffic. | |
478 | */ | |
479 | ||
480 | void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp) | |
481 | { | |
482 | if (avp->av_bcbuf != NULL) { | |
483 | struct ath_buf *bf; | |
484 | ||
485 | if (avp->av_bslot != -1) { | |
486 | sc->sc_bslot[avp->av_bslot] = ATH_IF_ID_ANY; | |
487 | sc->sc_nbcnvaps--; | |
488 | } | |
489 | ||
490 | bf = avp->av_bcbuf; | |
491 | if (bf->bf_mpdu != NULL) { | |
492 | struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu; | |
a8fff50e JM |
493 | pci_unmap_single(sc->pdev, bf->bf_dmacontext, |
494 | skb_end_pointer(skb) - skb->head, | |
495 | PCI_DMA_TODEVICE); | |
f078f209 LR |
496 | dev_kfree_skb_any(skb); |
497 | bf->bf_mpdu = NULL; | |
498 | } | |
499 | list_add_tail(&bf->list, &sc->sc_bbuf); | |
500 | ||
501 | avp->av_bcbuf = NULL; | |
502 | } | |
503 | } | |
504 | ||
505 | /* | |
506 | * Reclaim beacon resources and return buffer to the pool. | |
507 | * | |
508 | * This function will free any wbuf frames that are still attached to the | |
509 | * beacon buffers in the ATH object. Note that this does not de-allocate | |
510 | * any wbuf objects that are in the transmit queue and have not yet returned | |
511 | * to the ATH object. | |
512 | */ | |
513 | ||
514 | void ath_beacon_free(struct ath_softc *sc) | |
515 | { | |
516 | struct ath_buf *bf; | |
517 | ||
518 | list_for_each_entry(bf, &sc->sc_bbuf, list) { | |
519 | if (bf->bf_mpdu != NULL) { | |
520 | struct sk_buff *skb = (struct sk_buff *) bf->bf_mpdu; | |
a8fff50e JM |
521 | pci_unmap_single(sc->pdev, bf->bf_dmacontext, |
522 | skb_end_pointer(skb) - skb->head, | |
523 | PCI_DMA_TODEVICE); | |
f078f209 LR |
524 | dev_kfree_skb_any(skb); |
525 | bf->bf_mpdu = NULL; | |
526 | } | |
527 | } | |
528 | } | |
529 | ||
530 | /* | |
531 | * Tasklet for Sending Beacons | |
532 | * | |
533 | * Transmit one or more beacon frames at SWBA. Dynamic updates to the frame | |
534 | * contents are done as needed and the slot time is also adjusted based on | |
535 | * current state. | |
536 | * | |
537 | * This tasklet is not scheduled, it's called in ISR context. | |
538 | */ | |
539 | ||
540 | void ath9k_beacon_tasklet(unsigned long data) | |
541 | { | |
542 | #define TSF_TO_TU(_h,_l) \ | |
543 | ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) | |
544 | ||
545 | struct ath_softc *sc = (struct ath_softc *)data; | |
546 | struct ath_hal *ah = sc->sc_ah; | |
547 | struct ath_buf *bf = NULL; | |
548 | int slot, if_id; | |
549 | u32 bfaddr; | |
550 | u32 rx_clear = 0, rx_frame = 0, tx_frame = 0; | |
551 | u32 show_cycles = 0; | |
552 | u32 bc = 0; /* beacon count */ | |
553 | u64 tsf; | |
554 | u32 tsftu; | |
555 | u16 intval; | |
556 | ||
98deeea0 | 557 | if (sc->sc_flags & SC_OP_NO_RESET) { |
f078f209 LR |
558 | show_cycles = ath9k_hw_GetMibCycleCountsPct(ah, |
559 | &rx_clear, | |
560 | &rx_frame, | |
561 | &tx_frame); | |
562 | } | |
563 | ||
564 | /* | |
565 | * Check if the previous beacon has gone out. If | |
566 | * not don't try to post another, skip this period | |
567 | * and wait for the next. Missed beacons indicate | |
568 | * a problem and should not occur. If we miss too | |
569 | * many consecutive beacons reset the device. | |
570 | */ | |
571 | if (ath9k_hw_numtxpending(ah, sc->sc_bhalq) != 0) { | |
572 | sc->sc_bmisscount++; | |
573 | /* XXX: doth needs the chanchange IE countdown decremented. | |
574 | * We should consider adding a mac80211 call to indicate | |
575 | * a beacon miss so appropriate action could be taken | |
576 | * (in that layer). | |
577 | */ | |
578 | if (sc->sc_bmisscount < BSTUCK_THRESH) { | |
98deeea0 | 579 | if (sc->sc_flags & SC_OP_NO_RESET) { |
f078f209 LR |
580 | DPRINTF(sc, ATH_DBG_BEACON, |
581 | "%s: missed %u consecutive beacons\n", | |
582 | __func__, sc->sc_bmisscount); | |
583 | if (show_cycles) { | |
584 | /* | |
585 | * Display cycle counter stats | |
586 | * from HW to aide in debug of | |
587 | * stickiness. | |
588 | */ | |
589 | DPRINTF(sc, | |
590 | ATH_DBG_BEACON, | |
591 | "%s: busy times: rx_clear=%d, " | |
592 | "rx_frame=%d, tx_frame=%d\n", | |
593 | __func__, rx_clear, rx_frame, | |
594 | tx_frame); | |
595 | } else { | |
596 | DPRINTF(sc, | |
597 | ATH_DBG_BEACON, | |
598 | "%s: unable to obtain " | |
599 | "busy times\n", __func__); | |
600 | } | |
601 | } else { | |
602 | DPRINTF(sc, ATH_DBG_BEACON, | |
603 | "%s: missed %u consecutive beacons\n", | |
604 | __func__, sc->sc_bmisscount); | |
605 | } | |
606 | } else if (sc->sc_bmisscount >= BSTUCK_THRESH) { | |
98deeea0 | 607 | if (sc->sc_flags & SC_OP_NO_RESET) { |
f078f209 LR |
608 | if (sc->sc_bmisscount == BSTUCK_THRESH) { |
609 | DPRINTF(sc, | |
610 | ATH_DBG_BEACON, | |
611 | "%s: beacon is officially " | |
612 | "stuck\n", __func__); | |
613 | ath9k_hw_dmaRegDump(ah); | |
614 | } | |
615 | } else { | |
616 | DPRINTF(sc, ATH_DBG_BEACON, | |
617 | "%s: beacon is officially stuck\n", | |
618 | __func__); | |
619 | ath_bstuck_process(sc); | |
620 | } | |
621 | } | |
622 | ||
623 | return; | |
624 | } | |
625 | if (sc->sc_bmisscount != 0) { | |
98deeea0 | 626 | if (sc->sc_flags & SC_OP_NO_RESET) { |
f078f209 LR |
627 | DPRINTF(sc, |
628 | ATH_DBG_BEACON, | |
629 | "%s: resume beacon xmit after %u misses\n", | |
630 | __func__, sc->sc_bmisscount); | |
631 | } else { | |
632 | DPRINTF(sc, ATH_DBG_BEACON, | |
633 | "%s: resume beacon xmit after %u misses\n", | |
634 | __func__, sc->sc_bmisscount); | |
635 | } | |
636 | sc->sc_bmisscount = 0; | |
637 | } | |
638 | ||
639 | /* | |
640 | * Generate beacon frames. we are sending frames | |
641 | * staggered so calculate the slot for this frame based | |
642 | * on the tsf to safeguard against missing an swba. | |
643 | */ | |
644 | ||
a8fff50e JM |
645 | intval = sc->hw->conf.beacon_int ? |
646 | sc->hw->conf.beacon_int : ATH_DEFAULT_BINTVAL; | |
f078f209 LR |
647 | |
648 | tsf = ath9k_hw_gettsf64(ah); | |
649 | tsftu = TSF_TO_TU(tsf>>32, tsf); | |
650 | slot = ((tsftu % intval) * ATH_BCBUF) / intval; | |
651 | if_id = sc->sc_bslot[(slot + 1) % ATH_BCBUF]; | |
652 | DPRINTF(sc, ATH_DBG_BEACON, | |
653 | "%s: slot %d [tsf %llu tsftu %u intval %u] if_id %d\n", | |
654 | __func__, slot, (unsigned long long) tsf, tsftu, | |
655 | intval, if_id); | |
656 | bfaddr = 0; | |
657 | if (if_id != ATH_IF_ID_ANY) { | |
658 | bf = ath_beacon_generate(sc, if_id); | |
659 | if (bf != NULL) { | |
660 | bfaddr = bf->bf_daddr; | |
661 | bc = 1; | |
662 | } | |
663 | } | |
664 | /* | |
665 | * Handle slot time change when a non-ERP station joins/leaves | |
666 | * an 11g network. The 802.11 layer notifies us via callback, | |
667 | * we mark updateslot, then wait one beacon before effecting | |
668 | * the change. This gives associated stations at least one | |
669 | * beacon interval to note the state change. | |
670 | * | |
671 | * NB: The slot time change state machine is clocked according | |
672 | * to whether we are bursting or staggering beacons. We | |
673 | * recognize the request to update and record the current | |
674 | * slot then don't transition until that slot is reached | |
675 | * again. If we miss a beacon for that slot then we'll be | |
676 | * slow to transition but we'll be sure at least one beacon | |
677 | * interval has passed. When bursting slot is always left | |
678 | * set to ATH_BCBUF so this check is a noop. | |
679 | */ | |
680 | /* XXX locking */ | |
681 | if (sc->sc_updateslot == UPDATE) { | |
682 | sc->sc_updateslot = COMMIT; /* commit next beacon */ | |
683 | sc->sc_slotupdate = slot; | |
684 | } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot) | |
685 | ath_setslottime(sc); /* commit change to hardware */ | |
686 | ||
687 | if (bfaddr != 0) { | |
688 | /* | |
689 | * Stop any current dma and put the new frame(s) on the queue. | |
690 | * This should never fail since we check above that no frames | |
691 | * are still pending on the queue. | |
692 | */ | |
693 | if (!ath9k_hw_stoptxdma(ah, sc->sc_bhalq)) { | |
694 | DPRINTF(sc, ATH_DBG_FATAL, | |
695 | "%s: beacon queue %u did not stop?\n", | |
696 | __func__, sc->sc_bhalq); | |
697 | /* NB: the HAL still stops DMA, so proceed */ | |
698 | } | |
699 | ||
700 | /* NB: cabq traffic should already be queued and primed */ | |
701 | ath9k_hw_puttxbuf(ah, sc->sc_bhalq, bfaddr); | |
702 | ath9k_hw_txstart(ah, sc->sc_bhalq); | |
703 | ||
704 | sc->ast_be_xmit += bc; /* XXX per-vap? */ | |
705 | } | |
706 | #undef TSF_TO_TU | |
707 | } | |
708 | ||
709 | /* | |
710 | * Tasklet for Beacon Stuck processing | |
711 | * | |
712 | * Processing for Beacon Stuck. | |
713 | * Basically calls the ath_internal_reset function to reset the chip. | |
714 | */ | |
715 | ||
716 | void ath_bstuck_process(struct ath_softc *sc) | |
717 | { | |
718 | DPRINTF(sc, ATH_DBG_BEACON, | |
719 | "%s: stuck beacon; resetting (bmiss count %u)\n", | |
720 | __func__, sc->sc_bmisscount); | |
f45144ef | 721 | ath_reset(sc, false); |
f078f209 LR |
722 | } |
723 | ||
724 | /* | |
725 | * Configure the beacon and sleep timers. | |
726 | * | |
727 | * When operating as an AP this resets the TSF and sets | |
728 | * up the hardware to notify us when we need to issue beacons. | |
729 | * | |
730 | * When operating in station mode this sets up the beacon | |
731 | * timers according to the timestamp of the last received | |
732 | * beacon and the current TSF, configures PCF and DTIM | |
733 | * handling, programs the sleep registers so the hardware | |
734 | * will wakeup in time to receive beacons, and configures | |
735 | * the beacon miss handling so we'll receive a BMISS | |
736 | * interrupt when we stop seeing beacons from the AP | |
737 | * we've associated with. | |
738 | */ | |
739 | ||
740 | void ath_beacon_config(struct ath_softc *sc, int if_id) | |
741 | { | |
742 | #define TSF_TO_TU(_h,_l) \ | |
743 | ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) | |
744 | struct ath_hal *ah = sc->sc_ah; | |
745 | u32 nexttbtt, intval; | |
746 | struct ath_beacon_config conf; | |
747 | enum ath9k_opmode av_opmode; | |
748 | ||
749 | if (if_id != ATH_IF_ID_ANY) | |
750 | av_opmode = sc->sc_vaps[if_id]->av_opmode; | |
751 | else | |
b4696c8b | 752 | av_opmode = sc->sc_ah->ah_opmode; |
f078f209 LR |
753 | |
754 | memzero(&conf, sizeof(struct ath_beacon_config)); | |
755 | ||
756 | /* FIXME: Use default values for now - Sujith */ | |
757 | /* Query beacon configuration first */ | |
758 | /* | |
759 | * Protocol stack doesn't support dynamic beacon configuration, | |
760 | * use default configurations. | |
761 | */ | |
a8fff50e JM |
762 | conf.beacon_interval = sc->hw->conf.beacon_int ? |
763 | sc->hw->conf.beacon_int : ATH_DEFAULT_BINTVAL; | |
f078f209 LR |
764 | conf.listen_interval = 1; |
765 | conf.dtim_period = conf.beacon_interval; | |
766 | conf.dtim_count = 1; | |
767 | conf.bmiss_timeout = ATH_DEFAULT_BMISS_LIMIT * conf.beacon_interval; | |
768 | ||
769 | /* extract tstamp from last beacon and convert to TU */ | |
770 | nexttbtt = TSF_TO_TU(get_unaligned_le32(conf.u.last_tstamp + 4), | |
771 | get_unaligned_le32(conf.u.last_tstamp)); | |
772 | /* XXX conditionalize multi-bss support? */ | |
b4696c8b | 773 | if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP) { |
f078f209 LR |
774 | /* |
775 | * For multi-bss ap support beacons are either staggered | |
776 | * evenly over N slots or burst together. For the former | |
777 | * arrange for the SWBA to be delivered for each slot. | |
778 | * Slots that are not occupied will generate nothing. | |
779 | */ | |
780 | /* NB: the beacon interval is kept internally in TU's */ | |
781 | intval = conf.beacon_interval & ATH9K_BEACON_PERIOD; | |
782 | intval /= ATH_BCBUF; /* for staggered beacons */ | |
783 | } else { | |
784 | intval = conf.beacon_interval & ATH9K_BEACON_PERIOD; | |
785 | } | |
786 | ||
787 | if (nexttbtt == 0) /* e.g. for ap mode */ | |
788 | nexttbtt = intval; | |
789 | else if (intval) /* NB: can be 0 for monitor mode */ | |
790 | nexttbtt = roundup(nexttbtt, intval); | |
791 | DPRINTF(sc, ATH_DBG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", | |
792 | __func__, nexttbtt, intval, conf.beacon_interval); | |
793 | /* Check for ATH9K_M_HOSTAP and sc_nostabeacons for WDS client */ | |
b4696c8b | 794 | if (sc->sc_ah->ah_opmode == ATH9K_M_STA) { |
f078f209 LR |
795 | struct ath9k_beacon_state bs; |
796 | u64 tsf; | |
797 | u32 tsftu; | |
798 | int dtimperiod, dtimcount, sleepduration; | |
799 | int cfpperiod, cfpcount; | |
800 | ||
801 | /* | |
802 | * Setup dtim and cfp parameters according to | |
803 | * last beacon we received (which may be none). | |
804 | */ | |
805 | dtimperiod = conf.dtim_period; | |
806 | if (dtimperiod <= 0) /* NB: 0 if not known */ | |
807 | dtimperiod = 1; | |
808 | dtimcount = conf.dtim_count; | |
809 | if (dtimcount >= dtimperiod) /* NB: sanity check */ | |
810 | dtimcount = 0; /* XXX? */ | |
811 | cfpperiod = 1; /* NB: no PCF support yet */ | |
812 | cfpcount = 0; | |
813 | ||
814 | sleepduration = conf.listen_interval * intval; | |
815 | if (sleepduration <= 0) | |
816 | sleepduration = intval; | |
817 | ||
818 | #define FUDGE 2 | |
819 | /* | |
820 | * Pull nexttbtt forward to reflect the current | |
821 | * TSF and calculate dtim+cfp state for the result. | |
822 | */ | |
823 | tsf = ath9k_hw_gettsf64(ah); | |
824 | tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; | |
825 | do { | |
826 | nexttbtt += intval; | |
827 | if (--dtimcount < 0) { | |
828 | dtimcount = dtimperiod - 1; | |
829 | if (--cfpcount < 0) | |
830 | cfpcount = cfpperiod - 1; | |
831 | } | |
832 | } while (nexttbtt < tsftu); | |
833 | #undef FUDGE | |
834 | memzero(&bs, sizeof(bs)); | |
835 | bs.bs_intval = intval; | |
836 | bs.bs_nexttbtt = nexttbtt; | |
837 | bs.bs_dtimperiod = dtimperiod*intval; | |
838 | bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; | |
839 | bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; | |
840 | bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; | |
841 | bs.bs_cfpmaxduration = 0; | |
842 | /* | |
843 | * Calculate the number of consecutive beacons to miss | |
844 | * before taking a BMISS interrupt. The configuration | |
845 | * is specified in TU so we only need calculate based | |
846 | * on the beacon interval. Note that we clamp the | |
847 | * result to at most 15 beacons. | |
848 | */ | |
849 | if (sleepduration > intval) { | |
850 | bs.bs_bmissthreshold = | |
851 | conf.listen_interval * | |
852 | ATH_DEFAULT_BMISS_LIMIT / 2; | |
853 | } else { | |
854 | bs.bs_bmissthreshold = | |
855 | DIV_ROUND_UP(conf.bmiss_timeout, intval); | |
856 | if (bs.bs_bmissthreshold > 15) | |
857 | bs.bs_bmissthreshold = 15; | |
858 | else if (bs.bs_bmissthreshold <= 0) | |
859 | bs.bs_bmissthreshold = 1; | |
860 | } | |
861 | ||
862 | /* | |
863 | * Calculate sleep duration. The configuration is | |
864 | * given in ms. We insure a multiple of the beacon | |
865 | * period is used. Also, if the sleep duration is | |
866 | * greater than the DTIM period then it makes senses | |
867 | * to make it a multiple of that. | |
868 | * | |
869 | * XXX fixed at 100ms | |
870 | */ | |
871 | ||
872 | bs.bs_sleepduration = | |
873 | roundup(IEEE80211_MS_TO_TU(100), sleepduration); | |
874 | if (bs.bs_sleepduration > bs.bs_dtimperiod) | |
875 | bs.bs_sleepduration = bs.bs_dtimperiod; | |
876 | ||
877 | DPRINTF(sc, ATH_DBG_BEACON, | |
878 | "%s: tsf %llu " | |
879 | "tsf:tu %u " | |
880 | "intval %u " | |
881 | "nexttbtt %u " | |
882 | "dtim %u " | |
883 | "nextdtim %u " | |
884 | "bmiss %u " | |
885 | "sleep %u " | |
886 | "cfp:period %u " | |
887 | "maxdur %u " | |
888 | "next %u " | |
889 | "timoffset %u\n" | |
890 | , __func__ | |
891 | , (unsigned long long)tsf, tsftu | |
892 | , bs.bs_intval | |
893 | , bs.bs_nexttbtt | |
894 | , bs.bs_dtimperiod | |
895 | , bs.bs_nextdtim | |
896 | , bs.bs_bmissthreshold | |
897 | , bs.bs_sleepduration | |
898 | , bs.bs_cfpperiod | |
899 | , bs.bs_cfpmaxduration | |
900 | , bs.bs_cfpnext | |
901 | , bs.bs_timoffset | |
902 | ); | |
903 | ||
904 | ath9k_hw_set_interrupts(ah, 0); | |
905 | ath9k_hw_set_sta_beacon_timers(ah, &bs); | |
906 | sc->sc_imask |= ATH9K_INT_BMISS; | |
907 | ath9k_hw_set_interrupts(ah, sc->sc_imask); | |
908 | } else { | |
909 | u64 tsf; | |
910 | u32 tsftu; | |
911 | ath9k_hw_set_interrupts(ah, 0); | |
912 | if (nexttbtt == intval) | |
913 | intval |= ATH9K_BEACON_RESET_TSF; | |
b4696c8b | 914 | if (sc->sc_ah->ah_opmode == ATH9K_M_IBSS) { |
f078f209 LR |
915 | /* |
916 | * Pull nexttbtt forward to reflect the current | |
917 | * TSF . | |
918 | */ | |
919 | #define FUDGE 2 | |
920 | if (!(intval & ATH9K_BEACON_RESET_TSF)) { | |
921 | tsf = ath9k_hw_gettsf64(ah); | |
922 | tsftu = TSF_TO_TU((u32)(tsf>>32), | |
923 | (u32)tsf) + FUDGE; | |
924 | do { | |
925 | nexttbtt += intval; | |
926 | } while (nexttbtt < tsftu); | |
927 | } | |
928 | #undef FUDGE | |
929 | DPRINTF(sc, ATH_DBG_BEACON, | |
930 | "%s: IBSS nexttbtt %u intval %u (%u)\n", | |
931 | __func__, nexttbtt, | |
932 | intval & ~ATH9K_BEACON_RESET_TSF, | |
933 | conf.beacon_interval); | |
934 | ||
935 | /* | |
936 | * In IBSS mode enable the beacon timers but only | |
937 | * enable SWBA interrupts if we need to manually | |
938 | * prepare beacon frames. Otherwise we use a | |
939 | * self-linked tx descriptor and let the hardware | |
940 | * deal with things. | |
941 | */ | |
942 | intval |= ATH9K_BEACON_ENA; | |
60b67f51 | 943 | if (!(ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) |
f078f209 LR |
944 | sc->sc_imask |= ATH9K_INT_SWBA; |
945 | ath_beaconq_config(sc); | |
b4696c8b | 946 | } else if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP) { |
f078f209 LR |
947 | /* |
948 | * In AP mode we enable the beacon timers and | |
949 | * SWBA interrupts to prepare beacon frames. | |
950 | */ | |
951 | intval |= ATH9K_BEACON_ENA; | |
952 | sc->sc_imask |= ATH9K_INT_SWBA; /* beacon prepare */ | |
953 | ath_beaconq_config(sc); | |
954 | } | |
955 | ath9k_hw_beaconinit(ah, nexttbtt, intval); | |
956 | sc->sc_bmisscount = 0; | |
957 | ath9k_hw_set_interrupts(ah, sc->sc_imask); | |
958 | /* | |
959 | * When using a self-linked beacon descriptor in | |
960 | * ibss mode load it once here. | |
961 | */ | |
b4696c8b | 962 | if (sc->sc_ah->ah_opmode == ATH9K_M_IBSS && |
60b67f51 | 963 | (ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) |
f078f209 LR |
964 | ath_beacon_start_adhoc(sc, 0); |
965 | } | |
966 | #undef TSF_TO_TU | |
967 | } | |
968 | ||
969 | /* Function to collect beacon rssi data and resync beacon if necessary */ | |
970 | ||
971 | void ath_beacon_sync(struct ath_softc *sc, int if_id) | |
972 | { | |
973 | /* | |
974 | * Resync beacon timers using the tsf of the | |
975 | * beacon frame we just received. | |
976 | */ | |
977 | ath_beacon_config(sc, if_id); | |
672840ac | 978 | sc->sc_flags |= SC_OP_BEACONS; |
f078f209 | 979 | } |