Commit | Line | Data |
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f078f209 LR |
1 | /* |
2 | * Copyright (c) 2008 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | /* Implementation of beacon processing. */ | |
18 | ||
19 | #include <asm/unaligned.h> | |
20 | #include "core.h" | |
21 | ||
22 | /* | |
23 | * Configure parameters for the beacon queue | |
24 | * | |
25 | * This function will modify certain transmit queue properties depending on | |
26 | * the operating mode of the station (AP or AdHoc). Parameters are AIFS | |
27 | * settings and channel width min/max | |
28 | */ | |
29 | ||
30 | static int ath_beaconq_config(struct ath_softc *sc) | |
31 | { | |
32 | struct ath_hal *ah = sc->sc_ah; | |
ea9880fb | 33 | struct ath9k_tx_queue_info qi; |
f078f209 | 34 | |
ea9880fb | 35 | ath9k_hw_get_txq_props(ah, sc->sc_bhalq, &qi); |
b4696c8b | 36 | if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP) { |
f078f209 LR |
37 | /* Always burst out beacon and CAB traffic. */ |
38 | qi.tqi_aifs = 1; | |
39 | qi.tqi_cwmin = 0; | |
40 | qi.tqi_cwmax = 0; | |
41 | } else { | |
42 | /* Adhoc mode; important thing is to use 2x cwmin. */ | |
43 | qi.tqi_aifs = sc->sc_beacon_qi.tqi_aifs; | |
44 | qi.tqi_cwmin = 2*sc->sc_beacon_qi.tqi_cwmin; | |
45 | qi.tqi_cwmax = sc->sc_beacon_qi.tqi_cwmax; | |
46 | } | |
47 | ||
ea9880fb | 48 | if (!ath9k_hw_set_txq_props(ah, sc->sc_bhalq, &qi)) { |
f078f209 LR |
49 | DPRINTF(sc, ATH_DBG_FATAL, |
50 | "%s: unable to update h/w beacon queue parameters\n", | |
51 | __func__); | |
52 | return 0; | |
53 | } else { | |
54 | ath9k_hw_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ | |
55 | return 1; | |
56 | } | |
57 | } | |
58 | ||
59 | /* | |
60 | * Setup the beacon frame for transmit. | |
61 | * | |
62 | * Associates the beacon frame buffer with a transmit descriptor. Will set | |
63 | * up all required antenna switch parameters, rate codes, and channel flags. | |
64 | * Beacons are always sent out at the lowest rate, and are not retried. | |
65 | */ | |
66 | ||
67 | static void ath_beacon_setup(struct ath_softc *sc, | |
68 | struct ath_vap *avp, struct ath_buf *bf) | |
69 | { | |
70 | struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu; | |
71 | struct ath_hal *ah = sc->sc_ah; | |
72 | struct ath_desc *ds; | |
73 | int flags, antenna; | |
74 | const struct ath9k_rate_table *rt; | |
75 | u8 rix, rate; | |
76 | int ctsrate = 0; | |
77 | int ctsduration = 0; | |
78 | struct ath9k_11n_rate_series series[4]; | |
79 | ||
80 | DPRINTF(sc, ATH_DBG_BEACON, "%s: m %p len %u\n", | |
81 | __func__, skb, skb->len); | |
82 | ||
83 | /* setup descriptors */ | |
84 | ds = bf->bf_desc; | |
85 | ||
86 | flags = ATH9K_TXDESC_NOACK; | |
87 | ||
b4696c8b | 88 | if (sc->sc_ah->ah_opmode == ATH9K_M_IBSS && |
60b67f51 | 89 | (ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) { |
f078f209 LR |
90 | ds->ds_link = bf->bf_daddr; /* self-linked */ |
91 | flags |= ATH9K_TXDESC_VEOL; | |
92 | /* Let hardware handle antenna switching. */ | |
93 | antenna = 0; | |
94 | } else { | |
95 | ds->ds_link = 0; | |
96 | /* | |
97 | * Switch antenna every beacon. | |
98 | * Should only switch every beacon period, not for every | |
99 | * SWBA's | |
100 | * XXX assumes two antenna | |
101 | */ | |
102 | antenna = ((sc->ast_be_xmit / sc->sc_nbcnvaps) & 1 ? 2 : 1); | |
103 | } | |
104 | ||
105 | ds->ds_data = bf->bf_buf_addr; | |
106 | ||
107 | /* | |
108 | * Calculate rate code. | |
109 | * XXX everything at min xmit rate | |
110 | */ | |
86b89eed | 111 | rix = 0; |
f078f209 LR |
112 | rt = sc->sc_currates; |
113 | rate = rt->info[rix].rateCode; | |
672840ac | 114 | if (sc->sc_flags & SC_OP_PREAMBLE_SHORT) |
f078f209 LR |
115 | rate |= rt->info[rix].shortPreamble; |
116 | ||
ff9b662d S |
117 | ath9k_hw_set11n_txdesc(ah, ds, |
118 | skb->len + FCS_LEN, /* frame length */ | |
119 | ATH9K_PKT_TYPE_BEACON, /* Atheros packet type */ | |
120 | avp->av_btxctl.txpower, /* txpower XXX */ | |
121 | ATH9K_TXKEYIX_INVALID, /* no encryption */ | |
122 | ATH9K_KEY_TYPE_CLEAR, /* no encryption */ | |
123 | flags /* no ack, veol for beacons */ | |
f078f209 LR |
124 | ); |
125 | ||
126 | /* NB: beacon's BufLen must be a multiple of 4 bytes */ | |
ff9b662d S |
127 | ath9k_hw_filltxdesc(ah, ds, |
128 | roundup(skb->len, 4), /* buffer length */ | |
129 | true, /* first segment */ | |
130 | true, /* last segment */ | |
131 | ds /* first descriptor */ | |
f078f209 LR |
132 | ); |
133 | ||
134 | memzero(series, sizeof(struct ath9k_11n_rate_series) * 4); | |
135 | series[0].Tries = 1; | |
136 | series[0].Rate = rate; | |
137 | series[0].ChSel = sc->sc_tx_chainmask; | |
138 | series[0].RateFlags = (ctsrate) ? ATH9K_RATESERIES_RTS_CTS : 0; | |
139 | ath9k_hw_set11n_ratescenario(ah, ds, ds, 0, | |
140 | ctsrate, ctsduration, series, 4, 0); | |
141 | } | |
142 | ||
f078f209 LR |
143 | /* |
144 | * Generate beacon frame and queue cab data for a vap. | |
145 | * | |
146 | * Updates the contents of the beacon frame. It is assumed that the buffer for | |
147 | * the beacon frame has been allocated in the ATH object, and simply needs to | |
148 | * be filled for this cycle. Also, any CAB (crap after beacon?) traffic will | |
149 | * be added to the beacon frame at this point. | |
150 | */ | |
151 | static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id) | |
152 | { | |
f078f209 LR |
153 | struct ath_buf *bf; |
154 | struct ath_vap *avp; | |
155 | struct sk_buff *skb; | |
156 | int cabq_depth; | |
f078f209 | 157 | struct ath_txq *cabq; |
147583c0 | 158 | struct ieee80211_tx_info *info; |
f078f209 LR |
159 | avp = sc->sc_vaps[if_id]; |
160 | ||
f078f209 LR |
161 | cabq = sc->sc_cabq; |
162 | ||
163 | ASSERT(avp); | |
164 | ||
165 | if (avp->av_bcbuf == NULL) { | |
166 | DPRINTF(sc, ATH_DBG_BEACON, "%s: avp=%p av_bcbuf=%p\n", | |
167 | __func__, avp, avp->av_bcbuf); | |
168 | return NULL; | |
169 | } | |
170 | bf = avp->av_bcbuf; | |
171 | skb = (struct sk_buff *) bf->bf_mpdu; | |
a8fff50e JM |
172 | if (skb) { |
173 | pci_unmap_single(sc->pdev, bf->bf_dmacontext, | |
174 | skb_end_pointer(skb) - skb->head, | |
175 | PCI_DMA_TODEVICE); | |
176 | } | |
f078f209 | 177 | |
a8fff50e JM |
178 | skb = ieee80211_beacon_get(sc->hw, avp->av_if_data); |
179 | bf->bf_mpdu = skb; | |
180 | if (skb == NULL) | |
181 | return NULL; | |
147583c0 JM |
182 | info = IEEE80211_SKB_CB(skb); |
183 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { | |
184 | /* | |
185 | * TODO: make sure the seq# gets assigned properly (vs. other | |
186 | * TX frames) | |
187 | */ | |
188 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
189 | sc->seq_no += 0x10; | |
190 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); | |
191 | hdr->seq_ctrl |= cpu_to_le16(sc->seq_no); | |
192 | } | |
a8fff50e JM |
193 | bf->bf_buf_addr = bf->bf_dmacontext = |
194 | pci_map_single(sc->pdev, skb->data, | |
195 | skb_end_pointer(skb) - skb->head, | |
196 | PCI_DMA_TODEVICE); | |
f078f209 | 197 | |
e022edbd | 198 | skb = ieee80211_get_buffered_bc(sc->hw, avp->av_if_data); |
f078f209 | 199 | |
f078f209 LR |
200 | /* |
201 | * if the CABQ traffic from previous DTIM is pending and the current | |
202 | * beacon is also a DTIM. | |
203 | * 1) if there is only one vap let the cab traffic continue. | |
204 | * 2) if there are more than one vap and we are using staggered | |
205 | * beacons, then drain the cabq by dropping all the frames in | |
206 | * the cabq so that the current vaps cab traffic can be scheduled. | |
207 | */ | |
208 | spin_lock_bh(&cabq->axq_lock); | |
209 | cabq_depth = cabq->axq_depth; | |
210 | spin_unlock_bh(&cabq->axq_lock); | |
211 | ||
e022edbd | 212 | if (skb && cabq_depth) { |
f078f209 LR |
213 | /* |
214 | * Unlock the cabq lock as ath_tx_draintxq acquires | |
215 | * the lock again which is a common function and that | |
216 | * acquires txq lock inside. | |
217 | */ | |
218 | if (sc->sc_nvaps > 1) { | |
219 | ath_tx_draintxq(sc, cabq, false); | |
220 | DPRINTF(sc, ATH_DBG_BEACON, | |
221 | "%s: flush previous cabq traffic\n", __func__); | |
222 | } | |
223 | } | |
224 | ||
225 | /* Construct tx descriptor. */ | |
226 | ath_beacon_setup(sc, avp, bf); | |
227 | ||
228 | /* | |
229 | * Enable the CAB queue before the beacon queue to | |
230 | * insure cab frames are triggered by this beacon. | |
231 | */ | |
e022edbd JM |
232 | while (skb) { |
233 | ath_tx_cabq(sc, skb); | |
234 | skb = ieee80211_get_buffered_bc(sc->hw, avp->av_if_data); | |
235 | } | |
f078f209 | 236 | |
f078f209 LR |
237 | return bf; |
238 | } | |
239 | ||
240 | /* | |
241 | * Startup beacon transmission for adhoc mode when they are sent entirely | |
242 | * by the hardware using the self-linked descriptor + veol trick. | |
243 | */ | |
244 | ||
245 | static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id) | |
246 | { | |
247 | struct ath_hal *ah = sc->sc_ah; | |
248 | struct ath_buf *bf; | |
249 | struct ath_vap *avp; | |
250 | struct sk_buff *skb; | |
251 | ||
252 | avp = sc->sc_vaps[if_id]; | |
253 | ASSERT(avp); | |
254 | ||
255 | if (avp->av_bcbuf == NULL) { | |
256 | DPRINTF(sc, ATH_DBG_BEACON, "%s: avp=%p av_bcbuf=%p\n", | |
257 | __func__, avp, avp != NULL ? avp->av_bcbuf : NULL); | |
258 | return; | |
259 | } | |
260 | bf = avp->av_bcbuf; | |
261 | skb = (struct sk_buff *) bf->bf_mpdu; | |
262 | ||
263 | /* Construct tx descriptor. */ | |
264 | ath_beacon_setup(sc, avp, bf); | |
265 | ||
266 | /* NB: caller is known to have already stopped tx dma */ | |
267 | ath9k_hw_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); | |
268 | ath9k_hw_txstart(ah, sc->sc_bhalq); | |
269 | DPRINTF(sc, ATH_DBG_BEACON, "%s: TXDP%u = %llx (%p)\n", __func__, | |
270 | sc->sc_bhalq, ito64(bf->bf_daddr), bf->bf_desc); | |
271 | } | |
272 | ||
273 | /* | |
274 | * Setup a h/w transmit queue for beacons. | |
275 | * | |
276 | * This function allocates an information structure (struct ath9k_txq_info) | |
277 | * on the stack, sets some specific parameters (zero out channel width | |
278 | * min/max, and enable aifs). The info structure does not need to be | |
279 | * persistant. | |
280 | */ | |
281 | ||
282 | int ath_beaconq_setup(struct ath_hal *ah) | |
283 | { | |
ea9880fb | 284 | struct ath9k_tx_queue_info qi; |
f078f209 LR |
285 | |
286 | memzero(&qi, sizeof(qi)); | |
287 | qi.tqi_aifs = 1; | |
288 | qi.tqi_cwmin = 0; | |
289 | qi.tqi_cwmax = 0; | |
290 | /* NB: don't enable any interrupts */ | |
291 | return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi); | |
292 | } | |
293 | ||
294 | ||
295 | /* | |
296 | * Allocate and setup an initial beacon frame. | |
297 | * | |
298 | * Allocate a beacon state variable for a specific VAP instance created on | |
299 | * the ATH interface. This routine also calculates the beacon "slot" for | |
300 | * staggared beacons in the mBSSID case. | |
301 | */ | |
302 | ||
303 | int ath_beacon_alloc(struct ath_softc *sc, int if_id) | |
304 | { | |
305 | struct ath_vap *avp; | |
306 | struct ieee80211_hdr *wh; | |
307 | struct ath_buf *bf; | |
308 | struct sk_buff *skb; | |
309 | ||
310 | avp = sc->sc_vaps[if_id]; | |
311 | ASSERT(avp); | |
312 | ||
313 | /* Allocate a beacon descriptor if we haven't done so. */ | |
314 | if (!avp->av_bcbuf) { | |
315 | /* | |
316 | * Allocate beacon state for hostap/ibss. We know | |
317 | * a buffer is available. | |
318 | */ | |
319 | ||
320 | avp->av_bcbuf = list_first_entry(&sc->sc_bbuf, | |
321 | struct ath_buf, list); | |
322 | list_del(&avp->av_bcbuf->list); | |
323 | ||
b4696c8b | 324 | if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP || |
60b67f51 | 325 | !(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) { |
f078f209 LR |
326 | int slot; |
327 | /* | |
328 | * Assign the vap to a beacon xmit slot. As | |
329 | * above, this cannot fail to find one. | |
330 | */ | |
331 | avp->av_bslot = 0; | |
332 | for (slot = 0; slot < ATH_BCBUF; slot++) | |
333 | if (sc->sc_bslot[slot] == ATH_IF_ID_ANY) { | |
334 | /* | |
335 | * XXX hack, space out slots to better | |
336 | * deal with misses | |
337 | */ | |
338 | if (slot+1 < ATH_BCBUF && | |
339 | sc->sc_bslot[slot+1] == | |
340 | ATH_IF_ID_ANY) { | |
341 | avp->av_bslot = slot+1; | |
342 | break; | |
343 | } | |
344 | avp->av_bslot = slot; | |
345 | /* NB: keep looking for a double slot */ | |
346 | } | |
347 | BUG_ON(sc->sc_bslot[avp->av_bslot] != ATH_IF_ID_ANY); | |
348 | sc->sc_bslot[avp->av_bslot] = if_id; | |
349 | sc->sc_nbcnvaps++; | |
350 | } | |
351 | } | |
352 | ||
353 | /* release the previous beacon frame , if it already exists. */ | |
354 | bf = avp->av_bcbuf; | |
355 | if (bf->bf_mpdu != NULL) { | |
356 | skb = (struct sk_buff *)bf->bf_mpdu; | |
a8fff50e JM |
357 | pci_unmap_single(sc->pdev, bf->bf_dmacontext, |
358 | skb_end_pointer(skb) - skb->head, | |
359 | PCI_DMA_TODEVICE); | |
f078f209 LR |
360 | dev_kfree_skb_any(skb); |
361 | bf->bf_mpdu = NULL; | |
362 | } | |
363 | ||
364 | /* | |
365 | * NB: the beacon data buffer must be 32-bit aligned; | |
366 | * we assume the wbuf routines will return us something | |
367 | * with this alignment (perhaps should assert). | |
e022edbd | 368 | * FIXME: Fill avp->av_btxctl.txpower and |
f078f209 LR |
369 | * avp->av_btxctl.shortPreamble |
370 | */ | |
371 | skb = ieee80211_beacon_get(sc->hw, avp->av_if_data); | |
372 | if (skb == NULL) { | |
373 | DPRINTF(sc, ATH_DBG_BEACON, "%s: cannot get skb\n", | |
374 | __func__); | |
375 | return -ENOMEM; | |
376 | } | |
377 | ||
378 | /* | |
379 | * Calculate a TSF adjustment factor required for | |
380 | * staggered beacons. Note that we assume the format | |
381 | * of the beacon frame leaves the tstamp field immediately | |
382 | * following the header. | |
383 | */ | |
384 | if (avp->av_bslot > 0) { | |
385 | u64 tsfadjust; | |
386 | __le64 val; | |
387 | int intval; | |
388 | ||
a8fff50e JM |
389 | intval = sc->hw->conf.beacon_int ? |
390 | sc->hw->conf.beacon_int : ATH_DEFAULT_BINTVAL; | |
f078f209 LR |
391 | |
392 | /* | |
393 | * The beacon interval is in TU's; the TSF in usecs. | |
394 | * We figure out how many TU's to add to align the | |
395 | * timestamp then convert to TSF units and handle | |
396 | * byte swapping before writing it in the frame. | |
397 | * The hardware will then add this each time a beacon | |
398 | * frame is sent. Note that we align vap's 1..N | |
399 | * and leave vap 0 untouched. This means vap 0 | |
400 | * has a timestamp in one beacon interval while the | |
401 | * others get a timestamp aligned to the next interval. | |
402 | */ | |
403 | tsfadjust = (intval * (ATH_BCBUF - avp->av_bslot)) / ATH_BCBUF; | |
404 | val = cpu_to_le64(tsfadjust << 10); /* TU->TSF */ | |
405 | ||
406 | DPRINTF(sc, ATH_DBG_BEACON, | |
407 | "%s: %s beacons, bslot %d intval %u tsfadjust %llu\n", | |
408 | __func__, "stagger", | |
409 | avp->av_bslot, intval, (unsigned long long)tsfadjust); | |
410 | ||
411 | wh = (struct ieee80211_hdr *)skb->data; | |
412 | memcpy(&wh[1], &val, sizeof(val)); | |
413 | } | |
414 | ||
a8fff50e JM |
415 | bf->bf_buf_addr = bf->bf_dmacontext = |
416 | pci_map_single(sc->pdev, skb->data, | |
417 | skb_end_pointer(skb) - skb->head, | |
418 | PCI_DMA_TODEVICE); | |
f078f209 LR |
419 | bf->bf_mpdu = skb; |
420 | ||
421 | return 0; | |
422 | } | |
423 | ||
424 | /* | |
425 | * Reclaim beacon resources and return buffer to the pool. | |
426 | * | |
427 | * Checks the VAP to put the beacon frame buffer back to the ATH object | |
428 | * queue, and de-allocates any wbuf frames that were sent as CAB traffic. | |
429 | */ | |
430 | ||
431 | void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp) | |
432 | { | |
433 | if (avp->av_bcbuf != NULL) { | |
434 | struct ath_buf *bf; | |
435 | ||
436 | if (avp->av_bslot != -1) { | |
437 | sc->sc_bslot[avp->av_bslot] = ATH_IF_ID_ANY; | |
438 | sc->sc_nbcnvaps--; | |
439 | } | |
440 | ||
441 | bf = avp->av_bcbuf; | |
442 | if (bf->bf_mpdu != NULL) { | |
443 | struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu; | |
a8fff50e JM |
444 | pci_unmap_single(sc->pdev, bf->bf_dmacontext, |
445 | skb_end_pointer(skb) - skb->head, | |
446 | PCI_DMA_TODEVICE); | |
f078f209 LR |
447 | dev_kfree_skb_any(skb); |
448 | bf->bf_mpdu = NULL; | |
449 | } | |
450 | list_add_tail(&bf->list, &sc->sc_bbuf); | |
451 | ||
452 | avp->av_bcbuf = NULL; | |
453 | } | |
454 | } | |
455 | ||
456 | /* | |
457 | * Reclaim beacon resources and return buffer to the pool. | |
458 | * | |
459 | * This function will free any wbuf frames that are still attached to the | |
460 | * beacon buffers in the ATH object. Note that this does not de-allocate | |
461 | * any wbuf objects that are in the transmit queue and have not yet returned | |
462 | * to the ATH object. | |
463 | */ | |
464 | ||
465 | void ath_beacon_free(struct ath_softc *sc) | |
466 | { | |
467 | struct ath_buf *bf; | |
468 | ||
469 | list_for_each_entry(bf, &sc->sc_bbuf, list) { | |
470 | if (bf->bf_mpdu != NULL) { | |
471 | struct sk_buff *skb = (struct sk_buff *) bf->bf_mpdu; | |
a8fff50e JM |
472 | pci_unmap_single(sc->pdev, bf->bf_dmacontext, |
473 | skb_end_pointer(skb) - skb->head, | |
474 | PCI_DMA_TODEVICE); | |
f078f209 LR |
475 | dev_kfree_skb_any(skb); |
476 | bf->bf_mpdu = NULL; | |
477 | } | |
478 | } | |
479 | } | |
480 | ||
481 | /* | |
482 | * Tasklet for Sending Beacons | |
483 | * | |
484 | * Transmit one or more beacon frames at SWBA. Dynamic updates to the frame | |
485 | * contents are done as needed and the slot time is also adjusted based on | |
486 | * current state. | |
487 | * | |
488 | * This tasklet is not scheduled, it's called in ISR context. | |
489 | */ | |
490 | ||
491 | void ath9k_beacon_tasklet(unsigned long data) | |
492 | { | |
f078f209 LR |
493 | struct ath_softc *sc = (struct ath_softc *)data; |
494 | struct ath_hal *ah = sc->sc_ah; | |
495 | struct ath_buf *bf = NULL; | |
496 | int slot, if_id; | |
497 | u32 bfaddr; | |
498 | u32 rx_clear = 0, rx_frame = 0, tx_frame = 0; | |
499 | u32 show_cycles = 0; | |
500 | u32 bc = 0; /* beacon count */ | |
501 | u64 tsf; | |
502 | u32 tsftu; | |
503 | u16 intval; | |
504 | ||
98deeea0 | 505 | if (sc->sc_flags & SC_OP_NO_RESET) { |
f078f209 LR |
506 | show_cycles = ath9k_hw_GetMibCycleCountsPct(ah, |
507 | &rx_clear, | |
508 | &rx_frame, | |
509 | &tx_frame); | |
510 | } | |
511 | ||
512 | /* | |
513 | * Check if the previous beacon has gone out. If | |
514 | * not don't try to post another, skip this period | |
515 | * and wait for the next. Missed beacons indicate | |
516 | * a problem and should not occur. If we miss too | |
517 | * many consecutive beacons reset the device. | |
518 | */ | |
519 | if (ath9k_hw_numtxpending(ah, sc->sc_bhalq) != 0) { | |
520 | sc->sc_bmisscount++; | |
521 | /* XXX: doth needs the chanchange IE countdown decremented. | |
522 | * We should consider adding a mac80211 call to indicate | |
523 | * a beacon miss so appropriate action could be taken | |
524 | * (in that layer). | |
525 | */ | |
526 | if (sc->sc_bmisscount < BSTUCK_THRESH) { | |
98deeea0 | 527 | if (sc->sc_flags & SC_OP_NO_RESET) { |
f078f209 LR |
528 | DPRINTF(sc, ATH_DBG_BEACON, |
529 | "%s: missed %u consecutive beacons\n", | |
530 | __func__, sc->sc_bmisscount); | |
531 | if (show_cycles) { | |
532 | /* | |
533 | * Display cycle counter stats | |
534 | * from HW to aide in debug of | |
535 | * stickiness. | |
536 | */ | |
537 | DPRINTF(sc, | |
538 | ATH_DBG_BEACON, | |
539 | "%s: busy times: rx_clear=%d, " | |
540 | "rx_frame=%d, tx_frame=%d\n", | |
541 | __func__, rx_clear, rx_frame, | |
542 | tx_frame); | |
543 | } else { | |
544 | DPRINTF(sc, | |
545 | ATH_DBG_BEACON, | |
546 | "%s: unable to obtain " | |
547 | "busy times\n", __func__); | |
548 | } | |
549 | } else { | |
550 | DPRINTF(sc, ATH_DBG_BEACON, | |
551 | "%s: missed %u consecutive beacons\n", | |
552 | __func__, sc->sc_bmisscount); | |
553 | } | |
554 | } else if (sc->sc_bmisscount >= BSTUCK_THRESH) { | |
98deeea0 | 555 | if (sc->sc_flags & SC_OP_NO_RESET) { |
f078f209 LR |
556 | if (sc->sc_bmisscount == BSTUCK_THRESH) { |
557 | DPRINTF(sc, | |
558 | ATH_DBG_BEACON, | |
559 | "%s: beacon is officially " | |
560 | "stuck\n", __func__); | |
561 | ath9k_hw_dmaRegDump(ah); | |
562 | } | |
563 | } else { | |
564 | DPRINTF(sc, ATH_DBG_BEACON, | |
565 | "%s: beacon is officially stuck\n", | |
566 | __func__); | |
567 | ath_bstuck_process(sc); | |
568 | } | |
569 | } | |
570 | ||
571 | return; | |
572 | } | |
573 | if (sc->sc_bmisscount != 0) { | |
98deeea0 | 574 | if (sc->sc_flags & SC_OP_NO_RESET) { |
f078f209 LR |
575 | DPRINTF(sc, |
576 | ATH_DBG_BEACON, | |
577 | "%s: resume beacon xmit after %u misses\n", | |
578 | __func__, sc->sc_bmisscount); | |
579 | } else { | |
580 | DPRINTF(sc, ATH_DBG_BEACON, | |
581 | "%s: resume beacon xmit after %u misses\n", | |
582 | __func__, sc->sc_bmisscount); | |
583 | } | |
584 | sc->sc_bmisscount = 0; | |
585 | } | |
586 | ||
587 | /* | |
588 | * Generate beacon frames. we are sending frames | |
589 | * staggered so calculate the slot for this frame based | |
590 | * on the tsf to safeguard against missing an swba. | |
591 | */ | |
592 | ||
a8fff50e JM |
593 | intval = sc->hw->conf.beacon_int ? |
594 | sc->hw->conf.beacon_int : ATH_DEFAULT_BINTVAL; | |
f078f209 LR |
595 | |
596 | tsf = ath9k_hw_gettsf64(ah); | |
597 | tsftu = TSF_TO_TU(tsf>>32, tsf); | |
598 | slot = ((tsftu % intval) * ATH_BCBUF) / intval; | |
599 | if_id = sc->sc_bslot[(slot + 1) % ATH_BCBUF]; | |
600 | DPRINTF(sc, ATH_DBG_BEACON, | |
601 | "%s: slot %d [tsf %llu tsftu %u intval %u] if_id %d\n", | |
602 | __func__, slot, (unsigned long long) tsf, tsftu, | |
603 | intval, if_id); | |
604 | bfaddr = 0; | |
605 | if (if_id != ATH_IF_ID_ANY) { | |
606 | bf = ath_beacon_generate(sc, if_id); | |
607 | if (bf != NULL) { | |
608 | bfaddr = bf->bf_daddr; | |
609 | bc = 1; | |
610 | } | |
611 | } | |
612 | /* | |
613 | * Handle slot time change when a non-ERP station joins/leaves | |
614 | * an 11g network. The 802.11 layer notifies us via callback, | |
615 | * we mark updateslot, then wait one beacon before effecting | |
616 | * the change. This gives associated stations at least one | |
617 | * beacon interval to note the state change. | |
618 | * | |
619 | * NB: The slot time change state machine is clocked according | |
620 | * to whether we are bursting or staggering beacons. We | |
621 | * recognize the request to update and record the current | |
622 | * slot then don't transition until that slot is reached | |
623 | * again. If we miss a beacon for that slot then we'll be | |
624 | * slow to transition but we'll be sure at least one beacon | |
625 | * interval has passed. When bursting slot is always left | |
626 | * set to ATH_BCBUF so this check is a noop. | |
627 | */ | |
628 | /* XXX locking */ | |
629 | if (sc->sc_updateslot == UPDATE) { | |
630 | sc->sc_updateslot = COMMIT; /* commit next beacon */ | |
631 | sc->sc_slotupdate = slot; | |
632 | } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot) | |
633 | ath_setslottime(sc); /* commit change to hardware */ | |
634 | ||
635 | if (bfaddr != 0) { | |
636 | /* | |
637 | * Stop any current dma and put the new frame(s) on the queue. | |
638 | * This should never fail since we check above that no frames | |
639 | * are still pending on the queue. | |
640 | */ | |
641 | if (!ath9k_hw_stoptxdma(ah, sc->sc_bhalq)) { | |
642 | DPRINTF(sc, ATH_DBG_FATAL, | |
643 | "%s: beacon queue %u did not stop?\n", | |
644 | __func__, sc->sc_bhalq); | |
645 | /* NB: the HAL still stops DMA, so proceed */ | |
646 | } | |
647 | ||
648 | /* NB: cabq traffic should already be queued and primed */ | |
649 | ath9k_hw_puttxbuf(ah, sc->sc_bhalq, bfaddr); | |
650 | ath9k_hw_txstart(ah, sc->sc_bhalq); | |
651 | ||
652 | sc->ast_be_xmit += bc; /* XXX per-vap? */ | |
653 | } | |
f078f209 LR |
654 | } |
655 | ||
656 | /* | |
657 | * Tasklet for Beacon Stuck processing | |
658 | * | |
659 | * Processing for Beacon Stuck. | |
660 | * Basically calls the ath_internal_reset function to reset the chip. | |
661 | */ | |
662 | ||
663 | void ath_bstuck_process(struct ath_softc *sc) | |
664 | { | |
665 | DPRINTF(sc, ATH_DBG_BEACON, | |
666 | "%s: stuck beacon; resetting (bmiss count %u)\n", | |
667 | __func__, sc->sc_bmisscount); | |
f45144ef | 668 | ath_reset(sc, false); |
f078f209 LR |
669 | } |
670 | ||
671 | /* | |
672 | * Configure the beacon and sleep timers. | |
673 | * | |
674 | * When operating as an AP this resets the TSF and sets | |
675 | * up the hardware to notify us when we need to issue beacons. | |
676 | * | |
677 | * When operating in station mode this sets up the beacon | |
678 | * timers according to the timestamp of the last received | |
679 | * beacon and the current TSF, configures PCF and DTIM | |
680 | * handling, programs the sleep registers so the hardware | |
681 | * will wakeup in time to receive beacons, and configures | |
682 | * the beacon miss handling so we'll receive a BMISS | |
683 | * interrupt when we stop seeing beacons from the AP | |
684 | * we've associated with. | |
685 | */ | |
686 | ||
687 | void ath_beacon_config(struct ath_softc *sc, int if_id) | |
688 | { | |
f078f209 LR |
689 | struct ath_hal *ah = sc->sc_ah; |
690 | u32 nexttbtt, intval; | |
691 | struct ath_beacon_config conf; | |
692 | enum ath9k_opmode av_opmode; | |
693 | ||
694 | if (if_id != ATH_IF_ID_ANY) | |
695 | av_opmode = sc->sc_vaps[if_id]->av_opmode; | |
696 | else | |
b4696c8b | 697 | av_opmode = sc->sc_ah->ah_opmode; |
f078f209 LR |
698 | |
699 | memzero(&conf, sizeof(struct ath_beacon_config)); | |
700 | ||
701 | /* FIXME: Use default values for now - Sujith */ | |
702 | /* Query beacon configuration first */ | |
703 | /* | |
704 | * Protocol stack doesn't support dynamic beacon configuration, | |
705 | * use default configurations. | |
706 | */ | |
a8fff50e JM |
707 | conf.beacon_interval = sc->hw->conf.beacon_int ? |
708 | sc->hw->conf.beacon_int : ATH_DEFAULT_BINTVAL; | |
f078f209 LR |
709 | conf.listen_interval = 1; |
710 | conf.dtim_period = conf.beacon_interval; | |
711 | conf.dtim_count = 1; | |
712 | conf.bmiss_timeout = ATH_DEFAULT_BMISS_LIMIT * conf.beacon_interval; | |
713 | ||
714 | /* extract tstamp from last beacon and convert to TU */ | |
715 | nexttbtt = TSF_TO_TU(get_unaligned_le32(conf.u.last_tstamp + 4), | |
716 | get_unaligned_le32(conf.u.last_tstamp)); | |
717 | /* XXX conditionalize multi-bss support? */ | |
b4696c8b | 718 | if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP) { |
f078f209 LR |
719 | /* |
720 | * For multi-bss ap support beacons are either staggered | |
721 | * evenly over N slots or burst together. For the former | |
722 | * arrange for the SWBA to be delivered for each slot. | |
723 | * Slots that are not occupied will generate nothing. | |
724 | */ | |
725 | /* NB: the beacon interval is kept internally in TU's */ | |
726 | intval = conf.beacon_interval & ATH9K_BEACON_PERIOD; | |
727 | intval /= ATH_BCBUF; /* for staggered beacons */ | |
728 | } else { | |
729 | intval = conf.beacon_interval & ATH9K_BEACON_PERIOD; | |
730 | } | |
731 | ||
732 | if (nexttbtt == 0) /* e.g. for ap mode */ | |
733 | nexttbtt = intval; | |
734 | else if (intval) /* NB: can be 0 for monitor mode */ | |
735 | nexttbtt = roundup(nexttbtt, intval); | |
736 | DPRINTF(sc, ATH_DBG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", | |
737 | __func__, nexttbtt, intval, conf.beacon_interval); | |
738 | /* Check for ATH9K_M_HOSTAP and sc_nostabeacons for WDS client */ | |
b4696c8b | 739 | if (sc->sc_ah->ah_opmode == ATH9K_M_STA) { |
f078f209 LR |
740 | struct ath9k_beacon_state bs; |
741 | u64 tsf; | |
742 | u32 tsftu; | |
743 | int dtimperiod, dtimcount, sleepduration; | |
744 | int cfpperiod, cfpcount; | |
745 | ||
746 | /* | |
747 | * Setup dtim and cfp parameters according to | |
748 | * last beacon we received (which may be none). | |
749 | */ | |
750 | dtimperiod = conf.dtim_period; | |
751 | if (dtimperiod <= 0) /* NB: 0 if not known */ | |
752 | dtimperiod = 1; | |
753 | dtimcount = conf.dtim_count; | |
754 | if (dtimcount >= dtimperiod) /* NB: sanity check */ | |
755 | dtimcount = 0; /* XXX? */ | |
756 | cfpperiod = 1; /* NB: no PCF support yet */ | |
757 | cfpcount = 0; | |
758 | ||
759 | sleepduration = conf.listen_interval * intval; | |
760 | if (sleepduration <= 0) | |
761 | sleepduration = intval; | |
762 | ||
763 | #define FUDGE 2 | |
764 | /* | |
765 | * Pull nexttbtt forward to reflect the current | |
766 | * TSF and calculate dtim+cfp state for the result. | |
767 | */ | |
768 | tsf = ath9k_hw_gettsf64(ah); | |
769 | tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; | |
770 | do { | |
771 | nexttbtt += intval; | |
772 | if (--dtimcount < 0) { | |
773 | dtimcount = dtimperiod - 1; | |
774 | if (--cfpcount < 0) | |
775 | cfpcount = cfpperiod - 1; | |
776 | } | |
777 | } while (nexttbtt < tsftu); | |
778 | #undef FUDGE | |
779 | memzero(&bs, sizeof(bs)); | |
780 | bs.bs_intval = intval; | |
781 | bs.bs_nexttbtt = nexttbtt; | |
782 | bs.bs_dtimperiod = dtimperiod*intval; | |
783 | bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; | |
784 | bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; | |
785 | bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; | |
786 | bs.bs_cfpmaxduration = 0; | |
787 | /* | |
788 | * Calculate the number of consecutive beacons to miss | |
789 | * before taking a BMISS interrupt. The configuration | |
790 | * is specified in TU so we only need calculate based | |
791 | * on the beacon interval. Note that we clamp the | |
792 | * result to at most 15 beacons. | |
793 | */ | |
794 | if (sleepduration > intval) { | |
795 | bs.bs_bmissthreshold = | |
796 | conf.listen_interval * | |
797 | ATH_DEFAULT_BMISS_LIMIT / 2; | |
798 | } else { | |
799 | bs.bs_bmissthreshold = | |
800 | DIV_ROUND_UP(conf.bmiss_timeout, intval); | |
801 | if (bs.bs_bmissthreshold > 15) | |
802 | bs.bs_bmissthreshold = 15; | |
803 | else if (bs.bs_bmissthreshold <= 0) | |
804 | bs.bs_bmissthreshold = 1; | |
805 | } | |
806 | ||
807 | /* | |
808 | * Calculate sleep duration. The configuration is | |
809 | * given in ms. We insure a multiple of the beacon | |
810 | * period is used. Also, if the sleep duration is | |
811 | * greater than the DTIM period then it makes senses | |
812 | * to make it a multiple of that. | |
813 | * | |
814 | * XXX fixed at 100ms | |
815 | */ | |
816 | ||
817 | bs.bs_sleepduration = | |
818 | roundup(IEEE80211_MS_TO_TU(100), sleepduration); | |
819 | if (bs.bs_sleepduration > bs.bs_dtimperiod) | |
820 | bs.bs_sleepduration = bs.bs_dtimperiod; | |
821 | ||
822 | DPRINTF(sc, ATH_DBG_BEACON, | |
823 | "%s: tsf %llu " | |
824 | "tsf:tu %u " | |
825 | "intval %u " | |
826 | "nexttbtt %u " | |
827 | "dtim %u " | |
828 | "nextdtim %u " | |
829 | "bmiss %u " | |
830 | "sleep %u " | |
831 | "cfp:period %u " | |
832 | "maxdur %u " | |
833 | "next %u " | |
ff9b662d S |
834 | "timoffset %u\n", |
835 | __func__, | |
836 | (unsigned long long)tsf, tsftu, | |
837 | bs.bs_intval, | |
838 | bs.bs_nexttbtt, | |
839 | bs.bs_dtimperiod, | |
840 | bs.bs_nextdtim, | |
841 | bs.bs_bmissthreshold, | |
842 | bs.bs_sleepduration, | |
843 | bs.bs_cfpperiod, | |
844 | bs.bs_cfpmaxduration, | |
845 | bs.bs_cfpnext, | |
846 | bs.bs_timoffset | |
f078f209 LR |
847 | ); |
848 | ||
849 | ath9k_hw_set_interrupts(ah, 0); | |
850 | ath9k_hw_set_sta_beacon_timers(ah, &bs); | |
851 | sc->sc_imask |= ATH9K_INT_BMISS; | |
852 | ath9k_hw_set_interrupts(ah, sc->sc_imask); | |
853 | } else { | |
854 | u64 tsf; | |
855 | u32 tsftu; | |
856 | ath9k_hw_set_interrupts(ah, 0); | |
857 | if (nexttbtt == intval) | |
858 | intval |= ATH9K_BEACON_RESET_TSF; | |
b4696c8b | 859 | if (sc->sc_ah->ah_opmode == ATH9K_M_IBSS) { |
f078f209 LR |
860 | /* |
861 | * Pull nexttbtt forward to reflect the current | |
862 | * TSF . | |
863 | */ | |
864 | #define FUDGE 2 | |
865 | if (!(intval & ATH9K_BEACON_RESET_TSF)) { | |
866 | tsf = ath9k_hw_gettsf64(ah); | |
867 | tsftu = TSF_TO_TU((u32)(tsf>>32), | |
868 | (u32)tsf) + FUDGE; | |
869 | do { | |
870 | nexttbtt += intval; | |
871 | } while (nexttbtt < tsftu); | |
872 | } | |
873 | #undef FUDGE | |
874 | DPRINTF(sc, ATH_DBG_BEACON, | |
875 | "%s: IBSS nexttbtt %u intval %u (%u)\n", | |
876 | __func__, nexttbtt, | |
877 | intval & ~ATH9K_BEACON_RESET_TSF, | |
878 | conf.beacon_interval); | |
879 | ||
880 | /* | |
881 | * In IBSS mode enable the beacon timers but only | |
882 | * enable SWBA interrupts if we need to manually | |
883 | * prepare beacon frames. Otherwise we use a | |
884 | * self-linked tx descriptor and let the hardware | |
885 | * deal with things. | |
886 | */ | |
887 | intval |= ATH9K_BEACON_ENA; | |
60b67f51 | 888 | if (!(ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) |
f078f209 LR |
889 | sc->sc_imask |= ATH9K_INT_SWBA; |
890 | ath_beaconq_config(sc); | |
b4696c8b | 891 | } else if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP) { |
f078f209 LR |
892 | /* |
893 | * In AP mode we enable the beacon timers and | |
894 | * SWBA interrupts to prepare beacon frames. | |
895 | */ | |
896 | intval |= ATH9K_BEACON_ENA; | |
897 | sc->sc_imask |= ATH9K_INT_SWBA; /* beacon prepare */ | |
898 | ath_beaconq_config(sc); | |
899 | } | |
900 | ath9k_hw_beaconinit(ah, nexttbtt, intval); | |
901 | sc->sc_bmisscount = 0; | |
902 | ath9k_hw_set_interrupts(ah, sc->sc_imask); | |
903 | /* | |
904 | * When using a self-linked beacon descriptor in | |
905 | * ibss mode load it once here. | |
906 | */ | |
b4696c8b | 907 | if (sc->sc_ah->ah_opmode == ATH9K_M_IBSS && |
60b67f51 | 908 | (ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) |
f078f209 LR |
909 | ath_beacon_start_adhoc(sc, 0); |
910 | } | |
f078f209 LR |
911 | } |
912 | ||
913 | /* Function to collect beacon rssi data and resync beacon if necessary */ | |
914 | ||
915 | void ath_beacon_sync(struct ath_softc *sc, int if_id) | |
916 | { | |
917 | /* | |
918 | * Resync beacon timers using the tsf of the | |
919 | * beacon frame we just received. | |
920 | */ | |
921 | ath_beacon_config(sc, if_id); | |
672840ac | 922 | sc->sc_flags |= SC_OP_BEACONS; |
f078f209 | 923 | } |