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f1dc5600 S |
1 | /* |
2 | * Copyright (c) 2008 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include "core.h" | |
18 | #include "hw.h" | |
19 | #include "reg.h" | |
20 | #include "phy.h" | |
21 | ||
f1dc5600 S |
22 | /* We can tune this as we go by monitoring really low values */ |
23 | #define ATH9K_NF_TOO_LOW -60 | |
24 | ||
25 | /* AR5416 may return very high value (like -31 dBm), in those cases the nf | |
26 | * is incorrect and we should use the static NF value. Later we can try to | |
27 | * find out why they are reporting these values */ | |
28 | ||
29 | static bool ath9k_hw_nf_in_range(struct ath_hal *ah, s16 nf) | |
30 | { | |
31 | if (nf > ATH9K_NF_TOO_LOW) { | |
04bd4638 S |
32 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
33 | "noise floor value detected (%d) is " | |
f1dc5600 S |
34 | "lower than what we think is a " |
35 | "reasonable value (%d)\n", | |
04bd4638 | 36 | nf, ATH9K_NF_TOO_LOW); |
f1dc5600 S |
37 | return false; |
38 | } | |
39 | return true; | |
40 | } | |
41 | ||
42 | static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer) | |
43 | { | |
44 | int16_t nfval; | |
45 | int16_t sort[ATH9K_NF_CAL_HIST_MAX]; | |
46 | int i, j; | |
47 | ||
48 | for (i = 0; i < ATH9K_NF_CAL_HIST_MAX; i++) | |
49 | sort[i] = nfCalBuffer[i]; | |
50 | ||
51 | for (i = 0; i < ATH9K_NF_CAL_HIST_MAX - 1; i++) { | |
52 | for (j = 1; j < ATH9K_NF_CAL_HIST_MAX - i; j++) { | |
53 | if (sort[j] > sort[j - 1]) { | |
54 | nfval = sort[j]; | |
55 | sort[j] = sort[j - 1]; | |
56 | sort[j - 1] = nfval; | |
57 | } | |
58 | } | |
59 | } | |
60 | nfval = sort[(ATH9K_NF_CAL_HIST_MAX - 1) >> 1]; | |
61 | ||
62 | return nfval; | |
63 | } | |
64 | ||
65 | static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h, | |
66 | int16_t *nfarray) | |
67 | { | |
68 | int i; | |
69 | ||
70 | for (i = 0; i < NUM_NF_READINGS; i++) { | |
71 | h[i].nfCalBuffer[h[i].currIndex] = nfarray[i]; | |
72 | ||
73 | if (++h[i].currIndex >= ATH9K_NF_CAL_HIST_MAX) | |
74 | h[i].currIndex = 0; | |
75 | ||
76 | if (h[i].invalidNFcount > 0) { | |
77 | if (nfarray[i] < AR_PHY_CCA_MIN_BAD_VALUE || | |
78 | nfarray[i] > AR_PHY_CCA_MAX_HIGH_VALUE) { | |
79 | h[i].invalidNFcount = ATH9K_NF_CAL_HIST_MAX; | |
80 | } else { | |
81 | h[i].invalidNFcount--; | |
82 | h[i].privNF = nfarray[i]; | |
83 | } | |
84 | } else { | |
85 | h[i].privNF = | |
86 | ath9k_hw_get_nf_hist_mid(h[i].nfCalBuffer); | |
87 | } | |
88 | } | |
89 | return; | |
90 | } | |
91 | ||
92 | static void ath9k_hw_do_getnf(struct ath_hal *ah, | |
93 | int16_t nfarray[NUM_NF_READINGS]) | |
94 | { | |
95 | int16_t nf; | |
96 | ||
97 | if (AR_SREV_9280_10_OR_LATER(ah)) | |
98 | nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR); | |
99 | else | |
100 | nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR); | |
101 | ||
102 | if (nf & 0x100) | |
103 | nf = 0 - ((nf ^ 0x1ff) + 1); | |
104 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
105 | "NF calibrated [ctl] [chain 0] is %d\n", nf); | |
106 | nfarray[0] = nf; | |
107 | ||
793c5929 SB |
108 | if (!AR_SREV_9285(ah)) { |
109 | if (AR_SREV_9280_10_OR_LATER(ah)) | |
110 | nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), | |
111 | AR9280_PHY_CH1_MINCCA_PWR); | |
112 | else | |
113 | nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), | |
114 | AR_PHY_CH1_MINCCA_PWR); | |
f1dc5600 | 115 | |
f1dc5600 S |
116 | if (nf & 0x100) |
117 | nf = 0 - ((nf ^ 0x1ff) + 1); | |
04bd4638 | 118 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
793c5929 SB |
119 | "NF calibrated [ctl] [chain 1] is %d\n", nf); |
120 | nfarray[1] = nf; | |
121 | ||
122 | if (!AR_SREV_9280(ah)) { | |
123 | nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), | |
124 | AR_PHY_CH2_MINCCA_PWR); | |
125 | if (nf & 0x100) | |
126 | nf = 0 - ((nf ^ 0x1ff) + 1); | |
127 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
128 | "NF calibrated [ctl] [chain 2] is %d\n", nf); | |
129 | nfarray[2] = nf; | |
130 | } | |
f1dc5600 S |
131 | } |
132 | ||
133 | if (AR_SREV_9280_10_OR_LATER(ah)) | |
134 | nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), | |
135 | AR9280_PHY_EXT_MINCCA_PWR); | |
136 | else | |
137 | nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), | |
138 | AR_PHY_EXT_MINCCA_PWR); | |
139 | ||
140 | if (nf & 0x100) | |
141 | nf = 0 - ((nf ^ 0x1ff) + 1); | |
04bd4638 | 142 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
f1dc5600 S |
143 | "NF calibrated [ext] [chain 0] is %d\n", nf); |
144 | nfarray[3] = nf; | |
145 | ||
793c5929 SB |
146 | if (!AR_SREV_9285(ah)) { |
147 | if (AR_SREV_9280_10_OR_LATER(ah)) | |
148 | nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), | |
149 | AR9280_PHY_CH1_EXT_MINCCA_PWR); | |
150 | else | |
151 | nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), | |
152 | AR_PHY_CH1_EXT_MINCCA_PWR); | |
f1dc5600 | 153 | |
f1dc5600 S |
154 | if (nf & 0x100) |
155 | nf = 0 - ((nf ^ 0x1ff) + 1); | |
04bd4638 | 156 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
793c5929 SB |
157 | "NF calibrated [ext] [chain 1] is %d\n", nf); |
158 | nfarray[4] = nf; | |
159 | ||
160 | if (!AR_SREV_9280(ah)) { | |
161 | nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), | |
162 | AR_PHY_CH2_EXT_MINCCA_PWR); | |
163 | if (nf & 0x100) | |
164 | nf = 0 - ((nf ^ 0x1ff) + 1); | |
165 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
166 | "NF calibrated [ext] [chain 2] is %d\n", nf); | |
167 | nfarray[5] = nf; | |
168 | } | |
f1dc5600 S |
169 | } |
170 | } | |
171 | ||
172 | static bool getNoiseFloorThresh(struct ath_hal *ah, | |
76061abb | 173 | enum ieee80211_band band, |
f1dc5600 S |
174 | int16_t *nft) |
175 | { | |
76061abb LR |
176 | switch (band) { |
177 | case IEEE80211_BAND_5GHZ: | |
f9bbf431 | 178 | *nft = (int8_t)ath9k_hw_get_eeprom(ah, EEP_NFTHRESH_5); |
f1dc5600 | 179 | break; |
76061abb | 180 | case IEEE80211_BAND_2GHZ: |
f9bbf431 | 181 | *nft = (int8_t)ath9k_hw_get_eeprom(ah, EEP_NFTHRESH_2); |
f1dc5600 S |
182 | break; |
183 | default: | |
76061abb | 184 | BUG_ON(1); |
f1dc5600 S |
185 | return false; |
186 | } | |
187 | ||
188 | return true; | |
189 | } | |
190 | ||
191 | static void ath9k_hw_setup_calibration(struct ath_hal *ah, | |
192 | struct hal_cal_list *currCal) | |
193 | { | |
194 | REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0), | |
195 | AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, | |
196 | currCal->calData->calCountMax); | |
197 | ||
198 | switch (currCal->calData->calType) { | |
199 | case IQ_MISMATCH_CAL: | |
200 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); | |
201 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
04bd4638 | 202 | "starting IQ Mismatch Calibration\n"); |
f1dc5600 S |
203 | break; |
204 | case ADC_GAIN_CAL: | |
205 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); | |
206 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
04bd4638 | 207 | "starting ADC Gain Calibration\n"); |
f1dc5600 S |
208 | break; |
209 | case ADC_DC_CAL: | |
210 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); | |
211 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
04bd4638 | 212 | "starting ADC DC Calibration\n"); |
f1dc5600 S |
213 | break; |
214 | case ADC_DC_INIT_CAL: | |
215 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT); | |
216 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
04bd4638 | 217 | "starting Init ADC DC Calibration\n"); |
f1dc5600 S |
218 | break; |
219 | } | |
220 | ||
221 | REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), | |
222 | AR_PHY_TIMING_CTRL4_DO_CAL); | |
223 | } | |
224 | ||
225 | static void ath9k_hw_reset_calibration(struct ath_hal *ah, | |
226 | struct hal_cal_list *currCal) | |
227 | { | |
228 | struct ath_hal_5416 *ahp = AH5416(ah); | |
229 | int i; | |
230 | ||
231 | ath9k_hw_setup_calibration(ah, currCal); | |
232 | ||
233 | currCal->calState = CAL_RUNNING; | |
234 | ||
235 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { | |
236 | ahp->ah_Meas0.sign[i] = 0; | |
237 | ahp->ah_Meas1.sign[i] = 0; | |
238 | ahp->ah_Meas2.sign[i] = 0; | |
239 | ahp->ah_Meas3.sign[i] = 0; | |
240 | } | |
241 | ||
242 | ahp->ah_CalSamples = 0; | |
243 | } | |
244 | ||
245 | static void ath9k_hw_per_calibration(struct ath_hal *ah, | |
246 | struct ath9k_channel *ichan, | |
247 | u8 rxchainmask, | |
248 | struct hal_cal_list *currCal, | |
249 | bool *isCalDone) | |
250 | { | |
251 | struct ath_hal_5416 *ahp = AH5416(ah); | |
252 | ||
253 | *isCalDone = false; | |
254 | ||
255 | if (currCal->calState == CAL_RUNNING) { | |
256 | if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) & | |
257 | AR_PHY_TIMING_CTRL4_DO_CAL)) { | |
258 | ||
259 | currCal->calData->calCollect(ah); | |
260 | ahp->ah_CalSamples++; | |
261 | ||
262 | if (ahp->ah_CalSamples >= currCal->calData->calNumSamples) { | |
263 | int i, numChains = 0; | |
264 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { | |
265 | if (rxchainmask & (1 << i)) | |
266 | numChains++; | |
267 | } | |
268 | ||
269 | currCal->calData->calPostProc(ah, numChains); | |
270 | ichan->CalValid |= currCal->calData->calType; | |
271 | currCal->calState = CAL_DONE; | |
272 | *isCalDone = true; | |
273 | } else { | |
274 | ath9k_hw_setup_calibration(ah, currCal); | |
275 | } | |
276 | } | |
277 | } else if (!(ichan->CalValid & currCal->calData->calType)) { | |
278 | ath9k_hw_reset_calibration(ah, currCal); | |
279 | } | |
280 | } | |
281 | ||
c9e27d94 | 282 | /* Assumes you are talking about the currently configured channel */ |
f1dc5600 | 283 | static bool ath9k_hw_iscal_supported(struct ath_hal *ah, |
f1dc5600 S |
284 | enum hal_cal_types calType) |
285 | { | |
286 | struct ath_hal_5416 *ahp = AH5416(ah); | |
c9e27d94 | 287 | struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; |
f1dc5600 S |
288 | |
289 | switch (calType & ahp->ah_suppCals) { | |
c9e27d94 LR |
290 | case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */ |
291 | return true; | |
f1dc5600 S |
292 | case ADC_GAIN_CAL: |
293 | case ADC_DC_CAL: | |
c9e27d94 LR |
294 | if (conf->channel->band == IEEE80211_BAND_5GHZ && |
295 | conf_is_ht20(conf)) | |
296 | return true; | |
f1dc5600 S |
297 | break; |
298 | } | |
c9e27d94 | 299 | return false; |
f1dc5600 S |
300 | } |
301 | ||
302 | static void ath9k_hw_iqcal_collect(struct ath_hal *ah) | |
303 | { | |
304 | struct ath_hal_5416 *ahp = AH5416(ah); | |
305 | int i; | |
306 | ||
307 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { | |
308 | ahp->ah_totalPowerMeasI[i] += | |
309 | REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); | |
310 | ahp->ah_totalPowerMeasQ[i] += | |
311 | REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); | |
312 | ahp->ah_totalIqCorrMeas[i] += | |
313 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); | |
314 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
315 | "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n", | |
316 | ahp->ah_CalSamples, i, ahp->ah_totalPowerMeasI[i], | |
317 | ahp->ah_totalPowerMeasQ[i], | |
318 | ahp->ah_totalIqCorrMeas[i]); | |
319 | } | |
320 | } | |
321 | ||
322 | static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah) | |
323 | { | |
324 | struct ath_hal_5416 *ahp = AH5416(ah); | |
325 | int i; | |
326 | ||
327 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { | |
328 | ahp->ah_totalAdcIOddPhase[i] += | |
329 | REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); | |
330 | ahp->ah_totalAdcIEvenPhase[i] += | |
331 | REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); | |
332 | ahp->ah_totalAdcQOddPhase[i] += | |
333 | REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); | |
334 | ahp->ah_totalAdcQEvenPhase[i] += | |
335 | REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); | |
336 | ||
337 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
338 | "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " | |
339 | "oddq=0x%08x; evenq=0x%08x;\n", | |
340 | ahp->ah_CalSamples, i, | |
341 | ahp->ah_totalAdcIOddPhase[i], | |
342 | ahp->ah_totalAdcIEvenPhase[i], | |
343 | ahp->ah_totalAdcQOddPhase[i], | |
344 | ahp->ah_totalAdcQEvenPhase[i]); | |
345 | } | |
346 | } | |
347 | ||
348 | static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah) | |
349 | { | |
350 | struct ath_hal_5416 *ahp = AH5416(ah); | |
351 | int i; | |
352 | ||
353 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { | |
354 | ahp->ah_totalAdcDcOffsetIOddPhase[i] += | |
355 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); | |
356 | ahp->ah_totalAdcDcOffsetIEvenPhase[i] += | |
357 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); | |
358 | ahp->ah_totalAdcDcOffsetQOddPhase[i] += | |
359 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); | |
360 | ahp->ah_totalAdcDcOffsetQEvenPhase[i] += | |
361 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); | |
362 | ||
363 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
364 | "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " | |
365 | "oddq=0x%08x; evenq=0x%08x;\n", | |
366 | ahp->ah_CalSamples, i, | |
367 | ahp->ah_totalAdcDcOffsetIOddPhase[i], | |
368 | ahp->ah_totalAdcDcOffsetIEvenPhase[i], | |
369 | ahp->ah_totalAdcDcOffsetQOddPhase[i], | |
370 | ahp->ah_totalAdcDcOffsetQEvenPhase[i]); | |
371 | } | |
372 | } | |
373 | ||
374 | static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains) | |
375 | { | |
376 | struct ath_hal_5416 *ahp = AH5416(ah); | |
377 | u32 powerMeasQ, powerMeasI, iqCorrMeas; | |
378 | u32 qCoffDenom, iCoffDenom; | |
379 | int32_t qCoff, iCoff; | |
380 | int iqCorrNeg, i; | |
381 | ||
382 | for (i = 0; i < numChains; i++) { | |
383 | powerMeasI = ahp->ah_totalPowerMeasI[i]; | |
384 | powerMeasQ = ahp->ah_totalPowerMeasQ[i]; | |
385 | iqCorrMeas = ahp->ah_totalIqCorrMeas[i]; | |
386 | ||
387 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
388 | "Starting IQ Cal and Correction for Chain %d\n", | |
389 | i); | |
390 | ||
391 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
392 | "Orignal: Chn %diq_corr_meas = 0x%08x\n", | |
393 | i, ahp->ah_totalIqCorrMeas[i]); | |
394 | ||
395 | iqCorrNeg = 0; | |
396 | ||
397 | if (iqCorrMeas > 0x80000000) { | |
398 | iqCorrMeas = (0xffffffff - iqCorrMeas) + 1; | |
399 | iqCorrNeg = 1; | |
400 | } | |
401 | ||
402 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
403 | "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI); | |
404 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
405 | "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ); | |
406 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n", | |
407 | iqCorrNeg); | |
408 | ||
409 | iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128; | |
410 | qCoffDenom = powerMeasQ / 64; | |
411 | ||
412 | if (powerMeasQ != 0) { | |
413 | iCoff = iqCorrMeas / iCoffDenom; | |
414 | qCoff = powerMeasI / qCoffDenom - 64; | |
415 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
416 | "Chn %d iCoff = 0x%08x\n", i, iCoff); | |
417 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
418 | "Chn %d qCoff = 0x%08x\n", i, qCoff); | |
419 | ||
420 | iCoff = iCoff & 0x3f; | |
421 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
422 | "New: Chn %d iCoff = 0x%08x\n", i, iCoff); | |
423 | if (iqCorrNeg == 0x0) | |
424 | iCoff = 0x40 - iCoff; | |
425 | ||
426 | if (qCoff > 15) | |
427 | qCoff = 15; | |
428 | else if (qCoff <= -16) | |
429 | qCoff = 16; | |
430 | ||
431 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
432 | "Chn %d : iCoff = 0x%x qCoff = 0x%x\n", | |
433 | i, iCoff, qCoff); | |
434 | ||
435 | REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), | |
436 | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, | |
437 | iCoff); | |
438 | REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), | |
439 | AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, | |
440 | qCoff); | |
441 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
442 | "IQ Cal and Correction done for Chain %d\n", | |
443 | i); | |
444 | } | |
445 | } | |
446 | ||
447 | REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), | |
448 | AR_PHY_TIMING_CTRL4_IQCORR_ENABLE); | |
449 | } | |
450 | ||
451 | static void ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, u8 numChains) | |
452 | { | |
453 | struct ath_hal_5416 *ahp = AH5416(ah); | |
454 | u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset; | |
455 | u32 qGainMismatch, iGainMismatch, val, i; | |
456 | ||
457 | for (i = 0; i < numChains; i++) { | |
458 | iOddMeasOffset = ahp->ah_totalAdcIOddPhase[i]; | |
459 | iEvenMeasOffset = ahp->ah_totalAdcIEvenPhase[i]; | |
460 | qOddMeasOffset = ahp->ah_totalAdcQOddPhase[i]; | |
461 | qEvenMeasOffset = ahp->ah_totalAdcQEvenPhase[i]; | |
462 | ||
463 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
464 | "Starting ADC Gain Cal for Chain %d\n", i); | |
465 | ||
466 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
467 | "Chn %d pwr_meas_odd_i = 0x%08x\n", i, | |
468 | iOddMeasOffset); | |
469 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
470 | "Chn %d pwr_meas_even_i = 0x%08x\n", i, | |
471 | iEvenMeasOffset); | |
472 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
473 | "Chn %d pwr_meas_odd_q = 0x%08x\n", i, | |
474 | qOddMeasOffset); | |
475 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
476 | "Chn %d pwr_meas_even_q = 0x%08x\n", i, | |
477 | qEvenMeasOffset); | |
478 | ||
479 | if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) { | |
480 | iGainMismatch = | |
481 | ((iEvenMeasOffset * 32) / | |
482 | iOddMeasOffset) & 0x3f; | |
483 | qGainMismatch = | |
484 | ((qOddMeasOffset * 32) / | |
485 | qEvenMeasOffset) & 0x3f; | |
486 | ||
487 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
488 | "Chn %d gain_mismatch_i = 0x%08x\n", i, | |
489 | iGainMismatch); | |
490 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
491 | "Chn %d gain_mismatch_q = 0x%08x\n", i, | |
492 | qGainMismatch); | |
493 | ||
494 | val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); | |
495 | val &= 0xfffff000; | |
496 | val |= (qGainMismatch) | (iGainMismatch << 6); | |
497 | REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); | |
498 | ||
499 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
500 | "ADC Gain Cal done for Chain %d\n", i); | |
501 | } | |
502 | } | |
503 | ||
504 | REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), | |
505 | REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) | | |
506 | AR_PHY_NEW_ADC_GAIN_CORR_ENABLE); | |
507 | } | |
508 | ||
509 | static void ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u8 numChains) | |
510 | { | |
511 | struct ath_hal_5416 *ahp = AH5416(ah); | |
512 | u32 iOddMeasOffset, iEvenMeasOffset, val, i; | |
513 | int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch; | |
514 | const struct hal_percal_data *calData = | |
515 | ahp->ah_cal_list_curr->calData; | |
516 | u32 numSamples = | |
517 | (1 << (calData->calCountMax + 5)) * calData->calNumSamples; | |
518 | ||
519 | for (i = 0; i < numChains; i++) { | |
520 | iOddMeasOffset = ahp->ah_totalAdcDcOffsetIOddPhase[i]; | |
521 | iEvenMeasOffset = ahp->ah_totalAdcDcOffsetIEvenPhase[i]; | |
522 | qOddMeasOffset = ahp->ah_totalAdcDcOffsetQOddPhase[i]; | |
523 | qEvenMeasOffset = ahp->ah_totalAdcDcOffsetQEvenPhase[i]; | |
524 | ||
525 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
526 | "Starting ADC DC Offset Cal for Chain %d\n", i); | |
527 | ||
528 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
529 | "Chn %d pwr_meas_odd_i = %d\n", i, | |
530 | iOddMeasOffset); | |
531 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
532 | "Chn %d pwr_meas_even_i = %d\n", i, | |
533 | iEvenMeasOffset); | |
534 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
535 | "Chn %d pwr_meas_odd_q = %d\n", i, | |
536 | qOddMeasOffset); | |
537 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
538 | "Chn %d pwr_meas_even_q = %d\n", i, | |
539 | qEvenMeasOffset); | |
540 | ||
541 | iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) / | |
542 | numSamples) & 0x1ff; | |
543 | qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) / | |
544 | numSamples) & 0x1ff; | |
545 | ||
546 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
547 | "Chn %d dc_offset_mismatch_i = 0x%08x\n", i, | |
548 | iDcMismatch); | |
549 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
550 | "Chn %d dc_offset_mismatch_q = 0x%08x\n", i, | |
551 | qDcMismatch); | |
552 | ||
553 | val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); | |
554 | val &= 0xc0000fff; | |
555 | val |= (qDcMismatch << 12) | (iDcMismatch << 21); | |
556 | REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); | |
557 | ||
558 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
559 | "ADC DC Offset Cal done for Chain %d\n", i); | |
560 | } | |
561 | ||
562 | REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), | |
563 | REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) | | |
564 | AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE); | |
565 | } | |
566 | ||
c9e27d94 LR |
567 | /* This is done for the currently configured channel */ |
568 | bool ath9k_hw_reset_calvalid(struct ath_hal *ah) | |
f1dc5600 S |
569 | { |
570 | struct ath_hal_5416 *ahp = AH5416(ah); | |
c9e27d94 | 571 | struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; |
f1dc5600 S |
572 | struct hal_cal_list *currCal = ahp->ah_cal_list_curr; |
573 | ||
c9e27d94 LR |
574 | if (!ah->ah_curchan) |
575 | return true; | |
f1dc5600 S |
576 | |
577 | if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah)) | |
c9e27d94 | 578 | return true; |
f1dc5600 S |
579 | |
580 | if (currCal == NULL) | |
c9e27d94 | 581 | return true; |
f1dc5600 S |
582 | |
583 | if (currCal->calState != CAL_DONE) { | |
584 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
04bd4638 S |
585 | "Calibration state incorrect, %d\n", |
586 | currCal->calState); | |
c9e27d94 | 587 | return true; |
f1dc5600 S |
588 | } |
589 | ||
c9e27d94 LR |
590 | if (!ath9k_hw_iscal_supported(ah, currCal->calData->calType)) |
591 | return true; | |
f1dc5600 S |
592 | |
593 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
c9e27d94 LR |
594 | "Resetting Cal %d state for channel %u\n", |
595 | currCal->calData->calType, conf->channel->center_freq); | |
f1dc5600 | 596 | |
c9e27d94 | 597 | ah->ah_curchan->CalValid &= ~currCal->calData->calType; |
f1dc5600 S |
598 | currCal->calState = CAL_WAITING; |
599 | ||
c9e27d94 | 600 | return false; |
f1dc5600 S |
601 | } |
602 | ||
603 | void ath9k_hw_start_nfcal(struct ath_hal *ah) | |
604 | { | |
605 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, | |
606 | AR_PHY_AGC_CONTROL_ENABLE_NF); | |
607 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, | |
608 | AR_PHY_AGC_CONTROL_NO_UPDATE_NF); | |
609 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); | |
610 | } | |
611 | ||
612 | void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan) | |
613 | { | |
614 | struct ath9k_nfcal_hist *h; | |
615 | int i, j; | |
616 | int32_t val; | |
617 | const u32 ar5416_cca_regs[6] = { | |
618 | AR_PHY_CCA, | |
619 | AR_PHY_CH1_CCA, | |
620 | AR_PHY_CH2_CCA, | |
621 | AR_PHY_EXT_CCA, | |
622 | AR_PHY_CH1_EXT_CCA, | |
623 | AR_PHY_CH2_EXT_CCA | |
624 | }; | |
625 | u8 chainmask; | |
626 | ||
5dad40c1 S |
627 | if (AR_SREV_9285(ah)) |
628 | chainmask = 0x9; | |
629 | else if (AR_SREV_9280(ah)) | |
f1dc5600 S |
630 | chainmask = 0x1B; |
631 | else | |
632 | chainmask = 0x3F; | |
633 | ||
f1dc5600 | 634 | h = ah->nfCalHist; |
f1dc5600 S |
635 | |
636 | for (i = 0; i < NUM_NF_READINGS; i++) { | |
637 | if (chainmask & (1 << i)) { | |
638 | val = REG_READ(ah, ar5416_cca_regs[i]); | |
639 | val &= 0xFFFFFE00; | |
640 | val |= (((u32) (h[i].privNF) << 1) & 0x1ff); | |
641 | REG_WRITE(ah, ar5416_cca_regs[i], val); | |
642 | } | |
643 | } | |
644 | ||
645 | REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, | |
646 | AR_PHY_AGC_CONTROL_ENABLE_NF); | |
647 | REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, | |
648 | AR_PHY_AGC_CONTROL_NO_UPDATE_NF); | |
649 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); | |
650 | ||
651 | for (j = 0; j < 1000; j++) { | |
652 | if ((REG_READ(ah, AR_PHY_AGC_CONTROL) & | |
653 | AR_PHY_AGC_CONTROL_NF) == 0) | |
654 | break; | |
655 | udelay(10); | |
656 | } | |
657 | ||
658 | for (i = 0; i < NUM_NF_READINGS; i++) { | |
659 | if (chainmask & (1 << i)) { | |
660 | val = REG_READ(ah, ar5416_cca_regs[i]); | |
661 | val &= 0xFFFFFE00; | |
662 | val |= (((u32) (-50) << 1) & 0x1ff); | |
663 | REG_WRITE(ah, ar5416_cca_regs[i], val); | |
664 | } | |
665 | } | |
666 | } | |
667 | ||
668 | int16_t ath9k_hw_getnf(struct ath_hal *ah, | |
669 | struct ath9k_channel *chan) | |
670 | { | |
671 | int16_t nf, nfThresh; | |
672 | int16_t nfarray[NUM_NF_READINGS] = { 0 }; | |
673 | struct ath9k_nfcal_hist *h; | |
76061abb | 674 | struct ieee80211_channel *c = chan->chan; |
f1dc5600 S |
675 | |
676 | chan->channelFlags &= (~CHANNEL_CW_INT); | |
677 | if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { | |
678 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
04bd4638 | 679 | "NF did not complete in calibration window\n"); |
f1dc5600 S |
680 | nf = 0; |
681 | chan->rawNoiseFloor = nf; | |
682 | return chan->rawNoiseFloor; | |
683 | } else { | |
684 | ath9k_hw_do_getnf(ah, nfarray); | |
685 | nf = nfarray[0]; | |
76061abb | 686 | if (getNoiseFloorThresh(ah, c->band, &nfThresh) |
f1dc5600 S |
687 | && nf > nfThresh) { |
688 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
04bd4638 S |
689 | "noise floor failed detected; " |
690 | "detected %d, threshold %d\n", | |
f1dc5600 S |
691 | nf, nfThresh); |
692 | chan->channelFlags |= CHANNEL_CW_INT; | |
693 | } | |
694 | } | |
695 | ||
f1dc5600 | 696 | h = ah->nfCalHist; |
f1dc5600 S |
697 | |
698 | ath9k_hw_update_nfcal_hist_buffer(h, nfarray); | |
699 | chan->rawNoiseFloor = h[0].privNF; | |
700 | ||
701 | return chan->rawNoiseFloor; | |
702 | } | |
703 | ||
704 | void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah) | |
705 | { | |
706 | int i, j; | |
707 | ||
708 | for (i = 0; i < NUM_NF_READINGS; i++) { | |
709 | ah->nfCalHist[i].currIndex = 0; | |
710 | ah->nfCalHist[i].privNF = AR_PHY_CCA_MAX_GOOD_VALUE; | |
711 | ah->nfCalHist[i].invalidNFcount = | |
712 | AR_PHY_CCA_FILTERWINDOW_LENGTH; | |
713 | for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) { | |
714 | ah->nfCalHist[i].nfCalBuffer[j] = | |
715 | AR_PHY_CCA_MAX_GOOD_VALUE; | |
716 | } | |
717 | } | |
718 | return; | |
719 | } | |
720 | ||
721 | s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan) | |
722 | { | |
f1dc5600 S |
723 | s16 nf; |
724 | ||
5f8e077c | 725 | if (chan->rawNoiseFloor == 0) |
e56db718 LR |
726 | nf = -96; |
727 | else | |
5f8e077c | 728 | nf = chan->rawNoiseFloor; |
f1dc5600 S |
729 | |
730 | if (!ath9k_hw_nf_in_range(ah, nf)) | |
731 | nf = ATH_DEFAULT_NOISE_FLOOR; | |
732 | ||
733 | return nf; | |
734 | } | |
735 | ||
736 | bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan, | |
737 | u8 rxchainmask, bool longcal, | |
738 | bool *isCalDone) | |
739 | { | |
740 | struct ath_hal_5416 *ahp = AH5416(ah); | |
741 | struct hal_cal_list *currCal = ahp->ah_cal_list_curr; | |
f1dc5600 S |
742 | |
743 | *isCalDone = true; | |
744 | ||
f1dc5600 S |
745 | if (currCal && |
746 | (currCal->calState == CAL_RUNNING || | |
747 | currCal->calState == CAL_WAITING)) { | |
5f8e077c | 748 | ath9k_hw_per_calibration(ah, chan, rxchainmask, currCal, |
f1dc5600 S |
749 | isCalDone); |
750 | if (*isCalDone) { | |
751 | ahp->ah_cal_list_curr = currCal = currCal->calNext; | |
752 | ||
753 | if (currCal->calState == CAL_WAITING) { | |
754 | *isCalDone = false; | |
755 | ath9k_hw_reset_calibration(ah, currCal); | |
756 | } | |
757 | } | |
758 | } | |
759 | ||
760 | if (longcal) { | |
5f8e077c | 761 | ath9k_hw_getnf(ah, chan); |
f1dc5600 S |
762 | ath9k_hw_loadnf(ah, ah->ah_curchan); |
763 | ath9k_hw_start_nfcal(ah); | |
764 | ||
5f8e077c LR |
765 | if (chan->channelFlags & CHANNEL_CW_INT) |
766 | chan->channelFlags &= ~CHANNEL_CW_INT; | |
f1dc5600 S |
767 | } |
768 | ||
769 | return true; | |
770 | } | |
771 | ||
e7594072 SB |
772 | static inline void ath9k_hw_9285_pa_cal(struct ath_hal *ah) |
773 | { | |
774 | ||
775 | u32 regVal; | |
776 | int i, offset, offs_6_1, offs_0; | |
777 | u32 ccomp_org, reg_field; | |
778 | u32 regList[][2] = { | |
779 | { 0x786c, 0 }, | |
780 | { 0x7854, 0 }, | |
781 | { 0x7820, 0 }, | |
782 | { 0x7824, 0 }, | |
783 | { 0x7868, 0 }, | |
784 | { 0x783c, 0 }, | |
785 | { 0x7838, 0 }, | |
786 | }; | |
787 | ||
788 | if (AR_SREV_9285_11(ah)) { | |
789 | REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14)); | |
790 | udelay(10); | |
791 | } | |
792 | ||
793 | for (i = 0; i < ARRAY_SIZE(regList); i++) | |
794 | regList[i][1] = REG_READ(ah, regList[i][0]); | |
795 | ||
796 | regVal = REG_READ(ah, 0x7834); | |
797 | regVal &= (~(0x1)); | |
798 | REG_WRITE(ah, 0x7834, regVal); | |
799 | regVal = REG_READ(ah, 0x9808); | |
800 | regVal |= (0x1 << 27); | |
801 | REG_WRITE(ah, 0x9808, regVal); | |
802 | ||
803 | REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1); | |
804 | REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1); | |
805 | REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1); | |
806 | REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1); | |
807 | REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0); | |
808 | REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0); | |
809 | REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0); | |
810 | REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 1); | |
811 | REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0); | |
812 | REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0); | |
813 | REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7); | |
814 | REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0); | |
815 | ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP); | |
816 | REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 7); | |
817 | ||
818 | REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0); | |
819 | udelay(30); | |
820 | REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0); | |
821 | REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0); | |
822 | ||
823 | for (i = 6; i > 0; i--) { | |
824 | regVal = REG_READ(ah, 0x7834); | |
825 | regVal |= (1 << (19 + i)); | |
826 | REG_WRITE(ah, 0x7834, regVal); | |
827 | udelay(1); | |
828 | regVal = REG_READ(ah, 0x7834); | |
829 | regVal &= (~(0x1 << (19 + i))); | |
830 | reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9); | |
831 | regVal |= (reg_field << (19 + i)); | |
832 | REG_WRITE(ah, 0x7834, regVal); | |
833 | } | |
834 | ||
835 | REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1); | |
836 | udelay(1); | |
837 | reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9); | |
838 | REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field); | |
839 | offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS); | |
840 | offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP); | |
841 | ||
842 | offset = (offs_6_1<<1) | offs_0; | |
843 | offset = offset - 0; | |
844 | offs_6_1 = offset>>1; | |
845 | offs_0 = offset & 1; | |
846 | ||
847 | REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1); | |
848 | REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0); | |
849 | ||
850 | regVal = REG_READ(ah, 0x7834); | |
851 | regVal |= 0x1; | |
852 | REG_WRITE(ah, 0x7834, regVal); | |
853 | regVal = REG_READ(ah, 0x9808); | |
854 | regVal &= (~(0x1 << 27)); | |
855 | REG_WRITE(ah, 0x9808, regVal); | |
856 | ||
857 | for (i = 0; i < ARRAY_SIZE(regList); i++) | |
858 | REG_WRITE(ah, regList[i][0], regList[i][1]); | |
859 | ||
860 | REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org); | |
861 | ||
862 | if (AR_SREV_9285_11(ah)) | |
863 | REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT); | |
864 | ||
865 | } | |
866 | ||
f1dc5600 S |
867 | bool ath9k_hw_init_cal(struct ath_hal *ah, |
868 | struct ath9k_channel *chan) | |
869 | { | |
870 | struct ath_hal_5416 *ahp = AH5416(ah); | |
f1dc5600 S |
871 | |
872 | REG_WRITE(ah, AR_PHY_AGC_CONTROL, | |
873 | REG_READ(ah, AR_PHY_AGC_CONTROL) | | |
874 | AR_PHY_AGC_CONTROL_CAL); | |
875 | ||
876 | if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) { | |
877 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
04bd4638 S |
878 | "offset calibration failed to complete in 1ms; " |
879 | "noisy environment?\n"); | |
f1dc5600 S |
880 | return false; |
881 | } | |
882 | ||
e7594072 SB |
883 | if (AR_SREV_9285(ah) && AR_SREV_9285_11_OR_LATER(ah)) |
884 | ath9k_hw_9285_pa_cal(ah); | |
885 | ||
f1dc5600 S |
886 | REG_WRITE(ah, AR_PHY_AGC_CONTROL, |
887 | REG_READ(ah, AR_PHY_AGC_CONTROL) | | |
888 | AR_PHY_AGC_CONTROL_NF); | |
889 | ||
890 | ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr = NULL; | |
891 | ||
892 | if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) { | |
c9e27d94 | 893 | if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) { |
f1dc5600 S |
894 | INIT_CAL(&ahp->ah_adcGainCalData); |
895 | INSERT_CAL(ahp, &ahp->ah_adcGainCalData); | |
896 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
04bd4638 | 897 | "enabling ADC Gain Calibration.\n"); |
f1dc5600 | 898 | } |
c9e27d94 | 899 | if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) { |
f1dc5600 S |
900 | INIT_CAL(&ahp->ah_adcDcCalData); |
901 | INSERT_CAL(ahp, &ahp->ah_adcDcCalData); | |
902 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
04bd4638 | 903 | "enabling ADC DC Calibration.\n"); |
f1dc5600 | 904 | } |
c9e27d94 | 905 | if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) { |
f1dc5600 S |
906 | INIT_CAL(&ahp->ah_iqCalData); |
907 | INSERT_CAL(ahp, &ahp->ah_iqCalData); | |
908 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
04bd4638 | 909 | "enabling IQ Calibration.\n"); |
f1dc5600 S |
910 | } |
911 | ||
912 | ahp->ah_cal_list_curr = ahp->ah_cal_list; | |
913 | ||
914 | if (ahp->ah_cal_list_curr) | |
915 | ath9k_hw_reset_calibration(ah, ahp->ah_cal_list_curr); | |
916 | } | |
917 | ||
5f8e077c | 918 | chan->CalValid = 0; |
f1dc5600 S |
919 | |
920 | return true; | |
921 | } | |
922 | ||
923 | const struct hal_percal_data iq_cal_multi_sample = { | |
924 | IQ_MISMATCH_CAL, | |
925 | MAX_CAL_SAMPLES, | |
926 | PER_MIN_LOG_COUNT, | |
927 | ath9k_hw_iqcal_collect, | |
928 | ath9k_hw_iqcalibrate | |
929 | }; | |
930 | const struct hal_percal_data iq_cal_single_sample = { | |
931 | IQ_MISMATCH_CAL, | |
932 | MIN_CAL_SAMPLES, | |
933 | PER_MAX_LOG_COUNT, | |
934 | ath9k_hw_iqcal_collect, | |
935 | ath9k_hw_iqcalibrate | |
936 | }; | |
937 | const struct hal_percal_data adc_gain_cal_multi_sample = { | |
938 | ADC_GAIN_CAL, | |
939 | MAX_CAL_SAMPLES, | |
940 | PER_MIN_LOG_COUNT, | |
941 | ath9k_hw_adc_gaincal_collect, | |
942 | ath9k_hw_adc_gaincal_calibrate | |
943 | }; | |
944 | const struct hal_percal_data adc_gain_cal_single_sample = { | |
945 | ADC_GAIN_CAL, | |
946 | MIN_CAL_SAMPLES, | |
947 | PER_MAX_LOG_COUNT, | |
948 | ath9k_hw_adc_gaincal_collect, | |
949 | ath9k_hw_adc_gaincal_calibrate | |
950 | }; | |
951 | const struct hal_percal_data adc_dc_cal_multi_sample = { | |
952 | ADC_DC_CAL, | |
953 | MAX_CAL_SAMPLES, | |
954 | PER_MIN_LOG_COUNT, | |
955 | ath9k_hw_adc_dccal_collect, | |
956 | ath9k_hw_adc_dccal_calibrate | |
957 | }; | |
958 | const struct hal_percal_data adc_dc_cal_single_sample = { | |
959 | ADC_DC_CAL, | |
960 | MIN_CAL_SAMPLES, | |
961 | PER_MAX_LOG_COUNT, | |
962 | ath9k_hw_adc_dccal_collect, | |
963 | ath9k_hw_adc_dccal_calibrate | |
964 | }; | |
965 | const struct hal_percal_data adc_init_dc_cal = { | |
966 | ADC_DC_INIT_CAL, | |
967 | MIN_CAL_SAMPLES, | |
968 | INIT_LOG_COUNT, | |
969 | ath9k_hw_adc_dccal_collect, | |
970 | ath9k_hw_adc_dccal_calibrate | |
971 | }; |